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JOURNAL OF COMPUTING, VOLUME 4, ISSUE 8, AUGUST 2012, ISSN (Online) 2151-9617 https://sites.google.

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RNS OVERFLOW DETECTION SCHEME FOR THE MODULI SET {M-1, M}
M.I. DAABO1,2, K. A. GBOLAGADE1
1

Department of Computer Science, Faculty of Mathematical Sciences, University for 1 Development Studies, Navrongo, Ghana.
2

Department of Mathematical Applications, Wisconsin International University College, Accra, Ghana.

--------------------------------------------------------------------------------------------------------------------Abstract- This paper presents a new Residue Number System (RNS) overflow detection for the moduli set-{M-1, M}, where M is the system dynamic range. The algorithms are based on the computation of residues and then comparing their values. In detecting overflow with this scheme, we proposed that If the moduli set {M-1, M} is a transformation of the moduli set {m1, m2, m3,…, mn }, then for a given decimal number, X < M, there is no overflow when x1 computed is less than or equal to x0, where x0 = M-1 and x1= M. Based on this, a multiplicative and an additive overflow detection processor requiring relatively lesser hardware with faster operations when compared with the state of the art designs, is proposed. Theoretical analysis indicates that the proposed scheme outperforms the best known similar state of the art designs in terms of delay with similar area cost. Keywords: Residue Number System, Overflow detection, Dynamic Range. 1. Introduction Residue Number System (RNS) is a nonweighted system that supports carry free, parallel, high speed, low power and secure computing [7]. Due to these RNS features, RNS has been greatly applied in addition and multiplication dominated digital signal processing operations. Despite the above interesting inherent RNS features, RNS has not found a wide spread usage in general purpose computing due to the following RNS disadvantages: sign detection, magnitude comparison, overflow detection, moduli selection and data conversion. This paper focuses on overflow detection problem. Overflow in computing is a condition that occurs when a calculation produces a result that is greater in magnitude than that which a given register or storage location can store or represent. This condition may occur as a result of software/hardware failures [8]. In RNS, overflow is a condition where a calculated number falls outside the valid dynamic range of a particular RNS [1]. A considerable amount of work has been done on overflow detection in RNS. The existing works on overflow detection are based on either the Chinese Remainder Theorem (CRT) [3] and the Mixed Radix Conversions (MRC). These methods are however difficult and time consuming because of the involvement of the large modulo M calculations [1], [4]. The most recent work on overflow detection is based on processors built separately to detect multiplicative and additive overflow [6], [5]. But invariably, most of the schemes adopted are still dependent on the CRT and the MRC and thus processors built on these principles are hardware intensive and slow in nature. Siewobr et al [2] proposed an overflow detection algorithm for the moduli set {M, M+1}. In their proposal, the residue number

© 2012 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 8, AUGUST 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

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( ) is obtained from {M, M+1} and the validity of no overflow occurs when . However building adders with the M+1 modulus is very expensive. Siewobr et al [1] again developed an additive overflow detection algorithm that reduces the large modulo M to by scaling M and integers X and Y with = 2n. This approach is hardware intensive with increase in delay since the process involves scaling. In this paper, we present a new overflow detection algorithm for the moduli set {M-1, M}, where M is the system dynamic range. The algorithms are based on the computation .These residues are then of residues compared in order to determine whether overflow occurs or not. Our proposal eliminates the time consuming reverse conversion approach and uses less hardware in a similar way as was done in [3]. 2. The Proposed Scheme A simple RNS overflow detection algorithm has been proposed. The algorithm makes use of the redundant moduli set {M-1,
n

Proof

x1 = x0 =

M -1 M

But Implies

M -1

M

x1 ≤ x0

proposition 1. If the moduli set {M-3, M} is used in place of {m1 , m2, m3,…, mn }, then for any number X < M, the following hold true: (2.2) Proof x3 = x3 ≤ x0
M -3

x0 = But Implies
M -3

M

M

x3 ≤ x 0

proposition 2. If the moduli set {M-5, M} is used in place of {m1 , m2, m3,…, mn }, then for any number X < M, the following hold true: (2.3) Proof x5 ≤ x0 x5 = x0 = But Implies

M} where M = ∏ i=1 mi, is the dynamic range. In order to detect overflow using the moduli set {M-1, M}, we transform the moduli set {m1, m2,…, mn } into {M-1, M} for the residue number (x1, x2,…,xn )RNS . We make use of the following property in the proof of subsequent theorem. That is given a decimal number X and the moduli set {m1, m2,…, mn } , with M = ∏ni=1 mi, then the following holds true:
M -1

M -5 M M -5

M

x5 ≤ x 0

M

for X ≤ M-1 and X < M.

By mathematical induction if {M-k, M} is used in place of {m1 , m2, m3,…, mn }, then for any number X < M, the theorem holds for: (2.4) xk ≤ x0

Theorem. If the moduli set {M-1, M} is used in place of {m1 , m2, m3,…, mn }, then for any number X < M, the following hold true: (2.1) x1 ≤ x0

© 2012 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 8, AUGUST 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

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Proof

xk = x0 =

M -k M

A
1
M

B
2 4

X
5

Y

But Implies for k=

M -k

Multiplexer 10

Multiplexer 11

xk ≤ x 0
3 6

3. The Overflow Detection Algorithm

1. Given the RNS number ( x1, x2, x3,…,
xn) with respect to the moduli set { m1, m2, m3,…, mn } 2. The moduli set { m1, m2, m3,…, mn } is transformed into {M-k, M}, where
n

Delay Circuit 12
9

Logic gate 13

xk≤ x0
False
7 8

True

M = ∏ i=1 mi is the dynamic range and { 0 ,M-1 }, the legitimate range 3. The RNS number (xk, x0) is obtained base on the moduli set {M-k, M} 4. The validity is carried out based on the condition that xk ≤ x0 4.The Overflow Processor

Valid Fig. 1. The new proposed additive and multiplicative overflow detection processor
X+Y/X *Y

Invalid

We demonstrate how the scheme works with some numerical illustrative examples in the proceeding section. Numerical Examples How the processor detects overflow in the product of two numbers Given that we want to compute the product of two decimal numbers 8 and 9 in the RNS with moduli set {3, 4, 5}. M-1 = 59 and M = 60 We enter the numbers as: 8 = (8, 8) RNS 9 = (9, 9) RNS 8→ (8, 8) 9)

Multiplexer 10 receives RNS inputs A and B through signal lines 1 and 2 and computes their modular sum or product. The result is then sent to the delay circuit 12 through signal line 3. The inputs X and Y are transmitted to multiplexer 11 via signal lines 4 and 5 respectively. Multiplexer 11 computes the modular sum/product of X and Y and transmits the result to logic gate 13 through signal line 6. When xk ≤ x0, the result is valid and becomes invalid if xk ≥ x0. Logic gate 13 checks the logic xk ≤ x0 condition and decides whether to generate valid or invalid signals from signal lines 7 and 8 respectively.

*9 → (9,

72 → (72 mod 59, 72 mod 60) = (13, 12)

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Certainly, the condition x1 ≤ x0 does not hold, instead x0 ≤ x1 is true indicating that overflow has occurred. How the processor confirms no overflow in the product of two numbers Given that we want to compute the product of two decimal numbers 8 and 7 in the RNS with moduli set {3, 4, 5}. M-1 = 59 and M = 60 We enter the numbers as: 8 = (8, 8) RNS 9 = (7, 7) RNS 8→ (8, 8) 7)

Certainly, the condition x1 ≤ x0 does not hold, instead x0 ≤ x1 is true indicating that overflow has occurred. How the processor confirms no overflow in the sum of two numbers Given that we want to compute the sum of two decimal numbers 5 and 54 in the RNS with moduli set {3, 4, 5}. M-1 = 59 and M = 60 We enter the numbers as: 5 = (5, 5) RNS 54 = (54, 54) RNS 5→ (5, 5) 54)

*7 → (7,

+54 → (54,

56 → ( 56 mod 59, 56 mod 60) = (56, 56) Since, the condition x1 ≤ x0 holds true for the results, an overflow does not occur.

56 → ( 59 mod 59, 59 mod 60) = (0, 59) Since, the condition x1 ≤ x0 holds true for the results, an overflow does not occur.

How the processor detects overflow in the sum of two numbers Given that we want to compute the sum of two decimal numbers 6 and 54 in the RNS with moduli set {3, 4, 5}. M-1 = 59 and M = 60 We enter the numbers as: 6 = (6, 6) RNS 54 = (54, 54) RNS 6→ (6, 6) 54)

5. Performance Analysis We compare the proposed overflow detection processor with the best known state of the art processors in order to evaluate its performance. In Table1, we compare the processors in terms of area cost and delay.

+54 → (54,

60 → (60 mod 59, 60 mod 60) = (1, 0)

© 2012 Journal of Computing Press, NY, USA, ISSN 2151-9617

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 8, AUGUST 2012, ISSN (Online) 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

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X

Y
1

A
2

B
4

X
5

Y

Multiplexer 10
DELAY BASE EXT. CIRCUIT DELAY BASE EXT. CIRCUIT

Multiplexer 20

3

6

Delay Circuit

Logic gate 40 X1=x2 False
7 8

A ADDER

B

30
9

True

X+Y/X .Y
DELAY RESIDUE TO MIX BASED CONVERTER

Invalid Valid

Fig. 3. Multiplicative and additive overflow detection processor (PII)[2] The new proposed processor in Fig.1 is similar to that in Fig.3 (PII), in terms of design structure but different in operation by logic. It is generally easier to build adders with M-1 modulus as proposed in this paper than the M+1 modulus in (PI). Also, arithmetic operations involving mod (M-1) are much faster than the ones involving mod (M+1). Therefore the new design has better delay during computations than processors PI and PII. Thus the proposed design outperforms the best known state of the art designs.

X+Y

VALID

INVALID

Fig. 2. Multiplicative overflow detection processor (PI)[6] The processor in Fig.2, (PI) requires a considerable amount of hardware. This involves a lot of resources and increases the area cost. Also PI requires a converter which is very expensive and time consuming.

© 2012 Journal of Computing Press, NY, USA, ISSN 2151-9617

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TABLE 1 Comparison table Components/ Converters Mixed base converters Adder Multiplier Multiplexer Most significant digit detector Logic circuits Delay circuits PI 5 1 1 0 1 PII 0 0 0 2 0 Our proposal 0 0 0 2 0

[2] H. Siewobr and K.A. Gbolagade, “An Efficient RNS Overflow Detection Algorithm,”Far East Journal of Electronics and Communications. Vol. 6, No. 2, pp 83-91, 2011 [3] K. A. Gbolagade and S.D. Cotofana, “Residue-to-Decimal Converters for Moduli Set with Common Factors”,52nd IEEE International Midwest Symposium on circuits and Systems,(MWSCAS, 2009), PP.624-627, Cancun, Mexico, August, 2009.

2 7

1 1

1 1

6. Conclusion In this paper, we proposed an integrated overflow detection processor based on a new overflow detection algorithm using the {M-1, M} moduli set. The algorithms are based on; first the transformation of the moduli set {m1, m2,…,mn} into {M-1, M} and secondly the computation of the residues x1 and x0. To detect overflow with the proposed scheme, the computed residue values are compared such that for a given decimal number X < M, the expression x1<x0 is true. By mathematical induction, we proved that xk < x0 is always true for the set {1, 3, …, }. Theoretical analysis indicates that our proposal outperforms the best known similar state of the art design proposed in [1], [2],[6] in terms of delay with similar area cost. 7. Reference [1] H. Siewobr and K.A. Gbolagade, “An Overflow Detection in Residue Number Systems Addition before Forward Conversion,” International Journal of Computational Intelligence and Information Security. Vol. 2, No. 9, pp 48-54, 2011

[4] K.A.Gbolagade and S.D. Cotofana,”MRC Technique for RNS to Decimal Conversion for the moduli set {2n+2,2n+1,2n}”,16th Annual Workshop on Circuits, Systems, and Signal Processing, pp.318321,Veldhoven, The Netherlands, November 2008. [5] Mehrin Rouhifar, Mehdi Hosseinzadeh and Mohammad Teshnehlab,”A new approach to Overflow detection in moduli set (2n, 2n-1, 2n-1-1)”, International journal of Computational intelligence and Information Security, Vol.2, No.3, pp.3543, march 2011.

[6] Theodore L. Houk, Seattle, “Residue Addition Overflow Detection Processor Boeing Company, Seattle, Wash”. Application No.414276, Sep. 29, 1989. [7] T.Stouraitis, and V. Paliouras, “Considering the Alternative in low power Design”, IEEE Circuit Devices Magazine. Vol. 17, No.4, pp. 22-29, July, 2001. Wikipedia, The free Encyclopedia, http/en.wikipedia.org/wiki/Arithmetic_ove rflow retrieved on April 16, 2012, 3:30 pm

[8]

© 2012 Journal of Computing Press, NY, USA, ISSN 2151-9617