CAD for VLSI Design - II

Lecture 2 V. Kamakoti and Shankar Balachandran

Overview of this Lecture • • • • Modeling Delay and power Introduction to MOSFET Introduction to Layout Techniques Transistor level simulation .

– supply capacity and battery lifetime (determined by average power) – sizing of supply lines (determined by peak power) – packaging and cooling requirements Propagation delay is mostly determined by the speed at which a given amount of energy can be stored on the gate capacitors – the faster the energy transfer (or higher power dissipation) the faster the gate. and consumes little energy. and how much heat is dissipated. Energy consumed by the gate per switching event is simply the power-delay product (PDP). • • • • . E·D product is a combined metric – speed and energy. Ideal Gate: it is fast.Power and Energy Dissipation • Power consumption determines how much energy is consumed per operation.

Introduction to MOSFETs A MOSFET is a Voltage Controlled Switch .

MOSFETs as Switches for Gates .

MODEL NENH NMOS + Level= … … +…… .MOSFETs in SPICE .MODEL PENH PMOS + Level= … … +…… .

CMOS Inverter .

CMOS Logic Gate .

NMOSFETs in Series/Parallel Network .

PMOSFETs in Series/Parallel Networks .

CMOS NAND Gate .

CMOS NOR Gate .

Magic Layout Layers .

Magic Layout: CMOS Inverter Vdd! in out GND! Transistor level Schematic CMOS Layout .

( @@technology : scmos ).mag magic tech scmos timestamp 1011216956 << pdiffusion >> rect 13 12 14 16 rect 18 12 19 16 … << ndcontact >> rect 14 -12 18 -8 rect 14 -20 18 -16 << pdcontact >> rect 14 12 18 16 rect 14 4 18 8 << polysilicon >> rect 10 9 13 11 rect 19 9 21 11 rect 10 -13 12 9 … << metal1 >> rect 7 12 14 16 rect 18 12 23 16 rect 14 -8 18 4 … << labels >> rlabel polysilicon 11 -2 11 -2 3 in … rlabel metal1 9 -19 9 -19 2 GND! << end >> cell. End • layout • DRC • Mask info. 94 Vdd! 32 52 CMF. L CWN. B 40 64 64 40. 9 inv. … L CPG.8 ). B 64 16 60 56.( @@techdesc :… MOSIS Scalable CMOS Technology …). B 56 88 64 -56. B 32 64 64 -56.mag ). . C 1. L CSP.2. 94 out 64 -8 CMF. … L CCA. B 44 8 62 40. B 64 88 64 40. … DS 1 50 2. B 24 48 64 40. … L CAA. DF. L CWP.cif ( @@source : inv. 94 in 44 -8 CPG. 94 GND! 36 -76 CMF. … L CSN.Magic Files cell. B 8 8 64 56. L CMF. ( @@version : 8.

7p ps=6.5um(amic5)from:T01X scale 1000 1 30 resistclasses 82100 102500 827000 827000 1 26000 26500 26500 90 90 50 node "GND!" 443 1166.6u + ad=2.2fF .7p pd=6.sim R Vdd 123 ext2spice –c0 –t! –t# -f spice3 cell * SPICE3 file created from inv.6u + ad=1.2 13 4 pdif 19 24 30 22 0 0 0 0 0 0 0 0 0 0 0 0 80 48 0 0 0 0 node "in" 546 522.1 tech scmos style AMI0.4fF C1 in GND 0.6u m1001 out in GND Gnd nfet w=0.spice C2 Vdd GND 1.P_22 d=A_30.P_22 n in GND out 2 3 14 -15 g=S_Gnd s=A_19.71p pd=7.2u C0 out GND 1.72 10 -15 p 0 0 0 0 0 0 0 0 0 0 84 88 0 0 0 0 0 0 0 0 0 0 node "Vdd!" 123 1166.8u l=0.P_24 d=A_19.ext version 5.9u l=0.5fF cell.4 13 11 pdif 0 0 30 22 0 0 0 0 0 0 0 0 0 0 0 0 64 40 0 0 0 0 fet nfet 14 -15 15 -14 6 10 "Gnd!" "in" 4 0 "GND!" 3 0 "out" 3 0 fet pfet 13 9 14 10 12 16 "Vdd!" "in" 4 0 "out" 6 0 "Vdd!" 6 0 ext2sim –t! –t# cell | units: 30 tech: scmos format: SU p in out Vdd 2 6 13 9 g=S_Vdd s=A_30.P_24 R GND 443 R out 566 R in 546 cell.technology: scmos m1000 Vdd in out Vdd pfet w=1.Extracted Netlists timestamp 1011216956 cell.2u as=1.6u as=2.ext .71p ps=7.4 14 -20 ndc 19 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 40 0 0 0 0 node "out" 566 1411.

ext .05pF .7p pd=6.LIB /home/cad/vlsi/models/spice3/cmos0.5fF Vdd GND 1.6u ad=1.param PVCC 3.6u out in GND Gnd nfet w=0. ta) .param PFO 4 m1 + m2 + C1 C2 Vdd in out Vdd pfet w=1.2u in GND 0.5um.02ns 400ns .3V .param PStd_Load 0.2u as=1.SPICE Simulation * SPICE3 file created from inv.2fF Cout out GND #PFO*PStd_Load# VVdd Vdd 0 #PVCC# VGND GND 0 0v Vin in GND PBIT 0v #PVCC# 10n 1n 10n 1n 20n & $01010101010101010101 .71p pd=7.9u l=0.punch trans V (in out) P(VVdd.8u l=0.71p ps=7.6u as=2.7p ps=6.technology: scmos .6u ad=2.model noprint .tran 0.end .

Questions and Answers Thank You .

Sign up to vote on this title
UsefulNot useful