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Gal Gilat, KaiSemi Ltd.
FPGA design suits a fast time-to-market product, while its chip cost is high. ASIC design or traditional FPGA to ASIC design involve high resources cost, while the chip cost is low. This paper presents a smooth automated conversion from FPGA to ASIC which is seamless to customer resources, while being dedicated to cost optimization. FPGA cost overheads are tackled by addressing three aspects: redundant die area, pricing of various fab process and production material. Mainly, there are two FPGA to ASIC solutions: traditional full RTL flow to standard-cell ASIC and to Structured ASIC. KaiSemi presents a third solution: an automated conversion flow to standard-cell ASIC. The paper analyzes the risks, complexity, lead-times and costs involved with FPGA and FPGA-to-ASIC conversion options.
FPGA is good for creating a design in a fast time-to-market, but once the design becomes a product, cost becomes a major issue. An FPGA chip consists of various cost overheads, such as die area, fab process and production. In the die area cost overhead aspect, FPGAs actually waste expensive silicon area and resources in terms of logic, routing, configurations and utilization, reaching around 80% area overhead. o FPGA logic is based on look-up tables where a dedicated function uses only part of the look-up table addresses, while in ASIC a dedicated function uses dedicated logic gates. FPGA routing has huge redundancies. The fact that placement of internal FPGA blocks is arranged in a vertical tiles structure makes the routing longer, heavier and much less efficient than ASIC routing. The long FPGA routings require huge amount of additional signal buffers, apart from the fact that the FPGA clock tree requires the additional buffers to overcome the fan-out and the distances. FPGA configuration includes a huge SRAM memory which connects and holds all the junction states, while each routing junction is built out of several transistors and is not needed in ASIC. FPGA utilization of used atoms such as look-up tables and flops cannot reach 100%. It usually barely reaches 75% while holding the required system frequency.
In the fab process cost overhead aspect, FPGAs actually waste expensive frequency performance capability. o An FPGA-based design achieves a much lower frequency compared to the frequency of the same design with an ASIC in the same fab process (the difference is up to x5 in favor of the ASIC).
Another way of looking at this issue is as follows: an FPGA-based design reaches a frequency that is the same as the achievable frequency in an identical ASICbased design in an earlier fab process node. The difference is around 2-3 process nodes in favor of the ASIC. Moreover, whenever you move to an earlier process node, cost is massively reduced both in the mask-set and in wafer production. The cost reduction in wafer production is not accidental. One could argue that for each earlier fab process node logic area is expanded by x2, which is true. Nevertheless, since the original logic area is shrunk by 80% before being expanded by x2 for each earlier node, the actual die size of the earlier process node is still lower even it is 2 process node steps behind. In addition, when the FPGA utilization in a design is less than 100% (which is usually the case), the converted die size can theoretically be lower even on a 3 earlier nodes behind. Another aspect is related to a scenario that a design is pad-limited rather than core-limited. In that case, dies size in an earlier process node will remain the same, which means that wafer production cost is reduced due to the fact that wafers of earlier process nodes are cheaper.
In the production cost overhead aspect, FPGAs waste test time and programming time. o FPGA packaging cost is higher when a design has to deal with FPGA power consumption, which is up to 3 times higher than an ASIC replacement chip (i.e. heat sink, material corners, etc.), and when a design uses much less I/O pads compared to the number of package pins. FPGA manufacturing test time per chip is high, and reaches about x10 compared to an ASIC replacement. When FPGAs are included in a board production, it is necessary to program each FPGA device or FPGA-attached PROM/flash device for each final product board a process which requires more money and time resources compared to ASIC.
These technical facts explain why an ASIC replacement product that is optimized with all the above parameters will always be cheaper compared to an FPGA product. However, a breakeven point of minimum ASIC quantity per design is required. The minimum ASIC quantity is required to overcome ASIC one-time expenses of design resources and fab NRE. Nevertheless, the minimum quantity becomes lower and lower, as the targeted ASIC replacement process is more mature, and due to the fact that fab prices are being reduced each year. Companies that convert FPGA to ASIC, in addition to reducing costs, gain a reduction in power consumption and radiated EMI, while achieving a natural intellectual property protection. Board cost is also reduced by eliminating the need for a flash/EPROM chip. These insights lay the ground for a provider that supplies a pin-to-pin second-source ASIC replacement, which optimizes the above parameters in order to achieve cost reduction. In this solution, the FPGA-to-ASIC conversion work is automated and seamless to the customer's resources. Such a solution includes a functional guarantee and eliminates the need to pay NRE upfront. That is the point where KaiSemi enters the picture.
1. Traditional FPGA-to-ASIC conversions
Traditional migration from FPGA into ASIC is risky, expensive, complex and demanding in terms of time, customer involvement and human resources. Traditional FPGA-to-ASIC conversions employ a full RTL flow. A new ASIC flow starts from the sources of the RTL with no relation to the FPGA product outcome. It involves back and forward iterations which require the customer's engineers to spend valuable time in order to finally reach an ASIC gate level netlist.
2. Gate Array ASIC
Another alternative to FPGA-to-ASIC conversion which was common in the past is a netlist conversion to an ASIC gate array solution. In this solution, an FPGA netlist is converted to an ASIC netlist gate-level of a specific fab process. As a result, both logic sizes and complexity are limited and the conversion is handled manually. Later on, when FPGAs became larger and more complex, gate-array technology lagged behind, where only small designs with no special interface hard macro can be supported. They remained at older fab process nodes where the cost difference between gate array and standard-cell became insignificant. As a result, this solution became mostly obsolete.
3. Structured ASIC
Structured ASIC technology offers a variety of predefined mask-set templates. The mask-set templates come in fixed sizes and in fixed fab process nodes, since they are prepared in advance. One of the mask-set templates is selected for the targeted design. Nevertheless, the routing layers of the mask-set, which are about one third of the total mask-set, must be programmed from scratch anyway. In relation to unit cost, due to the predefined templates, the silicon area in Structured ASIC is larger than in standard cell-based ASIC. On top of that, Structured ASIC is limited to specific process nodes which require more expensive wafer material compared to standard cell-based ASIC. As a result, the manufacturing cost of any given chip in Structured ASIC is higher compared to standard cell-based ASIC chips. In relation to NRE cost, it is supposedly lower in Structured ASIC - which explains the claim that Structured ASIC chips fit low quantities only. Nevertheless, even in these quantities, prices could be higher compared to KaiSemi's flow. This is due to the fact that the partial (1/3) NRE for an advanced process mask-set is usually higher than the full NRE of an optimized earlier process. Structured ASIC processes sometimes involve additional downsides, such as the need to perform a full ASIC flow cycle starting from the RTL sources.
KaiSemi's Solution: FPGA-to-ASIC Conversion
KaiSemi employs a unique automated FPGA-to-ASIC conversion process which provides customers with a seamless full turnkey ASIC solution, selling fully compatible replacement chips. KaiSemi's process uses an in-house tool which performs an automated conversion directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. Backed by a tier-one fab vendor, KaiSemi's automated conversion utilizes a database of multiple proven standard-cell fab process libraries and standard cores. The libraries enable the conversion of any type and size of FPGA from any FPGA vendor while providing deep cost optimization during the automated conversion. The resulting ASICs – which are pincompatible, timing-compatible, and functionally identical to the original FPGAs – consume less power and cost up to 70% less than their FPGA counterparts. KaiSemi manages the whole FPGA-to-ASIC process for the customer, from the purchase order through conversion, ASIC flow and manufacturing, all the way through to the shipment of the ASIC chips. This seamless conversion process – combined with the Zero NRE model – lets the customer order an ASIC chip as if it were an off-the-shelf second-source replacement chip with a lead time of 8 to 22 weeks.
Figure 1: KaiSemi's FPGA-to-ASIC conversion solution
Comparison Table: FPGA-to-ASIC Conversion Alternatives
KaiSemi's FPGA-to-ASIC Full Cycle Lead Time Support any FPGA size and type Required Customer Involvement Hard Macro Support Level NRE Cost Unit Cost for Prototype Quantities Unit Cost for Low Quantities Unit Cost for Medium to High Quantities Automated Netlist Conversion with Functional Guarantee Traditional ASIC Structured ASIC Gate-Array ASIC (N/A) FPGA as Product
Short Yes Seamless High Zero N/A Low
Long Yes High High High N/A High
Long Partial High Partial Low Low Low
N/A No High No Low Low Low
Low N/A N/A High Zero Low High
KaiSemi's Fab Process: Technical Considerations
Many traditional ASIC flows, where RTL is handled manually, define a specific process library in advance. KaiSemi's process minimizes overall costs not just by optimizing silicon area, but also through the selection of the most optimized fab process library after checking the targeted design conversion under several process libraries within the automated tool workflow. 1. Wafer Manufacturing FPGAs are usually pad-limited rather than core-limited. In other vendors' case, shrinking them to the same process at 40nm for example, while die size is actually set by the amount of pads, will not allow smaller chips compared to KaiSemi's optimized functionally-identical die size in 90nm. Knowing that wafer cost in 40nm (FPGA) is ~33% higher than in 90nm (in this case, KaiSemi's ASIC), any given die size will be cheaper in KaiSemi's process.
2. Silicon Area In pad-limited designs, KaiSemi not only optimizes the cost, but can also achieve some reduction in the silicon area itself through the use of a smaller amount of pads compared to the FPGA. In core-limited designs, KaiSemi achieves an even more significant silicon area reduction, since the converted chip does not suffer from pad limitations. This fact maximizes our ability to minimize silicon area and therefore optimize overall costs. 3. Mask Manufacturing KaiSemi saves masks manufacturing costs. This is done by carefully targeting to the cheaper standard fab process technology node that is optimized to the requirements and constraints of the FPGA-to-ASIC conversion project.
KaiSemi's FPGA to ASIC Conversion Compared to Traditional ASIC in RTL Flow
KaiSemi's conversion process differs in relation to traditional ASIC flow processes in various aspects:
At the heart of KaiSemi's FPGA-to-ASIC solution lays the in-house tool which automates the operation of converting directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. This "push of a button" operation is the critical difference between KaiSemi's solution and the alternatives, and the source of all the other benefits of this solution.
2. Seamless: No Human Intervention
Traditional FPGA-to-ASIC conversions do not rely on netlist conversion apart from manual conversions of tiny netlists. They do rely on full RTL flow conversion that requires customer intervention and involves functional touch. These limitations do not allow them to provide any functional guarantee, which would oblige them to take high risks. KaiSemi's automated conversion technology performs netlist conversion to ASIC standard-cell solution, rather than a gate-array, and consists of a sophisticated tool which handles conversions of large amount of gate level logic with no possibility of human errors.
3. No RTL & Functional Touch
Since the execution of the conversion requires no manual touch in general and no RTL touch in particular, a minimum level of potential human errors is ensured. As for the customer, his need to allocate engineers and resources for the conversion is minimized. On this basis, KaiSemi can afford itself to offer a functional guarantee – ensuring that the ASIC chips are functionally identical to the original FPGA part, and taking solely the risk of respin.
4. Fast Cycle
Compared to a traditional manual RTL flow, KaiSemi shortens the total time to convert from a working FPGA into ASIC tapeout by around 50%, since the conversion itself takes around 1 day. For example, 130nm process chips typically reach tapeout within 8 weeks. Maximum lead time typically does not exceed 22 weeks. The automated process usually saves at least three months in the conversion process.
5. Pre-Installed Multiple Fab Process Libraries
Backed by a tier-one fab vendor, KaiSemi's automated conversion utilizes a database of five proven standard-cell fab process libraries, which are installed in advance. The wide range of libraries enables the conversion of any type and size of FPGA from any FPGA vendor. KaiSemi's conversion ecosystem includes a business relationship with a tier-one fab vendor and the ability to support other fabs such as TowerJazz, NEC, UMC and SMIC.
Conclusion: How Does KaiSemi's Business Model Work?
Traditional FPGA-to-ASIC conversion vendors usually charge for the one time design cost known also as NRE (Non Recurrent Engineering). KaiSemi's "Zero-NRE" model means that the customer doesn't pay in advance for the NRE. KaiSemi's ability to offer a Zero-NRE model is associated with the functional guarantee that the company gives while the payment is made within the unit price after prototypes are approved. As a result, the ASIC replacement unit cost of the first year orders is about 40%-50% cheaper than the FPGA unit cost, and the ASIC replacement unit cost of the second year orders is about 60%-70% cheaper than the FPGA unit cost.
Seamless Full Turnkey
Instead of paying for a traditional ASIC process, customers purchase from KaiSemi fully compatible second source FPGA replacement chips as if they were off-the-shelf products. This is enabled by the fact that KaiSemi combines the automated FPGA-to-ASIC conversion with a backend ASIC flow and foundry manufacturing, which results in providing final replacement chips. KaiSemi's full turnkey solution covers the whole process, from the purchase order up to the shipment. It includes backend flow such as DFT insertions, layout and tapeout handoff, in addition to wafer manufacturing at the fab, packaging and testing. ________
Gal Gilat is CEO of KaiSemi. Mr. Gilat has led and managed dozens of chip development projects from scratch, and gained significant experience in architecture design, FPGA and board design, ASIC tape-out and production.
Contact: Gal Gilat, CEO, KaiSemi Ltd., +972-54-6675544, +972-9-8920409, firstname.lastname@example.org. Website: www.kaisemi.com
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