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CHAPTER-1 INTRODUCTION

1.1 MOTIVATION

In the past few decades ago, the electronics industry has been experiencing an unprecedented spurt in growth, thanks to the use of integrated circuits in computing, telecommunications and consumer electronics. We have come a long way from the single transistor era in 1958 to the present day ULSI (Ultra Large Scale Integration) systems with more than 50 million transistors in a single chip.

The ever-growing number of transistors integrated on a chip and the increasing transistor switching speed in recent decades has enabled great performance improvement in computer systems by several orders of magnitude. Unfortunately, such phenomenal performance improvements have been accompanied by an increase in power and energy dissipation of the systems. Higher power and energy dissipation in high performance systems require moreexpensive packaging and cooling technologies, increase cost, and decrease system reliability. Nonetheless, the level of on-chip integration and clock frequency will continue to grow with increasing performance demands, and the power and energy dissipation of highperformance systems will be a critical design constraint. For example, high-end microprocessors in 2010 are predicted to employ billions of transistors at clock rates over 30GHz to achieve TIPS (Tera Instructions per seconds) performance .With this rate, high-end microprocessors power dissipation is projected to reach thousands of Watts. This thesis investigates one of the major sources of the power/energy dissipation and proposes and evaluates the techniques to reduce the dissipation.

Digital CMOS integrated circuits have been the driving force behind VLSI for high performance computing and other applications, related to science and technology. The demand for digital CMOS integrated circuits will continue to increase in the near future, due to its
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important salient features like low power, reliable performance and improvements in the processing technology.

1.2 NEED FOR LOW POWER DESIGN

There are various interpretations of the Moores Law that predicts the growth rate of integrated circuits. One estimate places the rate at 2X for every eighteen months. Others claim that the device density increases ten-fold every seven years. Regardless of the exact numbers, everyone agrees that the growth rate is rapid with no signs of slowing down.

New generations of processing technology are being developed while present generation devices are at very safe distance from the fundamental physical limits. A need for low power VLSI chips arises from such evolution forces of integrated circuits. The Intel 4004 microprocessor, developed in 1971, had 2300 transistors, dissipated about 1 watts of power and clocked at 1MHz. Then comes the Pentium in 2001, with 42 million transistors, dissipating around 65 watts of power and clocked at 2.40 GHz.While the power dissipation increases linearly as the years go by, the power density increases exponentially, because of the evershrinking size of the integrated circuits. If this exponential rise in the power density were to increase continuously, a microprocessor designed a few years later, would have the same power as that of the nuclear reactor. Such high power density introduces reliability concerns such as, electro migration, thermal stresses and hot carrier induced device degradation, resulting in the loss of performance.

Another factor that fuels the need for low power chips is the increased market demand for portable consumer electronics powered by batteries. The craving for smaller, lighter and more durable electronic products indirectly translates to low power requirements. Battery life is becoming a product differentiator in many portable systems. Being the heaviest and biggest component in many portable systems, batteries have not experienced the similar rapid density growth compared to the electronic circuits. The main source of power dissipation in these high performance battery-portable digital systems running on batteries such as note-book computers,
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cellular phones and personal digital assistants are gaining prominence. For these systems, low power consumption is a prime concern, because it directly affects the performance by having effects on battery longevity. In this situation, low power VLSI design has assumed great importance as an active and rapidly developing field.

Another major demand for low power chips and systems comes from the environmental concerns. Modern offices are now furnished with office automation equipment that consume large amount of power. A study by American Council for an Energy-Efficient Economy estimated that office equipment account for 5% for the total US commercial energy usage in 1997 and could rise to 10% by the year 2004 if no actions are taken to prevent the trend.

1.3 SIMULATION ENVIRONMENT


The simulation parameters have been analyzed with the help of the Microwind tool and DSCH for the schematic verification.

1.3.1. DSCH (DIGITAL SCHEMATIC)


DSCH is software for logic design. Based on primitives, a hierarchical circuit can be built and simulated. It also includes delay and power consumption evaluation. Silicon is for 3D display of the atomic structure of silicon, with emphasis on the silicon lattice, the dopants, and the silicon dioxide.

1.3.1.1. MOS AS A SWITCH


The MOS transistor is basically a switch. When used in logic cell design, it can be on or off. When on, a current can flow between drain and source. When off, no current flow between drain and source. The MOS is turned on or off depending on the gate voltage. In CMOS technology, both n-channel (and nMOS) and p-channel MOS (or pMOS) devices exist. The nMOS and pMOS symbols are reported below.

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Fig1.1.Symbol of NMOS and PMOS The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In contrary, the p-channel MOS device requires a logic value 0 to be on. When the MSO device is on, the link between the source and drain is equivalent to a resistance. The order of range of this on resistance is 100-5K. The off resistance is considered infinite at first order, as its value is several M.

1.3.1.2. CONNECTING PROCEDURE


Instantiate NMOS or PMOS transistors from the symbol library and place them in the editor window. Connect Vdd and GND to the schematic. Connect input button and output LED. The simulation output can be observed as a waveform after the application of the inputs as above. Click on the timing diagram icon in the icon menu to see the timing diagram of the input and output waveforms. The Verilog, Hierarchy and Netlist window appears. This window shows the Verilog representation of NORgate. Click OK to save the Verilog as a .txt file. The DSCH3 program is a logic editor and simulator. DSCH3 is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH3 provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structures. Some techniques for low power design are described in the manual. DSCH3 also features the symbols, models and assembly support for 8051 and 18f64. DSCH3 also includes an interface to SPICE. The
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MICROWIND3program allows the student to design and simulate an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to view and simulate. MICROWIND3includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, Verilog compiler, tutorial on MOS devices). You can gain access to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately.

1.3.2 THE MOS AS A SWITCH


The MOS transistor is basically a switch. When used in logic cell design, it can be on or off. When on, a current can flow between drain and source. When off, no current flow between drain and source. The MOS is turned on or off depending on the gate voltage. In CMOS technology, both n-channel (or nMOS) and pchannel MOS (or pMOS) devices exist. The nMOS and pMOS symbols are reported below. The symbols for the ground voltage source (0 or VSS) and the supply (1 or VDD).

The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In contrary, the p-channel MOS device requires a logic value 0 to be on. When the MSO device is on, the link between the source and drain is equivalent to a resistance. The order of range of this on resistance is 100-5K. The off resistance is considered infinite at first order, as its value is several M
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1.3.3 THE TRANSMISSION GATE:


Both NMOS devices and PMOS devices exhibit poor performances when transmitting one particular logic information. The nMOS degrades the logic level 1, the pMOS degrades the logic level 0. Thus, a perfect pass gate can be constructed from the combination of nMOS and pMOS devices working in a complementary way, leading to improved switching performances. Such a circuit

Fig1.2. is called the transmission gate. In DSCH3, the symbol may be found in the Advance menu in the palette. The transmission gate includes one inverter, one nMOS and one pMOS

The Logic Inverter


In this section, an inverter circuit is loaded and simulated. Click File Open in the main menu. Select INV.SCH in the list. In this circuit are one button situated on the left side of the design, the inverter and a led. Click Simulate Start simulation in the main menu.

Fig1.3. Now, click inside the buttons situated on the left part of the diagram. The result is displayed on the leds. The red value indicates logic 1, the black value means a logic 0. Click the button Stop simulation shown in the picture below. You are back to the editor.
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Click the chronogram icon to get access to the chronograms of the previous simulation . As seen in the waveform, the value of the output is the logic opposite of that of the input.

Double click on the INV symbol, the symbol properties window is activated. In this window appears the VERILOG description (left side) and the list of pins (right side). A set of drawing options is also reported inthe same window. Notice the gate delay (0.03ns in the default technology), the fan out that represents the number of cells connected to the output pin (1 cell connected), and the wire delay due to this cell connection (An extra 0.140ns delay).

1.3.4 THE CMOS INVERTER


The CMOS inverter design is detailed in the figure below. Here the p-channel MOS and the n-channel MOS transistors function as switches. When the input signal is logic 0 the nMOS is switched off while PMOS passes VDD through the output. When the input signal is logic 1, the pMOS is switched off while the nMOS passes VSS to the output.

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Fig1.4. `The fanout corresponds to the number of gates connected to the inverter output. Physically, a large fanout means a large number of connections, that is a large load capacitance. If we simulate an inverter loaded with one single output, the switching delay is small. Now, if we load the inverter by several outputs, the delay and the power consumption are increased. The power consumption linearly increases with the load capacitance. This is mainly due to the current needed to charge and discharge that capacitance.

Inverter Simulation

The inverter simulation is conducted as follows. Firstly, a VDD supply source (1.2V) is fixed to the upper metal2 supply line, and a VSS supply source (0.0V) is fixed to the lower metal2 supply line. The properties are located in the palette menu. Simply click the desired property , and click on the desired location in the layout. Add a clock on the inverter input node (The default node name clock1 has been changed into Vin)and a visible property on the output node Vout

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Fig 1.5 & 1.6. The command Simulate Run Simulation gives access to the analog simulation. Select the simulation mode Voltage vs. Time. The analog simulation of the circuit is performed. The time domain waveform, proposed by default, details the evolution of the voltages in1 and out1 versus time. This mode is also called transient simulation

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1.3.5 . MICROWIND
Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator. The Microwind program allows designing and simulating an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to view and simulate. Microwind includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view, Verilog compiler, tutorial on MOS devices). You can gain access to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately.

1.3.5.1. MOS LAYOUT


Microwind is used to draw the MOS layout and simulate its behavior. The Microwind display window includes four main windows: 1. The main menu 2. The layout display window 3. The icon menu 4. The layer palette.

The layout window features a grid, scaled in lambda () units. The lambda unit is fixed to half of the minimum available lithography of the technology. The default technology is a CMOS 6-metal layers 0.12m technology, consequently lambda is 0.06m (60nm).

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The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. By using the following procedure, you can create a manual design of the n-channel MOS. 1. Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box. Release the button. This creates a box in polysilicon layer. The box width should not be inferior to 2 , which is the minimum width of the polysilicon box. 2. Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 2-3. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device.

Fig.1.7 Creating the N-channel MOS transistor

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1.3.5.2

STATIC MOS CHARACTERISTICS

The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. In Figure, the MOS width is 1.74m and the length is 0.12m. A high gate voltage (Vg =1.2V) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. You may change the voltage values of Vd, Vg, Vs by using the voltage cursors situated on the right side of the window. A maximum current around 1.5mA is obtained for Vg=1.2V, Vd=1.2V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3.

Fig.1.8 N-Channel MOS characteristics.

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1.3.5.3MANUAL LAYOUT DESIGN


Click the icon MOS generator on the palette. The following window appears. By default the proposed length is the minimum length available in the technology (2 lambda), and the width is 10 lambda. In 0.12m technology, where lambda is 0.06m, the corresponding size is 0.12m for the length and 0.6m for the width. Simply click Generate Device, and click on the middle of the screen to fix the MOS device. Click again the icon MOS generator on the palette. Change the type of device by a tick on p-channel, and click Generate Device. Click on the top of the nMOS to fix the pMOS device.

Fig.1.9 Selecting the PMOS device

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1.3.5.4

CONNECTION BETWEEN DEVICES

METAL TO POLY
As polysilicon is a poor conductor, metal is preferred to interconnect signals and supplies. Consequently, the input connection of the inverter is made with metal. Metal and polysilicon are separated by an oxide which prevents electrical connections. Therefore, a box of metal drawn across a box of polysilicon does not allow an electrical connection. To build an electrical connection, a physical contact is needed. The corresponding layer is called "contact". You may insert a metal-to-polysilicon contact in the layout using a direct macro situated in the palette.

SUPPLY CONNECTIONS
The next design step consists in adding supply connections, that is the positive supply VDD and the ground supply VSS. We use the metal2 layer (Second level of metallization) to create horizontal supply connections. Enlarging the supply metal lines reduces the resistance and avoids electrical overstress. The simplest way to build the physical connection is to add a metal/Metal2 contact that may be found in the palette. The connection is created by a plug called "via" between metal2 and metal layers. The final layout design step consists in adding polarization contacts. These contacts convey the VSS and VDD voltage supply close to the bulk regions of the device. Remember that the n-well region should always be polarized to a high voltage to avoid short-circuit between VDD and VSS. Adding the VDD polarization in the n-well region is a very strict rule.

INTERCONNECTS
Up to 6 metal layers are available for signal connection and supply purpose. A significant gap exists between the 0.7m 2-metal layer technology and the 0.12m technology in terms of interconnects efficiency. Firstly, the contact size is 6 lambda in 0.7m technology, and only 4 lambda in 0.12m. This features a significant reduction of device connection to metal and metal2, as shown in figure 4-8. Notice that a MOS device generated using 0.7m design rules is

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still compatible with 0.12m technology. But a MOS device generated using 0.12m design rules would violate several rules if checked in 0.7m technology.

Secondly, the stacking of contacts is not allowed in micro technologies. This means that a contact from poly to metal2 requires a significant silicon area as contacts must be drawn in a separate location. In deep-submicron technology (Starting 0.35m and below), stacked contacts are allowed.

SIMULATION
A simulation window appears with inputs and output, shows the tphl, tplh and tp of the circuit. The power consumption is also shown on the right bottom portion of the window. If you are unable to meet the specifications of the circuit change the transistor sizes. Generate the layout again and run the simulations till you achieve your target delays. Depending on the input sequences assigned at the input the output is observed in the simulation. The power value is also given.

CHECKING THE LAYOUT


The Design Rule Checker (DRC) scans the design and verifies a set of design rules. The errors are highlighted in the display window, with an appropriate message giving the nature of the error. Details about the position and type of error(s) appear on the screen. Only an errorfree layout can be sent to fabrication.

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CHAPTER-2 SOURCES OF POWER DISSIPATION & REDUCTION OF ENERGY IN CMOS DIGITAL CIRCUITS

Power consumption is one of the basic parameters of any kind of integrated circuit (IC).Power and performance are always traded off to meet the system requirements. Power has a direct impact on the system cost. If an IC is consuming more power, then a better cooling mechanism would be required to keep the circuit in normal conditions. Otherwise, its performance is degraded and on continuous use it may be permanently damaged.

2.1 POWER AND ENERGY DEFINITIONS

It is important at this point, to distinguish between energy and power. The power consumed by a device is, by definition, the energy consumed per unit time. In other words, the energy (E) required for a given operation is the integral of the power (P) consumed over the operation time (Top), hence,
Top

E= P(t )dt
0

(2.1)

Here, the power of digital CMOS circuit is given by

P = C VDD VS f (2.2)

where, C is the capacitance being recharged during a transition. VDD is the supply voltage, Vsis the voltage swing of the signal, and f is the clock frequency. If it is assumed that an

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operation requires n clock cycles, Top can be expressed as n / f. Hence, Equation (2.1) can be rewritten as

E = n C VDD VS

(2.3)

It is important to note that the energy per operation is independent of the clock frequency. Reducing the frequency will lower the power consumption but will not change the energy required to perform a given operation [1]. Since the energy consumption is what determines thebattery life, it is imperative to reduce the energy rather than just the power. It is, however important to note that the power is critical for heat dissipation considerations.

2.2 OVERVIEW OF POWER DISSIPATION

It is more convenient to talk about power dissipation of digital circuits at this point. Although power depends greatly on the circuit style, it can be divided, in general, into static and dynamic power. The static power is generated due to the DC bias current, as is the case in transistor- transistor-logic (TTL), emitter-coupled logic (ECL), and N-type MOS (NMOS) logic families, or due to leakage currents. In all of the logic families except for the push-pull types such as CMOS, the static power tends to dominate. That is the reason why CMOS is the most suitable circuit style for very large scale integration (VLSI).

CMOS is the logic family preferred in many designs due to following reasons:(a) Impeccable noise margins. (b) Perfect logic levels. (c) Negligible static power dissipation. (d) Gives good performance in most cases. (e) Easy to get a functional circuits. (f) Lot of tools available to automate the design process. The power consumed when the CMOS circuit is in use can be decomposed into two basic classes: static and dynamic.

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2.2.1 STATIC POWER

The static or steady state power dissipation of a circuit is expressed by the following relation

Pstat= IstatVDD (2.4)

Where,Istatis the current that flows through the circuit when there is no switching activity. Ideally, CMOS circuits dissipate no static (DC) power since in the steady state there is no direct path from VDD to ground as PMOS and NMOS transistors are never on simultaneously. Of course, this scenario can never be realized in practice since in reality the MOS transistor is not a perfect switch. Thus, there will always be leakage currents and substrate injection currents, which will give to a static component of CMOS power dissipation. For a sub-micron NMOS deviceW/ L = 10/ 0.5, the substrate injection current is of the order of 1- 100 A for a VDD of 5 V. Another form of static power dissipation occurs for the so-called Rationed logic. PseudoNMOS is an example of a Ratioed CMOS logic family. In this, the PMOS pull-up is always on and acts as a load device for the NMOS pull-down network. Therefore, when the gate output is in low-state, there is a direct path from VDD to ground and the static currents flow. In this state, the exact value of the output voltage depends on the ratio of the strength of PMOS and NMOS networks hence the name. The static power consumed by these logic families can be considerable. For this reason, logic families such as this, which experience static power consumption, should be avoided for low-power design. With that in mind, the static component of power consumption in low-power CMOS circuits should be negligible and the focus shifts primarily to dynamic power consumption.

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Fig. 2.1.CMOS Inverter for Power Analysis.

2.2.2 DYNAMIC POWER

The dynamic component of power dissipation arises from the transient switching behavior of the CMOS device. At some point during the switching transient, both the NMOS and PMOS devices will be turned on. This occurs for gate voltages between Vtnand VDD - Vtp. During this time, a short-circuit exists between VDD and ground and the currents are allowed to flow. A detailed analysis of this phenomenon by Veendrick reveals that with careful design of the transition edges, this component can be kept below 10-15% of the total power [2]; this can be achieved by keeping the rise and fall times of all the signals throughout the design within a fixed range (preferably equal). Thus, although short circuit dissipation cannot always be completely ignored, it is certainly not the dominant component of power dissipation in well-designed CMOS circuits. Instead, dynamic dissipation due to capacitance charging consumes most of the power.

This component of dynamic power dissipation is the result of charging and discharging of the parasitic capacitances in the circuit. The situation is modeled in Figure 2.1, where the parasitic capacitances are lumped at the output in the capacitor C. Consider the behavior of the
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circuit over one full cycle of operation with the input voltage going from VDD to ground and back to VDD again. As the input switches from high to low, the NMOS pull-down network is cut-off and PMOS pull-up network is activated charging load capacitance C up to VDD. This charging process draws energy equal to C from the power supply. Half of this is dissipated

immediately in the PMOS transistors, while the other half is stored on the load capacitance. Then, when the input returns to VDD, the process is reversed and the capacitance is discharged, its energy being in the NMOS network. In summary, every time a capacitive node switches from ground to VDD (and back to ground), energy of C is consumed. This leads to the

conclusion that CMOS power consumption depends on the switching activity of the signals involved. We can define activity, as the expected number of zero to one transition per data cycle. If this is coupled with the average data rate, f, which maybe the clock frequency in a synchronous system, then the effective frequency of nodal charging is given the product of the activity and the data rate:f. This leads to the following formulation for the average CMOS power consumption: Pdyn= C f (2.5)

This classical result illustrates that the dynamic power is proportional to the switching activity, capacitive loading and the square of the supply voltage. In CMOS circuits, this component of power dissipation is by far the most important accounting for at least 90% of the total power dissipation.

So, to reduce the power dissipation, the circuit designer can minimize the switching event, decrease the node capacitance, reduce the voltage swing or apply a combination of these methods. Yet, in all these cases, the energy drawn from the power supply is used only once before being dissipated. To increase the energy efficiency of the logic circuits, other measures can be introduced for recycling the energy drawn from the power supply.

A novel class of logic circuits called ADIABATIC LOGIC offers the possibility of further reducing the energy dissipated during the switching events and the possibility of recycling or reusing some of the energy drawn from the power supply [3]. To accomplish this goal, the circuit topology and the operating principle have to be modified, sometimes drastically.

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The amount of energy recycling achievable using adiabatic techniques is also determined by the fabrication technology, switching speed and the voltage swing.

2.3 ENERGY-DELAY PRODUCT: A METRIC FOR LOW ENERGY DESIGN

The scaling of VDD is beneficial from the energy point of view but may have serious side effects on the delay. This implies that using the energy as the metric is not sufficient. Horowitz et al have proposed an alternative which accounts for both energy and delay by using the product of the ENERGY PER OPERATION and the DELAY PER OPERATION. This metric can be used as the basis for design optimization and comparison between different systems. To minimize the energy-delay product (EDP), we need to consider the trends of CMOS scaling and its implications on the delay. The delay of CMOS circuit will most probably increase as the supply voltage increases. This is illustrated below in Figure 2.2. It also shows the energy as a function of VDD.

Fig. 2.2.Normalized delay, energy and energy-delay product vs. supply voltage.

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Delay is normalized to delay value at largest supply voltage (3.0 V), and Energy is normalized to energy value at smallest supply voltage (0.6 V). The product of the energy and the delay, which is also shown in the same figure, demonstrates the trade-off between the delay and the energy. For low supply voltages, the energy is minimumbut the delay is not. Increasing the supply voltage may improve the speed but at the expense of the energy. The EDP is a metric that accounts for both and can be used to compare different processes. The closer the minimum of the energy-delay curve to the 1-V supply, the better the process is. The optimum supply voltage can also be determined from the EDP. Now, so far we have discussed the energy consumption in digital CMOS circuits. In this section, we would look at the means of reducing the energy/ power in digital CMOS circuits and systems.

2.4 REDUCTION OF POWER SUPPLY

The energy and power consumed by the CMOS digital circuits are sensitive to the power supply voltage as given by: E=C P=C f (2.6) (2.7)

Reducing the power supply voltage is an efficient approach to lower the energy and power. The power supply voltage is actually the most crucial factor in reducing energy/ power. This will, however, be at the expense of the delay of the circuits. Using the EDP as a metric, one can derive the optimum supply voltage that would yield minimum EDP. To simplify the analysis, it will be assumed that the saturation current of deep submicrometer MOSFETs is proportional to (VGS-VT)[5]. Assuming VGS = VDD (for maximum current) and using the delay expression, it can be shown that the delay becomes KVDD/ (VDD-VT), where K is a constant independent of VDD.

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The EDP can hence be expressed as ,

VDD 3_____ E td = const(VDD VT )(2.8)


The optimum supply voltage (for minimum EDP) can be found from Equation (2.7) and is given by VDD( opt) = 3VT (3 )(2.9)

The above expression is valid for long-channel and deep sub micrometer devices. For long- channel transistors ( = 2), the optimum supply voltage is equal to 3VT, which agrees with the result of the analysis presented in [6]. For deep sub micrometer devices with closer to unity the optimum voltage is expected to be less than 3VT. For example, if = 1.5, then VDD(opt) = 2VT. At any rate, the optimum value for VDD is proportional to the threshold voltage. So, the conclusion is that the supply voltage must be reduced to minimize the EDP. Scaling the supply voltage below the point of minimum EDP will cause severe degradation in the delay. The second point is that the optimum supply voltage is related to the threshold voltage.

2.5 REDUCTION OF SWITCHING ACTIVITY

In the previous section, the method for minimizing dynamic power consumption in CMOS digital integrated circuits by supply voltage scaling has been discussed. Another approach to low-power design is to reduce the switching activity and the amount of the switched capacitance to the minimum level required to perform a given task. The measures to accomplish this goal can range from optimization of algorithm to logic design, and finally to physical mask design.

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2.5.1 SWITCHING ACTIVITY REDUCTION

Switching activity in CMOS digital integrated circuits can be reduced by algorithmic optimization, architecture optimization, logic topology and circuit optimization. Each of these aspects will be discussed briefly as below

(a) ALGORITHMIC OPTIMIZATION. Algorithmic Optimization depends heavily on the application and on the characteristics of the data, such as the dynamic range, the correlation, statistics of the data transmission and so on. Some of the techniques apply only to applications such as digital Signal Processing (DSP) and cannot be used for general-purpose processing.

(b) ARCHITECTURE OPTIMIZATION. Several architectural techniques have been proposed to reduce the switching activity, such as, ordering of the input signals and delay path balancing to remove glitching. In multi-level logic circuits, the propagation delay from one logic block to the next can cause spurious signal transitions or glitches, as a result of critical races or dynamic hazards. In general, if all input signals of a gate change simultaneously, no glitching occurs. But a dynamic hazard or glitch can occur if input signals change at different times. Thus, a node can exhibit multiple transitions in a single clock cycle before settling to the correct logic level.

2.6 REDUCTION OF SWITCHED CAPACITANCE

The amount of switched capacitance plays a significant role in the dynamic power dissipation of the circuit as is given by Equation (2.5). Hence, the reduction of this parasitic capacitance is a major goal for low-power design of digital integrated circuits. The switching capacitance can be broken down into two categories, the capacitance in dense logic (which includes the transistor parasitic and wire capacitances at the output of the gates) and the capacitances of the busses and a clock network (which is mainly the wire capacitance). In some

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systems, the capacitance of the busses and a clock network may comprise close to 50% of the overall chip capacitance .An example of such system is the Alpha chip.

At the system level, one of the approaches to reduce the switched capacitance is to limit the use of shared resources. A simple example is the use of a global bus structure for the data transmission between a large numbers of operational modules .The type of logic style used to implement a digital circuit also affects the physical capacitance of the circuit. The physical capacitance is a function of the number of transistors that are required to implement a given function. For example, one approach to reduce the physical capacitance is to use transfer gates over conventional CMOS logic gates to implement logic functions. Pass-gate logic design is attractive since fewer transistors are required for certain functions such as XOR and XNOR. In many arithmetic operations where binary adders and multipliers are used, pass transistor logic offers significant advantages. Similarly, multiplexers and other key building blocks can also be simplified using deign style.

The amount of parasitic capacitance that is switched (i.e., charged up or charged down) during operation can also be reduced at the physical design level, or mask level. Designing a logic gate with minimum-size transistors certainly affects the dynamic performance of the circuit, and this trade-off between dynamic performance and power dissipation should be carefully considered in critical circuits. Consequently, a standard-cell based design may have considerable overhead in terms of switched capacitance in each cell.

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