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Advanced Digital IC-Design

This lecture will

The MOS-transistor

Refresh the MOS-transistor function and models Especially, Especially short channel effects

Digital IC-Design

The Diode in an IC-device

The Diode

Diodes appears in all MOS-transistors (the drain & source area) They have parasitics that affects the performance (speed, power) Diodes should always be backward y biased (negative VBS)

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doped Semiconductor 2 .British Patent in 1935 None of them built a working component The first working MOS-transistor was shown in the early sixties Metal Oxide Silicon.U S Patent in 1930 U. What is a MOS-transistor? MOS = ”Metal Oxide Semiconductor” Polysilicon SiO2 In early thirties. Julius Edgar Lilienfeld described the first MOSFET structure .S.The Simplest IC-device Discrete component p Metal p+ n+ Semiconductor n+ pp+ Advanced Digital IC-Design ICstructure SiO2 The MOS Transistor pn-junctions The MOS-transistor: An Old Invention In 1925. a similar structure was shown by Oskar Heil .Diode .

The MOS-transistor (or MOSFET) Most important device in digital design Very good as a switch V d i h Relatively few parasitics Rather low power consumption High integration density Simple manufacturing Economical for large complex circuits N-MOS Transistor Gate Bulk Source Drain Silicon Structure St t Thin Oxide Each box in the layout represents a mask or a step in the process + pp+ n+ n+ p - Mask Layout P-MOS Transistor Gate Bulk Source Drain How does it Work? Technologies N-Well N W ll P-Well VGS must be Opens a lager than a channel threshold VT np ++ p n- + p + Twin-Tub N-Well VGS Gate Source VDS ID VDS drives a current ID p - The gate length sets the name of the technology Drain 3 .

If not shown – it is assumed to be connected to the supply/GND.6 um 2003: 65 nm 2013: 18 nm? VGS > 0 L n+ n+ Depletion Region The technology is named after the gate length L “Diode area” p- 4 . Gate Source Drain Gate Source Bulk (Body) Drain Infinite resistance when VGS < VT Req when VGS ≥ VT VT = Threshold voltage Bulk (Body) Important Dimensions Gate Source Drain How does the Transistor Work? Technology development: When VGS is slightly increased g g Negative charges are attracted A depletion region is formed W tox 1993: 0.What is a MOS Transistor? MOS – a Four Terminal Device Gate voltage controls the current from drain to source A Switch VGS Circuit Symbol VGS Source connected to lower potential for n-channel devices ( (often to GND) ) Source connected to higher potential for p-channel devices (often to VDD) G G D S Ron eq D S Bulk keeps the substrate at a stable potential.

to the charge velocity caused by the drain voltage VDS Q ∼ VGS −VT Q ∼ VDS V ξ = DS L I D = k´n VGS forms a vertical E-field n+ n+ I D = k´n V W (VGS − VT − DS )VDS 2 L ID V W (VGS . to the # of charges attracted by the gate voltage VGS Linear Region (Resistive Operation) I D = μn Q ξ W μn = Electron mobility ξ = E-field over the channel # of charges attracted by the gate Less charges in drain region ID is proportional to the horizontal E-field i.e.DS ) VDS 2 L (k 'n = μnCox ) VDS establish a horizontal E-field p- From charge conc.VT . From Horizontal E-Field 5 .How does it Work? When VGS is increased above VT More negative than positive charges are attracted close to the gate (turns to n-type material) A channel is formed (Strong inversion) Linear Region (Resistive Operation) VDS is increased slightly Horizontal E-field from drain to source A current ID is established VGS > VT VDS<VGS-VT VGS > VT ID n+ n-channel p - n+ Depletion Region n+ n-channel n+ Depletion Region p- Linear Region (Resistive Operation) ID is proportional to the vertical E-field i.e.

e.VT in the linear equation VGS > VT VDS=VGS-VT ID n+ n+ ”VDS /2" p- V W (VGS − VT − DS )VDS L 2 W V −V I D = k´n (VGS − VT − GS T )(VGS − VT ) L 2 k´ W I D = n (VGS − VT ) 2 2 L I D = k´n Channel Length Modulation VDS > VGS-VT Channel Length Modulation Saturation VDS > VGS-VT ⇒ Pinch off The effective channel length is modulated by VDS g y Electrons are injected through the depletion region VGS>VT VDS>VGS-VT ID n+ L´ L n+ I D = k´n Pinch off W (VGS − VT ) 2 (1 + λVDS ) L λ = Empirical constant 6 . VGD = VT) No channel close to the drain Saturation Region Insert VDS = VGS .Saturation Region VDS = VGS – VT Strong inversion reached precisely (i.

for NMOS) There are always free electrons in the substrate To form a channel. I D = k´n VDS W V ((VGS − VT )VDS − DS )(1 + λVDS ) L 2 k´n W 2 ≥ VGS − VT . Not Allowed Positive VSB makes it h d t attract negative charges t P iti k harder to tt t ti h to the channel That is.The Threshold Voltage VT The substrate is slightly doped (p. we need to attract these negative charges T f h l dt tt t th ti h The threshold is when the number of negative and positive charges are equal The value of VT is thus set by the p-doping concentration The Bulk (Body) Potential The bulk is most often connected to GND (VDD for PMOS) Negative VSB opens the diode. the threshold voltage will increase VGS > VT p+ n n-channel p+ VSB VGS n+ n+ n + Depletion Region Strongly p-doped p- The Threshold Voltage VT MOS Model for Long Channels Widely used model for manual calculations VDS ≤ VGS − VT . I D = (VGS − VT ) (1 + λVDS ) 2 L 2 VT = VT 0 + γ ( − 2φF + VSB − − 2φF ) φF = Fermi potential γ increases with the acceptor concentration Low threshold ⇒ Low voltage transistors but they are leaky y y Two threshold voltage technologies can be used for low power k´n = μ n Cox VT = VT 0 + γ ( − 2φF + VSB − − 2φF ) Added to avoid discontinuity y 7 .

Velocity & Mobility The electron (hole) velocity is related to the mobility Velocity & Mobility (μ ) The electron (hole) velocity is related to the mobility The velocity is also dependent on the E-field (μ ) (ξ ) μn = 0. the velocity saturates due E field to collisions with other atoms υn = μn ξ DS E ν n (m/s) it y Mo b il Constant Velocity υsat m ≈ 105 for both electrons and holes s n+ n+ νsat = 105 m/s Co ns Source Drain ξ E ξc sat The mobility is not constant when velocity saturation is reached ta nt EDS [V/um] VDS establish a horizontal E-fieldp 0 8 .013 = Hole mobility Vs Typical 0.038 m2 = Electron mobility Vs m2 μ p = 0.35μm technology The mobility is dependent on doping concentration … Often determined empirically Note that the electron mobility is about 3 times higher m s m υ p = μ pξ s υn = μnξ Velocity Saturation (υ sat ) VDS forms a horizontal E-field Velocity Saturation (υ sat ) (ξ ) An increased E-field leads to higher electron velocity However at a critical E-field (ξ c ).

5 VGS= 1.ID versus VDS 0.63 V VGS = VDD = 2.5 ID (A) 3 2 1 0 0 1 0.5 1 1.2 0.5 1 VGS(V) 1.1 0.25 0 25 ID (mA) 0.6 06 0.07 V x 10 2.0 2.5 1 VGS(V) 1.0 0.1 0 0 0.5 2 2.15 0.3 0.VT 0.0.5 VDS (V) 1.2 A first order model of the velocity VGS= 2.5 0.5 VDS (V) Short Channel VGS= 1.1 0 0 0.5 ID (mA) VGS= 2.0 2 2.5 1 1.5 For both ID versus VGS x 10 -4 -4 ID (mA) 6 VGS-VT = 2.0 VDSAT = 0.05 0 05 0 0 0.5 2 2.43 = 2.2 0.4 0.5 .0 ⎧υ = μn ξ ⎪ ⎨ ⎪υ = υ = μ ξ sat n c ⎩ for ξ ≤ ξ c for f ξ ≥ ξc 9 .5 quadratic d ti 0.5 0 0 0.5 Long channel Long-channel model Short-channel model 5 2 4 ID (A) quadratic linear 1.5 2.5 VGS= 2.5 1.5 VGS= 2.5 0.4 0.0 0.5 VGS= 1.3 0.5 VDS (V) Long Channel VGS= 1.5 Long Channel Short Channel ID versus VDS Linear ID(VGS) Model for Manual Analysis Quadratic ID(VGS) VDS = VGS .5 2 2.

VDSAT ) A Unified Model for Manual Analysis ' I D = kn Three Regions VDSAT V 2 W ((VGS −VT )VDS − DS )(1+ λVDS ) Resistive 2 L 0.Model for Manual Analysis A Unified Model for Manual Analysis A first order model of the velocity y saturated region: I DSAT VDSAT 2 W = μn Cox ((VGS −VT )VDSAT − ) 2 L Vmin 2 W I D = k ((VGS −VT )Vmin − )(1+ λVDS ) L 2 ' n Vmin = min(VGS −VT .1 Linear Velocity saturated VGS = 1. VDS .15 0 15 0.5 V ' I D = kn V 2 W ((VGS −VT )VDSAT − DSAT )(1+ λVDS ) Velocity saturated L 2 0.63 V I D (mA) VGS = 2 V ID = ' kn W (VGS −VT )2 (1+ λVDS ) Saturated 2 L 0.5 VGS = 1 V VGS-VT 0 0 Saturated 1 VDS (V) 2 10 .

0V -0. Gate Capacitance .Diode areas .0V 2 0V Assume that all variables are negative! ln(ID) Super-threshold region (Super-VT) Sub-threshold region (Sub-VT) VT 1 2 3 -0.2 VGS = -1.The PMOS Transistor Velocity saturation is less pronounced for PMOS due to lower mobility 0 x 10 -4 Sub-threshold Region The sub threshold drain current have an exponential relation to the gate voltage (compare to bipolar) VGS = -1.Gate to Bulk .Gate to Source/Drain Xd 11 . Junction Cap.5V -0.5 VDS (V) -1 -0.8 VGS = -2.5V -1 -2.5 0 VGS (V) MOS Dynamic Behavior MOS Capacitances Source Gate Drain yp p Two Types of Capacitance Junction Capacitance .5 -2 -1.Divided in two parts .4 ID (A) -0.6 VGS = -2. p Overlap Cap.area and side wall CGS n+ CGD n+ tox CSB CG CDB Channel Cap.

Junction Capacitance Drain/Source Diffusion Bottom Junction Capacitance CDiff = CBot + CSW CDiff = CBot + CSW CBot = Cj × Area CSW = CjSW × Perimeter Cj in F/um2 CjSW in F/um G at e Don’t count the wall towards the channel Ch To an wa ne rds l W Ls Side Wall Nonlinear: dependent on the diode voltage Gate Capacitance Gate Source Drain Channel Capacitance Xd Cut off Linear CG = Cox × W × Leff CGS Leff CGD CGB n+ n+ n+ n+ CG depends on the region p g Saturation COX in F/um2 n+ n+ 12 .

Static Behavior Source Drain ' I D = kn CGD = Cox × W × Xd CGS = Cox × W × Xd Xd Leff CGS CGB CGD V 2 W ((VGS −VT )VDS − DS )(1+ λVDS ) Resistive 2 L Cox in F/um2 Or CGD = Co × W CGS = Co × W ID = ' kn W (VGS −VT )2 (1+ λVDS ) Saturated 2 L ' I D = kn V 2 W ((VGS −VT )VDSAT − DSAT )(1+ λVDS ) Velocity saturated L 2 Threshold Voltage Co in F/um VT = VT 0 + γ ( −2φF + VSB − −2φF ) A Unified Model for Manual Analysis Conclusions . VDSAT ) CDiff = CBot + CSW CBot = Cj × Area CSW = CjSW × Perimeter Junction J ti Capacitance VT = VT 0 + γ ( −2φF + VSB − −2φF ) 13 .Dynamic Behavior CG = Cox × W × Leff CGD = CGS = W × Cox Vmin 2 W ID = k ((VGS −VT )Vmin − )(1+ λVDS ) L 2 ' n × Xd Gate Capacitance Vmin = min(VGS −VT .Overlap Capacitance Gate Conclusions . VDS .