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A 5 GHz, 21 dBm Output-IP3 Resistive Feedback LNA in 90-nm CMOS

Bevin G. Perumana1, 2, Jing-Hong C. Zhan1, 3, Stewart S. Taylor1
Intel Corporation, Hillsboro, Oregon, USA. 3 RF Division, MediaTek, HsinChu, 300, Taiwan.,,
Abstract—An inductor-less low noise amplifier is implemented in 90 nm CMOS using resistive feedback and non-linearity cancellation. In the high-linearity mode with non-linearity cancellation, the LNA achieves an output IP3 of 21.2 dBm and a noise figure of 2.9 dB at 5 GHz. In the low-noise mode, when the cancellation is switched off, it has a noise figure of 2.3 dB and an output IP3 of 14.3 dBm at 5 GHz. In both modes, the LNA has a gain above 24 dB with a bandwidth above 6.2 GHz. This circuit consumes 42 mW of power and occupies an active die area of 0.016 mm2.

Joy Laskar2
Georgia Electronic Design Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA.



Broadband inductor-less LNAs based on resistive feedback [1] have been shown to be a cost-effective alternative to multiple tuned LNAs requiring numerous inductors for modern wireless systems supporting multiple standards over multiple frequency bands. Though such circuits have extremely small die area requirements, the power consumption is higher and the linearity worse. Linearity is further lowered by the loop-gain roll-off at higher frequencies. The linearity limitations in resistive feedback LNAs and techniques to improve IP3 are presented, including a nonlinearity cancellation technique which can be turned on and off as required, without significantly affecting gain and input matching. Based on these techniques, a 90-nm CMOS resistive feedback LNA is presented which can operate in two modes: a high-linearity mode and a low-noise mode. In the high-linearity mode, the LNA has an output IP3 of 21.2 dBm and a noise figure of 2.9 dB at 5 GHz. Its gain is 24.4 dB with a bandwidth of 6.2 GHz. In the low-noise mode, when the cancellation is switched off, it has a noise figure of 2.3 dB and an output IP3 of 14.3 dBm at 5GHz. In this mode, the LNA has a gain of 25.2 dB with a bandwidth of 7.25 GHz. This circuit consumes 42 mW of power and occupies an active die area of 0.016 mm2.

Figure 1. Schematic of the resistive feedback LNA with non-linearity cancellation.



In tuned LNAs based on inductive source degeneration, the main IP3 limitation is often due to the transconductance nonlinearity in the input transistor. Several linearity improvement techniques like derivative superposition [2], modified derivative superposition [3], and active post-distortion [4] have been demonstrated for the cellular band (869-894 MHz). In these techniques, the cascode transistor is assumed to be linear. In the resistive feedback LNA with gm-enhanced cascode structure [1], the cascode transistor has a smaller W/L ratio (to achieve a high bandwidth) and lower bias current (to reduce the voltage drop across the load resistor) when compared to the main transistor. Thus the gm of the cascode device is significantly lower than the main transistor, leading to a high gain in the common-source input stage preceding the cascode stage. This makes the gm non-linearity in the cascode

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Transistors in M1. Figure 2. Resistors RB2 and RB3 protect the transistors in the two source followers from breakdown. 3.stage limit the overall circuit linearity. The output buffer has an insertion loss of about 7dB and its input IP3 is higher than 15 dBm from 500 MHz to 6 GHz. Applying negative feedback to a non-linear amplifier modeled by the power series v out = a1v in + a2v in 2 + a3v in 3 improves its IP3 by the following factor: ! IP3 |CL a3 2 3/2 = (1+ a1 f ) 2 # (1+ a1 f ) IP3 |OL a3 (1+ a1 f ) " 2 fa2 To facilitate measurements. The output at the load resistor RL is fed back to the input through a source follower (M4). IP3 |CL . The cancellation is turned on and off by changing the gate voltage of M6 with little effect on the gain and input matching of the LNA. Transistor M6 is used to cancel the IP3 limiting non-linearity of the cascode transistor M2 in the high-linearity mode. IP3 |OL and f denote the close loop iIP3. While M6 is in weak-inversion for gm3 cancellation in the high-linearity mode. a level shifter (M3) and the feedback resistor RFB. 2. It occupies an active die area of 325 µm x 50 µm. significant improvement in linearity can only be achieved if the nonlinearity of the cascode stage is reduced. The schematic of the LNA is shown ! Fig. The chip microphotograph is shown in Fig. 373 . The IP3 of the circuit is kept high even without cancellation by reducing non-linearities in the loop and by increasing the open-loop bandwidth as described before. respectively. MEASUREMENT RESULTS This design is implemented in a seven metal. This implies that high frequency IP3 is improved by increasing the open-loop bandwidth. open loop iIP3 and the feedback factor of the feedback amplifier. 90-nm CMOS process. Schematic of the 50-Ω output buffer. Buffer 50 µ m Figure 3. Non-linearity cancellation is achieved when the gm3 (δ3ID/δV3GS) of M6 cancels that of M2 [2]. 2 fa2 2 << a3 (1+ a1 f ) . Hence. The LNA draws about 15. Figure 4. (1) LNA ! Here. a modified super source follower [1] was used as the 50-Ω output buffer. 325 µ m III.7 V supply.5 mA from a 2. Another source follower (M5 and R3) is used to drive a 50-Ω output buffer. Measured gain of the LNA in high linearity and low noise modes. which was characterized separately. it is biased in stronginversion region for the low-noise mode. The following measurement results are plotted after de-embedding the 50-Ω output stage. Chip micrograph of the LNA. Equation (1) shows that linearity is not significantly improved by feedback at high ! ! ! frequencies if there!is roll-off in loop-gain ( a1 f ) with frequency [5]. 1. The schematic of the buffer is shown in Fig. The level shifter M3 is used to bias the gmenhanced cascode by forming a DC feedback loop. M2 and resistor R1 form a gm-enhanced cascode amplifier.

3 dB to 2.7 – 5.2 dB with 7.5 – 3. 424 JSSC 2006 pp. The input-IP3s of the LNA in the two modes are plotted in Fig.016 0. Figure 5.1 1.6 2.25 1–7 0. the noise penalty due to cancellation increases because of the faster gain roll-off in the high-linearity mode.9 – 2. In the low-noise mode. 1333 ISSCC 2006 pp.1 – 10.8 9 45 38 LNA Area (mm2) 0. Measured input matching of the LNA.2 0–6 3.1 – 3. it improves with frequency in the high-linearity mode showing that the cancellation achieved is frequency dependent.7 1. 4.1 – 2.2 1. 41 ESSCIRC 2005 pp. There is little difference in the noise figures for the two modes at lower frequencies since the transistor biased in weak inversion is not placed directly at the input. oIP3 (dBm) 22 (5.6 – 10 12.8 GHz) 13 (5.3 2.2 Gain (dB) 24. not stated) 11 (2GHz) 8. Figure 6.5 – 7.1 25. Both the measured iIP3 and the de-embedded iIP3 are plotted. In the high-linearity mode. However at higher frequencies.2 – 6.6 – 4.While the iIP3 degrades with frequency in the lownoise mode. The input matching for the two modes is shown in Fig.6 3–5 2 – 5. 422 RFIC 2006 pp.4 25.25 GHz of bandwidth.8 16 NF (dB) 2.04 – 6.2 1. the noise figure increases from 2.0017 ~0.3 2.2 0.5 ~0. 5.4 The noise figure of the LNA is plotted in Fig. At 5 GHz.019 ~0. Measured input-IP3 of the LNA.2 1. S11 is lower than –11 dB at 5 GHz and better at lower frequencies in both the modes.15 90 nm CMOS Low Noise 130nm CMOS 180nm CMOS 90nm CMOS 90nm CMOS 130nm CMOS 130nm CMOS 130nm CMOS ISSCC 2007 pp. buffer.5 2 Power (mW) 42 25 9 42 9. 219 JSSC 2005 pp. In the high-linearity mode. 7.8 – 2. TABLE I PERFORMANCE COMPARISON Source This Work High Lin Process Frequency (GHz) 0.4 1.73 ~0.7 1.5 – 6.33 ~0.2 17 8 25 17.8 GHz) 12.9 dB when cancellation is applied.8 Supply (V) 2. 1983 4. it has a gain of 25.5 3. for example. 200 ISSCC 2007 pp.4 dB with 6.5 – 8.4 (3 GHz) 4.8 (5.025 0.2 0.2 GHz of bandwidth.9 (Freq. the LNA has a gain of 24.7 (Output P1dB: -8) 374 .The gains of the LNA in the two modes are plotted in Fig. 6.4 15.5 2.8GHz) 7 (5 GHz) 6. the measured iIP3 at high frequencies is limited by the non-linearity in the output buffer.

J-H C. R. “A 5GHz Resistive-Feedback CMOS LNA for Low-Cost Multi-Standard Application. 571-581. R.. pp. “A cellular-band CDMA 0. 2. 41. and J. May 1996. pp. IV. and low area requirement while consuming higher power. 2006.” Proc. G. Papers. Zhan and S. Resistive Feedback 90-nm CMOS LNA. no. Technology Colloq. N. and A. Microw. “Derivative superposition -a linearization technique for ultra broadband systems. S. iIP3 is improved by 10dB at 5GHz. Haigh. IEEE Asian Solid-State Circuits Conference (A-SSCC) 2006. ACKNOWLEDGMENT The authors would like to thank D. and K. Scott. vol.” IEEE J. Laskar. Aparin. C. When the cancellation is turned off.016 mm2. Larson. B. CONCLUSIONS [4] [5] A resistive feedback LNA is presented with non-linearity cancellation in 90 nm CMOS. R. D. Zhan. Duster for useful discussions. pp. Taylor. D.” IEE Wideband Circuits. S. die area of 0.3 dBm and a noise figure of 2. V. Carlton and J. K. Soumyanath for support and encouragement. pp. Tech. Bishop for measurement setup. 7. B. 2005. 2006.25-µm CMOS LNA linearized using active post-distortion. “A 0.” IEEE ISSCC Dig. Feb. and C.. At 5 GHz. Theory Tech. Parker. E. 1530-1534. This LNA achieves about 9 dB higher oIP3. no. Steele for layout assistance. 263266. 3/1-3/14.5-6 GHz Improved Linearity. Perumana. pp. Kim. it achieves an oIP3 of 14.3 dB. Persico. it achieves an oIP3 of 21 dBm and a noise figure of 2. Jul. REFERENCES [1] J-H. Barnett. vol. J. [3] The performance of this LNA is compared to other published results in Table 1. E.” IEEE Trans. high gain. G. Aparin and L. B.9 dB with cancellation. V. 53. It also has low noise. “Modified derivative superposition method for linearizing FET low-noise amplifiers. The LNA consumes 42 mW power and occupies an 375 . [2] Figure 7. Solid-State Circuits. Modelling. Measured noise figure of the LNA. 200-201. Taylor.