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Diode-clamped Three-Level Dual Buck Inverter

Zheng Jie
College of Information Science and
Technology
Nanjing University of Aeronautics&
Astronautics
Nanjing, China
zhengjienuaa@gmail.com
Wang Chenghua
College of Information Science and
Technology
Nanjing University of Aeronautics&
Astronautics
Nanjing, China
chwang@nuaa.edu.cn
Hong Feng
College of Information Science and
Technology
Nanjing University of Aeronautics&
Astronautics
Nanjing, China
hongfeng@nuaa.edu.cn


AbstractDual Buck inverter(DBI) is a new topology which
has the characteristics of high frequency and efficiency. But
the output voltage of the bridge is a bipolar PWM waveform
and voltage stress of the component in DBI is high, just like the
half bridge inverter. To overcome these problems, a novel
three-level DBI, which has unipolar PWM output waveforms
and low voltage stress, is presented in this paper. And the half
load-cycle operation mode of DBI is remained in it. But over-
voltage may occur if the current of inductor is discontinuous.
To solve this problem, a diode-clamped three-level DBI is
adopted, then the bridge voltage could be clamped, the volume
and weight of magnetic component are reduced at the same
time. The merits of DBI such as high efficiency and reliability
are remained at the same time. The above analyses are proved
to be true through the experimental results.
Keywords-Inverter; Three-level; Half bridge; Integrated
Magnetics
I. INTRODUCTION
The increasing concern about the available fossil fuel
reserves and the environmental aspects has given a high
impetus to the use of renewable energy sources in the present
scenario of power generation. It is a great research project to
get a high reliable and high efficiency inverter which is
suitable for photovoltaic (PV) system and other new power
systems. Dual Buck inverter (DBI)
[1-4]
is a novel topology
which has the characteristics of high frequency and
efficiency comparing with the traditional inverters. DBI
works at high reliability because that it overcomes the shoot-
through problem of the inverters. Switches and diodes of
DBI can be designed separately. High efficiency and good
dynamic performance can also be obtained when DBI works
in non-bias mode. Its excellent high frequency operational
capacity provides another way to realize high frequency and
efficiency operation of inverters. Then DBI has great value
in researches and applications. Since DBI needs both
positive and negative DC bus voltage inputs which is similar
to half bridge inverter (HBI), we call both of them as HBI in
the following discussions. Voltage stress of components in
HBI is twice as high as the maximum output voltage, as a
result, the efficiency of the system is low. Total harmonics
distortion is large due to the bipolar output voltage of bridge,
so high switching frequency or bulky filter is necessary.
Recently, The ability to endure high level voltage and
current of power semiconductors is at limit because of the
technics in manufacturing. One way to solve this problem is
to connect the switches in series, but the balance between
DC voltages is difficult to keep due to the different
parameters of components and the asynchronous of
switching. Multi-level technique by which voltage press can
be clamped to the same as the voltage of DC-link capacitor
in both steady state and transient state is a good way to solve
this problem. In addition, the filter of multi-level inverter is
much smaller than that of HBI, because of single polar
output voltage of bridge with lower harmonics distortion.
Since that, more and more researches on Multi-level
technique can be found recently.
II. THREE-LEVEL DUAL BUCK INVERTER
The topology of DBI in which two half period working
mode is adopted is shown in Fig.1(a). In the positive half
period, Buck I consists of S
1
D
1
L
1
C
f
works. In the negative
half period, Buck II consists of S
2
D
2
L
2
C
f
works, and Buck I
is suspended. Output voltage of DBI is called u
o
. Current
passing through the inductance, which is i
L1
in positive half
period and i
L2
in negative half period, is called i
L
. u
A

represents the output of Buck I in bridge A, while u
B
is the
output of Buck II in bridge B. Experimental waveforms are
shown in Fig.1(b) (t=5ms/div).

(a) Topology of DBI
(b) Typical waveforms of DBI
Fig 1.Topology of DBI and its typical waveforms
2009 International Conference on Energy and Environment Technology
978-0-7695-3819-8/09 $26.00 2009 IEEE
DOI 10.1109/ICEET.2009.269
131
Through the analysis and experimental results, we
know that there is no shoot-through problem in DBI,
and the ground of the output voltage is the same as the
input, then several DBIs can be easily connected in
parallel and adopted in three phase system. However,
there is also some drawbacks in it. Such as the voltage
stress of the components in DBI is 2U
d
assuming the
input bus voltage is U
d
. Besides the total harmonics
distortion is large due to bipolar output voltage of
bridge.
Three-Level DBI
[5-9]
which is derived from DBI is
presented in Fig.2(a). The voltage stress of this
topology is U
d
. Two half period working modes are also
adopted in it. In the positive half period, Buck I consists
of S
1
S
3
D
1
L
1
C
f
works. The current passes through the
inductance called i
L1
can be maintained when S
1
is OFF
if we keep S
3
ON during this time. While in the negative
half period, Buck II consists of S
2
S
4
D
2
L
2
C
f
works,
and Buck I is suspended. The current passes through the
inductance called i
L2
can also be maintained when S
2
is
OFF if we keep S
4
ON during this time.

(a) Topology of New three-level DBI

(b) Typical waveforms of New three-level DBI
Fig 2. New three-level DBI and its Waveforms

It is obvious that if the Buck I works, S
1
S
3
couldnt
be switched OFF at the same time, otherwise theres no
current loop for i
L1
causing the over voltage on the S
1

and S
3
. This also exists in Buck II. It can be observed
that the peak voltage exists in Fig.2(b) where u
o

represents the output voltage, i
L
is the current of
inductance, u
A
represents the output of Buck I in bridge
A while u
B
is bridge B, and the timescale is 5ms/div.
To solve these problems, we add a diode called D
clmp
to
provide the current loop for the inductance. It is discussed in
detail as follows
III. DIODE-CLAMPED THREE-LEVEL DUAL BUCK
INVERTER
Diode-clamped three-level DBI
[10]
could be built by
adding a clamped-diode between the filter inductance L
1

and L
2
for the continuous loop of the current, as shown
in Fig.3. In this topology, the voltage of bridge A(u
A
) is
equal to that of bridge B(u
B
). When Buck I works, S1
S3 turn OFF at the same time, if u
A
declined below -U
d
,
then the parasitic body diode of S
2
turns ON, u
A
and u
B

will be clamped to -U
d
. This is the same when Buck II
works. Hence the voltage of the bridge is clamped to
range of -U
d
to U
d
.

Fig 3. Diode-clamped three-level DBI


(a) Working mode I (b) Working mode II

(c) Working mode III (d) Working mode IV

(e) Working mode V (f) Working mode VI
Fig.4 Working models of diode-clamped three-level DBI
Fig.5 Key waveforms of diode-clamped three-level DBI

Working models of diode-clamped three-level DBI is
shown in Fig.4, and key waveforms of diode-clamped
132
three-level DBI is shown in Fig.5 where v
1
v
4
is the
driver of the switches S
1
S
4
and i
L1
is the current of L
1
,
i
L2
is the current of L
2
, i
L
is the summation of i
L1
and i
L2

called current of inductance. u
A
represents the voltage
of bridge A, and u
B
means that of B, the output voltage
of the inverter is u
A
or u
B
.
1. Half period when i
L
>0 [t
0
~t
1
]:
Buck I works and Buck II does not work during this
time. S
1
works in PWM mode, S
3
is ON, and S
2
, S
4
are
turned OFF. Circuit works in one of the following modes.
Mode I: Shown in Fig.4 (a). S
1
is ON, i
L1
rises linearly.
There is no current through S
3
and D
1
. Bridge output is
u
A
=+U
d.

Mode II: Shown in Fig.4 (b). S
1
turns OFF; i
L1
flows
from S
3
, D
1
and declines linearly. Bridge output is u
A
=0.

2. i
L
turns from positive to negative [t
1
~t
2
]:
Buck I and Buck II works in switch. Circuit mode is
among the mode I, II, III, IV, V and VI.
Mode III: Shown in Fig.4 (c). S
1
remains OFF, if S
3

turns OFF, then u
A
declines quickly because that i
L1
takes
out the current of the parasitic body capacitance in the
power switches. If u
A
<-U
d
, parastic body diode of S
2
is
turned ON forward due to the induction potential of u
B
.
Current loop through L
1
which declines linearly is continued
by D
clmp
and S
2
. Bridge output is u
B
=-U
d.

3. Half period when i
L
<0 [t
2
~t
3
]:
Buck II works and Buck I doesnt work. S
2
works in

PWM mode, S
4
remains ON; S
1
, S
3
are turned OFF. Circuit
works in one of following modes:
Mode IV: Shown in Fig.4 (d). S
2
is ON, i
L2
rises
linearly; there is no current in S
4
and D
2
. Bridge output u
B
is
equal to -U
d
.
Mode V: Shown in Fig.4 (e). S
2
turns OFF, i
L2
flows
from S
4
, D
2
, and declines linearly. Bridge output u
B
is 0.
4. i
L
turns from negative to positive [t
3
~t
4
]:
Buck I and Buck II works in switches. Circuit works in
mode of IV, V, VI and I, II, III.
Mode VI: Shown in Fig.4 (f). S
2
remains OFF, if S
4

turns OFF, then u
B
rises quickly because that i
L2
takes
out the current of the parasitic body capsitance in the
power switches. If u
B
>U
d
, parastic body diode of S
1
is
ON forward due to the `nduction potential of u
A
.
Current loop through L
2
which declines linearly is
continued by D
clmp
and S
1
. Bridge output is u
A
=U
d
.
It can be observed based on the analysis above that by
adding a clamped diode in the topology the bridge voltage,
u
A
and

u
B
, can be clamped in the range of [-U
d
,U
d
].
Meanwhile, the voltage stress of each power switch and
power diode is still U
d
. D
clmp
is ON during the switch time of
Buck I and Buck II. The interval is short, and the power
consumed is low.
IV. EXPERIMENTS
A 1000-VA experimental prototype was built in the
laboratory to verify the actual performance of the
clamped-diode three-level DBI, whose parameters was
that L
1
and L
2
is 125H, output capacitor C
f
is

9.4F,
input voltage U
d
is 170VDC, the output voltage u
o
is
110VAC/50HZ. Power MOSFETs (IRFP460) were used
as the controllable switching devices (S
1
, S
2
, S
3
, S
4
).
DSEI60-06A power diodes were used as D
1
and D
2
.
Experimental result is compared with that of DBI
prototype, whose parameters were the same, excepting
that L
1
and L
2
is 250H and C
f
is 14.7F. The same
power MOSFETs (IRFP460) and power diodes
(DSEI60-06A) were used for DBI.


(a) waveform of idle load (b) waveform of rating resistive
load
Fig. 6 Waves of coupled-inductance three-level DBI

Experimental waveforms are shown in Fig.6 where -
u
A
is channel 1(200V/div), u
o
is channel 2(200V/div), -
u
B
is channel 3(200V/div), i
L
is channel 4(5A/div) and
the timescale is 5ms/div. Fig.6(a) is the waveform of
idle load and Fig. 6(b) is the waveform of rating
resistive load. Experimental waveform verifies the
above analysis.

0.b
0.
0.8
0.9
!
! 3 9 !!
Outut Cuut ^
l

)
DbT
th
'v'
Fig. 7 Comparison of efficiency between DBI and clamped-
diode three-level DBI
0
0.
!
!.
?
! 3 9 !!
Outut Cuut ^
T
|
D
DbT
th
'v'
Fig. 8 Comparison of output voltage THD between DBI and
clamped-diode three-level DBI

Comparisons of efficiency and THD between DBI and
clamped-diode three-level DBI are shown in Fig.7 and Fig 8.
It is worth while to note that almost same performance can
be reached, but inductance of three-level DBI is smaller than
that of DBI.
133
V. CONCLUSION
In this paper, the importance of improvement on DBI has
been highlighted. Three level DBI topologies, especially the
clamped-diode three-level DBI have been proposed.
Relevant analysis, including working modes analysis of
proposed inverter and comparison between proposed inverter
and DBI, has been presented. Advantages of DBI, such as
high reliability and high efficiency, are inherited by
clamped-diode three-level DBI. By adding a diode to clamp
the voltage, bridge output became to three-level, and
harmonious was much smaller than that of DBI. Simulation
and experiments with a laboratory prototype have verified
the above conclusions.
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