AL-Falah School of Engineering & Technology (An Autonomous Institute

)

VLSI Design Lab

M.Tech VLSI Design Department of Electronics & Communication Engineering AL-Falah School of Engineering & Technology Dhauj Faridabad Haryana India

AL-Falah School of Engineering & Technology A

Page 1

AL-Falah School of Engineering & Technology (An Autonomous Institute)

L-T-P 0-0-3

Int 50

Ext Total 100 150

Code: MEVLSI-511 Paper: VLSI Design Lab

List of experiments using Tanner Tools
1. Design the layout for PMOS in layout editor. 2. Design the layout for NMOS in layout editor. 3. Design the layout for CMOS inverter with equal rise and fall time in layout editor. 4. Design the layout for 2-lnput AND 3-lnput NOR gate in layout editor. 5. Design the layout for 2-lnput and 3-lnput NAND gate in layout editor. 6. Design the layout for 2-lnput and 3-lnput Ex-OR gate in layout editor. 7. Design the layout for 2-lnput and 3-lnput Ex-NOR gate in layout editor. 8. Design the layout for clocked S-R flip-flop in layout editor.

Note: The Scheme of awarding the grades to a student in the course will be supplied by the University to the examiner. Teachers are allowed to perform other experiments relevant to the lab.

AL-Falah School of Engineering & Technology A

Page 2

AL-Falah School of Engineering & Technology (An Autonomous Institute)

INDEX
S.No. 1. 2. 3. 7. 8. 9. (a) (b) (c) (d) (e) (f) (g) (h) TITLE Integrated Circuit Layout Integrated Circuit Design Tanner IC Work Flow L-EDIT LVS (Layout Vs Schematic) Layout Examples Nand Gate Nor Gate Transmission Gate Xor Gate using TX gate Xnor Gate 4*1 Multiplexer Full Adder Parallel Adder Page No. 4 5 10 12 27 29 29 30 32 33 35 37 39 42

AL-Falah School of Engineering & Technology A

Page 3

AL-Falah School of Engineering & Technology (An Autonomous Institute)

Integrated Circuit Layout
Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors.

Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. When using a standard process - where the interaction of the many chemical, thermal, and photographic variables are known and carefully controlled - the behavior of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. A layout engineer's job is to place and connect all the components that make up a chip so that they meet all criteria. Typical goals are performance, size, and manufacturability. The layout must pass a series of checks in a process known as verification. The two most common checks in the verification process are Design Rule Checking (DRC), and Layout Versus Schematic (LVS). When all verification is complete the data is translated into an industry standard format, typically GDSII, and sent to a semiconductor foundry. The process of sending this data to the foundry is called tapeout due to the fact the data used to be shipped out on a magnetic tape. The foundry converts the data into another format and uses it to generate the photomasks used in a photolithographic process of semiconductor device fabrication. In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, much like the early days of PCB design. Modern IC Layout is done with the aid of IC layout editor software, or even automatically using EDA tools, including place and route tools or schematic driven layout tools. The manual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing".

AL-Falah School of Engineering & Technology A

Page 4

as well as market pressure to produce designs rapidly. The rules for what can and cannot be manufactured are also extremely complex. in order to achieve the desired speed of operation. and resistance. An IC process as of 2006 may well have more than 600 rules. ICs consist of miniaturized electronic components built into an electrical network on a monolithic semiconductor substrate by photolithography. is a subset of electrical engineering. as of 2006. Analog IC design is used in the design of op-amps. the physical layout of certain circuit subblocks is typically critical. Design steps A typical IC design cycle involves several steps: 1. and placing circuits so that clock and timing signals are routed efficiently. The two common methods are p-n junction isolation and dielectric isolation. or ICs. Furthermore. Finally. contacts and vias since ICs contain very tiny devices compared to discrete components. analog ICs use larger area active devices than digital designs and are usually less dense in circuitry.AL-Falah School of Engineering & Technology (An Autonomous Institute) Integrated circuit design Integrated circuit design. The complexity of modern IC design. Attention must be given to power dissipation of transistors and interconnect resistances and current density of the interconnect. to segregate noisy portions of an IC from quiet portions. In short. maximizing circuit density. ROM. and verification of the instructions that the IC is to carry out. Digital design focuses on logical correctness. since the manufacturing process itself is not completely predictable. A large chip. test. typically silicon. 3. may well have more transistors than there are people on Earth. encompassing the particular logic and circuit design techniques required to design integrated circuits. 2. Feasibility study and die size estimate Functional verification Circuit/RTL design Circuit/RTL simulation Logic simulation Page 5 AL-Falah School of Engineering & Technology A . Analog IC design also has specializations in power IC design and RF IC design. where such concerns are less of an issue. phase locked loops. such as transistors. Fidelity of analog signal amplification and filtering is usually critical and as a result. power dissipation. Modern ICs are enormously complicated. has led to the extensive use of automated design tools in the IC design process. Analog design is more concerned with the physics of the semiconductor devices such as gain. designers must account for its statistical nature. or to facilitate the placement of connections to circuitry outside the IC. FPGAs. to balance the effects of heat generation across the IC. matching. resistors. Digital IC design is used to produce components such as microprocessors. linear regulators. IC design can be divided into the broad categories of digital and analog IC design. 4. capacitors and the metallic interconnect of these components onto a piece of semiconductor. and flash) and digital ASICs. A method to isolate the individual components formed in the substrate is necessary since the substrate silicon is conductive and often forms an active region of the individual components. memories (RAM. Fundamentals Integrated circuit design involves the creation of electronic components. oscillators and active filters. or IC design. the design of an IC using EDA software is the design. Electromigration in metallic interconnect and ESD damage to the tiny components are also of concern.

Ramp up 22. Datasheet generation Portable Document Format 21. Examples include a C/C++ model. lint-like code checking. RTL design This is the hardest part. and the domain of functional verification. defining places for them. Post silicon validation 18. hardware emulation. Floorplanning 6. Wafer fabrication 15. none of them perfect but all of them useful – extensive logic simulation. formal methods. and wiring them together. RTL design. Design for manufacturability (IC) 13. AL-Falah School of Engineering & Technology A Page 6 . and a library of available logic gates. Layout review 11. Each of these innocent looking statements expands to hundreds of pages of text. Static timing analysis 10. Layout 8. does not affect the functionality at all (if done correctly) but determines how fast the chip operates and how much it costs. physical design. plan for next generation chip using production information if possible Digital design Roughly speaking. The RTL describes the exact behavior of the digital circuits on the chip. Yield Analysis / Warranty Analysis Reliability (semiconductor) 24. as well as the interconnections to inputs and outputs. This involves figuring out which gates to use. It is extremely difficult to verify that the RTL will do the right thing in all the possible cases that the user may throw at it. and creates a chip design. The spec may have some terse description. SystemC. and thousands of lines of computer code. Design For Test and Automatic test pattern generation 12. Tweak (if necessary) 20. Note that the second step. and so on. Design review 7. RTL design: This step converts the user specification (what the user wants the chip to do) into a register transfer level (RTL) description. The third step. such as encodes in the MP3 format or implements IEEE floating-point arithmetic. The user may use a variety of languages and tools to create this description. Packaging 17. Die test 16. Production 23. is responsible for the chip doing the right thing. Physical design: This step takes the RTL. SystemVerilog Transaction Level Models. Many techniques are used.AL-Falah School of Engineering & Technology (An Autonomous Institute) 5. Layout verification 9. digital IC design can be divided into three parts    ESL design: This step creates the user functional specification. Mask data preparation 14. Device characterization 19. Failure analysis on any returns 25.

In practice there is not a straightforward progression considerable iteration is required to ensure all objectives are met simultaneously. cores. Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints. called design closure. to make it as easy and efficient as possible to produce. Design for manufacturability: The design is modified. Routing: The wires that connect the gates in the netlist are added. Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.) are placed. This is achieved by adding extra vias or adding dummy metal/diffusion/poly layers wherever possible while complying to the design rules set by the foundry. in cases that occurred very infrequently. No one even noticed it until the chip had been in production for months. noise (Signal Integrity). where possible.           Floorplanning: The RTL of the chip is assigned to gross regions of the chip. Physical design Here are the main steps of physical design.AL-Falah School of Engineering & Technology (An Autonomous Institute) A tiny error here can make the whole chip useless. at a cost of $475 million (US). time consuming and hard to spot. extensive error checking is the rule. This is a difficult problem in its own right. Placement: The gates in the netlist are assigned to nonoverlapping locations on the die area. Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip. AL-Falah School of Engineering & Technology A Page 7 . etc. and yield (Design for Manufacturability) violations are removed. The famous Pentium FDIV bug caused the results of a division to be wrong by at most 61 parts per million. making sure the mapping to logic was done correctly. input/output (I/O) pins are assigned and large objects (arrays. for free. Postwiring optimization: Remaining performance (Timing Closure). Yet Intel was forced to offer to replace. or worse. and checking that the manufacturing rules were followed faithfully. every chip sold until they could fix the bug. Clock insertion: Balanced buffered clock trees are introduced into the design. Final checking: Since errors are expensive.

The first circuit simulator for analog ICs was called SPICE (Simulation Program with Integrated Circuits Emphasis). The computerized circuit simulators also enable mistakes to be found early in the design cycle before a physical device is fabricated. doping concentration variation and statistical process variations can be simulated easily to determine if an IC design is manufacturable. Reuse of proven designs allowed progressively more complicated ICs to be built upon prior knowledge. computerized circuit simulation enables a higher degree of confidence that the circuit will work as expected upon manufacture. These ICs were basic circuits. computer programs were written to simulate circuit designs with greater accuracy than practical by hand calculation. Computerized circuit simulation tools enable greater IC design complexity than hand calculations can achieve. a computerized circuit simulator can implement more sophisticated device models and circuit analysis too tedious for hand calculations. making the design of analog ASICs practical. Additionally. The effects of parameters such as temperature variation. Overall. AL-Falah School of Engineering & Technology A Page 8 . op-amps are one example. An iterative trial-and-error process and "overengineering" of device size was often necessary to achieve a manufacturable IC. permitting Monte Carlo analysis and process sensitivity analysis to be practical. A simple CMOS Operational Amplifier Layout Analog design Before the advent of the microprocessor and software based design tools. usually involving no more than ten transistors and few connections.AL-Falah School of Engineering & Technology (An Autonomous Institute) Process corners Process corners provide digital designers the ability to simulate the circuit while accounting for variations in the technology process. analog ICs were designed using hand calculations. When inexpensive computer processing became available in the 1970s.

Slight changes to the amount of diffusion time. which do match closely. To add to the design challenge. can have large effects on device properties. Device properties can even vary significantly across each individual IC due to doping gradients. Fortunately for IC design. Making devices large so that statistical variations becomes an insignificant fraction of the overall device property. For example. Using common centroid device layout to cancel variations in devices which must match closely (such as the transistor differential pair of an op amp). The design techniques necessary to reduce the effects of the device variation are:      Using the ratios of resistors. uneven doping levels. into parts and interweaving them to cancel variations. However. rather than absolute resistor value. AL-Falah School of Engineering & Technology A Page 9 . Segmenting large devices. this fabrication variability forces certain design techniques and prevents the use of other design techniques familiar to the board-level designer. Unlike board-level circuit design which permits the designer to select devices that have each been tested and binned according to value. device properties often vary between each processed semiconductor wafer. such as resistors. etc. the device values on an IC can vary widely which are uncontrollable by the designer. The underlying cause of this variability is that many semiconductor devices are highly sensitive to uncontrollable random variances in the process. Using devices with matched geometrical shapes so they have matched variations. the absolute values of the devices are less critical than the identical matching of device performance.AL-Falah School of Engineering & Technology (An Autonomous Institute) Coping with variability A challenge most critical to analog IC design involves the variability of the individual devices built on the semiconductor chip. some IC resistors can vary ±20% and β of an integrated BJT can vary from 20 to 100.

placement and routing.AL-Falah School of Engineering & Technology (An Autonomous Institute) Tanner IC Work Flow Tanner Tools are fully-integrated solutions consisting of tools for schematic entry. AL-Falah School of Engineering & Technology A Page 10 . LVS and design rule checking (DRC) verification. circuit simulation. full-custom layout editing. waveform probing. netlist extraction.

5. making sure L-EDIT generates the parasitic capacitances so they are included in the simulation. 2. Simulate the schematic to make sure it behaves as you expect using T-SPICE. AL-Falah School of Engineering & Technology A Page 11 . 3. What follows is a brief overview of the steps. Simulate the layout using T-SPICE with a high-level spice model. There are four basic steps: 1. 4. Perform an LVS (Layout VS Schematic) to make sure your layout is functionally the same as the schematic you designed in S-EDIT. Design the schematic in S-EDIT.AL-Falah School of Engineering & Technology (An Autonomous Institute) Introduction This document gives a rough overview of how to design & simulate things with Tanner Tools. Layout the schematic in L-EDIT.

AL-Falah School of Engineering & Technology (An Autonomous Institute) L-EDIT CMOS Inverter Structure: - Double click on L-Edit. File -> new AL-Falah School of Engineering & Technology A Page 12 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Now copy TDB (Tanner Data Base) file from browse Path for TDB File C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and LVS\Tech\Mosis\morbn20.tdb And Click OK Goto cell -> new AL-Falah School of Engineering & Technology A Page 13 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Name the cell-> Grids spacing can be minimized or maximized using – or + sign To change the technology Goto setup-> Design AL-Falah School of Engineering & Technology A Page 14 .

(2) From layer palette. we can select layer then for drawing layer we need to switch at Drawing boxes as follows Now we can start layout designing We are Taking Example of CMOS Layout design Background of L-Edit is P-Substrate by default We need to design PMOS.AL-Falah School of Engineering & Technology (An Autonomous Institute) Select Lambda or microns accordingly and click ok Before designing layout we need to remember following equations N Diffusion = N select and Active – (1) P Diffusion = P select and Active . First draw active AL-Falah School of Engineering & Technology A Page 15 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Now draw P select over Active with keeping in mind Lambda based design rules Now draw poly over it accordingly Now draw metal1 to design Contact AL-Falah School of Engineering & Technology A Page 16 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Now draw Active Contact for Active region We have designed source. gate and drain Now we need to put this in N-Well We can perform DRC (Design Rule Check) at every stage AL-Falah School of Engineering & Technology A Page 17 .

as follows It is called lens. now we need to edit N-well We can check DRC at every stage AL-Falah School of Engineering & Technology A Page 18 . it will be shown in corresponding layout.AL-Falah School of Engineering & Technology (An Autonomous Institute) If we are violating any Design rule then it will be shown in Error verification navigator On pointing any error.

we need to draw Poly contact To define port. we need to design Gate contact In case of Poly Layer. go to (A) AL-Falah School of Engineering & Technology A Page 19 .AL-Falah School of Engineering & Technology (An Autonomous Institute) Now we need to draw Body terminal. Gate contact After designing Body terminal (n select+ active+metal1+active contact).

AL-Falah School of Engineering & Technology A Page 20 .AL-Falah School of Engineering & Technology (An Autonomous Institute) Type the name of port.

and after connecting these two.AL-Falah School of Engineering & Technology (An Autonomous Institute) Similarly we can design N MOS. CMOS layout will look like as follows AL-Falah School of Engineering & Technology A Page 21 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Now we can extract netlist by doing some settings AL-Falah School of Engineering & Technology A Page 22 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Now select Extract standard rule set.ext AL-Falah School of Engineering & Technology A Page 23 .0\L-Edit and LVS\Tech\Mosis\morbn20. and click on pencil Now we need to include Extract file.ext file is C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13. and Spice output file at desired location Location for .

select Names (writing nodes) Click ok.AL-Falah School of Engineering & Technology (An Autonomous Institute) Define location for output files In output. now go to extract button AL-Falah School of Engineering & Technology A Page 24 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Click on extract.md file for analysis AL-Falah School of Engineering & Technology A Page 25 . An spice file will open as follows We can open this spice file in T-Spice and can perform desired analysis We need to include hp05.

PRINT TRAN V(vin) .tran 1ns 500ns After saving spice file. W-Edit will invoked and we can check the response: AL-Falah School of Engineering & Technology A Page 26 .AL-Falah School of Engineering & Technology (An Autonomous Institute) We need to insert some spice commands to perform transient analysis : VVoltageSource_1 Vdd Gnd DC 5 VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n) .PRINT TRAN V(vout) . we can simulate it.

Now we can compare results by using LVS Double click on LVS.AL-Falah School of Engineering & Technology (An Autonomous Institute) LVS (Layout Vs Schematic) We got two output files (one from S-Edit and second from L-Edit). and file -> new & Select file type-> LVS setup. then ok AL-Falah School of Engineering & Technology A Page 27 .

AL-Falah School of Engineering & Technology (An Autonomous Institute) We need to browse spice netlist files for layout netlist and Schematic netlist After including these files. AL-Falah School of Engineering & Technology A Page 28 . we need to run verification as follows & Results can be checked from Verification Window. Both netlists are equal.

include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.END AL-Falah School of Engineering & Technology A Page 29 .print tran v(1) v(a) v(b) .0\hp05.75u vdd vdd gnd 5 Va a gnd PULSE (0 5 0 100n 300n 3u 6u) Vb b gnd PULSE (0 5 0 100n 300n 6u 12u) . NAND gate: NAND gate layout Spice File: .tran .75u M2 vdd b 1 7 PMOS L=1u W=2.1u 100u .AL-Falah School of Engineering & Technology (An Autonomous Institute) LAYOUT EXAMPLES: 1.75u M3 5 a gnd 4 NMOS L=1u W=2.75u M4 1 b 5 4 NMOS L=1u W=2.md" M1 1 a vdd 7 PMOS L=1u W=2.

AL-Falah School of Engineering & Technology (An Autonomous Institute) Waveform: 2. NOR Gate: AL-Falah School of Engineering & Technology A Page 30 .

0\hp05.75u M2 gnd b outputa 7 NMOS L=1u W=2.75u M4 outputa b 5 4 PMOS L=1u W=2.AL-Falah School of Engineering & Technology (An Autonomous Institute) Spice File: .1u 100u .print tran v(outputa) v(a) v(b) .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.END Waveform: AL-Falah School of Engineering & Technology A Page 31 .75u M3 5 a vdd 4 PMOS L=1u W=2.md" M1 outputa a gnd 7 NMOS L=1u W=2.tran .75u vdd vdd gnd 5 Va a gnd PULSE (0 5 0 100n 300n 3u 6u) Vb b gnd PULSE (0 5 0 100n 300n 6u 12u) .

5u M2 out a in 3 NMOS L=1u W=2.md" M1 out a in 4 PMOS L=1u W=2.AL-Falah School of Engineering & Technology (An Autonomous Institute) 3.1u 40u .END Waveform: AL-Falah School of Engineering & Technology A Page 32 .0\hp05.5u vdd vdd gnd 5v Vin in gnd PULSE (0 5 0 1u 1u 4u 10u) Va a gnd PULSE (0 5 0 1u 1u 4u 10u) .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.print in out .tran . TRANSMISSION GATE: Spice File: .

75u M3 inta a vdd 7 PMOS L=1u W=2.75u M2 outputa b a 8 PMOS L=1u W=2.md" M1 outputa bbar inta 10 PMOS L=1u W=2.0\hp05.5u M4 outputa bbar a 6 NMOS L=1u W=3u M5 outputa b inta 6 NMOS L=1u W=3u M6 inta a 4 6 NMOS L=1u W=3u vdd vdd gnd 5v Va a gnd PULSE (0 5 0 1u 1u 4u 10u) Vb b gnd PULSE (0 5 0 1u 1u 4u 10u) Vbbar bbar gnd PULSE (5 5 0 1u 1u 4u 10u) .print a bbar outputa . XOR GATE USING TX GATES Spice File: .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.END AL-Falah School of Engineering & Technology A Page 33 .AL-Falah School of Engineering & Technology (An Autonomous Institute) 4.1u 40u .tran .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Waveform: AL-Falah School of Engineering & Technology A Page 34 .

0\hp05.END AL-Falah School of Engineering & Technology A Page 35 .AL-Falah School of Engineering & Technology (An Autonomous Institute) 5.75u M2 3 a vdd 9 PMOS L=1u W=2.5u M3 out bbar a 7 PMOS L=1u W=2.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.md" M1 out b 3 10 PMOS L=1u W=2.75u M4 out b a 6 NMOS L=1u W=3u M5 3 a gnd 6 NMOS L=1u W=3u M6 out bbar 3 6 NMOS L=1u W=3u vdd vdd gnd 5 Va a gnd PULSE (0 5 0 1u 1u 4u 10u) Vb b gnd PULSE (0 5 0 1u 1u 4u 10u) Vbbar bbar gnd PULSE (5 5 0 1u 1u 4u 10u) .1u 40u . XNOR GATE Spice File: .tran .print a bbar out .

AL-Falah School of Engineering & Technology (An Autonomous Institute) Waveform: AL-Falah School of Engineering & Technology A Page 36 .

4X1 MUX Spice File: .AL-Falah School of Engineering & Technology (An Autonomous Institute) 6.0\hp05.md" M1 out s2 16 9 PMOS L=1u W=5u M2 16 s1 B 7 PMOS L=1u W=5u M3 out s2bar 1 5 PMOS L=1u W=5u M4 1 s1bar A 3 PMOS L=1u W=5u M5 out s2 1 23 NMOS L=1u W=5u M6 1 s1 A 23 NMOS L=1u W=5u M7 out s2 11 31 PMOS L=1u W=5u M8 11 s1bar D 29 PMOS L=1u W=5u M9 out s2bar 14 27 PMOS L=1u W=5u M10 14 s1 C 25 PMOS L=1u W=5u M11 out s2bar 11 23 NMOS L=1u W=5u M12 11 s1 D 23 NMOS L=1u W=5u M13 out s2 14 23 NMOS L=1u W=5u M14 14 s1bar C 23 NMOS L=1u W=5u M15 out s2bar 16 23 NMOS L=1u W=5u M16 16 s1bar B 23 NMOS L=1u W=5u Va a gnd PULSE (0 5 0 0 0 2u 4u) Vb b gnd PULSE (0 5 0 0 0 4u 8u) Vc c gnd PULSE (0 5 0 0 0 8u 16u) AL-Falah School of Engineering & Technology A Page 37 .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.

tran .print v(s1) v(s2) v(out) .AL-Falah School of Engineering & Technology (An Autonomous Institute) Vd d gnd PULSE (0 5 0 0 0 16u 32u) Vs1 s1 gnd PULSE (0 5 0 0 0 16u 32u) Vs1bar s1bar gnd PULSE (0 5 16u 0 0 16u 32u) Vs2bar s2bar gnd PULSE (0 5 32u 0 0 32u 64u) Vs2 s2 gnd PULSE (0 5 0 0 0 32u 64u) .1u 200u .END Waveform AL-Falah School of Engineering & Technology A Page 38 .

FULL ADDER AL-Falah School of Engineering & Technology A Page 39 .AL-Falah School of Engineering & Technology (An Autonomous Institute) 7.

25p PS=8.5p PS=4u M24 11 b gnd 16 NMOS L=1u W=3u AD=7.25p PS=8.5p PS=8u M14 2 12 14 16 NMOS L=1u W=3u AD=7.5p PS=4u M17 13 b vdd 20 PMOS L=1u W=3u AD=7.5p PS=8u M13 S0 2 gnd 16 NMOS L=1u W=3u AD=12.5p PD=4u AS=7.5p PD=8u AS=7.5u M3 6 b 5 20 PMOS L=1u W=3u AD=1.5p PS=8u M27 gnd a 11 16 NMOS L=1u W=3u AD=7.5p PS=8u M26 15 a 12 16 NMOS L=1u W=3u AD=1.5p PS=4u M11 gnd b 14 16 NMOS L=1u W=3u AD=8.5p PS=8u M25 14 a gnd 16 NMOS L=1u W=3u AD=7.5p PS=8u M6 S0 2 vdd 20 PMOS L=1u W=3u AD=12p PD=14u AS=7.5u AS=7.5p PS=4u M9 14 c gnd 16 NMOS L=1u W=3u AD=7.5p PD=4u AS=7.5p PD=8u AS=1.5p PD=4u AS=7.md" M1 vdd c 6 20 PMOS L=1u W=3u AD=7.25p PD=8.5p PD=8u AS=7.AL-Falah School of Engineering & Technology (An Autonomous Institute) Spice File: .5p PD=8u AS=12p PS=14u M28 gnd 12 carry 16 NMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u vdd vdd gnd 5v .5u AS=7.5p PS=8u M20 vdd a 13 20 PMOS L=1u W=3u AD=7.5p PS=8u M8 gnd c 4 16 NMOS L=1u W=3u AD=7.5p PD=8u AS=8.5p PD=8u AS=1.25p PD=8.5p PS=8u M15 12 c 13 20 PMOS L=1u W=3u AD=7.tran 1m 100m va a gnd 0v vb b gnd 5v vc c gnd 5v .print tran v(a) v(s0) v(carry) .5p PD=4u AS=1.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.75p PD=14.end AL-Falah School of Engineering & Technology A Page 40 .0\hp05.5p PD=8u AS=7.5p PD=8u AS=1.5p PD=8u AS=7.5p PS=8u M12 3 a 2 16 NMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PS=8u M19 19 a 12 20 PMOS L=1u W=3u AD=1.5p PS=8u M23 gnd b 15 16 NMOS L=1u W=3u AD=7.5p PD=4u AS=1.5p PD=8u AS=7.5p PD=8u AS=8.5p PD=8u AS=7.5p PS=4u M4 vdd b 17 20 PMOS L=1u W=3u AD=8.5p PD=4u AS=7.5u M10 4 b 3 16 NMOS L=1u W=3u AD=1.5p PS=8u M16 vdd b 19 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M21 vdd 12 carry 20 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M22 12 c 11 16 NMOS L=1u W=3u AD=7.5p PS=8u M18 17 a vdd 20 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=1.5u AS=7.5p PS=8u M7 2 12 17 20 PMOS L=1u W=3u AD=7.5p PS=4u M2 17 c vdd 20 PMOS L=1u W=3u AD=7.5p PS=8u M5 5 a 2 20 PMOS L=1u W=3u AD=1.

AL-Falah School of Engineering & Technology (An Autonomous Institute) Waveform AL-Falah School of Engineering & Technology A Page 41 .

5u AS=7.5p PD=4u AS=7.5p PS=8u M18 vdd a0 11 22 PMOS L=1u W=3u AD=7. Four Bit Parallel Adder Spice File: .5p PD=8u AS=1.5p PD=4u AS=1.25p PD=8.5p PS=8u M12 16 c 11 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.25p PD=8.5p PS=8u M21 gnd b0 8 69 NMOS L=1u W=3u AD=8.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\Tanner Tools v13.25p PD=8.5p PS=8u M20 16 c 9 69 NMOS L=1u W=3u AD=7.5p PS=8u M10 2 16 8 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=8.5p PS=8u M17 14 a0 16 22 PMOS L=1u W=3u AD=1.5p PS=8u M6 gnd c 4 69 NMOS L=1u W=3u AD=7.5p PS=4u M7 4 b0 3 69 NMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PS=8u M26 gnd a0 9 69 NMOS L=1u W=3u AD=7.25p PD=8.5p PD=4u AS=1.5p PS=8u M22 gnd b0 12 69 NMOS L=1u W=3u AD=7.5p PS=8u M4 s0 2 vdd 22 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8u M9 s0 2 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=4u AS=7.5u AS=7.5p PD=8u AS=1.md" M1 vdd c 6 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PD=8u AS=7.5p PS=8u M5 2 16 10 22 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M27 vdd c0 23 35 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M19 gnd c 8 69 NMOS L=1u W=3u AD=8.5p PD=8u AS=7.5p PS=8u M16 10 a0 vdd 22 PMOS L=1u W=3u AD=7.5p PS=4u M3 5 a0 2 22 PMOS L=1u W=3u AD=1.5u M29 vdd 16 c0 22 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u AL-Falah School of Engineering & Technology A Page 42 .5p PS=4u M23 9 b0 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=7.5p PD=8u AS=1.5u AS=7.25p PS=8.AL-Falah School of Engineering & Technology (An Autonomous Institute) 8.5p PS=8u M14 vdd b0 14 22 PMOS L=1u W=3u AD=7.5p PS=8u M11 vdd c 10 22 PMOS L=1u W=3u AD=8.5p PD=8u AS=7.5p PS=8u M13 vdd b0 10 22 PMOS L=1u W=3u AD=8.5p PS=4u M8 3 a0 2 69 NMOS L=1u W=3u AD=1.5p PD=8u AS=1.5p PS=4u M2 6 b0 5 22 PMOS L=1u W=3u AD=1.5p PS=4u M28 28 c0 vdd 35 PMOS L=1u W=3u AD=7.5p PS=8u M24 8 a0 gnd 69 NMOS L=1u W=3u AD=7.0\hp05.5p PD=4u AS=7.5p PD=8u AS=7.5p PS=8u M25 12 a0 16 69 NMOS L=1u W=3u AD=1.5u AS=7.5p PS=4u M15 11 b0 vdd 22 PMOS L=1u W=3u AD=7.5p PD=4u AS=7.

5p PD=4u AS=1.25p PS=8.5p PD=8u AS=7.5u AS=7.5p PS=8u M40 17 27 25 69 NMOS L=1u W=3u AD=7.5p PS=8u M53 25 a1 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M74 50 a2 44 54 PMOS L=1u W=3u AD=1.5p PD=4u AS=7.5p PD=4u AS=7.5p PD=8u AS=1.5p PD=8u AS=1.5p PD=8u AS=7.5p PD=8u AS=12p PS=14u M76 vdd 44 c2 54 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M77 44 c1 43 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=7.5p PD=8u AS=7.5p PD=8u AS=7.5p PD=8u AS=8.5p PS=8u M71 vdd b2 50 54 PMOS L=1u W=3u AD=7.5p PS=4u M35 25 c0 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M62 34 44 45 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=8.5p PD=4u AS=7.5p PS=8u M50 gnd b1 25 69 NMOS L=1u W=3u AD=8.5p PS=4u M60 39 a2 34 54 PMOS L=1u W=3u AD=1.5p PS=8u M42 vdd b1 28 35 PMOS L=1u W=3u AD=8.5p PD=8u AS=7.5p PS=8u M51 gnd b1 30 69 NMOS L=1u W=3u AD=7.5p PS=8u M73 45 a2 vdd 54 PMOS L=1u W=3u AD=7.5p PD=15u AS=12p PS=14u M57 vdd c1 40 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=8u M70 vdd b2 45 54 PMOS L=1u W=3u AD=8.5p PS=4u M38 19 a1 17 69 NMOS L=1u W=3u AD=1.5p PS=4u M66 37 a2 34 69 NMOS L=1u W=3u AD=1.5p PS=8u M69 44 c1 46 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PS=4u M44 29 b1 vdd 35 PMOS L=1u W=3u AD=7.5p PS=8u M32 s1 17 vdd 35 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8u M55 gnd a1 26 69 NMOS L=1u W=3u AD=7.25p PD=8.5u M59 40 b2 39 54 PMOS L=1u W=3u AD=1.5p PS=8u M67 s2 34 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=8u M63 gnd c1 38 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=1.5u M36 gnd 16 c0 69 NMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M37 20 b1 19 69 NMOS L=1u W=3u AD=1.25p PD=8.25p PS=8.25p PS=8.5p PS=4u M64 42 c1 gnd 69 NMOS L=1u W=3u AD=7.5p PS=4u M58 45 c1 vdd 54 PMOS L=1u W=3u AD=7.5p PS=4u M52 26 b1 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M47 vdd a1 29 35 PMOS L=1u W=3u AD=7.5p PS=8u M39 s1 17 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=8u AS=12p PS=14u M48 vdd 27 c1 35 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M49 27 c0 26 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=1.5p PD=8u AS=12p PS=14u M56 gnd 27 c1 69 NMOS L=1u W=3u AD=13.5p PD=4u AS=1.5p PS=8u M54 30 a1 27 69 NMOS L=1u W=3u AD=1.5p PD=8u AS=1.5p PS=8u M43 vdd b1 32 35 PMOS L=1u W=3u AD=7.5p PS=8u M68 34 44 42 69 NMOS L=1u W=3u AD=7.5p PS=8u M45 28 a1 vdd 35 PMOS L=1u W=3u AD=7.5u AS=7.5p PD=8u AS=7.5p PS=8u M33 17 27 28 35 PMOS L=1u W=3u AD=7.5p PS=8u M46 32 a1 27 35 PMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PD=4u AS=7.5p PD=4u AS=7.5p PD=8u AS=7.5p PS=8u AL-Falah School of Engineering & Technology A Page 43 .5p PS=4u M72 46 b2 vdd 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.AL-Falah School of Engineering & Technology (An Autonomous Institute) M30 23 b1 21 35 PMOS L=1u W=3u AD=1.5p PS=4u M31 21 a1 17 35 PMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PD=8u AS=8.5p PS=8u M61 s2 34 vdd 54 PMOS L=1u W=3u AD=12p PD=14u AS=7.5u M65 38 b2 37 69 NMOS L=1u W=3u AD=1.5p PD=8u AS=7.5p PD=4u AS=7.5p PD=4u AS=7.5p PD=8u AS=7.5p PS=8u M34 gnd c0 20 69 NMOS L=1u W=3u AD=7.25p PD=8.5p PS=8u M41 27 c0 29 35 PMOS L=1u W=3u AD=7.5u AS=7.5p PS=8u M75 vdd a2 46 54 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.

5p PS=4u M80 43 b2 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=12p PS=14u M84 gnd 44 c2 69 NMOS L=1u W=3u AD=15p PD=16u AS=12p PS=14u M85 vdd c2 60 72 PMOS L=1u W=3u AD=7.5p PS=8u M107 gnd b3 68 69 NMOS L=1u W=3u AD=7.AL-Falah School of Engineering & Technology (An Autonomous Institute) M78 gnd b2 42 69 NMOS L=1u W=3u AD=8.5u AS=7.5p PS=8u M103 71 a3 63 72 PMOS L=1u W=3u AD=1.5p PD=15u AS=12p PS=14u vdd vdd gnd 5v .5p PS=8u M100 vdd b3 71 72 PMOS L=1u W=3u AD=7.5p PS=4u M108 62 b3 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=4u AS=1.5p PD=8u AS=12p PS=14u M105 vdd 63 c3 72 PMOS L=1u W=3u AD=12p PD=14u AS=12p PS=14u M106 63 c2 62 69 NMOS L=1u W=3u AD=7.5p PS=8u M110 68 a3 63 69 NMOS L=1u W=3u AD=1.5p PS=8u M79 gnd b2 47 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5u M94 58 b3 57 69 NMOS L=1u W=3u AD=1.5p PS=8u M90 s3 53 vdd 72 PMOS L=1u W=3u AD=12p PD=14u AS=7.5p PD=4u AS=7.5u AS=7.5p PD=8u AS=8.5p PD=8u AS=7.5p PS=8u M81 42 a2 gnd 69 NMOS L=1u W=3u AD=7.5p PS=8u M109 61 a3 gnd 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=7.5p PD=8u AS=7.5p PS=8u M89 59 a3 53 72 PMOS L=1u W=3u AD=1.5p PS=8u M91 53 63 64 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=4u AS=7.5p PS=8u M96 57 a3 53 69 NMOS L=1u W=3u AD=1.5p PS=4u M101 65 b3 vdd 72 PMOS L=1u W=3u AD=7.5u AS=7.5p PS=8u M98 53 63 61 69 NMOS L=1u W=3u AD=7.25p PD=8.25p PD=8.5p PD=8u AS=7.5p PD=8u AS=7.5p PS=8u M111 gnd a3 62 69 NMOS L=1u W=3u AD=7.5p PD=4u AS=7.5p PS=4u M86 64 c2 vdd 72 PMOS L=1u W=3u AD=7.5p PS=4u M93 61 c2 gnd 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=7.5p PD=8u AS=1.5p PD=4u AS=7.5p PD=8u AS=7.5p PS=8u M97 s3 53 gnd 69 NMOS L=1u W=3u AD=12p PD=14u AS=7.5p PS=4u M95 gnd b3 61 69 NMOS L=1u W=3u AD=8.tran 1m 100m va0 a0 gnd 0v vb0 b0 gnd 5v vc c gnd 5v va1 a1 gnd 5v vb1 b1 gnd 0v va2 a2 gnd 0v vb2 b2 gnd 5v va3 a3 gnd 5v vb3 b3 gnd 0v .print tran v(s0) v(s1) v(s2) v(s3) v(c3) .end AL-Falah School of Engineering & Technology A Page 44 .5p PS=8u M104 vdd a3 65 72 PMOS L=1u W=3u AD=7.25p PS=8.5p PS=8u M82 47 a2 44 69 NMOS L=1u W=3u AD=1.5u M87 60 b3 59 72 PMOS L=1u W=3u AD=1.25p PD=8.5p PS=8u M83 gnd a2 43 69 NMOS L=1u W=3u AD=7.5p PS=4u M88 vdd b3 64 72 PMOS L=1u W=3u AD=8.5p PS=8u M92 gnd c2 58 69 NMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PS=8u M99 63 c2 65 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=1.5p PD=4u AS=1.5p PS=8u M102 64 a3 vdd 72 PMOS L=1u W=3u AD=7.5p PD=8u AS=12p PS=14u M112 gnd 63 c3 69 NMOS L=1u W=3u AD=13.25p PS=8.5p PD=8u AS=7.5p PD=8u AS=8.5p PD=8u AS=1.

AL-Falah School of Engineering & Technology (An Autonomous Institute) Waveform: AL-Falah School of Engineering & Technology A Page 45 .

Master your semester with Scribd & The New York Times

Special offer for students: Only $4.99/month.

Master your semester with Scribd & The New York Times

Cancel anytime.