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1

P REFACE:
HI GH SP EED DESI GN TECHNI QUES
High speed int egr at ed cir cuit s, bot h analog, digit al, and mixed-signal ar e used in all
t ypes of elect r onic equipment t oday. This book examines high speed linear ICs bot h
fr om t he t heor et ical and pr act ical applicat ion point of view.
Figur e P.1 shows some of t he t ypical applicat ions for high speed int egr at ed cir cuit s
by mar ket segment . Many applicat ions can be filled using st andar d linear IC
pr oduct s, while ot her s may be bet t er ser ved wit h specially designed chipset s (see
Figur e P.2).
All of t hese high speed linear ICs depend upon a br oad base of high speed cor e
compet encies shown in Figur e P.3. Analog Devices has been a leader in r eal-wor ld
signal pr ocessing for over 30 year s and has t he r equir ed exper t ise in each cr it ical
compet ency ar ea. Regar dless of how complex or highly int egr at ed mixed-signal ICs
may become, t her e is no escaping t he r equir ement for t hese basic building blocks.
An under st anding of t hese building blocks is r equir ed for t he cust omer t o
successfully specify, select , and apply new high speed pr oduct s at t he syst em level.
While a det ailed knowledge of t he int er nal cir cuit s is not r equir ed, an over all
under st anding of t he oper at ion of t he devices is cr it ical t o success.
This book is not int ended t o be a syst em design manual. Inst ead, it cover s t he t heor y
and applicat ion of many high speed analog signal pr ocessing building blocks such as
amplifier s, ADCs, DACs, et c. Syst em applicat ions ar e pr esent ed when t hey ar e of
br oad gener al int er est or illust r at e emer ging mar ket t r ends.
The pr oper applicat ion of high speed devices also r equir es a t hor ough knowledge of
good har dwar e design t echniques, such as simulat ion, pr ot ot yping, layout ,
decoupling, and gr ounding. The last sect ion in t he book focuses on t hese issues as
well as EMI and RFI design consider at ions.
2
HIGH SPEED PRODUCTS: TYPICAL APPLICATIONS
VIDEO IMAGING COMMUNICATIONS INSTRUMENTATION
u u Cameras u u Medical u u Cellular:
Broadband
Narrowband
u u Oscilloscopes
u u Mixing
u u
Scanners
u u Direct Broadcast
Satellite
u u Spectrum
Analyzers
u u Distribution u u Copiers u u Hybrid Fiber Coax
(HFC)
u u Frequency
Synthesizers
u u Video
Conferencing
u u Lasers u u CATV u u Automatic Test
Equipment
u u Displays u u CCD u u ADSL/HDSL u uData Acquisition
u u MPEG Systems u uRadar/So
nar
u u Data Recovery and
Retiming
a P.1
ADI HIGH SPEED INTEGRATED / CHIPSET SOLUTIONS
n n Cellular Communications: GSM, DECT,
AMPS, PCS, etc. (Handsets and Basestations)
n n ADSL/HDSL
n n CCD Imaging
n n Video Signal Processing (MPEG, etc.)
n n Fiber Optic and Disk Drive Data Recovery
n n Direct Broadcast Satellite Receivers
n n High Speed Modems
n n Multimedia Sound and Video Processing
a P.2
3
CORE COMPETENCIES: "DC TO LIGHT"
n n Amplifiers:
Op Amps, VCAs, PGAs, Log Amps,
Sample-and-Hold Amplifiers
n n Switches and Multiplexers
n n Analog-to-Digital Converters (ADCs)
n n Digital-to-Analog Converters (DACs)
n n Analog Signal Processing
Multipliers, RMS-DC Converters, etc.
n n RF/IF Signal Processing
n n DSP
a P.3
1
SECTI ON 1
HI GH SP EED OP ERATI ONAL AMP LI FI ERS
Wa l t Kest er
I NTRODUCTI ON
High speed analog signal pr ocessing applicat ions, such as video and
communicat ions, r equir e op amps which have wide bandwidt h, fast set t ling t ime,
low dist or t ion and noise, high out put cur r ent , good DC per for mance, and oper at e at
low supply volt ages. These devices ar e widely used as gain blocks, cable dr iver s,
ADC pr e-amps, cur r ent -t o-volt age conver t er s, et c. Achieving higher bandwidt hs for
less power is ext r emely cr it ical in t oday's por t able and bat t er y-oper at ed
communicat ions equipment . The r apid pr ogr ess made over t he last few year s in
high-speed linear cir cuit s has hinged not only on t he development of IC pr ocesses
but also on innovat ive cir cuit t opologies.
The evolut ion of high speed pr ocesses by using amplifier bandwidt h as a funct ion of
supply cur r ent as a figur e of mer it is shown in Figur e 1.1. (In t he case of duals,
t r iples, and quads, t he cur r ent per amplifier is used). Analog Devices BiFET pr ocess,
which pr oduced t he AD712 and OP249 (3MHz bandwidt h, 3mA cur r ent ), yields
about 1MHz per mA. The CB (Complement ar y Bipolar ) pr ocess (AD817, AD847,
AD811, et c.) yields about 10MHz/mA of supply cur r ent . Ft 's of t he CB pr ocess PNP
t r ansist or s ar e about 700MHz, and t he NPN's about 900MHz.
The lat est gener at ion complement ar y bipolar pr ocess fr om Analog Devices is a
high speed dielect r ically isolat ed pr ocess called XFCB (eXt r a Fast Complement ar y
Bipolar ). This pr ocess (2-4 GHz Ft mat ching PNP and NPN t r ansist or s), coupled
wit h innovat ive cir cuit t opologies allow op amps t o achieve new levels of cost -
effect ive per for mance at ast onishing low quiescent cur r ent s. The appr oximat e figur e
of mer it for t his pr ocess is t ypically 100MHz/mA, alt hough t he AD8011 op amp is
capable of 300MHz bandwidt h on 1mA of supply cur r ent due t o it s unique t wo-st age
cur r ent -feedback ar chit ect ur e.
2
C
B
:


1
0
M
H
z

P
E
R

m
A
AMPLIFIER BANDWIDTH VERSUS SUPPLY CURRENT
FOR ANALOG DEVICES' PROCESSES
SUPPLY CURRENT (PER AMPLIFIER), mA
B
A
N
D
W
I
D
T
H

(
M
H
z
)
1000
300
100
30
10
3
1
0.3 1 3 10 30
AD8001
AD8011
AD811
AD847
AD817
OP482
AD712
OP249
741
1.1
X
F
C
B
:


1
0
0
M
H
z

P
E
R

m
A
B
i
F
E
T
:


1
M
H
z

P
E
R

m
A
a
In or der t o select int elligent ly t he cor r ect op amp for a given applicat ion, an
under st anding of t he var ious op amp t opologies as well as t he t r adeoffs bet ween
t hem is r equir ed. The t wo most widely used t opologies ar e volt age feedback (VFB)
and cur r ent feedback (CFB). The following discussion t r eat s each in det ail and
discusses t he similar it ies and differ ences.
VOLTAGE FEEDBACK (VFB) OP AMP S
A volt age feedback (VFB) op amp is dist inguished fr om a cur r ent feedback (CFB) op
amp by cir cuit t opology. The VFB op amp is cer t ainly t he most popular in low
fr equency applicat ions, but t he CFB op amp has some advant ages at high
fr equencies. We will discuss CFB in det ail lat er , but fir st t he mor e t r adit ional VFB
ar chit ect ur e.
Ear ly IC volt age feedback op amps wer e made on "all NPN" pr ocesses. These
pr ocesses wer e opt imized for NPN t r ansist or s, and t he "lat er al" PNP t r ansist or s had
r elat ively poor per for mance. Lat er al PNPs wer e gener ally only used as cur r ent
sour ces, level shift er s, or for ot her non-cr it ical funct ions. A simplified diagr am of a
t ypical VFB op amp manufact ur ed on such a pr ocess is shown in Figur e 1.2.
3
1.2
VOLTAGE FEEDBACK (VFB) OP AMP
DESIGNED ON AN "ALL NPN" IC PROCESS
a
v
OUT
V
BIAS
I
T
-V
S
I
T
2
C
P
R
T
I
T
2
Q2
Q3
Q1
+V
S
"LATERAL" PNP
I
T
Q4
"gm"
STAGE
A
i = vgm
v
+
-
I
T
2
gm = I
c

q
kT
v
OUT
= = v @ HF
i
j C
P
gm
j C
P
The input st age is a differ ent ial pair consist ing of eit her a bipolar pair (Q1, Q2) or a
FET pair . This "g
m
" (t r ansconduct ance) st age conver t s t he small-signal differ ent ial
input volt age, v, int o a cur r ent , i, i.e., it 's t r ansfer funct ion is measur ed in unit s of
conduct ance, 1/, (or mhos). The small signal emit t er r esist ance, r
e
, is
appr oximat ely equal t o t he r ecipr ocal of t he small-signal g
m
. The for mula for t he
small-signal g
m
of a single bipolar t r ansist or is given by t he following equat ion:
( ) g
m
r
e
q
kT
I
C
q
kT
I
T
= = =

1
2
, or
g
m
mV
I
T

1
26 2
.
I
T
is t he differ ent ial pair t ail cur r ent , I
C
is t he collect or bias cur r ent (I
C
= I
T
/2), q is
t he elect r on char ge, k is Bolt zmann's const ant , and T is absolut e t emper at ur e. At
+25C, V
T
= kT/q= 26mV (oft en called t he Ther mal Volt age, V
T
).
As we will see shor t ly, t he amplifier unit y gain-bandwidt h pr oduct , f
u
, is equal t o
g
m
/2Cp, wher e t he capacit ance Cp is used t o set t he dominant pole fr equency. For
t his r eason, t he t ail cur r ent , I
T
,is made pr opor t ional t o absolut e t emper at ur e
(PTAT). This cur r ent t r acks t he var iat ion in r
e
wit h t emper at ur e t her eby making
g
m
independent of t emper at ur e. It is r elat ively easy t o make Cp r easonably
const ant over t emper at ur e.
The out put of one side of t he g
m
st age dr ives t he emit t er of a lat er al PNP t r ansist or
(Q3). It is impor t ant t o not e t hat Q3 is not used t o amplify t he signal, only t o level
4
shift , i.e., t he signal cur r ent var iat ion in t he collect or of Q2 appear s at t he collect or
of Q3. The out put collect or cur r ent of Q3 develops a volt age acr oss high impedance
node A. Cp set s t he dominant pole of t he fr equency r esponse. Emit t er follower Q4
pr ovides a low impedance out put .
The effect ive load at t he high impedance node A can be r epr esent ed by a r esist ance,
R
T
, in par allel wit h t he dominant pole capacit ance, Cp. The small-signal out put
volt age, v
out
, is equal t o t he small-signal cur r ent , i, mult iplied by t he impedance of
t he par allel combinat ion of R
T
and Cp.
Figur e 1.3 shows a simple model for t he single-st age amplifier and t he
cor r esponding Bode plot . The Bode plot is const r uct ed on a log-log scale for
convenience.
1.3
MODEL AND BODE PLOT FOR A VFB OP AMP
a
6dB/OCTAVE
f = UNITY GAIN FREQUENCY
u
f
f = CLOSED LOOP BANDWIDTH
CL
1 +
1
R2
R1
NOISE GAIN = G
= 1 +
R2
R1
i = v gm
X1
R1
R2
v
v
in
+
-
gm
+
-
C
P
R
T
O
A
O
f
v
OUT
f
1
=
2 R C
O
P T
f
u
f
CL
f
u
=
=
gm
2 C
P
f
u
G
R1
R2
=
1 +
The low fr equency br eakpoint , f
o
,is given by:
f
o
R
T
Cp
=
1
2
.
Not e t hat t he high fr equency r esponse is det er mined solely by g
m
and Cp:
v
out
v
g
m
j Cp
=

.
The unit y gain-bandwidt h fr equency, f
u
, occur s wher e | v
out
| =| v| . Solving t he
above equat ion for f
u
,assuming | v
out
| =| v| :
5
f
u
g
m
Cp
=
2
.
We can use feedback t heor y t o der ive t he closed-loop r elat ionship bet ween t he
cir cuit 's signal input volt age, v
in
,and it 's out put volt age, v
out
:
v
out
v
in
R
R
j Cp
g
m
R
R
=
+
+ +

1
2
1
1 1
2
1

.
At t he op amp 3dB closed-loop bandwidt h fr equency, f
cl
, t he following is t r ue:
2
1
2
1
1
f
cl
Cp
g
m
R
R
+

= , and hence
f
cl
g
m
Cp R
R
=
+

2
1
1
2
1

, or
f
cl
f
u
R
R
=
+ 1
2
1
.
This demonst r at es a fundament al pr oper t y of VFB op amps: The closed-loop
bandwidth multiplied by the closed-loop gain is a constant, i.e., t he VFB op amp
exhibit s a const ant gain-bandwidt h pr oduct over most of t he usable fr equency r ange.
Some VFB op amps (called de-compensated) ar e unst able at unit y gain and ar e
designed t o be oper at ed at some minimum amount of closed-loop gain. For t hese op
amps, t he gain-bandwidt h pr oduct is st ill r elat ively const ant over t he r egion of
allowable gain.
Now, consider t he following t ypical example: I
T
= 100A, Cp = 2pF. We find t hat :
g
m
I
T
V
T
A
mV
= = =
/ 2 50
26
1
520

f
u
g
m
Cp
MHz = =


=
2
1
2 520 2 10
12
153

( )( )
.
Now, we must consider t he lar ge-signal r esponse of t he cir cuit . The slew-r at e, SR, is
simply t he t ot al available char ging cur r ent , I
T
/2, divided by t he dominant pole
capacit ance, Cp. For t he example under consider at ion,
6
I C
dv
dt
= ,
dv
dt
SR = , SR
I
C
=
SR
I
T
Cp
A
pF
V s = = =
/
/
2 50
2
25

.
The full-power bandwidt h (FPBW) of t he op amp can now be calculat ed fr om t he
for mula:
FPBW
SR
A
V s
V
MHz = =

=
2
25
2 1
4

/
, ,
wher e A is t he peak amplit ude of t he out put signal. If we assume a 2V peak-t o-peak
out put sinewave (cer t ainly a r easonable assumpt ion for high speed applicat ions),
t hen we obt ain a FPBW of only 4MHz, even t hough t he small-signal unit y gain-
bandwidt h pr oduct is 153MHz! For a 2V p-p out put sinewave, dist or t ion will begin
t o occur much lower t han t he act ual FPBW fr equency. We must incr ease t he SR by
a fact or of about 40 in or der for t he FPBW t o equal 153MHz. The only way t o do t his
is t o incr ease t he t ail cur r ent , I
T
,of t he input differ ent ial pair by t he same fact or .
This implies a bias cur r ent of 4mA in or der t o achieve a FPBW of 160MHz. We ar e
assuming t hat Cp is a fixed value of 2pF and cannot be lower ed by design.
7
VFB OP AMP BANDWIDTH AND SLEW RATE CALCULATION
n n Assume that I
T
= 100A, Cp = 2pF
n n g
m
I
c
V
T
A
mV
= = = = = =
50
26
1
520


n n
f
u
g
m
Cp
MHz = = = =
2
153

n n Slew Rate = SR =
I
T
Cp
V s
/
/
2
25 = =
BUT FOR 2V PEAK-PEAK OUTPUT (A = 1V)
n n
FPBW
SR
A
MHz = = = =
2
4

n n Must increase I
T
to 4mA to get FPBW = 160MHz!!
n n Reduce gm by adding emitter degeneration resistors
a 1.4
In pr act ice, t he FPBW of t he op amp should be appr oximat ely 5 t o 10 t imes t he
maximum out put fr equency in or der t o achieve accept able dist or t ion per for mance
(t ypically 55-80dBc @5 t o 20MHz, but act ual syst em r equir ement s var y widely).
Not ice, however , t hat incr easing t he t ail cur r ent causes a pr opor t ional incr ease in
g
m
and hence f
u
. In or der t o pr event possible inst abilit y due t o t he lar ge incr ease in
f
u
, g
m
can be r educed by inser t ing r esist or s in ser ies wit h t he emit t er s of Q1 and Q2
(t his t echnique, called emitter degeneration, also ser ves t o linear ize t he g
m
t r ansfer
funct ion and lower dist or t ion).
A major inefficiency of convent ional bipolar volt age feedback op amps is t heir
inabilit y t o achieve high slew r at es wit hout pr opor t ional incr eases in quiescent
cur r ent (assuming t hat Cp is fixed, and has a r easonable minimum value of 2 or
3pF). This of cour se is not meant t o say t hat high speed op amps designed using t his
ar chit ect ur e ar e deficient , it 's just t hat t her e ar e cir cuit design t echniques available
which allow equivalent per for mance at lower quiescent cur r ent s. This is ext r emely
impor t ant in por t able bat t er y oper at ed equipment wher e ever y milliwat t of power
dissipat ion is cr it ical.
VFB Op Amp s Desi gn ed on Comp lemen t a r y Bi p ola r P r ocesses
Wit h t he advent of complement ar y bipolar (CB) pr ocesses having high qualit y PNP
t r ansist or s as well as NPNs, VFB op amp configur at ions such as t he one shown in
t he simplified diagr am (Figur e 1.5) became popular .
8
1.5
VFB OP AMP USING TWO GAIN STAGES
a
I
T
C
P
Q3
Q2 Q1
+V
S
Q4
X1
-V
S
+
D1
-
OUTPUT
BUFFER
Not ice t hat t he input differ ent ial pair (Q1, Q2) is loaded by a cur r ent mir r or (Q3 and
D1). We show D1 as a diode for simplicit y, but it is act ually a diode-connect ed PNP
t r ansist or (mat ched t o Q3) wit h t he base and collect or connect ed t o each ot her . This
simplificat ion will be used in many of t he cir cuit diagr ams t o follow in t his sect ion.
The common emit t er t r ansist or , Q4, pr ovides a second volt age gain st age. Since t he
PNP t r ansist or s ar e fabr icat ed on a complement ar y bipolar pr ocess, t hey ar e high
qualit y and mat ched t o t he NPNs and suit able for volt age gain. The dominant pole
of t he amplifier is set by Cp, and t he combinat ion of t he gain st age,Q4, and Cp is
oft en r efer r ed t o as a Miller Integrator. The unit y-gain out put buffer is usually a
complement ar y emit t er follower .
The model for t his t wo-st age VFB op amp is shown in Figur e 1.6. Not ice t hat t he
unit y gain-bandwidt h fr equency, f
u
, is st ill det er mined by t he g
m
of t he input st age
and t he dominant pole capacit ance, Cp. The second gain st age incr eases t he DC
open-loop gain, but t he maximum slew r at e is st ill limit ed by t he input st age t ail
cur r ent : SR = I
T
/Cp.
9
1.6
MODEL FOR TWO STAGE VFB OP AMP
a
X1
R1
v
v
in
+
-
gm
+
v
out
V
REF
R2
C
P
-
I
T
i = vgm
a
+
-
f
u
=
f
CL
=
gm
2 C
P
f
u

R2
R1
SR =
I
T
C
P
1+
The t wo-st age t opology is widely used t hr oughout t he IC indust r y in VFB op amps,
bot h pr ecision and high speed.
Anot her popular VFB op amp ar chit ect ur e is t he folded cascode as shown in Figur e
1.7. An indust r y-st andar d video amplifier family (t he AD847) is based on t his
ar chit ect ur e. This cir cuit t akes advant age of t he fast PNPs available on a CB
pr ocess. The differ ent ial signal cur r ent s in t he collect or s of Q1 and Q2 ar e fed t o t he
emit t er s of a PNP cascode t r ansist or pair (hence t he t er m folded cascode). The
collect or s of Q3 and Q4 ar e loaded wit h t he cur r ent mir r or , D1 and Q5, and Q4
pr ovides volt age gain. This single-st age ar chit ect ur e uses t he junct ion capacit ance at
t he high-impedance node for compensat ion (and some var iat ions of t he design br ing
t his node t o an ext er nal pin so t hat addit ional ext er nal capacit ance can be added).
10
1.7
AD847-FAMILY FOLDED CASCODE SIMPLIFIED CIRCUIT
a
Q2
Q1
+V
S
X1
-V
S
+
-
Q5
Q4
Q3
2I
T
2I
T
2I
T
I
T
I
T
V
BIAS
C
COMP
C
STRAY
D1
AC GROUND
Wit h no emit t er degener at ion r esist or s in Q1 and Q2, and no addit ional ext er nal
compensat ing capacit ance, t his cir cuit is only st able for high closed-loop gains.
However , unit y-gain compensat ed ver sions of t his family ar e available which have
t he appr opr iat e amount of emit t er degener at ion.
The availabilit y of J FETs on a CB pr ocess allows not only low input bias cur r ent but
also impr ovement s in t he t r adeoff which must be made bet ween g
m
and I
T
found in
bipolar input st ages. Figur e 1.8 shows a simplified diagr am of t he AD845 16MHz op
amp. J FETs have a much lower g
m
per mA of t ail cur r ent t han a bipolar t r ansist or .
This allows t he input t ail cur r ent (hence t he slew r at e) t o be incr eased wit hout
having t o incr ease Cp t o maint ain st abilit y. The unusual t hing about t his seemingly
poor per for mance of t he J FET is t hat it is exact ly what is needed on t he input st age.
For a t ypical J FET, t he value of g
m
is appr oximat ely I
s
/1V (I
s
is t he sour ce cur r ent ),
r at her t han I
c
/26mV for a bipolar t r ansist or , i.e., about 40 t imes lower . This allows
much higher t ail cur r ent s (and higher slew r at es) for a given g
m
when J FETs ar e
used as t he input st age.
11
a
AD845 BiFET 16MHz OP AMP SIMPLIFIED CIRCUIT
1.8
-V
S
C
P
X1
Q2
Q3
Q1
+V
S
Q4
Q6
Q5
D1
V
BIAS
+
-
A New VF B Op Amp Ar ch i t ect u r e for "Cu r r en t -on -Dema n d " P er for ma n ce,
Lower P ower , a n d I mp r oved Slew Ra t e
Unt il now, op amp designer s had t o make t he above t r adeoffs bet ween t he input g
m
st age quiescent cur r ent and t he slew-r at e and dist or t ion per for mance. Analog
Devices' has pat ent ed a new cir cuit cor e which supplies current-on-demand t o char ge
and dischar ge t he dominant pole capacit or , Cp, while allowing t he quiescent cur r ent
t o be small. The addit ional cur r ent is pr opor t ional t o t he fast slewing input signal
and adds t o t he quiescent cur r ent . A simplified diagr am of t he basic cor e cell is
shown in Figur e 1.9.
12
1.9
"QUAD-CORE" VFB gm STAGE FOR CURRENT-ON-DEMAND
a
Q2
Q1
+V
S
-V
S
+ -
Q5
Q4
Q3
C
P1
Q6
Q7
Q8
X1
C
P2
The quad-core (g
m
st age) consist s of t r ansist or s Q1, Q2, Q3, and Q4 wit h t heir
emit t er s connect ed t oget her as shown. Consider a posit ive st ep volt age on t he
inver t ing input . This volt age pr oduces a pr opor t ional cur r ent in Q1 which is
mir r or ed int o Cp1 by Q5. The cur r ent t hr ough Q1 also flows t hr ough Q4 and Cp2.
At t he dynamic r ange limit , Q2 and Q3 ar e cor r espondingly t ur ned off. Not ice t hat
t he char ging and dischar ging cur r ent for Cp1 and Cp2 is not limit ed by t he quad
cor e bias cur r ent . In pr act ice, however , small cur r ent -limit ing r esist or s ar e r equir ed
for ming an "H" r esist or net wor k as shown. Q7 and Q8 for m t he second gain st age
(dr iven differ ent ially fr om t he collect or s of Q5 and Q6), and t he out put is buffer ed by
a unit y-gain complement ar y emit t er follower .
The quad cor e configur at ion is pat ent ed (Roy Gosser , U.S. Pat ent 5,150,074 and
ot her s pending), as well as t he cir cuit s which est ablish t he quiescent bias cur r ent s
(not shown in t he diagr am). A number of new VFB op amps using t his pr opr iet ar y
configur at ion have been r eleased and have unsur passed high fr equency low
dist or t ion per for mance, bandwidt h, and slew r at e at t he indicat ed quiescent cur r ent
levels (see Figur e 1.10). The AD9631, AD8036, and AD8047 ar e opt imized for a gain
of +1, while t he AD9632, AD8037, and AD8048 for a gain of +2. The same quad-cor e
ar chit ect ur e is used as t he second st age of t he AD8041 r ail-t o-r ail out put , zer o-volt
input single-supply op amp. The input st age is a differ ent ial PNP pair which allows
t he input common-mode signal t o go about 200mV below t he negat ive supply r ail.
The AD8042 and AD8044 ar e dual and quad ver sions of t he AD8041.
"QUAD-CORE" TWO STAGE XFCB VFB OP AMPS
AC CHARACTERISTICS VERSUS SUPPLY CURRENT
13
PART # I
SY
/ AMP BANDWIDTH SLEW RATE DISTORTION
AD9631/32 17mA 320MHz 1300V/s 72dBc@20MHz
AD8036/37 Clamped 20mA 240MHz 1200V/s 72dBc@20MHz
AD8047/48 5.8mA 250MHz 750V/s 66dBc@5MHz
AD8041 (1) 5.2mA 160MHz 160V/s 69dBc@10MHz
AD8042 (2) 5.2mA 160MHz 200V/s 64dBc@10MHz
AD8044 (4) 2.75mA 150MHz 170V/s 75dBc@5MHz
AD8031 (1) 0.75mA 80MHz 30V/s 62dBc@1MHz
AD8032 (2) 0.75mA 80MHz 30V/s 62dBc@1MHz
Number in ( ) indicates single, dual, or quad
a 1.10
CURRENT FEEDBACK (CFB) OP AMP S
We will now examine t he cur r ent feedback (CFB) op amp t opology which has
r ecent ly become popular in high speed op amps. The cir cuit concept s wer e
int r oduced many year s ago, however moder n high speed complement ar y bipolar
pr ocesses ar e r equir ed t o t ake full advant age of t he ar chit ect ur e.
It has long been known t hat in bipolar t r ansist or cir cuit s, cur r ent s can be swit ched
fast er t han volt ages, ot her t hings being equal. This for ms t he basis of non-
sat ur at ing emit t er -coupled logic (ECL) and devices such as cur r ent -out put DACs.
Maint aining low impedances at t he cur r ent swit ching nodes helps t o minimize t he
effect s of st r ay capacit ance, one of t he lar gest det r iment s t o high speed oper at ion.
The cur r ent mir r or is a good example of how cur r ent s can be swit ched wit h a
minimum amount of delay.
The cur r ent feedback op amp t opology is simply an applicat ion of t hese fundament al
pr inciples of cur r ent st eer ing. A simplified CFB op amp is shown in Figur e 1.11. The
non-inver t ing input is high impedance and is buffer ed dir ect ly t o t he inver t ing input
t hr ough t he complement ar y emit t er follower buffer s Q1 and Q2. Not e t hat t he
inver t ing input impedance is ver y low (t ypically 10 t o 100), because of t he low
emit t er r esist ance. In t he ideal case, it would be zer o. This is a fundament al
differ ence bet ween a CFB and a VFB op amp, and also a feat ur e which gives t he
CFB op amp some unique advant ages.
14
1.11
SIMPLIFIED CURRENT FEEDBACK (CFB) OP AMP
a
+V
S
-V
S
+
-
Q3
Q1
Q2
R1
R2
Q4
R
T
C
P
i
i
i
X1
The collect or s of Q1 and Q2 dr ive cur r ent mir r or s which mir r or t he inver t ing input
cur r ent t o t he high impedance node, modeled by R
T
and Cp. The high impedance
node is buffer ed by a complement ar y unit y gain emit t er follower . Feedback fr om t he
out put t o t he inver t ing input act s t o for ce t he inver t ing input current t o zer o, hence
t he t er m Current Feedback. (In t he ideal case, for zer o inver t ing input impedance, no
small signal volt age can exist at t his node, only small signal cur r ent ).
Consider a posit ive st ep volt age applied t o t he non-inver t ing input of t he CFB op
amp. Q1 immediat ely sour ces a pr opor t ional cur r ent int o t he ext er nal feedback
r esist or s cr eat ing an error cur r ent which is mir r or ed t o t he high impedance node by
Q3. The volt age developed at t he high impedance node is equal t o t his cur r ent
mult iplied by t he equivalent impedance. This is wher e t he t er m transimpedance op
amp or iginat ed, since t he t r ansfer funct ion is an impedance, r at her t han a unit less
volt age r at io as in a t r adit ional VFB op amp.
Not e t hat t he er r or cur r ent is not limit ed by t he input st age bias cur r ent , i.e., there
is no slew-rate limitation in an ideal CFB op amp. The cur r ent mir r or s supply
current-on-demand fr om t he power supplies. The negat ive feedback loop t hen for ces
t he out put volt age t o a value which r educes t he inver t ing input er r or cur r ent t o zer o.
The model for a CFB op amp is shown in Figur e 1.12 along wit h t he cor r esponding
Bode plot . The Bode plot is plot t ed on a log-log scale, and t he open-loop gain is
expr essed as a t r ansimpedance, T(s), wit h unit s of ohms.
15
( )
a
1.12
R2
R1
CFB OP AMP MODEL AND BODE PLOT
C
P
R
T
i
|T(s)|
( )
f
O
f
CL
1
1
2 R2C
P
R
O
R
O
R2 R1
X1
X1
R
O
V
OUT
V
IN
R
T
R2
R
O
6dB/OCTAVE
12dB/OCTAVE
f
CL
=

2 R2C
P
FOR
R
O
<< R1
R
O
<< R2
1 + +
The finit e out put impedance of t he input buffer is modeled by Ro. The input er r or
cur r ent is i. By applying t he pr inciples of negat ive feedback, we can der ive t he
expr ession for t he op amp t r ansfer funct ion:
v
out
v
in
R
R
j CpR
Ro
R
Ro
R
=
+
+ + +

1
2
1
1 2 1
2 1

.
At t he op amp 3db closed-loop bandwidt h fr equency, f
cl
, t he following is t r ue:
2 2 1
2 1
1 f
cl
CpR
Ro
R
Ro
R
+ +

= .
Solving for f
cl
:
f
cl
CpR
Ro
R
Ro
R
=
+ +

1
2 2 1
2 1

.
For t he condit ion Ro << R2 and R1, t he equat ion simply r educes t o:
f
cl
CpR
=
1
2 2
16
Examinat ion of t his equat ion quickly r eveals t hat the closed-loop bandwidth of a
CFB op amp is determined by the internal dominant pole capacitor, Cp, and the
external feedback resistor R2, and is independent of the gain-setting resistor, R1. This
abilit y t o maint ain const ant bandwidt h independent of gain makes CFB op amps
ideally suit ed for wideband pr ogr ammable gain amplifier s.
Because t he closed-loop bandwidt h is inver sely pr opor t ional t o t he ext er nal feedback
r esist or , R2, a CFB op amp is usually opt imized for a specific R2. Incr easing R2 fr om
it 's opt imum value lower s t he bandwidt h, and decr easing it may lead t o oscillat ion
and inst abilit y because of high fr equency par asit ic poles.
The fr equency r esponse of t he AD8011 CFB op amp is shown in Figur e 1.13 for
var ious closed-loop values of gain (+1, +2, and +10). Not e t hat even at a gain of +10,
t he closed loop bandwidt h is st ill gr eat er t han 100MHz. The peaking which occur s at
a gain of +1 is t ypical of wideband CFB op amps when used in t he non-inver t ing
mode and is due pr imar ily t o st r ay capacit ance at t he inver t ing input . The peaking
can be r educed by sacr ificing bandwidt h and using a slight ly lar ger feedback
r esist or . The AD8011 CFB op amp r epr esent s st at e-of-t he-ar t per for mance, and key
specificat ions ar e shown in Figur e 1.14.
a
+4
1.13
+3
AD8011 FREQUENCY RESPONSE
G = +1, +2, +10
+2
+1
0
-2
-3
-4
1 10 100 500
FREQUENCY - MHz
-1
+5
-5
G = +1
R
F
= 1k
G = +10
R
F
= 500
G = +2
R
F
= 1k
V
S
= +5V OR 5V
V
OUT
= 200mV p-p
N
O
R
M
A
L
I
Z
E
D

G
A
I
N

-

d
B
AD8011 CFB OP AMP KEY SPECIFICATIONS
n n 1mA Power Supply Current (+5V or 5V)
n n 300MHz Bandwidth (G = +1)
n n 2000 V/s Slew Rate
n n 29ns Settling Time to 0.1%
n n Video Specifications (G = +2)
Differential Gain Error 0.02%
17
Differential Phase Error 0.06
25MHz 0.1dB Bandwidth
n n Distortion
70dBc @ 5MHz
62dBc @ 20MHz
n n Fully Specified for 5V or +5V Operation
a 1.14
Tr adit ional cur r ent feedback op amps have been limit ed t o a single gain st age, using
cur r ent -mir r or s as pr eviously descr ibed. The AD8011 (and also ot her s in t his family:
AD8001, AD8002, AD8004, AD8005, AD8009, AD8013, AD8072, AD8073), unlike
t r adit ional CFB op amps uses a t wo-st age gain configur at ion as shown in Figur e
1.15. Unt il now, fully complement ar y t wo-gain st age CFB op amps have been
impr act ical because of t heir high power dissipat ion. The AD8011 employs a second
gain st age consist ing of a pair of complement ar y amplifier s (Q3 and Q4). Not e t hat
t hey ar e not connect ed as cur r ent mir r or s but as gr ounded-emit t er s. The det ailed
design of cur r ent sour ces (I1 and I2), and t heir r espect ive bias cir cuit s (Roy Gosser ,
pat ent -applied-for ) ar e t he key t o t he success of t he t wo-st age CFB cir cuit ; t hey
keep t he amplifier 's quiescent power low, yet ar e capable of supplying current-on-
demand for wide cur r ent excur sions r equir ed dur ing fast slewing.
a
SIMPLIFIED TWO-STAGE CFB OP AMP
1.15
-V
S
C
P
X1
Q2
Q3
Q1
+V
S
Q4
I1
+ -
I2
C
C
/2
C
C
/2
A fur t her advant age of t he t wo-st age amplifier is t he higher over all bandwidt h (for
t he same power ), which means lower signal dist or t ion and t he abilit y t o dr ive
heavier ext er nal loads.
18
Thus far , we have lear ned sever al key feat ur es of CFB op amps. The most impor t ant
is t hat for a given complement ar y bipolar IC pr ocess, CFB generally always yields
higher FPBW (hence lower distortion) than VFB for the same amount of quiescent
supply current. This is because t her e is pr act ically no slew-r at e limit ing in CFB.
Because of t his, t he full power bandwidt h and t he small signal bandwidt h ar e
appr oximat ely t he same.
The second impor t ant feat ur e is t hat t he inverting input impedance of a CFB op amp
is very low. This can be advant ageous when using t he op amp in t he inver t ing mode
as an I/V conver t er , because t her e is much less sensit ivit y t o inver t ing input
capacit ance t han wit h VFB.
The t hir d feat ur e is t hat the closed-loop bandwidth of a CFB op amp is determined
by the value of the internal Cp capacitor and the external feedback resistor R2 and is
relatively independent of the gain-setting resistor R1. We will now examine some
t ypical applicat ions issues and make fur t her compar isons bet ween CFBs and VFBs.
CURRENT FEEDBACK OP AMP FAMILY
PART I
SY
/AMP BANDWIDTH SLEW RATE DISTORTION
AD8001 (1) 5.5mA 880MHz 1200V/s 65dBc@5MHz
AD8002 (2) 5.0mA 600MHz 1200 V/s 65dBc@5MHz
AD8004 (4) 3.5mA 250MHz 3000 V/s 78dBc@5MHz
AD8005 (1) 0.4mA 180MHz 500 V/s 53dBc@5MHz
AD8009 (1) 11mA 1000MHz 7000 V/s 80dBc@5MHz
AD8011 (1) 1mA 300MHz 2000 V/s 70dBc@5MHz
AD8012 (2) 1mA 300MHz 1200 V/s 66dBc@5MHz
AD8013 (3) 4mA 140MHz 1000 V/s G=0.02%, =0.06
AD8072 (2) 5mA 100MHz 500 V/s G=0.05%, =0.1
AD8073 (3) 5mA 100MHz 500 V/s G=0.05%, =0.1
Number in ( ) Indicates Single, Dual, Triple, or Quad
a 1.16
SUMMARY: CURRENT FEEDBACK OP AMPS
n n CFB yields higher FPBW and lower distortion than
VFB for the same process and power dissipation
19
n n Inverting input impedance of a CFB op amp is low,
non-inverting input impedance is high
n n Closed-loop bandwidth of a CFB op amp is determined
by the internal dominant-pole capacitance and the
external feedback resistor, independent of the gain-
setting resistor
a 1.17
EFFECTS OF FEEDBACK CAP ACI TANCE I N OP AMP S
At t his point , t he t er m noise gain needs some clar ificat ion. Noise gain is t he amount
by which a small amplit ude noise volt age sour ce in ser ies wit h an input t er minal of
an op amp is amplified when measur ed at t he out put . The input volt age noise of an
op amp is modeled in t his way. It should be not ed t hat t he DC noise gain can also be
used t o r eflect t he input offset volt age (and ot her op amp input er r or sour ces) t o t he
out put .
Noise gain must be dist inguished fr om signal gain. Figur e 1.18 shows an op amp in
t he inver t ing and non-inver t ing mode. In t he non-inver t ing mode, not ice t hat noise
gain is equal t o signal gain. However , in t he inver t ing mode, t he noise gain doesn't
change, but t he signal gain is now R2/R1. Resist or s ar e shown as feedback
element s, however , t he net wor ks may also be r eact ive.
FOR VFB OP AMP:
CLOSED-LOOP BW =
f
CL
=
a
1.18
+
-
R1
R1
NOISE GAIN AND SIGNAL GAIN COMPARISON
V
OUT
V
IN
f
u
G
+
-
V
IN
V
OUT
R2
R2
V
N V
N
NON-INVERTING INVERTING
SIGNAL GAIN = 1 +
NOISE GAIN = = 1 +
SIGNAL GAIN =
NOISE GAIN = 1 +
UNITY GAIN BANDWIDTH FREQUENCY
NOISE GAIN
R2
R1
R2
R1
- R2
R1
R2
R1
20
Two ot her configur at ions ar e shown in Figur e 1.19 wher e t he noise gain has been
incr eased independent of signal gain by t he addit ion of R3 acr oss t he input
t er minals of t he op amp. This t echnique can be used t o st abilize de-compensat ed op
amps which ar e unst able for low values of noise gain. However , t he sensit ivit y t o
input noise and offset volt age is cor r espondingly incr eased.
R2
R1||R3
a
1.19
+
-
R1
R1
INCREASING THE NOISE GAIN
WITHOUT AFFECTING SIGNAL GAIN
V
OUT
V
IN
+
-
V
IN
V
OUT
R2
R2
V
N V
N
NON-INVERTING INVERTING
SIGNAL GAIN = 1 +
NOISE GAIN = = 1 +
SIGNAL GAIN =
NOISE GAIN = 1 +
R2
R1
- R2
R1
R2
R1||R3
R3
R3
Noise gain is oft en plot t ed as a funct ion of fr equency on a Bode plot t o det er mine t he
op amp st abilit y. If t he feedback is pur ely r esist ive, t he noise gain is const ant wit h
fr equency. However , r eact ive element s in t he feedback loop will cause it t o change
wit h fr equency. Using a log-log scale for t he Bode plot allows t he noise gain t o be
easily dr awn by simply calculat ing t he br eakpoint s det er mined by t he fr equencies of
t he var ious poles and zer os. The point of int er sect ion of t he noise gain wit h t he open-
loop gain not only det er mines t he op amp closed-loop bandwidth, but also can be
used t o analyze st abilit y.
An excellent explanat ion of how t o make simplifying appr oximat ions using Bode
plot s t o analyze gain and phase per for mance of a feedback net wor ks is given in
Refer ence 4.
J ust as signal gain and noise gain can be differ ent , so can t he signal bandwidth and
t he closed-loop bandwidth. The op amp closed-loop bandwidt h, f
cl
, is always
det er mined by t he int er sect ion of t he noise gain wit h t he open-loop fr equency
r esponse. The signal bandwidt h is equal t o t he closed-loop bandwidt h only if t he
feedback net wor k is pur ely r esist ive.
21
It is quit e common t o use a capacit or in t he feedback loop of a VFB op amp t o shape
t he fr equency r esponse as in a simple single-pole lowpass filt er (see Figur e 1.20a).
The r esult ing noise gain is plot t ed on a Bode plot t o analyze st abilit y and phase
mar gin. St abilit y of t he syst em is det er mined by t he net slope of t he noise gain and
t he open loop gain wher e t hey int er sect . For uncondit ional st abilit y, t he noise gain
plot must int er sect t he open loop r esponse wit h a net slope of less t han 12dB/oct ave.
In t his case, t he net slope wher e t hey int er sect is 6dB/oct ave, indicat ing a st able
condit ion. Not ice for t he case dr awn in Figur e 1.20a, t he second pole in t he
fr equency r esponse occur s at a consider ably higher fr equency t han f
u
.
a
1.20
R2
R1
NOISE GAIN STABILITY ANALYSIS FOR VFB AND CFB
OP AMPS WITH FEEDBACK CAPACITOR
f
p

=
1
2 R2C2
R
O
1 +
+
-
R2
A B
VFB OP AMP
CFB OP AMP
f
p

=
1
2 R2C2
f
CL
f
1
f
f
u
UNSTABLE
|A(s)| |T(s)|
( )
R1
R2
C2
In t he case of t he CFB op amp (Figur e 1.20b), t he same analysis is used, except t hat
t he open-loop t r ansimpedance gain, T(s), is used t o const r uct t he Bode plot . The
definit ion of noise gain (for t he pur poses of st abilit y analysis) for a CFB op amp,
however , must be r edefined in t er ms of a current noise sour ce at t ached t o t he
inver t ing input (see Figur e 1.21). This cur r ent is r eflect ed t o t he out put by an
impedance which we define t o be t he "cur r ent noise gain" of a CFB op amp:
" " CURRENT NOISE GAIN
Ro Z
Ro
Z
+ +

2 1
1
.
22
a 1.21
R
O
CURRENT "NOISE GAIN" DEFINITION
FOR CFB OP AMP FOR USE IN STABILITY ANALYSIS
i
Z1
X1
X1
i
R
O
V
OUT
V
OUT
Z1
Z2
Z2
T(s)
CURRENT
"NOISE GAIN" =
= R
O

+Z2(1+ )
V
OUT
i
R
O
Z1
Now, r et ur n t o Figur e 1.20b, and obser ve t he CFB current noise gain plot . At low
fr equencies, t he CFB cur r ent noise gain is simply R2 (making t he assumpt ion t hat
Ro is much less t han Z1 or Z2. The fir st pole is det er mined by R2 and C2. As t he
fr equency cont inues t o incr ease, C2 becomes a shor t cir cuit , and all t he inver t ng
input cur r ent flows t hr ough Ro (r efer back t o Figur e 1.21).
The CFB op amp is nor mally opt imized for best per for mance for a fixed feedback
r esist or , R2. Addit ional poles in t he t r ansimpedance gain, T(s), occur at fr equencies
above t he closed loop bandwidt h, f
cl
, (set by R2). Not e t hat t he int er sect ion of t he
CFB cur r ent noise gain wit h t he open-loop T(s) occur s wher e t he slope of t he T(s)
funct ion is 12dB/oct ave. This indicat es inst abilit y and possible oscillat ion.
It is for t his r eason t hat CFB op amps are not suitable in configurations which
require capacitance in the feedback loop, such as simple act ive int egr at or s or lowpass
filt er s. They can, however , be used in cer t ain act ive filt er s such as t he Sallen-Key
configur at ion shown in Figur e 1.22 which do not r equir e capacit ance in t he feedback
net wor k.
23
a
EITHER CFB OR VFB OP AMPS CAN BE USED IN
THE SALLEN-KEY FILTER CONFIGURATION
1.22
R2
R1
+
-
R2 FIXED FOR CFB OP AMP
VFB op amps, on t he ot her hand, make ver y flexible act ive filt er s. A mult iple
feedback 20MHz lowpass filt er using t he AD8048 is shown in Figur e 1.23.
a
1.23
MULTIPLE FEEDBACK 20MHz LOWPASS FILTER
USING THE AD8048 VFB OP AMP
1
V
IN

R4
154
C1
50pF
C2
100pF
R1
154
AD8048
R3
78.7
+5V
0.1 F
3
2
100
6 V
OUT
10 F
5 0.1 F
-5V
10 F
4
7
24
In gener al, t he amplifier should have a bandwidt h which is at least t en t imes t he
bandwidt h of t he filt er if pr oblems due t o phase shift of t he amplifier ar e t o be
avoided. (The AD8048 has a bandwidt h of over 200MHz in t his configur at ion). The
filt er is designed as follows:
Choose:
Fo = Cut off Fr equency = 20MHz
= Damping Rat io = 1/Q = 2
H = Absolut e Value of Cir cuit Gain
= | R4/R1| = 1
k = 2FoC1
C
C H
pF 2
4 1 1
2
100 =
+
=
( )

, for C1 = 50pF
R
Hk
1
2
159 2 = =

. , use 154
R
k H
3
2 1
79 6 =
+
=

( )
. , use 78.7
R4 = HR1 = 159.2, use 154
HI GH SP EED CURRENT-TO-VOLTAGE CONVERTERS, AND
THE EFFECTS OF I NVERTI NG I NP UT CAP ACI TANCE
Fast op amps ar e useful as cur r ent -t o-volt age conver t er s in such applicat ions as high
speed phot odiode pr eamplifier s and cur r ent -out put DAC buffer s. A t ypical
applicat ion using a VFB op amp as an I/V conver t er is shown in Figur e 1.24.
25
a
COMPENSATING FOR INPUT CAPACITANCE IN A
CURRENT-TO-VOLTAGE CONVERTER USING VFB OP AMP
1.24
+
-
C2
R2
C1
VFB
i
|A(s)|
1
f
p
f
x
f
u
f
COMPENSATED
UNCOMPENSATED
f
p

=
f
x
=
f
x
= f
p
f
u
C2 =
FOR 45 PHASE MARGIN
1
1
2 R2C1
2 R2C2
C1
2 R2 f
u
NOISE
GAIN
The net input capacit ance, C1, for ms a pole at a fr equency f
p
in t he noise gain
t r ansfer funct ion as shown in t he Bode plot , and is given by:
f
p
R C
=
1
2 2 1
.
If left uncompensat ed, t he phase shift at t he fr equency of int er sect ion, f
x
, will cause
inst abilit y and oscillat ion. Int r oducing a zer o at f
x
by adding feedback capacit or C2
st abilizes t he cir cuit and yields a phase mar gin of about 45 degr ees. The locat ion of
t he zer o is given by:
f
x
R C
=
1
2 2 2
.
Alt hough t he addit ion of C2 act ually decr eases t he pole fr equency slight ly, t his effect
is negligible if C2 << C1. The fr equency f
x
is t he geomet r ic mean of f
p
and t he unit y-
gain bandwidt h fr equency of t he op amp, f
u
,
f
x
f
p
f
u
= .
These equat ions can be solved for C2:
C
C
R f
u
2
1
2 2
=

.
26
This value of C2 will yield a phase mar gin of about 45 degr ees. Incr easing t he
capacit or by a fact or of 2 incr eases t he phase mar gin t o about 65 degr ees (see
Refer ences 4 and 5).
In pr act ice, t he opt imum value of C2 may be opt imized exper iment ally by var ying it
slight ly t o opt imize t he out put pulse r esponse.
A similar analysis can be applied t o a CFB op amp as shown in Figur e 1.25. In t his
case, however , t he low inver t ing input impedance, Ro, gr eat ly r educes t he sensit ivit y
t o input capacit ance. In fact , an ideal CFB wit h zer o input impedance would be
t ot ally insensit ive t o any amount of input capacit ance!
a
1.25
R
O
R2
COMPENSATING FOR INPUT CAPACITANCE IN A
CURRENT-TO-VOLTAGE CONVERTER USING CFB OP AMP
+
1
f
p

UNCOMPENSATED
2 R2C2
R2
f
f
x
|T(s)|
-
i
C1
C2
R2
R
O
f
p

=
f
CL

COMPENSATED
FOR 45 PHASE MARGIN
2 R
O
C1
1
1
2 R
O
||R2C1
f
x

=
f
x

= f
p

f
CL
C2

=

C1
2 R2f
CL

The pole caused by C1 occur s at a fr equency f
p
:
f
p
Ro R C RoC
=
1
2 2 1
1
2 1 ( | | )
.
This pole fr equency will be gener ally be much higher t han t he case for a VFB op
amp, and t he pole can be ignor ed complet ely if it occur s at a fr equency gr eat er t han
t he closed-loop bandwidt h of t he op amp.
We next int r oduce a compensat ing zer o at t he fr equency f
x
by inser t ing t he
capacit or C2:
f
x
R C
=
1
2 2 2
.
27
As in t he case for VFB, f
x
is t he geomet r ic mean of f
p
and f
cl
:
f
x
f
p
f
u
= .
Solving t he equat ions for C2 and r ear r anging it yields:
C
Ro
R
C
R f
cl
2
2
1
2 2
=

.
Ther e is a significant advant age in using a CFB op amp in t his configur at ion as can
be seen by compar ing t he similar equat ion for C2 r equir ed for a VFB op amp. If t he
unit y-gain bandwidt h pr oduct of t he VFB is equal t o t he closed-loop bandwidt h of
t he CFB (at t he opt imum R2), t hen t he size of t he CFB compensat ion capacit or , C2,
is r educed by a fact or of R Ro 2 / .
A compar ison in an act ual applicat ion is shown in Figur e 1.26. The full scale out put
cur r ent of t he DAC is 4mA, t he net capacit ance at t he inver t ing input of t he op amp
is 20pF, and t he feedback r esist or is 500. In t he case of t he VFB op amp, t he pole
due t o C1 occur s at 16MHz. A compensat ing capacit or of 5.6pF is r equir ed for 45
degr ees of phase mar gin, and t he signal bandwidt h is 57MHz.
a
1.26
LOW INVERTING INPUT IMPEDANCE OF CFB
OP AMP MAKES IT RELATIVELY INSENSITIVE TO INPUT
CAPACITANCE WHEN USED AS A
CURRENT-TO-VOLTAGE CONVERTER
+
1
f
u
= 200MHz
500
- 4mA
C1
C2
R2
VFB
f
p

=
2 R
O
C1
+
-
C1
C2
R2
CFB
500
4mA
20pF 20pF
f
CL
= 200MHz
R
O
= 50
= 160MHz
C2 = 1.8pF
f
x
= 176MHz
1
f
p

=
2 R2C1
= 16MHz
C2 = 5.6pF
f
x
= 57MHz
For t he CFB op amp, however , because of t he low inver t ing input impedance (Ro =
50), t he pole occur s at 160Mhz, t he r equir ed compensat ion capacit or is about
1.8pF, and t he cor r esponding signal bandwidt h is 176MHz. In act ual pr act ice, t he
28
pole fr equency is so close t o t he closed-loop bandwidt h of t he op amp t hat it could
pr obably be left uncompensat ed.
It should be not ed t hat a CFB op amp's r elat ive insensit ivit y t o inver t ing input
capacit ance is when it is used in t he inver t ing mode. In t he non-inver t ing mode,
even a few picofar ads of st r ay capacit ance on t he inver t ing input can cause
significant gain-peaking and pot ent ial inst abilit y.
Anot her advant age of t he low inver t ing input impedance of t he CFB op amp is when
it is used as an I/V conver t er t o buffer t he out put of a high speed cur r ent out put
DAC. When a st ep funct ion cur r ent (or DAC swit ching glit ch) is applied t o t he
inver t ing input of a VFB op amp, it can pr oduce a lar ge volt age t r ansient unt il t he
signal can pr opagat e t hr ough t he op amp t o it s out put and negat ive feedback is
r egained. Back-t o-back Schot t ky diodes ar e oft en used t o limit t his volt age swing as
shown in Figur e 1.27. These diodes must be low capacit ance, small geomet r y devices
because t heir capacit ance adds t o t he t ot al input capacit ance.
A CFB op amp, on t he ot her hand, pr esent s a low impedance (Ro) t o fast swit ching
cur r ent s even befor e t he feedback loop is closed, t her eby limit ing t he volt age
excur sion wit hout t he r equir ement of t he ext er nal diodes. This gr eat ly impr oves t he
set t ling t ime of t he I/V conver t er .
1.27
LOW INVERTING INPUT IMPEDANCE OF CFB OP AMP
HELPS REDUCE AMPLITUDE OF FAST DAC TRANSIENTS
a
R2
*
SCHOTTKY
CATCH
DIODES
CURRENT-OUTPUT
DAC
I
*
NOT REQUIRED FOR CFB OP AMP
BECAUSE OF LOW INVERTING INPUT IMPEDANCE
-
+
VFB
NOI SE COMP ARI SONS BETWEEN VFB AND CFB OP AMP S
29
Op amp noise has t wo component s: low fr equency noise whose spect r al densit y is
inver sely pr opor t ional t o t he squar e r oot of t he fr equency and whit e noise at
medium and high fr equencies. The low-fr equency noise is known as 1/f noise (t he
noise power obeys a 1/f law - t he noise volt age or noise cur r ent is pr opor t ional t o
1/f). The fr equency at which t he 1/f noise spect r al densit y equals t he whit e noise is
known as t he "1/f Cor ner Fr equency" and is a figur e of mer it for t he op amp, wit h
t he low values indicat ing bet t er per for mance. Values of 1/f cor ner fr equency var y
fr om a few Hz for t he most moder n low noise low fr equency amplifier s t o sever al
hundr eds, or even t housands of Hz for high-speed op amps.
In most applicat ions of high speed op amps, it is t he t ot al out put r ms noise t hat is
gener ally of int er est . Because of t he high bandwidt hs, t he chief cont r ibut or t o t he
out put r ms noise is t he whit e noise, and t hat of t he 1/f noise is negligible.
In or der t o bet t er under st and t he effect s of noise in high speed op amps, we use t he
classical noise model shown in Figur e 1.28. This diagr am ident ifies all possible whit e
noise sour ces, including t he ext er nal noise in t he sour ce and t he feedback r esist or s.
The equat ion allows you t o calculat e t he t ot al out put r ms noise over t he closed-loop
bandwidt h of t he amplifier . This for mula wor ks quit e well when t he fr equency
r esponse of t he op amp is r elat ively flat . If t her e is mor e t han a few dB of high
fr equency peaking, however , t he act ual noise will be gr eat er t han t he pr edict ed
because t he cont r ibut ion over t he last oct ave befor e t he 3db cut off fr equency will
dominat e. In most applicat ions, t he op amp feedback net wor k is designed so t hat t he
bandwidt h is r elat ively flat , and t he for mula pr ovides a good est imat e. Not e t hat
BW in t he equat ion is t he equivalent noise bandwidt h which, for a single-pole
syst em, is obt ained by mult iplying t he closed-loop bandwidt h by 1.57.
1.28
OP AMP NOISE MODEL FOR A
FIRST-ORDER CIRCUIT WITH RESISTIVE FEEDBACK
R
1
V
ON
R
p
I
n-
I
n+
V
ON
=
2
R
2
f
cl
= CLOSED LOOP BANDWIDTH
I
n-
2
R
2
2
+ I
n+
2
R
P
2


1 +
R
1
R
2
+ V
n
2
+ 4kTR
2
+ 4kTR
1
+ 4kTR
P
1 +
2
1 +
2
V
n
V
R2J
V
R1J
V
RPJ
BW = 1.57f
cl
BW
R
2
R
1
2
R
2
R
1
R
2
R
1
+
a
30
Figur e 1.29 shows a t able which indicat es how t he individual noise cont r ibut or s ar e
r efer r ed t o t he out put . Aft er calculat ing t he individual noise spect r al densit ies in
t his t able, t hey can be squar ed, added, and t hen t he squar e r oot of t he sum of t he
squar es yields t he RSS value of t he out put noise spect r al densit y since all t he
sour ces ar e uncor r elat ed. This value is mult iplied by t he squar e r oot of t he noise
bandwidt h (noise bandwidt h = closed-loop bandwidt h mult iplied by a cor r ect ion
fact or of 1.57) t o obt ain t he final value for t he out put r ms noise.
REFERRING ALL NOISE SOURCES TO THE OUTPUT
NOISE SOURCE EXPRESSED AS
A VOLTAGE
MULTIPLY BY THIS FACTOR TO REFER
TO THE OP AMP OUTPUT
Johnson Noise in R
p
:
4kTRp
Noise Gain
R
R
= = + + 1
2
1
Non-Inverting Input Current Noise
Flowing in R
p
:
I
n+
R
p
Noise Gain
R
R
= = + + 1
2
1
Input Voltage Noise:
V
n
Noise Gain
R
R
= = + + 1
2
1
Johnson Noise in R1:
4 1 kTR
R2/R1 (Gain from input of R1 to Output)
Johnson Noise in R2:
4 2 kTR
1
Inverting Input Current Noise
Flowing in R2:
I
n-
R2
1
a 1.29
Typical high speed op amps wit h bandwidt hs gr eat er t han 150MHz or so, and
bipolar input st ages have input volt age noises r anging fr om about 2 t o 20nV/Hz. To
put volt age noise in per spect ive, let 's look at t he J ohnson noise spect r al densit y of a
r esist or :
v
n
kTR BW = 4 ,
wher e k is Bolt zmann's const ant , T is t he absolut e t emper at ur e, R is t he r esist or
value, and BW is t he equivalent noise bandwidt h of int er est . (The equivalent noise
bandwidt h of a single-pole syst em is 1.57 t imes t he 3dB fr equency). Using t he
for mula, a 100 r esist or has a noise densit y of 1.3nV/Hz, and a 1000 r esist or
about 4nV/Hz (values ar e at r oom t emper at ur e: 27C, or 300K).
The base-emit t er in a bipolar t r ansist or has an equivalent noise volt age sour ce
which is due t o t he "shot noise" of t he collect or cur r ent flowing in t he t r ansist or 's
31
(noiseless) incr ement al emit t er r esist ance, r
e
. The cur r ent noise is pr opor t ional t o
t he squar e r oot of t he collect or cur r ent , Ic. The emit t er r esist ance, on t he ot her
hand, is inver sely pr opor t ional t o t he collect or cur r ent , so the shot-noise voltage is
inversely proportional to the square root of the collector current. (Refer ence 5, Sect ion
9).
Volt age noise in FET-input op amps t ends t o be lar ger t han for bipolar ones, but
cur r ent noise is ext r emely low (gener ally only a few t ens of fA/Hz) because of t he
low input bias cur r ent s. However , FET-input s ar e not gener ally r equir ed for op amp
applicat ions r equir ing bandwidt hs gr eat er t han 100MHz.
Op amps also have input cur r ent noise on each input . For high-speed FET-input op
amps, t he gat e cur r ent s ar e so low t hat input cur r ent noise is almost always
negligible (measur ed in fA/Hz).
For a VFB op amp, t he inver t ing and non-inver t ing input cur r ent noise ar e t ypically
equal, and almost always uncor r elat ed. Typical values for wideband VFB op amps
r ange fr om 0.5pA/Hz t o 5pA/Hz. The input cur r ent noise of a bipolar input st age
is incr eased when input bias-cur r ent cancellat ion gener at or s ar e added, because
t heir cur r ent noise is not cor r elat ed, and t her efor e adds (in an RSS manner ) t o t he
int r insic cur r ent noise of t he bipolar st age.
The input volt age noise in CFB op amps t ends t o be lower t han for VFB op amps
having t he same appr oximat e bandwidt h. This is because t he input st age in a CFB
op amp is usually oper at ed at a higher cur r ent , t her eby r educing t he emit t er
r esist ance and hence t he volt age noise. Typical values for CFB op amps r ange fr om
about 1 t o 5nV/Hz.
The input cur r ent noise of CFB op amps t ends t o be lar ger t han for VFB op amps
because of t he gener ally higher bias cur r ent levels. The inver t ing and non-inver t ing
cur r ent noise of a CFB is usually differ ent because of t he unique input ar chit ect ur e,
and ar e specified separ at ely. In most cases, t he inver t ing input cur r ent noise is t he
lar ger of t he t wo. Typical input cur r ent noise for CFB op amps r anges fr om 5 t o
40pA/Hz.
The gener al pr inciple of noise calculat ion is t hat uncor r elat ed noise sour ces add in a
r oot -sum-squar es manner , which means t hat if a noise sour ce has a cont r ibut ion t o
t he out put noise of a syst em which is less t han 20% of t he amplit ude of t he noise
fr om ot her noise sour ce in t he syst em, t hen it s cont r ibut ion t o t he t ot al syst em noise
will be less t han 2% of t he t ot al, and t hat noise sour ce can almost invar iably be
ignor ed - in many cases, noise sour ces smaller t han 33% of t he lar gest can be
ignor ed. This can simplify t he calculat ions using t he for mula, assuming t he cor r ect
decisions ar e made r egar ding t he sour ces t o be included and t hose t o be neglect ed.
The sour ces which dominat e t he out put noise ar e highly dependent on t he closed-
loop gain of t he op amp. Not ice t hat for high values of closed loop gain, t he op amp
volt age noise will t end be t he chief cont r ibut or t o t he out put noise. At low gains, t he
effect s of t he input cur r ent noise must also be consider ed, and may dominat e,
especially in t he case of a CFB op amp.
Feedfor war d/feedback r esist or s in high speed op amp cir cuit s may r ange fr om less
t han 100 t o mor e t han 1k, so it is difficult t o gener alize about t heir cont r ibut ion
32
t o t he t ot al out put noise wit hout knowing t he specific values and t he closed loop
gain. The best way t o make t he calculat ions is t o wr it e a simple comput er pr ogr am
which per for ms t he calculat ions aut omat ically and include all noise sour ces. In most
high speed applicat ions, t he sour ce impedance noise can be neglect ed for sour ce
impedances of 100 or less.
Figur e 1.30 shows an example calculat ion of t ot al out put noise for t he AD8011
(300MHz, 1mA) CFB op amp. All six possible sour ces ar e included in t he calculat ion.
The appr opr iat e mult iplying fact or s which r eflect t he sour ces t o t he out put ar e also
shown on t he diagr am. For G=2, t he close-loop bandwidt h of t he AD8011 is
180MHz. The cor r ect ion fact or of 1.57 in t he final calculat ion conver t s t his single-
pole bandwidt h int o t he cir cuit s equivalent noise bandwidt h.
a
1.30
AD8011 OUTPUT NOISE ANALYSIS
(G)
+
-
R
S
50
f
CL
= 180MHz
1.8nV/ Hz
0.5nV/ Hz
4nV/ Hz
4nV/ Hz
5nV/ Hz
4nV/ Hz
4nV/ Hz
5pA/ Hz
4nV/ Hz
AD8011
5pA/ Hz
0.9nV/ Hz
2nV/ Hz
R1
1k
R2
1k
OUTPUT NOISE SPECTRAL DENSITY = 8.7nV/ Hz
TOTAL NOISE = 8.7 1.57 X 180 X 10
6
= 146 V rms
(G R
S
)
(G)
(1)
(R2)
(-R2/R1)
G = 1 +
R2
R1
In communicat ions applicat ions, it is common t o specify t he noise figure (NF) of an
amplifier . Figur e 1.31 shows t he definit ion. NF is t he r at io of t he t ot al int egr at ed
out put noise fr om all sour ces t o t he t ot al out put noise which would r esult if t he op
amp wer e "noiseless" (t his noise would be t hat of t he sour ce r esist ance mult iplied by
t he gain of t he op amp using t he closed-loop bandwidt h of t he op amp t o make t he
calculat ion). Noise figur e is expr essed in dB. The value of t he sour ce r esist ance must
be specified, and in most RF syst ems, it is 50. Noise figur e is useful in
communicat ions r eceiver design, since it can be used t o measur e t he decr ease in
signal-t o-noise r at io. For inst ance, an amplifier wit h a noise figur e of 10dB following
a st age wit h a signal-t o-noise r at io of 50dB r educes t he signal-t o-noise r at io t o 40dB.
33
a
1.31
NOISE FIGURE OF AN OP AMP
+
-
R
S
50
NOISE FIGURE = 20log = 13.7dB
AD8011
0.9nV/ Hz
R2
1k
R1
1k
8.7
1.8
TOTAL = 8.7nV/ Hz
NOISE FIGURE = 20log
TOTAL OUTPUT NOISE
OUTPUT NOISE DUE TO R
S
1.8nV/ Hz G
The r at io is commonly expr essed in dB and is useful in signal chain analysis. In t he
pr evious example, t he t ot al out put volt age noise was 8.7nV/Hz. Int egr at ed over t he
closed loop bandwidt h of t he op amp (180MHz), t his yielded an out put noise of
146V r ms. The noise of t he 50 sour ce r esist ance is 0.9nV/Hz. If t he op amp wer e
noiseless (wit h noiseless feedback r esist or s), t his noise would appear at t he out put
mult iplied by t he noise gain (G=2) of t he op amp, or 1.8nV/Hz. The t ot al out put
r ms noise just due t o t he sour ce r esist or int egr at ed over t he same bandwidt h is
30.3V r ms. The noise figur e is calculat ed as:
NF dB =

= 20
10
146
30 3
13 7 log
.
. .
The same r esult can be obt ained by wor king wit h spect r al densit ies, since t he
bandwidt hs used for t he int egr at ion ar e t he same and cancel each ot her in t he
equat ion.
NF dB =

= 20
10
8 7
1 8
13 7 log
.
.
. .
HIGH SPEED OP AMP NOISE SUMMARY
n n Voltage Feedback Op Amps:
u u Voltage Noise: 2 to 20nV/ Hz
u u Current Noise: 0.5 to 5pA/ Hz
n n Current Feedback Op Amps:
34
u u Voltage Noise: 1 to 5nV/ Hz
u u Current Noise: 5 to 40pA/ Hz
n n Noise Contribution from Source Negligible if < 100
n n Voltage Noise Usually Dominates at High Gains
n n Reflect Noise Sources to Output and Combine (RSS)
n n Errors Will Result if there is Significant
High Frequency Peaking
a 1.32
DC CHARACTERI STI CS OF HI GH SP EED OP AMP S
High speed op amps ar e opt imized for bandwidt h and set t ling t ime, not for pr ecision
DC char act er ist ics as found in lower fr equency op amps such as t he indust r y
st andar d OP27. In spit e of t his, however , high speed op amps do have r easonably
good DC per for mance. The model shown in Figur e 1.33 shows how t o r eflect t he
input offset volt age and t he offset cur r ent s t o t he out put .
a
1.33
V
O
= V
OS
1 + + I
b+
R3 1 + - I
b-
R2
IF I
b+
= I
b-
AND R3 = R1||R2
V
O
= V
OS
1 +
MODEL FOR CALCULATING TOTAL
OP AMP OUTPUT VOLTAGE OFFSET
I
b-
V
OS
+
-
R3
R2
R1
R2
R1
I
b+
R2
R1
R2
R1
V
O
35
Input offset volt ages of high speed bipolar input op amps ar e r ar ely t r immed, since
offset volt age mat ching of t he input st age is excellent , t ypically r anging fr om 1 t o
3mV, wit h offset t emper at ur e coefficient s of 5 t o 15V/C.
Input bias cur r ent s on VFB op amps (wit h no input bias cur r ent compensat ion
cir cuit s) ar e appr oximat ely equal for (+) and () input s, and can r ange fr om 1 t o 5A.
The out put offset volt age due t o t he input bias cur r ent s can be nulled by making t he
effect ive sour ce r esist ance, R3, equal t o t he par allel combinat ion of R1 and R2.
This scheme will not wor k, however , wit h bias-cur r ent compensat ed VFB op amps
which have addit ional cur r ent gener at or s on t heir input s. In t his case, t he net input
bias cur r ent s ar e not necessar ily equal or of t he same polar it y. Op amps designed for
r ail-t o-r ail input oper at ion (par allel PNP and NPN differ ent ial st ages as descr ibed
lat er in t his sect ion) have bias cur r ent s which ar e also a funct ion of t he common-
mode input volt age. Ext er nal bias cur r ent cancellat ion schemes ar e ineffect ive wit h
t hese op amps also. It should be not ed, however , t hat it is oft en desir able t o mat ch
t he sour ce impedance seen by t he (+) and () input s of VFB op amps t o minimize
dist or t ion.
CFB op amps gener ally have unequal and uncor r elat ed input bias cur r ent s because
t he (+) and () input s have complet ely differ ent ar chit ect ur es. For t his r eason,
ext er nal bias cur r ent cancellat ion schemes ar e also ineffect ive. CFB input bias
cur r ent s r ange fr om 5 t o 15A, being gener ally higher at t he inver t ing input
OUTPUT OFFSET VOLTAGE SUMMARY
n n High Speed Bipolar Op Amp Input Offset Voltage:
u u Ranges from 1 to 3mV for VFB and CFB
u u Offset TC Ranges from 5 to 15V/C
n n High Speed Bipolar Op Amp Input Bias Current:
u u For VFB Ranges from 1 to 5A
u u For CFB Ranges from 5 to 15A
n n Bias Current Cancellation Doesn't Work for:
u u Bias Current Compensated Op Amps
u u Current Feedback Op Amps
a 1.34
P SRR CHARACTERI STI CS OF HI GH SP EED OP AMP S
As wit h most op amps, t he power supply r eject ion r at io (PSRR) of high speed op
amps falls off r apidly at higher fr equencies. Figur e 1.35 shows t he PSRR for t he
AD8011 CFB 300MHz CFB op amp. Not ice t hat at DC, t he PSRR is near ly 60dB,
however , at 10MHz, it falls t o only 20dB, indicat ing t he need for excellent ext er nal
LF and HF decoupling. These number s ar e fair ly t ypical of most high speed VFB or
CFB op amps, alt hough t he DC PSRR may r ange fr om 55 t o 80dB depending on t he
op amp.
36
a
1.35
AD8011 POWER SUPPLY REJECTION RATIO
+10
0
-10
-20
-30
-50
-60
-70
100k 1M 10M 100M 500M
FREQUENCY - Hz
-40
-80
-90
+PSRR
-PSRR
P
S
R
R

-

d
B
V
S
= +5V OR 5V
G = +2
R
F
= 1k
The power pins of op amps must be decoupled dir ect ly t o a lar ge-ar ea gr ound plane
wit h capacit or s which have minimal lead lengt h. It is gener ally r ecommended t hat a
low-induct ance cer amic sur face mount capacit or (0.01F t o 0.1F) be used for t he
high fr equency noise. The lower fr equency noise can be decoupled wit h low-
induct ance t ant alum elect r olyt ic capacit or s (1 t o 10F).
37
REFERENCES
1. Thomas M. Fr eder iksen, I n t u i t i ve Op er a t i on a l Amp li fi er s,
McGr aw-Hill, 1988.
2. Ser gio Fr anco, Current Feedback Amplifiers, EDN, J an.5, 1989.
3. Roy Gosser , U.S Pat ent 5,150,074.
4. J ames L. Melsa and Donald G. Schult z, Li n ea r Con t r ol Syst ems,
McGr aw-Hill, 1969, pp. 196-220.
5. Amp li fi er Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1992,
Sect ion 3.
6. Walt er G. J ung, I C Op a mp Cook book , Th i r d Ed i t i on ,
Howar d Sams & Co., 1986, ISBN: 0-672-22453-4.
7. Paul R. Gr ay and Rober t G. Meyer , An a lysi s a n d Desi gn of An a log
I n t egr a t ed Ci r cu i t s, Th i r d Ed i t i on , J ohn Wiley, 1993.
8. J . K. Rober ge, Op er a t i on a l Amp li fi er s-Th eor y a n d P r a ct i ce,
J ohn Wiley, 1975.
9. Henr y W. Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
Se con d Ed i t i on , J ohn Wiley, Inc., 1988.
10. Lewis Smit h and Dan Sheingold, Noise and Operational Amplifier Circuits,
An a log Di a logu e 25t h An n i ver sa r y I ssu e, pp. 19-31, 1991.
11. D. St out , M. Kaufman, Ha n d book of Op er a t i on a l Amp li fi er Ci r cu i t
Desi gn , New Yor k, McGr aw-Hill, 1976.
12. J oe Buxt on, Careful Design Tames High-S peed Op Amps, Elect r on i c
Desi gn , Apr il 11, 1991.
13. J . Dost al, Op er a t i on a l Amp li fi er s, Elsevier Scient ific Publishing,
New Yor k, 1981.
14. Bar r ie Gilber t , Contemporary Feedback Amplifier Design,
15. Ser gio Fr anco, Desi gn wi t h Op er a t i on a l Amp li fi er s a n d An a log I Cs,
McGr aw-Hill Book Company, 1988.
16. J er ald Gr aeme, P h ot od i od e Amp li fi er s-Op Amp Solu t i on s,
Gain Technology Cor por at ion, 2700 W. Br oadway Blvd., Tucson,
AZ 85745, 1996.
1
SECTI ON 2
HI GH SP EED OP AMP AP P LI CATI ONS
Wa l t Kest er , Wa l t J u n g
OP TI MI ZI NG THE FEEDBACK NETWORK FOR MAXI MUM
BANDWI DTH FLATNESS I N WI DEBAND CFB OP AMP S
Achieving t he highest 0.1dB bandwidt h flat ness is impor t ant in many video
applicat ions. Because of t he cr it ical r elat ionship bet ween t he feedback r esist or and
t he bandwidt h of a CFB op amp, opt imum bandwidt h flat ness is highly dependent
on t he feedback r esist or value, t he r esist or par asit ics, as well as t he op amp package
and PCB par asit ics. Figur e 2.1 shows t he fine scale (0.1dB/division) flat ness plot t ed
ver sus t he feedback r esist ance for t he AD8001 in a non-inver t ing gain of 2. These
plot s wer e made using t he AD8001 evaluat ion boar d wit h sur face mount r esist or s.
O
U
T
P
U
T

-

d
B

R
F
R
G
= R
F
G = +2
AD8001
a
2.1
AD8001 CFB OP AMP BANDWIDTH FLATNESS OPTIMIZED BY
PROPER SELECTION OF FEEDBACK RESISTOR
0.1
0
-0.9
1M 10M 100M
-0.1
-0.2
-0.3
-0.4
-0.5
FREQUENCY - Hz
-0.6
-0.7
-0.8
RF =
649
RF = 698
RF = 750
G = +2
It is r ecommended t hat once t he opt imum r esist or values have been det er mined, 1%
t oler ance values should be used. In addit ion, r esist or s of differ ent const r uct ion have
differ ent associat ed par asit ic capacit ance and induct ance. Sur face mount r esist or s
ar e t he opt imum choice, and it is not r ecommended t hat leaded component s be used
wit h high speed op amps at t hese fr equencies because of t heir par asit ics.
Slight ly differ ent r esist or values may be r equir ed t o achieve opt imum per for mance
in t he DIP ver sus t he SOIC packages (see Figur e 2.2). The SOIC package exhibit s
slight ly lower par asit ic capacit ance and induct ance t han t he DIP. The dat a shows
t he opt imum feedback (R
G
) and feedfor war d (R
F
) r esist or s for highest 0.1dB
bandwidt h for t he AD8001 in t he DIP and t he SOIC packages. As you might
2
suspect , t he SOIC package can be opt imized for slight ly higher 0.1dB bandwidt h
because of it s lower par asit ics.
OPTIMUM VALUES OF R
F
AND R
G
FOR AD8001
DIP AND SOIC PACKAGES (MAXIMUM 0.1dB BANDWIDTH)
AD8001AN (DIP) GAIN
Component 1 +1 +2
R
F
649 1050 750
R
G
649 - 750
0.1dB Flatness 105MHz 70MHz 105MHz
AD8001AR (SOIC) GAIN
Component 1 +1 +2
R
F
604 953 681
R
G
604 - 681
0.1dB Flatness 130MHz 100MHz 120MHz
a 2.2
As has been discussed, t he CFB op amp is r elat ively insensit ive t o capacit ance on
t he inver t ing input when it is used in t he inver t ing mode (as in an I/V applicat ion).
This is because t he low inver t ing input impedance is in par allel wit h t he ext er nal
capacit ance and t ends t o minimize it s effect . In t he non-inver t ing mode, however ,
even a few picofar ads of st r ay inver t ing input capacit ance may cause peaking and
inst abilit y. Figur e 2.3 shows t he effect s of adding summing junct ion capacit ance t o
t he inver t ing input of t he AD8004 (SOIC package) for G = +2. Not e t hat only 1pF of
added inver t ing input capacit ance (C
J
) causes a significant incr ease in bandwidt h
and an incr ease in peaking. For G = 2, however , 5pF of addit ional inver t ing input
capacit ance causes only a small incr ease in bandwidt h and no significant incr ease in
peaking.
High speed VFB op amps ar e sensit ive t o st r ay inver t ing input capacit ance when
used in eit her t he inver t ing or non-inver t ing mode.
3
a
2.3
AD8004 CFB OP AMP SENSITIVITY TO
INVERTING INPUT CAPACITANCE FOR G = +2, G = -2
FREQUENCY - MHz
+2
-8
1 500 10 40 100
-2
0
-4
-6
V
IN
= 50mV rms
RL = 100
5V
S
-10
-12
-14
+2
-8
-2
0
-4
-6
-10
-12
-14
C
J
= 1pF
C
J
= 0
C
J
= 5.1pF
C
J
= 0
G = +2
G = -2
N
O
R
M
A
L
I
Z
E
D

G
A
I
N

-

d
B
,

G

=

+
2
N
O
R
M
A
L
I
Z
E
D

G
A
I
N

-

d
B
,

G

=

-
2
DRI VI NG CAP ACI TI VE LOADS
Fr om syst em and signal fidelit y point s of view, t r ansmission line coupling bet ween
st ages is best , and is descr ibed in some det ail in t he next sect ion. However , complet e
t r ansmission line syst em design may not always be possible or pr act ical. In addit ion,
var ious ot her par asit ic issues need car eful consider at ion in high per for mance
designs. One such pr oblem par asit ic is amplifier load capacit ance, which pot ent ially
comes int o play for all wide bandwidt h sit uat ions which do not use t r ansmission line
signal coupling.
A gener al design r ule for wideband linear dr iver s is t hat capacit ive loading (cap
loading) effect s should always be consider ed. This is because PC boar d capacit ance
can build up quickly, especially for wide and long signal r uns over gr ound planes
insulat ed by a t hin, higher K dielect r ic. For example, a 0.025 PC t r ace using a G-10
dielect r ic of 0.03 over a gr ound plane will r un about 22pF/foot (Refer ence 1). Even
r elat ively small load capacit ance (i.e., <100 pF) can be t r oublesome, since while not
causing out r ight oscillat ion, it can st ill st r et ch amplifier set t ling t ime t o gr eat er
t han desir able levels for a given accur acy.
The effect s of cap loading on high speed amplifier out put s ar e not simply
det r iment al, t hey ar e act ually an anat hema t o high qualit y signals. However ,
befor e-t he-fact designer knowledge st ill allows high cir cuit per for mance by
employing var ious t r icks of t he t r ade t o combat t he capacit ive loading. If it is not
dr iven via a t r ansmission line, r emot e signal cir cuit r y should be checked for
capacit ive loading ver y car efully, and char act er ized as best possible. Dr iver s which
face poor ly defined load capacit ance should be bullet -pr oofed accor dingly wit h an
appr opr iat e design t echnique fr om t he opt ions list below.
4
Shor t of a t r ue mat ched t r ansmission line syst em, a number of ways exist t o dr ive a
load which is capacit ive in nat ur e while maint aining amplifier st abilit y.
Custom capacitive load (cap load) compensation includes two possible options,
namely a); overcompensation, and b); an intentionally forced-high loop noise gain
allowing crossover in a stable region. Both of these steps can be effective in special
situations, as they reduce the amplifiers effective closed loop bandwidth, so as to
restore stability in the presence of cap loading.
Overcompensation of t he amplifier , when possible, r educes amplifier bandwidt h so
t hat t he addit ional load capacit ance no longer r epr esent s a danger t o phase mar gin.
As a pr act ical mat t er however , amplifier compensat ion nodes t o allow t his ar e
available on few high speed amplifier s. One such useful example is t he AD829,
compensat ed by a single capacit or at pin 5. In gener al, almost any amplifier using
ext er nal compensat ion can always be over compensat ed t o r educe bandwidt h. This
will r est or e st abilit y against cap loads, by lower ing t he amplifier s unit y gain
fr equency.
Forcing a high noise gain, is shown in Figur e 2.4, wher e t he capacit ively loaded
amplifier wit h a noise gain of unit y at t he left is seen t o be unst able, due t o a 1/ -
open loop r olloff int er sect ion on t he Bode diagr am in an unst able 12dB/oct ave
r egion. For such a case, quit e oft en st abilit y can be r est or ed by int r oducing a higher
noise gain t o t he st age, so t hat t he int er sect ion t hen occur s in a st able 6dB/oct ave
r egion, as depict ed at t he diagr am r ight Bode plot .
a
GAIN
(dB) STABLE
UNSTABLE
NG = 1
LOG FREQUENCY
LOG FREQUENCY
2.4
NG = 1 +
R2
R1
0
CAPACITIVE LOADING ON OP AMP GENERALLY REDUCES
PHASE MARGIN AND MAY CAUSE INSTABILITY,
BUT INCREASING THE NOISE GAIN OF THE CIRCUIT
IMPROVES STABILITY
NOISE GAIN = 1
NOISE GAIN = 1 +
R2
R1
C
L
C
L
R2
R1
R
O
R
O
. . .
. . .
To enable a higher noise gain (which does not necessar ily need t o be t he same as t he
st ages signal gain), use is made of r esist ive or RC pads at t he amplifier input , as in
Figur e 2.5. This t r ick is mor e br oad in scope t han over compensat ion, and has t he
advant age of not r equir ing access t o any int er nal amplifier nodes. This gener ally
5
allows use wit h any amplifier set up, even volt age follower s. The t echnique adds an
ext r a r esist or R
D
, which wor ks against R
F
t o for ce t he noise gain of t he st age t o a
level appr eciably higher t han t he signal gain (which is unit y in bot h cases her e).
Assuming t hat C
L
is a value which pr oduces a par asit ic pole near t he amplifier s
nat ur al cr ossover , t his loading combinat ion would likely lead t o oscillat ion due t o t he
excessive phase lag. However wit h R
D
connect ed, t he higher amplifier noise gain
pr oduces a new 1/ - open loop r olloff int er sect ion, about a decade lower in
fr equency. This is set low enough t hat t he ext r a phase lag fr om C
L
is no longer a
pr oblem, and amplifier st abilit y is r est or ed.
RAISING NOISE GAIN (DC OR AC) FOR
FOLLOWER OR INVERTER STABILITY
2.5
a
(A) FOLLOWER
-
+
R
F
V
OUT
C
L
R
L
R
D
R
F
/10
=
C
D
V
IN
(B) INVERTER
-
+
R
F
V
OUT
C
L
R
L
R
D
R
F
/10
=
C
D
V
IN
R
IN
A dr awback t o t his t r ick is t hat t he DC offset and input noise of t he amplifier ar e
r aised by t he value of t he noise gain, when t he opt ional C
D
is not pr esent . But ,
when C
D
is used in ser ies wit h R
D
, t he offset volt age of t he amplifier is not r aised,
and t he gained-up AC noise component s ar e confined t o a fr equency r egion above
1/(2 R
D
C
D
). A fur t her caut ion is t hat t he t echnique can be somewhat t r icky
when separ at ing t hese oper at ing DC and AC r egions, and should be applied
car efully wit h r egar d t o set t ling t ime (Refer ence 2). Not e t hat t hese simplified
examples ar e gener ic, and in pr act ice t he absolut e component values should be
mat ched t o a specific amplifier .
Passivecap load compensation, shown in Figure 2.6, is the most simple (and most
popular) isolation technique available. It uses a simple out-of-the-loopseries resistor
R
X
to isolate the cap load, and can be used with any amplifier, current or voltage
feedback, FET or bipolar input.
6
a
OPEN-LOOP SERIES RESISTANCE ISOLATES CAPACITIVE
LOAD FOR AD811 CURRENT FEEDBACK OP AMP
(CIRCUIT BANDWIDTH = 13.5MHz)
2.6
6
7
4
3
2 -
+
AD811
R
IN
30.9k
R
F
750
R
X
12
R
L
500
V
OUT
C
L
1nF
0.1 F
+12V
-12V
100 F/
25V
100 F/
25V
0.1 F R
B
1k
V
IN
As not ed, t his t echnique can be applied t o vir t ually any amplifier , which is a major
r eason why it is so useful. It is shown her e wit h a cur r ent feedback amplifier
suit able for high cur r ent line dr iving, t he AD811, and it consist s of just t he simple
(passive) ser ies isolat ion r esist or , R
X
. This r esist or s minimum value for st abilit y
will var y fr om device t o device, so t he amplifier dat a sheet should be consult ed for
ot her ICs. Gener ally, infor mat ion will be pr ovided as t o t he amount of load
capacit ance t oler at ed, and a suggest ed minimum r esist or value for st abilit y
pur poses.
Dr awbacks of t his appr oach ar e t he loss of bandwidt h as R
X
wor ks against C
L
, t he
loss of volt age swing, a possible lower slew r at e limit due t o I
MAX
and C
L
, and a
gain er r or due t o t he R
X
-R
L
division. The gain er r or can be opt ionally compensat ed
wit h R
IN
, which is r at ioed t o R
F
as R
L
is t o R
X
. In t his example, a 100mA out put
fr om t he op amp int o C
L
can slew V
OUT
at a r at e of 100V/s, far below t he int r insic
AD811 slew r at e of 2500V/s. Alt hough t he dr awbacks ar e ser ious, t his for m of cap
load compensat ion is never t heless useful because of it s simplicit y. If t he amplifier is
not ot her wise pr ot ect ed, t hen an R
X
r esist or of 50-100 should be used wit h
vir t ually any amplifier facing capacit ive loading. Alt hough a non-inver t ing amplifier
is shown, t he t echnique is equally applicable t o inver t er st ages.
Wit h ver y high speed amplifier s, or in applicat ions wher e lowest set t ling t ime is
cr it ical, even small values of load capacit ance can be disr upt ive t o fr equency
r esponse, but ar e never t heless somet imes inescapable. One case in point is an
amplifier used for dr iving ADC input s. Since high speed ADC input s quit e oft en look
capacit ive in nat ur e, t his pr esent s an oil/wat er t ype pr oblem. In such cases t he
amplifier must be st able dr iving t he capacit ance, but it must also pr eser ve it s best
7
bandwidt h and set t ling t ime char act er ist ics. To addr ess t his t ype of cap load case,
R
s
and C
L
per for mance dat a for a specified set t ling t ime is most appr opr iat e.
Some applicat ions, in par t icular t hose t hat r equir e dr iving t he r elat ively high
impedance of an ADC, do not have a convenient back t er minat ion r esist or t o
dampen t he effect s of capacit ive loading. At high fr equencies, an amplifier s out put
impedance is r ising wit h fr equency and act s like an induct ance, which in
combinat ion wit h C
L
causes peaking or even wor se, oscillat ion. When t he bandwidt h
of an amplifier is an appr eciable per cent age of device F
t
,t he sit uat ion is complicat ed
by t he fact t hat t he loading effect s ar e r eflect ed back int o it s int er nal st ages. In spit e
of t his, t he basic behavior of most ver y wide bandwidt h amplifier s such as t he
AD8001 is ver y similar .
In gener al, a small damping r esist or (R
s
) placed in ser ies wit h C
L
will help r est or e
t he desir ed r esponse (see Figur e 2.7). The best choice for t his r esist or s value will
depend upon t he cr it er ion used in det er mining t he desir ed r esponse. Tr adit ionally,
simply st abilit y or an accept able amount of peaking has been used, but a mor e st r ict
measur e such as 0.1% (or even 0.01%) set t ling will yield differ ent values. For a given
amplifier , a family of R
s
- C
L
cur ves exist s, such as t hose of Figur e 2.7. These dat a
will aid in select ing R
s
for a given applicat ion.
AD8001 R
S
REQUIRED FOR VARIOUS C
L
VALUES
2.7
a
AD8001
R
S
C
L
G = +2,
20% OVERSHOOT
G = +2, 0.1% SETTLING
G = +10,
20% OVERSHOOT
R
S
( )
30
20
10
40
0
20
40 60 80
100
C
L
(pF)
The basic shape of t his cur ve can be easily explained. When C
L
is ver y small, no
r esist or is necessar y. When C
L
incr eases t o some t hr eshold value an R
s
becomes
necessar y. Since t he fr equency at which t he damping is r equir ed is r elat ed t o t he
R
s
C
L
t ime const ant , t he R
s
needed will init ially incr ease r apidly fr om zer o, and
t hen will decr ease as C
L
is incr eased fur t her . A r elat ively st r ict r equir ement , such as
for 0.1%, set t ling will gener ally r equir e a lar ger R
s
for a given C
L
, giving a cur ve
falling higher (in t er ms of R
s
) t han t hat for a less st r ingent r equir ement , such as
8
20% over shoot . For t he common gain configur at ion of +2, t hese t wo cur ves ar e
plot t ed in t he figur e for 0.1% set t ling (upper -most cur ve) and 20% over shoot (middle
cur ve). It is also wor t h ment ioning t hat higher closed loop gains lessen t he pr oblem
dr amat ically, and will r equir e less R
s
for t he same per for mance. The t hir d (lower -
most ) cur ve illust r at es t his, demonst r at ing a closed loop gain of 10 R
s
r equir ement
for 20% over shoot for t he AD8001 amplifier . This can be r elat ed t o t he ear lier
discussion associat ed wit h Figur e 2.5.
The r ecommended values for R
s
will opt imize r esponse, but it is impor t ant t o not e
t hat gener ally C
L
will degr ade t he maximum bandwidt h and set t ling t ime
per for mance which is achievable. In t he limit , a lar ge R
s
C
L
t ime const ant will
dominat e t he r esponse. In any given applicat ion, t he value for R
s
should be t aken as
a st ar t ing point in an opt imizat ion pr ocess which account s for boar d par asit ics and
ot her secondar y effect s.
Active or in-the-loopcap load compensation can also be used as shown in Figure
2.8, and this scheme modifies the passive configuration to provide feedback correction
for the DC & low frequency gain error associated with R
X
. In contrast to the passive
form, active compensation can only be used with voltage feedback amplifiers, because
current feedback amplifiers dont allow the integrating connection of C
F.
ACTIVE "IN-LOOP" CAPACITIVE LOAD COMPENSATION
CORRECTS FOR DC AND LF GAIN ERRORS
2.8
a
-
+
C
F
V
OUT
C
L
1nF
R
L
500
V
IN
R
X
33
+V
S
-V
S
R
F
R
IN
2.5k
50pF
2.5k
1k
U1
AD845
This cir cuit r et ur ns t he DC feedback fr om t he out put side of isolat ion r esist or R
X
,
t hus cor r ect ing for er r or s. AC feedback is r et ur ned via C
F
, which bypasses R
X
/R
F
at
high fr equencies. Wit h an appr opr iat e value of C
F
(which var ies wit h C
L
, for fixed
r esist ances) t his st age can be adjust ed for a well damped t r ansient r esponse
(Refer ence 2,3). Ther e is st ill a bandwidt h r educt ion, a headr oom loss, and also
(usually) a slew r at e r educt ion, but t he DC er r or s can be ver y low. A dr awback is t he
need t o t une C
F
t o C
L
, as even if t his is done well init ially, any change t o C
L
will
9
alt er t he r esponse away fr om flat . The cir cuit as shown is useful for volt age feedback
amplifier s only, because capacit or C
F
pr ovides int egr at ion ar ound U1. It also can be
implement ed in inver t ing fashion, by dr iving t he bot t om end of R
IN
.
Internal cap load compensation involves the use of an amplifier which has topological
provisions for the effects of external cap loading. To the user, this is the most
transparent of the various techniques, as it works for any feedback situation, for any
value of load capacitance. Drawbacks are that it produces higher distortion than does
an otherwise similar amplifier without the network, and the compensation against
cap loading is somewhat signal level dependent.
The int er nal cap load compensat ed amplifier sounds at fir st like t he best of all
possible wor lds, since t he user need do not hing at all t o set it up. Figur e 2.9, a
simplified diagr am of an AD817 amplifier wit h int er nal cap load compensat ion,
shows how it wor ks. The cap load compensat ion is t he C
F
-r esist or net wor k shown
ar ound t he unit y gain out put st age of t he amplifier - not e t hat t he dot t ed connect ion
of t his net wor k under scor es t he fact t hat it only makes it s pr esence felt for cer t ain
load condit ions.
a
2.9
AD817 SIMPLIFIED SCHEMATIC ILLUSTRATES INTERNAL
COMPENSATION FOR DRIVING CAPACITIVE LOADS
-IN
C
F
+V
S
OUTPUT
+IN
NULL 1 NULL 8
-V
S
Under nor mal (non-capacit ive or light r esist ive) loading, t her e is limit ed
input /out put volt age er r or acr oss t he out put st age, so t he C
F
net wor k t hen sees a
r elat ively small volt age dr op, and has lit t le or no effect on t he AD817s high
impedance compensat ion node. However when a capacit or (or ot her heavy) load is
pr esent , t he high cur r ent s in t he out put st age pr oduce a volt age differ ence acr oss
t he C
F
net wor k, which effect ively adds capacit ance t o t he compensat ion node. Wit h
t his r elat ively heavy loading, a net lar ger compensat ion capacit ance r esult s, and
r educes t he amplifier speed in a manner which is adapt ive t o t he ext er nal
10
capacit ance, C
L
. As a point of reference, note that it requires 6.3mA peak current to
support a 2Vp-p swing across a 100pF load at 10MHz.
Since t his mechanism is r esident in t he amplifier out put st age and it affect s t he
over all compensat ion char act er ist ics dynamically, it act s independent of t he specific
feedback hookup, as well as size of t he ext er nal cap loading. In ot her wor ds, it can
be t r anspar ent t o t he user in t he sense t hat no specific design condit ions need be set
t o make it wor k (ot her t han select ing an IC which employs it ). Some amplifier s
using int er nal cap load compensat ion ar e t he AD847 and t he AD817, and t heir dual
equivalent s, AD827 and AD826.
Ther e ar e, however , some caveat s also associat ed wit h t his int er nal compensat ion
scheme. As wit h t he passive compensat ion t echniques, bandwidt h decr eases as t he
device slows down t o pr event oscillat ion wit h higher load cur r ent s. Also, t his
adapt ive compensat ion net wor k has it s gr eat est effect when enough out put cur r ent
flows t o pr oduce significant volt age dr op acr oss t he C
F
net wor k. Conver sely, at
small signal levels, t he effect of t he net wor k on speed is less, so gr eat er r inging may
act ually be possible for some cir cuit s for lower -level out put s.
a
2.10
RESPONSE OF INTERNAL CAP LOAD
COMPENSATED AMPLIFIER VARIES WITH SIGNAL LEVEL
(A) V
OUT
= 10V p-p (B) V
OUT
= 200mV p-p
Vertical Scale: 5V/div
Vertical Scale: 100mV/div
Horizontal Scale: 500ns/div
AD817 INVERTER
R
F
= R
IN
= 1k
R
L
= 1k , C
L
= 1nF, V
S
= 15V
5V 500ns
5V
100mV
100mv
500ns
The dynamic nat ur e of t his int er nal cap load compensat ion is illust r at ed in Figur e
2.10, which shows an AD817 unit y gain inver t er being exer cised at bot h high and
low out put levels, wit h common condit ions of V
s
= 15V, R
L
= 1k, C
L
= 1nF, and
using 1k input /feedback r esist or s. In bot h phot os t he input signal is on t he t op
t r ace and t he out put signal is on t he bot t om t r ace, and t he t ime scale is fixed. In t he
10Vp-p out put (A) phot o at t he left , t he out put has slowed down appr eciably t o
accommodat e t he capacit ive load, but set t ling is st ill r elat ively clean, wit h a small
per cent age of over shoot . This indicat es t hat for t his high level case, t he bandwidt h
r educt ion due t o C
L
is most effect ive. However , in t he (B) phot o at t he r ight , t he
11
200mVp-p out put shows gr eat er over shoot and r inging, for t he lower level signal.
The point is t hat t he per for mance of t he cap load compensat ed amplifier is signal
dependent , but is always st able wit h any cap load.
Finally, because t he cir cuit is based on a nonlinear pr inciple, t he int er nal net wor k
affect s dist or t ion per for mance and load dr ive abilit y, and t hese fact or s influence
amplifier per for mance in video applicat ions. Though t he net wor ks pr esence does not
by any means make devices like t he AD847 or AD817 unusable for video, it does not
per mit t he ver y lowest levels of dist or t ion and differ ent ial gain and phase which ar e
achievable wit h ot her wise compar able amplifier s (for example, t he AD818 which is
an AD817 wit hout t he int er nal compensat ing net wor k).
While t he individual t echniques for count er ing cap loading out lined above have
var ious specific t r adeoffs as not ed, all of t he t echniques have a common dr awback of
r educing speed (bot h bandwidt h and slew r at e). If t hese par amet er s cannot be
sacr ificed, t hen a mat ched t r ansmission line syst em is t he solut ion, and is discussed
in mor e det ail lat er in t he chapt er . As for choosing among t he cap load compensat ion
schemes, it would seem on t he sur face t hat amplifier s using t he int er nal for m offer
t he best possible solut ion t o t he pr oblem- just pick t he r ight amplifier and for get
about it . And indeed, t hat would seem t he panacea solut ion for all cap load
sit uat ions - if you use t he r ight amplifier you never need t o t hink about cap
loading again. Could t her e be mor e t o it ?
Yes! The got cha of int er nal cap load compensat ion is subt le, and lies in t he fact
t hat t he dynamic adapt ive nat ur e of t he compensat ion mechanism act ually can
pr oduce higher levels of dist or t ion, vis--vis an ot her wise similar amplifier , without
t he C
F
-r esist or net wor k. Like t he old saying about no fr ee lunches, if you car e about
at t aining t op-not ch levels of high fr equency AC per for mance, you should give t he
issue of whet her t o use an int er nally compensat ed cap load amplifier mor e ser ious
t hought t han simply picking a t r endy device.
On t he ot her hand, if you have no r equir ement s for t he lowest levels of dist or t ion,
t hen such an amplifier could be a good choice. Such amplifier s ar e cer t ainly easier t o
use, and r elat ively for giving about loading issues. Some applicat ions of t his chapt er
illust r at e t he dist or t ion point specifically, quot ing per for mance in a dr iver cir cuit
wit h/wit hout t he use of an int er nal cap load compensat ed amplifier s.
CABLE DRI VERS AND RECEI VERS
High qualit y video signals ar e best t r ansmit t ed over t er minat ed coaxial cable having
a cont r olled char act er ist ic impedance. The char act er ist ic impedance is given by t he
equat ion Zo = (L/C) wher e L is t he dist r ibut ed induct ance per foot , and C is t he
dist r ibut ed capacit ance per foot . Popular values ar e 50, 75, and 93 or 100.
If a lengt h of coaxial cable is t er minat ed, it pr esent s a resistive load t o t he dr iver . If
left unt er minat ed, however , it may pr esent a pr edominat ely capacit ive load t o t he
dr iver depending on t he out put fr equency. If t he lengt h of an unt er minat ed cable is
much less t han t he wavelengt h of t he out put fr equency of t he dr iver , t hen t he load
appear s appr oximat ely as a lumped capacit ance. For inst ance, at t he audio
fr equency of 20kHz (wavelengt h 50,000 feet , or 9.5miles), a 5 foot lengt h of
unt er minat ed 50 coaxial cable would appear as a lumped capacit ance of
12
appr oximat ely 150pF (t he dist r ibut ed capacit ance of coaxial cable is about 30pF/ft ).
At 100MHz (wavelengt h 10 feet ), however , t he unt er minat ed coax must be t r eat ed
as a t r ansmission line in or der t o calculat e t he st anding wave pat t er n and t he
volt age at t he unt er minat ed cable out put .
Because of skin effect and wir e r esist ance, coaxial cable exhibit s a loss which is a
funct ion of fr equency. This var ies consider ably bet ween cable t ypes. For inst ance t he
at t enuat ion in at 100MHz of RG188A/U is 8dB/100ft , RG58/U is 5.5dB/100ft , and
RG59/U 3.6dB/100ft (Refer ence 4).
Skin effect also affect s t he pulse r esponse of long coaxial cables. The r esponse t o a
fast pulse will r ise shar ply for t he fir st 50% of t he out put swing, t hen t aper off
dur ing t he r emaining por t ion of t he edge. Calculat ions show t hat t he 10 t o 90%
wavefor m r iset ime is 30 t imes gr eat er t han t he 0 t o 50% r iset ime when t he cable is
skin effect limit ed (see Refer ence 5).
DRIVING CABLES
n n All Interconnections are Really Transmission Lines Which
Have a Characteristic Impedance (Even if Not Controlled)
n n The Characteristic Impedance is Equal to L/C, where L
and C are the Distributed Inductance and Capacitance
n n Correctly Terminated Transmission Lines Have Impedances Equal
to Their Characteristic Impedance
n n Unterminated Transmission Lines Behave Approximately as
Lumped Capacitance if the Wavelength of the Output Frequency
is Much Greater than the Length of the Cable
u u Example: At 20kHz (Wavelength = 9.5 miles), 5 feet of
Unterminated 50 Cable (30pF/ft) Appears Like 150pF Load
u u Example: At 100MHz (Wavelength = 10 feet), 5 feet of
50 Cable Must be Properly Terminated to
PreventReflections and Standing Waves!!!!
a 2.11
It is useful t o examine what happens for condit ions of pr oper and impr oper cable
sour ce/load t er minat ions. To illust r at e t he behavior of a high speed op amp dr iving a
coaxial cable, consider t he cir cuit of Figur e 2.12. The AD8001 dr ives 5 feet of 50
coaxial cable which is load-end t er minat ed in t he char act er ist ic impedance of 50.
No t er minat ion is used at t he amplifier (dr iving) end. The pulse r esponse is also
shown in t he figur e.
The out put of t he cable was measur ed by connect ing it dir ect ly t o t he 50 input of a
500MHz Tekt r onix 644A digit izing oscilloscope. The 50 r esist or t er minat ion is
13
act ually t he input of t he scope. The 50 load is not a per fect t er minat ion (t he scope
input capacit ance is about 10pF), so some of t he pulse is r eflect ed out of phase back
t o t he sour ce. When t he r eflect ion r eaches t he op amp out put , it sees t he closed-loop
out put impedance of t he op amp which, at 100MHz, is appr oximat ely 100. Thus, it
is r eflect ed back t o t he load wit h no phase r ever sal, account ing for t he negat ive-
going "blip" which occur s appr oximat ely 16ns aft er t he leading edge. This is equal t o
t he r ound-t r ip delay of t he cable (2 5ft 1.6 ns/ft =16ns). In t he fr equency domain
(not shown), t he cable mismat ch will cause a loss of bandwidt h flat ness at t he load.
PULSE RESPONSE OF AD8001 DRIVING
5 FEET OF LOAD-TERMINATED 50 COAXIAL CABLE
2.12
a
10pF
PULSE
INPUT
649
+5V
53.6
SCOPE
OUTPUT HORIZONTAL
SCALE: 10ns/div
8ns
-
+
AD8001
649
-5V
50
5ft
SCOPE
VERTICAL
SCALE: 200mV/div
Figur e 2.13 shows a second case, t he r esult s of dr iving t he same coaxial cable, but
now used wit h bot h a 50 sour ce-end as well as a 50 load-end t er minat ion. This
case is t he pr efer r ed way t o dr ive a t r ansmission line, because a por t ion of t he
r eflect ion fr om t he load impedance mismat ch is absor bed by t he amplifier s sour ce
t er minat ion r esist or . The disadvant age is t hat t her e is a 2 gain r educt ion, because
of t he volt age division bet ween t he equal value sour ce/load t er minat ions. However , a
major posit ive at t r ibut e of t his configur at ion, wit h mat ched sour ce and load
t er minat ions in conjunct ion wit h a low-loss cable, is t hat t he best bandwidt h
flat ness is ensur ed, especially at lower oper at ing fr equencies. In addit ion, t he
amplifier is oper at ed under near opt imum loading condit ions, i.e., a r esist ive load.
14
PULSE RESPONSE OF AD8001 DRIVING 5 FEET
OF SOURCE AND LOAD-TERMINATED 50 COAXIAL CABLE
2.13
a
10pF
PULSE
INPUT
649
+5V
53.6
SCOPE
OUTPUT
8ns
AD8001
649
-5V
50
5ft
SCOPE
50
+
-
VERTICAL
SCALE: 100mV/div
HORIZONTAL
SCALE: 10ns/div
Sour ce-end (only) t er minat ions can also be used as shown in Figur e 2.14, wher e t he
op amp is sour ce t er minat ed by t he 50 r esist or which dr ives t he cable. The scope is
set for 1M input impedance, r epr esent ing an appr oximat e open cir cuit . The init ial
leading edge of t he pulse at t he op amp out put sees a 100 load (t he 50 sour ce
r esist or in ser ies wit h t he 50 coax impedance. When t he pulse r eaches t he load, a
lar ge por t ion is r eflect ed in phase because of t he high load impedance, r esult ing in a
full-amplit ude pulse at t he load. When t he r eflect ion r eaches t he sour ce-end of t he
cable, it sees t he 50 sour ce r esist ance in ser ies wit h t he op amp closed loop out put
impedance (appr oximat ely 100 at t he fr equency r epr esent ed by t he 2ns r iset ime
pulse edge). The r eflect ed por t ion r emains in phase, and appear s at t he scope input
as t he posit ive-going "blip" appr oximat ely 16ns aft er t he leading edge.
15
PULSE RESPONSE OF AD8001 DRIVING 5 FEET
OF SOURCE-TERMINATED 50 COAXIAL CABLE
2.14
a
10pF
PULSE
INPUT
649
+5V
53.6
SCOPE
OUTPUT
VERTICAL
SCALE: 200mV/div
HORIZONTAL
SCALE: 10ns/div
8ns
649
-5V
1M
5ft
SCOPE
50
AD8001
-
+
Fr om t hese exper iment s, one can easily see t hat t he pr efer r ed met hod for minimum
r eflect ions (and t her efor e maximum bandwidt h flat ness) is t o use bot h sour ce and
load t er minat ions and t r y t o minimize any r eact ance associat ed wit h t he load. The
exper iment s r epr esent a wor st -case condit ion, wher e t he fr equencies cont ained in
t he fast edges ar e gr eat er t han 100MHz. (Using t he r ule-of-t humb t hat bandwidt h =
0.35/r iset ime). At video fr equencies, eit her load-only, or sour ce-only t er minat ions
may give accept able r esult s, but t he dat a sheet should always be consult ed t o
det er mine t he op amp's closed-loop out put impedance at t he maximum fr equency of
int er est . A major disadvant age of t he sour ce-only t er minat ion is t hat it r equir es a
t r uly high impedance load (high r esist ance and minimal par asit ic capacit ance) for
minimum absor pt ion of ener gy. It also places a bur den on t his amplifier t o maint ain
a low out put impedance at high fr equencies.
Now, for a t r uly wor st case, let us r eplace t he 5 feet of coaxial cable wit h an
uncont r olled-impedance cable (one t hat is lar gely capacit ive wit h lit t le induct ance).
Let us use a capacit ance of 150pF t o simulat e t he cable (cor r esponding t o t he t ot al
capacit ance of 5 feet of coaxial cable whose dist r ibut ed capacit ance is about
30pF/foot ). Figur e 2.15 shows t he out put of t he AD8001 dr iving a lumped 160pF
capacit ance (including t he scope input capacit ance of 10pF). Not ice t he over shoot
and r inging on t he pulse wavefor m due t o t he capacit ive loading. This example
illust r at es t he need t o use good qualit y cont r olled-impedance coaxial cable in t he
t r ansmission of high fr equency signals.
16
+
-
PULSE RESPONSE OF AD8001 DRIVING 160pF || 50 LOAD
2.15
a
10pF
PULSE
INPUT
649
+5V
53.6
SCOPE
OUTPUT
VERTICAL
SCALE: 200mV/div
HORIZONTAL
SCALE: 10ns/div
649
-5V
50
SCOPE
DIRECT
CONNECTION
AD8001
150pF
-
+
A HI GH P ERFORMANCE VI DEO LI NE DRI VER
The AD8047 and AD8048 VFB op amps have been opt imized t o offer out st anding
per for mance as video line dr iver s. They ut ilized t he "quad cor e" g
m
st age as
pr eviously descr ibed for high slew r at e and low dist or t ion. The AD8048 (opt imized
for G = +2) has a differ ent ial gain of 0.01% and a differ ent ial phase of 0.02, making
it suit able for HDTV applicat ions. In t he configur at ion shown in Figur e 2.16, t he
0.1dB bandwidt h is 50MHz for 5V supplies, slew r at e is 1000V/s, and 0.1%
set t ling t ime is 13ns. Tot al quiescent cur r ent is 6mA (5V), and quiescent power
dissipat ion 60mW.
17
a
2.16
VIDEO LINE DRIVER USING AD8047/AD8048:
G = 0.01%, = 0.02, 50MHz 0.1dB BANDWIDTH, 6mA (5V)
75
CABLE
200 200
75
CABLE
75
75
V
OUT
+V
S

-V
S

75
V
IN

0.1 F
10 F
AD8047/
AD8048
3
2
7
0.1 F
10 F
4
6
DI FFERENTI AL LI NE DRI VERS/RECEI VERS
Many applicat ions r equir e gain/phase mat ched complement ar y or differ ent ial
signals. Among t hese ar e analog-digit al-conver t er (ADC) input buffer s, wher e
differ ent ial oper at ion can pr ovide lower levels of 2nd har monic dist or t ion for cer t ain
conver t er s. Ot her uses include high fr equency br idge excit at ion, and dr iver s for
balanced t r ansmission t wist ed pair lines such as in ADSL and HDSL.
The t r ansmission of high qualit y signals acr oss noisy int er faces (eit her bet ween
individual PC boar ds or bet ween r acks) has always been a challenge t o design
engineer s. Differ ent ial t echniques using high common-mode-r eject ion-r at io (CMRR)
inst r ument at ion amplifier s lar gely solves t he pr oblem at low fr equencies.
At audio fr equencies, t r ansfor mer s, or pr oduct s such as t he SSM-2142 balanced line
dr iver and SSM-2141/SSM-2143 line r eceiver offer out st anding CMRRs and t he
abilit y t o t r ansmit low-level signals in t he pr esence of lar ge amount s of noise. At
high fr equencies, small t or oid t r ansfor mer s using bifilar windings ar e effect ive.
The pr oblem of signal t r ansmission at video fr equencies is complex. Tr ansfor mer s
ar e not effect ive, because t he baseband video signal has low-fr equency component s
down t o a few t ens of Hz. Video signals ar e gener ally single-ended, and t her efor e
don't adapt easily t o balanced t r ansmission line t echniques. In addit ion, shielded
t win-conduct or coaxial cable wit h good bandwidt h is usually somewhat bulky and
expensive. Finally, designing high bandwidt h, low dist or t ion differ ent ial video
dr iver s and r eceiver s wit h high CMRRs at high fr equencies is an ext r emely difficult
t ask.
Even wit h t he above pr oblems, t her e ar e differ ent ial t echniques available now which
offer dist inct advant ages over single-ended met hods. Some of t hese t echniques make
18
use of discr et e component s, while ot her s ut ilize t he lat est in st at e-of-t he-ar t video
differ ent ial amplifier s.
Two solut ions t o t he pr oblem of differ ent ial t r ansmission and r ecept ion ar e shown in
Figur e 2.17. The fir st r epr esent s t he ideal case, wher e a balanced differ ent ial line
dr iver dr ives a balanced t win-conduct or coaxial cable which in t ur n dr ives a
differ ent ial line r eceiver . This cir cuit , however , is difficult t o implement fully at
video fr equencies for t he r easons pr eviously discussed.
GND B
-
V
NOISE
a
TWO APPROACHES FOR
DIFFERENTIAL LINE DRIVING/RECEIVING
2.17
+
-
+
-
GND B V
NOISE
GND A
GND A
+
-
+
-
R
O
R
O
/2
R
O
/2
R
O
R
O
The second and most oft en used appr oach makes use of a single-ended dr iver which
dr ives a sour ce-t er minat ed coaxial cable. The shield of t he coaxial cable is gr ounded
at t he t r ansmit t ing end. At t he r eceiving end, t he coaxial cable is t er minat ed in it s
char act er ist ic impedance, but t he shield is left float ing in or der t o pr event a gr ound
loop bet ween t he t wo syst ems. The common mode gr ound noise is r eject ed by t he
CMRR of t he differ ent ial line r eceiver . The success of t his appr oach depends upon
t he char act er ist ics of t he line r eceiver .
I n ver t er -Follower Di ffer en t i a l Dr i ver
The cir cuit of Figur e 2.18 is useful as a high speed differ ent ial dr iver for dr iving
high speed 10-12 bit ADCs, differ ent ial video lines, and ot her balanced loads at
levels of 1-4Vr ms. As shown it oper at es fr om 5V supplies, but it can also be
adapt ed t o supplies in t he r ange of 5 t o 15V. When oper at ed dir ect ly fr om 5V as
her e, it minimizes pot ent ial for dest r uct ive ADC over dr ive when higher supply
volt age buffer s dr ive a 5V power ed ADC, in addit ion t o minimizing dr iver power .
19
DIFFERENTIAL DRIVER USING INVERTER/FOLLOWER
2.18 a
-
+
R
FB1
549
R4
301W
-5V
R
G1
205
NOTE: DECOUPLING
NOT SHOWN
R
TB
75
R
FB2
715
R
G2
715
-
+
+5V
R
TA
75
V
OUTA
V
OUTB
V
IN
R
IN
83.5 (75 )
53.6 (50 )
U1A
AD812
U1B
AD812
In many of t hese differ ent ial dr iver s t he per for mance cr it er ia is high. In addit ion t o
low out put dist or t ion, t he t wo signals should maint ain gain/phase flat ness. In t his
t opology, t wo sect ions of an AD812 dual cur r ent feedback amplifier ar e used for t he
channel A & B buffer s, U1A & U1B. This can pr ovide inher ent ly bet t er open-loop
bandwidt h mat ching t han t he use of t wo singles (wher e bandwidt h var ies bet ween
devices fr om differ ent manufact ur ing lot s).
The t wo buffer s her e oper at e wit h pr ecise gains of 1, as defined by t heir r espect ive
feedback and input r esist ances. Channel B buffer U1B is convent ional, and uses a
mat ched pair of 715 r esist or s- t he value for using t he AD812 on 5V supplies.
In channel A, non-inver t ing buffer U1A has an inher ent signal gain of 1, by vir t ue of
t he boot st r apped feedback net wor k R
FB1
and R
G1
(Refer ence 5). It also has a higher
noise gain, for phase mat ching. Nor mally a cur r ent feedback amplifier oper at ing as
a simple unit y gain follower would use one (opt imum) r esist or R
FB1
, and no gain
r esist or at all. Her e, wit h input r esist or R
G1
added, a U1A noise gain like t hat of
U1B r esult s. Due t o t he boot st r ap connect ion of R
FB1
-R
G1
, t he signal gain is
maint ained at unit y. Given t he mat ched open loop bandwidt hs of U1A and U1B,
similar noise gains in t he A-B channels pr ovide closely mat ched out put bandwidt hs
bet ween t he dr iver sides, a dist inct ion which gr eat ly impact s over all mat ching
per for mance.
In set t ing up a design for t he dr iver , t he effect s of r esist or gain er r or s should be
consider ed for R
G2
-R
FB2
. Her e a wor st case 2% mis-mat ch will r esult in less t han
0.2dB gain er r or bet ween channels A and B. This er r or can be impr oved simply by
specifying t ight er r esist or r at io mat ching, avoiding t r imming.
20
If desir ed, phase mat ching is t r immed via R
G1
, so t hat t he phase of channel A
closely mat ches t hat of B. This can be done for new cir cuit condit ions, by using a
pair of closely mat ched (0.1% or bet t er ) r esist or s t o sum t he A and B channels, as
R
G1
is adjust ed for t he best null condit ions at t he sum node. The A-B gain/phase
mat ching is quit e effect ive in t his dr iver , wit h t est r esult s of t he cir cuit as shown
0.04dB and 0.1 bet ween t he A and B out put signals at 10MHz, when oper at ed int o
dual 150 loads. The 3dB bandwidt h of t he dr iver is about 60MHz.
Net input impedance of t he cir cuit is set t o a st andar d line t er minat ion value such
as 75 (or 50), by choosing R
IN
so t hat t he desir ed value r esult s wit h R
IN
in
par allel wit h R
G2
. In t his example, an R
IN
value of 83.5 pr ovides a st andar d input
impedance of 75 when par alleled wit h 715. For t he cir cuit just as shown, dual
volt age feedback amplifier t ypes wit h sufficient ly high speed and low dist or t ion can
also be used. This allows gr eat er fr eedom wit h r egar d t o r esist or values using such
devices as t he AD826 and AD828.
Gain of t he cir cuit can be changed if desir ed, but t his is not t ot ally st r aight for war d.
An easy st ep t o sat isfy diver se gain r equir ement s is t o simply use a t r iple amplifier
such as t he AD813, wit h t he t hir d channel as a var iable gain input buffer .
Cr oss-Cou p led Di ffer en t i a l Dr i ver
Anot her differ ent ial dr iver appr oach uses cr oss-coupled feedback t o get ver y high
CMR and complement ar y out put s at t he same t ime. In Figur e 2.19, by connect ing
AD8002 dual cur r ent feedback amplifier sect ions as cr oss-coupled inver t er s, t heir
out put s ar e for ced equal and opposit e, assur ing zer o out put common mode volt age.
CROSS-COUPLED DIFFERENTIAL DRIVER
PROVIDES BALANCED OUTPUTS AND 250MHz BANDWIDTH
2.19
a
V
IN
R1
511
-5V
R
TA
49.9
A OUT
R
TB
49.9
B OUT
V
OUT
V
OUTB
V
OUTA
R
X
511W
R2
511
R
X
511
R
X
511
R
X
511
R4
100
C1 0.9pF (see text)
+5V
U1A
AD8002
+
+
-
-
U1B AD8002
ALL RESISTORS 1%
DECOUPLING NOT SHOWN
NOTE:
R3
(see text)
21
The gain cell which r esult s, U1A and U1B plus cr oss-coupling r esist ances R
X
, is
fundament ally a differ ent ial input and out put t opology, but it behaves as a volt age
feedback amplifier wit h r egar d t o t he feedback por t at t he U1A (+) node. The gain of
t he st age fr om V
IN
t o V
OUT
is:
G
V
OUT
V
IN
2R2
R1
= =
wher e V
OUT
is t he differ ent ial out put , equal t o V
OUTA
V
OUTB
.
This r elat ionship may not be obvious, so it can be der ived as follows:
Using t he convent ional inver t ing op amp gain equat ion, t he input volt age V
IN
develops an out put volt age V
OUTB
given by:
V
OUTB
V
IN
R
R
=
2
1
.
Also, V
OUTA
= V
OUTB
,
because V
OUTA
is inver t ed by U1B.
However , V
OUT
= V
OUTA
V
OUTB
= 2V
OUTB
.
Ther efor e,
V
OUT
V
IN
R
R
V
IN
R
R
=

= 2
2
1
2
2
1
, and
V
OUT
V
IN
R
R
=
2 2
1
.
This cir cuit has some unique benefit s. Fir st , differ ent ial gain is set by a single
r esist or r at io, so t her e is no necessit y for side-side r esist or mat ching wit h gain
changes, as is t he case for convent ional differ ent ial amplifier s (see line r eceiver s,
below). Second, because t he (over all) cir cuit emulat es a volt age feedback amplifier ,
t hese gain r esist ances ar e not as r est r ict ive as in t he case of a convent ional cur r ent
feedback amplifier . Thus, t hey ar e not highly cr it ical as t o value as long as t he
equivalent r esist ance seen by U1A is r easonably low (1k in t his case). Thir d, t he
cell bandwidt h can be opt imized t o t he desir ed gain by a single opt ional r esist or , R3,
as follows. If for inst ance, a net gain of 20 is desir ed (R2/R1=10), t he bandwidt h
would ot her wise be r educed by r oughly t his amount , since wit hout R3, t he cell
oper at es wit h a const ant gain-bandwidt h pr oduct (wor king in t he volt age feedback
mode). Wit h R3 pr esent however , advant age can be t aken of t he AD8002 cur r ent
feedback amplifier char act er ist ics. Addit ional int er nal gain is added by t he
connect ion of R3, which, given an appr opr iat e value, effect ively r aises gain-
bandwidt h t o a level so as t o r est or e t he bandwidt h which would ot her wise be lost
by t he higher closed loop gain.
22
In t he cir cuit as shown, no R3 is necessar y at t he low wor king gain of 2 t imes
differ ent ial, since t he 511 R
X
r esist or s ar e alr eady opt imized for maximum
bandwidt h. Not e t hat t hese four mat ched R
X
r esist ances ar e somewhat cr it ical, and
will change in absolut e value wit h t he use of anot her cur r ent feedback amplifier . At
higher gain closed loop gains as set by R2/R1, R3 can be chosen t o opt imize t he
wor king t r ansconduct ance in t he input st ages of U1A and U1B, as follows:
R3
Rx
(R2 / R1) 1

As in any high speed inver t ing feedback amplifier , a small high-Q chip t ype feedback
capacit ance, C1, may be needed t o opt imize flat ness of fr equency r esponse. In t his
example, a 0.9pF value was found opt imum for minimizing peaking. In gener al,
pr ovision should be made on t he PC layout for an NPO chip capacit or in t he r ange of
0.5-2pF. This capacit or is t hen value select ed at boar d char act er izat ion for opt imum
fr equency r esponse.
For t he dual t r ace, 1-500MHz swept fr equency r esponse plot of Figur e 2.20, out put
levels wer e 0dBm int o mat ched 50 loads, t hr ough back t er minat ion r esist ances
R
TA
and R
TB
, at V
OUTA
and V
OUTB
. In t his plot t he ver t ical scale is 2dB/div, and
it shows t he 3dB bandwidt h of t he dr iver measur ing about 250MHz, wit h peaking
about 0.1dB. The four R
X
r esist or s along wit h R
TA
and R
TB
cont r ol low fr equency
amplit ude mat ching, which was wit hin 0.1dB in t he lab t est s, using 511 1%
r esist or t ypes. For t ight est amplit ude mat ching, t hese r esist or r at ios can be mor e
closely cont r olled.
FREQUENCY RESPONSE OF AD8002 CROSS-COUPLED
DRIVER IS >250MHz (C1 = 0.9pF 0.1pF)
2.20
a
RELATIVE
RESPONSE
(dB)
FREQUENCY (MHz)
A OUT
B OUT
10 20 40 100 200 400
-3dB BW = 260 MHz
0
-2
-4
-6
-8
-10
-12
-14
-16
-18
Due t o t he high gain-bandwidt hs involved wit h t he AD8002, t he const r uct ion of t his
cir cuit should follow RF r ules, wit h t he use of a gr ound plane, chip bypass capacit or s
23
of zer o lead lengt h at t he 5V supply pins, and sur face mount r esist or s for lowest
induct ance.
4 Resi st or Di ffer en t i a l Li n e Recei ver
Figur e 2.21 shows a low cost , medium per for mance line r eceiver using a high speed
op amp r at ed for video use. It is act ually a st andar d 4 r esist or differ ence amplifier
opt imized for high speed, wit h a differ ent ial t o single-ended gain of R2/R1. Using low
value, DC accur at e/AC t r immed r esist ances for R1-R4 and a high speed, high CMR
op amp pr ovides t he good per for mance.
R
2
1k
0.1 F
U1
AD818
3
7
6
a
2.21
SIMPLE VIDEO LINE RECEIVER USING THE AD818 OP AMP
R
1
1k
R
3
1k
4
2
3
V
IN
V
OUT
0.1 F
R
4
1k
C
1
5pF
C
2
5pF
-V
S
+V
S
AC CMR
ADJUST
R
1
R
2
G = ,
R
2
R
1
R
3
R
4
=
Pr act ically speaking however , at low fr equencies r esist or mat ching can be mor e
cr it ical t o over all CMR t han t he r at ed CMR of t he op amp. For example, t he wor st
case CMR (in dB) of t his cir cuit due t o r esist or mismat ch is:
CMR
R
R
Kr
=
+

20
10
1
2
1
4
log .
In t his expr ession t he t er m Kr is a single r esist or t oler ance in fr act ional for m
(1%=0.01, et c.), and it is assumed t he amplifier has significant ly higher CMR
(100dB). Using discr et e 1% met al films for R1/R2 and R3/R4 yields a wor st case
CMR of 34dB, 0.1% t ypes 54dB, et c. Of cour se 4 r andom 1% r esist or s will on t he
aver age yield a CMR bet t er t han 34dB, but not dr amat ically so. A single subst r at e
dual mat ched pair t hin film net wor k is pr efer r ed, for r easons of best noise r eject ion
and simplicit y. One t ype suit able is t he Ohmt ek 1005, (Refer ence 6) which has a
r at io mat ch of 0.1%, which will pr ovide a wor st case low fr equency CMR of 66 dB.
24
This cir cuit has an int er est ing and desir able side pr oper t y. Because of t he r esist or s
it divides down t he input volt age, and t he amplifier is pr ot ect ed against over volt age.
This allows CM volt ages t o exceed 5V supply r ails in some cases wit hout hazar d.
For oper at ion wit h 15V supplies, input s should not exceed t he supply r ails.
At fr equencies above 1MHz, t he br idge balance is dominat ed by AC effect s, and a
C1-C2 capacit ive balance t r im should be used for best per for mance. The C1
adjust ment is int ended t o allow t his, pr oviding for t he cancellat ion of st r ay layout
capacit ance(s) by elect r ically mat ching t he net C1-C2 values. In a given PC layout
wit h low and st able par asit ic capacit ance, C1 is best adjust ed once in 0.5pF
incr ement s, for best high fr equency CMR. Using designat ed PC pads, pr oduct ion
values t hen would use t he t r immed value. Good AC mat ching is essent ial t o
achieving good CMR at high fr equencies. C1-C2 should be t ypes similar physically,
such as NPO (or ot her st able) cer amic chip st yle capacit or s.
While t he cir cuit as shown has unit y gain, it can be gain-scaled in discr et e st eps, as
long as t he not ed r esist or r at ios ar e maint ained. In pr act ice, t his means using t aps
on a mult i-r at io net wor k for gain change, so as t o r aise bot h R2 and R4, in ident ical
pr opor t ions. Ther e is no ot her simple way t o change gain in t his r eceiver cir cuit .
Alt er nat ely, a scheme for cont inuous gain cont r ol wit hout int er act ion wit h CMR is t o
follow t his r eceiver wit h a scaling amplifier /dr iver wit h adjust able gain. The similar
AD828 dual amplifier allows t his wit h t he addit ion of only t wo r esist or s.
Video gain/phase per for mance of t his st age is dependent upon t he device used for U1
and t he oper at ing supply volt ages. Suit able volt age feedback amplifier s wor k best at
supplies of 10 - 15V, which maximizes op amp bandwidt h. And, while many high
speed amplifier s funct ion in t his cir cuit , t hose expr essly designed wit h low dist or t ion
video oper at ion per for m best . The cir cuit as shown can be used wit h supplies of 5 t o
15V, but lowest NTSC video dist or t ion occur s for supplies of 10V or mor e, wher e
differ ent ial gain/differ ent ial phase er r or s ar e less t han 0.01%/0.05. Oper at ing at
5V supplies, t he dist or t ion r ises somewhat , but t he lowest power dr ain of 70mW
occur s.
One dr awback t o t his cir cuit is t hat it does load a 75 video line t o some ext ent , and
so should be used wit h t his loading t aken int o account . On t he plus side, it has wide
dynamic r ange for bot h signal and CM volt ages, plus t he inher ent over volt age
pr ot ect ion.
Act i ve Feed ba ck Di ffer en t i a l Li n e Recei ver
Fully int egr at ing t he line r eceiver funct ion eliminat es t he r esist or -r elat ed
dr awbacks of t he 4 r esist or line r eceiver , impr oving CMR per for mance, ease of use,
and over all cir cuit flexibilit y. An IC designed for t his funct ion is t he AD830 act ive
feedback amplifier (Refer ence 7,8). It s use as a differ ent ial line r eceiver wit h gain is
illust r at ed in Figur e 2.22.
25
a
VIDEO LOOP-THROUGH CONNECTION USING THE AD830
2.22
AD830
V
1
V
2
V
3
V
4
R3
249
1
2
3
4
G
M
G
M
-
-
+
+
C
8
7
6
5
A = 1
NC
C
A
(see text)
V
P
V
N
0.1 F
0.1 F
R2
499
R1
499
R
T
75
R
L
75
Z
CM
C
A
= 5.1pF (15V)
C
A
= 12pF (5V)
The AD830 oper at es as a feedback amplifier wit h t wo set s of fully differ ent ial
input s, available at pins 1-2 and 3-4, r espect ively. Int er nally, t he out put s of t he t wo
st ages ar e summed and dr ive a buffer out put st age. Bot h input st ages have high
CMR, and can handle differ ent ial signals up t o 2V, and CM volt ages can r ange up
t o V
s
+3V or +V
s
2.1V, wit h a 1V differ ent ial input applied. While t he AD830 does
not nor mally need pr ot ect ion against CM volt ages, if sust ained t r ansient volt age
beyond t he r ails is encount er ed, an opt ional pair of equal value (200) r esist ances
can be used in ser ies wit h pins 1-2.
In t his device t he over all feedback loop oper at es so t hat t he differ ent ial volt ages V
1-
2
and V
3-4
ar e for ced t o be equal. Feedback is t aken fr om t he out put back t o one
input differ ent ial pair , while t he ot her pair is dr iven by a differ ent ial input signal.
An impor t ant point of t his ar chit ect ur e is t hat high CM r eject ion is pr ovided by t he
t wo differ ent ial input pair s, so CMR isnt dependent on r esist or br idges and t heir
associat ed mat ching pr oblems. The inher ent ly wideband balanced cir cuit and t he
quasi-float ing oper at ion of t he dr iven input pr ovide t he high CMR, which is t ypically
100dB at DC.
The gener al expr ession for t he U1 st ages gain G is like a non-inver t ing op amp, or :
G
V
OUT
V
IN
R
R
= = + 1
2
1
For lowest DC offset , balancing r esist or R3 is used (equal t o R1| | R2).
In t his example of a video loop-t hr ough connect ion, t he input signal t apped fr om a
coax line and applied t o one input st age at pins 1-2, wit h t he scaled out put signal
26
t ied t o t he second input st age bet ween pins 3-4. Wit h t he R1-R2 feedback
at t enuat ion of 2/1, t he net r esult is t hat t he out put of U1, is t hen equal t o 2 V
IN
,
i.e., a gain of 2.
Funct ionally, t he input and local gr ounds ar e isolat ed by t he CMR of t he AD830,
which is t ypically 75dB at fr equencies below 1MHz, 60dB at 4.43MHz, and
r elat ively supply independent .
Wit h t he addit ion of an out put sour ce t er minat ion r esist or R
T
, t his cir cuit has an
over all loaded gain of unit y at t he load t er minat ion, R
L
. It is a gr ound isolat ing
video r epeat er , dr iving t he t er minat ed 75 out put line, deliver ing a final out put
equal t o t he or iginal input , V
IN
.
NTSC video per for mance will be dependent upon supplies. Dr iving a t er minat ed line
as shown, t he cir cuit has opt imum video dist or t ion levels for V
s
= 15V, wher e
differ ent ial gain is t ypically 0.06%, and differ ent ial phase 0.08. Bandwidt h can be
opt imized by t he opt ional 5.1pF (or 12pF) capacit or , C
A
, which allows a 0.1dB
bandwidt h of 10MHz wit h 15V oper at ion. The differ ent ial gain and phase er r or s
ar e about 2 at 5V.
HI GH SP EED CLAMP I NG AMP LI FI ERS
Ther e ar e many sit uat ions wher e it is desir able t o clamp t he out put of an op amp t o
pr event over dr iving t he cir cuit r y which follows. Specially designed high speed, fast
r ecover y clamping amplifier s offer an at t r act ive alt er nat ive t o designing ext er nal
clamping/pr ot ect ion cir cuit s. The AD8036/AD8037 low dist or t ion, wide bandwidt h
clamp amplifier s r epr esent a significant br eakt hr ough in t his t echnology. These
devices allow t he designer t o specify a high (V
H
) and low (V
L
) clamp volt age. The
out put of t he device clamps when t he input exceeds eit her of t hese t wo levels. The
AD8036/AD8037 offer super ior clamping per for mance compar ed t o compet ing
devices t hat use out put -clamping. Recover y t ime fr om over dr ive is less t han 5ns.
The key t o t he AD8036 and AD8037's fast , accur at e clamp and amplifier
per for mance is t heir pr opr iet ar y input clamp ar chit ect ur e. This new design r educes
clamp er r or s by mor e t han 10x over pr evious out put clamp based cir cuit s, as well as
subst ant ially incr easing t he bandwidt h, pr ecision, and ver sat ilit y of t he clamp
input s.
Figur e 2.23 is an idealized block diagr am of t he AD8036 connect ed as a unit y gain
volt age follower . The pr imar y signal pat h compr ises A1 (a 1200V/s, 240MHz high
volt age gain, differ ent ial t o single-ended amplifier ) and A2 (a G=+1 high cur r ent
gain out put buffer ). The AD8037 differ s fr om t he AD8036 only in t hat A1 is
opt imized for closed-loop gains of t wo or gr eat er .
27
+
-
A1
2.23
AD8036/AD8037 CLAMP AMPLIFIER EQUIVALENT CIRCUIT
R
F
a
140
V
OUT
-V
IN
+V
IN
V
H
+1
+1
+1
+
-
+
-
C
H
C
L
V
L
A
B
C
S1
A2
+1
S1 A B C
V
IN
> V
H
0 1 0
V
L
V
IN
V
H
1 0 0
V
IN
< V
L
0 0 1
The input clamp sect ion is compr ised of compar at or s C
H
and C
L
, which dr ive swit ch
S1 t hr ough a decoder . The unit y-gain buffer s in ser ies wit h t he +V
IN
, V
H
, and V
L
input s isolat e t he input pins fr om t he compar at or s and S1 wit hout r educing
bandwidt h or pr ecision.
The t wo compar at or s have about t he same bandwidt h as A1 (240MHz), so t hey can
keep up wit h signals wit hin t he useful bandwidt h of t he AD8036. To illust r at e t he
oper at ion of t he input clamp cir cuit , consider t he case wher e V
H
is r efer enced t o
+1V, V
L
is open, and t he AD8036 is set for a gain of +1 by connect ing it s out put
back t o it s inver t ing input t hr ough t he r ecommended 140 feedback r esist or . Not e
t hat t he main signal pat h always oper at es closed loop, since t he clamping cir cuit
only affect s A1's noninver t ing input .
If a 0V t o +2V volt age r amp is applied t o t he AD8036's +V
IN
for t he connect ion just
descr ibed, V
OUT
should t r ack +V
IN
per fect ly up t o +1V, t hen should limit at exact ly
+1V as +V
IN
cont inues t o +2V.
In pr act ice, t he AD8036 comes close t o t his ideal behavior . As t he +V
IN
input
volt age r amps fr om zer o t o 1V, t he out put of t he high limit compar at or C
H
st ar t s in
t he off st at e, as does t he out put of C
L
. When +V
IN
just exceeds V
H
(pr act ically, by
about 18mV), C
H
changes st at e, swit ching S1 fr om "A" t o "B" r efer ence level. Since
t he + input of A1 is now connect ed t o V
H
, fur t her incr eases in +V
IN
have no effect
on t he AD8036's out put volt age. The AD8036 is now oper at ing as a unit y-gain
buffer for t he V
H
input , as any var iat ion in V
H
, for V
H
> 1V, will be fait hfully
pr oduced at V
OUT
.
Oper at ion of t he AD8036 for negat ive input volt ages and negat ive clamp levels on
V
L
is similar , wit h compar at or C
L
cont r olling S1. Since t he compar at or s see t he
28
volt age on t he +V
IN
pin as t heir common r efer ence level, t he volt age V
H
and V
L
ar e
defined as "High" or "Low" wit h r espect t o +V
IN
. For example, if V
IN
is set t o zer o
volt s, V
H
is open, and V
L
is +1V, compar at or C
L
will swit ch S1 t o "C", so t he
AD8036 will buffer t he volt age on V
L
and ignor e +V
IN
.
The per for mance of t he AD8036/AD8037 closely mat ches t he ideal just descr ibed.
The compar at or 's t hr eshold ext ends fr om 60mV inside t he clamp window defined by
t he volt ages on V
L
and V
H
t o 60mV beyond t he window's edge. Swit ch S1 is
implement ed wit h cur r ent st eer ing, so t hat A1's + input makes a cont inuous
t r ansit ion fr om say, V
IN
t o V
H
as t he input volt age t r aver ses t he compar at or 's
input t hr eshold fr om 0.9V t o 1.0V for V
H
= 1.0V.
The pr act ical effect of t he non-ideal oper at ion is t o soft en t he t r ansit ion fr om
amplificat ion t o clamping modes, wit hout compr omising t he absolut e clamp limit set
by t he input clamping cir cuit . Figur e 2.24 is a gr aph of V
OUT
ver sus V
IN
for t he
AD8036 and a t ypical output clamp amplifier . Bot h amplifier s ar e set for G=+1 and
V
H
= +1V.
2.24
COMPARISON BETWEEN INPUT AND OUTPUT CLAMPING
a
INPUT VOLTAGE -
+V
IN
CLAMP ERROR - >200mV
OUTPUT CLAMP
CLAMP ERROR - 25mV
AD8036
AD8036
1.6
1.4
1.2
1.0
0.8
0.6
O
U
T
P
U
T

V
O
L
T
A
G
E

-

V
O
U
T
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2. 0
OUTPUT CLAMP AMP
The wor st case er r or bet ween V
OUT
(ideally clamped) and V
OUT
(act ual) is
t ypically 18mV t imes t he amplifier closed-loop gain. This occur s when V
IN
equals
V
H
(or V
L
). As V
IN
goes above and/or below t his limit , V
OUT
will st ay wit hin 5mV
of t he ideal value.
In cont r ast , t he out put clamp amplifier 's t r ansfer cur ve t ypically will show some
compr ession st ar t ing at an input of 0.8V, and can have an out put volt age as far as
200mV over t he clamp limit . In addit ion, since t he out put clamp causes t he
amplifier t o oper at e open-loop in t he clamp mode, t he amplifier 's out put impedance
will incr ease, pot ent ially causing addit ional er r or s, and t he r ecover y t ime is
significant ly longer .
29
It is impor t ant t hat a clamped amplifier such as t he AD8036/AD8037 maint ain low
levels of dist or t ion when t he input signals appr oach t he clamping volt ages. Figur e
2.25 shows t he second and t hir d har monic dist or t ion for t he amplifier s as t he out put
appr oaches t he clamp volt ages. The input signal is 20MHz, t he out put signal is 2V
peak-t o-peak, and t he out put load is 100.
Recover y fr om st ep volt age which is t wo t imes over t he clamping volt age is shown in
Figur e 2.26. The input st ep volt age st ar t s at +2V and goes t o 0V (left -hand t r aces on
scope phot o). The input clamp volt age (V
H
) is set at +1V. The r ight -hand t r ace
shows t he out put wavefor m. The key specificat ions for t he AD8036/AD8037 clamped
amplifier s ar e summar ized in Figur e 2.27.
2.25
AD8036/AD8037 DISTORTION NEAR CLAMPING REGION,
OUTPUT = 2V p-p, LOAD = 100 , f = 20MHz
a
ABSOLUTE VALUE OF OUTPUT VOLTAGE - Volts
AD8036 2ND
HARMONIC
AD8037 2ND
HARMONIC
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0
H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

-

d
B
c
AD8036 3RD
HARMONIC
AD8037 3RD
HARMONIC
AD8036 AD8037
V
H
+1V +0.5V
V
L
-1V -0.5V
G +1 +2
30
2.26
AD8036/AD8037 OVERDRIVE (2x) RECOVERY
a
INPUT
OUTPUT
+2V
+1V
REF
HORIZONTAL SCALE: 1ns/div
0V
1ns
AD8036/AD8037 SUMMARY SPECIFICATIONS
n n Proprietary Input Clamping Circuit with Minimized Nonlinear
Clamping Region
n n Small Signal Bandwidth: 240MHz (AD8036), 270MHz (AD8037)
n n Slew Rate: 1500V/s
n n 1.5ns Overdrive Recovery
n n Low Distortion: -72dBc @ 20MHz (500 load)
n n Low Noise: 4.5nv/ Hz, 2pA/ Hz
n n 20mA Supply Current on 5V
a 2.27
Figur e 2.28 shows t he AD9002 8-bit , 125MSPS flash conver t er dr iven by t he
AD8037 (240MHz bandwidt h) clamping amplifier . The clamp volt ages on t he
AD8037 ar e set t o +0.55 and 0.55V, r efer enced t o t he 0.5V input signal, wit h t he
ext er nal r esist ive divider s. The AD8037 also supplies a gain of t wo, and an offset of
1V (using t he AD780 volt age r efer ence), t o mat ch t he 0 t o 2V input r ange of t he
AD9002 flash conver t er . The out put signal is clamped at +0.1V and 2.1V. This
mult i-funct ion clamping cir cuit t her efor e per for ms sever al impor t ant funct ions as
31
well as pr event ing damage t o t he flash conver t er which occur s if it s input exceeds
+0.5V, t her eby for war d biasing t he subst r at e diode. The 1N5712 Schot t ky diode
adds fur t her pr ot ect ion dur ing power -up.
2.28
AD9002 8-BIT, 125MSPS FLASH CONVERTER
DRIVEN BY AD8037 CLAMP AMPLIFIER
R
T
+5V
+5V
0.1 F
BIPOLAR
SIGNAL
0.5V
75
0.1 F
-
+
AD8037
CLAMPING
AMP
AD9002
FLASH CONVERTER
(8-BITS, 125MSPS)
V
IN
= -1 1V
SUBSTRATE
DIODE
0.1 F
+
10 F
0.1 F
750
R3
806 100
V
H
= +0.55V
806 100
-5.2V
R2
301
R1
499
V
L
= -0.55V
49.9
IN5712
-5.2V
AD8037 OUTPUT
CLAMPS AT +0.1V, -2.1V
R1 R3 = R2
2.5 R1
R1 + R3
= 1 VOLT
AD780
+2.5V
REF
a
The feedback r esist or , R2 = 301, is select ed for opt imum bandwidt h per t he dat a
sheet r ecommendat ion. For a gain of t wo, t he par allel combinat ion of R1 and R3
must also equal R2:
R R
R R
R
1 3
1 3
2 301

+
= =
(near est 1% st andar d r esist or value).
In addit ion, t he Thevenin equivalent out put volt age of t he AD780 +2.5V r efer ence
and t he R3/ R1 divider must be +1V t o pr ovide t he 1V offset at t he out put of t he
AD8037.
2 5 1
1 3
1
.
+
=
R
R R
volt
Solving t he equat ions yields R1 = 499, R3 = 750 (using t he near est 1% st andar d
r esist or values).
Ot her input and out put volt ages r anges can be accommodat ed by appr opr iat e
changes in t he ext er nal r esist or s.
Fur t her examples of applicat ions of t hese fast clamping op amps ar e given in
Refer ence 9.
32
SI NGLE-SUP P LY/RAI L-TO-RAI L CONSI DERATI ONS
The mar ket is dr iving high speed amplifier s t o oper at e at lower power on lower
supply volt ages. High speed bipolar pr ocesses, such as Analog Devices' CB and
XFCB, ar e basically 12V pr ocesses, and cir cuit s designed on t hese pr ocesses ar e
gener ally limit ed t o 5V power supplies (or less). This is ideal for high speed video,
IF, and RF signals, which r ar ely exceed 5V peak-t o-peak.
The emphasis on low power , bat t er y-oper at ed por t able communicat ions and
inst r ument at ion equipment has br ought about t he need for ICs which oper at e on
single +5V, and +3V, and lower supplies. The t er m single-supply has var ious
implicat ions, some of which ar e oft en fur t her confused by mar ket ing hype.
Ther e ar e many obvious r easons for lower power dissipat ion, such as t he abilit y t o
funct ion wit hout fans, r eliabilit y issues, et c. Ther e ar e, t her efor e, many applicat ions
for single-supply devices ot her t han in syst ems which have only one supply volt age.
For example, t he lower power dissipat ion of a single-supply ADC may be t he r eason
for it s select ion, r at her t han t he fact t hat it r equir es just one supply.
Ther e ar e also syst ems which t r uly oper at e on a single power supply. In such cases,
it can oft en be difficult t o maint ain DC coupling fr om a t r ansducer all t he way
t hr ough t o t he ADC. In fact , AC coupling is oft en used in single-supply syst ems,
wit h DC r est or at ion pr eceding t he ADC. This may be r equir ed t o pr event t he loss of
dynamic r ange which would ot her wise occur because of t he need t o pr ovide adequat e
headr oom t o an AC coupled signal of ar bit r ar y dut y cycle. In t he AC-coupled
por t ions of such syst ems, a "false-gr ound" is oft en cr eat ed, usually cent er ed bet ween
t he r ails.
Ther e ar e ot her disadvant ages associat ed wit h lower power supply volt ages. Signal
swings ar e limit ed, t her efor e high-speed single-supply cir cuit s t end t o be mor e
sensit ive t o cor r upt ion by wideband noise, et c. The single-supply op amp and ADC
usually ut ilize t he same power bus t hat supplies t he digit al cir cuit s, making pr oper
filt er ing and decoupling ext r emely cr it ical.
In or der t o maximize t he signal swing in single-supply cir cuit s, it is desir able t hat a
high speed op amp ut ilize as much of t he supply r ange as possible on bot h t he input
and out put . Ideally, a t r ue rail-to-rail input op amp has an input common-mode
r ange t hat includes bot h supply r ails, and an out put r ange which does likewise. This
makes for some int er est ing t r adeoffs and compr omises in t he cir cuit design of t he op
amp.
In many cases, an op amp may be fully specified for bot h dual 5V and single-supply
oper at ion but neit her it s input nor it s out put can act ually swing closer t han about
1V t o eit her supply r ail. Such devices must be used in applicat ions wher e t he input
and out put common-mode r est r ict ions ar e not violat ed. This gener ally involves
offset t ing t he input s using a false gr ound r efer ence scheme.
To summar ize, t her e ar e many t r adeoffs involved in single-supply high-speed
designs. In many cases, using devices specified for oper at ion on +5V, but wit hout
t r ue r ail inclusive input /out put oper at ion can give good per for mance. Amplifier s ar e
33
also becoming available t hat ar e t r ue single supply r ail-t o-r ail devices.
Under st anding single-supply r ail-t o-r ail input and out put limit at ions is easy if you
under st and a few basics about t he cir cuit r y inside t he op amp. We shall consider
input and out put st ages separ at ely.
HIGH SPEED SINGLE SUPPLY AMPLIFIERS
n n Single Supply Offers:
u u Lower Power
u u Battery Operated Portable Equipment
u u Simplifies Power Supply Requirements (one voltage)
n n Design Tradeoffs:
u u Limited Signal Swings Increase Sensitivity to Noise
u u Usually Share Noisy Digital Power Supply
u u DC Coupling Throughout is Difficult
u u Rail-to-Rail Input and Output Increases Signal Swing,
but not Required in All Applications
u u Many Op Amps Specified for Single Supply, but do not
have Rail-to-Rail Inputs or Outputs
a 2.29
Ther e is some demand for high-speed op amps whose input common-mode volt age
includes bot h supply r ails. Such a feat ur e is undoubt edly useful in some
applicat ions, but engineer s should r ecognize t hat t her e ar e r elat ively few
applicat ions wher e it is absolut ely essent ial. These should be car efully dist inguished
fr om t he many applicat ions wher e common-mode r ange close t o t he supplies or one
t hat includes one of t he supplies is necessar y, but input r ail-t o-r ail oper at ion is not .
In many single-supply applicat ions, it is r equir ed t hat t he input go t o only one of t he
supply r ails (usually gr ound). Amplifier s which will handle zer o-volt input s ar e
r elat ively easily designed using PNP differ ent ial pair s (or N-channel J FET pair s) as
shown in Figur e 2.30 (cir cuit used in t he AD8041, AD8042, AD8044). The input
common-mode r ange of such an op amp ext ends fr om about 200mV below t he
negat ive supply t o wit hin about 1V of t he posit ive supply. If t he st age is designed
wit h N-channel J FETs (AD820/AD822/AD823/AD824), t he input common-mode
r ange would also include t he negat ive r ail.
34
OP90 AND OPX93 INPUT STAGE ALLOWS
INPUT TO GO TO THE NEGATIVE RAIL
2.30
a
+V
S

+V
BIAS

-V
S

The input st age could also be designed wit h NPN t r ansist or s (or P-channel J FETs),
in which case t he input common-mode r ange would include t he posit ive r ail and t o
wit hin about 1V of t he negat ive r ail; however , t his r equir ement t ypically occur s in
applicat ions such as high-side cur r ent sensing, a low-fr equency measur ement
applicat ion. The OP282/OP482 input st age uses t he P-channel J FET input pair
whose input common-mode r ange includes t he posit ive r ail.
Tr ue r ail-t o-r ail input st ages r equir e t wo long-t ailed pair s (see Figur e 2.31), one of
NPN bipolar t r ansist or s (or N-channel J FETs), t he ot her of PNP t r ansist or s (or
N-channel J FETs). These t wo pair s exhibit different offset s and bias cur r ent s, so
when t he applied input common-mode volt age changes, t he amplifier input offset
volt age and input bias cur r ent does also. In fact , when bot h cur r ent sour ces (I1 and
I2) r emain act ive t hr oughout t he ent ir e input common-mode r ange, amplifier input
offset volt age is t he average offset volt age of t he NPN pair and t he PNP pair . In
t hose designs wher e t he cur r ent sour ces ar e alt er nat ively swit ched off at some point
along t he input common-mode volt age, amplifier input offset volt age is dominat ed by
t he PNP pair offset volt age for signals near t he negat ive supply, and by t he NPN
pair offset volt age for signals near t he posit ive supply.
35
RAIL-TO-RAIL INPUT STAGE TOPOLOGY
2.31
a
+V
S

-V
S

R2
R1
Q1
Q3
I1
Q2
I
b

Q4
I2 R3
V
OS

R4
+IN
-IN
Amplifier input bias cur r ent , a funct ion of t r ansist or cur r ent gain, is also a funct ion
of t he applied input common-mode volt age. The r esult is r elat ively poor common-
mode r eject ion (CMR), and a changing common-mode input impedance over t he
common-mode input volt age r ange, compar ed t o familiar dual-supply devices. These
specificat ions should be consider ed car efully when choosing a r ail-r ail input op amp,
especially for a non-inver t ing configur at ion. Input offset volt age, input bias cur r ent ,
and even CMR may be quit e good over part of t he common-mode r ange, but much
wor se in t he r egion wher e oper at ion shift s bet ween t he NPN and PNP devices and
vice ver sa.
Tr ue r ail-t o-r ail amplifier input st age designs must t r ansit ion fr om one differ ent ial
pair t o t he ot her differ ent ial pair somewher e along t he input common-mode volt age
r ange. Devices like t he AD8031/AD8032 (specified for 5V, +5V, +3V, and +2.5V)
have a common-mode cr ossover t hr eshold at appr oximat ely 1V below t he posit ive
supply. The PNP differ ent ial input st age is act ive fr om about 200mV below t he
negat ive supply t o wit hin about 1V of t he posit ive supply. Over t his common-mode
r ange, amplifier input offset volt age, input bias cur r ent , CMR, input noise
volt age/cur r ent ar e pr imar ily det er mined by t he char act er ist ics of t he PNP
differ ent ial pair . At t he cr ossover t hr eshold, however , amplifier input offset volt age
becomes t he aver age offset volt age of t he NPN/PNP pair s and can change r apidly.
Also, amplifier bias cur r ent s, dominat ed by t he PNP differ ent ial pair over most of
t he input common-mode r ange, change polar it y and magnit ude at t he cr ossover
t hr eshold when t he NPN differ ent ial pair becomes act ive.
Applicat ions which r equir e t r ue r ail-r ail input s should t her efor e be car efully
evaluat ed, and t he amplifier chosen t o ensur e t hat it s input offset volt age, input bias
cur r ent , common-mode r eject ion, and noise (volt age and cur r ent ) ar e suit able.
36
Figur e 2.32 shows t wo t ypical high-speed op amp out put st ages. The emit t er -
follower st age is widely used, but it s out put volt age r ange is limit ed t o wit hin about
1V of eit her supply volt age. This is sufficient for many applicat ions, but t he
common-emit t er st age (used in t he AD8041/8042/8044/8031/8032 and ot her s) allows
t he out put t o swing t o wit hin t he t r ansist or sat ur at ion volt age, V
CE(SAT)
, of t he
r ails. For small amount s of load cur r ent (less t han 100A), t he sat ur at ion volt age
may be as low as 5 t o 20mV, but for higher load cur r ent s, t he sat ur at ion volt age can
incr ease t o sever al hundr ed millivolt s (for example, 500mV at 50mA). This is
illust r at ed in Figur e 2.33 for t he AD8042 (zer o-volt s in, r ail-t o-r ail out put ). The solid
cur ves show t he out put sat ur at ion volt age of t he PNP t r ansist or (out put sour cing
cur r ent ), and t he dot t ed cur ves t he NPN t r ansist or (sinking cur r ent ). The sat ur at ion
volt age incr eases wit h incr easing t emper at ur e as would be expect ed.
a
2.32
+V
S
HIGH SPEED SINGLE SUPPLY OP AMP OUTPUT STAGES
EMITTER FOLLOWER
COMMON EMITTER
+V
S
-V
S
-V
S
OUTPUT
OUTPUT
37
a
2.33
AD8042 OUTPUT SATURATION VOLTAGE
VERSUS LOAD CURRENT
0 50
LOAD CURRENT - mA
5 35
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0
V
S
= +5V
+5V - V
OH
(+125C)
10 15 20 25 30 40 45
+5V - V
OH
(+25C)
+5V - VOH (-55C)
+V
OL
(+25C)
+V
OL
(-55C)
+V
OL
(+125C)
0.80
O
U
T
P
U
T

S
A
T
U
R
A
T
I
O
N

V
O
L
T
A
G
E

-

V
An out put st age const r uct ed of CMOS FETs can pr ovide t r ue r ail-t o-r ail
per for mance, but only under no-load condit ions, and in much lower fr equency
amplifier s. If t he out put must sour ce or sink cur r ent , t he out put swing is r educed by
t he volt age dr opped acr oss t he FETs int er nal "on" r esist ance (t ypically 100).
SI NGLE SUP P LY OP AMP AP P LI CATI ONS
The following sect ion illust r at es a few applicat ions of op amps in single-supply
cir cuit s. All of t he op amps ar e fully specified for bot h 5V and +5V (and +3V wher e
t he design suppor t s it ). Bot h r ail-t o-r ail and non-r ail-t o-r ail applicat ions ar e shown.
A Si n gle-Su p p ly 10-bi t 20MSP S ADC Di r ect -Cou p led Dr i ver Usi n g t h e
AD8011
The cir cuit in Figur e 2.34 shows t he AD8011 op amp dr iving t he AD876 10-bit ,
20MSPS ADC in a dir ect -coupled applicat ion. The input and out put common-mode
volt age of t he AD8011 must lie bet ween appr oximat ely +1 and +4V when oper at ing
on a single +5V supply. The input r ange of t he AD876 is 2V peak-t o-peak cent er ed
ar ound a common-mode value of +2.6V, well wit hin t he out put volt age r ange of t he
AD8011. The upper and lower r ange set t ing volt ages ar e +1.6V and +3.6V and ar e
supplied ext er nally t o t he AD876. They ar e easily der ived fr om a r esist or divider
dr iven by a r efer ence such as t he REF198 (+4.096V). The t wo t aps on t he r esist or
divider should be buffer ed using pr ecision single-supply op amps such as t he AD822
(dual).
38
a
DC COUPLED SINGLE SUPPLY DRIVER FOR
AD876 10-BIT, 20MSPS ADC
2.34
+
-
R3
2000
R2
1000
100
50
R
T
88.7
75
R1
499
0 TO +2V
+1.6V
+5V
+5V +3.6V
REF*
+1.6V
REF*
AD876*
+5V
5pF
-FS REF
+FS REF
*COMPLETE CIRCUIT
NOT SHOWN
+5V
AD8011
The sour ce is r epr esent ed as a 2V video signal r efer enced t o gr ound. (The equivalent
of a cur r ent gener at or of 0 t o 27mA in par allel wit h t he 75 sour ce r esist or . The
t er minat ion r esist or , R
T
, is select ed such t hat t he par allel combinat ion of R
T
and R1
is 75. The peak-t o-peak swing at t he t er minat ion r esist or is 1V, so t he AD8011
must supply a gain of t wo.
The non-inver t ing input of t he AD8011 is biased t o a common-mode volt age of +1.6V
(well wit hin it 's allowable common-mode r ange). R3 is calculat ed as follows:
When t he sour ce volt age is zer o-volt s, t her e is a cur r ent of 3.0mA flowing t hr ough
R1 (499) and int o 40.6 t o gr ound (t he equivalent par allel combinat ion of t he 75
sour ce and t he 88.7 t er minat ion r esist or is 40.6). The out put of t he AD8011
should be +3.6V under t hese condit ions. This means t hat 2mA must flow t hr ough
R2. Ther efor e R3 (connect ed t o t he +3.6V sour ce) must supply 1.0mA int o t he
summing junct ion (+1.6V), and t her efor e it s value must be 2000.
The input of t he AD876 has a ser ies MOSFET swit ch t hat t ur ns on and off at t he
sampling fr equency. This MOSFET is connect ed t o a hold capacit or int er nal t o t he
device. The on impedance of t he MOSFET is about 50, while t he hold capacit or is
about 5pF.
In a wor st case condit ion, t he input volt age t o t he AD876 will change by a full-scale
value (2V) in one sampling cycle. When t he input MOSFET t ur ns on, t he out put of
t he op amp will be connect ed t o t he char ged hold capacit or t hr ough t he ser ies
r esist ance of t he MOSFET. Wit hout any ot her ser ies r esist ance, t he inst ant aneous
cur r ent t hat flows would be 40mA. This causes set t ling pr oblems for t he op amp.
39
The ser ies 100 r esist or limit s t he inst ant aneous cur r ent t o about 13mA. This
r esist or cannot be made t oo lar ge, or t he high fr equency per for mance will be
affect ed. In pr act ice, t he opt imum value is oft en det er mined exper iment ally.
The sampling MOSFET of t he AD876 is closed for half of each cycle (25ns when
sampling at 20MSPS). Appr oximat ely 7 t ime const ant s ar e r equir ed for set t ling t o
10 bit s. The ser ies 100 r esist or along wit h t he 50 on r esist ance and t he 5pF hold
capacit or for m a t ime const ant of about 750ps. These values leave a comfor t able
mar gin for set t ling. Over all, t he AD8011 pr ovides adequat e buffer ing for t he AD876
ADC wit hout int r oducing dist or t ion gr eat er t han t hat of t he ADC it self.
A 10-Bi t , 40MSP S ADC Low-Di st or t i on Si n gle-Su p p ly ADC Dr i ver Usi n g t h e
AD8041 Op Amp
A DC coupled applicat ion which r equir es t he r ail-t o-r ail out put capabilit y of t he
AD8041 is shown in Figur e 2.35 as a dr iver for t he AD9050 10-bit , 40MSPS single-
supply ADC. The input r ange of t he AD9050 is 1V p-p cent er ed ar ound +3.3V. The
maximum input signal is t her efor e +3.8V. The non-inver t ing input of t he AD8041 is
dr iven wit h a common-mode volt age of +1.65V which is der ived fr om t he unused
differ ent ial input of t he AD9050. This allows t he op amp t o act as a level shift er for
t he gr ound-r efer enced bipolar input 1V p-p signal, wit h unit y gain as det er mined by
t he 1k r esist or s, R1 and R2.
a
DC COUPLED SINGLE-SUPPLY DRIVER FOR
AD9050 10-BIT, 40MSPS ADC
2.35
AD8041
16k
+5V
R2
1000
V
IN
AD9050
+
-
AD820
+
-
+5V
+5V
1000
1000
R1
1000
-0.5 TO +0.5V
0.1 F
0.1 F
8k
+5V
+5V
8k
16k
V
CM
= +1.65V
VIN(B)
VIN(A)
+3.3V
+3.8V
TO +2.8V
+
-
Op amps wit h complement ar y emit t er follower out put s such as t he AD8011
(oper at ing on +5V) gener ally will exhibit high fr equency dist or t ion for sinewaves
wit h full-scale amplit udes of 1V p-p cent er ed at +3.3V. Because of it s common
emit t er out put st age, however , t he AD8041 is capable of dr iving t he AD9050, while
maint aining a dist or t ion floor of gr eat er t han 66dB wit h a 4.9MHz fullscale input
(see Figur e 2.36).
40
a
2.36
FFT OUTPUT OF AD9050 CIRCUIT WITH 4.9MHz INPUT
AND 40MSPS SAMPLING FREQUENCY
0
-10
-100
-60
-70
-80
-90
-40
-50
-30
-20
F
1
= 4.9MHz
FUNDAMENTAL = 0.6dB
2nd HARMONIC = 66.9dB
3rd HARMONIC = 74.7dB
SNR = 55.2dB
NOISE FLOOR = - 86.1dB
ENCODE FREQUENCY = 40MHz
Si n gle-Su p p ly RGB Bu ffer
Op amps such as t he AD8041/AD8042/ and AD8044 can pr ovide buffer ing of RGB
signals t hat include gr ound while oper at ing fr om a single +3V or +5V supply. The
signals t hat dr ive an RGB monit or ar e usually supplied by cur r ent out put DACs
t hat oper at e fr om a single +5V supply. Examples of such ar e t r iple video DACs like
t he ADV7120/21/22 fr om Analog Devices.
Dur ing t he hor izont al blanking int er val, t he cur r ent out put of t he DACs goes t o
zer o, and t he RGB signals ar e pulled t o gr ound by t he t er minat ion r esist or s. If mor e
t han one RGB monit or is desir ed, it cannot simply be connect ed in par allel because
it will pr ovide an addit ional t er minat ion. Ther efor e, buffer ing must be pr ovided
befor e connect ing a second monit or .
Since t he RGB signals include gr ound as par t of t heir dynamic out put r ange, it has
pr eviously been r equir ed t o use a dual supply op amp t o pr ovide t his buffer ing. In
some syst ems, t his is t he only component t hat r equir es a negat ive supply, so it can
be quit e inconvenient t o incor por at e t his mult iple monit or feat ur e.
Figur e 2.37 shows a diagr am of one channel of a single supply gain-of-t wo buffer for
dr iving a second RGB monit or . No cur r ent is r equir ed when t he amplifier out put is
at gr ound. The t er minat ion r esist or at t he monit or helps pull t he out put down at low
volt age levels.
41
a
SINGLE SUPPLY RGB BUFFER OPERATES ON +3V OR +5V
2.37
75
CURRENT OUTPUT
VIDEO DAC
AD8041
75
75
75
1k
1k
R, G, OR B
+3V OR +5V
PRIMARY RGB
MONITOR
SECOND RGB
MONITOR
0mA
TO
27mA
Figur e 2.38 shows t he out put of such a buffer oper at ing fr om a single +3V supply
and dr iven by t he Blue signal of a color bar pat t er n. Not e t hat t he input and out put
ar e at gr ound dur ing t he hor izont al blanking int er val. The RGB signals ar e specified
t o out put a maximum of 700mV peak. The out put of t he AD8041 is +1.4V wit h t he
t er minat ion r esist or s pr oviding a divide-by-t wo. The Red and Gr een signals can be
buffer ed in t he same manner wit h a duplicat ion of t his cir cuit . Anot her possibilit y is
t o use t he quad AD8044 single-supply op amp.
a
2.38
INPUT/OUTPUT OF SINGLE SUPPLY RGB BUFFER
OPERATING ON +3V
V
IN
GND
GND
V
OUT

10
0%
100
90
5s 500mV
500mV

42
Si n gle-Su p p ly Syn c St r i p p er
Some RGB monit or s use only t hr ee cables t ot al and car r y t he synchr onizing signals
and t he Gr een (G) signal on t he same cable. The sync signals ar e pulses t hat go in
t he negat ive dir ect ion fr om t he blanking level of t he G signal.
In some applicat ions, such as pr ior t o digit izing component video signals wit h ADCs,
it is desir able t o r emove or st r ip t he sync por t ion fr om t he G signal. Figur e 2.39 is a
cir cuit using t he AD8041 r unning on a single +5V supply t hat per for ms t his
funct ion.
a
SINGLE SUPPLY VIDEO SYNC STRIPPER
2.39
AD8041
75
R1
1k
+5V
75
75
R2
1k
V
IN V
OUT
0.8V
(2 X V
BLANK
)
V
BLANK
GREEN WITH SYNC
0V
+0.4V
GREEN WITHOUT SYNC
0V
+
-
The upper wavefor m in Figur e 2.40 shows t he Gr een plus sync signal t hat is out put
fr om an ADV7120, a single supply t r iple video DAC. Because t he DAC is single
supply, t he lowest level of t he sync t ip is at gr ound or slight ly above. The AD8041 is
set fr om a gain of t wo t o compensat e for t he divide-by-t wo of t he out put
t er minat ions. The r efer ence volt age for R1 should be t wice t he DC blanking level of
t he G signal. If t he blanking level is at gr ound and t he sync t ip is negat ive, as in
some dual supply syst ems, t hen R1 can be t ied t o gr ound. In eit her case, t he out put
will have t he sync r emoved and have t he blanking level at gr ound.
43
a
2.40
INPUT/OUTPUT OF SINGLE SUPPLY SYNC STRIPPER
10
0%
100
90
10s 500mV
500mV
V
IN
V
OUT

A Si n gle-Su p p ly Vi d eo Li n e Dr i ver wi t h Zer o-Volt Ou t p u t ,
Ea m on Na sh
When oper at ed wit h a single supply, t he AD8031 80MHz r ail-t o-r ail volt age
feedback op amp has opt imum dist or t ion per for mance when t he signal has a
common mode level of Vs/2, and when t her e is about 500mV of headr oom t o each
r ail. If low dist or t ion is r equir ed for signals which swing close t o gr ound, an emit t er
follower can be used at t he op amp out put .
Figur e 2.41 shows t he AD8031 configur ed as a single supply gain-of-t wo line dr iver .
Wit h t he out put dr iving a back t er minat ed 50 line, t he over all gain is unit y fr om
Vin t o Vout . In addit ion t o minimizing r eflect ions, t he 50 back t er minat ion r esist or
pr ot ect s t he t r ansist or fr om damage if t he cable is shor t cir cuit ed. The emit t er
follower , which is inside t he feedback loop, ensur es t hat t he out put volt age fr om t he
AD8031 st ays about 700mV above gr ound. Using t his cir cuit excellent dist or t ion is
obt ained even when t he out put signal swings t o wit hin 50mV of gr ound. The cir cuit
was t est ed at 500kHz and 2MHz using a single +5V supply. For t he 500kHz signal,
THD was 68dBc wit h a peak-t o-peak swing at Vout of 1.85V (50mV t o +1.9V). This
cor r esponds t o a signal at t he emit t er follower out put of 3.7V p-p (100mV t o 3.8V).
Dat a was t aken wit h an out put signal of 2MHz, and a THD of 55dBc was measur ed
wit h a Vout of 1.55V p-p (50mV t o 1.6V).
44
a
LOW DISTORTION ZERO-VOLT OUTPUT
SINGLE SUPPLY LINE DRIVER USING AD8031
2.41
2.49k
V
IN
2N3904
+
-
AD8031
V
OUT
+
+5V
2.49k
200
49.9
49.9
49.9
10 F
0.1 F
THD = 68dBc @ 500kHz FOR
V
OUT
= 1.85V
p-p
(50mV TO 1.9V)
THD = 55dBc @ 2MHz FOR
V
OUT
= 1.55V
p-p
(50mV TO 1.6V)
This cir cuit can also be used t o dr ive t he analog input of a single supply high speed
ADC whose input volt age r ange is gr ound-r efer enced. In t his case, t he emit t er of t he
ext er nal t r ansist or is connect ed dir ect ly t o t he ADC input . A peak posit ive volt age
swing of appr oximat ely 3.8V is possible befor e significant dist or t ion begins t o occur .
Hea d r oom Con si d er a t i on s i n AC-Cou p led Si n gle-Su p p ly Ci r cu i t s
The AC coupling of ar bit r ar y wavefor ms can act ually int r oduce pr oblems which
dont exist at all in DC coupled or DC r est or ed syst ems. These pr oblems have t o do
wit h t he wavefor m dut y cycle, and ar e par t icular ly acut e wit h signals which
appr oach t he r ails, as t hey can in low supply volt age syst ems which ar e AC coupled.
In Figur e 2.42 (A), an example of a 50% dut y cycle squar e wave of about 2Vp-p level
is shown, wit h t he signal swing biased symmet r ically bet ween t he upper and lower
clip point s of a 5V supply amplifier . Assume t hat t he amplifier has a complement ar y
emit t er follower out put and can only swing t o t he limit ed DC levels as mar ked,
about 1V fr om eit her r ail. In cases (B) and (C), t he dut y cycle of t he input wavefor m
is adjust ed t o bot h low and high dut y cycle ext r emes while maintaining the same
peak-to-peak input level. At t he amplifier out put , t he wavefor m is seen t o clip eit her
negat ive or posit ive, in (B) and (C), r espect ively.
45
WAVEFORM DUTY CYCLE TAXES
HEADROOM IN AC COUPLED AMPLIFIERS
2.42
a
(A)
50%
DUTY CYCLE
NO CLIPPING
(B)
LOW
DUTY CYCLE
CLIPPED
POSITIVE
(C)
HIGH
DUTY CYCLE
CLIPPED
NEGATIVE
2V
p-p
2V
p-p
2V
p-p
4.0V (+) CLIPPING
2.5V
1.0V (-) CLIPPING
4.0V (+) CLIPPING
2.5V
1.0V (-) CLIPPING
4.0V (+) CLIPPING
2.5V
1.0V (-) CLIPPING
Since st andar d video wavefor ms do var y in dut y cycle as t he scene changes, t he
point is made t hat low dist or t ion oper at ion on AC coupled single supply st ages must
t ake t he dut y cycle headr oom degr adat ion effect int o account . If a st age has a 3Vp-p
out put swing available befor e clipping, and it must cleanly r epr oduce an arbitrary
wavefor m, t hen t he maximum allowable amplit ude is less t han 1/2 of t his 3Vp-p
swing, t hat is <1.5Vp-p. An example of violat ing t his cr it er ia is t he 2Vp-p wavefor m
of Figur e 2.42, which is clipping for bot h t he high and low dut y cycles. Not e t hat t he
cr it er ia set down above is based on avoiding har d clipping, while subt le dist or t ion
incr eases may in fact t ake place at lower levels. This suggest s an even mor e
conser vat ive cr it er ia for lowest dist or t ion oper at ion such as composit e NTSC video
amplifier s.
Figur e 2.43 shows a single supply gain-of-t wo composit e video line dr iver using t he
AD8041. Since t he sync t ips of a composit e video signal ext end below gr ound, t he
input must be AC coupled and shift ed posit ively t o pr event clipping dur ing negat ive
excur sions. The input is t er minat ed in 75 and AC coupled via t he 47F t o a volt age
divider t hat pr ovides t he DC bias point t o t he input . Set t ing t he opt imal common-
mode bias volt age r equir es some under st anding of t he nat ur e of composit e video
signals and t he video per for mance of t he AD8041.
46
a
SINGLE SUPPLY AC COUPLED COMPOSITE VIDEO
LINE DRIVER HAS G = 0.06% AND = 0.06
2.43
AD8041
+
-
+5V
7.87k
R
BIAS
COMPOSITE
VIDEO
0.1 F
R
BIAS
OPTIMIZES
V
CM
= +2.2V
+
+
+
1000 F
75
10 F
0.1 F
4.99k
V
CM
4.99k
10 F
+
75
47 F
1k
1k
220 F
+
75
V
OUT
As discussed above, signals of bounded peak-t o-peak amplit ude t hat var y in dut y
cycle r equir e lar ger dynamic swing capabilit y t han t heir peak-t o-peak amplit ude
aft er AC coupling. As a wor st case, t he dynamic signal swing r equir ed will appr oach
t wice t he peak-t o-peak value. The t wo bounding cases ar e for a dut y cycle t hat is
most ly low, but occasionally goes high at a fr act ion of a per cent dut y cycle, and vice
ver sa.
Composit e video is not quit e t his demanding. One bounding ext r eme is for a signal
t hat is most ly black for an ent ir e fr ame, but occasionally has a whit e (full int ensit y),
minimum widt h spike at least once per fr ame.
The ot her ext r eme is for a video signal t hat is full whit e ever ywher e. The blanking
int er vals and sync t ips of such a signal will have negat ive going excur sions in
compliance wit h composit e video specificat ions. The combinat ion of hor izont al and
ver t ical blanking int er vals limit such a signal t o being at it s highest level (whit e) for
only about 75% of t he t ime.
As a r esult of t he dut y cycle var iat ions bet ween t he t wo ext r emes pr esent ed above, a
1V p-p composit e video signal t hat is mult iplied by a gain-of-t wo r equir es about 3.2V
p-p of dynamic volt age swing at t he out put for t he op amp t o pass a composit e video
signal of ar bit r ar y dut y cycle wit hout dist or t ion.
The AD8041 not only has ample signal swing capabilit y t o handle t he dynamic
r ange r equir ed, but also has excellent differ ent ial gain and phase when buffer ing
t hese signals in an AC coupled configur at ion.
To t est t his, t he differ ent ial gain and phase wer e measur ed for t he AD8041 while
t he supplies wer e var ied. As t he lower supply is r aised t o appr oach t he video signal,
t he fir st effect is t hat t he sync t ips become compr essed befor e t he differ ent ial gain
47
and phase ar e adver sely affect ed. Thus, t her e must be adequat e swing in t he
negat ive dir ect ion t o pass t he sync t ips wit hout compr ession.
As t he upper supply is lower ed t o appr oach t he video, t he differ ent ial gain and phase
wer e not significant ly adver sely affect ed unt il t he differ ence bet ween t he peak video
out put and t he supply r eached 0.6V. Thus, t he highest video level should be kept at
least 0.6V below t he posit ive supply r ail.
Taking t he above int o account , it was found t hat t he opt imal point t o bias t he non-
inver t ing input was at +2.2V DC. Oper at ing at t his point , t he wor st case differ ent ial
gain was 0.06% and t he differ ent ial phase 0.06.
The AC coupling capacit or s used in t he cir cuit at fir st glance appear quit e lar ge. A
composit e video signal has a lower fr equency band edge of 30Hz. The r esist ances at
t he var ious AC coupling point s - especially at t he out put - ar e quit e small. In or der
t o minimize phase shift s and baseline t ilt , t he lar ge value capacit or s ar e r equir ed.
For video syst em per for mance t hat is not t o be of t he highest qualit y, t he value of
t hese capacit or s can be r educed by a fact or of up t o five wit h only a slight obser vable
change in t he pict ur e qualit y.
Si n gle-Su p p ly AC Cou p led Si n gle-En d ed -t o-Di ffer en t i a l Dr i ver
The cir cuit shown in Figur e 2.44 pr ovides a flexible solut ion t o differ ent ial line
dr iving in a single-supply applicat ion and ut ilizes t he dual AD8042. The basic
oper at ion of t he cr oss-coupled configur at ion has been descr ibed ear lier in t his
sect ion. The input , V
IN
, is a single-ended signal t hat is capacit ively coupled int o t he
feedfor war d r esist or , R1. The non-inver t ing input s of each half of t he AD8042 ar e
biased at +2.5V. The gain fr om single-ended input t o differ ent ial out put is equal t o
2R2/R1. The gain can be var ied by changing one r esist or (eit her R1 or R2).
a
SINGLE SUPPLY AC COUPLED DIFFERENTIAL DRIVER
2.44
+
-
R1
1k
1k
0.1 F
0.1 F
V
IN
U = AD8042
+2.5V
2.49k
2.49k
1/2 U
+
-
1/2 U
+5V
+5V
R2
1k
1k
1k
1k
2V
IN

R2
R1
48
HI GH SP EED VI DEO MULTI P LEXI NG WI TH OP AMP S
UTI LI ZI NG DI SABLE FUNCTI ON
A common video cir cuit funct ion is t he mult iplexer , a st age which select s one of "N"
video input s and t r ansmit s a buffer ed ver sion of t he select ed signal t o t he out put . A
number of video op amps (AD810, AD813, AD8013) have a disable mode which,
when act ivat ed by applying t he appr opr iat e level t o a pin on t he package, disables
t he op amp out put st age and dr ops t he power t o a lower value.
In t he case of t he AD8013 (t r iple cur r ent -feedback op amp), asser t ing any one of t he
disable pins about 1.6V fr om t he negat ive supply will put t he cor r esponding
amplifier int o a disabled, power ed-down st at e. In t his condit ion, t he amplifier 's
quiescent cur r ent dr ops t o about 0.3mA, it s out put becomes a high impedance, and
t her e is a high level of isolat ion fr om t he input t o t he out put . In t he case of t he gain-
of-t wo line dr iver , for example, t he impedance at t he out put node will be about equal
t o t he sum of t he feedback and feedfor war d r esist or s (1.6k) in par allel wit h about
12pF capacit ance. Input -t o-out put isolat ion is about 66dB at 5MHz.
Leaving t he disable pin disconnect ed (float ing) will leave t he cor r esponding amplifier
oper at ional, in t he enabled st at e. The input impedance of t he disable pin is about
40k in par allel wit h 5pF. When dr iven t o 0V, wit h t he negat ive supply at 5V,
about 100A flows int o t he disable pin.
When t he disable pins ar e dr iven by CMOS logic, on a single +5V supply, t he disable
and enable t imes ar e about 50ns. When oper at ed on dual supplies, level shift ing will
be r equir ed fr om st andar d logic out put s t o t he disable pins.
The AD8013's input st ages include pr ot ect ion fr om t he lar ge differ ent ial volt ages
t hat may be applied when disabled. Int er nal clamps limit t his volt age t o about 3V.
The high input -t o-out put isolat ion will be maint ained for volt ages below t his limit .
Wir ing t he amplifier out put s t oget her as shown in Figur e 2.45 will for m a 3:1
mult iplexer wit h about 50ns swit ching t ime bet ween channels. The 0.1dB
bandwidt h of t he cir cuit is 35MHz, and t he OFF channel isolat ion is 60dB at
10MHz. The simple logic level-shift ing cir cuit shown on t he diagr am does not
significant ly affect swit ching t ime.
The r esist or s wer e chosen as follows. The feedback r esist or R2 of 845 was chosen
fir st for opt imum bandwidt h of t he AD8013 cur r ent feedback op amp. When any
given channel is ON, it must dr ive bot h t he t er minat ion r esist or R
L
, and t he net
dummy r esist ance, R
X
/2, wher e R
X
is an equivalent ser ies r esist ance equal t o R1 +
R2 + R3. To pr ovide a net over all gain of unit y plus an effect ive sour ce r esist ance of
75, t he ot her r esist or values must be as shown.
49
a
3:1 VIDEO MULTIPLEXER SWITCHES IN 50ns
2.45
+
-
FROM CMOS
75
75
-5V
75
V
OUT
+
-
+
-
R3
84
U1 = AD8013
DISABLE
DRIVERS
(ONE SHOWN)
1 = ENABLE
0 = DISABLE
R2, 845
R1, 665
665
75
84
84
845
845
DISABLE 1
DISABLE 2
DISABLE 3
+5V
665
V
IN
1
V
IN
2
V
IN
3
+5V
-5V
TO
DISABLE
8k
4k 4k
10k
2N3904
1/3 U1
1/3 U1
1/3 U1
Configur ing t wo amplifier s as unit y gain follower s and using t he t hir d t o set t he
gain r esult s in a high per for mance 2:1 mult iplexer as shown in Figur e 2.46. The
cir cuit t akes advant age of t he ver y low cr osst alk bet ween t he amplifier s and
achieves t he OFF channel isolat ion shown in Figur e 2.47. The differ ent ial gain and
phase per for mance of t he cir cuit is 0.03% and 0.07, r espect ively.
a
2:1 VIDEO MULTIPLEXER
2.46
+
-
2k
V
OUT
V
IN
1
U1 = AD8013
1/3U1
+
-
+5V
1/3U1
+
-
1/3U1
2k
V
IN
2
75
75
-5V
845
845
DISABLE 1
DISABLE 2
10
10
50
a
2.47
2:1 MULTIPLEXER ON-CHANNEL GAIN AND MUX
OFF-CHANNEL FEEDTHROUGH VS. FREQUENCY
FREQUENCY - Hz
1G 1M 100M
-8
-1
-2
-3
-4
-5
-6
-7
-40
-50
-60
-70
-80
0
1
2
-30
10M
GAIN
FEEDTHROUGH
F
E
E
D
T
H
R
O
U
G
H

-

d
B
C
L
O
S
E
D
-
L
O
O
P

G
A
I
N

-

d
B
VI DEO P ROGRAMMABLE GAI N AMP LI FI ER USI NG THE
AD813 TRI P LE CURRENT FEEDBACK OP AMP
Closely r elat ed t o t he mult iplexer s descr ibed above is a pr ogr ammable gain video
amplifier , or PGA, as shown in Figur e 2.48. In t he case of t he AD813, t he individual
op amps ar e disabled by pulling t he disable pin about 2.5V below t he posit ive
supply. This put s t he cor r esponding amplifier in it s power ed down st at e. In t his
condit ion, t he amplifier 's quiescent supply cur r ent dr ops t o about 0.5mA, it s out put
becomes a high impedance, and t her e is a high level of isolat ion bet ween t he input
and t he out put . Leaving t he disable pin disconnect ed (float ing) will leave t he
amplifier oper at ional, in t he enabled st at e. The input impedance of t he disable pins
is about 35k in par allel wit h 5pF. When gr ounded, about 50A flows out of a
disable pin when oper at ing on 5V supplies. The swit ching t hr eshold is such t hat
t he disable pins can be dr iven dir ect ly fr om +5V CMOS logic wit h no level shift ing
(as was r equir ed in t he pr evious example).
51
PROGRAMMABLE GAIN AMPLIFIER USING
AD813 TRIPLE CFB OP AMP
2.48 a
-
+
V
IN
R1
75
A
0
L
H
L
H
-
+
+
-
SELECT 1
U1
AD813
R2
649
R4
301
SELECT 2
SELECT 3
R5, 100
-5V
+5V
OUTPUT TABLE
A
1
L
L
H
H
+5V
U2
74HC238
A
0
A
1
A
2
E1
E2
E3
Y
1
R3, 649
Y
2
Y
0
1
2
3
NOTE: DECOUPLING
NOT SHOWN
V
OUT
/ V
IN
1
2, (1 + R2/R3)
4, (1 + R4/R5)
0, (OFF)
V
OUT
750
Wit h a t wo-line digit al cont r ol input , t his cir cuit can be set up t o pr ovide 3 differ ent
gain set t ings. This makes it a useful cir cuit in var ious syst ems which can employ
signal nor malizat ion or gain r anging pr ior t o A/D conver sion, such as CCD syst ems,
ult r asound, et c. The gains can be binar y r elat ed as her e, or t hey can be ar bit r ar y.
An ext r emely useful feat ur e of t he AD813 CFB cur r ent feedback amplifier is t he fact
t hat t he bandwidt h does not r educe as gain is incr eased. Inst ead, it st ays r elat ively
const ant as gain is r aised. Thus mor e useful bandwidt h is available at t he higher
pr ogr ammed gains t han would be t r ue for a fixed gain-bandwidt h pr oduct VFB
amplifier t ype.
In t he cir cuit , channel 1 of t he AD813 is a unit y gain channel, channel 2 has a gain
of 2, and channel 3 a gain of 4, while t he four t h cont r ol st at e is OFF. As is indicat ed
by t he t able, t hese gains can var ied by adjust ment of t he R2/R3 or R4/R5 r at ios. For
t he gain r ange and values shown, t he PGA will be able t o maint ain a 3dB
bandwidt h of about 50MHz or mor e for loading as shown (a high impedance load of
1k or mor e is assumed). Fine t uning t he bandwidt h for a given gain set t ing can be
accomplished by lower ing t he r esist or values at t he higher gains, as shown in t he
cir cuit , wher e for G=1, R1=750, for G=2, R2=649, and for G=4, R4=301.
VI DEO MULTI P LEXERS AND CROSSP OI NT SWI TCHES
Tr adit ional CMOS swit ches and mult iplexer s suffer fr om sever al disadvant ages at
video fr equencies. Their swit ching t ime (t ypically 100ns or so) is not fast enough for
t oday's applicat ions, and t hey r equir e ext er nal buffer ing in or der t o dr ive t ypical
video loads. In addit ion, t he small var iat ion of t he CMOS swit ch "on" r esist ance wit h
signal level (called R
on
modulation) int r oduces unwant ed dist or t ion and degr adat ion
52
in differ ent ial gain and phase. Mult iplexer s based on complement ar y bipolar
t echnology offer a bet t er solut ion at video fr equencies.
Funct ional block diagr ams of t he AD8170/8174/8180/8182 bipolar video mult iplexer
ar e shown in Figur e 2.49. These devices offer a high degr ee of flexibilit y and ar e
ideally suit ed t o video applicat ions, wit h excellent differ ent ial gain and phase
specificat ions. Swit ching t ime for all devices in t he family is 10ns t o 0.1%. The
AD8170/8174 muxes include an on-chip cur r ent feedback op amp out put buffer
whose gain can be set ext er nally. Off channel isolat ion and cr osst alk ar e t ypically
gr eat er t han 80dB for t he ent ir e family. Key specificat ions ar e shown in Figur e 2.50.
AD8170/8174/8180/8182 BIPOLAR VIDEO MULTIPLEXERS
+1 +1
AD8170
LOGIC
SELECT
IN0
+Vs
IN1
-V
IN
V
OUT

-Vs
GND
1
2
3
4
8
7
6
5
+ _

+1
+1
DECODER
7
AD8180
IN0
GND
IN1
+Vs
SELECT
ENABLE
OUT
-V
s
1
2
3
4
8
6
5
7
+1
AD8174
LOGIC
IN0
GND
IN1
+Vs
IN2
GND
IN3
A0
-V
IN
V
OUT

-Vs
S/D
ENABLE
A1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+1
+1
+1
+
_
2
2

AD8182
IN0A
GND
IN1A
+Vs
IN1B
GND
IN0B
SELECT A
ENABLE A
OUT A
-V
s
OUT B
ENABLE B
SELECT B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+1
+1
DECODER
+1
+1
DECODER
a 2.49
AD817X AND AD818X MULTIPLEXER KEY SPECIFICATIONS
n n 10ns Switching Time
n n Wide Bandwidth (-3dB BW):
u u 200MHz (AD817X)
u u 600MHz (AD818X)
n n Gain Flatness (0.1dB):
u u 80MHz (AD817X)
u u 150MHz (AD818X)
n n 0.02% / 0.02Differential Gain and Phase (AD817X, R
L
= 150 )
53
n n 0.02% / 0.03Differential Gain and Phase (AD818X, R
L
= 1k )
n n Off-Channel Isolation and Crosstalk > 80dB @ 10MHz
n n Low Power (5V Supplies):
u u AD8170 - 65mW u u AD8174 - 85mW
u u AD8180 - 35mW u u AD8182 - 70mW
a 2.50
Figur e 2.51 shows an applicat ion cir cuit for t hr ee AD8170 2:1 muxes wher e t he RGB
monit or can be swit ched bet ween t wo comput er s. The AD8174 4:1 mux is used in
Figur e 2.52 t o allow a single high speed ADC t o digit ize t he RGB out put s of a
scanner . Figur e 2.53 shows t wo AD8174 4:1 muxes expanded int o an 8:1 mux.
IN0
IN1
IN0
IN1
IN0
IN1
a
DUAL SOURCE RGB MULTIPLEXER USING THREE 2:1 MUXES
2.51
THREE AD8170 2:1 MUXES
CHANNEL
SELECT
MONITOR
R
G
B
COMPUTER
R G B
COMPUTER
R G B
54
a
DIGITIZING RGB SIGNALS WITH ONE ADC AND A 4:1 MUX
2.52
ADC
SCANNER
R
B
G
IN0
IN1
IN2
IN3
4:1
MUX
A0
A1
CHANNEL SELECT
AD8174
a
EXPANDING TWO 4:1 MUXES INTO AN 8:1 MUX
2.53
TWO AD8174
4:1 MUXES
CHANNEL SELECT
VIDEO
INPUTS
VIDEO
OUTPUT
IN0
IN1
IN2
IN3
IN0
IN1
IN2
IN3
A0
A1
A0
A1
EN
EN
The AD8116 ext ends t he concept s above t o yield a 1616 buffer ed video cr osspoint
swit ch mat r ix (Figur e 2.54). The 3dB bandwidt h is gr eat er t han 200MHz, and t he
0.1dB gain flat ness ext ends t o gr eat er t han 40MHz. Channel swit ching t ime is less
t han 30ns t o 0.1%. Cr osst alk is 70dB and isolat ion is 90dB (bot h measur ed at
10MHz). Differ ent ial gain and phase is 0.01% and 0.01 for a 150 load. Tot al
power dissipat ion is 900mW on 5V supplies.
55
The AD8116 includes out put buffer s which can be put int o a high impedance st at e
for par alleling cr osspoint st ages so t hat t he off channels do not load t he out put bus.
The channel swit ching is per for med via a ser ial digit al cont r ol which can
accommodat e "daisy chaining" of sever al devices. The AD8116 is packaged in a 128-
pin TQFP package. Key specificat ions for t he device ar e summar ized in Figur e 2.55.
AD8116 1616 BUFFERED VIDEO CROSSPOINT SWITCH
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
+1
80 Bit SHIFT REG.
PARALLEL LATCH
DECODE
16x5:16 Decoders
OUTPUT
BUFFER
RESET
80
C ENABLE
LATCH
SERIAL
DATA IN
SERIAL
CLOCK
SERIAL
CLOCK
SERIAL
DATA OUT
LATCH
C ENABLE
RESET
16 ANALOG
INPUTS
16 ANALOG
OUTPUTS
AD8116
SWITCH
MATRIX
S
E
T

I
N
D
I
V
D
U
A
L

O
R
R
E
S
E
T

A
L
L

O
U
T
P
U
T
S







T
O

"
O
F
F
"
E
N
A
B
L
E
/
D
I
S
A
B
L
E
80
256
16
a 2.54
56
AD8116 CROSSPOINT SWITCH KEY SPECIFICATIONS
n n 1616 Buffered Inputs and Outputs
n n Output Buffer Disable Feature Allows Expansion
n n 3dB Bandwidth 200MHz, 0.1dB Bandwidth 40MHz
n n 30ns Switching to 0.1%
n n Differential Gain 0.01%, Differential Phase 0.01
n n Power Dissipation: 900mW (5V Supplies)
n n 128-pin TQFP, 0.36 Square Inches Area
a 2.55
HI GH P OWER LI NE DRI VERS AND ADSL
ADSL (Asymmet r ic Digit al Subscr iber Line) uses t he cur r ent subscr iber line
connect ion t o t he cent r al office t o t r ansmit dat a as high as 8Mbps, almost 300 t imes
t he speed of t he fast est t r adit ional modem. ADSL uses t he ent ir e bandwidt h
(appr oximat ely 1MHz) of t he connect ion in addit ion for t he modulat ion scheme
called Discr et e Mult i Tone (DMT).
Alt hough high-speed fiber links alr eady exist , it is st ill t oo difficult and expensive t o
br ing t hem dir ect ly t o ever y r esidence. ADSL uses t he exist ing infr ast r uct ur e for
"t he last mile" connect ing t he home and t he local cent r al office (which alr eady has a
high-speed fiber link t o t he nat ional net wor k).
Many applicat ions ar e uneven (asymmet r ic) in t heir bandwidt h needs - sending
mor e infor mat ion in one dir ect ion t han t he ot her . Typically, a user will r equest a
video channel, ask for infor mat ion fr om a cent r al dat abase, or view complex
gr aphical images on a web page. All of t hese applicat ions r equir e consider able
bandwidt h. In cont r ast , t he user may only send commands or files back up t o t he
ser ver . Realizing t his, ADSL was designed t o deliver a bigger downst r eam capacit y
t o t he home, while having a smaller t wo-way capacit y.
Key t o t he ADSL syst em is t he r equir ement for a low-dist or t ion differ ent ial dr ive
amplifier which deliver s appr oximat ely 40V p-p int o a 60 differ ent ial load
impedance. The AD815 dual high cur r ent dr iver can deliver 40V p-p differ ent ial int o
a 50 load (cor r esponding t o 400mA peak cur r ent !) using t he applicat ion cir cuit
shown in Figur e 2.56. Low har monic dist or t ion is also r equir ed for ADSL
applicat ions, since it affect s syst em bit er r or r at es. The t ypical dist or t ion of t he
device is shown in Figur e 2.57 for 50 and 200 differ ent ial loads.
57
a
2.56
ADSL DIFFERENTIAL LINE DRIVER USING THE AD815
AMP1
+15V
-15V
499
RL
120
125
499
V
OUT
=
40Vp-p
VIN =
4Vp-p
1/2
AD815
G = +10
100
100
AMP2
VD =
40Vp-p
1:2
TRANSFORMER
R1 = 15
R2 = 15
1/2
AD815
a
2.57
THD VS. FREQUENCY FOR AD815 DIFFERENTIAL DRIVER
FREQUENCY - Hz
-40
-50
-110
100 10M 1k 10k 100k 1M
-60
-70
-80
-90
-100
VS = 15V
G = +10
VOUT = 40V p-p
RL = 50
(DIFFERENTIAL)
RL = 200
(DIFFERENTIAL)
T
O
T
A
L

H
A
R
M
O
N
I
C

D
I
S
T
O
R
T
I
O
N

-

d
B
c
Ther e ar e t hr ee AD815 models, t wo ar e available in a 15-pin power package, and
t he t hir d as a 24-pin t her mally enhanced SOIC. The 15-pin power package
(AD815AY-t hr ough hole and AD815AVR-sur face mount ) has a low t her mal
r esist ance (
J A
= 41C/W) which can be r educed consider ably ( t o
J A
= 16 C/W) by
connect ing t he package t o an ar ea of copper which act s as a heat sink. The AD815
incor por at es a t her mal shut down cir cuit t o pr ot ect t he die fr om t her mal over load.
58
The AD815 also has applicat ions as a gener al pur pose high cur r ent coil,
t r ansfor mer , or t wist ed pair cable dr iver , a CRT conver gence adjust ment cont r ol, or
a video signal dist r ibut ion amplifier . Each amplifier in t he AD815 is capable of
dr iving 6 back-t er minat ed 75 video loads wit h a differ ent ial gain and phase of
0.05% and 0.45 r espect ively.
HI GH SP EED P HOTODI ODE P REAMP S
Phot odiodes gener at e a small cur r ent which is pr opor t ional t o t he level of
illuminat ion. They have many applicat ions r anging fr om pr ecision light met er s t o
high-speed fiber opt ic r eceiver s.
The equivalent cir cuit for a phot odiode is shown in Figur e 2.58. One of t he st andar d
met hods for specifying t he sensit ivit y of a phot odiode is t o st at e it s shor t cir cuit
phot ocur r ent (I
sc
) at a given light level fr om a well defined light sour ce. The most
commonly used sour ce is an incandescent t ungst en lamp r unning at a color
t emper at ur e of 2850K. At 100fc (foot -candles) illuminat ion (appr oximat ely t he light
level on an over cast day), t he shor t cir cuit cur r ent is usually in t he picoamps t o
hundr eds of micr oamps r ange for small ar ea (less t han 1mm
2
) diodes.
a
2.58
PHOTODIODE EQUIVALENT CIRCUIT
INCIDENT
LIGHT
IDEAL
DIODE
PHOTO
CURRENT
R
S
<< R
SH
R
SH
(T)
C
J
100k TO
100G
The shor t cir cuit cur r ent is ver y linear over 6 t o 9 decades of light int ensit y, and is
t her efor e oft en used as a measur e of absolut e light levels. The open cir cuit for war d
volt age dr op acr oss t he phot odiode var ies logar it hmically wit h light level, but ,
because of it s lar ge t emper at ur e coefficient , t he diode volt age is seldom used as an
accur at e measur e of light int ensit y.
The shunt r esist ance is usually in t he or der of sever al hundr ed k t o mor e t han
1G at r oom t emper at ur e, and decr eases by a fact or of t wo for ever y 10C r ise in
59
t emper at ur e. Diode capacit ance is a funct ion of junct ion ar ea and t he diode bias
volt age. A value of 10 t o 50pF at zer o bias is t ypical for small ar ea diodes.
Phot odiodes may eit her be oper at ed wit h zer o bias (photovoltaic mode) or r ever se
bias (photoconductive mode) as shown in Figur e 2.59. The most pr ecise linear
oper at ion is obt ained in t he phot ovolt aic mode, while higher swit ching speeds ar e
r ealizable when t he diode is oper at ed in t he phot oconduct ive mode. Under r ever se
bias condit ions, a small amount of cur r ent called dark current will flow even when
t her e is no illuminat ion. Ther e is no dar k cur r ent in t he phot ovolt aic mode. In t he
phot ovolt aic mode, t he diode noise is basically t he t her mal noise gener at ed by t he
shunt r esist ance. In t he phot oconduct ive mode, shot noise due t o conduct ion is an
addit ional sour ce of noise. Phot odiodes ar e usually opt imized dur ing t he design
pr ocess for use in eit her t he phot ovolt aic mode or t he phot oconduct ive mode, but not
bot h.
a
2.59
PHOTODIODE MODES OF OPERATION
-V
BIAS
PHOTOVOLTAIC
PHOTOCONDUCTIVE
Zero Bias
No Dark Current
Precision Applications
Low Noise (Johnson)
Reverse Bias
Dark Current Exists
High Speed Applications
Higher Noise (Johnson + Shot))
Opt imizing phot odiode pr eamplifier s is pr obably one of t he most challenging of
design pr oblems, especially if high bandwidt h and dir ect coupling is r equir ed. Figur e
2.60 shows a basic phot odiode pr eamp designed wit h an op amp connect ed as a
cur r ent -t o-volt age conver t er .
60
a
2.60
HIGH BANDWIDTH PHOTODIODE PREAMP
EQUIVALENT CIRCUIT
SIGNAL BW =
I
D
= I
S
+ I
DARK
C
1
= C
D
+ C
IN
R
SH
>>R
2
R
SH
C
D I
D
-V
BIAS
C
IN
1
2 R
2
C
2

C
2
R
2
I
B
V
N
FOR R2 = 100k
I
D
= 100 A
V
OUT
= 10V
f
u
V
OUT
= R
2
I
D
f
u
= OP AMP GBW PRODUCT
The sensit ivit y of t he cir cuit is det er mined by t he amount of phot odiode cur r ent
mult iplied by t he feedback r esist or R2. The key par amet er s of t he diode (see Figur e
2.61) ar e it s sensit ivit y (out put cur r ent as a funct ion of illuminat ion level), dar k
cur r ent (t he amount of cur r ent which flows due t o t he r ever se bias volt age when t he
diode is not illuminat ed), r iset ime, shunt capacit ance, and shunt r esist ance.
The key par amet er s of t he op amp ar e it s input volt age and cur r ent noise, bias
cur r ent , unit y gain-bandwidt h pr oduct , f
u
, and input capacit ance, C
in
.
The HP 5082-4204 PIN Phot odiode will be used as an example for our discussion. It s
char act er ist ics ar e given in Figur e 2.61. It is t ypical of many commer cially available
PIN phot odiodes. As in most high-speed phot odiode applicat ions, t he diode is
oper at ed in t he r ever se-biased or photoconductive mode. This gr eat ly lower s t he
diode junct ion capacit ance, but causes a small amount of dark current t o flow even
when t he diode is not illuminat ed (we will show a cir cuit which compensat es for t he
dar k cur r ent er r or lat er in t he sect ion).
HP 5082-4204 PHOTODIODE
n n Sensitivity: 350A @ 1mW, 900nm
n n Maximum Linear Output Current: 100A
n n Area: 0.002cm
2
(0.2mm
2
)
n n Capacitance: 4pF @ 10V reverse bias
61
n n Shunt Resistance: 10
11

n n Risetime: 10ns
n n Dark Current: 600pA @ 10V reverse bias
a 2.61
This phot odiode is linear wit h illuminat ion up t o appr oximat ely 50 t o 100A of
out put cur r ent . The dynamic r ange is limit ed by t he t ot al cir cuit noise and t he diode
dar k cur r ent (assuming no dar k cur r ent compensat ion).
Using t he simple cir cuit shown in Figur e 2.60, assume t hat we wish t o have a full
scale out put of 10V for a diode cur r ent of 100A. This det er mines t he value of t he
feedback r esist or R2 t o be 10V/100A = 100k.
An a lysi s of F r equ en cy Resp on se a n d St a bi li t y
The phot odiode pr eamp model is t he classical second-or der syst em shown in Figur e
2.62, wher e t he I/V conver t er has a t ot al input capacit ance C1 (t he sum of t he diode
capacit ance and t he op amp input capacit ance). The shunt r esist ance of t he
phot odiode is neglect ed since it is much gr eat er t han R2, t he feedback r esist or .
a
COMPENSATING FOR INPUT CAPACITANCE IN A
CURRENT-TO-VOLTAGE CONVERTER USING VFB OP AMP
2.62
+
-
C2
R2
C1
VFB
i
|A(s)|
1
f
p
f
x
f
u
f
COMPENSATED
UNCOMPENSATED
f
p

=
f
x
=
f
x
= f
p
f
u
C2 =
FOR 45 PHASE MARGIN
1
1
2 R2C1
2 R2C2
C1
2 R2 f
u
The net input capacit ance, C1, for ms a pole at a fr equency f
p
in t he noise gain
t r ansfer funct ion as shown in t he Bode plot .
62
f
p
R C
=
1
2 2 1
.
Not e t hat we ar e neglect ing t he effect s of t he compensat ion capacit or C2 and ar e
assuming t hat it is small r elat ive t o C1 and will not significant ly affect t he pole
fr equency f
p
when it is added t o t he cir cuit . In most cases, t his appr oximat ion yields
r esult s which ar e close enough, consider ing t he ot her var iables in t he cir cuit .
If left uncompensat ed, t he phase shift at t he fr equency of int er sect ion, f
x
, will cause
inst abilit y and oscillat ion. Int r oducing a zer o at f
x
by adding t he feedback capacit or
C2 st abilizes t he cir cuit and yields a phase mar gin of about 45 degr ees.
f
x
R C
=
1
2 2 2
Since f
x
is t he geomet r ic mean of f
p
and t he unit y-gain bandwidt h fr equency of t he
op amp, f
u
,
f
x
f
p
f
u
= .
These equat ions can be solved for C2:
C
C
R f
u
2
1
2 2
=

.
This value of C2 will yield a phase mar gin of about 45 degr ees. Incr easing t he
capacit or by a fact or of 2 incr eases t he phase mar gin t o about 65 degr ees (see
Refer ences 4 and 5).
In pr act ice, t he opt imum value of C2 should be opt imized exper iment ally by var ying
it slight ly t o opt imize t he out put pulse r esponse.
Select i on of t h e Op Amp
The phot odiode pr eamp should be a wideband FET-input one in or der t o minimize
t he effect s of input bias cur r ent and allow low values of phot ocur r ent s t o be det ect ed.
In addit ion, if t he equat ion for t he 3dB bandwidt h, f
x
, is r ear r anged in t er ms of f
u
,
R2, and C1, t hen
f
x
f
u
R C
=
2 2 1
,
wher e C1 = C
D
+ C
in
By inspect ion of t his equat ion, it is clear t hat in or der t o maximize f
x
, t he FET-input
op amp should have bot h a high unit y gain-bandwidt h pr oduct , f
u
, and a low input
capacit ance, C
in
. In fact , t he r at io of f
u
t o C
in
is a good figur e-of-mer it when
evaluat ing differ ent op amps for t his applicat ion. Figur e 2.63 compar es a number of
FET-input op amps suit able for phot odiode pr eamps.
63
FET-INPUT OP AMP COMPARISON TABLE
FOR WIDE BANDWIDTH PHOTODIODE PREAMPS
Unity
GBW
Product,
f
u
(MHz)
Input
Capacitanc
eC
in
(pF)
f
u
/C
in
(MHz/pF)
Input Bias
Current
I
b
(pA)
Voltage Noise
@10kHz
(nV/ Hz)
AD823 16 1.8 8.9 3 16
AD843 34 6 5.7 600 19
AD744 13 5.5 2.4 100 16
AD845 16 8 2 500 18
AD745
*
20 20 1 250 2.9
AD645 1 1 1 1.5 8
AD820 1.9 2.8 0.7 2 13
AD743 4.5 20 0.2 250 2.9
*
Stable for Noise Gains > 5, Usually the Case, Since
High Frequency Noise Gain = 1 + C
1
/C
2
, and C
1
Usually > 4C
2
.
a 2.63
By inspect ion, t he AD823 op amp has t he highest r at io of unit y gain-bandwidt h
pr oduct t o input capacit ance, in addit ion t o r elat ively low input bias cur r ent . For
t hese r easons, it was chosen for t he wideband phot odiode pr eamp design.
Using t he diode capacit ance, C
D
=4pF, and t he AD823 input capacit ance, C
in
=1.8pF,
t he value of C1 = C
D
+C
in
= 5.8pF. Solving t he above equat ions using C1=5.8pF,
R2=100k, and f
u
=16MHz, we find t hat :
f
p
= 274kHz
C2 = 0.76pF
f
x
= 2.1MHz.
In t he final design (Figur e 2.64), not e t hat t he 100k r esist or is r eplaced wit h t hr ee
33.2k film r esist or s t o minimize st r ay capacit ance. The feedback capacit or , C2, is a
var iable 1.5pF cer amic and is adjust ed in t he final cir cuit for best bandwidt h/pulse
r esponse. The over all cir cuit bandwidt h is appr oximat ely 2MHz.
The full scale out put volt age of t he pr eamp for 100A diode cur r ent is 10V, and t he
er r or (RTO) due t o t he phot odiode dar k cur r ent of 600pA is 60mV. The dar k cur r ent
64
er r or can be canceled using a second phot odiode of t he same t ype in t he non-
inver t ing input of t he op amp as shown in Figur e 2.64.
a
2MHz BANDWIDTH PHOTODIODE PREAMP
WITH DARK CURRENT COMPENSATION
2.64
0.1 F
LOW LEAKAGE
POLYSTYRENE
+
-
+15V
D1, D2: HP-5082-4204
100k
AD823
-15V
R2 = 100k
C2
0.8pF
33.2k 33.2k 33.2k
-10V
D2
D1
C1
5.8pF
C1 = C
D
+ C
IN
C
D
= 4pF, C
IN
= 1.8pF
P h ot od i od e P r ea mp Noi se An a lysi s
As in most noise analyses, only t he key cont r ibut or s need be ident ified. Because t he
noise sour ces combine in an RSS manner , any single noise sour ce t hat is at least
t hr ee or four t imes as lar ge as any of t he ot her s will dominat e.
In t he case of t he wideband phot odiode pr eamp, t he dominant sour ces of out put
noise ar e t he input volt age noise of t he op amp, V
ni
, and t he r esist or noise due t o
R2, V
nR2
. The input cur r ent noise of t he FET-input op amp is negligible. The shot
noise of t he phot odiode (caused by t he r ever se bias) is negligible because of t he
filt er ing effect of t he shunt capacit ance C1. The r esist or noise is easily calculat ed by
knowing t hat a 1k r esist or gener at es about 4nV/Hz, t her efor e, a 100k r esist or
gener at es 40nV/Hz. The bandwidt h for int egr at ion is t he signal bandwidt h,
2.1MHz, yielding a t ot al out put r ms noise of:
V
nR OUT
Vr ms
2
40 1 57 21 10
6
73
( )
. . = = .
The fact or of 1.57 conver t s t he appr oximat e single-pole bandwidt h of 2.1MHz int o
t he equivalent noise bandwidth.
The out put noise due t o t he input volt age noise is obt ained by mult iplying t he noise
gain by t he volt age noise and int egr at ing t he ent ir e funct ion over fr equency. This
would be t edious if done r igor ously, but a few r easonable appr oximat ions can be
made which gr eat ly simplify t he mat h. Obviously, t he low fr equency 1/f noise can be
65
neglect ed in t he case of t he wideband cir cuit . The pr imar y sour ce of out put noise is
due t o t he high-fr equency noise-gain peaking which occur s bet ween f
p
and f
u
. If we
simply assume t hat t he out put noise is const ant over t he ent ir e r ange of fr equencies
and use t he maximum value for AC noise gain [1+(C1/C2)], t hen
V
ni OUT
V
ni
C
C
f
x
Vr ms
( )
. +

= 1
1
2
1 57 250 .
The t ot al r ms noise r efer r ed t o t he out put is t hen t he RSS value of t he t wo
component s:
( ) ( ) V
n TOTAL
Vr ms
( )
= + = 73
2
250
2
260 .
The t ot al out put dynamic r ange can be calculat ed by dividing t he full scale out put
signal (10V) by t he t ot al out put r ms noise, 260Vr ms, and conver t ing t o dB, yielding
appr oximat ely 92dB.
a
EQUIVALENT CIRCUIT FOR OUTPUT NOISE ANALYSIS
2.65
C1
+
-
AD823
C2
C1 = 5.8pF
C2 = 0.76pF
R2 = 100k
V
n (TOTAL)
R2
C1
V
ni
V
nR2
V
ni =
16nV/ Hz
NOISE GAIN
f
p
f
x
f
u
274kHz 2.1MHz 16MHz
1+
C2
V
ni(out)

V
ni
( ) 1.57f
x
= 250 V rms
V
nR2(out)
4kTR2 1.57f
x
= 73 V rms
V
n(TOTAL)
= 250
2
+ 73
2
= 260 V rms
DYNAMIC RANGE = 20 log = 92dB
C1
C2
1+
260 V
10V
1
66
REFERENCES
1. Walt Kest er , Maintaining Transmission Line Impedances on the
PC Board, wit hin Chapt er 11 of Syst em Ap p li ca t i on s Gu i d e,
Analog Devices, 1993.
2. J oe Buxt on, Careful Design Tames High-S peed Op Amps,
Elect r on i c Desi gn , Apr il 11, 1991.
3. Walt J ung, Op Amps in Line-Driver and Receiver Circuits, Part 1,
An a log Di a logu e, Vol. 26-2, 1992.
4. William R. Blood, J r ., MECL Syst em Desi gn Ha n d book
(HB205, Rev.1), Mot or ola Semiconduct or Pr oduct s, Inc., 1988.
5. Dave Whit ney, Walt J ung, Applying a High-Performance Video
Operational Amplifier, An a log Di a logu e, 26-1, 1992.
6. Ohmt ek, Niagar a Falls, NY, (716) 283-4025.
7. Walt Kest er , Video Line Receiver Applications Using the AD830
Active Feedback Amplifier Topology, wit hin Chapt er 11 of Syst em
Ap p li ca t i on s Gu i d e, Analog Devices, 1993.
8. Walt J ung, Analog-S ignal-Processing Concepts Get More Efficient,
Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e, J une 24, 1993.
9. Pet er Checkovich, Understanding and Using High-S peed Clamping
Amplifiers, An a log Di a logu e, Vol. 29-1, 1995.
10. Walt J ung, Scot t Wur cer , Design Video Circuits Using High-S peed
Op-Amp S ystems, Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e,
November 7, 1994.
11. W. A. Kest er , PCM S ignal Codecs for Video Applications,
SMP TE J ou r n a l, No. 88, November 1979, pp. 770-778.
12. IEEE S tandard for Performance Measurements of A/ D and D/ A
Converters for PCM Television Circuits, I EEE St a n d a r d 746-1984.
13. P r a ct i ca l An a log Desi gn Tech n i qu es, Chapt er s 1, 2, and 4,
1995, Analog Devices.
14. Amp li fi er Ap p li ca t i on s Gu i d e, 1992, Analog Devices.
15. J er ald G. Gr aeme, P h ot od i od e Amp li fi er s: Op Amp
Solu t i on s,, McGr aw Hill, 1995.
1
SECTI ON 3
RF/I F SUBSYSTEMS
Wa l t Kest er , J a m es Br ya n t , Bob Cl a r k e,
Ba r r i e Gi l ber t
DYNAMI C RANGE COMP RESSI ON
In many cases, a wide dynamic r ange is an essent ial aspect of a signal, somet hing t o
be pr eser ved at all cost s. This is t r ue, for example, in t he high-qualit y r epr oduct ion
of music and in communicat ions syst ems. However , it is oft en necessar y t o compr ess
t he signal t o a smaller r ange wit hout any significant loss of infor mat ion.
Compr ession is oft en used in magnet ic r ecor ding, wher e t he upper end of t he
dynamic r ange is limit ed by t ape sat ur at ion, and t he lower end by t he gr anular it y of
t he medium. In pr ofessional noise-r educt ion syst ems, compr ession is "undone" by
pr ecisely-mat ched nonlinear expansion dur ing r epr oduct ion. Similar t echniques ar e
oft en used in conveying speech over noisy channels, wher e t he per for mance is mor e
likely t o be measur ed in t er ms of wor d-int elligibilit y t han audio fidelit y. The
r ecipr ocal pr ocesses of compr essing and expanding ar e implement ed using
"compandor s", and many schemes have been devised t o achieve t his funct ion.
Ther e is a class of linear dynamic r ange compr ession syst ems wher e t he gain of t he
amplifier s in t he signal pr ocessing chain is independent of t he inst ant aneous
amplit ude of t he signal, but is cont r olled by a closed loop syst em in such a way as t o
r ender t he out put (t hat is t he peak, or r ms value) essent ially const ant . The
har monic dist or t ion is r elat ively low. These syst ems use what ar e oft en called
variable-gain amplifiers. While cor r ect , t his lacks pr ecision, because nonlinear
amplifier s (such as log amps) also exhibit var iable gain, but in dir ect r esponse t o t he
signal magnit ude. The t er m voltage controlled amplifier (VCA) is pr efer r ed in t his
cont ext ; it clear ly descr ibes t he way in which t he gain cont r ol is implement ed, while
allowing lat it ude in r egar d t o t he act ual cir cuit means used t o achieve t he funct ion.
The gain may be cont r olled by a current wit hin t he cir cuit , but usually a volt age.
Analog mult iplier s may be used as VCAs, but t her e ar e ot her t opologies which will
be discussed lat er in t his sect ion.
Logar it hmic amps find applicat ions wher e signals having wide dynamic r anges
(per haps gr eat er t han 100dB) must be pr ocessed by element s, such as ADCs, which
may have limit ed dynamic r anges. Log amps have maximum incr ement al gain for
small signals; t he gain decr eases in inver se pr opor t ion t o t he magnit ude of t he
input . This per mit s t he amplifier t o accept signals wit h a wide input dynamic r ange
and compr ess t hem subst ant ially.
Log amps pr ovide nonlinear dynamic r ange compr ession and ar e used in
applicat ions wher e low har monic dist or t ion is not a r equir ement . All t ypes of log
amps pr oduce a low dynamic r ange out put wit hout t he need t o fir st acquir e some
measur e of t he signal amplit ude for use in cont r olling gain.
2
We will fir st examine linear compr ession t echniques using volt age-cont r olled
amplifier s wit hin aut omat ic-gain-cont r ol (AGC) loops. Nonlinear signal compr ession
using log amps is t hen discussed.
Bot h AGC loops using VCAs and log amps make excellent building blocks for highly
int egr at ed RF/IF subsyst ems for signal pr ocessing in communicat ions syst ems as
will be demonst r at ed.
RF / IF SUBSYSTEM BUILDING BLOCKS
n n Signal Dynamic Range Compression Techniques
u u Linear: Automatic Gain Control Loop (AGC) using
Voltage Controlled Amplifier (VCA) and Detector
u u Non-Linear: Demodulating / Limiting Logarithmic
Amplifiers
n n Modulation / Demodulation: In-Phase and Quadrature (I/Q)
and Polar (Amplitude and Phase)
u u Dynamic Range Compression Required
u u IF Subsystems: AGC, Log / Limiting, RSSI, Mixers
a 3.1
AUTOMATI C GAI N CONTROL (AGC) AND VOLTAGE-
CONTROLLED AMP LI FI ERS (VCAS)
In r adio syst ems, t he r eceived ener gy exhibit s a lar ge dynamic r ange due t o t he
var iabilit y of t he pr opagat ion pat h, r equir ing dynamic-r ange compr ession in t he
r eceiver . In t his case, t he want ed infor mat ion is in t he modulat ion envelope
(what ever t he modulat ion mode), not in t he absolut e magnit ude of t he car r ier . For
example, a 1MHz car r ier modulat ed at 1kHz t o a 30% modulat ion dept h would
convey t he same infor mat ion, whet her t he r eceived car r ier level is at 0dBm or
120dBm. Some t ype of aut omat ic gain cont r ol (AGC) in t he r eceiver is gener ally
ut ilized t o r est or e t he car r ier amplit ude t o some nor malized r efer ence level, in t he
pr esence of lar ge input fluct uat ions. AGC cir cuit s ar e dynamic-r ange compr essor s
which r espond t o some met r ic of t he signal oft en it s mean amplit ude acquir ed
over an int er val cor r esponding t o many per iods of t he car r ier . Consequent ly, t hey
r equir e t ime t o adjust t o var iat ions in r eceived signal level. The t ime r equir ed t o
r espond t o a sudden incr ease in signal level can be r educed by using peak det ect ion
met hods, but wit h some loss of r obust ness, since t r ansient noise peaks can now
act ivat e t he AGC det ect ion cir cuit s. Nonlinear filt er ing and t he concept of "delayed
AGC" can be useful in opt imizing an AGC syst em. Many t r adeoffs ar e found in
pr act ice; Figur e 3.2 shows a basic syst em.
3
a
3.2
A TYPICAL AUTOMATIC GAIN CONTROL (AGC) SYSTEM
CONTROL
VOLTAGE
MEASURES
SIGNAL
LEVEL
-
+
VOLTAGE CONTROLLED AMP
DIFFERENCE
AMP
V
X
sin t
INPUT: UNKNOWN
AMPLITUDE
VCA
DETECTOR
V
R
sin t
OUTPUT: FIXED
AMPLITUDE
RECTIFIER
RMS/DC CONVERTER
PEAK DETECTOR
V
REF
LPF
It is int er est ing t o not e t hat an AGC loop act ually has t wo out put s. The obvious
out put is t he amplit ude-st abilized signal. The less obvious out put is t he cont r ol
volt age t o t he VCA, which is in r ealit y, a measur e of t he aver age amplit ude of t he
input signal. If t he syst em is pr ecisely scaled, t he cont r ol volt age may be used as a
measur e of t he input signal, somet imes r efer r ed t o as a received signal strength
indicator (RSSI).
VOLTAGE CONTROLLED AMP LI FI ERS (VCAS)
An analog mult iplier can be used as a var iable-gain amplifier as shown in Figur e
3.3. The cont r ol volt age is applied t o one input , and t he signal t o t he ot her . In t his
configur at ion, t he gain is dir ect ly pr opor t ional t o t he cont r ol volt age.
4
a 3.3
USING A MULTIPLIER AS A
VOLTAGE-CONTROLLED AMPLIFIER (VCA)
+
V
X
sin t
R
2
V
IN
-
V
C
CONTROL
INPUT
R
1
V
O
V
O
=
V
IN
K
1 + V
C
R
2
R
1
( )
Most VCAs made wit h analog mult iplier s have gain which is linear in volts wit h
r espect t o t he cont r ol volt age, and t hey t end t o be noisy. Ther e is a demand,
however , for a VCA which combines a wide gain r ange wit h const ant bandwidt h and
phase, low noise wit h lar ge signal-handling capabilit ies, and low dist or t ion wit h low
power consumpt ion, while pr oviding accur at e, st able, linear-in-dB gain. The AD600,
AD602, and AD603 achieve t hese demanding and conflict ing object ives wit h a
unique and elegant solut ion - t he X-AMP (for exponential amplifier). The concept
is simple: a fixed-gain amplifier follows a passive, br oadband at t enuat or equipped
wit h special means t o alt er it s at t enuat ion under t he cont r ol of a volt age (see Figur e
3.4). The amplifier is opt imized for low input noise, and negat ive feedback is used t o
accur at ely define it s moder at ely high gain (about 30 t o 40dB) and minimize
dist or t ion. Since t his amplifier 's gain is fixed, so also ar e it s ac and t r ansient
r esponse char act er ist ics, including dist or t ion and gr oup delay; since it s gain is high,
it s input is never dr iven beyond a few millivolt s. Ther efor e, it is always oper at ing
wit hin it s small signal r esponse r ange.
5
a 3.4
+
C1HI
V
G
RF2
2.24k (AD600)
694 (AD602)
SINGLE CHANNEL OF THE DUAL 30MHz AD600/AD602 X-AMP
C1LO
A1HI
GAIN CONTROL
INTERFACE
PRECISION
PASSIVE
INPUT
ATTENUATOR
-
SCALING
REFERENCE
GAT1
+
-
A1LO
500
R - 2R LADDER NETWORK
(R
O
= 100 2%)
62.5
0dB -6.02dB -12.04dB -18.06dB -22.08dB -33.1dB -36.12dB -42.14dB
GATING
INTERFACE
A1CM
A1OP
FIXED GAIN
AMPLIFIER
41.07dB (AD600)
31.07dB (AD602)
The at t enuat or is a 7-sect ion (8-t ap) R-2R ladder net wor k. The volt age r at io bet ween
all adjacent t aps is exact ly 2, or 6.02dB. This pr ovides t he basis for t he pr ecise
linear -in-dB behavior . The over all at t enuat ion is 42.14dB. As will be shown, t he
amplifier 's input can be connect ed t o any one of t hese t aps, or even interpolated
bet ween t hem, wit h only a small deviat ion er r or of about 0.2dB. The over all gain
can be var ied all t he way fr om t he fixed (maximum) gain t o a value 42.14dB less.
For example, in t he AD600, t he fixed gain is 41.07dB (a volt age gain of 113); using
t his choice, t he full gain r ange is 1.07dB t o +41.07dB. The gain is r elat ed t o t he
cont r ol volt age by t he r elat ionship G
dB
= 32V
G
+ 20 wher e V
G
is in volt s. For t he
AD602, t he fixed gain is 31.07dB (a volt age gain of 35.8), and t he gain is given by
G
dB
= 32V
G
+ 10.
The gain at V
G
= 0 is laser t r immed t o an absolut e accur acy of 0.2dB. The gain
scaling is det er mined by an on-chip bandgap r efer ence (shar ed by bot h channels),
laser t r immed for high accur acy and low t emper at ur e coefficient . Figur e 3.5 shows
t he gain ver sus t he differ ent ial cont r ol volt age for bot h t he AD600 and t he AD602.
6
a 3.5
GAIN OF THE AD600/AD602
AS A FUNCTION OF CONTROL VOLTAGE
AD602
AD600
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
V
G
- Millivolts
G
A
I
N

-

d
B
-800 -400 0 400 800
In or der t o under st and t he oper at ion of t he X-AMP, consider t he simplified diagr am
shown in Figur e 3.6. Not ice t hat each of t he eight t aps is connect ed t o an input of
one of eight bipolar differ ent ial pair s, used as cur r ent -cont r olled t r ansconduct ance
(g
m
) st ages; t he ot her input of all t hese g
m
st ages is connect ed t o t he amplifier 's
gain-det er mining feedback net wor k, R
F1
/R
F2
. When t he emit t er bias cur r ent , I
E
, is
dir ect ed t o one of t he 8 t r ansist or pair s (by means not shown her e), it becomes t he
input st age for t he complet e amplifier .
a
3.6
+
-
CONTINUOUS INTERPOLATION BETWEEN
TAPS IN THE X-AMP IS PERFORMCE WITH CURRENT-
CONTROLLED gm STAGES
(A1HI)
(A1LO)
R
O
=100
(R = 50 )
R
F1
R
R
A
OL

R
R 2R 2R
R R R R
2R 2R 2R 2R
I
E
6
I
E
5 I
E
4 I
E
3 I
E
2
I
E
1
I
E
+
R
F2
OUTPUT
(A1OP)
I
E
7 I
E
8
7
When I
E
is connect ed t o t he pair on t he left -hand side, t he signal input is connect ed
dir ect ly t o t he amplifier , giving t he maximum gain. The dist or t ion is ver y low, even
at high fr equencies, due t o t he car eful open-loop design, aided by t he negat ive
feedback. If I
E
wer e now t o be abr upt ly swit ched t o t he second pair , t he over all gain
would dr op by exact ly 6.02dB, and t he dist or t ion would r emain low, because only
one g
m
st age r emains act ive.
In r ealit y, t he bias cur r ent is gradually t r ansfer r ed fr om t he fir st pair t o t he second.
When I
E
is equally divided bet ween t wo gm st ages, bot h ar e act ive, and t he
sit uat ion ar ises wher e we have an op amp wit h t wo input st ages fight ing for cont r ol
of t he loop, one get t ing t he full signal, and t he ot her get t ing a signal exact ly half as
lar ge.
Analysis shows t hat t he effect ive gain is r educed, not by 3dB, as one might fir st
expect , but r at her by 20log1.5, or 3.52dB. This er r or , when divided equally over t he
whole r ange, would amount t o a gain r ipple of 0.25dB; however , t he int er polat ion
cir cuit act ually gener at es a Gaussian dist r ibut ion of bias cur r ent s, and a significant
fr act ion of I
E
always flows in adjacent st ages. This smoot hes t he gain funct ion and
act ually lower s t he r ipple (see Refer ence 12). As I
E
moves fur t her t o t he r ight , t he
over all gain pr ogr essively dr ops.
The t ot al input -r efer r ed noise of t he X-AMP is 1.4nV/Hz; only slight ly mor e t han
t he t her mal noise of a 100 r esist or which is 1.29nV/Hz at 25C. The input -
r efer r ed noise is const ant r egar dless of t he at t enuat or set t ing, t her efor e t he out put
noise is always const ant and independent of gain. For t he AD600, t he amplifier gain
is 113 and t he out put noise spect r al densit y is t her efor e 1.4nV/Hz113, or 158nV/
Hz. Refer r ed t o it s maximum out put of 2V r ms, t he signal-t o-noise r at io would be
82dB in a 1MHz bandwidt h. The cor r esponding signal-t o-noise r at io of t he AD602 is
10dB gr eat er , or 92dB. Key feat ur es of t he AD600/AD602 ar e summar ized in Figur e
3.7
KEY FEATURES OF THE AD600/AD602 X-AMPS
n n Precise Decibel-Scaled Gain Control
n n Accurate Absolute Gain Calibration
n n Low Input-Referred Noise (1.4nV/ Hz)
n n Constant Bandwidth (dc to 35MHz)
n n Low Distortion: 60dBc THD at 1V Output
n n Stable Group Delay (2ns Over Gain Range)
n n Response Time: Less than 1s for 40dB Gain Change
n n Low Power (125mW per channel maximum)
n n Differential Control Inputs
8
a 3.7
The AD603 X-AMP is a single ver sion of t he AD600/AD602 which pr ovides 90MHz
bandwidt h. Ther e ar e t wo pin-pr ogr ammable gain r anges: 11dB t o +31dB wit h
90MHz bandwidt h, and +9dB t o +51dB wit h 9MHz bandwidt h. Key specificat ions
for t he AD603 ar e summar ized in Figur e 3.8.
KEY FEATURES OF THE AD603 X-AMP
n n Precise "Linear in dB" Gain Control
n n Pin Programmable Gain Ranges:
11dB to +31dB with 90MHz Bandwidth
+9dB to + 51dB with 9MHz Bandwidth
n n Bandwidth Independent of Variable Gain
n n Low Input-Referred Noise (1.3nV/ Hz)
n n 0.5dB Typical Gain Accuracy
n n Low Distortion: 60dBc, 1V rms Output @ 10MHz
n n Low Power (125mW)
n n 8-pin Plastic SOIC or Ceramic DIP
a 3.8
AN 80 d B RMS-LI NEAR-d B MEASUREMENT SYSTEM
RMS/DC conver t er s pr ovide a means t o measur e t he r ms value of an ar bit r ar y
wavefor m. They also may pr ovide a low-accur acy logar it hmic ("decibel-scaled")
out put . However , t hey have a fair ly small dynamic r ange t ypically only 50dB.
Mor e t r oublesome is t hat t he bandwidt h is r oughly pr opor t ional t o t he signal level;
for example, t he AD636 pr ovides a 3dB bandwidt h of 900kHz for an input of 100mV
r ms, but only a 100kHz bandwidt h for an input of 10mV r ms. It s "r aw" logar it hmic
out put is unbuffer ed, uncalibr at ed, and not st able over t emper at ur e, r equir ing
consider able suppor t cir cuit r y, including at least t wo adjust ment s and a special
high-TC r esist or .
All of t hese pr oblems can be eliminat ed using an RMS/DC conver t er (i.e.,AD636)
mer ely as the detector element in an AGC loop, in which t he differ ence bet ween t he
r ms out put of t he AD636 and a fixed DC r efer ence is nulled in a loop int egr at or . The
9
dynamic r ange and t he accur acy wit h which t he signal can be det er mined ar e now
ent ir ely dependent on t he amplifier used in t he AGC syst em. Since t he input t o t he
RMS/DC conver t er is for ced t o a const ant amplit ude, close t o it s maximum input
capabilit y, t he bandwidt h is no longer signal-dependent . If t he amplifier has a
pr ecise exponent ial ("linear -dB") gain-cont r ol law, it s cont r ol volt age is for ced by t he
AGC loop t o have t he gener al for m
V
LOG
V
S
V
IN RMS
V
Z
= log
( )
10
wher e V
S
is t he logar it hmic slope and V
Z
is t he logar it hmic int er cept , t hat is, t he
value of V
IN
for which V
LOG
is zer o.
Figur e 3.9 shows a pr act ical wide-dynamic-r ange r ms measur ement syst em using
t he AD600. It can handle input s fr om 100V t o 1V r ms (4 decades) wit h a const ant
measur ement bandwidt h of 20Hz t o 2MHz, limit ed pr imar ily by t he AD636 RMS/DC
conver t er . It s logar it hmic out put is a buffer ed volt age, accur at ely-calibr at ed t o
100mV/dB, or 2V per decade, which simplifies t he int er pr et at ion of t he r eading
when using a DVM, and is ar r anged t o be 4V for an input of 100V r ms input , zer o
for 10mV, and +4V for a 1V r ms input . In t er ms of t he above equat ion, V
S
is 2V and
V
Z
is 10mV.
+6V DEC
a
3.9
A COMPLETE 80dB RMS-LINEAR-dB MEASUREMENT SYSTEM
V
RMS

U1 AD600
U2
AD636
VINP
C1LO
A1CM
13
14
INPUT
1V RMS
MAX
(SINE WAVE)
-6V DEC
-6V DEC
C2
2 F
NC
NC
NC
NC
-
U3A
U3B
+
-
+
-
-
+
+
12
11
10
9 8
7
6
5
4
3
2
1 16
15
+6V DEC
-6V DEC
FB
-6V
POWERSUPPLY
DECOUPLINGNETWORK
0.1 F
0.1 F
FB
+6V
+6V DEC
R1
115
R2200
R3
133k
A1HI
A1LO
GAT1
GAT2
A2LO
A2HI
C2LO
1/2
AD712
R5
16.2k
A2
A1
REF
V
G
15.625mV/dB
R4
3.01k
1/2
AD712
C
A
L
0
d
B
V
OUT
+100mV/dB
0V=0dB(AT10mVRMS)
NC=NOCONNECT
C3
1 F
+316.2mV
C1
0.1 F
C1HI
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI
NC
NC
8 7
6
5
4
3
2
1
13
14
12
11
10
9
COMM
VPOS
+
C4
4.7 F
R6
3.16k
R7
56.2k
LDLO
VRMS BFIN
BFOP
VLOG
CAVG
VNEG
AF/RF
OUTPUT
Not e t hat t he peak "log-out put " of 4V r equir es t he use of 6V supplies for t he dual
op-amp U3 (AD712), alt hough lower supplies would suffice for t he AD600 and
AD636. If only 5V supplies ar e available, it will eit her be necessar y t o use a
r educed value for V
S
(say, 1V, in which case t he peak out put would be only 2V), or
t o r est r ict t he dynamic r ange of t he signal t o about 60dB.
10
The t wo amplifier s of t he AD600 ar e used in cascade. The modest bandwidt h of t he
unit y-gain buffer U3A act s as a low pass filt er , t hus eliminat ing t he r isk of
inst abilit y at t he highest gains. The buffer also allows t he use of a high-impedance
coupling net wor k (C1/R3) which int r oduces a high-pass cor ner at about 12Hz. An
input at t enuat or of 10dB ( 0.316) is now pr ovided by R1 + R2 oper at ing in
conjunct ion wit h t he AD600's input r esist ance of 100. The adjust ment pr ovides
exact calibr at ion of V
Z
in cr it ical applicat ions, but R1 and R2 may be r eplaced by a
fixed r esist or of 215 if ver y close calibr at ion is not needed, since t he input
r esist ance of t he AD600 (and all t he ot her key par amet er s of it and t he AD636) ar e
alr eady laser -t r immed for accur at e oper at ion. This at t enuat or allows input s as lar ge
as 4V t o be accept ed, t hat is, signals wit h an r ms value of 1V combined wit h a
cr est -fact or of up t o 4.
The out put of A2 is AC-coupled via anot her 12Hz high-pass filt er for med by C2 and
t he 6.7k input r esist ance of t he AD636. The aver aging t ime-const ant for t he
RMS/DC conver t er is det er mined by C4. The unbuffer ed out put of t he AD636 (at pin
8) is compar ed wit h a fixed volt age of +316mV set by t he posit ive supply volt age of
+6V and r esist or s R6 and R7. (V
Z
is pr opor t ional t o t his volt age, and syst ems
r equir ing gr eat er calibr at ion accur acy should r eplace t he supply-dependent
r efer ence wit h a mor e st able sour ce. However , V
S
is independent of t he supply
volt ages, being det er mined by t he band-gap r efer ence in t he X-AMP.) Any
differ ence in t hese volt ages is int egr at ed by t he op-amp U3B, wit h a t ime-const ant
of 3ms for med by t he par allel sum of R6/R7 and C3.
If t he gain of t he AD600 is t oo high, V
OUT
will be gr eat er t han t he "set -point " of
316mV, causing t he out put of U3B t hat is, V
LOG
t o r amp up (not e t hat t he
int egr at or is non-inver t ing). A fr act ion of V
LOG
is connect ed t o t he inverting gain-
cont r ol input s of t he AD600, causing t he gain t o be r educed, as r equir ed, unt il V
OUT
is equal t o 316mV (DC), at which t ime t he AC volt age at t he out put of A2 is for ced t o
exact ly 316mV (r ms). This fr act ion is set by R4 and R5 such t hat a 15.625mV
change in t he cont r ol volt ages of A1 and A2 which would change t he gain of t he
t wo cascaded amplifier s by 1 dB r equir es a change of 100mV at V
LOG
. Since A2 is
for ced t o oper at e well below it s limit ing level, wavefor ms of high cr est -fact or can be
t oler at ed t hr oughout t he amplifier .
To ver ify t he oper at ion, assume an input of 10mV r ms is applied t o t he input ,
r esult ing in a volt age of 3.16mV r ms at t he input t o A1 (due t o t he 10dB
at t enuat or ). If t he syst em per for ms as claimed, V
LOG
(and hence V
G
) should be
zer o. This being t he case, t he gain of bot h A1 and A2 will be 20dB and t he out put of
t he AD600 will be 100 t imes (40dB) gr eat er t han it s input , 316mV r ms. This is t he
input r equir ed at t he AD636 t o balance t he loop, confir ming t he basic oper at ion.
Not e t hat unlike most AGC cir cuit s, (which oft en have a high gain/t emper at ur e
coefficient due t o t he int er nal "kT/q" scaling), t he volt ages and t hus t he out put of
t his measur ement syst em ar e ver y st able over t emper at ur e. This behavior ar ises
dir ect ly fr om t he exact exponent ial calibr at ion of t he ladder at t enuat or .
Typical r esult s ar e shown for a sinewave input at 100kHz. Figur e 3.10 shows t hat
t he out put is held ver y close t o t he set -point of 316mV r ms over an input r ange in
excess of 80dB.
11
a 3.10
SIGNAL OUTPUT V
OUT
VERSUS INPUT LEVEL
INPUT SIGNAL - V RMS
10 V 100 V 1mV 10mV 100mV 1V
10V
450
425
400
375
350
325
300
275
250
225
200
175
150
V
O
U
T

-

m
V

R
M
S
Figur e 3.11 shows t he "decibel" out put volt age, V
LOG
, and Figur e 3.12 shows t hat
t he deviation fr om t he ideal out put logar it hmic out put is wit hin 1 dB for t he 80dB
r ange fr om 80V t o 800mV.
a 3.11
THE LOGARITHMIC OUTPUT V
LOG
VERSUS INPUT SIGNAL LEVEL
INPUT SIGNAL - V RMS
10 V 100 V 1mV 10mV 100mV 1V
10V
5
4
3
2
1
0
-1
-2
-3
-4
-5
V
O
U
T

-

V

12
a 3.12
DEVIATION FROM THE IDEAL
LOGARITHMIC OUTPUT
INPUT SIGNAL - V RMS
10 V 100 V 1mV 10mV 100mV 1V
10V
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
O
U
T
P
U
T

E
R
R
O
R

-

d
B
By suit able choice of t he input at t enuat or , R1+R2, t his could be cent er ed t o cover
any r ange fr om 25V t o 250mV t o, say, 1mV t o 10V, wit h appr opr iat e cor r ect ion t o
t he value of V
Z
. (Not e t hat V
S
is not affect ed by t he changes in t he r ange). The gain
r ipple of 0.2dB seen in t his cur ve is t he r esult of t he finit e int er polat ion er r or of t he
X-AMP. It occur s wit h a per iodicit y of 12dB t wice t he separ at ion bet ween t he t ap
point s in each amplifier sect ion.
This r ipple can be canceled whenever t he X-AMP st ages ar e cascaded by int r oducing
a 3dB offset bet ween t he t wo pair s of cont r ol volt ages. A simple means t o achieve
t his is shown in Figur e 3.13: t he volt ages at C1HI and C2HI ar e "split " by
46.875mV, or 1.5dB. Alt er nat ively, eit her one of t hese pins can be individually
offset by 3dB, and a 1.5dB gain adjust ment made at t he input at t enuat or (R1+R2).
The er r or cur ve shown in Figur e 3.14 demonst r at es t hat over t he cent r al por t ion of
t he r ange, t he out put volt age can be maint ained ver y close t o t he ideal value. The
penalt y for t his modificat ion is higher er r or s at bot h ends of t he r ange.
13
a
3.13
METHOD FOR CANCELING THE
GAIN-CONTROL RIPPLE
U1
AD600
U2
AD636
-6V
DEC
10k
78.7 78.7 10k
+6V
DEC
3dB OFFSET
MODIFICATION
NC = NO CONNECT
-46.875mV +46.875mV
C1HI
A1CM
A1OP
VPOS
VNEG
A2OP
A2CM
C2HI
9
10
11
12
13
14
15
16
+6V DEC
-6V DEC
-6V
DEC
C2
2 F
NC
1
2
3
4
5
6
7
NC
NC
BFIN
BFOP
VLOG
CAVG
VNEG
VINP
a 3.14
LOGARITHMIC ERROR USING THE
PREVIOUS CIRCUIT MODIFICATION
INPUT SIGNAL - V RMS
10 V 100 V 1mV 10mV 100mV 1V
10V
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
O
U
T
P
U
T

E
R
R
O
R

-

d
B
Figur e 3.15 shows t he ease wit h which t he AD603 (90MHz X-AMP) can be used as a
high speed AGC amplifier . The cir cuit uses few par t s, has a linear -in-dB gain,
oper at es fr om a single supply, uses t wo cascaded amplifier s in sequent ial gain mode
for maximum S/N r at io (see t he dat a sheet for t he AD600/AD602, or AD603 for a
complet e descr ipt ion of t he met hods for cascading X-AMPS), and ext er nal r esist or
pr ogr ams each amplifier 's gain. It also uses a simple t emper at ur e-compensat ed
det ect or .
14
a
3.15
A 40MHz, 80dB, LOW-NOISE
AGC AMPLIFIER USING THE AD603
J1
8
6
5
7
2
1
3
4
8
6
5
7
2
1
3
4
C1
0.1 F
C7
0.1 F
C4
0.1 F
C3
100 F
R2
2.49k

C5
100 F
R1
2.49k

R
T
100
+10V
+
+10V
C2
0.1 F
C8
0.1 F
R14
2.49k

A2
AD603
A1
AD603
+10V
C6
0.1 F
R4
2.49k

C
AV
0.1 F
V
AGC

R9
1.54k

Q2
2N3906

Q1
2N3904
R8
806

R12
4.99k

C10
0.1 F
C9
0.1 F
J2
C11
0.1 F
R10
1.24k

R11
3.83k

THIS CAPACITOR SETS
AGC TIME CONSTANT
AGC LINE
R13
2.49k

R3
2.49k

R5
5.49k

+10V
5.5V R6
1.05k

6.5V
R7
3.48k
+10V
1V OFFSET FOR
SEQUENTIAL GAIN
NOTES:
1 R
T
PROVIDES A 50 INPUT IMPEDANCE
2 C3 AND C5 ARE TANTALUM
The cir cuit oper at es fr om a single +10V supply. Resist or s R1, R2 and R3, R4 bias t he
common pins of A1 and A2 at 5V. This pin is a low impedance point and must have a
low impedance pat h t o gr ound, pr ovided by t he 100F t ant alum capacit or and t he
0.1F cer amic capacit or s.
The cascaded amplifier s oper at e in sequent ial gain. The offset volt age bet ween t he
pins 2 (GNEG) of A1 and A2 is 1.05V (42.14dB x 25mV/dB), pr ovided by a volt age
divider consist ing of r esist or s R5, R6, and R7. Using st andar d values, t he offset is
not exact but is not cr it ical for t his applicat ion.
The gain of bot h A1 and A2 is pr ogr ammed by r esist or s R13 and R14, r espect ively,
t o be about 42dB; t hus t he maximum gain of t he cir cuit is t wice t hat , or 84dB. The
gain-cont r ol r ange can be shift ed up by as much as 20dB by appr opr iat e choices of
R13 and R14.
The cir cuit oper at es as follows. A1 and A2 ar e cascaded. Capacit or C1 and t he 100
of r esist ance at t he input of A1 for m a t ime-const ant of 10s. C2 blocks t he small DC
offset volt age at t he out put of A1 (which might ot her wise sat ur at e A2 at it s
maximum gain) and int r oduces a high-pass cor ner at about 16kHz, eliminat ing low
fr equency noise.
A half-wave det ect or is used based on Q1 and R8. The cur r ent int o capacit or C
AV
is
t he differ ence bet ween t he collect or cur r ent of Q2 (biased t o be 300A at 27C,
300K) and t he collect or cur r ent of Q1, which incr eases wit h t he amplit ude of t he
out put signal. The aut omat ic gain cont r ol volt age, V
AGC
, is t he t ime-int egr al of t his
er r or cur r ent . In or der for V
AGC
(and t hus t he gain) t o r emain insensit ive t o shor t -
t er m amplit ude fluct uat ions in t he out put signal, t he r ect ified cur r ent in Q1 must ,
15
on aver age, exact ly balance t he cur r ent in Q2. If t he out put of A2 is t oo small t o do
t his, V
AGC
will incr ease, causing t he gain t o incr ease, unt il Q1 conduct s sufficient ly.
Consider t he case wher e R8 is zer o and t he out put volt age V
OUT
is a squar e wave
at , say 455kHz, t hat is, well above t he cor ner fr equency of t he cont r ol loop.
Dur ing t he t ime V
OUT
is negat ive wit h r espect t o t he base volt age of Q1, Q1
conduct s; when V
OUT
is posit ive, it is cut off. Since t he aver age collect or cur r ent of
Q1 is for ced t o be 300A, and t he squar e wave has a dut y cycle of 1:1, Q1's collect or
cur r ent when conduct ing must be 600A. Wit h R8 omit t ed, t he peak amplit ude of
V
OUT
is for ced t o be just t he V
BE
of Q1 at 600A, t ypically about 700mV, or 2V
BE
peak-t o-peak. This volt age, hence t he amplit ude at which t he out put st abilizes, has
a st r ong negat ive t emper at ur e coefficient (TC), t ypically 1.7mV/C. Alt hough t his
may not be t r oublesome in some applicat ions, t he cor r ect value of R8 will r ender t he
out put st able wit h t emper at ur e.
To under st and t his, fir st not e t hat t he cur r ent in Q2 is made t o be pr opor t ional t o
absolut e t emper at ur e (PTAT). For t he moment , cont inue t o assume t hat t he signal
is a squar e wave.
When Q1 is conduct ing, V
OUT
is now t he sum of V
BE
and a volt age which is PTAT
and which can be chosen t o have an equal but opposit e TC t o t hat of V
BE
. This is
act ually not hing mor e t han an applicat ion of t he "bandgap volt age r efer ence"
pr inciple. When R8 is chosen such t hat t he sum of t he volt age acr oss it and t he V
BE
of Q1 is close t o t he bandgap volt age of about 1.2V, V
OUT
will be st able over a wide
r ange of t emper at ur es, pr ovided, of cour se, t hat Q1 and Q2 shar e t he same t her mal
envir onment .
Since t he aver age emit t er cur r ent is 600A dur ing each half-cycle of t he squar e
wave, a r esist or of 833 would add a PTAT volt age of 500mV at 300K, incr easing by
1.66mV/C. In pr act ice, t he opt imum value will depend on t he t ype of t r ansist or
used, and, t o a lesser ext ent , on t he wavefor m for which t he t emper at ur e st abilit y is
t o be opt imized; for t he inexpensive 2N3904/2N3906 pair and sine wave signals, t he
r ecommended value is 806.
This r esist or also ser ves t o lower t he peak cur r ent in Q1 when mor e t ypical signals
(usually sinusoidal) ar e involved, and t he 1.8kHz lowpass filt er it for ms wit h C
AV
helps t o minimize dist or t ion due t o r ipple in V
AGC
. Not e t hat t he out put amplit ude
under sine wave condit ions will be higher t han for a squar e wave, since t he aver age
value of t he cur r ent for an ideal r ect ifier would be 0.637 t imes as lar ge, causing t he
out put amplit ude t o be 1.2V/0.637=1.88V, or 1.33V r ms. In pr act ice, t he somewhat
nonideal r ect ifier r esult s in t he sine wave out put being r egulat ed t o about 1.4Vr ms,
or 3.6V p-p.
The bandwidt h of t he cir cuit exceeds 40MHz. At 10.7MHz, t he AGC t hr eshold is
100V (67dBm) and it s maximum gain is 83dB, 20log(1.4V/100V). The cir cuit
holds it s out put at 1.4V r ms for input s as low as 67dBm t o +15dBm (82dB), wher e
t he input signal exceeds t he AD603's maximum input r at ing. For a +10dBm input at
10.7MHz, t he second har monic is 34dB down fr om t he fundament al, and t he t hir d
har monic is 35dB down.
16
LOGARI THMI C AMP LI FI ERS
The t er m "Logar it hmic Amplifier " (gener ally abbr eviat ed t o "log amp") is somet hing
of a misnomer , and "Logar it hmic Conver t er " would be a bet t er descr ipt ion. The
conver sion of a signal t o it s equivalent logar it hmic value involves a nonlinear
oper at ion, t he consequences of which can be confusing if not fully under st ood. It is
impor t ant t o r ealize t hat many of t he familiar concept s of linear cir cuit s ar e
ir r elevant t o log amps. For example, t he incr ement al gain of an ideal log amp
appr oaches infinit y as t he input appr oaches zer o, and a change of offset at t he
out put of a log amp is equivalent t o a change of amplit ude at it s input - not a change
of input offset .
For t he pur poses of simplicit y in our init ial discussions, we shall assume t hat bot h
t he input and t he out put of a log amp ar e volt ages, alt hough t her e is no par t icular
r eason why logar it hmic cur r ent , t r ansimpedance, or t r ansconduct ance amplifier s
should not also be designed.
If we consider t he equat ion y = log(x) we find t hat ever y t ime x is mult iplied by a
const ant A, y incr eases by anot her const ant A1. Thus if log(K) = K1, t hen log(AK) =
K1 + A1, log(A
2
K) = K1 + 2A1, and log(K/A) = K1 A1. This gives a gr aph as shown
in Figur e 3.16, wher e y is zer o when x is unit y, y appr oaches minus infinit y as x
appr oaches zer o, and which has no values for x for which y is negat ive.
a 3.16
GRAPH OF Y = LOG(X)
X = 1
X
Y
On t he whole, log amps do not behave in t his way. Apar t fr om t he difficult ies of
ar r anging infinit e negat ive out put volt ages, such a device would not , in fact , be ver y
useful. A log amp must sat isfy a t r ansfer funct ion of t he for m
V
out
= V
y
log(V
in
/V
x
)
over some r ange of input values which may var y fr om 100:1 (40dB) t o over
1,000,000:1 (120dB).
17
Wit h input s ver y close t o zer o, log amps cease t o behave logar it hmically, and most
t hen have a linear V
in
/V
out
law. This behavior is oft en lost in device noise. Noise
oft en limit s t he dynamic r ange of a log amp. The const ant , V
y
,has t he dimensions of
volt age, because t he out put is a volt age. The input , V
in
, is divided by a volt age, V
x
,
because t he ar gument of a logar it hm must be a simple dimensionless r at io.
A gr aph of t he t r ansfer char act er ist ic of a log amp is shown in Figur e 3.17. The scale
of t he hor izont al axis (t he input ) is logar it hmic, and t he ideal t r ansfer char act er ist ic
is a st r aight line. When V
in
= V
x
, t he logar it hm is zer o (log 1 = 0). V
x
is t her efor e
known as t he intercept voltage of t he log amp because t he gr aph cr osses t he
hor izont al axis at t his value of V
in
.
a 3.17
LOG AMP TRANSFER FUNCTION
V
Y
LOG(V
IN
/V
X
)
INPUT ON
LOG SCALE
IDEAL
ACTUAL
SLOPE = V
Y
ACTUAL
IDEAL
V
IN
= V
X
V
IN
= 10V
X
V
IN
= 100V
X
2V
Y
V
Y
+
0
-
The slope of t he line is pr opor t ional t o V
y
. When set t ing scales, logar it hms t o t he
base 10 ar e most oft en used because t his simplifies t he r elat ionship t o decibel
values: when V
in
= 10V
x
,t he logar it hm has t he value of 1, so t he out put volt age is
V
y
. When V
in
= 100V
x
, t he out put is 2V
y
,and so for t h. V
y
can t her efor e be viewed
eit her as t he "slope volt age" or as t he "volt s per decade fact or ."
The logar it hm funct ion is indet er minat e for negat ive values of x. Log amps can
r espond t o negat ive input s in t hr ee differ ent ways: (1) They can give a fullscale
negat ive out put as shown in Figur e 3.18. (2) They can give an out put which is
pr opor t ional t o t he log of t he absolut e value of t he input and disr egar ds it s sign as
shown in Figur e 3.19. This t ype of log amp can be consider ed t o be a full-wave
det ect or wit h a logar it hmic char act er ist ic, and is oft en r efer r ed t o as a detecting log
amp. (3) They can give an out put which is pr opor t ional t o t he log of t he absolut e
value of t he input and has t he same sign as t he input as shown in Figur e 3.20. This
t ype of log amp can be consider ed t o be a video amp wit h a logar it hmic
char act er ist ic, and may be known as a logarithmic video (log video) amplifier or ,
somet imes, a true log amp (alt hough t his t ype of log amp is r ar ely used in video-
display-r elat ed applicat ions).
18
a 3.18
BASIC LOG AMP
(SATURATES WITH NEGATIVE INPUT)
-
OUTPUT
INPUT
+
-
+
a 3.19
DETECTING LOG AMP
(OUTPUT POLARITY INDEPENDENT
OF INPUT POLARITY)
-
OUTPUT
INPUT
+
-
+
19
a 3.20
LOG VIDEO OR "TRUE LOG AMP"
(SYMMETRICAL RESPONSE
TO POSITIVE OR NEGATIVE SIGNALS)
-
OUTPUT
INPUT
+
-
+
Ther e ar e t hr ee basic ar chit ect ur es which may be used t o pr oduce log amps: t he
basic diode log amp, t he successive detection log amp, and t he "true log amp" which
is based on cascaded semi-limit ing amplifier s.
The volt age acr oss a silicon diode is pr opor t ional t o t he logar it hm of t he cur r ent
t hr ough it . If a diode is placed in t he feedback pat h of an inver t ing op-amp, t he
out put volt age will be pr opor t ional t o t he log of t he input cur r ent as shown in Figur e
3.21. In pr act ice, t he dynamic r ange of t his configur at ion is limit ed t o 40-60dB
because of non-ideal diode char act er ist ic, but if t he diode is r eplaced wit h a diode-
connect ed t r ansist or as shown in Figur e 3.22, t he dynamic r ange can be ext ended t o
120dB or mor e. This t ype of log amp has t hr ee disadvant ages: (1) bot h t he slope and
int er cept ar e t emper at ur e dependent ; (2) it will only handle unipolar signals; and (3)
it s bandwidt h is bot h limit ed and dependent on signal amplit ude.
Wher e sever al such log amps ar e used on a single chip t o pr oduce an analog
comput er which per for ms bot h log and ant ilog oper at ions, t he t emper at ur e var iat ion
in t he log oper at ions is unimpor t ant , since it is compensat ed by a similar var iat ion
in t he ant ilogging. This makes possible t he AD538, a monolit hic analog comput er
which can mult iply, divide, and r aise t o power s. Wher e act ual logging is r equir ed,
however , t he AD538 and similar cir cuit s r equir e t emper at ur e compensat ion
(Refer ence 7). The major disadvant age of t his t ype of log amp for high fr equency
applicat ions, t hough, is it s limit ed fr equency r esponse - which cannot be over come.
However car efully t he amplifier is designed, t her e will always be a r esidual feedback
capacit ance C
c
(oft en known as Miller capacit ance), fr om out put t o input which
limit s t he high fr equency r esponse.
What makes t his Miller capacit ance par t icular ly t r oublesome is t hat t he impedance
of t he emit t er -base junct ion is inver sely pr opor t ional t o t he cur r ent flowing in it - so
t hat if t he log amp has a dynamic r ange of 1,000,000:1, t hen it s bandwidt h will also
var y by 1,000,000:1. In pr act ice, t he var iat ion is less because ot her consider at ions
20
limit t he lar ge signal bandwidt h, but it is ver y difficult t o make a log amp of t his
t ype wit h a small-signal bandwidt h gr eat er t han a few hundr ed kHz.
a
3.21
THE DIODE / OP-AMP LOG AMP
+ V -
I
V = In
if I >> I
O
kT
q
I
I
O
V
+
-
-V
IN

R
IN

I
IN

I = I
IN

E
O

E
O
= In
kT
q
I
IN
I
O
if I
IN
>> I
O
0.06log
V
IN
R
IN
I
O
a
3.22
TRANSISTOR / OP-AMP LOG AMP
I
E

E
O

kT
q
I
IN
I
IN
I
ES
+
-
E
O
= In
I
C

For high fr equency applicat ions, t her efor e, detecting and true log ar chit ect ur es ar e
used. Alt hough t hese differ in det ail, t he gener al pr inciple behind t heir design is
common t o bot h: inst ead of one amplifier having a logar it hmic char act er ist ic, t hese
designs use a number of similar cascaded linear st ages having well-defined lar ge
signal behavior .
Consider N cascaded limit ing amplifier s, t he out put of each dr iving a summing
cir cuit as well as t he next st age (Figur e 3.23). If each amplifier has a gain of A dB,
21
t he small signal gain of t he st r ip is NA dB. If t he input signal is small enough for
t he last st age not t o limit , t he out put of t he summing amplifier will be dominat ed by
t he out put of t he last st age.
a 3.23
BASIC MULTI-STAGE LOG AMP ARCHITECTURE
OUTPUT
INPUT

As t he input signal incr eases, t he last st age will limit . It will now make a fixed
cont r ibut ion t o t he out put of t he summing amplifier , but t he incr ement al gain t o t he
summing amplifier will dr op t o (N-1)A dB. As t he input cont inues t o incr ease, t his
st age in t ur n will limit and make a fixed cont r ibut ion t o t he out put , and t he
incr ement al gain will dr op t o (N-2)A dB, and so for t h - unt il t he fir st st age limit s,
and t he out put ceases t o change wit h incr easing signal input .
The r esponse cur ve is t hus a set of st r aight lines as shown in Figur e 3.24. The t ot al
of t hese lines, t hough, is a ver y good appr oximat ion t o a logar it hmic cur ve, and in
pr act ical cases, is an even bet t er one, because few limit ing amplifier s, especially
high fr equency ones, limit quit e as abr upt ly as t his model assumes.
22
a 3.24
BASIC MULTI-STAGE LOG AMP RESPONSE
(UNIPOLAR CASE)
OUTPUT
INPUT
G = 0
G = (N-4)A dB
G = (N-3)A dB
G = (N-2)A dB
G = (N-1)A dB
G = NA dB
}
}
}
}
The choice of gain, A, will also affect t he log linear it y. If t he gain is t oo high, t he log
appr oximat ion will be poor . If it is t oo low, t oo many st ages will be r equir ed t o
achieve t he desir ed dynamic r ange. Gener ally, gains of 10 t o 12dB (3x t o 4x) ar e
chosen.
This is, of cour se, an ideal and ver y gener al model - it demonst r at es t he pr inciple,
but it s pr act ical implement at ion at ver y high fr equencies is difficult . Assume t hat
t her e is a delay in each limit ing amplifier of t nanoseconds (t his delay may also
change when t he amplifier limit s but let 's consider fir st or der effect s!). The signal
which passes t hr ough all N st ages will under go delay of Nt nanoseconds, while t he
signal which only passes one st age will be delayed only t nanoseconds. This means
t hat a small signal is delayed by Nt nanoseconds, while a lar ge one is "smear ed",
and ar r ives spr ead over Nt nanoseconds. A nanosecond equals a foot at t he speed of
light , so such an effect r epr esent s a spr ead in posit ion of Nt feet in t he r esolut ion of
a r adar syst em-which may be unaccept able in some syst ems (for most log amp
applicat ions t his is not a pr oblem).
A solut ion is t o inser t delays in t he signal pat hs t o t he summing amplifier , but t his
can become complex. Anot her solut ion is t o alt er t he ar chit ect ur e slight ly so t hat
inst ead of limit ing gain st ages, we have st ages wit h small signal gain of A and lar ge
signal (incr ement al) gain of unit y (0dB). We can model such st ages as t wo par allel
amplifier s, a limit ing one wit h gain, and a unit y gain buffer , which t oget her feed a
summing amplifier as shown in Figur e 3.25.
23
a 3.25
STRUCTURE AND PERFORMANCE OF
"TRUE" LOG AMP ELEMENT AND OF A
LOG AMP FORMED BY SEVERAL SUCH ELEMENTS
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT

UNITY GAIN
AMPLIFIER
GAIN = 1
LIMITING
AMPLIFIER
GAIN = 3
UNITY GAIN
(LARGE SIGNAL)
GAIN = 4
(SMALL SIGNAL)
Figur e 3.25 shows t hat such st ages, cascaded, for m a log amp wit hout t he necessit y
of summing fr om individual st ages. Bot h t he mult i-st age ar chit ect ur es descr ibed
above ar e video log amplifier s, or true log amplifier s, but t he most common t ype of
high fr equency log amplifier is t he successive detection log amp ar chit ect ur e shown
in Figur e 3.26.
INPUT
a
3.26
SUCCESSIVE DETECTION LOGARITHMIC AMPLIFIER
WITH LOG AND LIMITER OUTPUTS
DETECTORS
LIMITER
OUTPUT
LIMITING AMPLIFIERS
DETECTORS MAY BE FULL OR HALF WAVE
SHOULD BE CURRENT OUTPUT DEVICES (NOT
SIMPLE DIODES) SO THAT OUTPUTS MAY BE
SUMMED WITHOUT ADDITIONAL SUMMING
COMPONENTS BEING NECESSARY
The successive detection log amp consist s of cascaded limit ing st ages as descr ibed
above, but inst ead of summing t heir out put s dir ect ly, t hese out put s ar e applied t o
det ect or s, and t he det ect or out put s ar e summed as shown in Figur e 3.26. If t he
24
det ect or s have cur r ent out put s, t he summing pr ocess may involve no mor e t han
connect ing all t he det ect or out put s t oget her .
Log amps using t his ar chit ect ur e have t wo out put s: t he log out put and a limit ing
out put . In many applicat ions, t he limit ing out put is not used, but in some (FM
r eceiver s wit h "S"-met er s, for example), bot h ar e necessar y. The limit ed out put is
especially useful in ext r act ing t he phase infor mat ion fr om t he input signal in polar
demodulat ion t echniques.
The log out put of a successive det ect ion log amplifier gener ally cont ains amplit ude
infor mat ion, and t he phase and fr equency infor mat ion is lost . This is not necessar ily
t he case, however , if a half-wave det ect or is used, and at t ent ion is paid t o equalizing
t he delays fr om t he successive det ect or s - but t he design of such log amps is
demanding.
The specificat ions of log amps will include noise, dynamic range, frequency response
(some of t he amplifier s used as successive det ect ion log amp st ages have low
fr equency as well as high fr equency cut off), t he slope of the transfer characteristic
(which is expr essed as V/dB or mA/dB depending on whet her we ar e consider ing a
volt age- or cur r ent -out put device), t he intercept point (t he input level at which t he
out put volt age or cur r ent is zer o), and t he log linearity. (See Figur es 3.27 and 3.28)
KEY PARAMETERS OF LOG AMPS
n n NOISE: The Noise Referred to the Input (RTI) of the Log Amp.
It May Be Expressed as a Noise Figure or as a Noise Spectral
Density (Voltage, Current, or Both) or as a Noise Voltage, a Noise
Current, or Both
n n DYNAMIC RANGE: Range of Signal Over Which the Amplifier
Behaves in a Logarithmic Manner (Expressed in dB)
n n FREQUENCY RESPONSE: Range of Frequencies Over Which
the Log Amp Functions Correctly
n n SLOPE: Gradient of Transfer Characteristic in V/dB or mA/dB
n n INTERCEPT POINT: Value of Input Signal at Which Output is Zero
n n LOG LINEARITY: Deviation of Transfer Characteristic (Plotted on
log/lin Axes) from a Straight Line (Expressed in dB)
a 3.27
25
a 3.28
LOG LINEARITY
E
O
(LINEAR)
E
i (dBm)
LOG ERROR
In t he past , it has been necessar y t o const r uct high per for mance, high fr equency
successive det ect ion log amps (called log st r ips) using a number of individual
monolit hic limit ing amplifier s such as t he Plessey SL-1521-ser ies (see Refer ence 16).
Recent advances in IC pr ocesses, however , have allowed t he complet e log st r ip
funct ion t o be int egr at ed int o a single chip, t her eby eliminat ing t he need for cost ly
hybr id log st r ips.
The AD641 log amp cont ains five limit ing st ages (10dB per st age) and five full-wave
det ect or s in a single IC package, and it s logar it hmic per for mance ext ends fr om dc t o
250MHz. Fur t her mor e, it s amplifier and full-wave det ect or st ages ar e balanced so
t hat , wit h pr oper layout , inst abilit y fr om feedback via supply r ails is unlikely. A
block diagr am of t he AD641 is shown in Figur e 3.29. Unlike many pr evious
int egr at ed cir cuit log amps, t he AD641 is laser t r immed t o high absolut e accur acy of
bot h slope and int er cept , and is fully t emper at ur e compensat ed. Key feat ur es of t he
AD641 ar e summar ized in Figur e 3.30. The t r ansfer funct ion for t he AD641 as well
as t he log linear it y is shown in Figur e 3.31.
26
a
3.29
BLOCK DIAGRAM OF THE AD641 MONOLITHIC LOG AMP
ATN LO
ATN COM
SIG +IN
SIG -IN
ATN COM
COM
27
30 270
ATN IN
1k 1k
RG1 RG0 RG2
-VS BL1
+VS
LOGOUT LOG COM
SIG +OUT
SIG -OUT
BL2
ITC
20
GAIN BIAS REGULATOR
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
ATN OUT
1
2
3
6 4 5
19
18
7
13
9
8
11
10
12
SLOPE BIAS REGULATOR
INTERCEPT POSITIONING BIAS 14 15 16 17
AD641 KEY FEATURES
n n 44dB Dynamic Range
n n Bandwidth dc to 250MHz
n n Laser-Trimmed Slope of 1mA/decade - Temperature Stable
n n Laser-Trimmed Intercept of 1mV - Temperature Stable
n n Less than 2dB Log Non-Linearity
n n Limiter Output: 1.6dB Gain Flatness, 2Phase Variation
for -44dBm to 0dBm inputs @ 10.7MHz
n n Balanced Circuitry for Stability
n n Minimal External Component Requirement
a 3.30
27
a
3.31
DC LOGARITHMIC TRANSFER FUNCTION
AND ERROR CURVE FOR SINGLE AD641
INPUT VOLTAGE - mV
(EITHER SIGN)
2
1.0
0.1 1.0 1000.0 10.0 100.0
1
1.2
1.4
1.6
1.8
2.0
2.2
2.4
0.8
0.6
0.4
0.2
0
-0.2
-0.4
0
E
R
R
O
R

-

d
B
O
U
T
P
U
T

C
U
R
R
E
N
T

-

m
A
Because of it s high accur acy, t he act ual wavefor m dr iving t he AD641 must be
consider ed when calculat ing r esponses. When a wavefor m passes t hr ough a log
funct ion gener at or , t he mean value of t he r esult ant wavefor m changes. This does
not affect t he slope of t he r esponse, but t he appar ent int er cept is modified accor ding
t o Figur e 3.32.
THE EFFECT OF WAVEFORM ON INTERCEPT POINT
INPUT
WAVEFORM
PEAK
OR RMS
INTERCEPT
FACTOR
ERROR (RELATIVE
TO A DC INPUT)
Square Wave Either 1 0.00dB
Sine Wave Peak 2 6.02dB
Sine Wave RMS 1.414 ( 2) 3.01dB
Triwave Peak 2.718 (e) 8.68dB
Triwave RMS 1.569 (e/ 3) 3.91dB
Gaussian Noise RMS 1.887 5.52dB
a 3.32
The AD641 is calibr at ed and laser t r immed t o give it s defined r esponse t o a DC level
or a symmet r ical 2kHz squar e wave. It is also specified t o have an int er cept of 2mV
for a sinewave input (t hat is t o say a 2kHz sinewave of amplit ude 2mV peak [not
28
peak-t o-peak] gives t he same mean out put signal as a DC or squar e wave signal of
1mV).
The wavefor m also affect s t he r ipple or nonlinear it y of t he log r esponse. This r ipple
is gr eat est for DC or squar e wave input s because ever y value of t he input volt age
maps t o a single locat ion on t he t r ansfer funct ion, and t hus t r aces out t he full
nonlinear it ies of t he log r esponse. By cont r ast , a gener al t ime-var ying signal has a
cont inuum of values wit hin each cycle of it s wavefor m. The aver aged out put is
t her eby "smoot hed" because t he per iodic deviat ions away fr om t he ideal r esponse, as
t he wavefor m "sweeps over " t he t r ansfer funct ion, t end t o cancel. As is clear in
Figur e 3.33, t his smoot hing effect is gr eat est for a t r iwave.
a
3.33
THE EFFECT OF WAVEFORM ON AD641 LOG LINEARITY
2
0
-2
-4
-6
-8
-10
-70 -60 -50 -40 -30 -20 -10 -80
SQUARE
WAVE INPUT
SINE WAVE
INPUT
TRIWAVE
INPUT
D
E
V
I
A
T
I
O
N

F
R
O
M

E
X
A
C
T

L
O
G
A
R
I
T
H
M
I
C
T
R
A
N
S
F
E
R

F
U
N
C
T
I
O
N

-

d
B
INPUT AMPLITUDE IN dB ABOVE 1V, AT 10kHz
Each of t he five st ages in t he AD641 has a gain of 10dB and a full-wave det ect ed
out put . The t r ansfer funct ion for t he device was shown in Figur e 3.21 along wit h t he
er r or cur ve. Not e t he excellent log linear it y over an input r ange of 1 t o 100mV
(40dB). Alt hough well suit ed t o RF applicat ions, t he AD641 is dc-coupled
t hr oughout . This allows it t o be used in LF and VLF syst ems, including audio
measur ement s, sonar , and ot her inst r ument at ion applicat ions r equir ing oper at ion t o
low fr equencies or even dc.
The limit er out put of t he AD641 has bet t er t han 1.6dB gain flat ness (-44dBm t o
0dBm @10.7MHz) and less t han 2 phase var iat ion, allowing it t o be used as a polar
demodulat or
The AD606 is a complet e monolit hic 50MHz bandwidt h log amp using 9 st ages of
successive det ect ion, and is shown in Figur e 3.34. Key specificat ions ar e
summar ized in Figur e 3.35. Seven of t he amplifier /det ect or st ages handle input s
fr om 80dBm (32V r ms) up t o about 14dBm (45mV r ms). The noise floor is about
83dBm (18V r ms). Anot her t wo par allel st ages r eceive t he input at t enuat ed by
22.3dB, and r espond t o input s up t o +10dBm (707mV r ms). The gain of each st age is
11.15dB and is accur at ely st abilized over t emper at ur e by a pr ecise biasing syst em.
29
The AD606 pr ovides bot h logar it hmic and limit ed out put s. The logar it hmic out put is
fr om a t hr ee-pole post -demodulat ion lowpass filt er and pr ovides an out put volt age of
+0.1V DC t o +4V DC. The logar it hmic scaling is such t hat t he out put is +0.5V for a
sinusoidal input of 75dBm, and +3.5V at an input of +5dBm. Over t his r ange, t he
log linear it y is t ypically wit hin 0.4dB.
a
3.34
AD606 50MHz, 80dB LOG AMP BLOCK DIAGRAM
X2
X1
16 15 14 13 12 11 10 9
8 7 6 5
4
3 2 1
REFERENCE
AND POWER UP
FINAL
LIMITER
360k
360k
30pF
30pF
30k
30k
OFFSET-NULL
LOW-PASS FILTER
1.5k
250
1.5k
12A/dB
ONE-POLE
FILTER
2A/dB
AD606
MAIN SIGNAL PATH
11.15 dB/STAGE
TWO-POLE
SALLEN-KEY
FILTER
2pF
2pF
9.375k
9.375k
HIGH-END
DETECTORS
INHI COMM PRUP VPOS FIL1 FIL2 LADJ LMHI
INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO
AD606 LOG AMP KEY FEATURES
n n Dynamic Range: 75dBm to +5dBm (80dB)
n n Input Noise: < 1.5nV/ Hz
n n Usable from 200Hz to Greater than 50MHz
n n Slope: 37.5mV/dB Voltage Output
n n On-Chip Lowpass Output Filter
n n Limiter Output: 1.6dB Gain Flatness, 2Phase Variation
for -44dBm to 0dBm inputs @ 10.7MHz
n n +5V Single-Supply, 65mW Power Consumption
a 3.35
30
The AD606 can oper at e above and below t hese limit s, wit h r educed linear it y, t o
pr ovide as much as 90dB of conver sion r ange. A second lowpass filt er aut omat ically
nulls t he input offset of t he fir st st age down t o t he submicr ovolt level.
The AD606's limit er out put pr ovides a har d-limit ed signal out put as a differ ent ial
cur r ent of 1.2mA fr om open-collect or out put s. In a t ypical applicat ion, bot h of t hese
out put s ar e loaded by 200 r esist or s t o pr ovide a volt age gain of mor e t han 90dB
fr om t he input . This limit ing amplifier has except ionally low amplit ude-t o-phase
conver sion. The limit er out put has 1dB out put flat ness and 3 phase st abilit y over
an 80dB r ange at 10.7MHz.
31
RECEI VER OVERVI EW
Wa l t Kest er , Bob Cl a r k e
We will now consider how t he pr eviously discussed building blocks can be used in
designing a r eceiver . Fir st , consider t he analog super het er odyne r eceiver invent ed in
1917 by Major Edwin H. Ar mst r ong (see Figur e 3.36). This ar chit ect ur e r epr esent ed
a significant impr ovement over single-st age dir ect conver sion (homodyne) r eceiver s
which had pr eviously been const r uct ed using t uned RF amplifier s, a single det ect or ,
and an audio gain st age. A significant advant age of t he super het er odyne r eceiver is
t hat it is much easier and mor e economical t o have t he gain and select ivit y of a
r eceiver at fixed int er mediat e fr equencies (IF) t han t o have t he gain and fr equency-
select ive cir cuit s "t une" over a band of fr equencies.
a
DUAL CONVERSION SUPERHET RECEIVER
(EXAMPLE FREQUENCIES)
3.36
900MHz
RF
LO1
TUNED
LO2
FIXED
1ST IF
240MHz
2ND IF
10.7MHz
IF STRIP
DEMODULATOR
The r eceiver shown is a dual conver sion r eceiver wit h t wo int er mediat e fr equency
(IF) st ages. The fr equencies chosen ar e t ypical in digit al mobile r adio (DMR), but t he
pr inciples apply t o ot her syst ems as well. The 900MHz RF signal is mixed down t o
t he fir st IF fr equency of 240MHz. Tuning is accomplished by t he fir st local oscillat or
(LO1). The LO1 fr equency is chosen such t hat t he out put of t he fir st mixer is at t he
fir st IF fr equency, 240MHz. Choosing a r elat ively high fir st IF fr equency eases t he
r equir ement on t he image fr equency r eject ion filt er as will be discussed in t he next
sect ion on mixer s. The fir st IF is t hen mixed down t o t he second IF fr equency of
10.7MHz, wher e it is demodulat ed (eit her using analog or digit al t echniques).
Because of t he wide dynamic r ange of t he RF signal, such a r eceiver r equir es t he use
of aut omat ic gain cont r ol, volt age cont r olled amplifier s, and in some cases
(depending on t he t ype of demodulat ion), logar it hmic amplifier s.
32
Receiver design is a complicat ed ar t , and t her e ar e many t r adeoffs t hat can be made
bet ween IF fr equencies, single-conver sion vs. double-conver sion or t r iple conver sion,
filt er cost and complexit y at each st age in t he r eceiver , demodulat ion schemes, et c.
Ther e ar e many excellent r efer ences on t he subject , and t he pur pose of t his sect ion is
only t o acquaint t he design engineer wit h some of t he building block ICs which can
make r eceiver design much easier .
Befor e we look at fur t her det ails of a r eceiver , t he subject of mixing r equir es fur t her
discussion.
33
MULTI P LI ERS, MODULATORS, AND MI XERS
Ba r r i e Gi l ber t , Bob Cl a r k e
An idealized mixer is shown in Figur e 3.37. An RF (or IF) mixer (not t o be confused
wit h video and audio mixer s) is an act ive or passive device t hat conver t s a signal
fr om one fr equency t o anot her . It can eit her modulat e or demodulat e a signal. It has
t hr ee signal connect ions, which ar e called ports in t he language of r adio engineer s.
These t hr ee por t s ar e t he r adio fr equency (RF) input , t he local oscillat or (LO) input ,
and t he int er mediat e fr equency (IF) out put .
a
THE MIXING PROCESS
3.37
RF INPUT
IF OUTPUT
IDEAL MIXER
LO INPUT
f
LO
f
RF
+ f
LO
f
RF
- f
LO
f
RF
A mixer t akes an RF input signal at a fr equency f
RF
, mixes it wit h a LO signal at a
fr equency f
LO
, and pr oduces an IF out put signal t hat consist s of t he sum and
differ ence fr equencies, f
RF
f
LO
. The user pr ovides a bandpass filt er t hat follows
t he mixer and select s t he sum (f
RF
+ f
LO
) or differ ence (f
RF
f
LO
) fr equency.
Some point s t o not e about mixer s and t heir t er minology:
When t he sum fr equency is used as t he IF, t he mixer called an upconverter; when
t he differ ence is used, t he mixer is called a downconverter. The for mer is oft en used
in a t r ansmit channel, t he lat t er in a r eceive channel.
In a r eceiver , when t he LO fr equency is below t he RF, it is called low-side injection
and t he mixer a low-side downconverter; when t he LO is above t he RF, it is called
high-side injection, and t he mixer a high-side downconverter.
Each of t he out put s is only half t he amplit ude (one-quar t er t he power ) of t he
individual input s; t hus, t her e is a loss of 6dB in t his ideal linear mixer . (In a
34
pr act ical mult iplier , t he conver sion loss may be gr eat er t han 6dB, depending on t he
scaling par amet er s of t he device. Her e, we assume a mathematical mult iplier ,
having no dimensional at t r ibut es.
A mixer can be implement ed in sever al ways, using act ive or passive t echniques.
A br ief r eview of t he var ious classes of nonlinear element s t hat can be used for
fr equency t r anslat ion may be helpful in set t ing t he cont ext . We can ident ify t hr ee
subclasses of cir cuit s, shar ing cer t ain similar it ies. All ar e in t he class of signal
mult iplier s, pr oducing at t heir out put a signal which is, in one way or anot her , t he
pr oduct of it s t wo input s. They ar e multipliers, modulators, and mixers.
An analog multiplier gener ally has t wo signal input por t s, which can be called X and
Y, and gener at es an out put W t hat is t he linear pr oduct of t he volt ages applied t o
t hese t wo por t s. To r et ain dimensional consist ency, t he analog linear mult iplicat ion
funct ion must invoke t he use of a r efer ence volt age, which we can call U, t hus
W=XY/U. In some cases, U is act ually a t hir d input t hat can be used t o implement
analog division.
Ther e ar e t hr ee funct ional cat egor ies of mult iplier s: In single-quadrant mult iplier s,
X and Y must be unipolar ; in two-quadrant mult iplier s, one of t he input s may be
bipolar ; in four-quadrant mult iplier s, bot h X and Y may be bipolar . Analog Devices
pr oduces a wide r ange of "linear " mult iplier s, including t he AD534, AD538, AD539,
AD633, AD734, AD834 and AD835, pr oviding t he highest available accur acy
(0.02% for t he AD734) t o t he highest speed (mor e t han 500MHz for t he AD834).
Modulators (somet imes called balanced-modulators, doubly-balanced modulators or
even on occasions high level mixers) can be viewed as sign-changers. The t wo input s,
X and Y, gener at e an out put W, which is simply one of t hese input s (say, Y)
mult iplied by just t he sign of t he ot her (say, X), t hat is W = Ysign(X). Ther efor e, no
r efer ence volt age is r equir ed. A good modulat or exhibit s ver y high linear it y in it s
signal pat h, wit h pr ecisely equal gain for posit ive and negat ive values of Y, and
pr ecisely equal gain for posit ive and negat ive values of X. Ideally, t he amplit ude of
t he X input needed t o fully swit ch t he out put sign is ver y small, t hat is, t he X-input
exhibit s a compar at or -like behavior . In some cases, wher e t his input may be a logic
signal, a simpler X-channel can be used. A highly-linear mixer such as t he AD831 is
well-suit ed as a modulat or .
A mixer is a modulat or opt imized for fr equency-t r anslat ion. It s place in t he signal
pat h is usually close t o t he ant enna, wher e bot h t he want ed and (oft en lar ge)
unwant ed signals coexist at it s signal input , usually called t he RF port. Thus, t he
mixer must exhibit excellent linear it y in t he sense t hat it s out put (at t he IF por t ) is
expect ed t o incr ease by t he same number of dB as a t est signal applied t o t he RF
por t , up t o as high as level as possible. This at t r ibut e is defined bot h by t he 1dB
gain-compr ession and t he 3r d-or der int er cept (lat er explained). The conver sion
pr ocess is dr iven by an input applied t o t he LO por t .
Noise and mat ching char act er ist ics ar e cr ucial t o achieving accept able levels of
per for mance in a r eceiver s mixer . It is desir able t o keep t he LO power t o a
minimum t o minimize cr oss-t alk bet ween t he t hr ee por t s, but t his oft en conflict s
wit h ot her r equir ement s. The gain fr om t he RF por t t o it s IF por t at specified RF
and LO fr equencies is called t he conversion gain and in classical diode-br idge mixer s
is less t han 4dB. Active mixers pr ovide higher conver sion gain, and bet t er por t -por t
35
isolat ion, but oft en at t he expense of noise and linear it y. It is not usually possibly
(nor even desir able) t o descr ibe mixer behavior using equat ions r elat ing t he
inst ant aneous values of input s and out put s; inst ead, we gener ally seek t o
char act er ize mixer s in t er ms of t heir non-ideal cr oss-pr oduct t er ms at t he out put . In
t his class, Analog Devices has t he AD831, and mixer s ar e found embedded in t he
AD607, AD608 and ot her signal-pr ocessing ICs.
Thus far , we have seen t hat mult iplier s ar e linear in t heir r esponse t o t he
inst ant aneous value of bot h of t heir input volt ages; modulat or s ar e linear in t heir
r esponse t o one input , t he ot her mer ely flipping t he sign of t his signal at r egular
int er vals, wit h vir t ually zer o t r ansit ion t ime, and beyond t hat having ideally no
ot her effect on t he signal; mixer s ar e a sor t of RF half-br eed, ideally being ver y
linear on t he RF input , and binar y in t heir swit ching funct ion in r esponse t o t he LO
input , but in r ealit y being nonideal in bot h r espect s; t hey ar e opt imized for ver y low
noise and minimal int er modulat ion dist or t ion.
Mi xi n g Usi n g a n I d ea l An a log Mu lt i p li er
Figur e 3.38 shows a gr eat ly simplified RF mixer by assuming t he use of an analog
mult iplier .
Ideally, t he mult iplier has no noise, no limit t o t he maximum signal amplit ude, and
no int er modulat ion bet ween t he var ious RF signals (t hat is, no spur ious
nonlinear it ies). Figur e 3.39 shows t he r esult of mixing (= mult iplying) an RF input
of sin
RF
t wit h (= by) a LO input of sin
LO
t , wher e
RF
= 211MHz and
LO
=
210MHz.
Clear ly, t o bet t er under st and mixer behavior , we will need t o consider not only t he
t ime-domain wavefor ms, as shown her e, but also t he spect r um of t he IF out put .
Figur e 3.40 shows t he out put spect r um cor r esponding t o t he above IF wavefor m.
36
a
"MIXING" USING AN ANALOG MULTIPLIER
3.38
RF INPUT
IF OUTPUT
ANALOG MULTIPLIER, e.g., AD834
V
X
V
Y
V
X
LO INPUT
V
Y
a
3.39
INPUTS AND OUTPUTS FOR MULTIPLYING MIXER
FOR f
RF
= 11MHz, f
LO
= 10MHz
RF
LO
IF
Horizontal:
200ns/div.
37
a
OUTPUT SPECTRUM FOR MULTIPLYING MIXER
FOR f
RF
= 11MHz, f
LO
= 10MHz
3.40
LINEAR
AMPLITUDE
FREQUENCY (MHz)
0.8
0.6
0.4
0.2
0
0 10 20 30 40 50 60
0.5 0.5
DIFFERENCE
AT 1MHz
SUM AT
21MHz
NO HARMONICS
f
LO
= 10MHz
f
RF
= 11MHz
LO AND RF FULLY SUPPRESSED
Ther e is no myst er y so far . The mat hemat ics ar e simple. Neglect ing scaling issues
(r eal signals ar e volt ages; t hus a pr act ical mult iplier needs an embedded volt age
r efer ence, ignor ed her e) t he r elat ionship is:
sin
RF
t sin
LO
t =
1
/
2
{ cos(
RF
+
LO
)t + cos(
RF

LO
)t } Eq. 1
The mult iplier has t hus t r ansfor med t he RF input int o t wo, equal-amplit ude
cosinusoidal component s at it s out put (t he IF por t ), one at t he sum fr equency,
RF
+

LO
, and t he ot her at t he differ ence fr equency,
RF

LO
.
In pr act ice, an analog mult iplier would be a poor choice for a mixer because t he t wo
linear input s br ing wit h t hem a ser ious noise penalt y.
I ma ge Resp on se
A r eceiver using even t his mat hemat ically per fect mixer suffer s a basic pr oblem,
t hat of image response. Consider t he use of a low-side downconver t er . The want ed
out put is found at t he fr equency
IF
=
RF

LO
. So we might suppose t hat t he only
component of t he RF spect r um t hat finds it s way t hr ough t he mixer sieve t o t he
nar r ow IF passband is t he want ed component at
RF
. But we could have just as
easily wr it t en (1) as
sin
RF
t sin
LO
t =
1
/
2
{ cos(
RF
+
LO
)t + cos(
LO

RF
)t } Eq. 1a
because t he cosine funct ion is symmet r ic about t = 0. So t her e is anot her spect r al
component at t he RF input t hat falls in t he IF passband, namely t he one for which

IF
=
LO

RF
, in t his case, t he image fr equency.
38
Consider t he above example, wher e f
LO

= 10MHz and f
IF
= 1MHz; t he want ed
r esponse is at t he IF fr equency, f
IF
= 1MHz for f
RF
= 11MHz. However , t he mixer
pr oduces t he same IF in r esponse t o t he image frequency, f
IMAGE
= 9MHz (see
Figur e 3.41).
IMAGE RESPONSE
3.41
f
IF
f
IMAGE
f
RF
f
LO
f
IF
f
IF
FREQUENCY (MHz)
0 1 9 10 11
SIGNAL AT THE
IMAGE FREQUENCY
ALSO PRODUCES A
RESPONSE AT THE
IF FREQUENCY
The most pr act ical solut ion t o t his dilemma is t o car efully choose t he IF fr equency t o
minimize t he likelihood of image sensit ivit y and also include an image-r eject filt er at
t he RF input , just ahead of t he mixer . Anot her appr oach is t o use a special t ype of
mixer cir cuit t hat does not r espond t o t he image fr equency. This appr oach r equir es
cir cuit r y which is consider ably mor e complex, and for t his r eason has gener ally been
unpopular , but it is becoming mor e pr act ical in a moder n IC implement at ion. It has
t he fur t her disadvant age of higher power consumpt ion, since t wo mixer cells
oper at ing in quadr at ur e ar e r equir ed.
Th e I d ea l Mi xer
Ideally, t o meet t he low-noise, high-linear it y object ives of a mixer we need some
cir cuit t hat implement s a polar it y-swit ching funct ion in r esponse t o t he LO input .
Thus, t he mixer can be r educed t o Figur e 3.42, which shows t he RF signal being
split int o in-phase (0) and ant i-phase (180) component s; a changeover swit ch,
dr iven by t he local oscillat or (LO) signal, alt er nat ely select s t he in-phase and
ant iphase signals. Thus r educed t o essent ials, t he ideal mixer can be modeled as a
sign-swit cher .
39
a
AN IDEAL SWITCHING MIXER
3.42
RF INPUT
IF OUTPUT
SWITCH, f
LO
+1
-1
In a per fect embodiment , t his mixer would have no noise (t he swit ch would have
zer o r esist ance), no limit t o t he maximum signal amplit ude, and would develop no
int er modulat ion bet ween t he var ious RF signals. Alt hough simple in concept , t he
wavefor m at t he int er mediat e fr equency (IF) out put can be ver y complex for even a
small number of signals in t he input spect r um. Figur e 3.43 shows t he r esult of
mixing just a single input at 11MHz wit h an LO of 10MHz.
The wanted IF at t he differ ence fr equency of 1MHz is st ill visible in t his wavefor m,
and t he 21MHz sum is also appar ent . But t he spect r um of t his wavefor m is clear ly
mor e complex t han t hat obt ained using t he analog mult iplier . How ar e we t o
analyze t his?
40
a
3.43
INPUTS AND OUTPUTS FOR IDEAL SWITCHING MIXER
FOR f
RF
= 11MHz, f
LO
= 10MHz
RF
LO
IF
Horizontal:
200ns/div.
We st ill have a pr oduct , but now it is t hat of a sinusoid (t he RF input ) at
RF
and a
var iable t hat can only have t he values +1 or 1, t hat is, a unit squar e wave at
LO
.
The lat t er can be expr essed as a Four ier ser ies
S
LO
=
4
/

{ sin
LO
t -
1
/
3
sin3
LO
t +
1
/
5
sin5
LO
t . . . . } Eq. 2
Thus, t he out put of t he swit ching mixer is it s RF input , which we can simplify as
sin
RF
t , mult iplied by t he above expansion for t he squar e wave, pr oducing
S
IF

=
4
/

{ sin
RF
t sin
LO
t
1
/
3
sin
RF
t sin3
LO
t
+
1
/
5
sin5
RF
t sin5
LO
t . . . . } Eq. 3
Now expanding each of t he pr oduct s, we obt ain
S
IF
=
2
/

{ sin(
RF
+
LO
)t + sin(
RF

LO
)t

1
/
3
sin(
RF
+ 3
LO
)t
1
/
3
sin(
RF
3
LO
)t
+
1
/
5
sin(
RF
+ 5
LO
)t +
1
/
5
sin(
RF
5
LO
)t . . . } Eq. 4
or simply
S
IF
=
2
/

{ sin(
RF
+
LO
)t + sin(
RF

LO
)t + har monics } Eq. 5
The most impor t ant of t hese har monic component s ar e sket ched in Figur e 3.44 for
t he par t icular case used t o gener at e t he wavefor m shown in Figur e 3.43, t hat is, f
RF
= 11MHz and f
LO
= 10MHz. Because of t he 2/ t er m, a mixer has a minimum 3.92
dB inser t ion loss (and noise figur e) in t he absence of any gain.
41
a
3.44
OUTPUT SPECTRUM FOR SWITCHING MIXER
FOR f
RF
= 11MHz AND f
LO
= 10MHz
LINEAR
AMPLITUDE
0 10 20 30 40 50 60
FREQUENCY (MHz)
0.127
0.8
0.6
0.4
0.2
0
0.637 = -3.9dB
0.212 = -13.5dB
0.127 = -17.9dB
0.090 = -20.9dB
0.09
0.212
0.127
0.212
0.637
0.637
SUM AT
21MHz
WANTED IF
AT 1MHz
Not e t hat t he ideal (swit ching) mixer has exact ly t he same pr oblem of image
r esponse t o
LO

RF
as t he linear mult iplying mixer . The image r esponse is
somewhat subt le, as it does not immediat ely show up in t he out put spect r um: it is a
lat ent r esponse, await ing t he occur r ence of t he "wr ong" fr equency in t he input
spect r um.
Di od e-Ri n g Mi xer
For many year s, t he most common mixer t opology for high-per for mance applicat ions
has been t he diode-r ing mixer , one for m of which is shown in Figur e 3.45. The
diodes, which may be silicon junct ion, silicon Schot t ky-bar r ier or gallium-ar senide
t ypes, pr ovide t he essent ial swit ching act ion. We do not need t o analyze t his cir cuit
in gr eat det ail, but not e in passing t hat t he LO dr ive needs t o be quit e highoft en
a subst ant ial fr act ion of one wat t in or der t o ensur e t hat t he diode conduct ion is
st r ong enough t o achieve low noise and t o allow lar ge signals t o be conver t ed
wit hout excessive spur ious nonlinear it y.
Because of t he highly nonlinear nat ur e of t he diodes, t he impedances at t he t hr ee
por t s ar e poor ly cont r olled, making mat ching difficult . Fur t her mor e, t her e is
consider able coupling bet ween t he t hr ee por t s; t his, and t he high power needed at
t he LO por t , make it ver y likely t hat t her e will be some component of t he (highly-
dist or t ed) LO signal coupled back t owar d t he ant enna. Finally, it will be appar ent
t hat a passive mixer such as t his cannot pr ovide conver sion gain; in t he idealized
scenar io, t her e will be a conver sion loss of 2/ [as Eq. 4 shows], or 3.92dB. A
pr act ical mixer will have higher losses, due t o t he r esist ances of t he diodes and t he
losses in t he t r ansfor mer s.
42
a
3.45
DIODE-RING MIXER
RF
IN
IF
OUT
LO
IN
User s of t his t ype of mixer ar e accust omed t o judging t he signal handling
capabilit ies by a Level r at ing. Thus, a Level-17 mixer needs +17dBm (50mW) of
LO dr ive and can handle an RF input as high as +10dBm (1V). A t ypical mixer in
t his class would be t he Mini-Cir cuit s LRMS-1H, cover ing 2-500MHz, having a
nominal inser t ion loss of 6.25dB (8.5dB max), a wor st -case LO-RF isolat ion of 20dB
and a wor st -case LO-IF isolat ion of 22dB (t hese figur es for an LO fr equency of 250-
500MHz). The pr ice of t his component is appr oximat ely $10.00 in small quant it ies.
Even t he most expensive diode-r ing mixer s have similar dr ive power r equir ement s,
high losses and high coupling fr om t he LO por t .
FET Mi xer s
A moder n alt er nat ive t o t he diode-r ing mixer is one in which t he diodes ar e r eplaced
by FETs. The idea her e is t o r educe t he dist or t ion caused by t he inher ent
nonlinear it ies of junct ion diodes, whose incr ement al r esist ance var ies wit h t he
inst ant aneous signal cur r ent . To r educe t his effect , t he diodes ar e oft en dr iven t o
ver y high cur r ent levels. Indeed, some user s of diode-r ing mixer s push t hem t o
ext r emes, oper at ing at cur r ent levels close t o t hose which will cause t he diodes t o
fail by over -dissipat ion. Thus, in comment ing about a cer t ain minor var iat ion t o t he
diode-r ing-mixer , we r ead:
This helps t he mixer t o accept higher LO power wit hout bur ning out t he diodes!
(Fr om Wes Haywar d, S olid S tate Design for the Radio Amateur, ARRL, 1986,
Chapt er 6, p.120)
To avoid bur ning out t he diodes, some mixer s use t wo or four J -FETs in an
analogous way t o t hat shown in Figur e 3.45. The idea is t hat t he channel r esist ance
43
of a lar ge FET dr iven int o it s t r iode r egion of conduct ion can be as low as t he
dynamic r esist ance of a diode, t hus achieving similar conver sion gain and noise
levels. But t his low r esist ance ar ises wit hout any cur r ent flow in t he channel and it
is also mor e linear t han t hat of t he diodes when signal cur r ent does flow, t hus
r esult ing in lower int er modulat ion, and hence a lar ger over all dynamic r ange. MOS-
FETs can also be used in a similar way.
This st yle of FET-based mixer s is ver y at t r act ive for many high-per for mance
applicat ions. However , since t he act ive devices ar e st ill used only as swit ches, t hey
do not pr ovide power gain, and have t ypical inser t ion losses of 6 t o 8dB.
Fur t her mor e, t he balance of t hese mixer s is st ill cr it ically dependent on such t hings
as t r ansist or mat ching and t r ansfor mer winding accur acy, lar ge LO dr ives (volt s)
ar e needed, and t he over all mat ching r equir ement s cont inue t o be difficult t o
achieve over t he full fr equency r ange. Finally, of cour se, t hey ar e not dir ect ly
amenable t o monolit hic int egr at ion.
Anot her popular cir cuit , widely used in many inexpensive r eceiver s, is t he dual-gat e
MOS-FET mixer . In t his t ype of mixer , t he RF signal is applied t o one gat e of t he
FET and t he LO signal t o t he second gat e. The mult iplicat ion pr ocess is not ver y
well-defined, but in gener al t er ms r elies on t he fact t hat bot h t he fir st and second
gat es influence t he cur r ent in t he channel. The st r uct ur e can be modeled as t wo
FETs, wher e t he dr ain of t he lower FET (having t he RF input applied t o it ) is
int imat ely connect ed t o t he sour ce of t he upper FET (having t he LO input on it s
gat e). The lower FET oper at es in it s t r iode r egion, and t hus exhibit s a g
m
t hat is a
funct ion of it s dr ain volt age, cont r olled by t he LO. Though not r eadily modeled t o
gr eat accur acy, t his mixer , like many ot her s, can be pr agmat ically opt imized t o
achieve useful per for mance, t hough not wit hout t he suppor t of many associat ed
passive component s for biasing and mat ching.
Cla ssi c Act i ve Mi xer
The diode-r ing mixer not only has cer t ain per for mance limit at ions, but it is also not
amenable t o fabr icat ion using int egr at ed cir cuit t echnologies, at least in t he for m
shown in Figur e 3.45. In t he mid sixt ies it was r ealized t hat t he four diodes could be
r eplaced by four t r ansist or s t o per for m essent ially t he same swit ching funct ion. This
for med t he basis of t he now-classical bipolar cir cuit shown in Figur e 3.46, which is a
minimal configur at ion for t he fully-balanced ver sion. Millions of such mixer s have
been made, including var iant s in CMOS and GaAs. We will limit our discussion t o
t he BJ T for m, an example of which is t he Mot or ola MC1496, which, alt hough quit e
r udiment ar y in st r uct ur e, has been a mainst ay in semi-discr et e r eceiver designs for
about 25 year s.
44
LO
INPUT
a
3.46
CLASSIC ACTIVE MIXER
IF OUTPUT
Q2
I
EE
Q6 Q5
Q4
Q3
Q1
RF
INPUT
The active mixer is at t r act ive for t he following r easons:
It can be monolit hically int egr at ed wit h ot her signal pr ocessing cir cuit r y.
It can pr ovide conver sion gain, wher eas a diode-r ing mixer always has an inser t ion
loss. (Not e: Act ive mixer s may have gain. The analog Devices' AD831 act ive mixer ,
for example, amplifies t he r esult in Eq. 5 by /2 t o pr ovide unit y gain fr om RF t o IF.)
It r equir es much less power t o dr ive t he LO por t .
It pr ovides excellent isolat ion bet ween t he signal por t s.
Is far less sensit ive t o load-mat ching, r equir ing neit her diplexer nor br oadband
t er minat ion.
Using appr opr iat e design t echniques it can pr ovide t r ade-offs bet ween t hir d-or der
int er cept (3OI or IP3) and t he 1dB gain-compr ession point (P
1dB
), on t he one hand,
and t ot al power consumpt ion (P
D
) on t he ot her . (That is, including t he LO power ,
which in a passive mixer is "hidden" in t he dr ive cir cuit r y.)
Ba si c Op er a t i on of t h e Act i ve Mi xer
Unlike t he diode-r ing mixer , which per for ms t he polar it y-r ever sing swit ching
funct ion in t he volt age domain, t he act ive mixer per for ms t he swit ching funct ion in
t he cur r ent domain. Thus t he act ive mixer cor e (t r ansist or s Q3 t hr ough Q6 in Figur e
3.46) must be dr iven by cur r ent -mode signals. The volt age-t o-cur r ent conver t er
for med by Q1 and Q2 r eceives t he volt age-mode RF signal at t heir base t er minals
and t r ansfor ms it int o a differ ent ial pair of cur r ent s at t he t heir collect or s.
45
A second point of differ ence bet ween t he act ive mixer and diode r ing mixer ,
t her efor e, is t hat t he act ive mixer r esponds only t o magnit ude of t he input volt age,
not t o t he input power ; t hat is, t he act ive mixer is not mat ched t o t he sour ce. (The
concept of mat ching is t hat bot h t he cur r ent and t he volt age at some por t ar e used
by t he cir cuit r y which for ms t hat por t ). By alt er ing t he bias cur r ent , I
EE
, t he
t r ansconduct ance of t he input pair Q1-Q2 can be set over a wide r ange. Using t his
capabilit y, an act ive mixer can pr ovide var iable gain.
A t hir d point of differ ence is t hat t he out put (at t he collect or s of Q3Q6) is in t he
for m of a cur r ent , and can be conver t ed back t o a volt age at some ot her impedance
level t o t hat used at t he input , hence, can pr ovide fur t her gain. By combining bot h
out put cur r ent s (t ypically, using a t r ansfor mer ) t his volt age gain can be doubled.
Finally, it will be appar ent t hat t he isolat ion bet ween t he var ious por t s, in
par t icular , fr om t he LO por t t o t he RF por t , is inher ent ly much lower t han can be
achieved in t he diode r ing mixer , due t o t he r ever sed-biased junct ions t hat exist
bet ween t he por t s.
Br iefly st at ed, t hough, t he oper at ion is as follows. In t he absence of any volt age
differ ence bet ween t he bases of Q1 and Q2, t he collect or cur r ent s of t hese t wo
t r ansist or s ar e essent ially equal. Thus, a volt age applied t o t he LO input r esult s in
no change of out put cur r ent . Should a small DC offset volt age be pr esent at t he RF
input (due t ypically t o mismat ch in t he emit t er ar eas of Q1 and Q2), t his will only
r esult in a small feedt hr ough of t he LO signal t o t he IF out put , which will be
blocked by t he fir st IF filt er .
Conver sely, if an RF signal is applied t o t he RF por t , but no volt age differ ence is
applied t o t he LO input , t he out put cur r ent s will again be balanced. A small offset
volt age (due now t o emit t er mismat ches in Q3Q6) may cause some RF signal
feedt hr ough t o t he IF out put ; as befor e, t his will be r eject ed by t he IF filt er s. It is
only when a signal is applied t o bot h t he RF and LO por t s t hat a signal appear s at
t he out put ; hence, t he t er m doubly-balanced mixer .
Act ive mixer s can r ealize t heir gain in one ot her way: t he mat ching net wor ks used
t o t r ansfor m a 50 sour ce t o t he (usually) high input impedance of t he mixer
pr ovides an impedance t r ansfor mat ion and t hus volt age gain due t o t he impedance
st ep up. Thus, an act ive mixer t hat has loss when t he input is t er minat ed in a
br oadband 50 t er minat ion can have gain when an input mat ching net wor k is
used.
Th e AD831, 500MHz, Low Di st or t i on Act i ve Mi xer
The AD831 is a low dist or t ion, wide dynamic r ange, monolit hic mixer for use in such
applicat ions as RF t o IF down conver sion in HF and VHF r eceiver s, t he second
mixer in digit al mobile r adio base st at ions, dir ect -t o-baseband conver sion,
quadr at ur e modulat ion and demodulat ion, and doppler -fr equency shift det ect ion in
ult r asound imaging applicat ions. The mixer includes a local oscillat or dr iver and a
low-noise out put amplifier . The AD831 pr ovides a +24dBm t hir d-or der int er cept
point for 10dBm local oscillat or power , t hus impr oving syst em per for mance and
r educing syst em cost , compar ed t o passive mixer s, by eliminat ing t he need for a high
power local oscillat or dr iver and it s associat ed shielding and isolat ion pr oblems. A
46
simplified block diagr am of t he AD831 is shown in Figur e 3.47, and key
specificat ions in Figur e 3.48.
a
3.47
AD831 500MHz LOW DISTORTION ACTIVE MIXER
51.1
110
IF
OUTPUT
R
T
BPF
R
T
NC
-5V
0.1F
0.1F
+5V
51.1
0.1F
+5V
-5V
0.1F
-5V
0.1F
C2
L1
C1
RF
INPUT
CF
82pF
CF
82pF
0.1F
+5V
IFN VP IFP AP
GND
VN
RFP
RFN
VN
VP
LON LOP
VP
GND
BIAS
VN AD831
Top View
50
50
6
7
8
4
5
9 10 11 12 13
AN
VFB
COM
OUT
14
15
16
17
18
1 2 3 19 20
LO INPUT
-10 dBm
AD831 ACTIVE MIXER KEY SPECIFICATIONS
n n Doubly-Balanced Mixer, 10dB Noise Figure
n n Low Distortion (IF = 10.7MHz, RF to 200MHz):
u u +24dBm Third Order Intercept
u u +10dBm 1dB Compression Point
n n Low LO Drive Required: 10dBm
n n Bandwidth:
u u 500MHz RF and LO Input Bandwidths
u u 250MHz Differential Current IF Output
u u DC to > 200MHz Single-Ended Voltage IF Output
a 3.48
47
Noi se Fi gu r e
Noise Figur e (NF) is a figur e of mer it used t o det er mine how a device degr ades t he
signal-t o-noise r at io of it s input . Not e: in RF syst ems, t he impedance is 50 unless
ot her wise st at ed. Mat hemat ically, noise figur e is defined as:
NF
S
I
N
I
S
O
N
O
= 20
10
log
/
/
,
wher e S
I
/N
I
is t he input signal-t o-noise r at io, and S
O
/N
O
is t he out put signal-t o-
noise r at io.
Typical noise figur es for passive mixer s wit h post amplifier s ar e 12 t o 15dB. The NF
of t he AD831 is 10dB wit h a mat ched input , which is adequat e for applicat ions in
which t her e is gain in fr ont of t he mixer .
Noise Figur e is used in a "cascaded noise figur e calculat ion", which gives t he over all
noise figur e of a r eceiver . Basically, t he noise figur e of each st age is conver t ed int o a
noise fact or (F = ant ilog NF/10) and plugged int o a spr eadsheet cont aining t he Fr iis
Equat ion:
F
RECEIVER
F
F
G
F
G G
F
K
G
J
J
K
K
N
= +

+

+

=

1
2
1
1
3
1
1 2
1
1
1
4
,
wher e F
N
and G
N
ar e t he noise fact or and gain, r espect ively, of t he Nt h st age in t he
r eceiver .
For a passive diode-r ing mixer , t he noise figur e is t he same as t he inser t ion loss. For
an act ive mixer , however , noise is added t o t he signal by t he act ive devices in t he
signal pat h. The differ ence bet ween t he noise figur e of a mat ched act ive mixer and
an unmat ched act ive mixer can be sever al dB due t o t he volt age gain of t he
impedance-mat ching net wor k, which act s as a noiseless pr eamplifier (Figur e 3.49).
In t he case of t he AD831, t he noise figur e for t he mat ched cir cuit is 10 dB (at
70MHz) and t he unmat ched cir cuit wit h it s input t er minat ed wit h a 50 r esist or is
16dB.
The noise figur e is 11.7dB at 220 MHz using t he ext er nal mat ching net wor k shown
in Figur e 3.49. The values shown ar e for 220 MHz and pr ovide 10 dB of volt age
gain.
48
a
3.49
AD831 ACTIVE MIXER WITH 220MHz
EXTERNAL MATCHING NETWORK
AD831
RFP
RFN
7
6
C2
L2
L1
C1
RF
INPUT
L1: 100nH, COILCRAFT 1008CS-101
L2: 56nH, COILCRAFT 1008CS-560
C1, C2: 2-10pF CERAMIC VARIABLE
I n t er mod u la t i on Di st or t i on
Even befor e t he mixing pr ocess in t he cor e, t he ent ir e signal spect r um co-exist s
wit hin t he RF input st age. This par t of t he mixer is inevit ably nonlinear , t o a
gr eat er or lesser ext ent , and, wit h or wit hout t he LO input oper at ive, gener at es a
ver y lar ge number of int er modulat ion pr oduct s.
Thus, t he key object ives in t he design of a high-per for mance act ive mixer ar e t o
achieve a ver y linear RF input sect ion, followed by a near -ideal polar it y-swit ching
st age, followed by a ver y linear IF out put amplifier (if used) pr ior t o t he fir st filt er .
1d B Comp r essi on P oi n t a n d Th i r d -Or d er I n t er cep t P oi n t
For a single-sinusoid input t o a syst em, a point will be r eached as t he input
amplit ude is incr eased at which t he appar ent gain becomes 1dB lower t han t hat
obser ved at lower input amplit udes. This is called t he 1dB gain compr ession level,
which well abbr eviat e P
1dB
, and is usually quot ed in dBm, or decibels above 1mW,
t hat is, it is expr essed as a power measur ement . When using an act ive mixer wit h
an input mat ching net wor k, t he gain of t he input mat ching net wor k must be t aken
int o account when defining t he syst em in t er ms of an act ive mixer s 1dB
compr ession point , since t he impedance t r ansfor mat ion of t he net wor k incr eases t he
input volt age t o mixer .
Anot her met r ic used in char act er izing mixer s is t he t hir d-or der int er cept , known as
P
3OI
or IP3. If t wo t ones of fr equency f
1
and f
2
(r epr esent ing t wo adjacent channels
in a communicat ions syst em, for example) ar e applied t o a non-linear syst em, t her e
will be a lar ge number of int er modulat ion pr oduct s gener at ed. The t hir d-or der
49
dist or t ion pr oduct s which fall at 2f
2
-f
1
and 2f
1
-f
2
ar e par t icular ly t r oublesome,
because t hey ar e close t o t he or iginal fr equencies (see Figur e 3.50). If t he t wo t ones
r epr esent t r ue signals, t hen t he t hir d-or der IMD pr oduct s can int er fer e wit h signals
in t he adjacent channels.
a
THIRD-ORDER INTERMODULATION DISTORTION
3.50
FREQUENCY
f
1
f
2
2f
2
- f
1
2f
1
- f
2
Rat her t han measur ing t he t hir d-or der dist or t ion pr oduct s for a var iet y of signal
amplit udes, t he concept of t hir d-or der int er cept can be used t o ext r act t he IMD
infor mat ion and is oft en used as a figur e of mer it for mixer s and amplifier s in RF
applicat ions.
A plot (Figur e 3.51) of t he power levels at t he out put of t he syst em for t he
fundament al of t he out put fr equency and for it s t hir d har monic, plot t ed ver sus t he
input power , will gener ally yield a pair of st r aight lines which event ually int er sect
(at t he 3r d or der int er cept point , IP3).
50
a
3.51
THIRD-ORDER INTERCEPT USING DATA FOR AD831
OUTPUT
POWER
(dBm)
+24
+10
-10
-78
IF = 10.7 MHz
RF = 100 MHz
LINEAR
OUTPUT
3RD ORDER INTERCEPT POINT
1 dB
IP3
INPUT POWER (dBm)
3RD ORDER IMD
AT 2f
1
- f
2
AND 2f
2
- f
1
1 dB COMPRESSION POINT
The pr oblem wit h t his met r ic is t hat it has meaning only for cer t ain simple cases. In
par t icular , t he 3r d har monic is assumed t o incr ease at t hr ee t imes t he r at e of t he
fundament al. The appeal of P
3OI
lies in t he fact t hat it is easily measur ed, or at
least , it is easy t o obt ain measur ement s. (The measur ement s ar e not har d t o make,
but it will be found t hat t he appar ent P
3OI
is signal-dependent ). Apply a low level
signal, at some known level P
O
(in dBm, see Figur e 3.51), measur e t he out put power
at t he fundament al, P
1
(in r elat ive t er ms, dBc) and at t he t hir d har monic, P
3
(also in
dBc) and fr om simple geomet r y calculat e
P
3OI
= P
O
+
1
/
2
(P
1
P
3
) Eq. 6
The non-linear it y in some classical cir cuit s, such as t he diode-r ing mixer ,
appr oximat es a cubic funct ion, and t he above r elat ionship holds, but in pr act ice, t he
P
3OI
can be quit e misleading, for sever al r easons. Fir st , ot her cir cuit s may not , in
gener al, exhibit t his t ype of non-linear it y. This t ype of behavior could easily lead t o
appar ent t hir d-or der int er cept values which wer e impr essively high (t heor et ically
infinit e, if measur ed using signals of less t han t he cr it ical amplit ude).
A spur chart is a compilat ion of t he nf
1
mf
2
pr oduct s t hat r esult fr om t he mixing
pr ocess. The spur char t is useful because it allows an engineer developing a
fr equency plan for a r adio t o ident ify possible pr oblems due t o spur ious signals
cr eat ed in t he mixer . However , t he spur char t is also t edious t o cr eat e; for n = m = 7,
a char t r equir es 112 measur ement s.
The compilat ion of r esult s is t he spur char t (also called a mixer t able). Det ails of
making t he spur char t measur ement s and r esult s ar e given in t he AD831 dat a sheet
(see Refer ence 17).
51
Mi xer Su mma r y
Mixer s ar e a special kind of analog mult iplier opt imized for use in fr equency
t r anslat ion, having one linear input (t hat associat ed wit h t he RF signal) and a
second (t hat associat ed wit h t he LO input ) which alt er nat es t he phase of t he fir st
input by 0/180. In int egr at ing complet e r eceiver s in monolit hic for m, cer t ain basic
cir cuit for ms have pr oven useful. So far , we have consider ed a classic for m, a six-
t r ansist or cir cuit exemplified by t he AD831. Compar ed t o a diode-r ing mixer , t his
cir cuit has sever al advant ages, including much bet t er isolat ion bet ween por t s, t he
abilit y t o pr ovide conver sion gain (which may also be var iable), t he need for much
lower LO dr ive levels, and t he eliminat ion of special mat ching net wor ks.
Oft en cit ed as a disadvant age of t he act ive mixer is it s poor er dynamic r ange: we
have just begun t o examine what defines t his, beginning wit h a consider at ion of t he
linear it y of t he RF por t , t r adit ionally char act er ized by t he 1dB gain-compr ession
input power , P
1dB
, and t he t hir d-or der int er cept , P
3OI
. The second of t hese measur es
was shown t o be meaningful only if t he nonlinear it y is essent ially cubic in for m,
which may not always be t r ue. In passing, we point ed out t hat while input s and
out put s ar e invar iably char act er ized in t er ms of a power level of so-many-dBm,
act ive mixer s r espond t o inst ant aneous signal volt ages at t heir input s, which ar e
usually not mat ched t o t heir sour ce, which can be confusing at t imes.
Now t hat we have examined each of t he fundament al r eceiver building blocks, we
ar e r eady t o look at r eceiver subsyst ems.
52
RECEI VER SUBSYSTEMS
Bob Cl a r k e, Wa l t Kest er
In or der t o design a communicat ions r eceiver , a clear under st anding of t he
modulat ion t echnique is essent ial. Ther e ar e many t ypes of modulat ion, r anging
fr om simple amplit ude modulat ion (AM), phase modulat ion (PM), and fr equency
modulat ion (FM) t o mult i-level quadr at ur e-amplit ude-modulat ion (QAM) wher e
bot h amplit ude and phase ar e modulat ed. Most moder n modulat ion schemes make
use of bot h signal amplit ude and phase infor mat ion. A complex signal can t hus be
r epr esent ed in t wo ways as shown in t he diagr ams in Figur e 3.52. The left -hand
diagr am r epr esent s t he signal in r ect angular coor dinat es as an inphase (I) and
quadr at ur e (Q) signal of t he for m:
S(t ) = I(t ) + jQ(t ).
The r ight hand diagr am r epr esent s t he same signal expr essed in polar coor dinat es:
S(t ) = A(t )e
j(t )
.
The conver sions bet ween t he t wo coor dinat e syst ems ar e:
S(t ) = A(t )e
j(t )
= I(t ) + jQ(t ), wher e
A(t ) = I t Q t ( ) ( )
2 2
+ ,
(t ) = ar ct an
Q t
I t
( )
( )

.
53
a
RECTANGULAR AND POLAR REPRESENTATIONS OF
AMPLITUDE AND PHASE MODULATED SIGNAL
3.52
RECTANGULAR POLAR
Q(t)
Q(t)
I(t) I(t)
S(t) = I(t) + jQ(t)
A(t)
j (t)
(t)
S(t) = A(t)e
Not e t hat t he signals ar e ident ical, only t heir r epr esent at ion is differ ent .
In t he case of t he I/Q (r ect angular ) r epr esent at ion, a linear IF st r ip is r equir ed.
Var iable gain is r equir ed because of t he wide dynamic r ange, and amplit ude and
phase infor mat ion must be pr eser ved. This t ype of IF st r ip oft en incor por at es an I/Q
demodulat or whose out put s dr ive baseband ADCs followed by a DSP. Linear IF
amplifier s ar e used in t hese syst ems.
For t he case of t he polar r epr esent at ion, t he signal amplit ude is der ived fr om t he
RSSI (log) out put of a log/limit ing amplifier and t he phase infor mat ion fr om t he
limit ed out put . This t ype of IF st r ip oper at es at a high fixed gain, r et ains t he phase
infor mat ion in t he limit ed out put , and oft en incor por at es a phase demodulat or .
In or der t o handle t hese t wo fundament al r epr esent at ions of modulat ion, ADI has
developed t wo IF subsyst ems, t he AD607 and t he AD608. These ar e used in such
applicat ions as PHS, PCN, DECT, CT2, and GSM wher e t he modulat ion mode is
some for m of phase-shift keying (PSK).
The chose of demodulat ion t echnique depends on t he r eceiver ar chit ect ur e. The
st andar d ar chit ect ur e in GSM and PHS uses a r ect angular r epr esent at ion of t he
signal, t hat is S(t ) = I(t ) + jQ(t ) and r equir es a linear IF amplifier st age such as t hat
in t he AD607. In t his ar chit ect ur e, a baseband conver t er consist ing of t wo signal
input s; each wit h individual low-pass filt er s, digit izes t he I(t ) and Q(t ) out put s of t he
IF IC's quadr at ur e demodulat or . Fur t her demodulat ion is per for med digit ally using
a DSP. An equalizer in t he DSP t hen det er mines t he cor r ect manual gain cont r ol
(MGC) volt age (or digit al signal) t o change t he IF gain t o cent er t he signal in t he
dynamic r ange of t he baseband ADCs. The equalizer calculat es t he RSSI value as
par t of t his pr ocess (see Figur e 3.53).
54
a
RECEIVER BASED ON AD607 SUBSYSTEM
USING INPHASE/QUADRATURE MODULATION
3.53
10.7MHz LO2
900MHz
LO1
240MHz
AD607
BPF OR
LPF
LPF
LPF
QVCO
BASEBAND
ADCs AND
DSP
90dB RANGE
0
90
MGC
I
Q
A det ailed block diagr am of t he AD607 Mixer /AGC/RSSI 3V r eceiver IF subsyst em is
shown in Figur e 3.54. The RF input fr equency can be as high as 500MHz, and t he
IF fr equency fr om 400kHz t o 12MHz. It consist s of a mixer , linear IF amplifier s, I
and Q demodulat or s, a phase-locked quadr at ur e oscillat or , AGC det ect or , and a
biasing syst em wit h ext er nal power -down. Tot al power on +3V is 25mW.
a
3.54
AD607 FUNCTIONAL BLOCK DIAGRAM
RFHI
RFLO
IFLO
BPF
LOIP
MXOP
MID-POINT
BIAS
GENERATOR
VMID
IFHI
BIAS
GENERATOR
VPS1
VPS2
PRUP
COM1 COM2
VMID
AGC
DETECTOR
PTAT
VOLTAGE
IFOP
BPF OR
LPF
DMIP
IOUT
FDIN
FLTR
QOUT
GAIN/RSSI
AD607
GREF
VQFO
55
The AD607's low noise, high int er cept mixer is a doubly-balanced Gilber t cell t ype.
It has a nominal 15dBm input -r efer r ed 1dB compr ession point and a 8dBm input -
r efer r ed t hir d-or der int er cept . The mixer sect ion also includes a local oscillat or
pr eamplifier , which lower s t he r equir ed ext er nal LO dr ive t o 16dBm.
The var iable-gain mixer and t he linear four -st age IF amplifier st r ip t oget her pr ovide
a volt age cont r olled gain r ange of mor e t han 90dB. The I and Q demodulat or s, each
consist ing of a mult iplier followed by a 2-pole, 2MHz low-pass filt er , ar e dr iven by a
phase-locked loop pr oviding inphase and quadr at ur e clocks. An int er nal AGC
det ect or is included, and t he t emper at ur e st able gain cont r ol syst em pr ovides an
accur at e RSSI capabilit y.
The I and Q demodulat or s pr ovide inphase and quadr at ur e baseband out put s t o
int er face wit h Analog Devices' AD7013 (IS54/IS136, TETRA, MSAT) and AD7015
(GSM) baseband conver t er s.
Key specificat ions for t he AD607 ar e summar ized in Figur e 3.55.
AD607 MIXER / AGC / RSSI 3V RECEIVER KEY FEATURES
n n Mixer:
u u 15dBm Input 1dB Compression Point
u u 8dBm Input Third Order Intercept Point
u u RF/LO Inputs to 500MHz
u u 12dB Noise Figure, Matched Input
u u 16dBm LO Drive
n n Linear IF Amplifier:
u u 45MHz Bandwidth
u u Linear-in-dB Gain Control Over 90dB Gain Range
u u 15dBm Input 1dB Compression Point
u u +18dBm Output Third Order Intercept Point
n n In-Phase and Quadrature Demodulators:
u u 1.5MHz Output Bandwidth
u u Compatible with Baseband Converters (AD7013, AD7015)
n n 25mW Total Power @ Single +3V Supply
a 3.55
For cases wher e t he signal is r epr esent ed in polar for m, t he AD608 is t he pr oper
choice. The AD608 Mixer /Limit er /RSSI 3V Receiver IF Subsyst em consist s of a
mixer followed by a logar it hmic amplifier ; t he logar it hmic amplifier has bot h limit ed
out put (phase infor mat ion) and an RSSI out put (amplit ude infor mat ion). This
ar chit ect ur e is useful in polar demodulat ion applicat ions as shown in Figur e 3.56.
A block diagr am of t he AD608 is shown in Figur e 3.57, and key specificat ions in
Figur e 3.58.
56
RECEIVER BASED ON AD608 SUBSYSTEM
USING POLAR DEMODULATION
3.56
DETECTORS
LIMITING
AMPLIFIERS
80dB RANGE
10.7MHz LO2
900MHz
LO1
240MHz
AD608
RSSI
DEMOD
AND
DSP
LPF
PHASE
a
3.57
AD608 FUNCTIONAL BLOCK DIAGRAM
24dB MIXER GAIN 100dB LIMITER GAIN
90dB RSSI
BIAS
MXOP
MIXER
BPF
DRIVER
VMID LO
PREAMP
AD608
RFHI
RFLO
IF INPUT
-75dBm TO
+15dBm2
IFHI
IFLO
LMOP
VPS2
RSSI
FDBK
COM3
FINAL
LIMITER
100nF
10nF
330
50A
330
MID-SUPPLY
IF BIAS
5
7
8 10
9
13
14
12
11
2 4 16
LIMITER
OUTPUT
400mVp-p
PRUP
RF INPUT
-95 TO
-15dBm1
VPS1 COM1 COM2
LOHI
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
3dB NOMINAL
INSERTION LOSS
+2.7V TO 5.5V
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
7 FULL-WAVE
RECTIFIER CELLS
+2.7V TO
5.5V
LO INPUT
-16dBm
CMOS LOGIC
INPUT
6mA MAX OUTPUT
(890mV INTO 165 )
100
18nF
1
-15dBm= 56mV MAX FORLINEAROPERATION
2MHz
LPF
15
1 3
6
2 39.76V RMS TO 397.6mV RMS FOR 1dB RSSI ACCURACY
NOTES:
10.7MHz
BANDPASS
FILTER

AD608 MIXER / LIMITER / RSSI 3V RECEIVER KEY FEATURES


n n Mixer:
u u 15dBm Input 1dB Compression Point
57
u u 5dBm Input Third Order Intercept Point
u u RF/LO Inputs to 500MHz
u u 12dB Noise Figure, Matched Input
u u 16dBm LO Drive
n n Logarithmic Amplifier / Limiter:
u u 100dB Limiter Gain, 90dB RSSI
u u 1dB Log Linearity
u u 3Phase Variation, 75dBm to +5dBm IF @ 10.7MHz
n n 21mW Total Power @ Single +3V Supply
a 3.58
The log amp bot h measur es t he level of t he signal (like t he AD641 and AD606) and
limit s t he signal. The RSSI or Received Signal St r engt h Indicat or out put is
pr opor t ional t o t he log of t he input signal. As a limit ing amplifier , t he AD608
r emoves any amplit ude changes in t he signal and keeps only t he phase or fr equency
changes. These phase or fr equency changes ar e pr opor t ional t o t he modulat ing
signal and cont ain t he int elligence in t he signal. The AD608's limit ing amplifier is a
5-st age log amp wit h mor e t han 80dB of dynamic r ange.
In a t ypical mobile phone applicat ion, t he RF signal (t ypically 900MHz or 1800MHz)
is mixed down t o t he fir st IF (t ypically 240MHz), is filt er ed, and ent er s t he AD608,
wher e it is mixed down t o a second IF at 10.7MHz, wher e it is amplified, limit ed,
and measur ed. The limit ed out put is demodulat ed by an ext er nal fr equency or phase
demodulat or . The RSSI out put is digit ized by an ADC and used for act ive power
cont r ol in t he phone syst em.
As a pr act ical not e, t he cut off fr equency of t he log amp's int er nal low pass filt er
depends on what r ange of fr equencies t he log amp was designed for . In analog
cellular syst ems, wher e t he modulat ion mode is nar r ow-band FM, t he IF is t ypically
450kHz. The low pass filt er s in t he IF ICs designed for t hese st andar ds have a fair ly
low cut off fr equency, and t he filt er 's volt age out put r esponse pr ovides a "slow" RSSI.
In GSM (Global Syst em for Mobile Communicat ions) and PHS (Per sonal Handy
Syst em) applicat ions, t he IF is t ypically 10.7MHz or higher , and t he filt er 's volt age
out put r esponse pr ovides a "fast " RSSI. The cut off fr equency of t he low pass filt er in
t he AD608 is 2MHz.
58
REF ERENCES
1. Bar r ie Gilber t , I SSCC Di gest of Tech n i ca l P a p er s 1968, pp. 114-115
Febr uar y 16, 1968.
2. Bar r ie Gilber t , J ou r n a l of Soli d St a t e Ci r cu i t s, Vol. SC-3, December 1968,
pp. 353-372.
3. C.L. Rut hr off, S ome Broadband Transformers, P r oc. I .R.E., Vol.47,
August , 1959, pp.1337-1342.
4. J ames M. Br yant , Mixers for High Performance Radio, Wescon 1981:
Sessi on 24 (Published by Elect r onic Convent ions, Inc., Sepulveda Blvd.,
El Segundo, CA)
5. P.E. Chadwick, High Performance IC Mixers, I ERE Con fer en ce on Ra d i o
Recei ver s a n d Associ a t ed Syst ems, Leeds, 1981, IERE Confer ence
Publicat ion No. 50.
6. P.E. Chadwick, Phase Noise, Intermodulation, and Dynamic Range,
RF Exp o, Anaheim, CA, J anuar y, 1986.
7. Daniel H. Sheingold, Edit or , Non li n ea r Ci r cu i t s Ha n d b ook , Analog
Devices, Inc., l974.
8. Richar d Smit h Hughes, Loga r i t h mi c Amp li fi er s, Ar t ech House, Inc.,
Dedham, MA., 1986.
9. William L. Bar ber and Edmund R. Br own, A True Logarithmic Amplifier for
Radar IF Applications, I EEE J ou r n a l of Soli d St a t e Ci r cu i t s, Vol. SC-15,
No. 3, J une, 1980, pp. 291-295.
10. Br oa d ba n d Amp li fi er Ap p li ca t i on s, Plessey Co. Publicat ion P.S. 1938,
Sept ember , 1984.
11. M. S. Gay, SL521 Ap p li ca t i on Not e, Plessey Co., 1966.
12. Amp li fi er Ap p li ca t i on s Gu i d e, Analog Devices, Inc., 1992. Sect ion 9.
13. Char les Kit chen and Lew Count s, RMS-t o-DC Con ver si on Ap p li ca t i on
Gu i d e, Secon d Ed i t i on , Analog Devices, Inc., 1986.
14. Bar r ie Gilber t , A Low Noise Wideband Variable-Gain Amplifier Using
an Interpolated Ladder Attenuator, I EEE I SSCC Tech n i ca l Di gest , 1991,
pp. 280, 281, 330.
15. Bar r ie Gilber t , A Monolithic Microsystem for Analog S ynthesis of
Trigonometric Functions and their Inverses, I EEE J ou r n a l of Soli d
St a t e Ci r cu i t s, Vol. SC-17, No. 6, December , 1982, pp. 1179-1191.
16. Li n ea r Desi gn Semi n a r , Analog Devices, 1995, Sect ion 3.
59
17. AD831 Da t a Sh eet , Rev. B, Analog Devices.
1
SECTI ON 4
HI GH SP EED SAMP LI NG AND
HI GH SP EED ADCs, Wa l t Kest er
I NTRODUCTI ON
High speed ADCs ar e used in a wide var iet y of r eal-t ime DSP signal-pr ocessing
applicat ions, r eplacing syst ems t hat used analog t echniques alone. The major r eason
for using digit al signal pr ocessing ar e (1) t he cost of DSP pr ocessor s has gone down,
(2) t heir speed and comput at ional power has incr eased, and (3) t hey ar e
r epr ogr ammable, t her eby allowing for syst em per for mance upgr ades wit hout
har dwar e changes. DSP offer s solut ions t hat cannot be achieved in t he analog
domain, i.e. V.32 and V.34 modems.
However , in or der for digit al signal pr ocessing t echniques t o be effect ive in solving
an analog signal pr ocessing pr oblem, appr opr iat e cost effect ive high speed ADCs
must be available. The ADCs must be t est ed and specified in such a way t hat t he
design engineer can r elat e t he ADC per for mance t o specific syst em r equir ement s,
which can be mor e demanding t han if t hey wer e used in pur ely analog signal
pr ocessing syst ems. In most high speed signal pr ocessing applicat ions, AC
per for mance and wide dynamic r ange ar e much mor e impor t ant t han t r adit ional DC
per for mance. This r equir es t hat t he ADC manufact ur er not only design t he r ight
ADCs but specify t hem as complet ely as possible t o cover a wide var iet y of
applicat ions.
Anot her impor t ant aspect of int egr at ing ADCs int o a high speed syst em is a
complet e under st anding of t he sampling pr ocess and t he dist or t ion mechanisms
which ult imat ely limit syst em per for mance. High speed sampling ADCs fir st wer e
used in inst r ument at ion and signal pr ocessing applicat ions, wher e much emphasis
was placed on t ime-domain per for mance. While t his is st ill impor t ant , applicat ions
of ADCs in communicat ions also r equir e compr ehensive fr equency-domain
specificat ions.
Moder n IC pr ocesses also allow t he int egr at ion of mor e analog funct ionalit y int o t he
ADC, such as on-boar d r efer ences, sample-and-hold amplifier s, PGAs, et c. This
makes t hem easier t o use in a syst em by minimizing t he amount of suppor t cir cuit r y
r equir ed.
Anot her dr iving for ce in high speed ADC development is t he t r end t owar d lower
power and lower supply volt ages. Most high speed sampling ADCs t oday oper at e on
eit her dual or single 5V supplies, and t her e is incr easing int er est in single-supply
conver t er s which will oper at e on 3V or less for bat t er y power ed applicat ions. Lower
supply volt ages t end t o incr ease a cir cuit 's sensit ivit y t o power supply noise and
gr ound noise, especially mixed-signal devices such as ADCs and DACs.
The t r end t owar d lower cost and lower power has led t o t he development of a var iet y
of high speed ADCs fabr icat ed on st andar d 0.6 micr on CMOS pr ocesses. Making a
pr ecision ADC on a digit al pr ocess (no t hin film r esist or s ar e available) is a r eal
challenge t o t he IC cir cuit designer . ADCs which r equir e t he maximum in
2
per for mance st ill r equir e a high speed complement ar y bipolar pr ocess (such as
Analog Devices' XFCB) wit h t hin film r esist or s.
The pur pose of t his sect ion is t o equip t he engineer wit h t he pr oper t ools necessar y
t o under st and and select ADCs for high speed syst ems applicat ions. Making
int elligent t r adeoffs in t he syst em design r equir es a t hor ough under st anding of t he
fundament al capabilit ies and limit at ions of st at e-of-t he-ar t high speed sampling
ADCs.
HIGH SPEED SAMPLING ADCs
n n Wide Acceptance in Signal Processing and Communications
n n Emphasis on Dynamic Performance
n n Trend to Low Power, Low Voltage, Single-Supply
n n More On-Chip Functionality: PGAs, SHA, Digital Filters, etc.
n n Process Technology:
u u Low Cost CMOS: Up to 12-bits @ 10MSPS
u u High Speed Complementary Bipolar: Up to 12-bits @ 70MSPS
u u Statistical Matching Techniques Rather than Thin Film
Laser Trimming
a 4.1
FUNDAMENTALS OF HI GH SP EED SAMP LI NG
The sampling pr ocess can be discussed fr om eit her t he fr equency or t ime domain or
bot h. Fr equency-domain analysis is applicable t o communicat ions, so t hat 's what we
will consider .
Fir st consider t he case of a single fr equency sinewave of fr equency f
a
sampled at a
fr equency f
s
by an ideal impulse sampler (see t op diagr am in Figur e 4.2). Also
assume t hat f
s
> 2f
a
as shown. The fr equency-domain out put of t he sampler shows
aliases or images of t he or iginal signal ar ound ever y mult iple of f
s
, i.e. at fr equencies
equal t o
| Kf
s
f
a
| , K = 1, 2, 3, 4, .....
3
a
ANALOG SIGNAL f
a
SAMPLED @ f
s
USING IDEAL SAMPLER
HAS IMAGES (ALIASES) AT |Kf
s
f
a
|, K = 1, 2, 3, . . .
4.2
0.5f
s
0.5f
s
f
s
f
s
1.5f
s
1.5f
s
2f
s
2f
s
ZONE 1 ZONE 2 ZONE 3 ZONE 4
f
a I
I I
I I I I
I
f
a
The Nyquist bandwidt h is defined t o be t he fr equency spect r um fr om DC t o f
s
/2. The
fr equency spect r um is divided int o an infinit e number of Nyquist zones, each having
a widt h equal t o 0.5f
s
as shown. In pr act ice, t he ideal sampler is r eplaced by an
ADC followed by an FFT pr ocessor . The FFT pr ocessor only pr ovides an out put fr om
DC t o f
s
/2, i.e., t he signals or aliases which appear in t he fir st Nyquist zone.
Now consider t he case of a signal which is out side t he fir st Nyquist zone (Figur e 4.2,
bot t om diagr am) Not ice t hat even t hough t he signal is out side t he fir st Nyquist
zone, it s image (or alias), f
s
f
a
, falls inside. Ret ur ning t o Figur e 4.2, t op diagr am, it
is clear t hat if an unwant ed signal appear s at any of t he image fr equencies of f
a
, it
will also occur at f
a
, t her eby pr oducing a spur ious fr equency component in t he fir st
Nyquist zone. This is similar t o t he analog mixing pr ocess and implies t hat some
filt er ing ahead of t he sampler (or ADC) is r equir ed t o r emove fr equency component s
which ar e out side t he Nyquist bandwidt h, but whose aliased component s fall inside
it . The filt er per for mance will depend on how close t he out -of-band signal is t o f
s
/2
and t he amount of at t enuat ion r equir ed.
BASEBAND ANTI ALI ASI NG FI LTERS
Baseband sampling implies t hat t he signal t o be sampled lies in t he fir st Nyquist
zone. It is impor t ant t o not e t hat wit h no input filt er ing at t he input of t he ideal
sampler , any frequency component (either signal or noise) that falls outside the
Nyquist bandwidth in any Nyquist zone will be aliased back into the first Nyquist
zone. For t his r eason, an ant ialiasing filt er is used in almost all sampling ADC
applicat ions t o r emove t hese unwant ed signals.
4
Pr oper ly specifying t he ant ialiasing filt er is impor t ant . The fir st st ep is t o know t he
char act er ist ics of t he signal being sampled. Assume t hat t he highest fr equency of
int er est is f
a
. The ant ialiasing filt er passes signals fr om DC t o f
a
while at t enuat ing
signals above f
a
.
Assume t hat t he cor ner fr equency of t he filt er is chosen t o be equal t o f
a
. The effect
of t he finit e t r ansit ion fr om minimum t o maximum at t enuat ion on syst em dynamic
r ange is illust r at ed in Figur e 4.3.
a
EFFECTS OF ANTIALIASING FILTER
ON SYSTEM DYNAMIC RANGE
4.3
f
a
STOPBAND ATTENUATION = DR
TRANSITION BAND: f
a
TO f
s
- f
a
CORNER FREQUENCY: f
a
f
s f
f
s
- f
a
f
s
2
f
s
- f
a
f
a
DR
FILTER
SPECIFICATIONS
Assume t hat t he input signal has fullscale component s well above t he maximum
fr equency of int er est , f
a
. The diagr am shows how fullscale fr equency component s
above f
s
f
a
ar e aliased back int o t he bandwidt h DC t o f
a
. These aliased
component s ar e indist inguishable fr om act ual signals and t her efor e limit t he
dynamic r ange t o t he value on t he diagr am which is shown as DR.
Some t ext s r ecommend specifying t he ant ialiasing filt er wit h r espect t o t he Nyquist
fr equency, f
s
/2, but t his assumes t hat t he signal bandwidt h of int er est ext ends fr om
DC t o f
s
/2 which is r ar ely t he case. In t he example shown in Figur e 4.3, t he aliased
component s bet ween f
a
and f
s
/2 ar e not of int er est and do not limit t he dynamic
r ange.
The ant ialiasing filt er t r ansit ion band is t her efor e det er mined by t he cor ner
fr equency f
a
, t he st opband fr equency f
s
f
a
, and t he st opband at t enuat ion, DR. The
r equir ed syst em dynamic r ange is chosen based on our r equir ement for signal
fidelit y.
5
Filt er s have t o become mor e complex as t he t r ansit ion band becomes shar per , all
ot her t hings being equal. For inst ance, a But t er wor t h filt er gives 6dB at t enuat ion
per oct ave for each filt er pole. Achieving 60dB at t enuat ion in a t r ansit ion r egion
bet ween 1MHz and 2MHz (1 oct ave) r equir es a minimum of 10 poles, not a t r ivial
filt er , and definit ely a design challenge.
Ther efor e, ot her filt er t ypes ar e gener ally mor e suit ed t o high speed applicat ions
wher e t he r equir ement is for a shar p t r ansit ion band and in-band flat ness coupled
wit h linear phase r esponse. Ellipt ic filt er s meet t hese cr it er ia and ar e a popular
choice.
Ther e ar e a number of companies which specialize in supplying cust om analog
filt er s. TTE is an example of such a company (Refer ence 1). As an example, t he
nor malized r esponse of t he TTE, Inc., LE1182 11-pole ellipt ic ant ialiasing filt er is
shown in Figur e 4.4. Not ice t hat t his filt er is specified t o achieve at least 80dB
at t enuat ion bet ween f
c
and 1.2f
c
. The cor r esponding passband r ipple, r et ur n loss,
delay, and phase r esponse ar e also shown in Figur e 4.4. This cust om filt er is
available in cor ner fr equencies up t o 100MHz and in a choice of PC boar d, BNC, or
SMA wit h compat ible packages.
a
CHARACTERISTICS OF TTE, INC., LE1182-SERIES
11-POLE ELLIPTICAL FILTER
4.4
Reprinted with Permission of
TTE, Inc., 2251 Barry Ave., Los Angeles, CA 90064
0
10
20
30
40
50
60
70
80
90
100
.893 933 .972 1.01 1.052 1.092 1.131 1.171 1.211 1.250 1.29
LE1182
Normalized Response Normalized Passband: Amplitude & Return Loss
Normalized Delay & Variation from Linear O
Ultimate guaranteed stopband
- refer to page 3-1
F/Fc Transition Ratio
LE1182
LE1182
.005 .105 .205 .304 .404 .504 .604 .704 .803 .903 1.003
0
5
10
15
20
25
30
F/Fc Transition Ratio
F/Fc Transition Ratio
0
0.5
1.0
1.5
2.0
2.5
3.0
12.6S
6.6S
.6S
1
.
2
S
/
D
iv
.
(
P
le
a
s
e

r
e
f
e
r

t
o

p
a
g
e

3
-
3
)
.005 .105 .205 .304 .404 .504 .604 .704 .803 .903 1.003
0
o
175
o
350
o
O
R
e
l
a
t
i
v
e

A
t
t
e
n
u
a
t
i
o
n

,

(
d
B
)
P
a
s
s
b
a
n
d

A
t
t
n
.
,

(
d
B
)
R
e
t
u
r
n

L
o
s
s
,

(
d
B
)
3
5
o
/
D
iv
.
Fr om t his discussion, we can see how t he shar pness of t he ant ialiasing t r ansit ion
band can be t r aded off against t he ADC sampling fr equency. Choosing a higher
sampling r at e (over sampling) r educes t he r equir ement on t r ansit ion band shar pness
(hence, t he filt er complexit y) at t he expense of using a fast er ADC and pr ocessing
dat a at a fast er r at e. This is illust r at ed in Figur e 4.5 which shows t he effect s of
6
incr easing t he sampling fr equency while maint aining t he same analog cor ner
fr equency, f
a
,and t he same dynamic r ange, DR, r equir ement .
a 4.5
INCREASING SAMPLING FREQUENCY RELAXES
REQUIREMENT ON ANTIALIASING FILTER
f
s
B
A
DR
0.5f
s
0.5f
s
f
s
f
a f
s
- f
a
f
s
- f
a
f
a
LOWPASS FILTER SPECIFICATIONS:
The above design pr ocess is st ar t ed by choosing an init ial sampling r at e of 2 t o 4
t imes f
a
. Det er mine t he filt er specificat ions based on t he r equir ed dynamic r ange
and see if such a filt er is r ealizable wit hin t he const r aint s of t he syst em cost and
per for mance. If not , consider a higher sampling r at e which may r equir e using a
fast er ADC.
The ant ialiasing filt er r equir ement s can be r elaxed somewhat if it is cer t ain t hat
t her e will never be a fullscale signal at t he st opband fr equency f
s
f
a
. In many
applicat ions, it is impr obable t hat fullscale signals will occur at t his fr equency. If t he
maximum signal at t he fr equency f
s
f
a
will never exceed XdB below fullscale.
Then, t he filt er st opband at t enuat ion r equir ement is r educed by t hat same amount .
The new r equir ement for st opband at t enuat ion at f
s
f
a
based on t his knowledge of
t he signal is now only DR XdB. When making t his t ype of assumpt ion, be car eful
t o t r eat any noise signals which may occur above t he maximum signal fr equency f
a
as unwant ed signals which will also alias back int o t he signal bandwidt h.
UNDERSAMP LI NG (HARMONI C SAMP LI NG, BANDP ASS
SAMP LI NG, I F SAMP LI NG, DI RECT I F TO DI GI TAL
CONVERSI ON)
Thus far we have consider ed t he case of baseband sampling, i.e., all t he signals of
int er est lie wit hin t he fir st Nyquist zone. Figur e 4.6A shows such a case, wher e t he
band of sampled signals is limit ed t o t he fir st Nyquist zone, and images of t he
or iginal band of fr equencies appear in each of t he ot her Nyquist zones.
7
Consider t he case shown in Figur e 4.6B, wher e t he sampled signal band lies ent ir ely
wit hin t he second Nyquist zone. The pr ocess of sampling a signal out side t he fir st
Nyquist zone is oft en r efer r ed t o as undersampling, or harmonic sampling. Not e t hat
t he fir st Nyquist zone image cont ains all t he infor mat ion in t he or iginal signal, wit h
t he except ion of it s or iginal locat ion (t he or der of t he fr equency component s wit hin
t he spect r um is r ever sed, but t his is easily cor r ect ed by r e-or der ing t he out put of t he
FFT).
a
UNDERSAMPLING
4.6
A
B
C
ZONE 1
ZONE 2
ZONE 3
I
I
0.5f
s
0.5f
s
0.5f
s
f
s
f
s
f
s
1.5f
s
1.5f
s
1.5f
s
2f
s
2f
s
2f
s
2.5f
s
2.5f
s
2.5f
s
3f
s
3f
s
3f
s
3.5f
s
3.5f
s
3.5f
s
Figur e 4.6C shows t he sampled signal r est r ict ed t o t he t hir d Nyquist zone. Not e t hat
t he fir st Nyquist zone image has no fr equency r ever sal. In fact , t he sampled signal
fr equencies may lie in any unique Nyquist zone, and t he fir st Nyquist zone image is
st ill an accur at e r epr esent at ion (wit h t he except ion of t he fr equency r ever sal which
occur s when t he signals ar e locat ed in even Nyquist zones). At t his point we can
clear ly st at e t he Nyquist cr it er ia:
A signal must be sampled at a rate equal to or greater than twice its ba n d wi d t h in
order to preserve all the signal information.
Not ice t hat t her e is no ment ion of t he absolut e location of t he band of sampled
signals wit hin t he fr equency spect r um r elat ive t o t he sampling fr equency. The only
const r aint is t hat t he band of sampled signals be r est r ict ed t o a single Nyquist zone,
i.e., t he signals must not over lap any mult iple of f
s
/2 (t his, in fact , is t he pr imar y
funct ion of t he ant ialiasing filt er ).
Sampling signals above t he fir st Nyquist zone has become popular in
communicat ions because t he pr ocess is equivalent t o analog demodulat ion. It is
becoming common pr act ice t o sample IF signals dir ect ly and t hen use digit al
t echniques t o pr ocess t he signal, t her eby eliminat ing t he need for t he IF
8
demodulat or . Clear ly, however , as t he IF fr equencies become higher , t he dynamic
per for mance r equir ement s on t he ADC become mor e cr it ical. The ADC input
bandwidt h and dist or t ion per for mance must be adequat e at t he IF fr equency, r at her
t han only baseband. This pr esent s a pr oblem for most ADCs designed t o pr ocess
signals in t he fir st Nyquist zone, t her efor e an ADC suit able for under sampling
applicat ions must maint ain dynamic per for mance int o t he higher or der Nyquist
zones.
ANTI ALI ASI NG FI LTERS I N UNDERSAMP LI NG
AP P LI CATI ONS
Figur e 4.7 shows a signal in t he second Nyquist zone cent er ed ar ound a car r ier
fr equency, f
c
, whose lower and upper fr equencies ar e f
1
and f
2
. The ant ialiasing
filt er is a bandpass filt er . The desir ed dynamic r ange is DR, which defines t he filt er
st opband at t enuat ion. The upper t r ansit ion band is f
2
t o 2f
s
f
2
, and t he lower is f
1
t o f
s
f
1
. As in t he case of baseband sampling, t he ant ialiasing filt er r equir ement s
can be r elaxed by pr opor t ionally incr easing t he sampling fr equency, but f
c
must also
be incr eased so t hat it is always cent er ed in t he second Nyquist zone.
a
4.7
ANTIALIASING FILTER FOR UNDERSAMPLING
DR
0.5f
S
f
S
f
s
- f
1
BANDPASS FILTER SPECIFICATIONS:
STOPBAND ATTENUATION = DR
TRANSITION BAND: f
2
TO 2f
s
- f
2
CORNER FREQUENCIES: f
1
, f
2
f
1 f
2
2f
s
- f
2
1.5f
S
2f
S
0
IMAGE
SIGNALS
OF
INTEREST
IMAGE
IMAGE
f
c
f
1
TO f
s
- f
1
Two key equat ions can be used t o select t he sampling fr equency, f
s
, given t he car r ier
fr equency, f
c
, and t he bandwidt h of it s signal, f. The fir st is t he Nyquist cr it er ia:
f
s
> 2f Eq. 1
The second equat ion ensur es t hat f
c
is placed in t he cent er of a Nyquist zone:
f
s
f
c
NZ
=

4
2 1
, Eq. 2
9
wher e NZ = 1, 2, 3, 4, .... and NZ cor r esponds t o t he Nyquist zone in which t he
car r ier and it s signal fall (see Figur e 4.8).
NZ is nor mally chosen t o be as lar ge as possible while st ill maint aining f
s
> 2f. This
r esult s in t he minimum r equir ed sampling r at e. If NZ is chosen t o be odd, t hen f
c
and it 's signal will fall in an odd Nyquist zone, and t he image fr equencies in t he fir st
Nyquist zone will not be r ever sed. Tr adeoffs can be made bet ween t he sampling
fr equency and t he complexit y of t he ant ialiasing filt er by choosing smaller values of
NZ (hence a higher sampling fr equency).
a 4.8
CENTERING AN UNDERSAMPLED SIGNAL
WITHIN A NYQUIST ZONE
0.5f
s
0.5f
s
0.5f
s
I I
f
ZONE NZ - 1 ZONE NZ ZONE NZ + 1
f
c
f
s
> 2 f
f
s
= , NZ = 1, 2, 3, . . .
4f
c
2NZ - 1
As an example, consider a 4MHz wide signal cent er ed ar ound a car r ier fr equency of
71MHz. The minimum r equir ed sampling fr equency is t her efor e 8MSPS. Solving Eq.
2 for NZ using f
c
= 71MHz and f
s
= 8MSPS yields NZ = 18.25. However , NZ must be
an int eger , so we r ound 18.25 t o t he next lowest int eger , 18. Solving Eq. 2 again for
f
s
yields f
s
= 8.1143MSPS. The final values ar e t her efor e f
s
= 8.1143MSPS, f
c
=
71MHz, and NZ = 18.
Now assume t hat we desir e mor e mar gin for t he ant ialiasing filt er , and we select f
s
t o be 10MSPS. Solving Eq. 2 for NZ, using f
c
= 71MHz and f
s
= 10MSPS yields NZ =
14.7. We r ound 14.7 t o t he next lowest int eger , giving NZ = 14. Solving Eq. 2 again
for f
s
yields f
s
= 10.519MSPS. The final values ar e t her efor e f
s
= 10.519MSPS, f
c
=
71MHz, and NZ = 14.
The above it er at ive pr ocess can also be car r ied out st ar t ing wit h f
s
and adjust ing t he
car r ier fr equency t o yield an int eger number for NZ.
DI STORTI ON AND NOI SE I N AN I DEAL N-BI T ADC
10
Thus far we have looked at t he implicat ions of t he sampling pr ocess wit hout
consider ing t he effect s of ADC quant izat ion. We will now t r eat t he ADC as an ideal
sampler , but include t he effect s of quant izat ion.
The only er r or s (DC or AC) associat ed wit h an ideal N-bit ADC ar e t hose r elat ed t o
t he sampling and quant izat ion pr ocesses. The maximum er r or an ideal ADC makes
digit izing a DC input signal is 1/2LSB. Any AC signal applied t o an ideal N-bit
ADC will pr oduce quant izat ion noise whose r ms value (measur ed over t he Nyquist
bandwidt h, DC t o f
s
/2) is appr oximat ely equal t o t he weight of t he least significant
bit (LSB), q, divided by 12. (See Refer ence 2). This assumes t hat t he signal is at
least a few LSBs in amplit ude so t hat t he ADC out put always changes st at e. The
quant izat ion er r or signal fr om a linear r amp input is appr oximat ed as a sawt oot h
wavefor m wit h a peak-t o-peak amplit ude equal t o q, and it s r ms value is t her efor e
q/12 (see Figur e 4.9).
SNR = 6.02N + 1.76dB + 10log FOR FS SINEWAVE
f
s
2BW
a
4.9
IDEAL N-BIT ADC QUANTIZATION NOISE
DIGITAL
CODE
OUTPUT
RMS ERROR = q/ 12
ANALOG
INPUT
ERROR
q = 1LSB
It can be shown t hat t he r at io of t he r ms value of a full scale sinewave t o t he r ms
value of t he quant izat ion noise (expr essed in dB) is:
SNR = 6.02N + 1.76dB,
wher e N is t he number of bit s in t he ideal ADC. This equation is only valid if the
noise is measured over the entire Nyquist bandwidth from DC to f
s
/ 2. If t he signal
bandwidt h, BW, is less t han f
s
/2, t hen t he SNR wit hin t he signal bandwidt h BW is
incr eased because t he amount of quant izat ion noise wit hin t he signal bandwidt h is
smaller . The cor r ect expr ession for t his condit ion is given by:
SNR N dB
f
s
BW
= + +

6 02 1 76 10
2
. . log .
11
The above equat ion r eflect s t he condit ion called oversampling, wher e t he sampling
fr equency is higher t han t wice t he signal bandwidt h. The cor r ect ion t er m is oft en
called processing gain. Not ice t hat for a given signal bandwidt h, doubling t he
sampling fr equency incr eases t he SNR by 3dB.
Alt hough t he r ms value of t he noise is accur at ely appr oximat ed q/12, it s fr equency
domain cont ent may be highly cor r elat ed t o t he AC input signal. For inst ance, t her e
is gr eat er cor r elat ion for low amplit ude per iodic signals t han for lar ge amplit ude
r andom signals. Quit e oft en, t he assumpt ion is made t hat t he t heor et ical
quant izat ion noise appear s as whit e noise, spr ead unifor mly over t he Nyquist
bandwidt h DC t o f
s
/2. Unfor t unat ely, t his is not t r ue. In t he case of st r ong
cor r elat ion, t he quant izat ion noise appear s concent r at ed at t he var ious har monics of
t he input signal, just wher e you don't want t hem.
In most applicat ions, t he input t o t he ADC is a band of fr equencies (usually summed
wit h some noise), so t he quant izat ion noise t ends t o be r andom. In spect r al analysis
applicat ions (or in per for ming FFTs on ADCs using spect r ally pur e sinewaves - see
Figur e 4.10), however , t he cor r elat ion bet ween t he quant izat ion noise and t he signal
depends upon t he r at io of t he sampling fr equency t o t he input signal. This is
demonst r at ed in Figur e 4.11, wher e an ideal 12-bit ADCs out put is analyzed using a
4096-point FFT. In t he left -hand FFT plot , t he r at io of t he sampling fr equency t o
t he input fr equency was chosen t o be exact ly 32, and t he wor st har monic is about
76dB below t he fundament al. The r ight hand diagr am shows t he effect s of slight ly
offset t ing t he r at io, showing a r elat ively r andom noise spect r um, wher e t he SFDR is
now about 92dBc. In bot h cases, t he r ms value of all t he noise component s is q/12,
but in t he fir st case, t he noise is concent r at ed at har monics of t he fundament al.
4.10
DYNAMIC PERFORMANCE ANALYSIS
OF AN IDEAL N-BIT ADC
a
ANALOG
INPUT
f
a
f
s
N
M
2
POINT
SPECTRAL
OUTPUT
IDEAL
N-BIT
ADC
BUFFER
MEMORY
M-WORDS
M-POINT
FFT
PROCESSOR
12
4.11
EFFECT OF RATIO OF SAMPLING CLOCK TO INPUT
FREQUENCY ON SFDR FOR IDEAL 12-BIT ADC
a
f
s
/ f
a
= 32
0 500 1000 1500 2000
0 500 1000 1500 2000
M = 4096
f
s
/ f
a
= 32.25196850394
SFDR = 76dBc
SFDR = 92dBc
Not e t hat t his var iat ion in t he appar ent har monic dist or t ion of t he ADC is an
ar t ifact of t he sampling pr ocess and t he cor r elat ion of t he quant izat ion er r or wit h
t he input fr equency. In a pr act ical ADC applicat ion, t he quant izat ion er r or gener ally
appear s as r andom noise because of t he r andom nat ur e of t he wideband input signal
and t he addit ional fact t hat t her e is a usually a small amount of syst em noise which
act s as a dither signal t o fur t her r andomize t he quant izat ion er r or spect r um. (For
fur t her discussions on dit her , see Sect ion 5 of t his book).
It is impor t ant t o under st and t he above point , because single-t one sinewave FFT
t est ing of ADCs is a univer sally accept ed met hod of per for mance evaluat ion. In
or der t o accur at ely measur e t he har monic dist or t ion of an ADC, st eps must be t aken
t o ensur e t hat t he t est set up t r uly measur es t he ADC dist or t ion, not t he ar t ifact s
due t o quant izat ion noise cor r elat ion. This is done by pr oper ly choosing t he
fr equency r at io and somet imes by inject ing a small amount of noise (dit her ) wit h t he
input signal.
Now, r et ur n t o Figur e 4.11, and not e t hat t he aver age value of t he noise floor of t he
FFT is gr eat er t han 100dB below full scale, but t he t heor et ical SNR of a 12-bit ADC
is 74dB. The FFT noise floor is not t he SNR of t he ADC, because t he FFT act s like
an analog spect r um analyzer wit h a bandwidt h of f
s
/M, wher e M is t he number of
point s in t he FFT, r at her t han f
s
/2. The t heor et ical FFT noise floor is t her efor e
10log
10
(M/2)dB below t he quant izat ion noise floor due t o t he so-called processing
gain of t he FFT (see Figur e 4.12). In t he case of an ideal 12-bit ADC wit h an SNR of
74dB, a 4096-point FFT would r esult in a pr ocessing gain of 10log
10
(4096/2) =
33dB, t her eby r esult ing in an over all FFT noise floor of 74+33=107dBc. In fact , t he
FFT noise floor can be r educed even fur t her by going t o lar ger and lar ger FFTs; just
as an analog spect r um analyzer 's noise floor can be r educed by nar r owing t he
bandwidt h.
13
4.12
NOISE FLOOR FOR AN IDEAL 12-BIT ADC
USING 4096-POINT FFT
a
(dB)
0
20
40
60
100
FFT NOISE FLOOR
f
s
80
120
RMS QUANTIZATION NOISE LEVEL
2
f
s
4096
33dB = 10log
BIN SPACING =
74dB = 6.02N + 1.76dB
ADC FULLSCALE
N = 12-BITS
M = 4096
M
2
( )
DI STORTI ON AND NOI SE I N P RACTI CAL ADCS
A pr act ical sampling ADC (one t hat has an int egr al sample-and-hold), r egar dless of
ar chit ect ur e, has a number of noise and dist or t ion sour ces as shown in Figur e 4.13.
The wideband analog fr ont -end buffer has wideband noise, non-linear it y, and also
finit e bandwidt h. The SHA int r oduces fur t her non-linear it y, bandlimit ing, and
aper t ur e jit t er . The act ual quant izer por t ion of t he ADC int r oduces quant izat ion
noise, and bot h int egr al and differ ent ial non-linear it y. In t his discussion, assume
t hat sequent ial out put s of t he ADC ar e loaded int o a buffer memor y of lengt h M and
t hat t he FFT pr ocessor pr ovides t he spect r al out put . Also assume t hat t he FFT
ar it hmet ic oper at ions t hemselves int r oduce no significant er r or s r elat ive t o t he ADC.
However , when examining t he out put noise floor , t he FFT pr ocessing gain
(dependent on M) must be consider ed.
14
M
2
PROCESSING GAIN = 10log
ROUNDOFF ERROR (NEGLIGIBLE)
( )
a
4.13
f
s
ADC MODEL SHOWING NOISE AND DISTORTION SOURCES
ADC
N
N
TEST
SYSTEM
ANALOG
INPUT
NOISE
DISTORTION
BAND LIMITING

NOISE
DISTORTION
BAND LIMITING
APERTURE JITTER

QUANTIZATION NOISE
DIFFERENTIAL NON-LINEARITY
INTEGRAL NON-LINEARITY
TO MEMORY

BUFFER
SAMPLE
AND
HOLD
ENCODER
M-POINT
FFT
PROCESSOR
BUFFER
MEMORY
M
M
2
POINT
SPECTRAL
OUTPUT
Equ i va len t I n p u t Refer r ed Noi se (Th er ma l Noi se)
The wideband ADC int er nal cir cuit s pr oduce a cer t ain amount of wideband r ms
noise due t o t her mal effect s. This noise is pr esent even for DC input signals, and
account s for t he fact t hat t he out put of most wideband ADCs is a dist r ibut ion of
codes, cent er ed ar ound t he nominal value of a DC input (see Figur e 4.14). To
measur e it s value, t he input of t he ADC is gr ounded, and a lar ge number of out put
samples ar e collect ed and plot t ed as a hist ogr am (somet imes r efer r ed t o as a
grounded-input hist ogr am). Since t he noise is appr oximat ely Gaussian, t he st andar d
deviat ion of t he hist ogr am is easily calculat ed (see Refer ence 3), cor r esponding t o t he
effect ive input r ms noise. It is common pr act ice t o expr ess t his r ms noise in t er ms of
LSBs, alt hough it can be expr essed as an r ms volt age.
15
4.14
HISTOGRAM OF 5000 CONVERSIONS
FOR A DC INPUT SHOWS 5 LSB p-p OR
0.8LSB RMS EQUIVALENT INPUT NOISE
a
CODE
(X-2) (X-1) (X) (X+1) (X+2) (X+3)
C
O
D
E

F
R
E
Q
U
E
N
C
Y
I n t egr a l a n d Di ffer en t i a l Non -Li n ea r i t y
The over all int egr al non-linear it y of an ADC is due t o t he int egr al non-linear it y of
t he fr ont -end and SHA as well as t he over all int egr al non-linear it y in t he ADC
t r ansfer funct ion. However , differential non-linearity is due exclusively to the
encoding process and may var y consider ably dependent on t he ADC encoding
ar chit ect ur e. Over all int egr al non-linear it y pr oduces dist or t ion pr oduct s whose
amplit ude var ies as a funct ion of t he input signal amplit ude. For inst ance, second-
or der int er modulat ion pr oduct s incr ease 2dB for ever y 1dB incr ease in signal level,
and t hir d-or der pr oduct s incr ease 3dB for ever y 1dB incr ease in signal level.
QUANTIFYING ADC DYNAMIC PERFORMANCE
n n Harmonic Distortion
n n Worst Harmonic
n n Total Harmonic Distortion (THD)
n n Total Harmonic Distortion Plus Noise (THD + N)
n n Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D)
n n Effective Number of Bits (ENOB)
n n Signal-to-Noise Ratio (SNR)
16
n n Analog Bandwidth (Full-Power, Small-Signal)
n n Spurious Free Dynamic Range (SFDR)
n n Two-Tone Intermodulation Distortion
n n Noise Power Ratio (NPR)
a 4.15
The differ ent ial non-linear it y in t he ADC t r ansfer funct ion pr oduces dist or t ion
pr oduct s which not only depend on t he amplit ude of t he signal but t he posit ioning of
t he differ ent ial non-linear it y along t he ADC t r ansfer funct ion. Figur e 4.16 shows
t wo ADC t r ansfer funct ions cont aining differ ent ial non-linear it y. The left -hand
diagr am shows an er r or which occur s at midscale. Ther efor e, for bot h lar ge and
small signals, t he signal cr osses t hr ough t his point pr oducing a dist or t ion pr oduct
which is r elat ively independent of t he signal amplit ude. The r ight -hand diagr am
shows anot her ADC t r ansfer funct ion which has differ ent ial non-linear it y er r or s at
1/4 and 3/4 full scale. Signals which ar e above 1/2 scale peak-t o-peak will exer cise
t hese codes, while t hose less and 1/2 scale peak-t o-peak will not .
4.16
ADC DNL ERRORS
a
CODE
OUT
CODE
OUT
IN IN
MIDSCALE DNL
1/4FS, 3/4FS DNL
The design of most high-speed ADCs is such t hat differ ent ial non-linear it y is spr ead
acr oss t he ent ir e ADC r ange. Ther efor e, for signals which ar e wit hin a few dB of full
scale, t he over all int egr al non-linear it y of t he t r ansfer funct ion det er mines t he
dist or t ion pr oduct s. For lower level signals, however , t he har monic cont ent becomes
dominat ed by t he differ ent ial non-linear it ies and does not gener ally decr ease
pr opor t ionally wit h decr eases in signal amplit ude.
17
Ha r mon i c Di st or t i on , Wor st Ha r mon i c, Tot a l Ha r mon i c Di st or t i on (THD),
Tot a l Ha r mon i c Di st or t i on P lu s Noi se (THD + N)
Ther e ar e a number of ways t o quant ify t he dist or t ion of an ADC. An FFT analysis
can be used t o measur e t he amplit ude of t he var ious har monics of a signal as shown
in Figur e 4.17. The har monics of t he input signal can be dist inguished fr om ot her
dist or t ion pr oduct s by t heir locat ion in t he fr equency spect r um. The figur e shows a
7MHz input signal sampled at 20MSPS and t he locat ion of t he fir st 9 har monics.
Aliased har monics of f
a
fall at fr equencies equal t o | Kf
s
nf
a
| , wher e n is t he or der
of t he har monic, and K = 0, 1, 2, 3,.... The second and t hir d har monics ar e gener ally
t he only ones specified on a dat a sheet because t hey t end t o be t he lar gest , alt hough
some dat a sheet s may specify t he value of t he worst har monic. Har monic dist or t ion
is nor mally specified in dBc (decibels below car r ier ), alt hough at audio fr equencies it
may be specified as a per cent age. Har monic dist or t ion is specified wit h an input
signal near full scale (gener ally 0.5 t o 1dB below full scale t o pr event clipping). For
signals much lower t han full scale, ot her dist or t ion pr oduct s (not dir ect har monics)
may limit per for mance.
4.17
LOCATION OF HARMONIC DISTORTION PRODUCTS:
INPUT SIGNAL = 7MHz, SAMPLING RATE = 20MSPS
a
RELATIVE
AMPLITUDE
FREQUENCY (MHz)
f
a
1 2 3 4 5 6 7 8 9 10
3
6
9
8
5
7
HARMONICS AT: |Kf
s
nf
a
|
n = ORDER OF HARMONIC, K = 0, 1, 2, 3, . . .
2
4
Tot al har monic dist or t ion (THD) is t he r at io of t he r ms value of t he fundament al
signal t o t he mean value of t he r oot -sum-squar e of it s har monics (gener ally, only t he
fir st 5 ar e significant ). THD of an ADC is also gener ally specified wit h t he input
signal close t o full scale.
Tot al har monic dist or t ion plus noise (THD+ N) is t he r at io of t he r ms value of t he
fundament al signal t o t he mean value of t he r oot -sum-squar e of it s har monics plus
all noise component s (excluding DC). The bandwidt h over which t he noise is
measur ed must be specified. In t he case of an FFT, t he bandwidt h is DC t o f
s
/2. (If
18
t he bandwidt h of t he measur ement is DC t o f
s
/2, THD+N is equal t o SINAD - see
below).
Si gn a l-t o-Noi se-a n d -Di st or t i on Ra t i o (SI NAD), Si gn a l-t o-Noi se Ra t i o (SNR),
a n d Effect i ve Nu mber of Bi t s (ENOB)
SINAD and SNR deser ve car eful at t ent ion, because t her e is st ill some var iat ion
bet ween ADC manufact ur er s as t o t heir pr ecise meaning. Signal-t o-noise-and
Dist or t ion (SINAD, or S/N+D) is t he r at io of t he r ms signal amplit ude t o t he mean
value of t he r oot -sum-squar e (RSS) of all ot her spect r al component s, including
harmonics, but excluding DC. SINAD is a good indicat ion of t he over all dynamic
per for mance of an ADC as a funct ion of input fr equency because it includes all
component s which make up noise (including t her mal noise) and dist or t ion. It is oft en
plot t ed for var ious input amplit udes. SINAD is equal t o THD+N if t he bandwidt h for
t he noise measur ement is t he same. A t ypical plot for t he AD9220 12-bit , 10MSPS
ADC is shown in Figur e 4.19.
SINAD, ENOB, AND SNR
n n SINAD (Signal-to-Noise-and-Distortion Ratio):
The ratio of the rms signal amplitude to the mean value of
the root-sum-squares (RSS) of all other spectral components,
including harmonics, but excluding DC
n n ENOB (Effective Number of Bits):
ENOB
SINAD dB
= =
176
6 02
.
.
n n SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio
Without Harmonics):
The ratio of the rms signal amplitude to the mean value of
the root-sum-squares (RSS) of all other spectral components,
excluding the first 5 harmonics and DC
a 4.18
19
4.19
AD9220 12-BIT, 10MSPS ADC SINAD AND ENOB
VS. INPUT FREQUENCY FOR SAMPLING RATE = 10MSPS:
SINGLE-ENDED DRIVE, V
cm
= +2.5V, INPUT SPAN = 2V p-p
a
65
FREQUENCY - MHz
80
75
40
70
45
60
55
50
0.1 1.0 10.0
-0.5dB
-6dB
-20dB
13
S
I
N
A
D

-

d
B
12.2
11.3
10.5
9.7
8.8
8
7.2
6.3
E
N
O
B
S
The SINAD plot shows wher e t he AC per for mance of t he ADC degr ades due t o high-
fr equency dist or t ion and is usually plot t ed for fr equencies well above t he Nyquist
fr equency so t hat per for mance in under sampling applicat ions can be evaluat ed.
SINAD is oft en conver t ed t o effect ive-number -of-bit s (ENOB) using t he r elat ionship
for t he t heor et ical SNR of an ideal N-bit ADC: SNR = 6.02N + 1.76dB. The equat ion
is solved for N, and t he value of SINAD is subst it ut ed for SNR:
ENOB
SINAD dB
=
1 76
6 02
.
.
.
Signal-t o-noise r at io (SNR, or S NR-without-harmonics) is calculat ed t he same as
SINAD except t hat t he signal har monics ar e excluded fr om t he calculat ion, leaving
only t he noise t er ms. In pr act ice, it is only necessar y t o exclude t he fir st 5 har monics
since t hey dominat e. The SNR plot will degr ade at high fr equencies also, but not as
r apidly as SINAD because of t he exclusion of t he har monic t er ms.
Many cur r ent ADC dat a sheet s somewhat loosely r efer t o SINAD as SNR, so t he
engineer must be car eful when int er pr et ing t hese specificat ions.
An a log Ba n d wi d t h
The analog bandwidt h of an ADC is t hat fr equency at which t he spect r al out put of
t he fundamental swept fr equency (as det er mined by t he FFT analysis) is r educed by
3dB. It may be specified for eit her a small signal (SSBW- small signal bandwidt h),
or a full scale signal (FPBW- full power bandwidt h), so t her e can be a wide var iat ion
in specificat ions bet ween manufact ur er s.
20
Like an amplifier , t he analog bandwidt h specificat ion of a conver t er does not imply
t hat t he ADC maint ains good dist or t ion per for mance up t o it s bandwidt h fr equency.
In fact , t he SINAD (or ENOB) of most ADCs will begin t o degr ade consider ably
befor e t he input fr equency appr oaches t he act ual 3dB bandwidt h fr equency. Figur e
4.20 shows ENOB and full scale fr equency r esponse of an ADC wit h a FPBW of
1MHz, however , t he ENOB begins t o dr op r apidly above 100kHz.
a 4.20
ADC GAIN (BANDWIDTH) AND ENOB VERSUS FREQUENCY
SHOWS IMPORTANCE OF ENOB SPECIFICATION
ADC INPUT FREQUENCY (Hz)
ENOB
GAIN (FS INPUT)
ENOB (FS INPUT)
ENOB (-20dB INPUT)
FPBW = 1MHz
10 100 1k 10k 100k 1M 10M
Sp u r i ou s Fr ee Dyn a mi c Ra n ge (SFDR)
Pr obably t he most significant specificat ion for an ADC used in a communicat ions
applicat ion is it s spur ious fr ee dynamic r ange (SFDR). The SFDR specificat ion is t o
ADCs what t he t hir d or der int er cept specificat ion is t o mixer s and LNAs. SFDR of
an ADC is defined as t he r at io of t he r ms signal amplit ude t o t he r ms value of t he
peak spurious spectral content (measur ed over t he ent ir e fir st Nyquist zone, DC t o
f
s
/2). SFDR is gener ally plot t ed as a funct ion of signal amplit ude and may be
expr essed r elat ive t o t he signal amplit ude (dBc) or t he ADC full scale (dBFS).
For a signal near full scale, t he peak spect r al spur is gener ally det er mined by one of
t he fir st few har monics of t he fundament al. However , as t he signal falls sever al dB
below full scale, ot her spur s gener ally occur which ar e not dir ect har monics of t he
input signal. This is because of t he differ ent ial non-linear it y of t he ADC t r ansfer
funct ion as discussed ear lier . Ther efor e, SFDR consider s all sour ces of dist or t ion,
r egar dless of t heir or igin.
The AD9042 is a 12-bit , 41MSPS wideband ADC designed for communicat ions
applicat ions wher e high SFDR is impor t ant . The SFDR for a 19.5MHz input and a
sampling fr equency of 41MSPS is shown in Figur e 4.21. Not e t hat a minimum of
21
80dBc SFDR is obt ained over t he ent ir e fir st Nyquist zone (DC t o 20MHz). The plot
also shows SFDR expr essed as dBFS.
4.21
AD99042 12-BIT, 41MSPS ADC
SFDR VS. INPUT POWER LEVEL
a
ANALOG INPUT POWER LEVEL - dBFS
100
0
-80 0 -70 -60 -50 -40 -30 -20 -10
90
60
40
20
10
80
70
50
30
ENCODE = 41 MSPS
AIN = 19.5MHz
dBFS
dBc
SFDR = 80dB
REFERENCE LINE
W
O
R
S
T

C
A
S
E

S
P
U
R
I
O
U
S

-

d
B
c

A
N
D

d
B
F
S
SFDR is gener ally much gr eat er t han t he ADCs t heor et ical N-bit SNR (6.02N +
1.76dB). For example, t he AD9042 is a 12-bit ADC wit h an SFDR of 80dBc and a
t ypical SNR of 65dBc (t heor et ical SNR is 74dB). This is because t her e is a
fundament al dist inct ion bet ween noise and dist or t ion measur ement s. The pr ocess
gain of t he FFT (33dB for a 4096-point FFT) allows fr equency spur s well below t he
noise floor t o be obser ved. Adding ext r a r esolut ion t o an ADC may ser ve t o incr ease
it s SNR but may or may not incr ease it s SFDR.
Two Ton e I n t er mod u la t i on Di st or t i on
Two t one IMD is measur ed by applying t wo spect r ally pur e sinewaves t o t he ADC at
fr equencies f1 and f2, usually r elat ively close t oget her . The amplit ude of each t one is
set slight ly mor e t han 6dB below full scale so t hat t he ADC does not clip when t he
t wo t ones add in-phase. The locat ion of t he second and t hir d-or der pr oduct s ar e
shown in Figur e 4.22. Not ice t hat t he second-or der pr oduct s fall at fr equencies
which can be r emoved by digit al filt er s. However , t he t hir d-or der pr oduct s 2f2f1
and 2f1f2 ar e close t o t he or iginal signals and ar e mor e difficult t o filt er . Unless
ot her wise specified, t wo-t one IMD r efer s t o t hese t hir d-or der pr oduct s. The value of
t he IMD pr oduct is expr essed in dBc r elat ive t o t he value of either of t he t wo or iginal
t ones, and not t o t heir sum.
22
a 4.22
SECOND AND THIRD-ORDER INTERMODULATION
PRODUCTS FOR f
1
= 5MHz, f
2
= 6MHz
FREQUENCY: MHz
2 = SECOND ORDER IMD PRODUCTS
3 = THIRD ORDER IMD PRODUCTS
NOTE: f
1
= 5MHz, f
2
= 6MHz
f
2
- f
1
2f
1
- f
2
2f
2
- f
1
f
1
f
2
2f
1
2f
2
f
2
+ f
1
2f
1
+ f
2
3f
1
2f
2
+ f
1
3f
2
2
3 3
2
3
3
1 4 5 6 7 10 11 12 15 16 17 18
Not e, however , t hat if t he t wo t ones ar e close t o f
s
/4, t hen t he aliased t hir d har monic
of t he fundament al can make t he ident ificat ion of t he act ual 2f2f1 and 2f1f2
pr oduct s difficult . Similar ly, if t he t wo t ones ar e close t o f
s
/3, t he aliased second
har monic may int er fer e wit h t he measur ement .
The concept of second and third-order intercept points is not valid for an ADC,
because t he dist or t ion pr oduct s do not var y in a pr edict able manner (as a funct ion
of signal amplit ude). The ADC does not gr adually begin t o compr ess signals
appr oaching full scale (t her e is no 1dB compr ession point ), it act s as a hard limiter
as soon as t he signal exceeds t he ADC input r ange, t her eby suddenly pr oducing
ext r eme amount s of dist or t ion because of clipping.
On t he ot her hand, for signals much below full scale, t he dist or t ion floor r emains
r elat ively const ant and is independent of signal level. This is illust r at ed in Figur e
4.23 for t he AD9042, wher e t wo-t one SFDR is plot t ed as a funct ion of signal level.
The plot indicat es t hat t he dist or t ion floor r anges fr om 85 t o 90dBFS r egar dless of
t he input signal amplit ude.
23
4.23
AD9042 12-BIT, 41MSPS ADC TWO-TONE SFDR
a
INPUT POWER LEVEL (F1 = F2) - dBFS
100
0
-80 0 -70 -60 -50 -40 -30 -20 -10
90
60
40
20
10
80
70
50
30
ENCODE = 41 MSPS
F1 = 19.3MHz
F2 = 19.51MHz
SFDR = 80dB
REFERENCE LINE
dBFS
dBc
W
O
R
S
T

C
A
S
E

S
P
U
R
I
O
U
S

-

d
B
c

A
N
D

d
B
F
S
Noi se P ower Ra t i o (NP R)
Noise power r at io t est ing has been used ext ensively t o measur e t he t r ansmission
char act er ist ics of Fr equency Division Mult iplexed (FDM) communicat ions links (see
Refer ence 4). In a t ypical FDM syst em, 4kHz wide voice channels ar e "st acked" in
fr equency bins for t r ansmission over coaxial, micr owave, or sat ellit e equipment . At
t he r eceiving end, t he FDM dat a is demult iplexed and r et ur ned t o 4kHz individual
baseband channels. In an FDM syst em having mor e t han appr oximat ely 100
channels, t he FDM signal can be appr oximat ed by Gaussian noise wit h t he
appr opr iat e bandwidt h. An individual 4kHz channel can be measur ed for
"quiet ness" using a nar r ow-band not ch (bandst op) filt er and a specially t uned
r eceiver which measur es t he noise power inside t he 4kHz not ch (see Figur e 4.24).
24
a
4.24
NOISE POWER RATIO (NPR) MEASUREMENTS
f
s
GAUSSIAN
NOISE
SOURCE
GAUSSIAN
NOISE
SOURCE
LPF
LPF
NOTCH
FILTER
NOTCH
FILTER
N
ADC
TRANSMISSION
SYSTEM
NARROWBAND
RECEIVER
BUFFER
MEMORY
AND FFT
PROCESSOR
0.5f
s
RMS
NOISE
LEVEL
(dB)
NPR
FREQUENCY
Noise Power Rat io (NPR) measur ement s ar e st r aight for war d. Wit h t he not ch filt er
out , t he r ms noise power of t he signal inside t he not ch is measur ed by t he
nar r owband r eceiver . The not ch filt er is t hen swit ched in, and t he r esidual noise
inside t he slot is measur ed. The r at io of t hese t wo r eadings expr essed in dB is t he
NPR. Sever al slot fr equencies acr oss t he noise bandwidt h (low, midband, and high)
ar e t est ed t o char act er ize t he syst em adequat ely. NPR measur ement s on ADCs ar e
made in a similar manner except t he analog r eceiver is r eplaced by a buffer memor y
and an FFT pr ocessor .
NPR is usually plot t ed on an NPR cur ve. The NPR is plot t ed as a funct ion of r ms
noise level r efer r ed t o t he peak r ange of t he syst em. For ver y low noise loading level,
t he undesir ed noise (in non-digit al syst ems) is pr imar ily t her mal noise and is
independent of t he input noise level. Over t his r egion of t he cur ve, a 1dB incr ease in
noise loading level causes a 1dB incr ease in NPR. As t he noise loading level is
incr eased, t he amplifier s in t he syst em begin t o over load, cr eat ing int er modulat ion
pr oduct s which cause t he noise floor of t he syst em t o incr ease. As t he input noise
incr eases fur t her , t he effect s of "over load" noise pr edominat e, and t he NPR is
r educed dr amat ically. FDM syst ems ar e usually oper at ed at a noise loading level a
few dB below t he point of maximum NPR.
In a digit al syst em cont aining an ADC, t he noise wit hin t he slot is pr imar ily
quant izat ion noise when low levels of noise input ar e applied. The NPR cur ve is
linear in t his r egion. As t he noise level incr eases, t her e is a one-for -one
cor r espondence bet ween t he noise level and t he NPR. At some level, however ,
"clipping" noise caused by t he har d-limit ing act ion of t he ADC begins t o dominat e. A
t heor et ical cur ve for 10, 11, and 12-bit ADCs is shown in Figur e 4.25 (see Refer ence
5). Peak NPR and cor r esponding loading levels ar e shown in Figur e 4.26.
25
a
4.25
THEORETICAL NPR FOR 10, 11, 12-BIT ADCs
V
O

NPR
(dB) 62.7dB
RMS NOISE LOADING LEVEL = -20log(k) dB
57.1dB
51.6dB
60
55
50
45
-30 -25 -20 -15 -10
ADC RANGE = V
O
k =
= RMS NOISE LEVEL
1
2
-
B
I
T
S
1
1
-
B
I
T
S
1
0
-
B
I
T
S
THEORETICAL NPR SUMMARY
BITS k OPTIMUM k(dB) MAX NPR (dB)
8 3.92 11.87 40.60
9 4.22 12.50 46.05
10 4.50 13.06 51.56
11 4.76 13.55 57.12
12 5.01 14.00 62.71
13 5.26 14.41 68.35
14 5.49 14.79 74.01
15 5.72 15.15 79.70
16 5.94 15.47 85.40
ADC Range = V
o
k = V
o
/
= RMS Noise Level
a 4.26
In mult i-channel high fr equency communicat ion syst ems, NPR can also be used t o
simulat e t he dist or t ion caused by a lar ge number of individual channels, similar t o
26
an FDM syst em. A not ch filt er is placed bet ween t he noise sour ce and t he ADC, and
an FFT out put is used in place of t he analog r eceiver . The widt h of t he not ch filt er is
set for sever al MHz as shown in Figur e 4.27 for t he AD9042. NPR is t he "dept h" of
t he not ch. An ideal ADC will only gener at e quant izat ion noise inside t he not ch,
however a pr act ical one has addit ional noise component s due t o int er modulat ion
dist or t ion caused by ADC non-linear it y. Not ice t hat t he NPR is about 60dB
compar ed t o 62.7dB t heor et ical.
4.27
AD9042 12-BIT, 41MSPS ADC NPR
MEASURES 60dB (62.7dB THEORETICAL)
a
FREQUENCY - MHz
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L

S
C
A
L
E

-

d
B
0
-80
-120
-40
-100
-20
-60
dc 4.1 8.2 12.3 16.4
20.5
ENCODE = 41 MSPS
AIN = BROADBAND_NOISE
Ap er t u r e J i t t er a n d Ap er t u r e Dela y
Anot her r eason t hat t he SNR of an ADC decr eases wit h input fr equency may be
deduced fr om Figur e 4.28, which shows t he effect s of phase jit t er (or aper t ur e t ime
jit t er ) on t he sampling clock of an ADC (or int er nal in t he sample-and-hold). The
phase jit t er causes a volt age er r or which is a funct ion of slew r at e and r esult s in an
over all degr adat ion in SNR as shown in Figur e 4.29. This is quit e ser ious, especially
at higher input /out put fr equencies. Ther efor e, ext r eme car e must be t aken t o
minimize phase noise in t he sampling/r econst r uct ion clock of any sampled dat a
syst em. This car e must ext end t o all aspect s of t he clock signal: t he oscillat or it self
(for example, a 555 t imer is absolut ely inadequat e, but even a quar t z cr yst al
oscillat or can give pr oblems if it uses an act ive device which shar es a chip wit h noisy
logic); t he t r ansmission pat h (t hese clocks ar e ver y vulner able t o int er fer ence of all
sor t s), and phase noise int r oduced in t he ADC or DAC. A ver y common sour ce of
phase noise in conver t er cir cuit r y is aper t ur e jit t er in t he int egr al sample-and-hold
(SHA) cir cuit r y.
27
a 4.28
EFFECTS OF APERTURE AND SAMPLING CLOCK JITTER
TRACK
NOMINAL
HELD
OUTPUT
ANALOG
INPUT
= SLOPE
dv
dt
HOLD
t
RMS
= APERTURE JITTER
v
RMS
= APERTURE JITTER ERROR
{
v = t
dv
dt
a 4.29
SNR DUE TO APERTURE AND SAMPLING CLOCK JITTER
SNR
(dB)
ENOB
FULLSCALE SINEWAVE INPUT FREQUENCY (MHz)
100
80
60
40
20
0
16
14
12
10
8
6
4
1 3 10 30 100
SNR = 20log
10
1
2 ft
j
t
j
=
1
p
s
t
j
=
1
0
p
s
t
j
=
1
0
0
p
s
t
j
=
1
n
s
A decade or so ago, sampling ADCs wer e built up fr om a separ at e SHA and ADC.
Int er face design was difficult , and a key par amet er was aper t ur e jit t er in t he SHA.
Today, most sampled dat a syst ems use sampling ADCs which cont ain an int egr al
SHA. The aper t ur e jit t er of t he SHA may not be specified as such, but t his is not a
28
cause of concer n if t he SNR or ENOB is clear ly specified, since a guar ant ee of a
specific SNR is an implicit guar ant ee of an adequat e aper t ur e jit t er specificat ion.
However , t he use of an addit ional high-per for mance SHA will somet imes impr ove
t he high-fr equency ENOB of a even t he best sampling ADC by pr esent ing "DC" t o
t he ADC, and may be mor e cost -effect ive t han r eplacing t he ADC wit h a mor e
expensive one.
It should be not ed t hat t her e is also a fixed component which makes up t he ADC
aper t ur e t ime. This component , usually called effective aperture delay time, does not
pr oduce an er r or . It simply r esult s in a t ime offset bet ween t he t ime t he ADC is
asked t o sample and when t he act ual sample t akes place (see Figur e 4.30), and may
be posit ive or negat ive. The var iat ion or t oler ance placed on t his par amet er fr om
par t t o par t is impor t ant in simult aneous sampling applicat ions or ot her
applicat ions such as I and Q demodulat ion wher e t wo ADCs ar e r equir ed t o t r ack
each ot her .
a 4.30
EFFECTIVE APERTURE DELAY TIME
SAMPLING
CLOCK
ANALOG INPUT
SINEWAVE
ZERO CROSSING
+FS
-FS
0V
+t
e
-t
e
t
e
HI GH SP EED ADC ARCHI TECTURES
Su ccessi ve Ap p r oxi ma t i on ADCs
The successive appr oximat ion (SAR) ADC ar chit ect ur e has been used for decades
and is st ill a popular and cost effect ive for m of conver t er for sampling fr equencies of
1MSPS or less. A simplified block diagr am of a SAR ADC is shown in Figur e 4.31.
On t he START CONVERT command, all t he bit s of t he successive appr oximat ion
r egist er (SAR) ar e r eset t o "0" except t he MSB which is set t o "1". Bit 1 is t hen t est ed
in t he following manner : If t he DAC out put is gr eat er t han t he analog input , t he
MSB is r eset , ot her wise it is left set . The next most significant bit is t hen t est ed by
set t ing it t o "1". If t he DAC out put is gr eat er t han t he analog input , t his bit is r eset ,
29
ot her wise it is left set . The pr ocess is r epeat ed wit h each bit in t ur n. When all t he
bit s have been set , t est ed, and r eset or not as appr opr iat e, t he cont ent s of t he SAR
cor r espond t o t he digit al value of t he analog input , and t he conver sion is complet e.
4.31
SUCCESSIVE APPROXIMATION ADC
a
ANALOG
INPUT
START
CONVERT
COMPARATOR
EOC OR
DRDY
SHA
+
-
DAC
SAR*
*SUCCESSIVE
APPROXIMATION
REGISTER
DIGITAL
OUTPUT
An N-bit conver sion t akes N st eps. It would seem on super ficial examinat ion t hat a
16-bit conver t er would have a conver sion t ime t hat is t wice as long as an 8-bit one,
but t his is not t he case. In an 8-bit conver t er , t he DAC must set t le t o 8-bit accur acy
befor e t he bit decision is made, wher eas in a 16-bit conver t er , it must set t le t o 16-bit
accur acy, which t akes a lot longer . In pr act ice, 8-bit successive appr oximat ion ADCs
can conver t in a few hundr ed nanoseconds, while 16-bit ones will gener ally t ake
sever al micr oseconds.
The classic SAR ADC is only a quant izer : no sampling t akes place, and for an
accur at e conver sion, t he input must r emain const ant for t he ent ir e conver sion
per iod. Most moder n SAR ADCs ar e sampling t ypes and have an int er nal sample-
and-hold so t hat t hey can pr ocess AC signals. They ar e specified for bot h AC and DC
applicat ions. A SHA is r equir ed in a SAR ADC because t he signal must r emain
const ant dur ing t he ent ir e N-bit conver sion cycle.
The accur acy of a SAR ADC depends pr imar ily on t he accur acy (differ ent ial and
int egr al linear it y, gain, and offset ) of t he int er nal DAC. Unt il r ecent ly, t his accur acy
was achieved using laser t r immed t hin film r esist or s. Moder n SAR ADCs ut ilize
CMOS swit ched capacit or char ge r edist r ibut ion DACs. This t ype of DAC depends on
t he accur at e r at io mat ching and st abilit y of on-chip capacit or s r at her t han t hin film
r esist or s. For r esolut ions gr eat er t han 12-bit s, on-chip aut ocalibr at ion t echniques
using an addit ional calibration DAC and t he accompanying logic can accomplish t he
same t hing as t hin film laser t r immed r esist or s, at much less cost . Ther efor e, t he
ent ir e ADC can be made on a st andar d sub-micr on CMOS pr ocess.
30
The successive appr oximat ion ADC has a ver y simple st r uct ur e, is low power , and
has r easonably fast conver sion t imes (<1MSPS). It is pr obably t he most widely used
ADC ar chit ect ur e, and will cont inue t o be used for medium speed and medium
r esolut ion applicat ions.
Cur r ent 12-bit SAR ADCs achieve sampling r at es up t o about 1MSPS, and 16-bit
ones up t o about 300kSPS. Examples of t ypical st at e-of-t he-ar t SAR ADCs ar e t he
AD7892 (12-bit s at 600kSPS), t he AD976/977 (16-bit s at 100kSPS), and t he AD7882
(16-bit s at 300kSPS).
Fla sh Con ver t er s
Flash ADCs (somet imes called parallel ADCs) ar e t he fast est t ype of ADC and use
lar ge number s of compar at or s. An N-bit flash ADC consist s of 2
N
r esist or s and 2
N
1
compar at or s ar r anged as in Figur e 4.32. Each compar at or has a r efer ence volt age
which is 1 LSB higher t han t hat of t he one below it in t he chain. For a given input
volt age, all t he compar at or s below a cer t ain point will have t heir input volt age
lar ger t han t heir r efer ence volt age and a "1" logic out put , and all t he compar at or s
above t hat point will have a r efer ence volt age lar ger t han t he input volt age and a
"0" logic out put . The 2
N
1 compar at or out put s t her efor e behave in a way analogous
t o a mer cur y t her momet er , and t he out put code at t his point is somet imes called a
thermometer code. Since 2
N
1 dat a out put s ar e not r eally pr act ical, t hey ar e
pr ocessed by a decoder t o an N-bit binar y out put .
a
4.32
FLASH OR PARALLEL ADC
ANALOG
INPUT
DIGITAL
OUTPUT
N
R
R
R
R
R
R
0.5R
1.5R
+V
REF
STROBE
PRIORITY
ENCODER
AND
LATCH
31
The input signal is applied t o all t he compar at or s at once, so t he t her momet er
out put is delayed by only one compar at or delay fr om t he input , and t he encoder
N-bit out put by only a few gat e delays on t op of t hat , so t he pr ocess is ver y fast .
However , t he ar chit ect ur e uses lar ge number s of r esist or s and compar at or s and it
limit ed t o low r esolut ions, and if it is t o be fast , each compar at or must r un at
r elat ively high power levels. Hence, t he pr oblems of flash ADCs include limit ed
r esolut ion, high power dissipat ion because of t he lar ge number of high speed
compar at or s (especially at sampling r at es gr eat er t han 50MSPS), and r elat ively
lar ge (and t her efor e expensive) chip sizes. In addit ion, t he r esist ance of t he r efer ence
r esist or chain must be kept low t o supply adequat e bias cur r ent t o t he fast
compar at or s, so t he volt age r efer ence has t o sour ce quit e lar ge cur r ent s (>10 mA).
In pr act ice, flash conver t er s ar e available up t o 10-bit s, but mor e commonly t hey
have 8-bit s of r esolut ion. Their maximum sampling r at e can be as high as
500 MSPS, and input full-power bandwidt hs in excess of 300 MHz.
But as ment ioned ear lier , full-power bandwidt hs ar e not necessar ily full-r esolut ion
bandwidt hs. Ideally, t he compar at or s in a flash conver t er ar e well mat ched bot h for
DC and AC char act er ist ics. Because t he st r obe is applied t o all t he compar at or s
simult aneously, t he flash conver t er is inher ent ly a sampling conver t er . In pr act ice,
t her e ar e delay var iat ions bet ween t he compar at or s and ot her AC mismat ches which
cause a degr adat ion in ENOB at high input fr equencies. This is because t he input s
ar e slewing at a r at e compar able t o t he compar at or conver sion t ime.
The input t o a flash ADC is applied in par allel t o a lar ge number of compar at or s.
Each has a volt age-var iable junct ion capacit ance, and t his signal-dependent
capacit ance r esult s in all flash ADCs having r educed ENOB and higher dist or t ion at
high input fr equencies. A model is shown in Figur e 4.33, wher e t he input
capacit ance is modeled as a fixed 10pF capacit or in par allel wit h a var iable capacit or
(modeled as a diode wit h a zer o-bias junct ion capacit ance of 6pF). As t he input
changes fr om FS t o +FS, t he t ot al input capacit ance changes fr om about 12.5 t o
16pF. The wideband ext er nal dr ive amplifier is isolat ed fr om t he flash conver t er by
a 50 ser ies r esist or . The dist or t ion of t his cir cuit degr ades fr om about 70dBc at
1MHz t o 35dBc at 100MHz.
32
a
4.33
SIGNAL-DEPENDENT INPUT CAPACITANCE CAUSES
DISTORTION AT HIGH FREQUENCIES
THD
(dB)
70
60
50
40
30
1 10 100
ANALOG
INPUT
50
-FS TO +FS
10pF
+FS
C
JO
= 6pF
FLASH INPUT MODEL
A
INPUT FREQUENCY (MHz)
High dat a r at e digit al communicat ions applicat ions such as set -t op boxes for dir ect
br oadcast sat ellit es (DBS) r equir e dual 6 or 8-bit high speed ADCs t o per for m
quadr at ur e demodulat ion. A dual flash conver t er ensur es good mat ching bet ween
t he t wo ADCs. The AD9066 (dual 6-bit , 60MSPS) flash conver t er is r epr esent at ive of
t his t ype of conver t er . The AD9066 is fabr icat ed on a BiCMOS pr ocess, oper at es on a
single +5V supply, and dissipat es 400mW. The effect ive bit per for mance of t he
device is shown in Figur e 4.34. Not e t hat t he device maint ains gr eat er t han 5
ENOBs up t o 60MSPS analog input .
33
a
4.34
AD9066 DUAL 6-BIT, 60MSPS ADC ENOB
VS. ANALOG INPUT FREQUENCY
MHz
5.8
5.7
5.2
1 100 10
5.6
5.5
5.4
5.3
ENCODE = 60 MSPS
E
N
O
B

-

B
i
t
s
Par t of t he r eason for t he excellent per for mance of t he AD9066 is t he use of an
int er polat ion scheme t hat r educes t he number of differ ent ial amplifier s r equir ed by
a fact or of t wo (see Refer ence 6). The ar chit ect ur e enables 64 possible quant izat ion
levels t o be det er mined wit h only 32 pr eamplifier s which dr ive 63 lat ches. This
keeps t he input capacit ance t o a minimum (10pF) and r educes t ot al power
dissipat ion of t he device. The basic int er polat ion cir cuit is shown in Figur e 4.35.
34
B
a 4.35
"INTERPOLATING" FLASH REDUCES THE NUMBER
OF PREAMPLIFIERS BY FACTOR OF TWO
V1A =
A2
LATCH
STROBE
ANALOG
INPUT ANALOG
INPUT
DECODE
LATCH
2
LATCH
1A
LATCH
1
A
B
V2
V1
A
A1
+
+
-
-
B
B
V1A
V1
A
A
V2
V1 + V2
2
The pr eamplifier s ar e low-gain g
m
st ages whose bandwidt h is pr opor t ional t o t he
t ail cur r ent s of t he differ ent ial pair s. Consider t he case for a posit ive-going r amp
input which is init ially below t he r efer ence t o AMP A1, V1. As t he input signal
appr oaches V1, t he differ ent ial out put of A1 appr oaches zer o (i.e., A = A ), and t he
decision point is r eached. The out put of A1 dr ives t he differ ent ial input of LATCH 1.
As t he input signals cont inues t o go posit ive, A cont inues t o go posit ive, and B
begins t o go negat ive. The int er polat ed decision point is det er mined when A = B . As
t he input cont inues posit ive, t he t hir d decision point is r eached when B = B . This
novel ar chit ect ur e r educes t he ADC input capacit ance and t her eby minimizes it s
change wit h signal level and t he associat ed dist or t ion. The input capacit ance of t he
AD9066 is only about 10pF. Key specificat ions for t he device ar e summar ized in
Figur e 4.36.
AD9066 DUAL 6-BIT, 60MSPS FLASH ADC
KEY SPECIFICATIONS
n n Input Range: 500mV p-p
n n Input Impedance: 50k || 10pF
n n ENOB: 5.7bits @ 15.5MHz Input
n n On-Chip Reference
n n Power Supply: Single +5V
n n Power Dissipation: 400mW
35
n n Package: 28-pin SOIC
n n Ideal for Quadrature Demodulation
a 4.36
Su br a n gi n g (P i p eli n ed ) ADCs
Alt hough it is not pr act ical t o make flash ADCs wit h high r esolut ion, flash ADCs ar e
oft en used as subsyst ems in "subr anging" ADCs (somet imes known as "half-flash
ADCs"), which ar e capable of much higher r esolut ions (up t o 16-bit s).
A block diagr am of an 8-bit subr anging ADC based upon t wo 4-bit flash conver t er s is
shown in Figur e 4.37. Alt hough 8-bit flash conver t er s ar e r eadily available at high
sampling r at es, t his example will be used t o illust r at e t he t heor y. The conver sion
pr ocess is done in t wo st eps. The fir st four significant bit s (MSBs) ar e digit ized by
t he fir st flash (t o bet t er t han 8-bit s accur acy), and t he 4-bit binar y out put is applied
t o a 4-bit DAC (again, bet t er t han 8-bit accur at e). The DAC out put is subt r act ed
fr om t he held analog input , and t he r esult ing r esidue signal is amplified and applied
t o t he second 4-bit flash. The out put s of t he t wo 4-bit flash conver t er s ar e t hen
combined int o a single 8-bit binar y out put wor d. If t he r esidue signal r ange does not
exact ly fill t he r ange of t he second flash conver t er , non-linear it ies and per haps
missing codes will r esult .
a
8-BIT SUBRANGING ADC
4.37
ANALOG
INPUT
4
8
SHA
4-BIT
FLASH
4-BIT
DAC
4-BIT
FLASH
GAIN
4
+
-
RESIDUE
SIGNAL
OUTPUT REGISTER
Moder n subr anging ADCs use a t echnique called digital correction t o eliminat e
pr oblems associat ed wit h t he ar chit ect ur e of Figur e 4.37. A simplified block diagr am
36
of a 12-bit digit ally cor r ect ed subr anging (DCS) ADC is shown in Figur e 4.38. The
ar chit ect ur e is similar t o t hat used in t he AD9042 12-bit , 41MSPS ADC. Not e t hat a
6-bit and an 7-bit ADC have been used t o achieve an over all 12-bit out put . These
ar e not flash ADCs, but ut ilize a magnitude-amplifier (MagAmp) ar chit ect ur e
which will be descr ibed shor t ly.
a
AD9042 12-BIT, 41MSPS PIPELINED SUBRANGING ADC
WITH DIGITAL ERROR CORRECTION
4.38
+
-
ANALOG
INPUT
7
12
ERROR CORRECTION LOGIC
OUTPUT REGISTERS
SHA
1
SHA
2
6-BIT
ADC
6-BIT
DAC
7-BIT
ADC
SHA
3
GAIN
12
BUFFER
REGISTER
6
6
If t her e wer e no er r or s in t he fir st -st age conver sion, t he 6-bit "r esidue" signal
applied t o t he 7-bit ADC by t he summing amplifier would never exceed one-half of
t he r ange of t he 7-bit ADC. The ext r a r ange in t he second ADC is used in
conjunct ion wit h t he er r or cor r ect ion logic (usually just a full adder ) t o cor r ect t he
out put dat a for most of t he er r or s inher ent in t he t r adit ional uncor r ect ed subr anging
conver t er ar chit ect ur e. It is impor t ant t o not e t hat t he 6-bit DAC must be bet t er
t han 12-bit accur at e, because t he digit al er r or cor r ect ion does not cor r ect for DAC
er r or s. In pr act ice, "t her momet er " or "fully-decoded" DACs using one cur r ent swit ch
per level (63 swit ches in t he case of a 6-bit DAC) ar e oft en used inst ead of a "binar y"
DAC t o ensur e excellent differ ent ial and int egr al linear it y and minimum swit ching
t r ansient s.
The second SHA delays t he held out put of t he fir st SHA while t he fir st -st age
conver sion occur s, t her eby maximizing t hr oughput . The t hir d SHA ser ves t o deglitch
t he r esidue out put signal, t her eby allowing a full conver sion cycle for t he 7-bit ADC
t o make it s decision (t he 6 and 7-bit ADCs in t he AD9042 ar e bit -ser ial MagAmp
ADCs which r equir e mor e set t ling t ime t han a flash conver t er ).
This mult i-st age conver sion t echnique is somet imes r efer r ed t o as "pipelining."
Addit ional shift r egist er s in ser ies wit h t he digit al out put s of t he fir st -st age ADC
ensur e t hat it s out put is ult imat ely t ime-aligned wit h t he last 7 bit s fr om t he
second ADC when t heir out put s ar e combined in t he er r or cor r ect ion logic. A
37
pipelined ADC t her efor e has a specified number of clock cycles of latency, or pipeline
delay associat ed wit h t he out put dat a. The leading edge of t he sampling clock (for
sample N) is used t o clock t he out put r egist er , but t he dat a which appear s as a
r esult of t hat clock edge cor r esponds t o sample N L, wher e L is t he number of clock
cycles of lat ency. In t he case of t he AD9042, t her e ar e t wo clock cycles of lat ency.
Key specificat ions for t he AD9042 ar e shown in Figur e 4.39.
AD9042 12-BIT, 41MSPS ADC KEY SPECIFICATIONS
n n Input Range: 1V peak-to-peak, V
cm
= +2.4V
n n Input Impedance: 250 to V
cm
n n Effective Input Noise: 0.33LSBs rms
n n SFDR at 20MHz Input: 80dB minimum
n n SINAD (S/N+D) at 20MHz Input = 67dB
n n Digital Outputs: TTL Compatible
n n Power Supply: Single +5V
n n Power Dissipation: 595mW
n n Fabricated on High Speed Dielectrically Isolated
Complementary Bipolar Process
a 4.39
The er r or cor r ect ion scheme descr ibed above is designed t o cor r ect for er r or s made in
t he fir st conver sion. Int er nal ADC gain, offset , and linear it y er r or s ar e cor r ect ed as
long as t he r esidue signal fall wit hin t he r ange of t he second-st age ADC. These
er r or s will not affect t he linear it y of t he over all ADC t r ansfer char act er ist ic. Er r or s
made in t he final conver sion, however , do t r anslat e dir ect ly as er r or s in t he over all
t r ansfer funct ion. Also, linear it y er r or s or gain er r or s eit her in t he DAC or t he
r esidue amplifier will not be cor r ect ed and will show up as nonlinear it ies or non-
monot onic behavior in t he over all ADC t r ansfer funct ion.
So far , we have consider ed only t wo-st age subr anging ADCs, as t hese ar e easiest t o
analyze. Ther e is no r eason t o st op at t wo st ages, however . Thr ee-pass and four -pass
subr anging pipelined ADCs ar e quit e common, and can be made in many differ ent
ways, usually wit h digit al er r or cor r ect ion.
A simplified block diagr am of t he AD9220 12-bit , 10MSPS single-supply, 250mW
CMOS ADC is shown in Figur e 4.40. The AD9221 (1.25MSPS, 60mW) and t he
AD9223 (3MSPS, 100mW) ADCs use t he ident ical ar chit ect ur e but oper at e at lower
power and lower sampling r at es. This is a four -st age pipelined ar chit ect ur e wit h an
addit ional bit in t he second, t hir d, and four t h st age for er r or cor r ect ion. Because of
38
t he pipelined ar chit ect ur e, t hese ADCs have a 3 clock-cycle lat ency (see Figur e 4.41).
Key specificat ions for t he AD9220/9221/9223 ar e given in Figur e 4.42.
a
AD9220/9221/9223 12-BIT PIPELINED CMOS ADC
4.40
ANALOG
INPUT
+ +
+
- - -
5
4 3
3
12
12
BUFFER REGISTERS AND
ERROR CORRECTION LOGIC
OUTPUT REGISTERS
SHA
1
SHA
2
SHA
3
SHA
4
5-BIT
ADC
5-BIT
DAC
4-BIT
ADC
4-BIT
DAC
3-BIT
ADC
3-BIT
DAC
3-BIT
ADC
a
4.41
LATENCY (PIPELINE DELAY)
OF AD9220/9221/9223 ADC
ANALOG
INPUT
SAMPLING
CLOCK
OUTPUT
DATA
DATA N - 3 DATA N - 2 DATA N - 1 DATA N
N
N + 1 N + 2 N + 3
39
AD9220, AD9221, AD9223
CMOS 12-BIT ADCs KEY SPECIFICATIONS
n n Family Members:
AD9221 (1.25MSPS), AD9223 (3MSPS), AD9220 (10MSPS)
n n Power Dissipation: 60, 100, 250mW, Respectively
n n FPBW: 25, 40, 60MHz, Respectively
n n Effective Input Noise: 0.1LSB rms (Span = 5V)
n n SINAD: 71dB
n n SFDR: 88dBc
n n On-Chip Reference
n n Differential Non-Linearity: 0.3LSB
n n Single +5V Supply
n n 28-Pin SOIC Package
a 4.42
Bi t -P er -St a ge (Ser i a l, or Ri p p le) ADCs
Var ious ar chit ect ur es exist for per for ming A/D conver sion using one st age per bit . In
fact , a mult ist age subr anging ADC wit h one bit per st age and no er r or cor r ect ion is
one for m. Figur e 4.43 shows t he over all concept . The SHA holds t he input signal
const ant dur ing t he conver sion cycle. Ther e ar e N st ages, each of which have a bit
out put and a r esidue out put . The r esidue out put of one st age is t he input t o t he
next . The last bit is det ect ed wit h a single compar at or as shown.
40
4.43
BIT-PER-STAGE, SERIAL, OR RIPPLE ADC
a
ANALOG
INPUT
SHA
STAGE
1
STAGE
2
DECODE LOGIC AND OUTPUT REGISTERS
+
-
BIT 1
MSB
BIT 2
V
REF
N
R1 R2
STAGE
N-1
BIT N-1
BIT N
LSB
The basic st age for per for ming a single binar y bit conver sion is shown in Figur e
4.44. It consist s of a gain-of-t wo amplifier , a compar at or , and a 1-bit DAC. The
compar at or det ect s t he zer o-cr ossing of t he input and is t he binar y bit out put for
t hat st age. The compar at or also swit ches a 1-bit DAC whose out put is summed wit h
t he out put of t he gain-of-t wo amplifier . The r esult ing r esidue out put is t hen applied
t o t he next st age.
41
a
4.44
SINGLE-STAGE OF BINARY ADC
INPUT
INPUT
RESIDUE
+V
R
+V
R
-V
R
-V
R
0
0
RESIDUE
+V
R
-V
R
G = 2
+
-

BIT OUTPUT
(BINARY CODE)
SWITCH POSITION
SHOWN FOR
NEGATIVE INPUT
A simplified 3-bit ser ial-binar y ADC is shown in Figur e 4.45, and t he r esidue
out put s ar e shown in Figur e 4.46. Each r esidue out put signal has discont inuit ies
which cor r espond t o t he point wher e t he compar at or changes st at e and causes t he
DAC t o swit ch. The fundament al pr oblem wit h t his ar chit ect ur e is t he discont inuit y
in t he r esidue out put wavefor ms. Adequat e set t ling t ime must be allowed for t hese
t r ansient s t o pr opagat e t hr ough all t he st ages and set t le at t he final compar at or
input . The pr ospect s of making t his ar chit ect ur e oper at e at high speed ar e t her efor e
dismal.
42
4.45
3-BIT SERIAL ADC WITH BINARY OUTPUT
a
ANALOG
INPUT
SHA
STAGE
1
STAGE
2
OUTPUT REGISTER
+
-
BIT 1 BIT 2
BIT 3
V
R
3
R1 R2
a
INPUT AND RESIDUE WAVEFORMS OF
3-BIT BINARY RIPPLE ADC
4.46
INPUT
R1
R2
BINARY
CODE
-V
R
-V
R
-V
R
+V
R
+V
R
+V
R
000 001 010 011 100 101 110 111
0
0
0
A much bet t er bit -per -st age ar chit ect ur e was developed by F.D. Waldhauer
(Refer ence 7) based on absolut e value amplifier s (magnit ude amplifier s, or simply
MagAmps). This scheme has oft en been r efer r ed t o as serial-Gray (since t he out put
coding is in Gr ay code), or folding conver t er (Refer ences 8, 9, 10). The basic st age is
43
shown funct ionally in Figur e 4.47. The compar at or det ect s t he polar it y of t he input
signal and pr ovides t he Gr ay bit out put for t he st age. It also det er mines whet her t he
over all st age gain is +2 or 2. The r efer ence volt age V
R
is summed wit h t he swit ch
out put t o gener at e t he r esidue signal which is applied t o t he next st age. The
t r ansfer funct ion for t he folding st age is also shown in Figur e 4.47.
a
4.47
MagAmp STAGE FUNCTIONAL EQUIVALENT CIRCUIT
INPUT
G = +2
INPUT
RESIDUE
+V
R
+V
R
-V
R
-V
R
0
0
RESIDUE
V
R
+
-
BIT OUTPUT
(GRAY CODE)
G = -2

SWITCH POSITION
SHOWN FOR
NEGATIVE INPUT
A 3-bit MagAmp folding ADC is shown in Figur e 4.48, and t he cor r esponding
r esidue wavefor ms in Figur e 4.49. Not ice t hat t her e is no abr upt t r ansit ion in any of
t he folding st age out put wavefor ms.
44
4.48
3-BIT MagAmp (FOLDING) ADC BLOCK DIAGRAM
a
ANALOG
INPUT
SHA
MAGAMP
1
MAGAMP
2
GRAY-TO-BINARY CONVERTER
OUTPUT REGISTER
GRAY CODE REGISTER
+
-
BIT 1 BIT 2
BIT 3
V
R
3
3
3
a
INPUT AND RESIDUE WAVEFORMS
FOR 3-BIT MagAmp ADC
4.49
INPUT
R1
R2
GRAY
CODE
-V
R
-V
R
-V
R
+V
R
+V
R
+V
R
000 001 011 010 110 111 101 100
0
0
0
The key t o oper at ing t his ar chit ect ur e at high speeds is t he folding st age. Ear ly
designs (see Refer ences 7, 8, 9) used discr et e op amps wit h diodes inside t he
feedback loop t o gener at e t he folding t r ansfer funct ion. Moder n IC cir cuit designs
implement t he t r ansfer funct ion using cur r ent -st eer ing open-loop gain t echniques
45
which can be made t o oper at e much fast er . Fully differ ent ial st ages (including t he
SHA) also pr ovide speed, lower dist or t ion, and yield 8-bit accur at e folding st ages
wit h no r equir ement for t hin film r esist or laser t r imming.
An example of a fully differ ent ial gain-of-t wo MagAmp folding st age is shown in
Figur e 4.50 (see Refer ences 11, 12, 13). The differ ent ial input signal is applied t o t he
degener at ed-emit t er differ ent ial pair Q1,Q2 and t he compar at or . The differ ent ial
input volt age is conver t ed int o a differ ent ial cur r ent which flows in t he collect or s of
Q1, Q2. If +IN is gr eat er t han IN, cascode-connect ed t r ansist or s Q3, Q6 ar e on, and
Q4, Q6 ar e off. The differ ent ial signal cur r ent s t her efor e flow t hr ough t he collect or s
of Q3, Q6 int o level-shift ing t r ansist or s Q7, Q8 and int o t he out put load r esist or s,
developing t he differ ent ial out put volt age bet ween +OUT and OUT. The over all
differ ent ial volt age gain of t he cir cuit is t wo.
If +IN is less t han IN (negat ive differ ent ial input volt age), t he compar at or changes
st age and t ur ns Q4, Q5 on and Q3, Q6 off. The differ ent ial signal cur r ent s flow fr om
Q5 t o Q7 and fr om Q4 t o Q8, t her eby maint aining t he same r elat ive polar it y at t he
differ ent ial out put as for a posit ive differ ent ial input volt age. The r equir ed offset
volt age is developed by adding a cur r ent I
OFF
t o t he emit t er cur r ent of Q7 and
subt r act ing it fr om t he emit t er cur r ent of Q8.
The differ ent ial r esidue out put volt age of t he st age dr ives t he next st age input , and
t he compar at or out put r epr esent s t he Gr ay code out put for t he st age.
V
BIAS
Q4
Q7
a 4.50
CIRCUIT DETAILS OF MagAmp STAGE
+OUT
+5V
Q8
-OUT
R
-IN
+IN
R
R
I I
Q6
Q5 Q3
Q1
GRAY GRAY
Q2
R
i+ i-
V
BIAS
2I + I
OFF
2I - I
OFF
+
-
The MagAmp ar chit ect ur e can be ext ended t o sampling r at es pr eviously dominat ed
by flash conver t er s. The AD9059 8-bit , 60MSPS dual ADC is shown in Figur e 4.51.
The fir st five bit s (Gr ay code) ar e der ived fr om five differ ent ial MagAmp st ages. The
differ ent ial r esidue out put of t he fift h MagAmp st age dr ives a 3-bit flash conver t er ,
r at her t han a single compar at or . The Gr ay-code out put of t he five MagAmps and t he
46
binar y-code out put of t he 3-bit flash ar e lat ched, all conver t ed int o binar y, and
lat ched again in t he out put dat a r egist er . Key specificat ions for t he AD9059 ar e
shown in Figur e 4.52.
4.51
AD9059 DUAL 8-BIT, 60MSPS ADC FUNCTIONAL DIAGRAM
a
8
8
8
ANALOG
INPUT
SHA
MAGAMP
1
MAGAMP
2
MAGAMP
3
MAGAMP
4
MAGAMP
5
3-BIT
FLASH
ADC
BIT
1
GRAY
BIT
2
GRAY
BIT
3
GRAY
BIT
4
GRAY
BIT
5
GRAY
3
GRAY-TO-BINARY CONVERTER
OUTPUT REGISTER
BINARY
DIFFERENTIAL
OUTPUTS ON
BITS 1 - 5
REGISTER
AD9059 DUAL 8-BIT, 60MSPS ADC
KEY SPECIFICATIONS
n n Input Range: 1V p-p, Vcm = +2.5V
n n Input Impedance: 200k || 5pF
n n ENOB: 7.3 @ 10.3MHz Input
n n On-Chip Reference
n n Power Supply: Single +5V Supply (+5 or +3V Digital)
n n Power Dissipation: 375mW (Power Down: 10mW)
n n Package: 28-lead SSOP
n n Ideal for Quadrature Demodulation in DBS
Set-Top Boxes
a 4.52
47
48
REFERENCES
1. Act i ve a n d P a ssi ve Elect r i ca l Wa ve Fi lt er Ca t a log, Vol. 34, TTE,
Incor por at ed, 2251 Bar r y Avenue, Los Angeles, CA 90064.
2. W. R. Bennet t , Spect r a of Quant ized Signals, Bell Syst em Tech n i ca l
J ou r n a l, No. 27, J uly 1948, pp. 446-472.
3. St eve Ruscak and Lar r y Singer , Using Histogram Techniques to
Measure A/ D Converter Noise, An a log Di a logu e, Vol. 29-2, 1995.
4. M.J . Tant , Th e Wh i t e Noi se Book , Mar coni Inst r ument s, J uly 1974.
5. G.A. Gr ay and G.W. Zeoli, Quantization and S aturation Noise due
to A/ D Conversion, I EEE Tr a n s. Aer osp a ce a n d Elect r on i c
Syst ems, J an. 1971, pp. 222-223.
6. Chuck Lane, A 10-bit 60MS PS Flash ADC, P r oceed i n gs of t h e 1989
Bi p ola r Ci r cu i t s a n d Tech n ology Meet i n g, IEEE Cat alog No.
89CH2771-4, Sept ember 1989, pp. 44-47.
7. F.D. Waldhauer , Analog to Digital Converter, U.S. P a t en t
3-187-325, 1965.
8. J .O. Edson and H.H. Henning, Broadband Codecs for an Experimental
224Mb/ s PCM Terminal, Bell Syst em Tech n i ca l J ou r n a l, 44,
November 1965, pp. 1887-1940.
9. J .S. Ma yo, Exper i m en t a l 224Mb/s PCM Ter m i n a l s, Bell Syst em
Tech n i ca l J ou r n a l, 44, November 1965, pp. 1813-1941.
10. Her mann Schmid, Elect r on i c An a log/Di gi t a l Con ver si on s,
Van Nost r and Reinhold Company, New Yor k, 1970.
11. Car l Mor eland, An 8-bit 150MS PS S erial ADC, 1995 I SSCC Di gest
of Tech n i ca l P a p er s, Vol. 38, p. 272.
12. Roy Gosser and Fr ank Mur den, A 12-bit 50MS PS Two-S tage A/ D
Converter, 1995 I SSCC Di gest of Tech n i ca l P a p er s, p. 278.
13. Car l Mor eland, An An a log-t o-Di gi t a l Con ver t er Usi n g Ser i a l-
Ri p p le Ar ch i t ect u r e, Mast er s' Thesis, Flor ida St at e Univer sit y
College of Engineer ing, Depar t ment of Elect r ical Engineer ing, 1995.
14. P r a ct i ca l An a log Desi gn Tech n i qu es, Analog Devices, 1995, Chapt er
4, 5, and 8.
15. Li n ea r Desi gn Semi n a r , Analog Devices, 1995, Chapt er 4, 5.
16. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 12, 13,
15,16.
49
17. Amp li fi er Ap p li ca t i on s Gu i d e, Analog Devices, 1992, Chapt er 7.
18. Walt Kest er , Drive Circuitry is Critical to High-S peed S ampling ADCs,
Elect r on i c Desi gn Sp eci a l An a log I ssu e, Nov. 7, 1994, pp. 43-50.
19. Walt Kest er , Basic Characteristics Distinguish S ampling A/ D Converters,
EDN, Sept . 3, 1992, pp. 135-144.
20. Walt Kest er , Peripheral Circuits Can Make or Break S ampling ADC
S ystems, EDN, Oct . 1, 1992, pp. 97-105.
21. Walt Kest er , Layout, Grounding, and Filtering Complete S ampling
ADC S ystem, EDN, Oct . 15, 1992, pp. 127-134.
22. Rober t A. Wit t e, Distortion Measurements Using a S pectrum Analyzer,
RF Desi gn , Sept ember , 1992, pp. 75-84.
23. Walt Kest er , Confused About Amplifier Distortion S pecs?, An a log
Di a logu e, 27-1, 1993, pp. 27-29.
24. Syst em Ap p li ca t i on s Gu i d e, Analog Devices, 1993, Chapt er 16.
25. Fr eder ick J . Har r is, On the Use of Windows for Harmonic Analysis
with the Discrete Fourier Transform, I EEE P r oceed i n gs, Vol. 66, No. 1,
J an. 1978, pp. 51-83.
26. J oey Doer nber g, Hae-Seung Lee, David A. Hodges, Full S peed Testing
of A/ D Converters, I EEE J ou r n a l of Soli d St a t e Ci r cu i t s, Vol. SC-19,
No. 6, Dec. 1984, pp. 820-827.
27. Br endan Coleman, Pat Meehan, J ohn Reidy and Pat Weeks, Coherent
S ampling Helps When S pecifying DS P A/ D Converters, EDN, Oct ober 15,
1987, pp. 145-152.
28. Rober t W. Ramier ez, Th e F F T: F u n d a men t a ls a n d Con cep t s,
Pr ent ice-Hall, 1985.
29. R. B. Blackman and J . W. Tukey, Th e Mea su r emen t of P ower
Sp e ct r a , Dover Publicat ions, New Yor k, 1958.
30. J ames J . Colot t i, Digital Dynamic Analysis of A/ D Conversion
S ystems Through Evaluation S oftware Based on FFT/ DFT Analysis,
RF Exp o Ea st 1987 P r oceed i n gs, Car diff Publishing Co., pp. 245-272.
31. HP J ou r n a l, Nov. 1982, Vol. 33, No. 11.
32. HP P r od u ct Not e 5180A-2.
33. HP J ou r n a l, Apr il 1988, Vol. 39, No. 2.
34. HP J ou r n a l, J une 1988, Vol. 39, No. 3.
50
35. Dan Sheingold, Edit or , An a log-t o-Di gi t a l Con ver si on Ha n d book ,
Th i r d Ed i t i on , Pr ent ice-Hall, 1986.
36. Lawr ence Rabiner and Ber nar d Gold, Th eor y a n d Ap p li ca t i on of
Di gi t a l Si gn a l P r ocessi n g, Pr ent ice-Hall, 1975.
37. Mat t hew Mahoney, DSP -Ba sed Test i n g of An a log a n d Mi xed -Si gn a l
Ci r cu i t s, IEEE Comput er Societ y Pr ess, Washingt on, D.C., 1987.
38. I EEE Tr i a l-Use St a n d a r d for Di gi t i zi n g Wa vefor m Recor d er s,
No. 1057-1988.
39. Richar d J . Higgins, Di gi t a l Si gn a l P r ocessi n g i n VSLI , Pr ent ice-Hall,
1990.
40. M. S. Ghausi and K. R. Laker , Mod er n Fi lt er Desi gn : Act i ve RC a n d
Swi t ch e d Ca p a ci t or s, Pr ent ice Hall, 1981.
41. Mat hcad 4.0 soft war e package available fr om Mat hSoft , Inc.,
201 Br oadway, Cambr idge MA, 02139.
42. Howar d E. Hilt on, A 10MHz Analog-to-Digital Converter with 110dB
Linearity, H.P . J ou r n a l, Oct ober 1993, pp. 105-112.
1
SECTI ON 5
HI GH SP EED ADC AP P LI CATI ONS
Wa l t Kest er , Br a d Br a n n on , Pa u l Hen d r i ck s
DRI VI NG ADC I NP UTS FOR LOW DI STORTI ON AND WI DE
DYNAMI C RANGE
In or der t o achieve wide dynamic r ange in high speed ADC applicat ions, car eful
at t ent ion must be given t o t he analog int er face. Many ADCs ar e designed so t hat
analog signals can be int er faced dir ect ly t o t heir input s wit hout t he necessit y of a
dr ive amplifier . This is especially t r ue in ADCs such as t he AD9220/21/23 family
and t he AD9042, wher e even a low dist or t ion dr ive amplifier may r esult in some
degr adat ion in AC per for mance. If a buffer amplifier is r equir ed, it must be car efully
select ed so t hat it s dist or t ion and noise per for mance is bet t er t han t hat of t he ADC.
Single-supply ADCs gener ally yield opt imum AC per for mance when t he common-
mode input volt age is cent er ed bet ween t he supply r ails (alt hough t he opt imum
common-mode volt age may be skewed slight ly in eit her dir ect ion about t his point
depending upon t he par t icular design). This also eases t he dr ive r equir ement on t he
input buffer amplifier (if r equir ed) since even "r ail-t o-r ail" out put op amps give best
dist or t ion per for mance if t heir out put is cent er ed about mid-supply, and t he peak
signals ar e kept at least 1V fr om eit her r ail.
Typical high speed single-supply ADC peak-t o-peak input volt age r anges may var y
fr om about 0.5V t o 5V, but in most cases, 1V t o 2V peak-t o-peak r epr esent s t he
opt imum t r adeoff bet ween noise and dist or t ion per for mance.
In single-supply applicat ions r equir ing DC coupling, car eful at t ent ion must be given
t o t he input and out put common-mode r ange of t he dr iving amplifier . Level shift ing
is oft en r equir ed in or der t o cent er a gr ound-r efer enced signal wit hin t he allowable
common-mode input r ange of t he ADC.
Small RF t r ansfor mer s ar e quit e useful in AC coupled applicat ions, especially if t he
ADC has differ ent ial input s. Significant impr ovement in even-or der dist or t ion
pr oduct s and common-mode noise r eject ion may be r ealized, depending upon t he
char act er ist ics of t he ADC.
An under st anding of t he input st r uct ur e of t he ADC is t her efor e necessar y in or der
t o pr oper ly design t he analog int er face cir cuit r y. ADCs designed on CMOS pr ocesses
t ypically connect t he sample-and-hold swit ches dir ect ly t o t he analog input , t her eby
gener at ing t r ansient cur r ent pulses. These t r ansient s may significant ly degr ade
per for mance if t he set t ling t ime of t he op amp is not sufficient ly fast . On t he ot her
hand, ADCs designed on bipolar pr ocesses may pr esent a r elat ively benign load t o
t he dr ive amplifier wit h minimal t r ansient cur r ent s.
The dat a sheet for t he ADC is t he pr ime sour ce an engineer should use in designing
t he int er face cir cuit s. It should cont ain r ecommended int er face cir cuit s and spell out
r elevant t r adeoffs. However , no dat a sheet can subst it ut e for a fundament al
under st anding of what 's inside t he ADC.
2
HIGH SPEED ADC INPUT CONSIDERATIONS
n n Selection of Drive Amplifier (Only if Needed!)
n n Single Supply Implications
n n Input Range (Span): Typically 1V to 2V peak-to-peak
for best distortion / noise tradeoff
n n Input Common-Mode Range:
V
s
/ 2 (Nominally) for Single Supply ADCs
n n Differential vs. Single-Ended
n n AC Coupling Using Transformers
n n Input Transient Currents
a 5.1
Swi t ch ed -Ca p a ci t or I n p u t ADCs
The AD9220/21/23-ser ies of ADCs ar e excellent examples of t he pr ogr ess t hat has
been made in ut ilizing low-cost CMOS pr ocesses t o achieve a high level of
per for mance. A funct ional block diagr am is shown in Figur e 5.2. This family of
ADCs offer s sampling r at es of 1.25MSPS (AD9221), 3MSPS (AD9223), and 10MSPS
(AD9220) at power dissipat ions of 60, 100, and 250mW r espect ively. Key
specificat ions for t he family of ADCs ar e given in Figur e 5.3. The devices cont ain an
on-chip r efer ence volt age which allows t he full scale span t o be set at 2V or 5V peak-
t o-peak (full scale spans bet ween 2V and 5V can be set by adding t wo ext er nal gain
set t ing r esist or s).
3
5.2
AD922X-SERIES ADC FUNCTIONAL DIAGRAM
a
VINA
CAPT
CAPB
SENSE
OTR
BIT 1
(MSB)
BIT 12
(LSB)
VREF
DVSS AVSS CML
AD9221/23/20
SHA
DIGITAL CORRECTION LOGIC
OUTPUT BUFFERS
VINB
1V
REFCOM
5
5
4
4
3
3 3
12
DVDD AVDD CLK
MODE
SELECT
MDAC3
GAIN = 4
MDAC2
GAIN = 8
MDAC1
GAIN = 16
A/D A/D A/D A/D
AD9220, AD9221, AD9223
CMOS 12-BIT ADCs KEY SPECIFICATIONS
n n Family Members:
AD9221 (1.25MSPS), AD9223 (3MSPS), AD9220 (10MSPS)
n n Power Dissipation: 60, 100, 250mW, Respectively
n n FPBW: 25, 40, 60MHz, Respectively
n n Effective Input Noise: 0.1LSB rms (Span = 5V)
n n SINAD: 71dB
n n SFDR: 88dBc
n n On-Chip Reference
n n Differential Non-Linearity: 0.3LSB
n n Single +5V Supply
n n 28-Pin SOIC Package
4
a 5.3
The input cir cuit of t he AD9220/21/23-ser ies of CMOS ADCs cont ains t he
differ ent ial sample-and-hold as shown in Figur e 5.4. The swit ches ar e shown in t he
t r ack mode. They open and close at t he sampling fr equency. The 16pF capacit or s
r epr esent t he effect ive capacit ance of swit ches S1 and S2 plus t he st r ay input
capacit ance. The C
s
capacit or s (4pF) ar e t he sampling capacit or s, and t he C
H
capacit or s ar e t he hold capacit or s. Alt hough t he input cir cuit is complet ely
differ ent ial, t he ADC can be dr iven eit her single-ended or differ ent ial. Opt imum
SFDR, however , is obt ained using a differ ent ial t r ansfor mer dr ive.
5.4
SIMPLIFIED INPUT CIRCUIT OF AD922X ADC FAMILY
V
INB
a
+
-
SWITCHES SHOWN IN TRACK MODE
A
V
INA
C
P
16pF
C
P
16pF
S1
S2
S3
S4
S5
S7
S6
C
S
4pF
C
S
4pF
C
H
4pF
C
H
4pF
In t he t r ack mode, t he differ ent ial input volt age is applied t o t he C
s
capacit or s.
When t he cir cuit ent er s t he hold mode, t he volt age acr oss t he sampling capacit or s is
t r ansfer r ed t o t he C
H
hold capacit or s and buffer ed by t he amplifier A. (The swit ches
ar e cont r olled by t he appr opr iat e phases of t he sampling clock). When t he SHA
r et ur ns t o t he t r ack mode, t he input sour ce must char ge or dischar ge t he volt age
st or ed on C
s
t o t he new input volt age. This act ion of char ging and dischar ging C
s
,
aver aged over a per iod of t ime and for a given sampling fr equency fs, makes t he
input impedance appear t o have a benign r esist ive component . However , if t his
act ion is analyzed wit hin a sampling per iod (1/f
s
), t he input impedance is dynamic,
and hence cer t ain pr ecaut ions on t he input dr ive sour ce should be obser ved.
The r esist ive component t o t he input impedance can be comput ed by calculat ing t he
aver age char ge t hat is dr awn by C
H
fr om t he input dr ive sour ce. It can be shown
t hat if C
s
is allowed t o fully char ge t o t he input volt age befor e swit ches S1 and S2
ar e opened t hat t he aver age cur r ent int o t he input is t he same as if t her e wer e a
5
r esist or equal t o 1/(C
s
f
s
) connect ed bet ween t he input s. Since C
s
is only a few
picofar ads, t his r esist ive component is t ypically gr eat er t han sever al k for an f
s
=
10MSPS.
If one consider s t he SHA's input impedance over a sampling per iod, it appear s as a
dynamic load t o t he input dr ive sour ce. When t he SHA r et ur ns t o t he t r ack mode,
t he input sour ce should ideally pr ovide t he char ging cur r ent t hr ough t he R
on
of
swit ches S1 and S2 in an exponent ial manner . The r equir ement of exponent ial
char ging means t hat t he sour ce impedance should be bot h low and r esist ive up t o
and beyond t he sampling fr equency.
The out put impedance of an op amp can be modeled as a ser ies induct or and
r esist or . When a capacit ive load is swit ched ont o t he out put of t he op amp, t he
out put will moment ar ily change due t o it s effect ive high fr equency out put
impedance. As t he out put r ecover s, r inging may occur . To r emedy t his sit uat ion, a
ser ies r esist or can be inser t ed bet ween t he op amp and t he SHA input . The opt imum
value of t his r esist or is dependent on sever al fact or s including t he sampling
fr equency and t he op amp select ed, but in most applicat ions, a 30 t o 50 r esist or is
opt imum.
The input volt age span of t he AD922X-family is set by pin-st r ap opt ions using t he
int er nal volt age r efer ence (see Figur e 5.5). The common-mode volt age can be set by
eit her pin st r ap or applying t he common-mode volt age t o t he VINB pin. Tr adeoffs
can be made bet ween noise and dist or t ion per for mance. Maximum input r ange
allowable is 5V peak-t o-peak, in which case, t he common-mode input volt age must
be one-half t he supply volt age, or +2.5V. The minimum input r ange is 2V peak-t o-
peak, in which case t he common-mode input volt age can be set fr om +1V t o +4V. For
best DC linear it y and maximum signal-t o-noise r at io, t he ADC should be oper at ed
wit h an input signal of 5V peak-t o-peak. However , for best high fr equency noise and
dist or t ion per for mance, 2V peak-t o-peak wit h a common-mode volt age of +2.5V is
pr efer r ed. This is because t he CMOS FET on-r esist ance is a minimum at t his
volt age, and t he non-linear it y caused by t he signal-dependence of R
on
(R
on
modulat ion effect ) is also minimal.
AD922X ADC INPUT VOLTAGE RANGE OPTIONS
SINGLE-ENDED INPUT
Input Signal Range
(Volts)
Peak-to-Peak Signal
(Volts)
Common-Mode Voltage
(Volts)
0 to +2 2 +1
0 to +5 5 +2.5
+1.5 to +3.5 2 +2.5
DIFFERENTIAL INPUT
Input Signal Range Peak-to-Peak Signal Common-Mode Voltage
6
(Volts) Differential (Volts) (Volts)
+2 to +3 2 +2.5
+1.25 to +3.75 5 +2.5
a 5.5
Figur e 5.6 shows t he THD per for mance of t he AD9220 for a 2V peak-t o-peak input
signal span and common-mode input volt age of 2.5V and 1V. The dat a was t aken
wit h a single-ended dr ive. Not e t hat t he per for mance is significant ly bet t er for V
cm
= +2.5V.
a
AD9220 THD VS. INPUT FREQUENCY: SINGLE-ENDED DRIVE
2V p-p INPUT, V
cm
= +1V AND V
cm
= +2.5V, f
s
= 10MSPS
5.6
THD
(dBc)
INPUT FREQUENCY (MHz)
V
cm
= +1V
V
cm
= +2.5V
50
60
70
80
90
0.1 0.2 0.5 1 2 5 10
A simple single-ended cir cuit for AC coupling int o t he input s of t he AD9220-family is
shown in Figur e 5.7. Not e t hat t he common-mode input volt age is set for +2.5V by
t he 4.99k r esist or s. The input impedance is also balanced for opt imum dist or t ion
per for mance.
7
5.7
SINGLE-ENDED AC-COUPLED
DRIVE CIRCUIT FOR AD922X ADC
33
+5V
a
4.99k
0.1 F
33
4.99k
4.99k
4.99k
10 F
+5V
0.1 F
10 F
51.1
INPUT
+
+5V
AD922X
V
INA
V
INB
+
+2.5V
If t he input t o t he ADC is coming fr om a long coaxial cable r un, it may be desir able
t o buffer t he t r ansient cur r ent s at t he ADC input s fr om t he cable t o pr event
pr oblems r esult ing fr om r eflect ions, especially if t he cable is not sour ce-t er minat ed.
The cir cuit shown in Figur e 5.8 uses t he low dist or t ion AD8011 op amp as a buffer
which can opt ionally pr ovide signal gain. In all cases, t he feedback r esist or should be
fixed at 1k for best op amp per for mance, since t he AD8011 is a cur r ent -feedback
t ype. In t his t ype of ar r angement , car e must be t aken t o obser ve t he allowable input
and out put r ange of t he op amp. The AD8011 input common-mode r ange (oper at ing
on a single +5V supply) is fr om +1.5 t o +3.5V, and it s out put +1V t o +4V. The ADC
should be oper at ed wit h a 2V peak-t o-peak input r ange. The 33 ser ies r esist or is
r equir ed t o isolat e t he out put of t he AD8011 fr om t he effect ive input capacit ance of
t he ADC. The value was empir ically det er mined t o yield t he best high-fr equency
SINAD.
8
5.8
BUFFERED AC-COUPLED INPUT DRIVE
CIRCUIT FOR AD922X ADC
+5V
a
4.99k
33
4.99k
4.99k 10 F
+5V
0.1 F
10 F
51.1
INPUT
+
+5V
AD922X
V
INA
V
INB
+
-
AD8011
+5V
4.99k
0.1 F
1k
0.1 F
1k
33
10 F
+
2V
p-p
1V
p-p
+2.5V
Dir ect coupling of gr ound-r efer enced signals using a single supply r equir es t he use of
an op amp wit h an accept able common-mode input volt age, such as t he AD8041
(input can go t o 200mV below gr ound). The cir cuit shown in Figur e 5.9 level shift s
t he gr ound-r efer enced bipolar input signal t o a common-mode volt age of +2.5V at
t he ADC input . The common-mode bias volt age of +2.5V is developed dir ect ly fr om
an AD780 r efer ence, and t he AD8041 common-mode volt age of +1.25V is der ived
wit h a simple divider .
9
5.9
DIRECT-COUPLED LEVEL SHIFTER
FOR DRIVING AD922X ADC INPUT
a
10 F
+5V
52.3
INPUT
+
+5V
AD922X
V
INA
V
INB
+
-
AD8041
+5V
0.1 F
1k
0.1 F
1k
33
AD780
2.5V
REF.
1k
1V
+1.25V
+2.5V
1k
10 F
33
+
+2.5V 1V

Tr ansfor mer coupling pr ovides t he best CMR and t he lowest dist or t ion. Figur e 5.10
shows t he suggest ed cir cuit . The t r ansfor mer is a Mini-Cir cuit s RF t r ansfor mer ,
model #T4-6T which has an impedance r at io of four (t ur ns r at io of 2). The schemat ic
assumes t hat t he signal sour ce has a 50 sour ce impedance. The 1:4 impedance
r at io r equir es t he 200 secondar y t er minat ion for opt imum power t r ansfer and
VSWR. The Mini-Cir cuit s T4-6T has a 1dB bandwidt h fr om 100kHz t o 100MHz. The
cent er t ap of t he t r ansfor mer pr ovides a convenient means of level shift ing t he input
signal t o t he opt imum common-mode volt age. The AD922X CML pin is used t o
pr ovide t he +2.5 common-mode volt age.
10
5.10
TRANSFORMER COUPLING INTO AD922X ADC
a
+5V
AD922X
V
INA
V
INB
0.1 F
+2.5V
33
CML
33
200
1:2
RF TRANSFORMER:
MINI-CIRCUITS T4-6T
2V
p-p
49.9
Tr ansfor mer s wit h ot her t ur ns r at ios may also be select ed t o opt imize t he
per for mance for a given applicat ion. For example, a given input signal sour ce or
amplifier may r ealize an impr ovement in dist or t ion per for mance at r educed out put
power levels and signal swings. Hence, select ing a t r ansfor mer wit h a higher
impedance r at io (i.e. Mini-Cir cuit s #T16-6T wit h a 1:16 impedance r at io, t ur ns r at io
1:4) effect ively "st eps up" t he signal level t hus r educing t he dr iving r equir ement s of
t he signal sour ce.
Not e t he 33 ser ies r esist or s inser t ed bet ween t he t r ansfor mer secondar y and t he
ADC input . These values wer e specifically select ed t o opt imize bot h t he SFDR and
t he SNR per for mance of t he ADC. They also pr ovide isolat ion fr om t r ansient s at t he
ADC input s. Tr ansient s cur r ent s ar e appr oximat ely equal on t he VINA and VINB
input s, so t hey ar e isolat ed fr om t he pr imar y winding of t he t r ansfor mer by t he
t r ansfor mer 's common-mode r eject ion.
Tr ansfor mer coupling using a common-mode volt age of +2.5V pr ovides t he
maximum SFDR when dr iving t he AD922X-ser ies. By dr iving t he ADC
differ ent ially, even-or der har monics ar e r educed compar ed wit h t he single-ended
cir cuit . Figur e 5.11 shows a plot of SFDR and SNR for t he t r ansfor mer -coupled
differ ent ial dr ive cir cuit using 2V p-p and 5V p-p input s and a common-mode volt age
of +2.5V. Not e t hat t he SFDR is gr eat er t han 80dBc for input signals up t o full scale
wit h a 5MHz input signal.
11
5.11
AD9220 SFDR AND SNR FOR 5Vp-p AND 2Vp-p INPUT:
V
cm
= +2.5V, 5MHz INPUT, f
s
= 10MSPS
TRANSFORMER-COUPLED DIFFERENTIAL DRIVE
a
INPUT AMPLITUDE - dBFS
90
50
20
-50 0 -40 -30 -20 -10
80
70
40
30
60
SNR - 5.0
Vp-p
SFDR - 5.0
Vp-p
SFDR - 2.0
Vp-p
SNR - 2.0
Vp-p
S
N
R

-

d
B

A
N
D

S
F
D
R

-

d
B
Figur e 5.11 also shows differ ences bet ween t he SFDR and SNR per for mance for 2V
p-p and 5V p-p input s. Not e t hat t he SNR wit h a 5V p-p input is appr oximat ely 2dB
t o 3dB bet t er t han t hat for a 2V p-p input because of t he addit ional dynamic r ange
pr ovided by t he lar ger input r ange. Also, t he SFDR per for mance using a 5V p-p
input is 3 t o 5dB bet t er for signals bet ween about 6dBFS and 36dBFS. This
impr ovement in SNR and SFDR for t he 5V p-p input r ange may be advant ageous in
syst ems which r equir e mor e t han 6dB headr oom t o minimize clipping of t he ADC.
Dr i vi n g Bi p ola r I n p u t ADCs
Bipolar t echnology is t ypically used for ext r emely high per for mance ADCs wit h wide
dynamic r ange and high sampling r at es such as t he AD9042. The AD9042 is a st at e-
of-t he-ar t 12-bit , 41MSPS t wo st age subr anging ADC consist ing of a 6-bit coar se
ADC and a 7-bit r esidue ADC wit h one bit of over lap t o cor r ect for any DNL, INL,
gain or offset er r or s of t he coar se ADC, and offset er r or s in t he r esidue pat h. A block
diagr am is shown in Figur e 5.12 and key specificat ions in Figur e 5.13. A pr opr iet ar y
gr ay-code ar chit ect ur e is used t o implement t he t wo int er nal ADCs. The gain
alignment s of t he coar se and r esidue, likewise t he subt r act ion DAC, r ely on t he
st at ist ical mat ching of t he devices on t he pr ocess. As a r esult , 12-bit int egr al and
differ ent ial linear it y is obt ained wit hout laser t r im. The int er nal DAC consist s of
126 int er digit at ed cur r ent sour ces. Also on t he DAC r efer ence, t her e ar e an
addit ional 20 int er digit at ed cur r ent sour ces t o set t he coar se gain, r esidue gain, and
full scale gain. The int er digit izat ion r emoves t he r equir ement for laser t r im. The
AD9042 is fabr icat ed on a high speed dielect r ically isolat ed complement ar y bipolar
pr ocess. The t ot al power dissipat ion is only 575mW when oper at ing on a single +5V
supply.
12
a
AD9042 12-BIT, 41MSPS ADC BLOCK DIAGRAM
5.12
+
-
ANALOG
INPUT
7
12
ERROR CORRECTION LOGIC
OUTPUT REGISTERS
SHA
1
SHA
2
6-BIT
ADC
6-BIT
DAC
7-BIT
ADC
SHA
3
GAIN
12
BUFFER
REGISTER
6
6
AD9042 12-BIT, 41MSPS ADC KEY SPECIFICATIONS
n n Input Range: 1V peak-to-peak, V
cm
= +2.4V
n n Input Impedance: 250 to V
cm
n n Effective Input Noise: 0.33LSBs rms
n n SFDR at 20MHz Input: 80dB
n n SINAD at 20MHz Input = 66dB
n n Digital Outputs: TTL Compatible
n n Power Supply: Single +5V
n n Power Dissipation: 575mW
n n Fabricated on High Speed Dielectrically Isolated
Complementary Bipolar Process
a 5.13
The out st anding per for mance of t he AD9042 is par t ly due t o t he use of differ ent ial
t echniques t hr oughout t he device. The low dist or t ion input amplifier conver t s t he
single-ended input signal int o a differ ent ial one. If maximum SFDR per for mance is
13
desir ed, t he signal sour ce should be coupled dir ect ly int o t he input of t he AD9042
wit hout using a buffer amplifier . Figur e 5.14 shows a met hod using capacit ive
coupling. Tr ansfor mer coupling can also be used if desir ed.
5.14
INPUT STRUCTURE OF AD9042 ADC IS
DESIGNED TO BE DRIVEN DIRECTLY FROM 50
SOURCE FOR BEST SFDR
a
FROM 50
SOURCE
R
T
61.9
250
250
AD9042
INPUT =
1V p-p
+
-
The AD9050 is a 10-bit , 40MSPS single supply ADC designed for wide dynamic
r ange applicat ions such as ult r asound, inst r ument at ion, digit al communicat ions,
and pr ofessional video. Like t he AD9042, it is fabr icat ed on a high speed
complement ar y bipolar pr ocess. A block diagr am of t he AD9050 (Figur e 5.15)
illust r at es t he t wo-st ep subr anging ar chit ect ur e, and key specificat ions ar e
summar ized in Figur e 5.16.
14
a
5.15
AD9050 10-BIT, 40MSPS SINGLE SUPPLY ADC
ENCODE
AMP
ARRAY
6-BIT
ADC
DECODE
LOGIC
ERROR
CORRECTION
DECODE
LOGIC
AD9050
BANDGAP
REFERENC
E
5-BIT
ADC
10
AIN
AIN
V
REF
OUT
V
REF
IN
REF
BP
AD9050 10-BIT, 40MSPS ADC KEY SPECIFICATIONS
n n 10-Bits, 40MSPS, Single +5V Supply
n n Selectable Digital Supply: +5V, or +3V
n n Low Power: 300mW on BiCMOS Process
n n On-Chip SHA and +2.5V reference
n n 56dB S/(N+D), 9 Effective Bits, with 10.3MHz Input Signal
n n No input transients, Input Impedance 5k , 5pF
n n Input Range +3.3V 0.5V Single-Ended or Differential
n n 28-pin SOIC / SSOP Packages
n n Ideal for Digital Beamforming Ultrasound Systems
a 5.16
The analog input cir cuit of t he AD9050 (see Figur e 5.17) is differ ent ial, but can be
dr iven eit her single-endedly or differ ent ially wit h equal per for mance. The input
signal r ange of t he AD9050 is 0.5V cent er ed ar ound a common-mode volt age of
15
+3.3V, which makes single supply op amp select ion mor e difficult since t he amplifier
has t o dr ive +3.8V peak signals wit h low dist or t ion.
5.17
AD9050 SIMPLIFIED INPUT CIRCUIT
GND
INPUT RANGE:
+3.3V 0.5V
INPUT BUFFER
+5V
AIN(A)
AIN(B)
8k
16k
8k
16k
a
The input cir cuit of t he AD9050 is a r elat ively benign and const ant 5k in par allel
wit h appr oximat ely 5pF. Because of it s well-behaved input , t he AD9050 can be
dr iven dir ect ly fr om 50, 75, or 100 sour ces wit hout t he need for a low-dist or t ion
buffer amplifier . In ult r asound applicat ions, it is nor mal t o AC couple t he signal
(gener ally bet ween 1MHz and 15MHz) int o t he AD9050 differ ent ial input s using a
wideband t r ansfor mer as shown in Figur e 5.18. The Mini-Cir cuit s T1-1T
t r ansfor mer has a 1dB bandwidt h fr om 200kHz t o 80MHz. Signal-t o-noise plus
dist or t ion (SINAD) values of 57dB (9.2 ENOB) ar e t ypical for a 10MHz input signal.
If t he input signal comes dir ect ly fr om a 50, 75, or 100 single-ended sour ce,
capacit ive coupling as shown in Figur e 5.18 can be used.
16
5.18
AC COUPLING INTO THE INPUT OF THE AD9050 ADC
TRANSFORMER
COUPLING
16k
16k
50
CAPACITIVE
COUPLING
8k
8k
+5V
T1
T1:
MINI-CIRCUITS
T1 - 1T
+5V
50
8k
8k
16k
16k
a
If DC coupling is r equir ed, t he AD8041 (zer o-volt in, r ail-t o-r ail out put ) op amp can
be used as a low dist or t ion dr iver . The cir cuit shown in Figur e 5.19 level shift s a
gr ound-r efer enced video signal t o fit t he +3.3V 0.5V input r ange of t he AD9050.
The sour ce is a gr ound-r efer enced 0 t o +2V signal which is ser ies-t er minat ed in 75.
The t er minat ion r esist or , R
T
, is chosen such t hat t he par allel combinat ion of R
T
and
R1 is 75. The AD8041 op amp is configur ed for a signal gain of 1. Assuming t hat
t he video sour ce is at zer o volt s, t he cor r esponding ADC input volt age should be
+3.8V. The common-mode volt age, V
cm
, is det er mined fr om t he following equat ion:
V
cm
R
s
R
T
R
R
s
R
T
R R
V =
+
+ +

=
+
+ +

= 3 8
1
1 2
3 8
38 8 1000
38 8 1000 1000
1 94 .
| |
| |
.
.
.
.
The common-mode volt age, V
cm
, is der ived fr om t he common-mode volt age at t he
inver t ing input of t he AD9050. The +3.3V is buffer ed by t he AD820 single-supply
FET-input op amp. A divider net wor k gener at es t he r equir ed +1.94V for t he
AD8011, and a pot ent iomet er pr ovides offset adjust ment capabilit y.
The AD8041 volt age feedback op amp was chosen because of it s low power (26mW),
wide bandwidt h (160MHz), and low dist or t ion (69dBc at 10MHz). It is fully
specified for bot h 5V,+5V, and +3V oper at ion. When oper at ing on a single +5V
supply, t he input common-mode r ange is 0.2V t o +4V, and t he out put swing is
+0.1V t o +4.9V. Dist or t ion per for mance of t he ent ir e cir cuit including t he ADC is
bet t er t han 60dBc for an input fr equency of 10MHz and a sampling r at e of
40MSPS.
17
5.19
DC-COUPLED SINGLE-SUPPLY DRIVE CIRCUIT FOR
AD9050 10-BIT, 40MSPS ADC USING AD8041 OP AMP
+
+
-
R2
1000
80.6
1000
+5V
1000
R
T
R1
R
S
75
+5V
0 TO
+2V
AD9050
0.1 F
0.1 F
V
CM
= +1.94V
+
-
+5V
OFFSET
ADJUST
50 365 249
0.1 F
+5V
8k
16k
AIN(A)
AIN(B)
8k
16k
+3.3V
3.8V TO 2.8V
AD8041
0.1 F
10 F
AD820
a
72mV TO 1.072V
18
AP P LI CATI ONS OF HI GH SP EED ADCS I N CCD I MAGI NG
Char ge coupled devices (CCDs) cont ains a lar ge number of small phot ocells called
phot osit es or pixels which ar e ar r anged eit her in a single r ow (linear ar r ays) or in a
mat r ix (ar ea ar r ays). CCD ar ea ar r ays ar e commonly used in video applicat ions,
while linear ar r ays ar e used in facsimile machines, gr aphics scanner s, and pat t er n
r ecognit ion equipment .
The linear CCD ar r ay consist s of a r ow of image sensor element s (phot osit es, or
pixels) which ar e illuminat ed by light fr om t he object or document . Dur ing one
exposur e per iod each phot osit e acquir es an amount of char ge which is pr opor t ional
t o it s illuminat ion. These phot osit e char ge packet s ar e subsequent ly swit ched
simult aneously via t r ansfer gat es t o an analog shift r egist er . The char ge packet s on
t his shift r egist er ar e clocked ser ially t o a char ge det ect or (st or age capacit or ) and
buffer amplifier (sour ce follower ) which conver t t hem int o a st r ing of phot o-
dependent out put volt age levels (see Figur e 5.20). While t he char ge packet s fr om
one exposur e ar e being clocked out t o t he char ge det ect or , anot her exposur e is
under way. The analog shift r egist er t ypically oper at es at fr equencies bet ween 1 and
10MHz.
5.20
LINEAR CCD ARRAY
a
SHIFT
CLOCKS
TRANSFER
CLOCKS
EXPOSURE
CLOCKS
RESET
LEVEL
CCD
OUTPUT
SAMPLE VIDEO/
SAMPLE RESET
FET SWITCH
TRANSFER GATE
PHOTO-SITES (PIXELS)
ANALOG TRANSPORT
SHIFT REGISTER
+V
-V
C
H
The char ge det ect or r eadout cycle begins wit h a r eset pulse which causes a FET
swit ch t o set t he out put st or age capacit or t o a known volt age. Swit ching t he FET
causes capacit ive feedt hr ough which r esult s in a r eset glit ch at t he out put as shown
in Figur e 5.21. The swit ch is t hen opened, isolat ing t he capacit or , and t he char ge
fr om t he last pixel is dumped ont o t he capacit or causing a volt age change. The
differ ence bet ween t he r eset volt age and t he final volt age (video level) shown in
Figur e 5.21 r epr esent s t he amount of char ge in t he pixel. CCD char ges may be as
19
low as 10 elect r ons, and a t ypical CCD out put sensit ivit y is 0.6V/elect r on. Most
CCDs have a sat ur at ion out put volt age of about 1V (see Refer ence 1).
5.21
CCD OUTPUT WAVEFORM
a
RESET
GLITCH
RESET
LEVEL
RESET
LEVEL
RESET
LEVEL
VIDEO
LEVEL
VIDEO
LEVEL
VIDEO
LEVEL
PIXEL PERIOD
V
t
CCD
OUTPUT
Since CCDs ar e gener ally fabr icat ed on MOS pr ocesses, t hey have limit ed capabilit y
t o per for m on-chip signal condit ioning. Ther efor e, t he CCD out put is gener ally
pr ocessed by ext er nal condit ioning cir cuit s.
CCD out put volt ages ar e small and quit e oft en bur ied in noise. The lar gest sour ce of
noise is t he t her mal noise in t he r esist ance of t he FET r eset swit ch. This noise may
have a t ypical value of 100 t o 300 elect r ons r ms (appr oximat ely 60 t o 180mV r ms).
This noise occur s as a sample-to-sample var iat ion in t he CCD out put level and is
common t o bot h t he r eset level and t he video level for a given pixel per iod. A
t echnique called correlated double sampling (CDS) is oft en used t o r educe t he effect
of t his noise. Figur e 5.22 shows t wo cir cuit implement at ions of t he CDS scheme. In
t he t op cir cuit , t he CCD out put dr ives bot h SHAs. At t he end of t he r eset int er val,
SHA1 holds t he r eset volt age level. At t he end of t he video int er val, SHA2 holds t he
video level. The SHA out put s ar e applied t o a differ ence amplifier which subt r act s
one fr om t he ot her . In t his scheme, t her e is only a shor t int er val dur ing which bot h
SHA out put s ar e st able, and t heir differ ence r epr esent s V, so t he differ ence
amplifier must set t le quickly t o t he desir ed r esolut ion.
Anot her ar r angement is shown in t he bot t om half of Figur e 5.22, which uses t hr ee
SHAs and allows eit her for fast er oper at ion or mor e t ime for t he differ ence amplifier
t o set t le. In t his cir cuit , SHA1 holds t he r eset level so t hat it occur s simult aneously
wit h t he video level at t he input t o SHA2 and SHA3. When t he video clock is applied
simult aneously t o SHA2 and SHA3, t he input t o SHA2 is t he r eset level, and t he
input t o SHA3 t he video level. This ar r angement allows t he ent ir e pixel per iod (less
t he acquisit ion t ime of SHA2 and SHA3) for t he differ ence amplifier t o set t le.
20
CORRELATED DOUBLE SAMPLING (CDS)
MINIMIZES SWITCHING NOISE AT OUTPUT
5.22
a
CCD
OUTPUT
CCD
OUTPUT
OUTPUT
OUTPUT
RESET
CLOCK
VIDEO
CLOCK
SHA 1
RESET CLOCK
VIDEO CLOCK
METHOD #1
METHOD #2
-
+
-
+
SHA 2
SHA 1 SHA 2
SHA 3
The AD9807 is a complet e CCD imaging decoder and signal pr ocessor on a single
chip (see Figur e 5.23). The input of t he AD9807 allows dir ect AC coupling of t he
CCD out put s and includes all t he cir cuit r y t o per for m t hr ee-channel cor r elat ed
double sampling (CDS) and pr ogr ammable gain adjust ment (1X t o 4X in 16
incr ement s) of t he CCD out put . A 12-bit ADC quant izes t he analog signal
(maximum sampling fr equency 6MSPS). Aft er digit izat ion, t he on-boar d DSP allows
pixel r at e offset and gain cor r ect ion. The DSP also cor r ect s odd/even CCD r egist er
imbalance er r or s. A par allel cont r ol bus pr ovides a simple int er face t o 8-bit
micr ocont r oller s. The device oper at es on a single +5V supply and dissipat es 500mW.
The AD9807 comes in a space saving 64-pin plast ic quad flat pack (PQFP). By
disabling t he CDS, t he AD9807 is also suit able for non-CCD applicat ions t hat do not
r equir e CDS. The AD9807 is also offer ed in a pin-compat ible 10-bit ver sion, t he
AD9805, t o allow upgr adeabilit y and simplify design issues acr oss differ ent scanner
models.
21
CONFI GURATION
REGISTER
CONFI GURATION
REGISTER
2
CSB
RDB
WRB
A0
A1
A2
OEB
DOUT<11:0>
CDS
CDS
CDS
PGA
PGA
PGA
3:1 MUX
12-BIT A/D
DIGITAL
SUBTRACTOR
R
G
B
CDSCLK1 CDSCLK2
STRTLN ADCCLK
R
G
B
R
ODD
G
ODD
B
ODD
R
EVEN
G
EVEN
B
EVEN
DIGITAL
MULTI PLIER
x
8-10 12-10
12 12 12
12
MPU
PORT
VINR
VING
VINB
INPUT
OFFSET
REGISTER
GAIN<N:0> OFFSET<M:0> VREF
DVDD CML CAPT CAPB AVSS DVSS AVDD
BANDGAP
REFERENCE
8
DRVDD DRVSS
a 5.23
22
HI GH SP EED ADC AP P LI CATI ONS I N DI GI TAL
RECEI VERS
I n t r od u ct i on
Consider t he analog super het er odyne r eceiver invent ed in 1917 by Major Edwin H.
Ar mst r ong (see Figur e 5.24). This ar chit ect ur e r epr esent ed a significant
impr ovement over single-st age dir ect conver sion (homodyne) r eceiver s which had
pr eviously been const r uct ed using t uned RF amplifier s, a single det ect or , and an
audio gain st age. A significant advant age of t he super het r odyne r eceiver is t hat it is
much easier and mor e economical t o have t he gain and select ivit y of a r eceiver at
fixed int er mediat e fr equencies (IF) t han t o have t he gain and fr equency-select ive
cir cuit s "t une" over a band of fr equencies.
a
U.S. ADVANCED MOBILE PHONE SERVICE (AMPS)
SUPERHETERODYNE ANALOG RECEIVER
5.24
SAME AS ABOVE
CHANNEL 1
30kHz
CHANNEL n
30kHz
RF
BPF
LNA
LO1
TUNED
70MHz
1ST IF 2ND IF
3RD IF
10.7MHz 455kHz
LO2
FIXED
LO3
FIXED
ANALOG
DEMOD,
FILTER
AMPS: 416 CHANNELS ("A" OR "B" CARRIER)
30kHz WIDE, FM
12.5MHz TOTAL BANDWIDTH
1 CALLER/CHANNEL
The fr equencies shown in Figur e 5.24 cor r espond t o t he AMPS (Advanced Mobile
Phone Ser vice) analog cellular phone syst em cur r ent ly used in t he U.S. The r eceiver
is designed for AMPS signals at 900MHz RF. The signal bandwidt h for t he "A" or
"B" car r ier s ser ving a par t icular geogr aphical ar ea is 12.5MHz (416 channels, each
30kHz wide). The r eceiver shown uses t r iple conver sion, wit h a fir st IF fr equency of
70MHz and a second IF of 10.7MHz, and a t hir d of 455kHz. The image fr equency at
t he r eceiver input is separ at ed fr om t he RF car r ier fr equency by an amount equal t o
t wice t he fir st IF fr equency (illust r at ing t he point t hat using r elat ively high fir st IF
fr equencies makes t he design of t he image r eject ion filt er easier ).
The out put of t he t hir d IF st age is demodulat ed using analog t echniques
(discr iminat or s, envelope det ect or s, synchr onous det ect or s, et c.). In t he case of
AMPS t he modulat ion is FM. An impor t ant point t o not ice about t he above scheme
23
is t hat t her e is one receiver required per channel, and only t he ant enna, pr efilt er , and
LNA can be shar ed.
It should be not ed t hat in t o make t he r eceiver diagr ams mor e manageable, t he
int er st age amplifier s ar e not shown. They ar e, however , an impor t ant par t of t he
r eceiver , and t he r eader should be awar e t hat t hey must be pr esent .
Receiver design is a complicat ed ar t , and t her e ar e many t r adeoffs t hat can be made
bet ween IF fr equencies, single-conver sion vs. double-conver sion or t r iple conver sion,
filt er cost and complexit y at each st age in t he r eceiver , demodulat ion schemes, et c.
Ther e ar e many excellent r efer ences on t he subject , and t he pur pose of t his sect ion is
only t o acquaint t he design engineer wit h some of t he emer ging ar chit ect ur es,
especially in t he applicat ion of digit al t echniques in t he design of advanced
communicat ions r eceiver s.
A Recei ver Usi n g Di gi t a l P r ocessi n g a t Ba seba n d
Wit h t he availabilit y of high per for mance high speed ADCs and DSPs (such as
ADSP-2181 and t he ADSP-21062), it is now becoming common pr act ice t o use
digit al t echniques in at least par t of t he r eceive and t r ansmit pat h, and var ious
chipset s ar e available fr om Analog Devices t o per for m t hese funct ions for GSM and
ot her cellular st andar ds. This is illust r at ed in Figur e 5.25 wher e t he out put of t he
last IF st age is conver t ed int o a baseband in-phase (I) and quadr at ur e (Q) signal
using a quadr at ur e demodulat or . The I and Q signals ar e t hen digit ized by t wo
ADCs. The DSPs t hen per for m t he addit ional signal pr ocessing. The signal can t hen
be conver t ed int o analog for mat using a DAC, or it can be pr ocessed, mixed wit h
ot her signals, upconver t ed, and r et r ansmit t ed.
CHANNEL 1
SIN
COS
Q
I
Q
I
QVCO
a
DIGITAL RECEIVER USING
BASEBAND SAMPLING AND DIGITAL PROCESSING
5.25
SAME AS ABOVE
CHANNEL n
DSP
CHANNEL
1
CHANNEL
n
LPF
ADC
ADC
LPF
455kHz
3RD IF
24
At t his point , we should make it clear t hat a digital receiver is not the same thing as
digital modulation. In fact , a digit al r eceiver will do an excellent job of r eceiving an
analog signal such as AM or FM. Digit al r eceiver s can be used t o r eceive any t ype of
modulat ion st andar d including analog (AM, FM) or digit al (QPSK, QAM, FSK,
GMSK, et c.). Fur t her mor e, since t he cor e of a digit al r adio is it s digit al signal
pr ocessor (DSP), t he same r eceiver can be used for bot h analog and digit ally
modulat ed signals (simult aneously if necessar y), assuming t hat t he RF and IF
har dwar e in fr ont of t he DSP is pr oper ly designed. Since it is soft war e t hat
det er mines t he char act er ist ics of t he r adio, changing t he soft war e changes t he r adio.
For t his r eason, digit al r eceiver s ar e oft en r efer r ed t o as software radios.
The fact t hat a r adio is soft war e pr ogr ammable offer s many benefit s. A r adio
manufact ur er can design a gener ic r adio in har dwar e. As int er face st andar ds change
(as fr om FM t o CDMA or TDMA), t he manufact ur er is able t o make t imely design
changes t o t he r adio by r epr ogr amming t he DSP. Fr om a user or ser vice-pr ovider s
point of view, t he soft war e r adio can be upgr aded by loading t he new soft war e at a
small cost , while r et aining all of t he init ial har dwar e invest ment . Addit ionally, t he
r eceiver can be t ailor ed for cust om applicat ions at ver y low cost , since only soft war e
cost s ar e involved.
A digit al r eceiver per for ms t he same funct ion as an analog one wit h one differ ence;
some of t he analog funct ions have been r eplaced wit h t heir digit al equivalent . The
main differ ence bet ween Figur e 5.24 and Figur e 5.25 is t hat t he FM discr iminat or
in t he analog r adio has been r eplaced wit h t wo ADCs and a DSP. While t his is a
ver y simple example, it shows t he fundament al beginnings of a digit al, or software
r adio.
An added benefit of using digit al t echniques is t hat some of t he filt er ing in t he r adio
is now per for med digit ally. This eliminat es t he r equir ement of t ight t oler ances and
mat ching for fr equency-sensit ive component s such as induct or s and capacit or s. In
addit ion, since filt er ing is per for med wit hin t he DSP, t he filt er char act er ist ics can be
implement ed in soft war e inst ead of cost ly and sensit ive SAW, cer amic, or cr yst al
filt er s. In fact , many filt er s can be synt hesized digit ally t hat could never be
implement ed in a st r ict ly analog r eceiver .
This simple example is only t he beginning. Wit h cur r ent t echnology, much mor e of
t he r eceiver can be implement ed in digit al for m. Ther e ar e numer ous advant ages t o
moving t he digit al por t ion of t he r adio closer t o t he ant enna. In fact , placing t he
ADC at t he out put of t he RF sect ion and per for ming dir ect RF sampling might seem
at t r act ive, but does have some ser ious dr awbacks, par t icular ly in t er ms of select ivit y
and out -of-band (image) r eject ion. However , t he concept makes clear one key
advant age of soft war e r adios: t hey ar e pr ogr ammable and r equir e lit t le or no
component select ion or adjust ment s t o at t ain t he r equir ed r eceiver per for mance.
Na r r owba n d I F-Sa mp li n g Di gi t a l Recei ver s
A r easonable compr omise in many digit al r eceiver s is t o conver t t he signal t o digit al
for m at t he out put of t he fir st or t he second IF st age. This allows for out -of-band
signals t o be filt er ed befor e r eaching t he ADC. It also allows for some aut omat ic gain
cont r ol (AGC) in t he analog st age ahead of t he ADC t o r educe t he possibilit y of in-
band signals over dr iving t he ADC and allows for maximum signal gain pr ior t o t he
A/D conver sion. This r elieves some of t he dynamic r ange r equir ement s on t he ADC.
25
Addit ionally, IF sampling and digit al r eceiver t echnology r educe cost s by eliminat ion
of fur t her IF st ages (mixer s, filt er s, and amplifier s) and adds flexibilit y by t he
r eplacement of fixed analog filt er component s wit h pr ogr ammable digit al ones.
In analyzing an analog r eceiver design, much of t he signal gain is aft er t he fir st IF
st age. This pr event s fr ont -end over dr ive due t o out -of-band signals or st r ong in-band
signals. However , in an IF sampling digit al r eceiver , all of t he gain is in t he fr ont
end, and gr eat car e must be t aken t o pr event in-band and out -of-band signals fr om
sat ur at ing t he ADC, which r esult s in excessive dist or t ion. Ther efor e, a met hod of
at t enuat ion must be pr ovided when lar ge in-band signals occur . While addit ional
signal gain can be obt ained digit ally aft er t he ADC, t her e ar e cer t ain r est r ict ions.
Gain pr ovided in t he analog domain impr oves t he SNR of t he signal and only
r educes t he per for mance t o t he degr ee t hat t he noise figur e (NF) degr ades noise
per for mance.
Figur e 5.26 shows a det ailed IF sampling digit al r eceiver for t he GSM syst em . The
r eceiver has RF gain, aut omat ic gain cont r ol (AGC), a high per for mance ADC,
digit al demodulat or /filt er , and a DSP.
a
NARROWBAND IF SAMPLING GSM DIGITAL RECEIVER
5.26
SAME AS ABOVE
CHANNEL
1
900MHz
LO1
TUNED
70MHz
1ST IF
DSP
200kHz WIDE CHANNELS
16 CALLERS/CHANNEL
CHANNEL
n
DIGITAL
DEMODULATION
AND
DECIMATION
FILTER
RSSI
ADC
AGC
The hear t of t he syst em is t he AD6600 dual channel, gain r anging 11-bit , 20MSPS
ADC wit h RSSI (Received Signal St r engt h Indicat or ) and t he AD6620 dual channel
decimat ing r eceiver . A det ailed block diagr am of t he AD6600 is shown in Figur e
5.27 and key specificat ions in Figur e 5.28.
26
a
AD6600 DUAL CHANNEL GAIN RANGING ADC WITH
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
5.27
IF
A
IF
B
A/B
ATTEN
ATTEN
MUX
PEAK
DETECTOR
RSSI
CONTROL
EXTERNAL
FILTER
T/H
11-BIT
ADC
11
3
+
+
-
-
12dB
AD6600 KEY SPECIFICATIONS
n n Dual Input, 11-bit, 20MSPS ADC Plus 3-bits RSSI
n n Dynamic Range > 100dB
u u 11-bit ADC 62dB
u u 3-bits RSSI 30dB (5 levels, 6dB / level)
u u Process Gain 12dB (6.5MSPS Sampling, 200kHz Channel)
n n On-Chip Reference and Timing
n n Single +5V Supply, 400mW
n n 44-pin TQFP Package
n n Optimum Design for Narrowband Digital Receivers
with IF Frequencies to 250MHz
a 5.28
The AD6600 is a mixed signal chip t hat dir ect ly samples nar r ow band signals at IF
fr equencies up t o 250MHz. The device includes an 11-bit , 20MSPS ADC, input
at t enuat or s, aut omat ic gain r anging cir cuit r y, a 450MHz bandwidt h t r ack-and-hold,
27
digit al RSSI out put s, r efer ences, and cont r ol cir cuit r y. The device accept s t wo input s
(for use wit h diver sit y ant ennas) which ar e mult iplexed t o t he single ADC.
The AD6600 pr ovides gr eat er t han 92dB dynamic r ange fr om t he ADC and t he aut o
gain-r anging/RSSI cir cuit s. The gain r ange is 36dB in 6dB incr ement s (cont r olled by
a 3-bit wor d fr om t he RSSI cir cuit ). This set s t he smallest input r ange at 31mV
peak-t o-peak, and t he lar gest at 2V peak-t o-peak. SFDR is 70dBc @100MHz and
53dBc @250MHz. Channel isolat ion is 70dB @100MHz and 60dB @250MHz. The
SNR per for mance of t he AD6600 is shown in Figur e 5.29. The dynamic r ange of t he
AD6600 is gr eat er t han t he minimum GSM specificat ion of 91dB.
AD6600 INPUT VS. SNR
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
+10
-2
-8
-14
-20
-26
-88
-83
Ain
SNR
RSSI=101, Vin>=.5Vpp
RSSI=100, .25Vpp<=Vin<.5Vpp
RSSI=011, .125Vpp<=Vin<.25Vpp
RSSI=010, .0625Vpp<=Vin<.125Vpp
RSSI=001, .03125Vpp<=Vin<.0625Vpp
RSSI=000, Vin<.03125Vpp
Input voltage range & RSSI
for AD6600 input ranges
a 5.29
The analog input t o t he AD6600 consist s of t wo par allel at t enuat or st ages followed
by an out put select ion mult iplexer . The at t enuat ion levels can be set eit her by t he
on-chip aut omat ic RSSI cir cuit (synchr onous peak det ect or ) or can be set digit ally
wit h ext er nal logic. The ADC T/H input can also be accessed dir ect ly by by-passing
t he fr ont -end at t enuat or s.
An ext er nal analog filt er is r equir ed bet ween t he at t enuat or out put and t he t r ack-
and-hold input of t he ADC sect ion. This filt er may be eit her a lowpass or a bandpass
depending on t he syst em ar chit ect ur e. Since t he input bandwidt h of t he ADC is
450MHz, t he filt er minimizes t he wideband noise ent er ing t he t r ack-and-hold. The
bandwidt h of t he filt er should be set t o allow sufficient set t ling t ime (1/2 t he
sampling per iod) dur ing t he RSSI peak det ect ion per iod.
28
The ADC is based on t he high dynamic r ange AD9042 ar chit ect ur e cover ed
pr eviously. The ADC input is designed t o t ake advant age of t he excellent small-
signal linear it y of t he t r ack-and-hold. Ther efor e, t he full scale input t o t he ADC
sect ion is only 50mV peak-t o-peak. The t r ack-and-hold is followed by a gain block
wit h a 6dB gain-select t o incr ease t he signal level for digit izat ion by t he 11-bit ADC.
This amplifier only r equir es enough bandwidt h t o accur at ely set t le t o t he next value
dur ing t he sampling per iod (77ns for f
s
= 13MSPS). Because of it s r educed
bandwidt h, any high fr equency t r ack-and-hold feed t hr ough is also minimized.
The RSSI peak det ect or funct ion consist s of a bank of 5 high speed compar at or s wit h
separ at e r efer ence input s. Each r efer ence input is 6dB lower t han t he pr evious one.
Each compar at or has 6dB of built -in hyst er esis t o eliminat e level uncer t aint y at t he
t hr eshold point s. Once one of t he compar at or s is t r ipped, it st ays in t hat st at e unt il
it is r eset by t he negat ive-going edge of t he sampling clock. The 5 compar at or
out put s ar e decoded int o a 3-bit wor d t hat is used t o select t he pr oper input
at t enuat ion.
The RSSI follows t he IF signal one clock cycle befor e t he conver sion is made. Dur ing
t his t ime per iod, t he RSSI looks for t he signal peaks. Pr ior t o digit izat ion, t he RSSI
wor d select s t he cor r ect at t enuat or fact or t o pr event t he ADC fr om over -r anging on
t he following conver sion cycle. The peak signal is set 6dB below t he full scale r ange
of t he 11-bit ADC. The RSSI wor d can be r ead via t he RSSI pins. The 11-bit ADC
out put funct ions as t he mant issa, while t he RSSI wor d is t he exponent , and t he
combinat ion for ms a float ing point number .
The AD6600 is ideal for use in a GSM nar r owband basest at ion. Figur e 5.30 shows a
block diagr am of t he fundament al r eceiver . Two separ at e ant ennas and RF sect ions
ar e used (t his is oft en called diversity) t o r educe t he signal st r engt h var iat ions due t o
mult ipat h effect s. The IF out put (appr oximat ely 70MHz) of each channel is digit ized
by t he AD6600 at a sampling r at e of 6.5MSPS (one-half t he mast er GSM clock
fr equency of 13MHz). The t wo ant ennas need only be separ at ed by a few feet t o
pr ovide t he r equir ed signal st r engt h diver sit y (t he wavelengt h of a 900MHz signal is
about 1 foot ). The DSP por t ion of t he r eceiver select s t he channel which has t he
lar gest signal amplit ude.
29
a
NARROWBAND GSM BASESTATION WITH DIVERSITY
5.30
DSP
CHANNEL
1
IF
900MHz
CHANNEL
n
LO
TUNED
A
AD6600
LNA
IF
CHANNEL A
ANTENNA
CHANNEL B
ANTENNA
LNA
AD6620
ADSP-2181,
ADSP-21062
CHANNEL
n
DUAL-CHANNEL
ADC, RSSI
AND GAIN
RANGING
DUAL-CHANNEL
DEMODULATION
AND
DECIMATION
69.875MHz
1ST IF
B
f
s

= 6.5MSPS
PER CHANNEL
SAME AS ABOVE
The bandwidt h of a single GSM channel is 200kHz, and each channel can handle up
t o 8 simult aneous caller s for full-r at e syst ems and 16 simult aneous caller s for t he
newer one-half-r at e syst ems. A t ypical basest at ion may be r equir ed t o handle 50 t o
60 simult aneous caller s, t her eby r equir ing 4 separ at e signal pr ocessing channels
(assuming a one-half-r at e syst em).
The IF fr equency is chosen t o be 69.875MHz, t hus cent er ing t he 200kHz signal in
t he 22nd Nyquist zone (see Figur e 5.31). The dual channel digit al decimat ing
r eceiver (AD6620) r ever ses t he fr equency sense of t he signal and shift s it down t o
baseband.
30
a
NARROWBAND GSM RECEIVER BANDPASS SAMPLING
OF A 200kHz CHANNEL AT 6.5MSPS
5.31
ZONE
1
12f
s

ZONE
2
ZONE
3
ZONE
22
f
s

11f
s

IF = 69.875MHz 100kHz
FREQUENCY (MHz)
0 3.25 6.50 9.75 68.25 71.50 74.75 78.00
We now have a 200kHz baseband signal (gener at ed by under sampling) which is
being oversampled by a fact or of appr oximat ely 16 .
The signal is t hen passed t hr ough a digit al filt er (par t of t he AD6620) which
r emoves all fr equency component s above 200kHz, including t he quant izat ion noise
which falls in t he r egion bet ween 200kHz and 3.25MHz (t he Nyquist fr equency) as
shown in Figur e 5.32. The r esult ant incr ease in SNR is 12dB (pr ocessing gain).
Ther e is now no infor mat ion cont ained in t he signal above 200kHz, and t he out put
dat a r at e can be r educed (decimat ed) fr om 6.5MSPS t o 406.25kSPS, a dat a r at e
which t he DSP can handle. The dat a cor r esponding t o t he 200kHz channel is
t r ansmit t ed t o t he DSP over a simple 3-wir e ser ial int er face. The DSP per for ms such
funct ions as channel equalizat ion, decoding, and spect r al shaping.
31
a
DIGITAL FILTERING AND DECIMATION
OF THE 200kHz CHANNEL
5.32
f
s
= 406.25kSPS

f
s
/2

3.25MHz
AFTER FREQUENCY TRANSLATION
3.25MHz
3.25MHz
3.25MHz
f
s
= 6.5MSPS

AFTER DIGITAL FILTERING
PROCESSING GAIN = 12dB
AFTER DECIMATION ( 16)
QUANTIZATION
NOISE
0
0
0
0
200kHz
The concept of processing gain is common t o all communicat ions syst ems, analog or
digit al. In a sampling syst em, t he quant izat ion noise pr oduced by t he ADC is spr ead
over t he ent ir e Nyquist bandwidt h which ext ends fr om DC t o f
s
/2. If t he signal
bandwidt h, BW, is less t han f
s
/2, digit al filt er ing can r emove t he noise component s
out side t his bandwidt h, t her eby incr easing t he effect ive SNR. The pr ocessing gain in
a sampling syst em can be calculat ed fr om t he for mula:
Pr ocessing Gain = 10
2
log
f
s
BW

.
The SINAD (noise and dist or t ion measur ed over f
s
/2 bandwidt h) of t he ADC at t he
bandwidt h of t he signal should be used t o comput e t he act ual SINAD by adding t he
pr ocessing gain det er mined by t he above equat ion. If t he ADC is an ideal N-bit
conver t er , t hen it s SNR (measur ed over t he Nyquist bandwidt h) is 6.02N + 1.76dB.
PROCESSING GAIN
n n Measure ADC SINAD (6.02N + 1.76dB Theoretical)
n n Sampling Frequency = f
s
n n Signal Bandwidth = BW
n n Processing Gain =
10
2
log
f
s
BW






32
n n SINAD in Signal Bandwidth = SINAD +
10
2
log
f
s
BW






n n SINAD (Theoretical) = 6.02N + 1.76dB +
10
2
log
f
s
BW






n n Processing Gain Increases 3dB each time f
s
is doubled
a 5.33
Not ice t hat as shown in t he pr evious nar r owband r eceiver example, t her e can be
pr ocessing gain even if t he or iginal signal is an under sampled one. The only
r equir ement is t hat t he signal bandwidt h be less t han f
s
/2, and t hat t he noise
out side t he signal bandwidt h be r emoved wit h a digit al filt er .
Wi d eba n d I F-Sa mp li n g Di gi t a l Recei ver s
Thus far , we have avoided a det ailed discussion of narrowband ver sus wideband
digit al r eceiver s. A digit al r eceiver can be eit her , but mor e det ailed definit ions ar e
impor t ant at t his point . By narrowband, we mean t hat sufficient pr e-filt er ing has
been done such t hat all undesir ed signals have been eliminat ed and t hat only t he
signal of int er est is pr esent ed t o t he ADC input . This is t he case for t he GSM
basest at ion example pr eviously discussed.
Wideband simply means t hat a number of channels ar e pr esent ed t o input of t he
ADC and fur t her filt er ing, t uning, and pr ocessing is per for med digit ally. Usually, a
wideband r eceiver is designed t o r eceive an ent ir e band; cellular or ot her similar
wir eless ser vices such as PCS (Per sonal Communicat ions Syst ems). In fact , one
wideband digit al r eceiver can be used t o r eceive all channels wit hin t he band
simult aneously, allowing almost all of t he analog har dwar e (including t he ADC) t o
be shar ed among all channels as shown in Figur e 5.34 which compar es t he
nar r owband and t he wideband appr oaches.
33
a
NARROWBAND VERSUS WIDEBAND DIGITAL RECEIVER
5.34
CHANNEL
1
TUNED
LO
IF
BW: 30-200kHZ
DSP
CHANNEL
n
ADC
NARROWBAND
CHANNEL
1
CHANNEL
n
RF
FRONT
END
RF
FRONT
END
BW: 5-25MHz
TUNED
LO
IF
IF
ADC
ADC
DIGITAL
DECIMATION
FILTER
DIGITAL
DECIMATION
FILTER
DSP
DSP
WIDEBAND
DIGITAL
CHANNELIZER
DIGITAL
CHANNELIZER
DSP
DSP
FIXED
LO
IF
IF
Not e t hat in t he nar r owband digit al r adio, t her e is one fr ont -end LO and mixer
r equir ed per channel t o pr ovide individual channel t uning. In t he wideband digit al
r adio, however , t he fir st LO fr equency is fixed, and t he "t uning" is done in t he
digital channelizer cir cuit s following t he ADC.
A t ypical wideband digit al r eceiver may pr ocess a 5 t o 25MHz band of signals
simult aneously. This appr oach is fr equent ly called block conversion. In t he wideband
digit al r eceiver , t he var iable local oscillat or in t he nar r owband r eceiver has been
r eplaced wit h a fixed oscillat or , so t uning must be accomplished digit ally. Tuning is
per for med using a digit al down conver t er (DDC) and filt er chip fr equent ly called a
channelizer. The t er m channelizer is used because t he pur pose of t hese chips is t o
select one channel out of t he many wit hin t he br oadband spect r um act ually pr esent
in t he ADC out put . A t ypical channelizer is shown in Figur e 5.35.
34
DATA FROM
WIDEBAND
ADC
SIN
COS
Q
a
DIGITAL CHANNELIZER IN WIDEBAND RECEIVER
5.35
I
Q
I
TUNING
NCO
TUNING
CONTROL
DECIMATION
FILTER
DECIMATION
FILTER
LOWPASS
FILTER
LOWPASS
FILTER
SERIAL
DATA
TO
DSP
It consist s of an NCO (Numer ically Cont r olled Oscillat or ) wit h t uning capabilit y,
dual mixer , and mat ched digit al filt er s. These ar e t he same funct ions t hat would be
r equir ed in an analog r eceiver , but implement ed in digit al for m. The digit al out put
fr om t he channelizer is t he demodulat ed signal in I and Q for mat , and all ot her
signals have been filt er ed and r emoved. Since t he channelizer out put consist s of one
select ed RF channel, one channelizer is r equir ed for each channel. The channelizer
also ser ves t o decimat e t he out put dat a r at e such t hat it can be pr ocessed by a DSP
such as t he ADSP-2181 or t he ADSP-21062. The DSP ext r act s t he signal
infor mat ion fr om t he I and Q dat a and per for ms fur t her pr ocessing. Anot her effect of
t he filt er ing pr ovided by t he channelizer is t o incr ease t he SNR by adding pr ocessing
gain.
In t he case of an AMPS signal, t her e ar e 416 channels, each 30kHz wide, for a t ot al
bandwidt h of 12.5MHz (each of t he t wo car r ier s in a given r egion ar e allocat ed
12.5MHz of t he t ot al 25MHz cellular band). Each channel car r ies one call, so t her e is
a clear advant age in using t he wideband appr oach ver sus t he nar r owband one in an
AMPS basest at ion which must handle bet ween 50 and 60 simult aneous calls. On
t he ot her hand, a 200kHz GSM channel can car r y 16 calls simult aneously (for half-
r at e syst ems), so only t hr ee or four channels ar e r equir ed in t he t ypical GSM
basest at ion, and t he nar r owband appr oach is mor e cost -effect ive. Using t oday's
t echnology (1996), t he br eak-even cost point bet ween nar r owband and wideband
r anges fr om t wo and eight channels.
In an ADC used for nar r owband applicat ions, t he key specificat ions ar e SINAD,
SFDR, and SNR. The nar r owband ADC can t ake advant age of aut omat ic gain
r anging (as in t he AD6600) t o account for signal amplit ude var iat ions bet ween
individual channels and t her eby achieve ext r a dynamic r ange.
35
On t he ot her hand, an ADC used in a wideband r eceiver must digit ize all channels
simult aneously, t her eby eliminat ing t he possibilit y of per -channel analog gain
r anging. For example, t he GSM (Eur opean Digit al Cellular ) syst em specificat ion
r equir es t he r eceiver t o pr ocess signals bet ween 13dBm and 104dBm (wit h a noise
floor of 114dBm) in t he pr esence of many ot her signals. This is a dynamic r ange of
91dB! This implies t hat t he SFDR of t he ADC and t he analog fr ont end must be
appr oximat ely 95 t o 100dBFS, allowing for addit ional headr oom. In addit ion, t he
GSM syst em has 124 channels, each having a bandwidt h of 200kHz for a t ot al
signal bandwidt h of 25MHz. The minimum r equir ed sampling r at e for an ADC
suit able for wideband GSM is t her efor e gr eat er t han 50MSPS.
SFDR is a ver y impor t ant specificat ion when a mobile phone is near t he basest at ion
because it is an indicat ion of how st r ong signals int er fer e wit h signals in ot her
channels. St r ong signals usually pr oduce t he lar gest spur s due t o fr ont -end
dist or t ion, and t hese spur s can mask weaker signals fr om mobile phones near t he
cell fr inges. The SFDR for weak signals pr ovides an indicat ion of t he over all noise
floor , or SINAD which can ult imat ely be r elat ed t o t he r eceiver bit er r or r at e (BER).
When digit izing a wideband signal, full scale single-t one evaluat ions ar e no longer
sufficient . Two-t one and mult iple-t one int er modulat ion t est ing in conjunct ion wit h
SFDR amplit ude sweeps ar e bet t er indicat or s of per for mance.
GSM VERSUS AMPS COMPARISONS
GSM AMPS
Digital Receiver Narrowband Wideband
# of Channels 124 416
Channel BW 200kHz 30kHz
Total BW 25MHz 12.5MHz
Callers/Channel 16 (one-half rate) 1
ADC
Requirements
11-bits with RSSI
6.5 MSPS
92dB Dynamic Range
12-bits
30.72 MSPS
80dB SFDR
Process Gain 12dB 27dB
a 5.36
The AMPS cellular syst em basest at ion is ideally suit ed t o t he wideband digit al
r eceiver design, and a simplified diagr am of one is shown in Figur e 5.37. The
AD9042 sampling fr equency of 30.72MSPS is chosen t o be a power -of-t wo mult iple
36
of t he channel bandwidt h (30kHz x 1024). Anot her popular AMPS wideband
r eceiver sampling fr equency is 40.96MSPS. The choice of IF fr equency is flexible,
and a second IF st age may be r equir ed if lower IF fr equencies ar e chosen.
a
AMPS WIDEBAND DIGITAL RECEIVER
5.37
CHANNEL
1
900MHz
LO1
FIXED
IF
BW: 12.5MHz
DSP
416 CHANNELS
30kHz CHANNEL BW
1 CALLER/CHANNEL
CHANNEL
n
AD9042
ADC
LNA
DSP
CHANNELIZER
CHANNELIZER
NOTE: THERE MAY BE
2 IF STAGES
f
s
= 30.72 MSPS
OR 40.96 MSPS
Wit h a sampling fr equency of 30.72MSPS, t he 12.5MHz bandwidt h signal can be
posit ioned in t he fir st Nyquist zone (DC t o 15.36MHz) wit h an IF fr equency of
7.68MHz, or in t he second Nyquist zone (15.36MHz t o 30.72MHz) wit h an IF
fr equency of 23.04MHz.
Wit h a sampling fr equency of 40.96MSPS, t he 12.5 MHz bandwidt h signal can be
posit ioned in t he fir st Nyquist zone (DC t o 20.48MHz) wit h an IF fr equency of
10.24MHz, or in t he second Nyquist zone (20.48MHz t o 40.96MHz) wit h an IF
fr equency of 30.72MHz.
The digit al channelizer s pr ovide t he r eceiver t uning and demodulat e t he signal int o
t he I and Q component s. The out put dat a r at e t o t he DSPs aft er decimat ion is
60kSPS. The pr ocessing gain incur r ed is calculat ed as follows:
Pr ocessing Gain = 10
30 72
2 0 03
271 log
.
.
. .

= dB
AMPS WIDEBAND RECEIVER PROCESS GAIN
n n fs = 30.72MSPS (1024 30kHz)
n n Channel BW = 30kHz
37
n n Process Gain =
10
2
log
f
s
BW






= 27.1dB
a 5.38
In addit ion t o SFDR, t wo-t one and mult i-t one int er modulat ion dist or t ion is
impor t ant in an ADC for wideband r eceiver applicat ions. Figur e 5.39 shows t wo
st r ong signals in t wo adjacent channels at fr equencies f1 and f2. If t he ADC has
t hir d-or der int er modulat ion dist or t ion, t hese pr oduct s will fall at 2f
2
f
1
and 2f
1
f
2
and ar e indist inguishable fr om signals which might be pr esent in t hese channels.
This is one r eason t he GSM syst em is difficult t o implement using t he wideband
appr oach, since t he dynamic r ange r equir ement is gr eat er t han 91dB.
a
TWO-TONE INTERMODULATION DISTORTION
IN MULTICHANNEL SYSTEM
(GSM REQUIREMENTS SHOWN)
5.39
f
2f
2
- f
1
f
1
f
2
STRONG SIGNALS
2f
1
- f
2
WEAK SIGNAL
OR 3RD ORDER IMD?
-13dBm
-104dBm
-114dBm
The t wo-t one SFDR of t he AD9042 is gr eat er t han 80dB wit h input t ones at
15.3MHz and 19.5MHz as shown in Figur e 5.40. Not e t han t he amplit ude of each
t one must be 6dB below full scale in or der t o pr event t he ADC fr om being
over dr iven. The t wo-t one SFDR as a funct ion of input signal amplit ude is shown in
Figur e 5.41 for t one fr equencies of 19.3MHz and 19.51MHz. The upper cur ve is in
dBFS, and t he lower in dBc. Not e t hat t he SFDR is gr eat er t han 80dBFS for all
input amplit udes. Figur e 5.42 shows a mult it one FFT out put for t he AD9042, and
t he ADC st ill maint ains 85dBFS of SFDR.
38
AD9042 TWO-TONE FFT OUTPUT
F1 = 15.3MHz, F2 = 19.5MHz, f
s
= 41MSPS
5.40
a
FREQUENCY - MHz
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 41 MSPS
AIN = 15.3, 19.5MHz
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L
-
S
C
A
L
E

-

d
B
AD9042 TWO-TONE SFDR
F1 = 19.3MHz, F2 = 19.51MHz, f
s
= 41MSPS
5.41
a
INPUT POWER LEVEL (F1 = F2) - dBFS
100
0
-80 0 -70 -60 -50 -40 -30 -20 -10
90
60
40
20
10
80
70
50
30
ENCODE = 41 MSPS
F1 = 19.3MHz
F2 = 19.51MHz
SFDR = 80dB
REFERENCE LINE
dBFS
dBc
W
O
R
S
T

C
A
S
E

S
P
U
R
I
O
U
S

-

d
B
c

A
N
D

d
B
F
S
39
AD9042 MULTITONE PERFORMANCE (4 TONES)
f
s
= 41MSPS
5.42
a
FREQUENCY - MHz
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 41 MSPS
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L
-
S
C
A
L
E

-

d
B
3 6 9 7 4 2 5 8
Di r ect I F-t o-Di gi t a l Con si d er a t i on s
The dynamic per for mance of t he AD9042 ext ends well beyond 20MHz analog input
signals (see Figur e 5.43). Ther efor e it can be used t o per for m dir ect IF-t o-digit al
conver sions using a wide r ange of IF fr equencies. These IF signals can be
under sampled as pr eviously descr ibed, and t he minimum sampling fr equency
r equir ed is det er mined by t he bandwidt h of t he IF signal. Figur e 5.44 shows a
21.4MHz signal sampled at 10MSPS using t he AD9042. Not e t hat under t hese
condit ions, t he SFDR per for mance is gr eat er t han 80dBFS.
40
AD9042 SFDR VERSUS INPUT FREQUENCY
5.43
a
W
O
R
S
T

S
P
U
R

-

d
B
F
S
ANALOG INPUT FREQUENCY - MHz
90
30
1 100 10
80
70
60
50
40
2 4 20 40
5.44
a
AD9042 OUTPUT FOR IF SAMPLED INPUT:
f
s
= 10MSPS, ANALOG INPUT = 21.4MHz
W
O
R
S
T

S
P
U
R

-

d
B
F
S
FREQUENCY - MHz
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 10.0 MSPS
AIN = 21.4MHz
8 7 8 6 2 5 3 4
The AD6640 r epr esent s t he next gener at ion in IF sampling ADCs. Key
specificat ions for t he AD6640 ar e summar ized in Figur e 5.45. The ar chit ect ur e is
similar t o t hat of t he AD9042, but t he device is fabr icat ed on a fast er XFCB pr ocess.
The input st r uct ur e is fully differ ent ial and designed for t r ansfor mer coupling for
41
minimum dist or t ion. Maximum sampling fr equency is 65MSPS, and t he SINAD
per for mance is 67dB at 60MHz analog input . SFDR is gr eat er t han 80dBFS for
fr equencies up t o 25MHz. This device allows dir ect IF sampling in wideband
communicat ions syst ems having bandwidt hs up t o 25MHz (such as t he AMPS
syst em, wher e each car r ier is allocat ed 12.5MHz of spect r um). For syst ems wit h
smaller bandwidt hs, t he higher sampling fr equency pr ovided by t he AD6640 will
allow analog ant ialiasing filt er r equir ement s t o be r elaxed and pr ovide pr ocessing
gain. In under sampling applicat ions, t he device can be used t o digit ize 70MHz IF
signals which lie in t he second or t hir d Nyquist zone. For inst ance, a 30MHz
wideband signal bandwidt h cent er ed ar ound a car r ier fr equency of 48.75MHz can be
digit ized at 65MSPS as shown in Figur e 5.46. In nar r owband applicat ions, t he high
sampling fr equency can be used t o achieve addit ional pr ocessing gain.
AD6640 12-BIT, 65MSPS ADC KEY SPECIFICATIONS
n n 12-bit, 65MSPS IF-SAMPLING ADC
n n Based on AD9042 architecture, but 1.5X faster CB process
n n Fully differential inputs for optimum distortion performance
n n SFDR Greater than 80dB up to 25MHz Input
n n 68dB SINAD for 60MHz IF input
n n Single +5V Supply, 695mW
n n 44-Lead TQFP Package
a 5.45
42
a
SAMPLING A 25MHz BW SIGNAL USING AD6640:
IF FREQUENCY = 48.75MHz, f
s
= 65MSPS
5.46
0
f
s
= 65MSPS
ZONE 1
IF = 48.75MHz
SIGNAL BW = 25MHz
32.5 65 97.5
f(MHz)
ZONE 2 ZONE 3
IF
Ach i evi n g Wi d e Dyn a mi c Ra n ge i n Hi gh Sp eed ADCs Usi n g Di t h er
Ther e ar e t wo fundament al limit at ions t o maximizing SFDR in a high speed ADC.
The fir st is t he dist or t ion pr oduced by t he fr ont -end amplifier and t he sample-and-
hold cir cuit . The second is t hat pr oduced by non-linear it y in t he act ual t r ansfer
funct ion of t he encoder por t ion of t he ADC. The key t o wide SFDR is t o minimize t he
non-linear it y of each.
Ther e is not hing t hat can be done ext er nally t o t he ADC t o significant ly r educe t he
inher ent dist or t ion caused by t he ADC fr ont end. However , t he non-linear it y in t he
ADC encoder t r ansfer funct ion can be r educed by t he pr oper use of dit her (ext er nal
noise which is summed wit h t he analog input signal t o t he ADC).
Dit her ing impr oves ADC SFDR under cer t ain condit ions. For example, even in a
per fect ADC, t her e is some cor r elat ion bet ween t he quant izat ion noise and t he input
signal. This can r educe t he SFDR of t he ADC, especially if t he input signal is an
exact sub-mult iple of t he sampling fr equency. Summing br oadband noise (about 1/2
LSB r ms in amplit ude) wit h t he input signal t ends t o r andomize t he quant izat ion
noise and minimize t his effect (see Figur e 5.47). In most syst ems, however , t her e is
enough noise r iding on t op of t he signal so t hat adding addit ional dit her noise is not
r equir ed. Incr easing t he wideband r ms noise level beyond an LSB will pr opor t ionally
r educe t he ADC SNR.
43
a
USING DITHER TO RANDOMIZE ADC TRANSFER FUNCTION
5.47
INPUT
SMALL
AMPLI TUDE
+
+
ADC
NOISE
GENERATOR
1/2 LSB RMS
INPUT
LARGE
AMPLI TUDE
+
-
ADC
RANDOM
NUMBER
GENERATOR
ADDER
DAC
Ot her schemes have been developed which use lar ger amount s of dit her noise t o
r andomize t he t r ansfer funct ion of t he ADC. Figur e 5.47 also shows a dit her noise
sour ce compr ised of a pseudo-r andom number gener at or which dr ives a DAC. This
signal is subt r act ed fr om t he ADC input signal and t hen digit ally added t o t he ADC
out put , t her eby causing no significant degr adat ion in SNR. An inher ent
disadvant age of t his t echnique is t hat t he allowable input signal swing is r educed as
t he amplit ude of t he dit her signal is incr eased. This r educt ion in signal amplit ude is
r equir ed t o pr event over dr iving t he ADC. It should be not ed t hat t his scheme does
not significant ly impr ove dist or t ion cr eat ed by t he fr ont -end of t he ADC, only t hat
pr oduced by t he non-linear it y of t he ADC encoder t r ansfer funct ion.
Anot her met hod which is easier t o implement , especially in wideband r eceiver s, is t o
inject a nar r owband dit her signal outside the signal band of interest as shown in
Figur e 5.48. Usually, t her e ar e no signal component s locat ed in t he fr equency r ange
near DC, so t his low-fr equency r egion is oft en used for such a dit her signal. Anot her
possible locat ion for t he dit her signal is slight ly below f
s
/2. Because t he dit her signal
occupies only a small bandwidt h r elat ive t o t he signal bandwidt h, t her e is no
significant degr adat ion in SNR, as would occur if t he dit her was br oadband.
44
INPUT
a
INJECTING OUT-OF-BAND DITHER TO IMPROVE ADC SFDR
5.48
BPF
OUT-OF-
BAND
FILTER
ADC
NOISE
GENERATOR
+
+
f
s
OUT-OF-BAND NOISE
NEAR DC OR f
s
/2
A subr anging ADC such as t he AD9042 (see Figur e 5.49) has small differ ent ial non-
linear it y er r or s t hat occur at specific r egions acr oss t he ADC r ange. For inst ance,
t he AD9042 uses a 6-bit ADC followed by a 7-bit one. Ther e ar e 64 decision point s
associat ed wit h t he main-r ange 6-bit ADC, and t hey occur ever y 15.625mV for a 1V
full scale input r ange. Figur e 5.50 shows a gr eat ly exagger at ed r epr esent at ion of
t hese non-linear it ies.
45
a
AD9042 12-BIT, 41MSPS PIPELINED SUBRANGING ADC
WITH DIGITAL ERROR CORRECTION
5.49
+
-
ANALOG
INPUT
7
12
ERROR CORRECTION LOGIC
OUTPUT REGISTERS
SHA
1
SHA
2
6-BIT
ADC
6-BIT
DAC
7-BIT
ADC
SHA
3
GAIN
12
BUFFER
REGISTER
6
6
a
AD9042 SUBRANGING POINT DNL ERRORS
(EXAGGERATED)
5.50
OUTPUT
CODE
ANALOG INPUT
15.625mV
64 LSBs
The dist or t ion component s pr oduced by t he fr ont end of t he AD9042 up t o about
20MHz analog input ar e negligible compar ed t o t hose pr oduced by t he encoder . That
46
is, the static non-linearity of the AD9042 transfer function is t he chief limit at ion t o
SFDR.
The goal is t o select t he pr oper amount of out -of-band dit her so t hat t he effect of
t hese small DNL er r or s ar e randomized acr oss t he ADC input r ange, t her eby
r educing t he aver age DNL er r or . The fir st plot shown in Figur e 5.51 shows t he
undit her ed DNL over a small por t ion of t he input signal r ange. The hor izont al axis
has been expanded t o show t wo of t he subr anging point s which ar e spaced
15.625mV (64 LSBs) apar t . The second plot shows t he DNL aft er adding 5.3mV r ms
(22 LSBs r ms) of dit her . This amount of dit her cor r esponds t o 32.5dBm (1V p-p full
scale cor r esponds t o +4dBm). It was det er mined t hat fur t her incr eases in dit her
amplit ude pr ovided no impr ovement in t he AD9042 SFDR and would only ser ve t o
cause a loss in headr oom and a decr ease in SNR.
5.51
a
AD9042 UNDITHERED AND DITHERED DNL
UNDITHERED
21.3 LSBs DITHER
1.5
1.0
-0.5
0.5
0
1.5
1.0
-0.5
0.5
0
DNL
(LSBs)
+FS -FS +FS -FS
The dit her signal was gener at ed using a volt age feedback op amp (AD8048,
3.8nV/Hz input volt age noise, 200MHz gain-bandwidt h pr oduct ) as t he noise sour ce
(see Figur e 5.52). The op amp is configur ed for a gain of +26, and t he out put noise
spect r al densit y is about 100nV/Hz over an 8MHz bandwidt h. The out put of t he
noise gener at or is t hen amplified by t he AD600 dual wideband VCA which pr ovides
a gain (in dB) which is pr opor t ional t o t he cont r ol volt age. The cont r ol volt age can be
fixed, or pr ogr ammed using a DAC as shown. The gain of t he AD600 can be set fr om
0dB t o 80dB by var ying t he cont r ol volt age fr om 0 t o +1V. The bandwidt h of t he
noise is limit ed t o about 300kHz wit h a lowpass filt er . The filt er can be eit her
passive or act ive, but r equir es at least 4 poles in or der t o at t enuat e t he out -of-band
noise. The out put of t he lowpass filt er is buffer ed wit h t he AD797 low-noise op amp
which also pr ovides a gain of +2. The filt er ed noise is summed dir ect ly int o t he input
cir cuit of t he AD9042 t hr ough a capacit or and a 1k ser ies r esist or . The net input
impedance of t he AD9042 is 50 (61.9 in par allel wit h t he 250 AD9042 int er nal
impedance).
47
5.52
DITHER NOISE GENERATOR
+
-
1000
0.1 F
a
+
-
+
-
+
-
10
100
1 F
FILM
0.1 F
61.9
AD797
NOISE
SIGNAL
301
301
AD9042
Z = 250
10
249
1 F
FILM
300kHz
LPF
DAC
AD8048
A1
A2
0 TO +1V, 0 TO 80dB GAIN
A1, A2:
1/2 AD600
100nV/ Hz
BW 8MHz
The dr amat ic impr ovement in SFDR obt ained wit h out -of-band dit her is shown in
Figur e 5.53 using a 4k FFT, wher e t he AD9042 is sampling a 19.5MHz signal (
29dBFS) at 41MSPS. Not e t hat t he SFDR wit hout dit her is appr oximat ely 80dBFS
compar ed t o 94dBFS wit h dit her , r epr esent ing a 14dB impr ovement ! This
impr ovement is also shown in t he SFDR amplit ude sweeps shown in Figur e 5.54.
Not e t he similar impr ovement .
48
5.53
a
AD9042 UNDITHERED AND DITHERED 4k FFT OUTPUT
UNDITHERED DITHERED
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 41 MSPS
AIN = 19.5MHz @ -29 dBFS
NO DITHER
2 4 6 8 8 7 5 3
FREQUENCY - MHz
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 41 MSPS
AIN = 19.5MHz @ -29 dBFS
DITHER = -32.5dBm
2 4 6 8 8 7 5 3
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L

S
C
A
L
E

-

d
B
FREQUENCY - MHz
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L

S
C
A
L
E

-

d
B
5.54
a
AD9042 UNDITHERED AND DITHERED SFDR
UNDITHERED DITHERED
W
O
R
S
T

C
A
S
E

S
P
U
R
I
O
U
S

-

d
B
c
ANALOG INPUT POWER LEVEL - dBFS
100
0
-80 0 -70 -60 -50 -40 -30 -20 -10
90
60
40
20
10
80
70
50
30
ENCODE = 41 MSPS
AIN = 19.5MHz
NO DITHER
SFDR = 80dB
REFERENCE LINE
W
O
R
S
T

C
A
S
E

S
P
U
R
I
O
U
S

-

d
B
c
ANALOG INPUT POWER LEVEL - dBFS
100
0
-80 0 -70 -60 -50 -40 -30 -20 -10
90
60
40
20
10
80
70
50
30
ENCODE = 41 MSPS
AIN = 19.5MHz
DITHER = -32.5dBm
SFDR = 80dB
REFERENCE LINE
At lower fr equencies, t he FFT size must be incr eased fr om 4k t o 128k (r educing t he
FFT noise floor by 15dB) in or der t o measur e t he dit her ed SFDR. Figur e 5.55 shows
t he effect s of dit her using a 128k FFT and a 2.5MHz input signal. The SFDR wit h
dit her is gr eat er t han 100dBFS.
49
5.55
a
AD9042 UNDITHERED AND DITHERED 128k FFT OUTPUTS
UNDITHERED
DITHERED
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L

S
C
A
L
E

-

d
B
P
O
W
E
R

R
E
L
A
T
I
V
E

T
O

A
D
C

F
U
L
L

S
C
A
L
E

-

d
B
FREQUENCY - MHz
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 41 MSPS
AIN = 2.5MHz @ -26 dBFS
NO DITHER
FREQUENCY - MHz
0
-80
-120
-40
-100
-20
-60
dc 20.5 4.1 8.2 12.3 16.4
ENCODE = 41 MSPS
AIN = 2.5MHz@-26dBFS
DITHER = -32.5dBm
Hi gh Sp eed ADC Ap p li ca t i on s i n Di gi t a l Commu n i ca t i on s Syst ems a n d
Di r ect Br oa d ca st Sa t elli t e (DBS) Set -Top Boxes
In a digit al communicat ions syst em, digit al dat a (which can be digit ized analog
signals) is for mat t ed and t r ansmit t ed ser ially over an appr opr iat e medium. The
GSM cellular t elephone syst em is an example. The ubiquit ous modem
(modulat or /demodulat or ), which PCs and FAX machines use t o t r ansmit and r eceive
dat a over t he st andar d dial-up t elephone connect ion, uses sophist icat ed modulat ion
t echniques t o place huge amount s of dat a in t he 4kHz bandwidt h t elephone channel.
Most digit al t r ansmission schemes use some for m of in-phase and quadr at ur e (I and
Q) modulat ion t o maximize t he amount of dat a t r ansmit t ed over a given channel
bandwidt h. Two examples ar e shown in Figur e 5.56 and Figur e 5.57. The fir st is
called Quadr at ur e Phase Shift Keying (QPSK) and is used in Dir ect Br oadcast
Sat ellit e syst ems. The diagr am (constellation) shows t he four possible dat a point s,
each r epr esent ing 2-bit s of binar y infor mat ion. Each point in t he const ellat ion is
called a symbol and has a specific I and Q value. In t he case of QPSK, t her e ar e t wo
bit s of infor mat ion per symbol. The symbol r at e is oft en r efer r ed t o as t he baud r at e.
For example, in QPSK, if t he symbol (or baud) r at e is 30Mbaud (1baud =
1symbol/sec), t he bit r at e is 60Mbit s/sec. It is common pr act ice t o sample t hese t ypes
of signals at t wice t he symbol (or baud) r at e. The I and Q ADC and DSP must
ident ify t he signal as r epr esent ing one of t wo possible levels, and ADCs of 4, 5, or 6-
bit s ar e commonly used in t his applicat ion for addit ional noise mar gin and t o
achieve t he over all syst em bit -er r or -r at e (BER) r equir ement .
50
a
QPSK MODULATION
5.56
01
00 10
11
Q
I
2-BITS/SYMBOL
I OR Q CHANNEL
SAMPLING
CLOCK
t
In t he QPSK syst em, t he magnit ude of each symbol is equal, and only t he phase is
modulat ed. Mor e complex modulat ion schemes such as QAM (Quadr at ur e Amplit ude
Modulat ion), use mor e symbols on t he const ellat ion and t her eby t r ansmit mor e bit s
of infor mat ion per symbol (at t he expense of mor e sensit ivit y t o noise and mor e
complex digit al signal pr ocessing). Figur e 5.57 shows a 16-QAM const ellat ion which
cont ains 4-bit s of infor mat ion per symbol. Not e t hat t he I and Q channel r eceiver
DSP must now ident ify t he signal as r epr esent ing one of t he four possible levels.
Alt hough t he 16-QAM signal car r ies mor e bit s per symbol, it is mor e sensit ive t o
noise, and t he ADC r equir es mor e r esolut ion (t ypically 8-bit s) t han for QPSK
modulat ion (t ypically 4, 5, or 6 bit s).
51
a
16-QAM MODULATION
5.57
0000
1111
Q
I
4-BITS/SYMBOL
I OR Q CHANNEL
SAMPLING
CLOCK
t
In t he digit al r eceiver , t he I and Q component s ar e separ at ed by a quadr at ur e
demodulat or and digit ized by t wo ADCs oper at ing in par allel. The ADC sampling
r at e is gener ally t wice t he symbol r at e. In t he case of Dir ect Br oadcast Sat ellit e
(DBS), t he symbol r at e is 30Mbaud (1baud = 1symbol/sec), t he bit r at e 60Mbit s/sec,
and t he ADC sampling r at e is 60MSPS. The act ual signals at t he ADC input ar e
called "eye pat t er ns" because t he int er symbol int er fer ence due t o noise and limit ed
bandwidt h smears t he level t r ansit ions so t hat t he r egions wher e t he dat a is valid
ar e locat ed in t he cent er of t he eye opening. Figur e 5.58 shows a t ypical I/Q
demodulat or followed by a dual ADC such as t he AD9066 (6-bit s, 60MSPS).
52
70MHz
IF
SIN
COS
LPF
DSP
I
Q
a
IF SAMPLING USING AD9066 6-BIT, 60MSPS ADC
5.58
I
LPF
Q
Q
I
QVCO
AD9066
ADC
FOR DBS, SYMBOL (BAUD) RATE = 30MBAUD, QPSK
SAMPLING RATE = 60MSPS
A r ecent popular consumer applicat ion of digit al communicat ions is in Dir ect
Br oadcast Sat ellit e (DBS) syst ems. A simplified block diagr am of a DBS syst em is
shown in Figur e 5.59. The object ive is t o t r ansmit up t o 150 channels of video
pr ogr amming t o home r eceiver s which use a small (18 inch) dish and an inexpensive
(less t han $500) r eceiver (set -t op box). The subscr ipt ion cost s of t he ser vices is
compat ible wit h cable TV, but pict ur e qualit y (because of digit al t r ansmission
inher ent noise immunit y) is gener ally super ior over all 150 channels.
53
a
DIRECT BROADCAST SATELLITE (DBS)
5.59
UPLINK
MPEG
COMPRESSION
VIDEO
SOURCES
DBS
SATELLITE
LNB
DOWNCONVERTER
LPF
LPF
ADC
ADC
QVCO
COS
SIN
I
Q
DSP
MPEG
DECODE
AND
DAC
BASEBAND
VIDEO
OR
CH. 3, 4 RF
70MHz
12.2 - 12.7 GHz, 150 CHANNELS
18" DISH
1GHz
LO 1
VARIABLE
LO 2
FIXED
1ST IF 2ND IF
480MHz 70MHz
MPEG encoding and decoding r educes t he dat a r at es t o fit t he channel bandwidt h.
The MPEG (Mot ion Pict ur e Exper t s Gr oup) st andar d suppor t s var ious dat a r at es
and minimizes t he bandwidt h used. For example, a t ypical 24-fr ame-per -second
NTSC-qualit y movie needs about 3Mbit s/sec aft er encoding. A mor e complex and
fast -moving show, such as a soccer game, r equir es 5 t o 6 Mbit s/sec. In a DBS
syst em, t he MPEG encoding r at e is kept at a minimum value compat ible wit h t he
ant icipat ed video signal char act er ist ics. Mult iple MPEG dat a st r eams ar e
mult iplexed and sent t hr ough a single sat ellit e t r ansponder . In addit ion, st at ist ical
mult iplexing dynamically var ies t he dat a r at e given t o each sour ce as t he pr ogr am
cont ent changes.
The sat ellit e downlink fr equency is Ku-band (12.2 t o 12.7GHz), and t he t r ansponder
out put power is about 120W (10 t o 20 t imes t hat of a t ypical communicat ions
sat ellit e which is designed for much lar ger r eceiver ant ennas). The LNB (Low Noise
Block Conver t er ) conver t s t he 12.2 t o 12.7GHz unt uned band down t o 950MHz t o
1450MHz, wher e t he signal is easier t o t une, filt er , and br ing int o t he home over
st andar d coaxial cable. The lower fr equency signal (1GHz) incur s less loss over
st andar d coaxial cable fr om t he out side ant enna t o t he inside of t he house (gener ally
50 feet or mor e) t han t he Ku-band signal (12GHz).
The set -t op box mixes t he RF (1GHz) signal down t o t he fir st fixed IF fr equency of
480MHz. The LO which dr ives t he mixer is used for channel t uning. A second fixed-
fr equency IF st age br ings t he t uned signal down t o 70MHz wher e it is
synchr onously demodulat ed int o baseband I and Q component s. The modulat ion
scheme is QPSK, t he symbol r at e is 30Mbaud, and t he ADC sampling r at e 60MSPS.
Figur e 5.60 shows a t wo-chip solut ion t o t he fr ont -end of t he set -t op box using t he
AD6461 (quadr at ur e demodulat or and baseband filt er ) and t he AD6462 (dual 5-bit
54
ADC and digit al r eceiver ). The input t o t he AD6461 is t he 480MHz DBS IF signal.
The chip-set is designed t o suppor t symbol r at es up t o 42.5Mbaud. The AD6461
ut ilizes Analog Devices' XFCB pr ocess and is packaged in 28-pin SOIC dissipat ing
about 500mW. The AD6462 ut ilizes a 0.6 micr on CMOS pr ocess and is packaged in
an 80-pin PQFP dissipat ing appr oximat ely 1.2W (oper at ing dynamically).
IF
480MHz
QVCO
SIN
COS
MATCHED
FILTER
MATCHED
FILTER
VCO AND
TUNING
CONTROL
AGC
DAC
FREQ.
SYNTH.
ADC
ADC
DEMOD
I
Q
FORWARD
ERROR
CORRECTION
SERIAL PORT
AND
CONTROL
DATA
OUT
a
NEXT-GENERATION DBS 480MHz IF SIGNAL PROCESSING
5.60
AD6461 QUADRATURE DEMOD
AND BASEBAND FILTER
AD6462 DUAL 5-BIT ADC
AND DIGITAL RECEIVER
55
REFERENCES
1. An Introduction to the Imaging CCD Array, Technical Not e 82W-4022,
Tekt r onix, Inc., Beaver t on, OR., 1987.
2. Br ad Br annon, Using Wide Dynamic Range Converters for Wide
Band Radios, RF Desi gn , May 1995, pp.50-65.
3. J oe Mit ola, The S oftware Radio Architecture, I EEE Commu n i ca t i on s
Ma ga zi n e, Vol. 33, No.5, May 1995, pp. 26-38.
4. J effer y Wepman, Analog-to-Digital Converters and Their Applications
in Radio Receivers, I EEE Commu n i ca t i on s Ma ga zi n e,
Vol. 33, No.5, May 1995, pp. 39-45.
5. Ruper t Baines, The DS P Bottleneck, I EEE Commu n i ca t i on s
Ma ga zi n e, Vol. 33, No.5, May 1995, pp. 46-54.
6. Br ad Br annon, Overcoming Converter Nonlinearities with Dither,
Ap p li ca t i on Not e AN-410, Analog Devices, 1995.
7. Chr is Keat e and Mar k O'Br ien, DBS Receiver Chip S implifies S et-Top
Box Design, RF Desi gn , November 1995, pp. 36-42.
8. Bill Schweber , Direct S atellite Broadcast, EDN, December 21,
1995, pp. 53-58.
1
SECTI ON 6
HI GH SP EED DACs AND DDS SYSTEMS
Wa l t Kest er
I NTRODUCTI ON
A fr equency synt hesizer gener at es mult iple fr equencies fr om one or mor e fr equency
r efer ences. These devices have been used for decades, especially in communicat ions
syst ems. Many ar e based upon swit ching and mixing fr equency out put s fr om a bank
of cr yst al oscillat or s. Ot her s have been based upon well under st ood t echniques
ut ilizing phase-locked loops (PLLs). This mat ur e t echnology is illust r at ed in Figur e
6.1. A fixed-fr equency r efer ence dr ives one input of t he phase compar at or . The ot her
phase compar at or input is dr iven fr om a divide-by-N count er which is in t ur n dr iven
by a volt age-cont r olled-oscillat or (VCO). Negat ive feedback for ces t he out put of t he
int er nal loop filt er t o a value which makes t he VCO out put fr equency N-t imes t he
r efer ence fr equency. The t ime const ant of t he loop is cont r olled by t he loop filt er .
Ther e ar e many t r adeoffs in designing a PLL, such a phase noise, t uning speed,
fr equency r esolut ion, et c., and t her e ar e many good r efer ences on t he subject (see
Refer ences 1, 2, and 3).
a
FREQUENCY SYNTHESIS USING
OSCILLATORS AND PHASE-LOCKED LOOPS
6.1
OSCILLATOR BANK
MIXER
MIXER
XO
1
XO
2
XO
3
XO
n
SW
f
out
PHASE-LOCKED LOOP
f
c
f
out
FIXED
FREQUENCY
REFERENCE
LOOP
FILTER
N
f
out
PHASE
COMPARATOR
VCO
= N f
c
Wit h t he widespr ead use of digit al t echniques in inst r ument at ion and
communicat ions syst ems, a digit ally-cont r olled met hod of gener at ing mult iple
fr equencies fr om a r efer ence fr equency sour ce has evolved called Dir ect Digit al
Synt hesis (DDS). The basic ar chit ect ur e is shown in Figur e 6.2. In t his simplified
model, a st able clock dr ives a pr ogr ammable-r ead-only-memor y (PROM) which
st or es one or mor e int egr al number of cycles of a sinewave (or ot her ar bit r ar y
2
wavefor m, for t hat mat t er ). As t he addr ess count er st eps t hr ough each memor y
locat ion, t he cor r esponding digit al amplit ude of t he signal at each locat ion dr ives a
DAC which in t ur n gener at es t he analog out put signal. The spect r al pur it y of t he
final analog out put signal is det er mined pr imar ily by t he DAC. The phase noise is
basically t hat of t he r efer ence clock.
The DDS syst em differ s fr om t he PLL in sever al ways. Because a DDS syst em is a
sampled dat a syst em, all t he issues involved in sampling must be consider ed:
quant izat ion noise, aliasing, filt er ing, et c. For inst ance, t he higher or der har monics
of t he DAC out put fr equencies fold back int o t he Nyquist bandwidt h, making t hem
unfilt er able, wher eas, t he higher or der har monics of t he out put of PLL-based
synt hesizer s can be filt er ed. Ther e ar e ot her consider at ions which will be discussed
shor t ly.
a
FUNDAMENTAL DIRECT DIGITAL SYNTHESIS SYSTEM
6.2
f
c
ADDRESS
COUNTER
SIN
LOOKUP
TABLE
N-BITS
CLOCK
REGISTER
LPF
DAC
f
out
LOOKUP TABLE CONTAINS SIN
DATA FOR INTEGRAL NUMBER
OF CYCLES
N-BITS
A fundament al pr oblem wit h t his simple DDS syst em is t hat t he final out put
fr equency can be changed only by changing t he r efer ence clock fr equency or by
r epr ogr amming t he PROM, making it r at her inflexible. A pr act ical DDS syst em
implement s t his basic funct ion in a much mor e flexible and efficient manner using
digit al har dwar e called a Numer ically Cont r olled Oscillat or (NCO). A block diagr am
of such a syst em is shown in Figur e 6.3.
3
a
A FLEXIBLE DDS SYSTEM
6.3
f
c
SERIAL
OR BYTE
LOAD
REGISTER
n
n
FREQUENCY CONTROL
PHASE
REGISTER
LPF
DAC
PARALLEL
DELTA
PHASE
REGISTER
M
CLOCK
n n SIN ROM
LOOKUP
TABLE
PHASE ACCUMULATOR
n
PHASE
TRUNCATION
14-16 BITS
AMPLITUDE
TRUNCATION
f
o
2
n
= f
o
M f
c
n = 24-32 BITS
N-BITS
The hear t of t he syst em is t he phase accumulator whose cont ent s is updat ed once
each clock cycle. Each t ime t he phase accumulat or is updat ed, t he digit al number ,
M, st or ed in t he delta phase register is added t o t he number in t he phase
accumulat or r egist er . Assume t hat t he number in t he delt a phase r egist er is 00...01
and t hat t he init ial cont ent s of t he phase accumulat or is 00...00. The phase
accumulat or is updat ed by 00...01 on each clock cycle. If t he accumulat or is 32-bit s
wide, 2
32
clock cycles (over 4 billion) ar e r equir ed befor e t he phase accumulat or
r et ur ns t o 00...00, and t he cycle r epeat s.
The t r uncat ed out put of t he phase accumulat or ser ves as t he addr ess t o a sine (or
cosine) lookup t able. Each addr ess in t he lookup t able cor r esponds t o a phase point
on t he sinewave fr om 0 t o 360. The lookup t able cont ains t he cor r esponding digit al
amplit ude infor mat ion for one complet e cycle of a sinewave. (Act ually, only dat a for
90 is r equir ed because t he quadr at ur e dat a is cont ained in t he t wo MSBs). The
lookup t able t her efor e maps t he phase infor mat ion fr om t he phase accumulat or int o
a digit al amplit ude wor d, which in t ur n dr ives t he DAC.
Consider t he case for n=32, and M=1. The phase accumulat or st eps t hr ough each of
2
32
possible out put s befor e it over flows. The cor r esponding out put sinewave
fr equency is equal t o t he clock fr equency divided by 2
32
. If M=2, t hen t he phase
accumulat or r egist er "r olls over " t wice as fast , and t he out put fr equency is doubled.
This can be gener alized as follows.
For an n-bit phase accumulat or (n gener ally r anges fr om 24 t o 32 in most DDS
syst ems), t her e ar e 2
n
possible phase point s. The digit al wor d in t he delt a phase
r egist er , M, r epr esent s t he amount t he phase accumulat or is incr ement ed each clock
cycle. If f
c
is t he clock fr equency, t hen t he fr equency of t he out put sinewave is equal
t o:
4
f
o
M f
c
n
=

2
.
This equat ion is known as t he DDS "t uning equat ion." Not e t hat t he fr equency
r esolut ion of t he syst em is equal t o f
c
/2
n
. For n=32, t he r esolut ion is gr eat er t han
one par t in four billion! In a pr act ical DDS syst em, all t he bit s out of t he phase
accumulat or ar e not passed on t o t he lookup t able, but ar e t r uncat ed, leaving only
t he fir st 13 t o 15 MSBs. This r educes t he size of t he lookup t able and does not affect
t he fr equency r esolut ion. The phase t r uncat ion only adds a small but accept able
amount of phase noise t o t he final out put .
The r esolut ion of t he DAC is t ypically 2 t o 4 bit s less t han t he widt h of t he lookup
t able. Even a per fect N-bit DAC will add quant izat ion noise t o t he out put . Figur e 6.4
shows t he calculat ed out put spect r um for a 32-bit phase accumulat or , 15-bit phase
t r uncat ion, and a 12-bit DAC. The value of M was chosen so t hat t he out put
fr equency was slight ly offset fr om 0.25 t imes t he clock fr equency. Not e t hat t he
spur s caused by t he phase t r uncat ion and t he finit e DAC r esolut ion ar e all at least
90dB below t he fullscale out put . This per for mance far exceeds t hat of any
commer cially available 12-bit DAC and is adequat e for most applicat ions.
a
CALCULATED OUTPUT SPECTRUM SHOWS
90dB SFDR FOR 15-BIT PHASE TRUNCATION AND
12-BIT OUTPUT DATA TRUNCATION
6.4
NORMALIZED FREQUENCY - f
OUT
/f
CLK
0
-20
-40
-60
-80
-100
-120
M
A
G
N
I
T
U
D
E

-

d
B
c
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
The basic DDS syst em descr ibed above is ext r emely flexible and has high r esolut ion.
The fr equency can be changed inst ant aneously wit h no phase discont inuit y by
simply changing t he cont ent s of t he M-r egist er . However , pr act ical DDS syst ems
fir st r equir e t he execut ion of a ser ial, or byt e-loading sequence t o get t he new
fr equency wor d int o an int er nal buffer r egist er which pr ecedes t he par allel-out put
M-r egist er . This is done t o minimize package pin count . Aft er t he new wor d is loaded
5
int o t he buffer r egist er , t he par allel-out put delt a phase r egist er is clocked, t her eby
changing all t he bit s simult aneously. The number of clock cycles r equir ed t o load t he
delt a-phase buffer r egist er det er mines t he maximum r at e at which t he out put
fr equency can be changed.
ALI ASI NG I N DDS SYSTEMS
Ther e is one impor t ant limit at ion t o t he r ange of out put fr equencies t hat can be
gener at ed fr om t he simple DDS syst em. The Nyquist Cr it er ia st at es t hat t he clock
fr equency (sample r at e) must be at least t wice t he out put fr equency. Pr act ical
limit at ions r est r ict t he act ual highest out put fr equency t o about 1/3 t he clock
fr equency. Figur e 6.5 shows t he out put of a DAC in a DDS syst em wher e t he out put
fr equency is 30MHz and t he clock fr equency is 100MHz. An ant ialiasing filt er must
follow t he r econst r uct ion DAC t o r emove t he lower image fr equency (100
30=70MHz) as shown in t he figur e.
a
6.5
ALIASING IN A DDS SYSTEM
f
c
100MHz
dB
FREQUENCY (MHz)
LPF
IMAGE
IMAGE
0 10 20 30 40 50 60 70 80 90 100 110 120 130
f
o
30MHz
sin x
x
3
3 3 4
4
4
2 2
Not e t hat t he amplit ude r esponse of t he DAC out put (befor e filt er ing) follows a
sin(x)/x r esponse wit h zer os at t he clock fr equency and mult iples t her eof. The exact
equat ion for t he nor malized out put amplit ude, A(f
o
), is given by:
A f
o
f
o
f
c
f
o
f
c
( )
sin
=

,
wher e f
o
is t he out put fr equency and f
c
is t he clock fr equency.
6
This r olloff is because t he DAC out put is not a ser ies of zer o-widt h impulses (as in a
per fect r e-sampler ), but a ser ies of r ect angular pulses whose widt h is equal t o t he
r ecipr ocal of t he updat e r at e. The amplit ude of t he sin(x)/x r esponse is down 3.92dB
at t he Nyquist fr equency (1/2 t he DAC updat e r at e). In pr act ice, t he t r ansfer
funct ion of t he ant ialiasing filt er is designed t o compensat e for t he sin(x)/x r olloff so
t hat t he over all fr equency r esponse is r elat ively flat up t o t he maximum out put DAC
fr equency (gener ally 1/3 t he updat e r at e).
Anot her impor t ant consider at ion is t hat , unlike a PLL-based syst em, t he higher
or der har monics of t he fundament al out put fr equency in a DDS syst em will fold
back int o t he baseband because of aliasing. These har monics cannot be r emoved by
t he ant ialiasing filt er . For inst ance, if t he clock fr equency is 100MHz, and t he
out put fr equency is 30MHz, t he second har monic of t he 30MHz out put signal
appear s at 60MHz (out of band), but also at 10060=40MHz (t he aliased component .
Similar ly, t he t hir d har monic (90MHz) appear s inband at 10090=10MHz, and t he
four t h at 120100MHz=20MHz. Higher or der har monics also fall wit hin t he Nyquist
bandwidt h (DC t o f
c
/2). The locat ion of t he fir st four har monics is shown in t he
diagr am.
125MSP S DDS SYSTEM (AD9850)
The AD9850 125MSPS DDS syst em (Figur e 6.6) uses a 32-bit phase accumulat or
which is t r uncat ed t o 14-bit s (MSBs) befor e being passed t o t he lookup t able. The
final digit al out put is 10-bit s t o t he int er nal DAC. The AD9850 allows t he out put
phase t o be modulat ed using an addit ional r egist er and an adder placed bet ween t he
out put of t he phase accumulat or r egist er and t he input t o t he lookup t able. The
AD9850 uses a 5-bit wor d t o cont r ol t he phase which allows shift ing t he phase in
incr ement s of 180, 90, 45, 22.5, 11.25, and any combinat ion t her eof. The device
also cont ains an int er nal high speed compar at or which can be configur ed t o accept
t he (ext er nally) filt er ed out put of t he DAC t o gener at e a low-jit t er out put pulse
suit able for dr iving t he sampling clock input of an ADC. The full scale out put
cur r ent can be adjust ed fr om 10 t o 20mA using a single ext er nal r esist or , and t he
out put volt age compliance is +1V. Key specificat ions ar e summar ized in Figur e 6.7.
7
a
AD9850 CMOS 125MSPS DDS/DAC SYNTHESIZER
6.6
SIN
LOOKUP
TABLE
10
10-BIT
DAC
PHASE
CONTROL
PHASE
ACCUMULATOR
DATA AND
CONTROL
INPUT
REGISTER
+
-
HIGH SPEED
COMPARATOR
14
32
5
5
32
ANALOG
OUT
R
SET
BYTE LOAD
8 BITS X 5
SERIAL LOAD
1 BIT X 40
WORD LOAD CLOCK
REFERENCE CLOCK IN
AD9850 DDS/DAC SYNTHESIZER KEY SPECIFICATIONS
n n 125MSPS Clock Rate
n n On-Chip 10-bit DAC and High Speed Comparator
n n DAC SFDR > 50dBc @ 40MHz Output
n n 32-bit Frequency Tuning
n n 5-bit Phase Modulation
n n Simplified Control Interface: Byte-Parallel or Serial Load
n n +5V or +3.3V Supplies
n n 380mW Dissipation @ 125MSPS on +5V Supply
(30mW Power-Down Mode)
n n 28-Pin Shrink Small Outline Package (SSOP)
a 6.7
The fr equency t uning (delt a-phase r egist er input wor d) and phase modulat ion wor ds
ar e loaded int o t he AD9850 via a par allel or ser ial loading for mat . The par allel load
8
for mat consist s of five consecut ive loads of an 8-bit cont r ol wor d (byt e). The fir st 8-
bit byt e cont r ols phase modulat ion (5-bit s), power -down enable (1-bit ), and loading
for mat (2-bit s). Byt es 2-5 compr ise t he 32-bit fr equency t uning wor d. The maximum
cont r ol r egist er updat e fr equency is 23MHz. Ser ial loading of t he AD9850 is
accomplished via a 40-bit ser ial dat a st r eam on a single pin. Maximum updat e r at e
of t he cont r ol r egist er in t he ser ial-load mode is 3MHz.
The AD9850 consumes only 380mW of power on a single +5V supply at a maximum
125MSPS clock r at e. The device is available in a 28-pin sur face mount SSOP
(Shr ink Small Out line Package).
DDS SYSTEMS AS ADC CLOCK DRI VERS
DDS syst ems such as t he AD9850 pr ovide an excellent met hod of gener at ing t he
sampling clock t o t he ADC, especially when t he ADC sampling fr equency must be
under soft war e cont r ol and locked t o t he syst em clock (see Figur e 6.8). The true DAC
out put cur r ent I
out
, dr ives a 200, 42MHz lowpass filt er which is sour ce and load
t er minat ed, t her eby making t he equivalent load 100. The filt er r emoves spur ious
fr equency component s above 42MHz. The filt er ed out put dr ives one input of t he
AD9850 int er nal compar at or . The complementary DAC out put cur r ent dr ives a 100
load. The out put of t he 100k r esist or divider placed bet ween t he t wo out put s is
decoupled and gener at es t he r efer ence volt age for t he int er nal compar at or .
The compar at or out put has a 2ns r ise and fall t ime and gener at es a TTL/CMOS-
compat ible squar e wave. The jit t er of t he compar at or out put edges is less t han 20ps
r ms. Tr ue and complement ar y out put s ar e available if r equir ed.
In t he cir cuit shown (Figur e 6.8), t he t ot al out put r ms jit t er for a 40MSPS ADC
clock is 50ps r ms, and t he r esult ing degr adat ion in SNR must be consider ed in wide
dynamic r ange applicat ions.
9
a
6.8
USING DDS SYSTEMS AS ADC CLOCK DRIVERS
DAC OUTPUT
125 MHz
FREQ.
CONTROL
AD9850
DDS/DAC
SYNTHESIZER
I
I
200
100k
42MHz
200
LPF
100k
470pF
100
-
+
200
AMP LI TUDE MODULATI ON I N A DDS SYSTEM
Amplit ude modulat ion in a DDS syst em can be accomplished by placing a digit al
mult iplier bet ween t he lookup t able and t he DAC input as shown in Figur e 6.9.
Anot her met hod t o modulat e t he DAC out put amplit ude is t o var y t he r efer ence
volt age t o t he DAC. In t he case of t he AD9850, t he bandwidt h of t he int er nal
r efer ence cont r ol amplifier is appr oximat ely 1MHz. This met hod is useful for
r elat ively small out put amplit ude changes as long as t he out put signal does not
exceed t he +1V compliance specificat ion.
10
f
c
PHASE
ACCUMULATOR
N
SIN
LOOKUP
TABLE
DAC
AM
REGISTER
N
MULTIPLIER
V
REF
OUTPUT
a
AMPLITUDE MODULATION IN A DDS SYSTEM
6.9
THE AD9830/9831 COMP LETE DDS SYSTEMS
The AD9830/9831 CMOS DDS syst ems (see Figur e 6.10) cont ain t wo fr equency
r egist er s and four phase r egist er s t her eby allowing bot h fr equency and phase
modulat ion. The r egist er s ar e loaded t hr ough a par allel micr opr ocessor por t . The
DDS chips cont ain a 32-bit phase accumulat or r egist er , 12-bit sin ROM lookup t able,
and a 10-bit DAC. The AD9830 oper at es at 50MSPS and dissipat es 250mW on t he
+5V supply. The AD9831 oper at es at 25MSPS and dissipat es 150mW on a +5V
supply and 35mW on +3V. Key specificat ions for t he devices ar e summar ized in
Figur e 6.11.
AD9830/9831, 50/25MSPS COMPLETE DDS SYSTEMS
11
SIN
ROM
Parallel Register
D0 D15
AGND
RESET
CLOCK
AVDD
WR CS A2

CONTROL REG
Register
Select MPU Interface
10-Bit DAC
IOUT
COMP
VREF
IOUT
FullScale
Control
Phase
Accumulator
(32 Bit)
SLEEP
FS ADJUST DGND
MUX
FREQ0 REG
FSELECT
FREQ1 REG
DVDD
A1 A0
PHASE2 REG
PHASE1 REG
PHASE0 REG
PHASE3 REG
12
PSEL0 PSEL1
MUX
a 6.10
AD9830/9831 DDS SYSTEMS KEY SPECIFICATIONS
n n 50MSPS (AD9830), 25MSPS (AD9831) Update Rate
n n Single +5V (AD9830), +5V/+3V (AD9831) Supply
n n 32-bit Phase Accumulator, 12-bit Address Sine ROM
n n On Chip 10-bit DAC (70dB SFDR)
n n Two On-Chip Frequency Modulation Registers
n n Four On-Chip Phase Modulation Registers
n n On-Chip Reference
n n Power Dissipation: 250mW (AD9830),
150mW (AD9831 @ +5V), 35mW (AD9831 @ +3V)
n n 48-pin TQFP
a 6.11
12
SP URI OUS FREE DYNAMI C RANGE CONSI DERATI ONS I N
DDS SYSTEMS
In many DDS applicat ions, t he spect r al pur it y of t he DAC out put is of pr imar y
concer n. Unfor t unat ely, t he measur ement , pr edict ion, and analysis of t his
per for mance is complicat ed by a number of int er act ing fact or s.
Even an ideal N-bit DAC will pr oduce har monics in a DDS syst em. The amplit ude of
t hese har monics is highly dependent upon t he r at io of t he out put fr equency t o t he
clock fr equency. This is because t he spect r al cont ent of t he DAC quant izat ion noise
var ies as t his r at io var ies, even t hough it s t heor et ical r ms value r emains equal t o
q/12 (wher e q is t he weight of t he LSB). The assumpt ion t hat t he quant izat ion
noise appear s as whit e noise and is spr ead unifor mly over t he Nyquist bandwidt h is
simply not t r ue in a DDS syst em (it is mor e apt t o be a t r ue assumpt ion in an ADC-
based syst em, because t he ADC adds a cer t ain amount of noise t o t he signal which
t ends t o "dit her " or r andomize t he quant izat ion er r or . However , a cer t ain amount of
cor r elat ion st ill exist s). For inst ance, if t he DAC out put fr equency is set t o an exact
submult iple of t he clock fr equency, t hen t he quant izat ion noise will be concent r at ed
at mult iples of t he out put fr equency, i.e., it is highly signal dependent . If t he out put
fr equency is slight ly offset , however , t he quant izat ion noise will become mor e
r andom, t her eby giving an impr ovement in t he effect ive SFDR.
This is illust r at ed in Figur e 6.12, wher e a 4096 point FFT is calculat ed based on
digit ally gener at ed dat a fr om an ideal 12-bit DAC. In t he left -hand diagr am, t he
r at io bet ween t he clock fr equency and t he out put fr equency was chosen t o be exact ly
32 (128 cycles of t he sinewave in t he FFT r ecor d lengt h), yielding an SFDR of about
78dBc. In t he r ight -hand diagr am, t he r at io was changed t o 32.25196850394 (127
cycles of t he sinewave wit hin t he FFT r ecor d lengt h), and t he effect ive SFDR is now
incr eased t o 92dBc. In t his ideal case, we obser ved a change in SFDR of 14dB just
by slight ly changing t he fr equency r at io.
13
6.12
EFFECT OF RATIO OF CLOCK TO OUTPUT FREQUENCY
ON THEORETICAL 12-BIT DAC SFDR USING 4096-POINT FFT
a
f
c
/ f
o
= 32
0 500 1000 1500 2000
0 500 1000 1500 2000
f
c
/ f
o
= 32.25196850394
Best SFDR can t her efor e be obt ained by t he car eful select ion of t he clock and out put
fr equencies. However , in some applicat ions, t his may not be possible. In ADC-based
syst ems, adding a small amount of r andom noise t o t he input t ends t o r andomize t he
quant izat ion er r or s and r educe t his effect . The same t hing can be done in a DDS
syst em as shown in Figur e 6.13 (Refer ence 5). The pseudo-r andom digit al noise
gener at or out put is added t o t he DDS sine amplit ude wor d befor e being loaded int o
t he DAC. The amplit ude of t he digit al noise is set t o about 1/2 LSB. This
accomplishes t he r andomizat ion pr ocess at t he expense of a slight incr ease in t he
over all out put noise floor . In most DDS applicat ions, however , t her e is enough
flexibilit y in select ing t he var ious fr equency r at ios so t hat dit her ing is not r equir ed.
14
a
INJECTION OF DIGITAL DITHER IN A DDS SYSTEM TO
RANDOMIZE QUANTIZATION NOISE AND INCREASE SFDR
6.13
f
c
DAC
M
V
N
= rms
PSEUDORANDOM
NUMBER
GENERATOR
ADDER
SINE
LOOKUP
TABLE
PHASE
ACCUMU-
LATOR
DELTA
PHASE
REGISTER
q
2
A non-ideal DAC will int r oduce sever al ot her mechanisms of dist or t ion. Fir st , t he
over all int egr al non-linear it y of t he DAC t r ansfer funct ion will int r oduce har monic
dist or t ion. This dist or t ion behaves much like t hat pr oduced by t he non-linear it y of
an amplifier . The dist or t ion due t o t he differ ent ial non-linear it y of t he DAC is highly
dependent upon t he nat ur e of t he differ ent ial non-linear it y and is difficult t o pr edict
mat hemat ically. The t hir d sour ce of DAC dist or t ion ar e code-dependent out put
glit ches. In a DAC t her e is a t r ansient (or glit ch) pr oduced whenever t he DAC input
code changes. This glit ch is usually wor st at midscale, wher e t he DAC makes t he
t r ansit ion bet ween t he codes 1000...000 and 0111...111, and all t he DAC bit s must
swit ch. These glit ches occur because of t he unequal t ur n-on/t ur n-off t imes of t he
DAC cur r ent swit ches. They also occur at 1/4 scale, 1/8 scale, et c., wit h decr easing
amplit ude. Because t he glit ches ar e code-dependent (hence signal-dependent ) t hey
pr oduce har monics of t he fundament al out put DAC fr equency. For inst ance, each
t ime t he sinewave cr osses t hr ough mid-scale, a glit ch occur s, t her eby pr oducing a
second har monic - since t he sinewave passes t hr ough midscale t wice each cycle. The
har monics pr oduced by t hese code-dependent glit ches fold back int o t he Nyquist
bandwidt h due t o aliasing and t her eby affect t he SFDR.
CONTRIBUTORS TO DDS DAC DISTORTION
n n Resolution
n n Integral Non-Linearity
n n Differential Non-Linearity
n n Code-Dependent Glitches
n n Ratio of Clock Frequency to Output Frequency
15
(Even in an Ideal DAC)
n n Mathematical Analysis is Difficult !
a 6.14
Low dist or t ion high-speed DACs gener ally have a specificat ion for t he ar ea of t he
wor st glit ch (called glitch impulse area). In gener al, t he smaller t he glit ch ar ea, t he
bet t er t he dist or t ion-but it is difficult t o mat hemat ically r elat e t he dist or t ion
per for mance t o t he glit ch ar ea. The glit ch impulse ar ea for low dist or t ion DACs is
usually less t han 30pV-sec. A t ypical midscale glit ch impulse is shown for t he
AD9721 DAC in Figur e 6.15.
a
AD9720/AD9721 DAC MIDSCALE GLITCH SHOWS 1.34pV-s
NET IMPULSE AREA AND SETTLING TIME OF 4.5ns
6.15
5ns/DIVISION
AD9720
I
OUT
100MHz
LPF
TEST CIRCUIT
50
The best way t o measur e DAC per for mance is wit h a spect r um analyzer , wit h a
DDS syst em used t o dr ive t he DAC (Figur e 6.16). Because t her e ar e near ly an
infinit e combinat ion of possible clock and out put fr equencies, SFDR is gener ally
specified for only a few select ed combinat ions. One met hod is t o plot t he SFDR as a
funct ion of clock fr equency for t he out put fr equency slight ly offset fr om 1/3 or 1/4 t he
clock fr equency. The small fr equency offset r andomizes t he quant izat ion noise and
also allows t he dist or t ion pr oduct s t o be easily obser ved.
16
a
TEST SETUP FOR MEASURING DAC SFDR
6.16
f
c
PC
STABLE
FREQUENCY
REFERENCE
DDS LATCH DAC
SPECTRUM
ANALYZER
f
o
N
N
PARALLEL OR
SERIAL PORT
Not e t hat for t he out put slight ly offset fr om f
c
/3, t he even har monics will be aliased
ver y close t o t he out put signal as shown in Figur e 6.17. Similar ly, for t he out put
slight ly offset fr om f
c
/4, t he odd har monics will fall close t o t he out put fr equency
(Figur e 6.18).The SFDR at f
c
/3 is usually consider ed a wor se case condit ion and is
oft en plot t ed as a funct ion of clock fr equency as shown in Figur e 6.19 for t he
AD9721 10-bit , 100MSPS TTL-compat ible DAC.
17
a
LOCATION OF EVEN HARMONICS FOR
f
o
= f
c
/ 3 - f
6.17
f
o
10
4 2
8
f
f
c
3
a
LOCATION OF ODD HARMONICS FOR
f
o
= f
c
/ 4 - f
6.18
f
o
9 5 3 7
f
f
c
4
18
a
SFDR OF AD9721 10-BIT DAC FOR
f
o
~ f
c
/ 3 (BANDWIDTH: DC TO f
c
/ 2)
6.19
SFDR
(dBc)
CLOCK FREQUENCY (MHz)
80
70
60
50
40
20 40 60 80 100 0
HI GH SP EED LOW DI STORTI ON DAC ARCHI TECTURES
Because of t he emphasis in communicat ions syst ems for DDS DACs wit h high
SFDR, much effor t has been placed on det er mining opt imum DAC ar chit ect ur es.
Pr act ically all low dist or t ion high speed DACs make use of some for m of non-
sat ur at ing cur r ent -mode swit ching. A st r aight binar y DAC wit h one cur r ent swit ch
per bit pr oduces code-dependent glit ches as discussed above and is cer t ainly not t he
most opt imum ar chit ect ur e (Figur e 6.20). A DAC wit h one cur r ent sour ce per code
level can be shown not t o have code-dependent glit ches, but it is not pr act ical t o
implement for high r esolut ions. However , t his per for mance can be appr oached by
decoding t he fir st few MSBs int o a "t her momet er " code and have one cur r ent swit ch
per level. For example, a 5-bit t her momet er DAC would have an ar chit ect ur e similar
t o t hat shown in Figur e 6.21.
19
a
6.20
5-BIT BINARY DAC ARCHITECTURES
R (CAN BE EXTERNAL)
I I I I I I
I/2
I/4 I/8 I/16
OUTPUT OUTPUT
MSB
MSB
R
R
R R
R 2R 2R
2R
a
5-BIT "THERMOMETER" OR "FULLY-DECODED" DAC
6.21
CLOCK
CURRENT
OUTPUT
31-BIT
LATCH
31
EQUAL
CURRENT
SWITCHES
5-TO-31
DECODE
LOGIC
5-BIT
LATCH
MSB
LSB
31
LINES
31
LINES
The input binar y wor d is lat ched and t hen decoded int o 31 out put s which dr ive a
second lat ch. The out put of t he second lat ch dr ives 31 equally weight ed cur r ent
swit ches whose out put s ar e summed t oget her . This scheme effect ively r emoves
near ly all t he code-dependence of t he out put glit ch. The r esidual glit ch t hat does
occur at t he out put is equal r egar dless of t he out put code change and can be filt er ed.
20
The dist or t ion mechanisms associat ed wit h t he full-decoded ar chit ect ur e ar e
pr imar ily asymmet r ical out put slewing, finit e swit ch t ur n-on and t ur n-off t imes, and
int egr al nonlinear it y.
The obvious disadvant age of t his t ype of t her momet er DAC is t he lar ge number of
lat ches and swit ches r equir ed t o make a 12, 10, or even 8-bit DAC. However , if t his
t echnique is used on t he 5 MSBs of an 8, 10, or 12-bit DAC, a significant r educt ion
in t he code-dependent glit ch is possible. This pr ocess is called segmentation and is
quit e common in low dist or t ion DACs.
Figur e 6.22 shows a scheme wher eby t he fir st 5 bit s of a 10-bit DAC ar e decoded as
descr ibed above and dr ive 31 equally weight ed swit ches. The last 5 bit s ar e der ived
fr om binar ily weight ed cur r ent sour ces. Equally weight ed cur r ent sour ces dr iving an
R/2R r esist or ladder could be used t o der ive t he LSBs, however , t his appr oach
r equir es t hin film r esist or s which ar e not gener ally available on a low-cost CMOS
pr ocess. Also, t he use of R/2R net wor ks lower s t he DAC out put impedance, t her eby
r equir ing mor e dr ive cur r ent t o develop t he same volt age acr oss a fixed load
r esist ance.
CURRENT
OUTPUT
CLOCK
10-BIT
LATCH
36-BIT
LATCH
FULLY
DECODED
MSB
DAC
MSB
DECODE
5
31 31 5
10
BINARY
LSB
DAC
5
a
10-BIT SEGMENTED DAC
6.22
The AD9850 int er nal 10-bit DAC uses t wo major st ages of segment at ion as shown
in Figur e 6.23. The fir st 5 bit s (MSBs) ar e fully decoded and dr ive 31 equally
weight ed cur r ent swit ches (320A each). The next 4 bit s ar e decoded int o 15 lines
which dr ive 15 cur r ent swit ches, each supplying 20A (1/16 t he cur r ent supplied by
each MSB swit ch). The LSB is lat ched and dr ives a single cur r ent swit ch which
supplies 10A (1/32 t he cur r ent supplied by each MSB swit ch). A t ot al of 47 cur r ent
swit ches and lat ches ar e r equir ed t o implement t his ar chit ect ur e.
21
CLOCK
10-BIT
LATCH
47-BIT
LATCH
31
CURRENT
SWITCHES
320 A
15
CURRENT
SWITCHES
20 A
1
CURRENT
SWITCH
10 A
BITS 1-5
DECODE
5-TO-31
BITS 6-9
DECODE
4-TO-15
LSB 1 1
15
15
4
31 31 5
10
CURRENT
OUTPUT
FS =
10.23mA
a
AD9850 10-BIT CMOS CURRENT SWITCH DAC CORE
6.23
The basic cur r ent swit ching cell is made up of a differ ent ial PMOS t r ansist or pair as
shown in Figur e 6.24. The differ ent ial pair s ar e dr iven wit h low-level logic t o
minimize swit ching t r ansient s and t ime skew. The DAC out put s ar e symmet r ical
differ ent ial cur r ent s which help t o minimize even-or der dist or t ion pr oduct s
(especially which dr iving a differ ent ial out put such as a t r ansfor mer or an op amp
differ ent ial I/V conver t er ).
The over all ar chit ect ur e of t he AD9850 is an excellent t r adeoff bet ween
power /per for mance and allows t he ent ir e DDS funct ion t o be implement ed on a
st andar d CMOS pr ocess wit h no t hin film r esist or s. Single-supply oper at ion on
+3.3V or +5V makes t he device ext r emely at t r act ive for por t able and low power
applicat ions. The SFDR per for mance is t ypically 60, 55, and 45dBc for out put
fr equencies of 1, 20, and 40MHz, r espect ively (clock fr equency = 125MSPS).
22
a
6.24
PMOS TRANSISTOR CURRENT SWITCHES
R
L
+V
S
R
L
The AD9760 (10-bit ), AD9762 (12-bit ) and AD9764 (14-bit ) 100MSPS DACs ut ilize
t he same basic swit ching cor e as t he AD9850. This family of DACs is pin-compat ible,
and offer s except ional AC and DC per for mance. They oper at e on single +5V or +3V
supplies and cont ain on-chip lat ches, r efer ence, and ar e ideal for t he t r ansmit
channel in wir eless basest at ions, ADSL/HFC modems, and DDS applicat ions. Key
specificat ions for t he family ar e summar ized in Figur e 6.25.
AD9760/9762/9764 FAMILY OF 100MSPS DACs
n n Pin-Compatible 10-bit (AD9760), 12-bit (AD9762),
and 14-bit (AD9764)
n n SFDR for 15MHz Output: -60dBc
n n Low Glitch Impulse: 5pVsec
n n On-Chip Reference
n n Single +5V or +3V Supplies
n n Power Dissipation: 175mW @ 5V
n n Power-Down Mode: 30mW
a 6.25
23
I MP ROVI NG SF DR USI NG SAMP LE-AND-HOLD
DEGLI TCHERS
High-speed sample-and-hold amplifier s (such as t he AD9100 and AD9101) can be
used t o deglit ch DAC out put s as shown in Figur e 6.26. J ust pr ior t o lat ching new
dat a int o t he DAC, t he SHA is put int o t he hold mode so t hat t he DAC swit ching
glit ches ar e isolat ed fr om t he out put . The swit ching t r ansient s pr oduced by t he SHA
ar e code-independent and occur at t he clock fr equency and hence ar e easily filt er ed.
However , gr eat car e must be t aken so t hat t he r elat ive t iming bet ween t he SHA
clock and t he DAC updat e clock is opt imum. In addit ion, t he dist or t ion per for mance
of t he SHA must be at least 6 t o 10dB bet t er t han t he DAC, or no impr ovement in
SFDR will be r ealized. Achieving good r esult s using an ext er nal SHA deglit cher
becomes incr easingly mor e difficult as clock fr equencies appr oach 100MSPS.
DAC
INPUT
a
6.26
SAMPLE-AND-HOLD (SHA) USED AS DAC DEGLITCHER
OUTPUT
DAC
OUTPUT
SHA
MODE
SHA
OUTPUT
T
T
H
T
H
T
DAC SHA
MODE CONTROL
0111 . . . 1
1000 . . . 0
H
The AD6742 is a 12-bit , 65MSPS low dist or t ion DAC wit h on-chip SHA deglit cher
designed for communicat ions applicat ions. This DAC is fabr icat ed on t he XFCB
pr ocess and pr ovides 75dB SFDR for a 20MHz out put . A funct ional diagr am is
shown in Figur e 6.27, and key specificat ions in Figur e 6.28.
AD6742 12-BIT, 65MSPS DEGLITCHED DAC
24
DIGITAL DIGITAL INPUT INPUT STAGES STAGES AND AND LATCHES LATCHES
- - 2 2 . . 4 4 V V
R RE EF F. .
A A M M P P
D11 D11 D D1 1 0 0 D D 9 9 D D 8 8 D D 7 7 D D 6 6 D D 5 5 D D 4 4 D D 3 3 D D 2 2 D D1 1 D D 0 0
( ( M M S S B B ) )
( ( L L S SB B ) )
V V C C C C G G N N D D V V E E E E
C CL L O O C C K K C CL L O OC C K K
V V R R E E F F R RE E F F I I N N B B Y Y P P A A S S S S D D A A C C R R E E F F
D D A A T T A A
R RE EF F. . C CU UR RR RE EN NT T S SO OU UR RC CE ES S/ / S SW WI I T TC CH HE ES S
I I N NT T E E R RN NA A L L
T T I I M M I I N N G G
V V O O U U T T
R R- - 2 2 R R
N NE ET TW WO OR RK K S S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D DR RE E F F
T T/ / H H
R R
L L
V V
R R
L L
V V
I I ( ( D D1 1 1 1- - D D5 5 ) ) I I ( ( D D 4 4 - - D D 0 0 ) ) V V E E E E
I I R RE E F F
R R
SET SET
a 6.27
AD6742 12-BIT, 65MSPS DAC KEY SPECIFICATIONS
n n 12-bit, 65MSPS Communications DAC
n n Ideal for Wideband Multichannel Transmit Path
n n High SFDR: 78dB (typ) @ 20MHz Output, 65MSPS Update
n n Fabricated on XFCB process
n n On-Chip Reference
n n Dual 5V Supplies, 900mW power dissipation
a 6.28
HI GH SP EED I NTERP OLATI NG DACS
Consider a DDS syst em which oper at es at a clock fr equency of 100MSPS and
out put s a 30MHz sinewave (see Figur e 6.29). The fir st aliased (or image) fr equency
occur s at 10030 = 70MHz. Assume we wish t he ant ialiasing filt er t o at t enuat e t his
image fr equency component by 60dB. The filt er must go fr om a passband of 30MHz
t o 60dB st opband at t enuat ion over t he t r ansit ion band lying bet ween 30 and 70MHz
(appr oximat ely one oct ave). A But t er wor t h filt er design gives 6dB at t enuat ion per
oct ave for each pole. Ther efor e, a minimum of 10 poles is r equir ed t o pr ovide t he
desir ed at t enuat ion. Filt er s become even mor e complex as t he t r ansit ion band
becomes nar r ower .
25
a
6.29
LPF REQUIRED TO REJECT IMAGE FREQUENCY
f
c
100MHz
dB
FREQUENCY (MHz)
LPF
IMAGE
IMAGE
0 10 20 30 40 50 60 70 80 90 100 110 120 130
f
o
30MHz
TRANSITION
BAND
-60
0
In ADC-based syst ems, over sampling can ease t he r equir ement s on t he ant ialiasing
filt er , and a sigma-delt a ADC has t his inher ent advant age. In a DAC-based syst em
(such as DDS), t he concept of int er polat ion can be used in a similar manner . This
concept is common in digit al audio CD player s, wher e t he basic updat e r at e of t he
dat a fr om t he CD is about 44kSPS. "Zer os" ar e inser t ed int o t he par allel dat a,
t her eby incr easing t he effect ive updat e r at e t o 4-t imes, 8-t imes, or 16-t imes t he
fundament al t hr oughput r at e. The 4x, 8x, or 16x dat a st r eam is passed t hr ough a
digit al int er polat ion filt er which gener at es t he ext r a dat a point s. The high
over sampling r at e moves t he image fr equencies higher , t her eby allowing a less
complex filt er wit h a wider t r ansit ion band.
The same concept can be applied t o a high speed DDS DAC. Assume a t r adit ional
DAC is dr iven at an input wor d r at e of 30MSPS (see Figur e 6.30). The maximum
r ealizable DAC out put fr equency is about 10MHz. The image fr equency component
at 3010 = 20MHz must be at t enuat ed by t he analog ant ialiasing filt er , and t he
t r ansit ion band of t he filt er is 10 t o 20MHz.
Assume t hat we incr ease t he updat e r at e t o 60MSPS by inser t ing a "zer o" bet ween
each or iginal dat a sample. The par allel dat a st r eam is now 60MSPS and is passed
t hr ough t he digit al int er polat ion filt er which comput es t he addit ional dat a point s.
The r esponse of t he digit al filt er r elat ive t o t he 2-t imes over sampling fr equency is
shown in Figur e 6.30. The analog ant ialiasing filt er t r ansit ion zone is now 10 t o
50MHz (t he fir st image occur s at 2f
c
f
o
=6010=50MHz).
26
a
6.30
f
c
= 30MSPS AND f
c
= 60MSPS
f
CLOCK = 30MSPS
dB
IMAGE
10 20 30 40 50 60 70 80
f
o
ANALOG LPF
10 20 30 40 50 60 70 80
IMAGE
ANALOG
LPF
FREQUENCY (MHz)
IMAGE
IMAGE
IMAGE
IMAGE
f
o
f
CLOCK = 60MSPS
dB
The AD977x is a 4-t imes over sampling int er polat ing 10-bit DAC, and a simplified
block diagr am is shown in Figur e 6.31. The device is designed t o handle 10-bit input
wor d r at es up t o about 30MSPS. The int er nal digit al filt er consist s of a 15-t ap filt er
oper at ing at 2f
c
followed by a 7-t ap filt er oper at ing at 4f
c
. The out put wor d r at e is
120MSPS, put t ing t he image fr equency at 4f
c
f
o
=12010=110MHz. SFDR of t he
DAC for a 10MHz out put is appr oximat ely 60dBc.
27
a
INCREASING THE DAC THROUGHPUT RATE BY "K"
USING A PLL AND A DIGITAL INTERPOLATION FILTER
(INTERPOLATING DAC)
6.31
f
o
Kf
c
f
c
LATCH
LATCH DAC
LPF
DIGITAL
INTERPOLATION
FILTER
PLL
10
10 10
10
TYPICAL APPLICATION: f
c
= 33MSPS
f
o
= 10MHz
K = 4 OR 8
QP SK SI GNAL GENERATI ON USI NG DDS (AD9853)
The AD9853 is a digit al Quadr at ur e Phase Shift Keying (QPSK) modulat or useful in
t he 5 t o 40MHz r et ur n pat h t r ansmit t er in a hybr id fiber coax (HFC) CATV cable
modem applicat ion (see Figur e 6.32). This allows asynchr onous dat a t r ansfer over
t he HFC cable plant . The device t akes t he ser ial QPSK dat a input , split s it int o an
in-phase (I) and quadr at ur e (Q) signal. The I and Q channel dat a is t hen filt er ed and
passed t hr ough a digit al quadr at ur e modulat or . The quadr at ur e modulat or s ar e
dr iven by t he sine and cosine out put s fr om t he DDS sect ion. The modulat or out put s
ar e t hen r ecombined digit ally and t hen conver t ed int o analog by an int er nal 10-bit
DAC. The r esult ing QPSK const ellat ion is shown in Figur e 6.33. This scheme of
modulat ion is quit e common, and r esult s in r elat ively high noise immunit y. Key
specificat ions for t he AD9853 ar e given in Figur e 6.34.
28
REF CLOCK INPUT
140MSPS DDS AND CONTROL FUNCTIONS
CLOCKS
X4 PLL
I
Q
MUX
FIR
FILTER
FIR
FILTER
INTERPOLATING
FILTER
INTERPOLATING
FILTER
10
10-BIT
DAC
SIN COS
QPSK
FORMAT
2
SERIAL
QPSK
INPUT
BURST
MODE
CONTROL
MASTER
RESET
FREQ.
UPDATE
WORD
LOAD
CLOCK
32-BIT FREQ.
TUNING AND
CONTROL WORD
a
AD9853 DIGITAL QPSK MODULATOR
6.32
a
QPSK CONSTELLATION
6.33
Q
I
01
00
10
11
AD9853 DIGITAL QPSK MODULATOR KEY SPECIFICATIONS
29
n n Performs Transmit Function for QPSK 5-40MHz
Hybrid Fiber Coax (HFC) Return Path
n n Includes Raised Cosine Pulse-Shaping Filter
(Alpha = 0.5) and Interpolation Filters
n n 140MSPS Clock Frequency
n n 46dBc SFDR @ 40MHz Output
n n +5V or +3.3V Operation
n n 300mW Dissipation @ 125MSPS Clock Frequency
(30mW Power-Down Mode)
n n 28-Pin SSOP Surface-Mount Package
a 6.34
30
REFERENCES
1. R.E. Best , P h a se-Lock ed Loop s, McGr aw-Hill, New Yor k, 1984.
2. F.M. Gar dner , P h a selock Tech n i qu es, 2nd Edit ion, J ohn Wiley,
New Yor k, 1979.
3. Phase-Locked Loop Design Fundamentals, Applicat ions Not e AN-535,
Mot or ola, Inc.
4. Th e ARRL Ha n d book for Ra d i o Ama t eu r s, Amer ican Radio
Relay League, Newingt on, CT, 1992.
5. Richar d J . Ker r and Lindsay A. Weaver , Pseudorandom Dither for
Frequency S ynthesis Noise, Unit ed St at es Pat ent Number 4,901,265,
Febr uar y 13, 1990.
6. Henr y T. Nicholas, III and Henr y Samueli, An Analysis of the Output
S pectrum of Direct Digital Frequency S ynthesizers in the Presence of
Phase-Accumulator Truncation, I EEE 41st An n u a l F r equ en cy Con t r ol
Symp osi u m Di gest of P a p er s, 1987, pp. 495-502, IEEE Publicat ion No.
CH2427-3/87/0000-495.
7. Henr y T. Nicholas, III and Henr y Samueli, The Optimization of Direct
Digital Frequency S ynthesizer Performance in the Presence of Finite Word
Length Effects, I EEE 42n d An n u a l F r equ en cy Con t r ol Symp osi u m
Di gest of P a p er s, 1988, pp. 357-363, IEEE Publicat ion No. CH2588-
2/88/0000-357.
1
SECTI ON 7
HI GH SP EED HARDWARE DESI GN
TECHNI QUES
Wa l t Kest er , J a m es Br ya n t , Wa l t J u n g, Ad ol f o
Ga r ci a , J oh n McDon a l d , J oe Bu xt on
ANALOG CI RCUI T SI MULATI ON
Wa l t Kest er , J oe Bu xt on
In r ecent year s t her e has been much pr essur e placed on syst em designer s t o ver ify
t heir designs wit h comput er simulat ions befor e commit t ing t o act ual pr int ed cir cuit
boar d layout s and har dwar e. Simulat ing complex digit al designs is ext r emely
beneficial, and ver y oft en, t he pr ot ot ype phase can be eliminat ed ent ir ely. However ,
bypassing t he pr ot ot ype phase in high-speed/high-per for mance analog or mixed-
signal cir cuit designs can be r isky for a number of r easons.
For t he pur poses of t his discussion, an analog cir cuit is any cir cuit which uses ICs
such as op amps, inst r ument at ion amps, pr ogr ammable gain amps (PGAs), volt age
cont r olled amps (VCAs), log amps, mixer s, analog mult iplier s, et c. A mixed-signal
cir cuit is an A/D conver t er (ADC), D/A conver t er (DAC), or combinat ions of t hese in
conjunct ion wit h some amount of digit al signal pr ocessing which may or may not be
on t he same IC as t he conver t er s.
Consider a t ypical IC oper at ional amplifier . It may cont ain some 20-40 t r ansist or s,
almost as many r esist or s, and a few capacit or s. A complet e SPICE (Simulat ion
Pr ogr am wit h Int egr at ed Cir cuit Emphasis, see Refer ence 1) model will cont ain all
t hese component s, and pr obably a few of t he mor e impor t ant par asit ic capacit ances
and spur ious diodes for med by t he var ious junct ions in t he op-amp chip. For high-
speed ICs, t he package and wir ebond par asit ics may also be included. This is t he
t ype of model t hat t he IC designer uses t o opt imize t he device dur ing t he design
phase and is t ypically r un on a CAD wor kst at ion. Because it is a det ailed model, it
will be r efer r ed t o as a micromodel. In simulat ions, such a model will behave ver y
much like t he act ual op-amp, but not exact ly.
The IC designer uses t r ansist or and ot her device models based on t he act ual pr ocess
upon which t he component is fabr icat ed. Semiconduct or manufact ur er s invest
consider able t ime and money developing and r efining t hese device models so t hat
t he IC designer s can have a high degr ee of confidence t hat t he fir st silicon will wor k
and t hat mask changes (cost ing addit ional t ime and money) r equir ed for t he final
manufact ur ed pr oduct ar e minimized.
However , t hese device models ar e not published, neit her ar e t he IC micromodels, as
t hey cont ain pr opr iet ar y infor mat ion which would be of use t o ot her semiconduct or
companies who might wish t o copy or impr ove on t he design. It would also t ake far
t oo long for a simulat ion of a syst em cont aining sever al ICs (each r epr esent ed by it s
own micr omodel) t o r each a useful r esult . SPICE micr omodels of analog ICs oft en
2
fail t o conver ge (especially under t r ansient condit ions), and mult iple IC cir cuit s
make t his a gr eat er possibilit y.
For t hese r easons, t he SPICE models of analog cir cuit s published by manufact ur er s
or soft war e companies ar e macromodels (as opposed t o micromodels), which simulat e
t he major feat ur es of t he component , but lack fine det ail. Most manufact ur er s of
linear ICs (including Analog Devices) pr ovide t hese macr omodels for component s
such as oper at ional amplifier s, analog mult iplier s, r efer ences, et c. (Refer ence 2 and
3). These models r epr esent approximations t o t he act ual cir cuit , and par asit ic effect s
such as package capacit ance and induct ance and PC boar d layout ar e r ar ely
included. The models ar e designed t o wor k wit h var ious ver sions of SPICE
simulat ion pr ogr ams such as PSpice (Refer ence 4) and r un on wor kst at ions or
per sonal comput er s. The models ar e simple enough so t hat cir cuit s using mult iple
ICs can be simulat ed in a r easonable amount of comput at ion t ime and wit h good
cer t aint y of conver gence. Consequent ly, SPICE modeling does not always r epr oduce
t he exact per for mance of a cir cuit and should always be ver ified exper iment ally
using a car efully built pr ot ot ype.
Finally, t her e ar e mixed-signal ICs such as A/D and D/A conver t er s which have no
SPICE models, or if t hey exist , t he models do not simulat e dynamic per for mance
(Signal-t o-noise, effect ive bit s, et c.), and pr ot ot ypes of cir cuit s using t hem should
always be built .
SPICE SIMULATIONS:
MACROMODEL OR MICROMODEL?
METHODOLOGY ADVANTAGES DISADVANTAGES
MACROMODEL Ideal Elements
Model the Device
Behavior
Fast Simulation
Time, Easy to
Modify
May Not Model All
Characteristics
MICROMODEL Fully
Characterized
Transistor Level
Most Complete
Model
Slow Simulation,
Difficulty in
Convergence
Not Available to
Customers
a 7.1
Th e ADSp i ce Mod el
The ADSpice model was developed t o advance t he st at e-of-t he-ar t in op amp
macr omodelling and pr ovide a t ool for designer s t o simulat e accur at ely t heir cir cuit s.
Pr eviously, t he dominant model ar chit ect ur e was t he Boyle model (Refer ence 3).
However , t his model was developed over 20 year s ago and does not accur at ely model
many of t oday's higher speed amplifier s. The pr imar y r eason for t his is t hat t he
Boyle model has only t wo fr equency shaping poles and no zer oes. In cont r ast , t he
3
ADSpice model has an open ar chit ect ur e t hat allows for unlimit ed poles and zer oes,
leading t o much mor e accur at e AC and t r ansient r esponses.
The ADSpice model is compr ised of t hr ee main por t ions: t he input and gain st age,
t he pole/zer o st ages, and t he out put st age. The input st age shown in Figur e 7.2 uses
t he only t wo t r ansist or s in t he ent ir e model. These ar e needed t o model pr oper ly an
op amp's differ ent ial input st age char act er ist ics. Alt hough t he example her e uses
NPN t r ansist or s, t he input st age can easily be modified t o include PNP, J FET, or
CMOS devices. The r est of t he input st age uses simple SPICE element s such as
r esist or s, capacit or s, and cont r olled sour ces.
ADSpice INPUT AND GAIN STAGE MODEL
7.2
a a
V
D
OPEN LOOP GAIN = gm
1
R7
I
OS
Vd
C
IN
V
CS
R3
V+
V-
I
3
2
IN+
R4
R5 R6
gm
1
R7
C3
EREF
IN-
1
R1
R2
C2
Q1
Q2
+ -
+
-
+ -
An example of a cont r olled sour ce is gm
1
in t he gain st age, which is a volt age
cont r olled cur r ent sour ce. It senses t he differ ent ial collect or volt age fr om t he input
st age and conver t s t hat t o a cur r ent . When t he cur r ent flows t hr ough R7, a single-
ended volt age is pr oduced. By making t he pr oduct of gm
1
and R7 equal t o t he open
loop gain, t he ent ir e open-loop gain is pr oduced in t he gain st age, which means t hat
all ot her st ages ar e set t o unit y gain. This leads t o significant flexibilit y in adding
and delet ing st ages.
Following t he gain st age ar e an unlimit ed number of pole / zer o st ages and t heir
combinat ions. The t ypical t opology of t hese st ages is shown in Figur e 7.3, which is
similar t o t he gain st age. The main differ ence is t hat now t he pr oduct of gm
2
t imes
R8 is equal t o unit y. The pole or zer o fr equency is set by t he par allel combinat ion of
t he r esist or and capacit or , R8-C4 for t he pole and Rg-C5 for t he zer o. Because t hese
st ages ar e unit y gain, any number of t hem can be added or delet ed wit hout affect ing
t he low fr equency r esponse of t he model. Inst ead, t he high fr equency gain and phase
r esponse can be t ailor ed t o mat ch accur at ely t he act ual amplifier 's r esponse. The
benefit s ar e especially appar ent in closed loop pulse r esponse and st abilit y analysis.
4
POLE AND ZERO STAGE
7.3 a
gm
2
EREF
+
-
+
-
+
- E
1
EREF
POLE
gm
2
R8 = 1
R8
C4
ZERO
R10
Rg
C5
E
1
R10
Rg + R10
= 1
The out put st age in Figur e 7.4 not only models t he open loop out put impedance at
DC but wit h t he inclusion of an induct or also models t he r ise in impedance at high
fr equencies. Addit ionally, t he out put cur r ent is cor r ect ly r eflect ed in t he supply
cur r ent s. This is a significant impr ovement over t he Boyle model because now t he
power consumpt ion of t he cir cuit under load can be analyzed accur at ely.
Fur t her mor e, cir cuit s t hat use t he supply cur r ent s for feedback can also be
simulat ed.
5
I
SY
OUTPUT STAGE
7.4
a a
D7
+ -
V
X
Rg
D5
OUTPUT IMPEDANCE = +sL
O
R11 + R12
2
+ -
V5
V6
D6
D10
gm
6
gm
4
gm
3
R12
L
O
V
O
R11
gm
5
D8
V+
R13
R14
D7
V-
As an illust r at ion of using t he ADSpice model t o pr edict cir cuit per for mance, t he
AD847 op amp (50MHz unit y gain-bandwidt h pr oduct ) out put was loaded in a 65pF
capacit or and t he r esponse measur ed (bot h in ADSpice and in t he cir cuit ). The
r esult s shown in Figur e 7.5 illust r at e good cor r elat ion bet ween t he simulat ed and
t he act ual r esponse. As an addit ional example, ext r a par asit ic capacit ances wer e
added as shown in Figur e 7.6, and t he simulat ed and act ual r esponses compar ed.
Again, not e t he excellent gener al agr eement .
6
AD847 PULSE RESPONSE
7.5
a a
50
65pF
(A)
Properly laid out PC board and simulation agree closely
845
AD847
+
-
(B) (C)
0ns 100ns 200ns 300ns
Time
200mV
100mV
0mV
-100mV
-200mV
PC BOARD PARASITICS WILL ALTER THE RESULTS
7.6
a a
50
65pF
(A)
Parasitic capacitances worsen the circuit's response
Properly modelling the parasitics in SPICE yields good results
845
(B) (C)
0ns 100ns 200ns 300ns
Time
200mV
100mV
0mV
-100mV
-200mV
AD847
+
-
8pF
8pF
2pF
Ot h er Fea t u r es of ADSp i ce Mod els
In addit ion t o offer ing models of op amps (bot h volt age and cur r ent feedback), which
allow simulat ion of AC and DC per for mance, Analog Devices has included noise in
many of it s amplifier models. The capabilit y t o model a cir cuit 's noise per for mance in
SPICE can be appr eciat ed by anyone who has t r ied t o analyze noise by hand. A
7
complet e analysis is a ver y involved and t edious t ask which r equir es calculat ing all
t he individual noise cont r ibut or s and r eflect ing t hem t o t he input or out put . The
pr ocedur e is fur t her complicat ed by t he fact t hat noise gain is gener ally a funct ion of
fr equency and can significant ly affect r esult s if not car efully consider ed.
To gr eat ly simplify t his t ask, t he ADSpice model was enhanced t o include noise
gener at or s which accur at ely pr edict t he br oadband and 1/f noise of t he act ual
amplifier . Noise is cur r ent ly modeled in a number of ADI op amps, var iable gain
amplifier s, and volt age r efer ences. For fur t her discussion on t he noise model det ails,
see Refer ence 2.
In addit ion t o amplifier s, ADSpice models exist for inst r ument at ion amplifier s,
analog mult iplier s, volt age r efer ences, analog swit ches, mult iplexer s, mat ched
t r ansist or s, and buffer s. A complet e set of ADSpice models is available fr om Analog
Devices upon r equest .
ADSpice will give good appr oximat ions t o act ual per for mance, if used cor r ect ly.
However , t he user must include t he ext er nal component s and par asit ics which may
affect t he device per for mance in t he cir cuit . This becomes a difficult t ask at
fr equencies much above 100MHz, and caut ion must be used in int er pr et ing t he
simulat ion r esult s. Ther e is no subst it ut e for pr ot ot yping at t hese fr equencies.
While pulse and fr equency r esponse can be successfully simulat ed using t he
ADSpice models, dist or t ion per for mance cannot be pr edict ed since non-linear effect s
ar e not included in t he models. As ment ioned pr eviously, models for ADCs and DACs
ar e not available due t o t he difficult y in modeling t heir AC per for mance.
SUMMARY: ADSpice FEATURES
n n Transistor-Level Input Stage Model
n n Unlimited Poles and Zeros
n n Noise is Included in Some Models
n n Distortion is not Modeled
n n Over 500 Models Exist for:
u u Amplifiers
u u Instrumentation Amplifiers
u u Analog Multipliers
u u Voltage References
u u VCAs
u u Multiplexers and Switches
n n But There is no Substitute for a Good Prototype!!
a 7.7
8
P ROTOTYP I NG TECHNI QUES
J a m es Br ya n t , Wa l t Kest er
The basic pr inciple of a br eadboar d or pr ot ot ype is t hat it is a temporary st r uct ur e,
designed t o t est t he per for mance of a cir cuit or syst em, and must t her efor e be easy
t o modify.
Ther e ar e many commer cial pr ot ot yping syst ems, but almost all of t hem ar e
designed t o facilit at e t he pr ot ot yping of digital syst ems, wher e noise immunit ies ar e
hundr eds of millivolt s or mor e. Non copper -clad Mat r ix boar d, Vect or boar d,
wir e-wr ap, and plug-in br eadboar d syst ems ar e, wit hout except ion, unsuit able for
high per for mance or high fr equency analog pr ot ot yping because t heir r esist ance,
induct ance, and capacit ance ar e t oo high. Even t he use of st andar d IC socket s is
inadvisable in many pr ot ot yping applicat ions.
An impor t ant consider at ion in select ing a pr ot ot yping met hod is t he r equir ement for
a lar ge-ar ea gr ound plane. This is r equir ed for high fr equency cir cuit s as well as low
speed pr ecision cir cuit s, especially when pr ot ot yping cir cuit s involving ADCs or
DACs. The differ ent iat ion bet ween high-speed and high-precision mixed-signal
cir cuit s is difficult t o make. For example, 16+ bit ADCs (and DACs) may oper at e on
high speed clocks (>10MHz) wit h r ise and fall t imes of less t han a few nanoseconds,
while t he effect ive t hr oughput r at e of t he conver t er s may be less t han 100kSPS.
Successful pr ot ot yping of t hese cir cuit s r equir es t hat equal at t ent ion be given t o
good high-speed and high-pr ecision cir cuit t echniques.
The simplest t echnique for analog pr ot ot yping uses a solid copper -clad boar d as a
gr ound plane (Refer ence 5 and 6). The gr ound pins of t he ICs ar e solder ed dir ect ly t o
t he plane, and t he ot her component s ar e wir ed t oget her above it . This allows HF
decoupling pat hs t o be ver y shor t indeed. All lead lengt hs should be as shor t as
possible, and signal r out ing should separ at e high-level and low-level signals.
Connect ion wir es should be locat ed close t o t he sur face of t he boar d t o minimize t he
possibilit y of st r ay induct ive coupling. In most cases, 18-gauge or lar ger insulat ed
wir e should be used. Par allel r uns should not be "bundled" because of possible
coupling. Ideally t he layout (at least t he r elat ive placement of t he component s on t he
boar d) should be similar t o t he layout t o be used on t he final PCB. This appr oach is
oft en r efer r ed t o as deadbug prototyping because t he ICs ar e oft en mount ed upside
down wit h t heir leads up in t he air (wit h t he except ion of t he gr ound pins, which ar e
bent over and solder ed dir ect ly t o t he gr ound plane). The upside-down ICs look like
deceased insect s, hence t he name.
Figur e 7.8 shows a hand-wir ed br eadboar d using t wo high speed op amps which
gives excellent per for mance in spit e of it s lack of est het ic appeal. The IC op amps
ar e mount ed upside down on t he copper boar d wit h t he leads bent over . The signals
ar e connect ed wit h shor t point -t o-point wir ing. The char act er ist ic impedance of a
wir e over a gr ound plane is about 120, alt hough t his may var y as much as 40%
depending on t he dist ance fr om t he plane. The decoupling capacit or s ar e connect ed
dir ect ly fr om t he op amp power pins t o t he copper -clad gr ound plane. When wor king
at fr equencies of sever al hundr ed MHz, it is a good idea t o use only one side of t he
boar d for gr ound. Many people dr ill holes in t he boar d and connect bot h sides
t oget her wit h shor t pieces of wir e solder ed t o bot h sides of t he boar d. If car e is not
9
t aken, however , t his may r esult in unexpect ed gr ound loops bet ween t he t wo sides of
t he boar d, especially at RF fr equencies.
"DEADBUG" PROTOTYPE
a 7.8
Pieces of copper -clad boar d may be solder ed at r ight angles t o t he main gr ound
plane t o pr ovide scr eening, or cir cuit r y may be const r uct ed on bot h sides of t he boar d
(wit h connect ions t hr ough holes) wit h t he boar d it self pr oviding scr eening. In t his
case, t he boar d will need st andoffs at t he cor ner s t o pr ot ect t he component s on t he
under side fr om being cr ushed.
When t he component s of a br eadboar d of t his t ype ar e wir ed point -t o-point in t he air
(a t ype of const r uct ion st r ongly advocat ed by Rober t A. Pease of Nat ional
Semiconduct or (Refer ence 6) and somet imes known as "bir d's nest " const r uct ion)
t her e is always t he r isk of t he cir cuit r y being cr ushed and r esult ing shor t -cir cuit s.
Also, if t he cir cuit r y r ises high above t he gr ound plane, t he scr eening effect of t he
gr ound plane is diminished, and int er act ion bet ween differ ent par t s of t he cir cuit is
mor e likely. Never t heless, t he t echnique is ver y pr act ical and widely used because
t he cir cuit may easily be modified (assuming t he per son doing t he modificat ions is
adept at using a solder ing ir on, solder -wick, and a solder -sucker ).
Anot her pr ot ot ype br eadboar d is shown in Figur e 7.9. The single-sided copper -clad
boar d has pr e-dr illed holes on 0.1" cent er s (Refer ence 7). Power busses ar e at t he t op
and bot t om of t he boar d. The decoupling capacit or s ar e used on t he power pins of
each IC. Because of t he loss of copper ar ea due t o t he pr e-dr illed holes, t his
t echnique does not pr ovide as low a gr ound impedance as a complet ely cover ed
copper -clad boar d.
10
"DEADBUG" PROTOTYPE USING PRE-DRILLED
SINGLE-SIDED COPPER-CLAD BOARD
a 7.9
In a var iat ion of t his t echnique, t he ICs and ot her component s ar e mount ed on t he
non-copper -clad side of t he boar d. The holes ar e used as vias, and t he point -t o-point
wir ing is done on t he copper -clad side of t he boar d. The copper sur r ounding each
hole used for a via must be dr illed out t o pr event shor t ing. This appr oach r equir es
t hat all IC pins be on 0.1" cent er s. Low pr ofile socket s can be used for low fr equency
cir cuit s, and t he socket pins allow easy point -t o-point wir ing.
Ther e is a commer cial br eadboar ding syst em which has most of t he advant ages of
t he above t echniques (r obust gr ound, scr eening, ease of cir cuit alt er at ion, low
capacit ance and low induct ance) and sever al addit ional advant ages: it is r igid,
component s ar e close t o t he gr ound plane, and wher e necessar y, node capacit ances
and line impedances can be calculat ed easily. This syst em is made by Wainwr ight
Inst r ument s and is available in Eur ope as "Mini-Mount " and in t he USA (wher e t he
t r ademar k "Mini-Mount " is t he pr oper t y of anot her company) as "Solder -Mount "
(Refer ence 8).
Solder -Mount consist s of small pieces of PCB wit h et ched pat t er ns on one side and
cont act adhesive on t he ot her . These pieces ar e st uck t o t he gr ound plane, and
component s ar e solder ed t o t hem. They ar e available in a wide var iet y of pat t er ns,
including r eady-made pads for IC packages of all sizes fr om 8-pin SOICs t o 64-pin
DILs, st r ips wit h solder pads at int er vals (which int er vals r ange fr om 0.040" t o
0.25", t he r ange includes st r ips wit h 0.1" pad spacing which may be used t o mount
DIL devices), st r ips wit h conduct or s of t he cor r ect widt h t o for m micr ost r ip
t r ansmission lines (50, 60, 75 or 100) when mount ed on t he gr ound plane, and
a var iet y of pads for mount ing var ious ot her component s. Self-adhesive t inned
11
copper st r ips and r ect angles (LO-PADS) ar e also available as t ie-point s for
connect ions. They have a r elat ively high capacit ance t o gr ound and t her efor e ser ve
as low-induct ance decoupling capacit or s. They come in sheet for m and may be cut
wit h a knife or scissor s. A few of t he many t ypes of Solder -Mount building-block
component s ar e shown in Figur e 7.10.
SAMPLES OF "SOLDER-MOUNT" COMPONENTS
a 7.10
The main advant age of Solder -Mount const r uct ion over "bir d's nest " or "deadbug" is
t hat t he r esult ing cir cuit is far mor e r igid, and, if desir ed, may be made far smaller
(t he lat est Solder -Mount s ar e for sur face-mount devices and allow t he const r uct ion
of br eadboar ds scar cely lar ger t han t he final PC boar d, alt hough it is gener ally mor e
convenient if t he pr ot ot ype is somewhat lar ger ). Solder -Mount is sufficient ly dur able
t hat it may be used for small quant it y pr oduct ion as well as pr ot ot yping.
Figur e 7.11 shows an example of a 2.5GHz phase-locked-loop pr ot ot ype built wit h
Solder -Mount . This is a high speed cir cuit , but t he t echnique is equally suit able for
t he const r uct ion of high r esolut ion low fr equency analog cir cuit r y. A par t icular ly
convenient feat ur e of Solder -Mount at VHF is t he ease wit h which it is possible t o
make a t r ansmission line.
"SOLDER-MOUNT" PROTOTYPE
12
a 7.11
If a conduct or r uns over a gr ound plane, it for ms a micr ost r ip t r ansmission line. The
Solder -Mount component s include st r ips which for m micr ost r ip lines when mount ed
on a gr ound plane (t hey ar e available wit h impedances of 50, 60, 75, and
100). These st r ips may be used as t r ansmission lines, for impedance mat ching, or
simply as power buses. (Glass fiber /epoxy PCB is somewhat lossy at VHF and UHF,
but t he losses will pr obably be t oler able if micr ost r ip r uns ar e shor t .)
Bot h t he "deadbug" and t he "Solder -Mount " pr ot ot yping t echniques become
somewhat t edious for complex analog or mixed-signal cir cuit s. Lar ger cir cuit s ar e
oft en bet t er pr ot ot yped using mor e for mal layout t echniques.
An appr oach t o pr ot ot yping mor e complex analog cir cuit s is t o act ually lay out a
double-sided boar d using CAD t echniques. PC-based soft war e layout packages offer
ease of layout as well as schemat ic capt ur e t o ver ify connect ions (Refer ence 9).
Alt hough most layout soft war e has some amount of aut o-r out ing capabilit y, t his
feat ur e is best left t o digit al designs. Aft er t he component s ar e placed in t heir
desir ed posit ions, t he int er connect ions should be r out ed manually following good
analog layout guidelines. Aft er t he layout is complet e, t he soft war e ver ifies t he
connect ions per t he schemat ic diagr am net list .
Many design engineer s find t hat t hey can use CAD t echniques t o lay out simple
boar ds t hemselves, or wor k closely wit h a layout per son who has exper ience in
analog cir cuit boar ds. The r esult is a pat t er n-gener at ion t ape (or Ger ber file) which
would nor mally be sent t o a PCB manufact ur ing facilit y wher e t he final boar d is
made. Rat her t han use a PC boar d manufact ur er , however , aut omat ic dr illing and
milling machines ar e available which accept t he PG t ape dir ect ly (Refer ence 10).
These syst ems pr oduce single and double-sided cir cuit boar ds dir ect ly by dr illing all
holes and using a milling t echnique t o r emove copper and cr eat e insulat ion pat hs
and finally, t he finished boar d. The r esult is a boar d ver y similar t o t he final
manufact ur ed double-sided PC boar d, t he chief except ion being t hat t her e is no
13
"plat ed-t hr ough" hole capabilit y, and any "vias" bet ween t he t wo layer s of t he boar d
must be wir ed and solder ed on bot h sides. Minimum t r ace widt hs of 25 mils (1 mil =
0.001") and 12 mil spacing bet ween t r aces ar e st andar d, alt hough smaller t r ace
widt hs can be achieved wit h car e. The minimum spacing bet ween lines is dict at ed
by t he size of t he milling bit , t ypically 10 t o 12 mils. An example of such a pr ot ot ype
boar d is shown in Figur e 7.12 (t op view) and Figur e 7.13 (bot t om view).
"MILLED" PROTOTYPE - TOP VIEW
a 7.12
"MILLED" PROTOTYPE - BOTTOM VIEW
14
a 7.13
IC socket s can degr ade t he per for mance of high speed or high pr ecision analog ICs.
Alt hough t hey make pr ot ot yping easier , even low-profile socket s oft en int r oduce
enough par asit ic capacit ance and induct ance t o degr ade t he per for mance of t he
cir cuit . If socket s must be used in high speed cir cuit s, an IC socket made of
individual pin sockets (somet imes called cage jacks) mount ed in t he gr ound plane
boar d may be accept able (clear t he copper , on bot h sides of t he boar d, for about
0.5mm ar ound each ungr ounded pin socket and solder t he gr ounded ones t o gr ound
on bot h sides of t he boar d). Bot h capped and uncapped ver sions of t hese pin socket s
ar e available (AMP par t number s 5-330808-3, and 5-330808-6, r espect ively). The
pin socket s pr ot r ude t hr ough t he boar d far enough t o allow point -t o-point wir ing
int er connect ions bet ween t hem (see Figur e 7.14).
The spr ing-loaded gold-plat ed cont act s wit hin t he pin socket makes good elect r ical
and mechanical connect ion t o t he IC pins. Mult iple inser t ions, however , may
degr ade t he per for mance of t he pin socket . The uncapped ver sions allow t he IC pins
t o ext end out t he bot t om of t he socket . Aft er t he pr ot ot ype is funct ional and no
fur t her changes ar e t o be made, t he IC pins can be solder ed dir ect ly t o t he bot t om of
t he socket , t her eby making a per manent and r ugged connect ion.
PIN SOCKETS (CAGE JACKS) HAVE MINIMUM PARASITIC
RESISTANCE, INDUCTANCE, AND CAPACITANCE
7.14
a a
COPPER SOLDER
SOLDER
SOLDER
SOLDER
PCB DIELECTRIC
PCB DIELECTRIC
CAPPED OR UNCAPPED
VERSIONS AVAILABLE
SPRING
CONTACTS
The pr ot ot yping t echniques discussed so far have been limit ed t o single or double-
sided PC boar ds. Mult ilayer PC boar ds do not easily lend t hemselves t o st andar d
pr ot ot yping t echniques. If mult ilayer boar d pr ot ot yping is r equir ed, one side of a
double-sided boar d can be used for gr ound and t he ot her side for power and signals.
Point -t o-point wir ing can be used for addit ional r uns which would nor mally be
placed on t he addit ional layer s pr ovided by a mult i-layer boar d. However , it is
difficult t o cont r ol t he impedance of t he point -t o-point wir ing r uns, and t he high
15
fr equency per for mance of a cir cuit pr ot ot yped in t his manner may differ significant ly
fr om t he final mult ilayer boar d.
Ot her difficult ies in pr ot ot yping may occur wit h op amps or ot her linear devices
having bandwidt hs gr eat er t han a few hundr ed megaher t z. Small var iat ions in
par asit ic capacit ance (<1pF) bet ween t he pr ot ot ype and t he final boar d may cause
subt le differ ences in bandwidt h and set t ling t ime. Oft ent imes pr ot ot yping is done
wit h DIP packages, when t he final pr oduct ion package is an SOIC. This can account
for differ ences bet ween pr ot ot ype and final PC boar d per for mance.
EVALUATI ON BOARDS
Wa l t Kest er
Most manufact ur er s of analog ICs pr ovide evaluat ion boar ds (usually at a nominal
cost ) which allow cust omer s t o evaluat e pr oduct s wit hout const r uct ing t heir own
pr ot ot ypes. Regar dless of t he pr oduct , t he manufact ur er has t aken pr oper
pr ecaut ions r egar ding gr ounding, layout , and decoupling t o ensur e opt imum device
per for mance. The ar t wor k or CAD file is usually made available fr ee of char ge,
should t he cust omer wish t o copy t he layout dir ect ly or make modificat ions t o suit
t he applicat ion.
Figur e 7.15 shows t he schemat ic for t he AD8001 (SOIC package) 800MHz op amp
evaluat ion boar d. Figur es 7.16 and 7.17, r espect ively, show t he t op and bot t om side
of t he PCB. The amplifier is connect ed in t he non-inver t ing mode. The t op side
(Figur e 7.16) shows t he t op side of t he SOIC package along wit h input and out put
SMA connect or s. Not ice t hat t he gr ound plane is cut away ar ound t he SOIC in or der
t o minimize par asit ic capacit ance. The bot t om side of t he boar d (Figur e 7.17) shows
t he sur face mount r esist or s and capacit or s which compr ise t he op amp gain-set t ing
and power supply decoupling cir cuit s, r espect ively.
16
AD8001AR (SOIC) 800MHz OP AMP: NON-INVERTING
MODE EVALUATION BOARD SCHEMATIC
7.15
a a
AD8001
IN
+
-
681
49.9
R
G
R
T
-V
S
+V
S
R
O
49.9
+
R
F
681
OUT
1000pF
1000pF
0.01 F
10 F
10 F
0.01 F
+
AD8001AR (SOIC) EVALUATION BOARD - TOP VIEW
a 7.16
AD8001AR (SOIC) EVALUATION BOARD - BOTTOM VIEW
17
a 7.17
In high speed/high pr ecision ICs, special at t ent ion must be given t o power supply
decoupling. For example, fast slewing signals int o r elat ively low impedance loads
pr oduce high speed t r ansient cur r ent s at t he power supply pins of an op amp. The
t r ansient cur r ent s, in t ur n, pr oduce cor r esponding volt ages acr oss any par asit ic
impedance which may exist in t he power supply t r aces. These volt ages, in t ur n, may
couple t o t he amplifier out put because of t he op amp's finit e power supply r eject ion
at high fr equencies.
A t hr ee-capacit or decoupling scheme was chosen for t he AD8001 evaluat ion boar d t o
ensur e a low impedance pat h t o gr ound at all t r ansient fr equencies. The highest
fr equency t r ansient s ar e shunt ed t o gr ound by t he 1000pF and t he 0.01F cer amic
capacit or s. These ar e locat ed as close t o t he power supply pins as possible t o
minimize any ser ies induct ance and r esist ance. Because t he devices ar e sur face
mount , t her e is minimum st r ay induct ance and r esist ance in t he pat h t o t he gr ound
plane. The lower fr equency t r ansient cur r ent s ar e shunt ed t o gr ound by t he 10F
t ant alum capacit or s.
The input and out put signal t r aces ar e of t he AD8001 evaluat ion boar d ar e 50
micr ost r ip t r ansmission lines. Not ice t hat t her e is consider able cont inuous gr ound
plane ar ea on bot h sides of t he PCB. Plat ed-t hr ough holes connect t he t op and
bot t om side gr ound planes at sever al point s in or der t o maint ain low impedance
gr ound cont inuit y at high fr equencies.
Evaluat ion boar ds can r ange fr om r elat ively simple ones (op amps, for example) t o
r at her complex ones for mixed-signal ICs such as A/D conver t er s. ADC evaluat ion
boar ds oft en have on-boar d memor y and DSPs for analyzing t he ADC per for mance.
Soft war e is oft en pr ovided wit h t hese mor e complex evaluat ion boar ds so t hat t hey
can int er face wit h a per sonal comput er t o per for m complex signal analysis such as
hist ogr am and FFT t est ing.
18
Complet e evaluat ions of ADCs r equir es t he use of FFTs t o fully char act er ize t he
devices AC per for mance. A t ypical t est set up is shown in Figur e 7.18. The
manufact ur er 's evaluat ion boar d is used as a means for int er facing t o t he ADC. The
evaluat ion boar d is designed t o allow easy access t o t he ADC input s and out put s
while also pr oviding a good layout (including all necessar y r efer ences, buffer
amplifier s, and decoupling). The evaluat ion boar d allows t he ADC out put dat a t o be
capt ur ed on a par allel out put connect or . Most ADC evaluat ion boar ds cont ain an on-
boar d DAC which can be used t o check t he funct ionalit y of t he ADC, but is
somewhat limit ed in per for ming meaningful AC t est ing. A block diagr am of t he
AD9042 (12-bit s, 41MSPS) evaluat ion boar d is shown in Figur e 7.19, and a phot o in
Figur e 7.20.
a
TEST SETUP REQUIRED TO EVALUATE HIGH SPEED ADCs
7.18
f
s
PC
MONI TOR
ADC ON
EVALUATION
BOARD
MEMORY
OR LOGIC
ANALYZER
BANDPASS
FILTER
LOW PHASE
JITTER
SINEWAVE
SOURCE
LOW PHASE
JITTER
SAMPLING
CLOCK
SOURCE
CLOCK
PARALLEL OR
SERIAL PORT
POWER
SUPPLIES
19
a
AD9042 12-BIT, 41MSPS ADC EVALUATION BOARD
FUNCTIONAL DIAGRAM
7.19
74AS00 74AS00
499
499
CK
100
50
0.1 F
60.4
T1 - 1T
MINICIRCUITS
ANALOG
INPUT
EXTERNAL
SAMPLING
CLOCK
XTAL
OSC
40.96MHz
AD9042
74AC574
REGISTERS
(2)
ENCODE
ENCODE
AD9042 EVALUATION BOARD - TOP VIEW
a 7.20
20
The most complex par t of t he pr oblem is usually designing t he buffer memor y
module. A high speed logic analyzer is one met hod of capt ur ing t he ADC out put
dat a, and int er faces easily t o t he ADC evaluat ion boar d. Dat a fr om t he logic
analyzer can be loaded int o a PC t hr ough eit her par allel or ser ial por t s. Once t he
ADC dat a is inside t he PC, soft war e packages such as Mat hcad can be used t o
per for m t he act ual FFT.
Anot her alt er nat ive is t o use a commer cially-available dat a acquisit ion module t hat
plugs dir ect ly int o a car d slot of t he PC. These modules come complet e wit h FFT and
ot her ADC t est soft war e, but ar e not easily por t able fr om one PC t o anot her and ar e
gener ally difficult t o int er face wit h lapt op comput er s.
Alt hough fast and r elat ively low power memor ies (FIFOs) ar e available
commer cially, designing a buffer memor y, t he int er faces t o t he ADC and t he PC,
and t he necessar y soft war e can be a t ime-consuming pr oject . Analog Devices has
designed a simple 16-bit by 16k deep 100MHz memor y boar d (3 x 4 inches) and t he
necessar y soft war e t o allow high speed ADC evaluat ion boar ds t o int er face dir ect ly
wit h t he par allel pr int er por t of most PCs. The cor e of t he memor y design is t he
IDT72265 16k by 18-bit wide FIFO or alt er nat ely, t he IDT72255 is an 8k pin
compat ible device which may be subst it ut ed if t he deeper memor y is not r equir ed.
This FIFO chip feat ur es fully independent I/O por t s t hat allow dat a t o be loaded at
up t o 100MSPS and downloaded at t he r at e of a par allel pr int er por t . Since t he por t s
ar e independent , bot h can oper at e simult aneously, i.e., dat a may be r ead out while
new dat a is being wr it t en. The chip t akes car e of all addr essing, over head and much
of t he hand-shaking for t hese oper at ions. Included is cir cuit r y t hat pr event s unr ead
dat a fr om being over wr it t en, eliminat ing t he need for ext ensive wr it e cont r ol
cir cuit r y.
A phot ogr aph of t he Fifo Memory boar d is shown in Figur e 7.21, and Figur e 7.22
shows it connect ed t o t he AD9042 evaluat ion boar d.
BUFFER MEMORY FIFO BOARD - TOP VIEW
21
a 7.21
MEMORY BOARD / AD9042 EVALUATION BOARD
a 7.22
Using t his har dwar e and Windows-based soft war e t o capt ur e t he ADC dat a, many
t est ing possibilit ies exist . Figur e 7.23 shown a t ime-domain plot of dat a capt ur ed
using t he fifo memor y. Once t he dat a is capt ur ed, FFT analysis (Figur e 7.24) or
DNL hist ogr ams (Figur e 7.25) ar e easily gener at ed.
DATA CAPTURE PC OUTPUT DISPLAY
a 7.23
22
FFT OUTPUT
a 7.24
DNL HISTOGRAM
23
a 7.25
In summar y, good analog designer s ut ilize as many t ools as possible t o ensur e t hat
t he final syst em design per for ms cor r ect ly. The fir st st ep is t he int elligent use of IC
macr omodels, wher e available, t o simulat e t he cir cuit . The second st ep is t he
const r uct ion of a pr ot ot ype boar d t o fur t her ver ify t he design and t he simulat ion.
The final PCB layout should be t hen be based on t he pr ot ot ype layout as much as
possible.
Finally, evaluat ion boar ds can be ext r emely useful in evaluat ing new analog ICs,
and allow designer s t o ver ify t he IC per for mance wit h a minimum amount of effor t .
The layout of t he component s on t he evaluat ion boar d can ser ve as a guide t o bot h
t he pr ot ot ype and t he final PC boar d layout . Ger ber files ar e gener ally available for
all evaluat ion boar d layout s and may be obt ained at no char ge.
24
REFERENCES: SI MULATI ON, P ROTOTYP I NG, AND
EVALUATI ON BOARDS
1. Paolo Ant ognet t i and Guiseppe Massobr io, Ed, Semi con d u ct or Devi ce
Mod eli n g wi t h SP I CE, McGr aw Hill, 1988.
2. Amp li fi er Ap p li ca t i on s Gu i d e, Sect ion 13, Analog Devices, Inc.,
Nor wood, MA, 1992.
3. Boyle, et al, Macromodelling of Integrated Circuit
Operational Amplifiers, I EEE J ou r n a l of Soli d St a t e Ci r cu i t s,
Vol. SC-9, no.6, December 1974.
4. PSpice Simulat ion soft war e.
Micr oSim Cor por at ion, 20 Fair banks, Ir vine, CA 92718, 714-770-3022
5. J im Williams, Hi gh Sp eed Amp li fi er Tech n i qu es, Linear Technology
Applicat ion Not e 47, August , 1991.
6. Rober t A. Pease, Tr ou blesh oot i n g An a log Ci r cu i t s, But t er wor t h-
Heinemann, 1991.
7. Vect or Elect r onic Company, 12460 Gladst one Ave., Sylmar , CA 91342,
Tel. 818-365-9661, Fax. 818-365-5718.
8. Wainwr ight Inst r ument s Inc., 69 Madison Ave., Telfor d, PA,
18969-1829, Tel. 215-723-4333, Fax. 215-723-4620.
Wainwr ight Inst r ument s GmbH, Widder sber ger St r asse 14,
DW-8138 Andechs-Fr ieding, Ger many. Tel: +49-8152-3162,
Fax: +49-8152-40525.
9. Schemat ic Capt ur e and Layout Soft war e:
PADS Soft war e, INC, 165 For est St ., Mar lbor o, MA, 01752 and
ACCEL Technologies, Inc., 6825 Flander s Dr ., San Diego, CA,
92121
10. Pr ot ot ype Boar d Cut t er s:
LPKF CAD/CAM Syst ems, Inc., 6190 Ar t ic Dr , PO Box 6209,
Beaver t on, OR, 97005 and
T-Tech, Inc., 5591-B New Peacht r ee Road, At lant a, GA,
34341
11. Howar d W. J ohnson and Mar t in Gr aham, Hi gh -Sp eed Di gi t a l Desi gn ,
PTR Pr ent ice Hall, 1993.
12. P r a ct i ca l An a log Desi gn Tech n i qu es, Analog Devices, 1995.
25
1
GROUNDI NG I N HI GH SP EED SYSTEMS
Wa l t Kest er , J a m es Br ya n t
The impor t ance of maint aining a low impedance lar ge ar ea gr ound plane is cr it ical
t o pr act ically all analog cir cuit s t oday, especially at high speeds. The gr ound plane
not only act s as a low impedance r et ur n pat h for high fr equency cur r ent s but also
minimizes EMI/RFI emissions. Because of t he shielding act ion of t he gr ound plane,
t he cir cuit s suscept ibilit y t o ext er nal EMI/RFI is also r educed.
All IC gr ound pins should be solder ed dir ect ly t o t he gr ound plane t o minimize ser ies
induct ance. Power supply pins should be decoupled t o t he gr ound plane using low
induct ance cer amic sur face mount capacit or s. If t hr ough-hole mount ed cer amic
capacit or s must be used, t heir leads should be less t han 1mm. Fer r it e beads may be
also r equir ed.
The gr ound plane allows t he impedance of PCB t r aces t o be cont r olled, and high
fr equency signals can be t er minat ed in t he char act er ist ic impedance of t he t r ace t o
minimize r eflect ions when necessar y.
Each PCB in t he syst em should have at least one complet e layer dedicat ed t o t he
gr ound plane. Ideally, a double-sided boar d should have one side dedicat ed t o
gr ound and t he ot her side for int er connect ions. In pr act ice, t his is not possible, since
some of t he gr ound plane will cer t ainly have t o be r emoved t o allow for signal and
power cr ossover s and vias. Never t heless, as much ar ea as possible should be
pr eser ved, and at least 75% should r emain. Aft er complet ing an init ial layout , t he
gr ound layer should be checked car efully t o make sur e t her e ar e no isolat ed gr ound
"islands." IC gr ound pins locat ed in a gr ound "island" have no cur r ent r et ur n pat h t o
t he gr ound plane.
The best way of minimizing gr ound impedance in a mult icar d syst em is t o use
anot her PCB as a backplane for int er connect ions bet ween car ds, t hus pr oviding a
cont inuous gr ound plane t o t he mot her car d. The PCB connect or should have at
least 30-40% of it s pins devot ed t o gr ound, and t hese pins should be connect ed t o t he
gr ound plane on t he backplane mot her car d. To complet e t he over all syst em
gr ounding scheme t her e ar e t wo possibilit ies: (1) The backplane gr ound plane can be
connect ed t o chassis gr ound at numer ous point s, t her eby diffusing t he var ious
gr ound cur r ent r et ur n pat hs. (2) The gr ound plane can be connect ed t o a single
syst em "st ar gr ound" point (gener ally at t he power supply).
The fir st appr oach is oft en used at ver y high fr equencies and wher e t he r et ur n
cur r ent s ar e r elat ively const ant . The low gr ound impedance is maint ained all t he
way t hr ough t he PC boar ds, t he backplane, and ult imat ely t he chassis. It is cr it ical
t hat good elect r ical cont act be made wher e t he gr ounds ar e connect ed t o t he sheet
met al chassis. This r equir es self-t apping sheet met al scr ews or "bit ing" washer s.
Special car e must be t aken wher e anodized aluminum is used for t he chassis
mat er ial, since it s sur face act s as an insulat or .
In ot her syst ems, especially high speed ones wit h lar ge amount s of digit al cir cuit r y,
it is highly desir able t o physically separ at e sensit ive analog component s fr om noisy
digit al component s. It is usually desir able t o use separ at e gr ound planes for t he
analog and t he digit al cir cuit r y. On PCBs which have bot h analog and digit al
2
cir cuit s, t her e ar e t wo separ at e gr ound planes. These planes should not over lap in
or der t o minimize capacit ive coupling bet ween t he t wo. The separ at e analog and
digit al gr ound planes ar e cont inued on t he backplane using eit her mot her boar d
gr ound planes or "gr ound scr eens" which ar e made up of a ser ies of wir ed
int er connect ions bet ween t he connect or gr ound pins. The ar r angement shown in
Figur e 7.26 illust r at es t hat t he t wo planes ar e kept separ at e all t he way back t o a
common syst em "st ar " gr ound, gener ally locat ed at t he power supplies. The
connect ions bet ween t he gr ound planes, t he power supplies, and t he "st ar " should be
made up of mult iple bus bar s or wide copper br ads for minimum r esist ance and
induct ance. The back-t o-back Schot t ky diodes on each PCB ar e inser t ed t o pr event
accident al DC volt age fr om developing bet ween t he t wo gr ound syst ems when car ds
ar e plugged and unplugged.
a
SEPARATING ANALOG AND DIGITAL GROUNDS
7.26
SYSTEM STAR
GROUND
POWER
SUPPLIES
ANALOG GND PLANE
DIGITAL GND PLANE
BACKPLANE
DIGITAL
GROUND
PLANE
ANALOG
GROUND
PLANE
DIGITAL
GROUND
PLANE
ANALOG
GROUND
PLANE
PCB
A D A
V
A
V
D
PCB
V
D
V
A
V
D
V
A
D
Sensit ive analog component s such as amplifier s and volt age r efer ences ar e
r efer enced and decoupled t o t he analog gr ound plane. The ADCs and DACs (and
even some mixed-signal ICs) should be treated as analog components and also
grounded and decoupled to the analog ground plane. At fir st glance, t his may seem
somewhat cont r adict or y, since a conver t er has an analog and digit al int er face and
usually pins designat ed as analog gr ound (AGND) and digit al gr ound (DGND). The
diagr am shown in Figur e 7.27 will help t o explain t his seeming dilemma.
3
7.27
PROPER GROUNDING OF ADCs, DACs,
AND OTHER MIXED-SIGNAL ICs
a
"QUIET"
DIGITAL
BUFFER
LATCH
NOISY
DATA BUS
= DIGITAL
GROUND PLANE
D
A
AGND DGND
I
A
I
D
B
A
= ANALOG
GROUND PLANE
ANALOG
IN/OUT
C
STRAY
C
STRAY
V
A
V
D
A
A
D
ADC,
OR
DAC
V
A
A
V
D
D
A
ANALOG
CIRCUITS
DIGITAL
CIRCUITS
A
Inside an IC t hat has bot h analog and digit al cir cuit s, such as an ADC or a DAC, t he
gr ounds ar e usually kept separ at e t o avoid coupling digit al signals int o t he analog
cir cuit s. Figur e 7.27 shows a simple model of a conver t er . Ther e is not hing t he IC
designer can do about t he wir ebond induct ance and r esist ance associat ed wit h
connect ing t he pads on t he chip t o t he package pins except t o r ealize it 's t her e. The
r apidly changing digit al cur r ent s pr oduce a volt age at point B which will inevit ably
couple int o point A of t he analog cir cuit s t hr ough t he st r ay capacit ance, C
STRAY
. In
addit ion, t her e is appr oximat ely 0.2pF unavoidable st r ay capacit ance bet ween ever y
pin of t he IC package! It 's t he IC designer 's job t o make t he chip wor k in spit e of
t his. However , in or der t o pr event fur t her coupling, t he AGND and DGND pins
should be joined t oget her ext er nally t o t he analog gr ound plane wit h minimum lead
lengt hs. Any ext r a impedance in t he DGND connect ion will cause mor e digit al noise
t o be developed at point B; it will, in t ur n, couple mor e digit al noise int o t he analog
cir cuit t hr ough t he st r ay capacit ance.
The name "DGND" on an IC tells us that this pin connects to the digital ground of the
IC. This does not imply that this pin must be connected to the digital ground of the
system.
It is t r ue t hat t his ar r angement will inject a small amount of digit al noise on t he
analog gr ound plane. These cur r ent s should be quit e small, and can be minimized by
ensur ing t hat t he conver t er input /or out put does not dr ive a lar ge fanout (t hey
nor mally can't by design). Minimizing t he fanout on t he conver t er 's digit al por t will
also keep t he conver t er logic t r ansit ions r elat ively fr ee fr om r inging, and t her eby
minimize any pot ent ial coupling int o t he analog por t of t he conver t er . The logic
4
supply pin (V
D
) can be fur t her isolat ed fr om t he analog supply by t he inser t ion of a
small lossy fer r it e bead as shown in Figur e 7.27. The int er nal digit al cur r ent s of t he
conver t er will r et ur n t o gr ound t hr ough t he V
D
pin decoupling capacit or (mount ed
as close t o t he conver t er as possible) and will not appear in t he ext er nal gr ound
cir cuit . It is always a good idea (as shown in Figur e 7.27) t o place a buffer lat ch
adjacent t o t he conver t er t o isolat e t he conver t er 's digit al lines fr om any noise which
may be on t he dat a bus. Even t hough a few high speed conver t er s have t hr ee-st at e
out put s/input s, t his isolat ion lat ch r epr esent s good design pr act ice.
The buffer lat ch and ot her digit al cir cuit s should be gr ounded and decoupled t o t he
digit al gr ound plane of t he PC boar d. Not ice t hat any noise bet ween t he analog and
digit al gr ound plane r educes t he noise mar gin at t he conver t er digit al int er face.
Since digit al noise immunit y is of t he or der s of hundr eds or t housands of millivolt s,
t his is unlikely t o mat t er .
7.28
POWER SUPPLY, GROUNDING, AND DECOUPLING POINTS
a
= DIGITAL GROUND PLANE
= ANALOG GROUND PLANE
A
D
A
BUFFER
LATCH
TO OTHER
DIGITAL
CIRCUITS
ADC
OR
DAC
A
A
A
A A A
A
A
A
V
A
V
A
V
D
D
D
V
A
V
A
V
D
DGND
AGND
V
A
VOLTAGE
REFERENCE
SAMPLING
CLOCK
GENERATOR
Separ at e power supplies for analog and digit al cir cuit s ar e also highly desir able. The
analog supply should be used t o power t he conver t er . If t he conver t er has a pin
designat ed as a digit al supply pin (V
D
), it should eit her be power ed fr om a separ at e
analog supply, or filt er ed as shown in t he diagr am. All conver t er power pins should
be decoupled t o t he analog gr ound plane, and all logic cir cuit power pins should be
decoupled t o t he digit al gr ound plane. If t he digit al power supply is r elat ively quiet ,
it may be possible t o use it t o supply analog cir cuit s as well, but be ver y caut ious.
The sampling clock gener at ion cir cuit r y should also be gr ounded and heavily-
decoupled t o t he analog gr ound plane. As pr eviously discussed, phase noise on t he
sampling clock pr oduces degr adat ion in syst em SNR.
A low phase-noise cr yst al oscillat or should be used t o gener at e t he ADC sampling
clock, because sampling clock jit t er modulat es t he input signal and r aises t he noise
5
and dist or t ion floor . The sampling clock gener at or should be isolat ed fr om noisy
digit al cir cuit s and gr ounded and decoupled t o t he analog gr ound plane, as is t r ue
for t he op amp and t he ADC.
Ideally, t he sampling clock gener at or should be r efer enced t o t he analog gr ound
plane in a split -gr ound syst em. However , t his is not always possible because of
syst em const r aint s. In many cases, t he sampling clock must be der ived fr om a
higher fr equency mult i-pur pose syst em clock which is gener at ed on t he digit al
gr ound plane. If it is passed bet ween it s or igin on t he digit al gr ound plane t o t he
ADC on t he analog gr ound plane, t he gr ound noise bet ween t he t wo planes adds
dir ect ly t o t he clock and will pr oduce excess jit t er . The jit t er can cause degr adat ion
in t he signal-t o-noise r at io and also pr oduce unwant ed har monics. This can be
r emedied somewhat by t r ansmit t ing t he sampling clock signal as a differ ent ial one
using eit her a small RF t r ansfor mer or a high speed differ ent ial dr iver and r eceiver
as shown in Figur e 7.29. The dr iver and r eceiver should be ECL t o minimize phase
jit t er . In eit her case, t he or iginal mast er syst em clock should be gener at ed fr om a
low phase noise cr yst al oscillat or .
a
SAMPLING CLOCK DISTRIBUTION FROM
DIGITAL TO ANALOG GROUND PLANES
7.29
DIGITAL
GROUND PLANE
(D)
+V
D ANALOG
GROUND PLANE
(A)
SAMPLING
CLOCK
SAMPLING
CLOCK
+V
D
+V
D
+V
D
+V
A
A
A
D
D
D D
D
LOW PHASE
NOISE
MASTER CLOCK
SYSTEM CLOCK
GENERATORS
DSP
METHOD 1
METHOD 2
It is evident t hat noise can be minimized by paying at t ent ion t o t he syst em layout
and pr event ing differ ent signals fr om int er fer ing wit h each ot her . High level analog
signals should be separ at ed fr om low level analog signals, and bot h should be kept
away fr om digit al signals. We have seen elsewher e t hat in wavefor m sampling and
r econst r uct ion syst ems t he sampling clock (which is a digit al signal) is as vulner able
t o noise as any analog signal, but is as liable t o cause noise as any digit al signal,
and so must be kept isolat ed fr om bot h analog and digit al syst ems.
If a gr ound plane is used, as it should in be most cases, it can act as a shield wher e
sensit ive signals cr oss. Figur e 7.30 shows a good layout for a dat a acquisit ion boar d
6
wher e all sensit ive ar eas ar e isolat ed fr om each ot her and signal pat hs ar e kept as
shor t as possible. While r eal life is r ar ely as t idy as t his, t he pr inciple r emains a
valid one.
7.30
A PC BOARD LAYOUT SHOWING GOOD SIGNAL ROUTING
a
SAMPLING CLOCK
GENERATOR
POWER
ANALOG
INPUT
MULTIPLE
GROUNDS
DATA
BUS
ADDRESS
BUS
MULTIPLE
GROUNDS
ADC
FILTER
AMPLIFIER
DSP
BUFFER
LATCH
CONTROL
LOGIC
DEMULTIPLEXER
BUFFER
MEMORY
REF
TIMING
CIRCUITS
Ther e ar e a number of impor t ant point s t o be consider ed when making signal and
power connect ions. Fir st of all a connect or is one of t he few places in t he syst em
wher e all signal conduct or s must r un par allel - it is t her efor e a good idea t o separ at e
t hem wit h gr ound pins (cr eat ing a far aday shield) t o r educe coupling bet ween t hem.
Mult iple gr ound pins ar e impor t ant for anot her r eason: t hey keep down t he gr ound
impedance at t he junct ion bet ween t he boar d and t he backplane. The cont act
r esist ance of a single pin of a PCB connect or is quit e low (of t he or der of 10 mOhms)
when t he boar d is new - as t he boar d get s older t he cont act r esist ance is likely t o
r ise, and t he boar d's per for mance may be compr omised. It is t her efor e well
wor t hwhile t o affor d ext r a PCB connect or pins so t hat t her e ar e many gr ound
connect ions (per haps 30-40% of all t he pins on t he PCB connect or should be gr ound
pins). For similar r easons t her e should be sever al pins for each power connect ion,
alt hough t her e is no need t o have as many as t her e ar e gr ound pins.
7
P OWER SUP P LY NOI SE REDUCTI ON AND
FI LTERI NG
Wa l t J u n g a n d J oh n McDon a l d
Pr ecision analog cir cuit r y has t r adit ionally been power ed fr om well r egulat ed, low
noise linear power supplies. Dur ing t he last decade however , swit ching power
supplies have become much mor e common in elect r onic syst ems. As a consequence,
t hey also ar e being used for analog supplies. Good r easons for t he gener al popular it y
include t heir high efficiency, low t emper at ur e r ise, small size, and light weight .
In spit e of t hese benefit s, swit cher s do have dr awbacks, most not ably high out put
noise. This noise gener ally ext ends over a br oad band of fr equencies, r esult ing in
bot h conduct ed and r adiat ed noise, as well as unwant ed elect r ic and magnet ic fields.
Volt age out put noise of swit ching supplies ar e shor t -dur at ion volt age t r ansient s, or
spikes. Alt hough t he fundament al swit ching fr equency can r ange fr om 20kHz t o
1MHz, t he spikes can cont ain fr equency component s ext ending t o 100MHz or mor e.
While specifying swit ching supplies in t er ms of RMS noise is common vendor
pr act ice, as a user you should also specify t he peak (or p-p) amplit udes of t he
swit ching spikes, wit h t he out put loading of your syst em.
The following sect ion discusses filt er t echniques for r ender ing a noisy swit cher
out put analog ready, t hat is sufficient ly quiet t o power pr ecision analog cir cuit r y
wit h r elat ively small loss of DC t er minal volt age. The filt er solut ions pr esent ed ar e
gener ally applicable t o all power supply t ypes incor por at ing swit ching element (s) in
t heir ener gy pat h. This includes var ious DC-DC conver t er s as well as popular 5V
(PC t ype) supplies.
An under st anding of t he EMI pr ocess is necessar y t o under st and t he effect s of
supply noise on analog cir cuit s and syst ems. Ever y int er fer ence pr oblem has a
source, a path, and a receptor [Refer ence 1]. In gener al, t her e ar e t hr ee met hods for
dealing wit h int er fer ence. Fir st , sour ce emissions can be minimized by pr oper
layout , pulse-edge r ise t ime cont r ol/r educt ion, filt er ing, and pr oper gr ounding.
Second, r adiat ion and conduct ion pat hs should be r educed t hr ough shielding and
physical separ at ion. Thir d, r ecept or immunit y t o int er fer ence can be impr oved, via
supply and signal line filt er ing, impedance level cont r ol, impedance balancing, and
ut ilizing differ ent ial t echniques t o r eject undesir ed common-mode signals. This
sect ion focuses on r educing swit ching power supply noise wit h ext er nal post filt er s.
Tools useful for combat ing high fr equency swit cher noise ar e shown by Figur e 7.31.
They differ in elect r ical char act er ist ics as well as pr act icalit y t owar ds noise
r educt ion, and ar e list ed r oughly in an or der of pr ior it ies. Of t hese t ools, L and C ar e
t he most power ful filt er element s, and ar e t he most cost -effect ive, as well as small
sized.
NOISE REDUCTION TOOLS
n n Capacitors
n n Inductors
8
n n Ferrites
n n Resistors
n n Linear Post Regulation
n n PHYSICAL SEPARATION FROM SENSITIVE
ANALOG CIRCUITS !!
a 7.31
Capacitors ar e pr obably t he single most impor t ant filt er component for swit cher s.
Ther e ar e many differ ent t ypes of capacit or s, and an under st anding of t heir
individual char act er ist ics is absolut ely mandat or y t o t he design of effect ive pr act ical
supply filt er s. Ther e ar e gener ally t hr ee classes of capacit or s useful in 10kHz-
100MHz filt er s, br oadly dist inguished as t he gener ic dielect r ic t ypes; electrolytic,
film, and ceramic. These can in t ur n can be fur t her sub-divided. A t humbnail sket ch
of capacit or char act er ist ics is shown in t he char t of Figur e 7.32.
CAPACITOR SELECTION
Aluminum
Electrolytic
(General
Purpose)
Aluminum
Electrolytic
(Switching
Type)
Tantalum
Electrolytic
Polyester
(Stacked
Film)
Ceramic
(Multilayer)
Size 100 F (1) 120 F (1) 100 F (1) 1 F 0.1 F
Rated
Voltage
25 V 25 V 20 V 400 V 50 V
ESR 0.6 @
100 kHz
0.18 @
100 kHz
0.12 @
100 kHz
0.11 @
1 MHz
0.12 @
1 MHz
Operating
Frequenc
y (2)
100 kHz 500 kHz 1 MHz 10 MHz 1 GHz
(1) Types shown in Figure 7.33 data
(2) Upper frequency limit is strongly size and package dependent
a 7.32
Wit h any dielect r ic, a major pot ent ial filt er loss element is ESR (equivalent ser ies
r esist ance), t he net par asit ic r esist ance of t he capacit or . ESR pr ovides an ult imat e
limit t o filt er per for mance, and r equir es mor e t han casual consider at ion, because it
9
can var y bot h wit h fr equency and t emper at ur e in some t ypes. Anot her capacit or loss
element is ESL (equivalent ser ies induct ance). ESL det er mines t he fr equency wher e
t he net impedance char act er ist ic swit ches fr om capacit ive t o induct ive. This var ies
fr om as low as 10kHz in some elect r olyt ics t o as high as 100MHz or mor e in chip
cer amic t ypes. Bot h ESR and ESL ar e minimized when a leadless package is used.
All capacit or t ypes ment ioned ar e available in sur face mount packages, pr efer able
for high speed uses.
The electrolytic family pr ovides an excellent , cost -effect ive low-fr equency filt er
component , because of t he wide r ange of values, a high capacit ance-t o-volume r at io,
and a br oad r ange of wor king volt ages. It includes general purpose aluminum
electrolytic t ypes, available in wor king volt ages fr om below 10V up t o about 500V,
and in size fr om 1 t o sever al t housand F (wit h pr opor t ional case sizes). All
elect r olyt ic capacit or s ar e polar ized, and t hus cannot wit hst and mor e t han a volt or
so of r ever se bias wit hout damage. They also have r elat ively high leakage cur r ent s
(up t o t ens of A, and st r ongly dependent upon design specifics).
A subset of t he gener al elect r olyt ic family includes tantalum t ypes, gener ally limit ed
t o volt ages of 100V or less, wit h capacit ance of 500F or less[Refer ence 3]. In a given
size, t ant alums exhibit a higher capacit ance-t o-volume r at ios t han do gener al
pur pose elect r olyt ics, and have bot h a higher fr equency r ange and lower ESR. They
ar e gener ally mor e expensive t han st andar d elect r olyt ics, and must be car efully
applied wit h r espect t o sur ge and r ipple cur r ent s.
A subset of aluminum elect r olyt ic capacit or s is t he switching t ype, designed for
handling high pulse cur r ent s at fr equencies up t o sever al hundr ed kHz wit h low
losses [Refer ence 4]. This capacit or t ype compet es dir ect ly wit h t ant alums in high
fr equency filt er ing applicat ions, wit h t he advant age of a br oader r ange of values.
A mor e specialized high per for mance aluminum elect r olyt ic capacit or t ype uses an
or ganic semiconduct or elect r olyt e [Refer ence 5]. The OS -CON capacit or s feat ur e
appr eciably lower ESR and higher fr equency r ange t han do ot her elect r olyt ic t ypes,
wit h an addit ional feat ur e of low low-t emper at ur e ESR degr adat ion.
Film capacit or s ar e available in ver y br oad value r anges and an ar r ay of dielect r ics,
including polyest er , polycar bonat e, polypr opylene, and polyst yr ene. Because of t he
low dielect r ic const ant of t hese films, t heir volumet r ic efficiency is quit e low, and a
10F/50V polyest er capacit or (for example) is act ually a handful. Met alized (as
opposed t o foil) elect r odes does help t o r educe size, but even t he highest dielect r ic
const ant unit s among film t ypes (polyest er , polycar bonat e) ar e st ill lar ger t han any
elect r olyt ic, even using t he t hinnest films wit h t he lowest volt age r at ings (50V).
Wher e film t ypes excel is in t heir low dielect r ic losses, a fact or which may not
necessar ily be a pr act ical advant age for filt er ing swit cher s. For example, ESR in
film capacit or s can be as low as 10m or less, and t he behavior of films gener ally is
ver y high in t er ms of Q. In fact , t his can cause pr oblems of spur ious r esonance in
filt er s, r equir ing damping component s.
Typically using a wound layer -t ype const r uct ion, film capacit or s can be induct ive,
which can limit t heir effect iveness for high fr equency filt er ing. Obviously, only non-
induct ively made film caps ar e useful for swit ching r egulat or filt er s. One specific
st yle which is non-induct ive is t he stacked-film t ype, wher e t he capacit or plat es ar e
cut as small over lapping linear sheet sect ions fr om a much lar ger wound dr um of
10
dielect r ic/plat e mat er ial. This t echnique offer s t he low induct ance at t r act iveness of a
plat e sheet st yle capacit or wit h convent ional leads [see Refer ences 4, 5, 6].
Obviously, minimal lead lengt h should be used for best high fr equency effect iveness.
Ver y high cur r ent polycar bonat e film t ypes ar e also available, specifically designed
for swit ching power supplies, wit h a var iet y of low induct ance t er minat ions t o
minimize ESL [Refer ence 7].
Dependent upon t heir elect r ical and physical size, film capacit or s can be useful at
fr equencies t o well above 10MHz. At t he highest fr equencies, only st acked film t ypes
should be consider ed. Some manufact ur er s ar e now supplying film t ypes in leadless
sur face mount packages, which eliminat es t he lead lengt h induct ance.
Ceramic is oft en t he capacit or mat er ial of choice above a few MHz, due t o it s
compact size, low loss, and availabilit y up t o sever al F in t he high-K dielect r ic
for mulat ions (X7R and Z5U), at volt age r at ings up t o 200V [see cer amic families of
Refer ence 3]. NP0 (also called COG) t ypes use a lower dielect r ic const ant
for mulat ion, and have nominally zer o TC, plus a low volt age coefficient (unlike t he
less st able high-K t ypes). NP0 t ypes ar e limit ed t o values of 0.1F or less, wit h
0.01F r epr esent ing a mor e pr act ical upper limit .
Mult ilayer cer amic chip caps ar e ver y popular for bypassing/ filt er ing at 10MHz or
mor e, simply because t heir ver y low induct ance design allows near opt imum RF
bypassing. For smaller values, cer amic chip caps have an oper at ing fr equency r ange
t o 1GHz. For high fr equency applicat ions, a useful select ion can be ensur ed by
select ing a value which has a self-r esonant fr equency above t he highest fr equency of
int er est .
All capacit or s have some finit e ESR. In some cases, t he ESR may act ually be helpful
in r educing r esonance peaks in filt er s, by supplying fr ee damping. For example, in
most elect r olyt ic t ypes, a nominally flat br oad ser ies r esonance r egion can be not ed
in an impedance vs. fr equency plot . This occur s wher e | Z| falls t o a minimum level,
nominally equal t o t he capacit or s ESR at t hat fr equency. This low Q r esonance can
gener ally be not ed t o cover a r elat ively wide fr equency r ange of sever al oct aves.
Cont r ast ed t o t he ver y high Q shar p r esonances of film and cer amic caps, t he low Q
behavior of elect r olyt ics can be useful in cont r olling r esonant peaks.
In most elect r olyt ic capacit or s, ESR degr ades not iceably at low t emper at ur e, by as
much as a fact or of 4-6 t imes at 55C vs. t he r oom t emper at ur e value. For cir cuit s
wher e ESR is cr it ical t o per for mance, t his can lead t o pr oblems. Some specific
elect r olyt ic t ypes do addr ess t his pr oblem, for example wit hin t he HFQ swit ching
t ypes, t he 10C ESR at 100kHz is no mor e t han 2 t hat at r oom t emper at ur e. The
OSCON elect r olyt ics have a ESR vs. t emper at ur e char act er ist ic which is r elat ively
flat .
Figur e 7.33 illust r at es t he high fr equency impedance char act er ist ics of a number of
elect r olyt ic capacit or t ypes, using nominal 100F/20V samples. In t hese plot s, t he
impedance, | Z| , vs. fr equency over t he 20Hz-200kHz r ange is displayed using a
high r esolut ion 4-t er minal set up [Refer ence 8]. Shown in t his display ar e
per for mance samples for a 100F/25V gener al pur pose aluminum unit (t op cur ve @
r ight ), a 120F/25V HFQ unit (next cur ve down @r ight ), a 100F/20V t ant alum
bead t ype (next cur ve down @r ight ), and a 100F/20V OS-CON unit (lowest cur ve @
r ight ). While t he HFQ and t ant alum samples ar e close in 100kHz impedance, t he
11
gener al pur pose unit is about 4 t imes wor se. The OS-CON unit is near ly an or der of
magnit ude lower in 100kHz impedance t han t he t ant alum and swit ching elect r olyt ic
t ypes.
IMPEDANCE Z( ) ) VS. FREQUENCY FOR 100 F
ELECTROLYTIC CAPACITORS (AC CURRENT = 50mA RMS)
7.33
a
100
10
1
0.1
10m
1m
Z ( )
FREQUENCY (Hz)
20 100 1k 10k 100k 200k
"HFQ" 120F, 25V
GEN. PURPOSE AL
100F, 25V
TANTALUM BEAD
100F, 20V
OS-CON AL
100F, 20V
As not ed, all r eal capacit or s have par asit ic element s which limit t heir per for mance.
The equivalent elect r ical net wor k r epr esent ing a r eal capacit or models bot h ESR
and ESL as well as t he basic capacit ance, plus some shunt r esist ance. In such a
pr act ical capacit or , at low fr equencies t he net impedance is almost pur ely capacit ive
(not ed in Figur e 7.33 by t he 100Hz impedance). At int er mediat e fr equencies, t he net
impedance is det er mined by ESR, for example about 0.12 t o 0.4 at 125kHz, for
sever al t ypes. Above about 1MHz t hese capacit or t ypes become induct ive, wit h
impedance dominat ed by t he effect of ESL (not shown). All elect r olyt ics will display
impedance cur ves similar in gener al shape. The minimum impedance will var y wit h
t he ESR, and t he induct ive r egion will var y wit h ESL (which in t ur n is st r ongly
effect ed by package st yle).
Regar ding induct or s, Ferrites (non-conduct ive cer amics manufact ur ed fr om t he
oxides of nickel, zinc, manganese, or ot her compounds) ar e ext r emely useful in
power supply filt er s [Refer ence 9]. At low fr equencies (<100kHz), fer r it es ar e
induct ive; t hus t hey ar e useful in low-pass LC filt er s. Above 100kHz, fer r it es become
r esist ive, an impor t ant char act er ist ic in high-fr equency filt er designs. Fer r it e
impedance is a funct ion of mat er ial, oper at ing fr equency r ange, DC bias cur r ent ,
number of t ur ns, size, shape, and t emper at ur e. Figur e 7.34 summar ize a number
fer r it e char act er ist ics.
CHARACTERISTICS OF FERRITES
n n Good for frequencies above 25kHz
12
n n Many sizes and shapes available including
leaded "resistor style"
n n Ferrite impedance at high frequencies is
primarily resistive -- Ideal for HF filtering
n n Low DC loss: Resistance of wire passing through
ferrite is very low
n n High saturation current
n n Low cost
a 7.34
Sever al fer r it e manufact ur er s offer a wide select ion of fer r it e mat er ials fr om which
t o choose, as well as a var iet y of packaging st yles for t he finished net wor k (see
Refer ences 10 and 11). A simple for m is t he bead of fer r it e mat er ial, a cylinder of t he
fer r it e which is simply slipped over t he power supply lead t o t he decoupled st age.
Alt er nat ely, t he leaded ferrite bead is t he same bead, pr e-mount ed on a lengt h of
wir e and used as a component (see Refer ence 11). Mor e complex beads offer mult iple
holes t hr ough t he cylinder for incr eased decoupling, plus ot her var iat ions. Sur face
mount beads ar e also available.
PSpice fer r it e models for Fair -Rit e mat er ials ar e available, and allow fer r it e
impedance t o be est imat ed [see Refer ence 12]. These models have been designed t o
mat ch measur ed impedances r at her t han t heor et ical impedances.
A fer r it es impedance is dependent upon a number of int er -dependent var iables, and
is difficult t o quant ify analyt ically, t hus select ing t he pr oper fer r it e is not
st r aight for war d. However , knowing t he following syst em char act er ist ics will make
select ion easier . Fir st , det er mine t he fr equency r ange of t he noise t o be filt er ed.
Second, t he expect ed t emper at ur e r ange of t he filt er should be known, as fer r it e
impedance var ies wit h t emper at ur e. Thir d, t he DC cur r ent flowing t hr ough t he
fer r it e must be known, t o ensur e t hat t he fer r it e does not sat ur at e. Alt hough models
and ot her analyt ical t ools may pr ove useful, t he gener al guidelines given above,
coupled wit h some exper iment at ion wit h t he act ual filt er connect ed t o t he supply
out put under syst em load condit ions, should lead t o a pr oper fer r it e select ion.
CHOOSING THE RIGHT FERRITE DEPENDS ON
n n Source of Interference
n n Interference Frequency Range
n n Impedance Required at Interference Frequency
n n Environmental Conditions:
Temperature, AC and DC Field Strength,
13
Size / Space Available
n n Don't fail to Test the Design -------
EXPERIMENT! EXPERIMENT!
a 7.35
Using pr oper component select ion, low and high fr equency band filt er s can be
designed t o smoot h a noisy swit cher s DC out put so as t o pr oduce an analog ready
5V supply. It is most pr act ical t o do t his over t wo (and somet imes mor e) st ages, each
st age opt imized for a r ange of fr equencies. A basic st age can be used t o car r y all of
t he DC load cur r ent , and filt er noise by 60dB or mor e up t o a 1-10MHz r ange. This
lar ger filt er is used as a card entry filter pr oviding br oadband filt er ing for all power
ent er ing a PC car d. Smaller , mor e simple local filt er st ages ar e also used t o pr ovide
higher fr equency decoupling r ight at t he power pins of individual st ages.
Figur e 7.36 illust r at es a car d ent r y filt er suit able for use wit h swit ching supplies.
Wit h a low r olloff point of 1.5kHz and mV level DC er r or s, it is effect ive for a wide
var iet y of filt er applicat ions just as shown. This filt er is a single st age LC low-pass
filt er cover ing t he 1kHz t o 1MHz r ange, using car efully chosen par t s. Because of
component losses, it begins t o lose effect iveness above a few MHz, but is st ill able t o
achieve an at t enuat ion appr oaching 60dB at 1MHz.
"CARD-ENTRY" SWITCHING SUPPLY FILTER
7.36
a
C1
100 F,20V
TANTALUM
R1
1
5V INPUT
FROM NOISY
SWITCHING
SUPPLY OR DC
TO DC
CONVERTER
C2
1 F
CERAMIC
L1
100 H
+
+
- -
OUTPUT TO
300mA LOAD
ANALOG STAGE +
The key t o low DC losses is t he use of input choke, L1, a fer r it e-cor e unit select ed for
a low DC r esist ance (DCR) of <0.25 at t he 100H induct ance (eit her an axial lead
14
t ype 5250 or a r adial st yle 6000-101K choke should give compar able r esult s)
[Refer ence 13]. These chokes have low induct ance shift wit h a 300mA load cur r ent ,
and t he low DCR allows t he 300mA t o be passed wit h no mor e t han 75mV of DC
er r or . Alt er nat ely, r esist ive filt er ing might be used in place of L1, but a basic
t r adeoff her e is t hat load cur r ent capacit y will be compr omised for compar able DC
er r or s. C1, a 100F/20V t ant alum t ype, pr ovides t he bulk of t he capacit ive filt er ing,
shunt ed by a 1F mult ilayer cer amic.
Figur e 7.37 shows t he fr equency r esponse of t his filt er in t er ms of SPICE simulat ion
and lab measur ement s, wit h good agr eement bet ween t he simulat ion and t he
measur ement s below 1MHz.
OUTPUT RESPONSE OF "CARD-ENTRY" FILTER
LAB VS. SIMULATION
7.37
a
0
-20
-40
-60
-80
-100
Z ( )
FREQUENCY (Hz)
10 100 1.0k 10k 100k 1.0M 10M 100M
= SPICE SIMULATION
= LAB RESULTS
X
X X X
X
X
X
X
X
X
X
X
X
X
This t ype of filt er does have some pot ent ial pit falls, and one of t hem is t he cont r ol of
r esonances. If t he LCR cir cuit for med does not have sufficient ly high r esist ance at
t he r esonant fr equency, amplit ude peaking will r esult . This peaking can be
minimized wit h r esist ance at t wo locat ions: in ser ies wit h L1, or in ser ies wit h
C1+C2. Obviously, limit ed r esist ance is usable in ser ies wit h L1, as t his incr eases
t he DC er r or s.
In t he filt er , R1 is a damping r esist or , used t o cont r ol r esonant peaks, and it should
not be eliminat ed. A 1 value pr ovides a slight ly under damped r esponse, wit h
peaking on t he or der of 1dB. Alt er nat ely, 1.5 can be used for less peaking, wit h a
t r adeoff of less at t enuat ion below 1MHz. Not e t hat for wide t emper at ur e r ange
applicat ions, all t emper at ur e sensit ive filt er component s will need consider at ion.
15
A local high fr equency filt er useful wit h t he car d ent r y filt er is shown in Figur e 7.38.
This simple filt er can be consider ed an opt ion, one which is exer cised dependent
upon t he high fr equency char act er ist ics of t he associat ed IC and t he r elat ive
at t enuat ion desir ed. It uses Z1, a leaded fer r it e bead such as t he Panasonic
EXCELSA39, pr oviding a r esist ance of mor e t han 80 at 10MHz, incr easing t o over
100 at 100MHz. The fer r it e bead is best used wit h a local high fr equency
decoupling cap r ight at t he IC power pins, such as a 0.1F cer amic unit shown.
HIGH FREQUENCY LOCALIZED DECOUPLING
7.38 a
Z1
LEADED FERRITE BEAD
PANASONIC EXCELSA39
(OPTIONAL)
+5V
FROM
CARD-ENTRY
FILTER
ANALOG
IC
U1
0.1 F
CERAMIC
TO ADDITIONAL
STAGES
U1
Bot h t he car d ent r y filt er and t he local high fr equency decoupling filt er s ar e
designed t o filt er differ ent ial-mode noise only, and use common, off t he shelf
component s [Refer ence 14].
The following list summar izes t he swit ching power supply filt er layout /const r uct ion
guidelines which will help ensur e t hat t he filt er does t he best possible job:
(1) Pick the highest electrical value and voltage rating for filter capacitors which is
consistent with budget and space limits. This minimizes ES R, and maximizes filter
performance. Pick chokes for low L at the rated DC current, as well as low DCR.
(2) Use short and wide PCB tracks to decrease voltage drops and minimize
inductance. Make track widths at least 200 mils for every inch of track length for
lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and
inductance.
(3) Use short leads or better yet, leadless components, to minimize lead inductance.
This minimizes the tendency to add excessive ES L and/ or ES R. S urface mount
packages are preferred.
16
(4) Use a large-area ground plane for minimum impedance.
(5) Know what your components do over frequency, current and temperature
variations! Make use of vendor component models for the simulation of prototype
designs, and make sure that lab measurements correspond reasonably with the
simulation. While simulation is not absolut ely necessary, it does instill confidence in
a design when correlation is achieved(see Refer ence 15).
The discussion above assumes t hat t he incoming AC power is r elat ively clean, an
assumpt ion not always valid. The AC power line can also be an EMI ent r y/exit pat h!
To r emove t his noise pat h and r educe emissions caused by t he swit ching power
supply or ot her cir cuit s, a power line filter is r equir ed.
It is important to remember that AC line power can potentially be lethal! Do not
experiment without proper equipment and training! All component s used in power
line filt er s should be UL appr oved, and t he best way t o pr ovide t his is t o specify a
packaged UL appr oved filt er . It should be inst alled in such a manner t hat it is t he
fir st t hing t he AC line sees upon ent er ing t he equipment (see Figur e 7.39). St andar d
t hr ee wir e IEC st yle line cor ds ar e designed t o mat e wit h t hr ee t er minal male
connect or s int egr al t o many line filt er s. This is t he best way t o achieve t his
funct ion, as it aut omat ically gr ounds t he t hir d wir e t o t he shell of t he filt er and
equipment chassis via a low induct ance pat h.
POWER LINE FILTERING IS ALSO IMPORTANT
7.39 a
POWER
LINE
POWER
LINE
FILTER
SWITCHING
POWER
SUPPLY
SWITCHING
POWER
SUPPLY
FILTER
Power Line Filter Blocks EMI from Entering
or Exiting Box Via Power Lines
Commer cial power line filt er s can be quit e effect ive in r educing AC power -line noise.
This noise gener ally has bot h common-mode and differ ent ial-mode component s.
Common-mode noise is noise t hat is found on any t wo of t he t hr ee power connect ions
17
(black, whit e, or gr een) wit h t he same amplit ude and polar it y. In cont r ast ,
differ ent ial-mode noise is noise found only bet ween t wo lines. By design, most
commer cially available filt er s addr ess bot h noise modes (see Refer ence 16).
18
REFERENCES: NOI SE REDUCTI ON AND FI LTERI NG
1. EMC Desi gn Wor k sh op Not es, Kimmel-Ger ke Associat es, Lt d.,
St . Paul, MN. 55108, (612) 330-3728.
2. Walt J ung, Dick Mar sh, Picking Capacitors, Parts 1 & 2, Au d i o,
Febr uar y, Mar ch, 1980.
3. Tant alum Elect r olyt ic and Cer amic Capacit or Families, Kemet
Elect r onics, Box 5928, Gr eenville, SC, 29606, (803) 963-6300.
4. Type HFQ Aluminum Elect r olyt ic Capacit or and t ype V St acked
Polyest er Film Capacit or , Panasonic, 2 Panasonic Way, Secaucus,
NJ , 07094, (201) 348-7000.
5. OS-CON Aluminum Elect r olyt ic Capacit or 93/94 Technical Book,
Sanyo, 3333 Sanyo Road, For r est Cit y, AK, 72335, (501) 633-6634.
6. Ian Clelland, Metalized Polyester Film Capacitor Fills High Frequency
S witcher Needs, P CI M, J une 1992.
7. Type 5MC Met allized Polycar bonat e Capacit or , Elect r onic Concept s, Inc.,
Box 1278, Eat ont own, NJ , 07724, (908) 542-7880.
8. Walt J ung, Regulators for High-Performance Audio, Parts 1 and 2,
Th e Au d i o Ama t eu r , issues 1 and 2, 1995.
9. Henr y Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
2d Ed ., 1988, Wiley.
10. Fair -Rit e Linear Fer r it es Cat alog, Fair -Rit e Pr oduct s, Box J , Wallkill,
NY, 12886, (914) 895-2055.
11. Type EXCEL leaded fer r it e bead EMI filt er , and t ype EXC L leadless
fer r it e bead, Panasonic, 2 Panasonic Way, Secaucus, NJ , 07094,
(201) 348-7000.
12. St eve Hageman, Use Ferrite Bead Models to Analyze EMI S uppression,
Th e Desi gn Cen t er Sou r ce, Micr oSim Newslet t er , J anuar y, 1995.
13. Type 5250 and 6000-101K chokes, J . W. Miller , 306 E. Alondr a Blvd.,
Gar dena, CA, 90247, (310) 515-1720.
14. DIGI-KEY, PO Box 677, Thief River Falls, MN, 56701-0677,
(800) 344-4539.
15. Tant alum Elect r olyt ic Capacit or SPICE Models, Kemet Elect r onics,
Box 5928, Gr eenville, SC, 29606, (803) 963-6300.
16. Eichhoff Elect r onics, Inc., 205 Hallene Road, War wick, RI., 02886,
(401) 738-1440.
19
P OWER SUP P LY REGULATI ON/CONDI TI ONI NG
Wa l t J u n g
Many analog cir cuit s r equir e st able r egulat ed volt ages r elat ively close in pot ent ial
t o an unr egulat ed sour ce. An example would be a linear post r egulat or for a
swit ching power supply, wher e volt age loss (dr opout ) is cr it ical. This low dropout
t ype of r egulat or is r eadily implement ed wit h a r ail-r ail out put op amp. The wide
out put swing and low sat ur at ion volt age enables out put s t o come wit hin a fr act ion of
a volt of t he sour ce for medium cur r ent (<30mA) loads, such as r efer ence
applicat ions. For higher out put cur r ent s, t he r ail-r ail volt age swing feat ur e allows
dir ect dr ive t o low sat ur at ion volt age pass devices, such as power PNPs or P-channel
MOSFETs. Op amps wor king fr om 3V up wit h t he r ail-r ail feat ur es ar e most
suit able her e, pr oviding power economy and maximum flexibilit y.
LOW DROP OUT REFERENCES
Ba si c r efer en ces
Among t he many pr oblems in making st able DC volt age r efer ences wor k fr om 5V
and lower supplies ar e quiescent power consumpt ion, over all efficiency, t he abilit y t o
oper at e down t o 3V, low input /out put (dr opout ) capabilit y, and minimum noise
out put . Because low volt age supplies can't suppor t zener s of 6V, low volt age r efer -
ences must necessar ily be bandgap based-- a basic 1.2V pot ent ial. Wit h low volt age
syst ems, power conser vat ion can be a cr it ical issue wit h r efer ences, as can out put
DC pr ecision.
For many applicat ions, simple one-package fixed (or var iable) volt age r efer ences
wit h minimal ext er nal cir cuit r y and high accur acy ar e at t r act ive. Two unique
feat ur es of t he t hr ee t er minal REF19X bandgap r efer ence family ar e low power , and
shut down capabilit y. The ser ies allows fixed out put s fr om 2.048-5V t o be cont r olled
bet ween ON and OFF, via a TTL/CMOS power cont r ol input . It pr ovides pr ecision
r efer ence qualit y for t hose popular volt ages shown in Figur e 7.40.
20
30mA REFERENCE FAMILY WITH OPTIONAL SHUTDOWN
7.40
a
V
OUT
C1
1 F
(TANTALUM)
V
S >
V
OUT
+ 0.5V
TO +15V
V
OUT
(V)
2.048
2.5
3.0
3.3
4.096
4.5
5.0
U1
REF19X
6
+
4
2
3
V
S
+
C2
10 F
V
C
POWER
CONTROL
TTL/CMOS
LEVELS
HIGH (OR OPEN) =
ON
LOW = OFF
U1
REF191
REF192
REF193
REF196
REF198
REF194
REF195
The REF19X family can be used as a simple t hr ee t er minal fixed r efer ence as per
t he t able by t ying pins 2 and 3 t oget her , or as an ON/OFF cont r olled device, by
pr ogr amming pin 3 as not ed. In addit ion t o t he shut down capacit y, t he
dist inguishing funct ional feat ur es ar e a low dr opout of 0.5V at 10mA, and a low
cur r ent dr ain for bot h quiescent and shut down st at es, 45 and 15A (max.),
r espect ively. For example, wor king fr om input s in t he r ange of 6.3 t o 15V, a REF195
used as shown dr ives 5V loads at up t o 30mA, wit h gr ade dependent t oler ances of t2
t o t5mV, and max TCs of 5 t o 25ppm/C. Ot her devices in t he ser ies pr ovide
compar able accur acy specificat ions, and all have low dr opout feat ur es.
To maximize DC accur acy in t his cir cuit , t he out put of U1 should be connect ed
dir ect ly t o t he load wit h shor t heavy t r aces, t o minimize IR dr ops. The common
t er minal (pin 4) is less cr it ical due t o lower cur r ent in t his leg.
Sca led Refer en ces
Anot her appr oach, one wit h t he advant age of volt age flexibilit y, is t o buffer /scale a
low volt age r efer ence diode. Wit h t his appr oach, one difficult y is get t ing an amplifier
t o wor k well at 3V. A wor khor se solut ion is t he low power r efer ence and scaling
buffer shown in Figur e 7.41. Her e a low cur r ent 1.2V, t wo-t er minal r efer ence diode
is used for D1, eit her t he 1.235V AD589 or t he 1.225V AD1580. Resist or R1 set s t he
diode cur r ent , chosen for 50A at a minimum supply of 2.7V. Obviously, loading on
t he unbuffer ed diode must be minimized at t he V
REF
node.
21
RAIL-TO-RAIL OUTPUT OP AMPS ALLOW GREATEST
FLEXIBILITY IN LOW DROPOUT REGULATORS
7.41
C1
0.1 F
R3
R2
D1
AD589
+1.235V
AD1580
+1.225V
U1
+3V OR MORE
V
REF
(UNBUFFERED)
V
OUT
= V
REF
OR
V
OUT
= V
REF
(1 + R2/R3)
U1: SEE TEXT
R1
27.4k
+
-
a
Amplifier U1 bot h buffer s and opt ionally scales up t he nominal 1.2V r efer ence,
allowing much higher sour ce/sink cur r ent s. A higher op amp quiescent cur r ent is
expended in doing t his, but t his is a basic t r adeoff of t he appr oach. Quiescent
cur r ent is amplifier dependent , r anging fr om 45A/channel wit h t he OP196/296/496
ser ies t o 1000-2000A/channel wit h t he OP284 and OP279. The for mer ser ies is
most useful for ver y light loads (<2mA), while t he lat t er ser ies pr ovide device
dependent out put s up t o 50mA. Var ious devices can be used in t he cir cuit as shown,
and t heir key specs ar e summar ized in Figur e 7.42.
OP AMPS USEFUL IN LOW VOLTAGE RAIL-RAIL REFERENCES
AND REGULATORS

Device* Iq/channel
mA
Vsat(+),
V(min @ mA)
Vsat(-), V
(max @ mA)
Isc, mA
(min)
OP193/293/493 0.017 4.20 @ 1 0.280 @ 1
(typ)
8
OP196/296/496 0.045 4.30 @ 1 0.430 @ 1 4
OP295/495 0.150 (max) 4.50 @ 1 0.110 @ 1 11
OP191/291/491 0.300 4.80 @ 2.5 0.075 @ 2.5 8.75
AD820/822/824 0.620 4.89 @ 2 0.055 @ 2 15
OP184/284/484 1.250 (max) 4.85 @ 2.5 0.125 @ 2.5 7.5
22
OP279 2.000 4.80 @ 10 0.075 @ 10 45
*Typical device specifications @ Vs = +5V, T
A
= 25 C, unless otherwise noted.
a 7.42
In Figur e 7.41, wit hout gain scaling r esist or s R2-R3, V
OUT
is simply equal t o V
REF
.
Wit h t he scaling r esist or s, V
OUT
can be set anywher e bet ween V
REF
and t he
posit ive r ail, due t o t he op amps r ail-r ail out put swing. Also, t his buffer ed r efer ence
is inher ent ly low dr opout , allowing a +4.5V r efer ence out put on a +5V supply, for
example. The gener al expr ession for V
OUT
is shown in t he figur e, wher e V
REF
is
t he r efer ence volt age.
Amplifier st andby cur r ent can be fur t her r educed below 20A, if an amplifier fr om
t he OP193/293/493 ser ies is used. This will be at t he expense of cur r ent dr ive and
posit ive r ail sat ur at ion, but does pr ovide t he lowest possible quiescent cur r ent if
necessar y. All devices in Figur e 7.42 oper at e fr om volt ages down t o 3V (except t he
OP279, which oper at es at 5V).
Low Dr op ou t Regu la t or s
By adding a boost t r ansist or t o t he basic r ail-r ail out put low dr opout r efer ence of
Figur e 7.41, out put cur r ent s of 100mA or mor e ar e possible, st ill r et aining feat ur es
of low st andby cur r ent and low dr opout volt age. Figur e 7.43 shows a low dr opout
r egulat or wit h 800A st andby cur r ent , suit able for a var iet y of out put s at cur r ent
levels of 100mA.
100mA LOW NOISE, LOW DROPOUT REGULATOR
7.43
a
V
OUT
V
OUT
6V
5V
4V
3.3V
3.0V
+
+V
IN
+
C1
100 F/25V
(LOW ESR)
R4
39.2k
C5
0.1 F
R3
2k
R1
(TABLE)
Q1
MJE170
U1
AD820
C4
0.01 F
COMMON
C2
100 F/25V
(LOW ESR)
3-6V (TABLE)
C3
1 F
FILM
R5
100k
D1
AD589
1.235V
R2
100k
+ -
6
4 7
2 3
R1
383k
301k
226k
169k
143k
V
IN
(min)
6.2V
5.2V
4.2V
3.5V
3.2V
OUTPUT TABLE
23
The 100mA out put is achieved wit h a cont r olled gain bipolar power t r ansist or for
pass device Q1, an MJ E170. Maximum out put cur r ent cont r ol is pr ovided by
limit ing base dr ive t o Q1 via ser ies r esist or R3. This limit s t he base cur r ent t o about
2mA, so t he max H
FE
of Q1 t hen allows no mor e t han 500mA. This limit s Q1s shor t
cir cuit power dissipat ion t o safe levels.
Over all, t he cir cuit oper at es as a follower wit h gain, as was t r ue in t he case of
Figur e 7.41, so V
OUT
has a similar out put expr ession. The cir cuit is adapt ed for
differ ent volt ages simply by pr ogr amming R1 via t he t able. Dr opout wit h a 100mA
load is about 200mV, t hus a 5V out put is maint ained for input s above 5.2V (see
t able), and V
OUT
levels down t o 3V ar e possible. St ep load r esponse of t his cir cuit is
quit e good, and t r ansient er r or is only a few mVp-p for a 30-100mA load change.
This is achieved wit h low ESR swit ching t ype capacit or s at C1-C2, but t he cir cuit
also wor ks wit h convent ional elect r olyt ics (wit h higher t r ansient er r or s).
If desir ed, lowest out put noise wit h t he AD820 is r eached by including t he opt ional
r efer ence noise filt er , R5-C3. Lower cur r ent op amps can also be used for lower
st andby cur r ent , but wit h lar ger t r ansient er r or s due t o r educed bandwidt h.
While t he 30mA r at ed out put cur r ent of t he REF19X ser ies is higher t han most
r efer ence ICs, it can be boost ed t o much higher levels if desir ed, wit h t he addit ion of
a PNP t r ansist or , as shown in Figur e 7.44. This cir cuit uses full t ime cur r ent
limit ing for pr ot ect ion of pass t r ansist or shor t s.
150 mA BOOSTED OUTPUT REGULATOR/REFERENCE
WITH CURRENT LIMITING
7.44
a
U1
REF192
REF193
REF196
REF194
REF195
V
OUT
(V)
2.5
3.0
3.3
4.5
5.0
R1
1k
V
OUT
+V
S
= 6 TO 9V
(SEE TEXT)
+
C2
100 F/25V
Q2
2N3906
COMMON
C3
0.1 F
R4
2
R
L
COMMON
V
S
U1
REF196
(SEE TABLE)
V
C
C1
10 F/25V
(TANTALUM)
4
3 6
2
+
R2
1.5k
Q2
TIP32A
(SEE TEXT)
D1
1N4148
(SEE TEXT
ON SLEEP)
R3
1.82k
F
S
S
F
+V
OUT
3.3V
@ 150mA
OUTPUT TABLE
In t his cir cuit t he supply cur r ent of r efer ence U1 flows in R1-R2, developing a base
dr ive for pass device Q1, whose collect or pr ovides t he bulk of t he out put cur r ent .
Wit h a t ypical gain of 100 in Q1 for 100-200mA loads, U1 is never r equir ed t o
fur nish mor e t han a few mA, and t his fact or minimizes t emper at ur e r elat ed dr ift .
24
Shor t cir cuit pr ot ect ion is pr ovided by Q2, which clamps dr ive t o Q1 at about 300mA
of load cur r ent . Wit h separ at ion of cont r ol/power funct ions, DC st abilit y is opt imum,
allowing best advant age of pr emium gr ade REF19X devices for U1. Of cour se, load
management should st ill be exer cised. A shor t , heavy, low r esist ance conduct or
should be used fr om U1-6 t o t he V
OUT
sense point S, wher e t he collect or of Q1
connect s t o t he load.
Because of t he cur r ent limit ing, dr opout volt age is r aised about 1.1V over t hat of t he
REF19X devices. However , over all dr opout t ypically is st ill low enough t o allow
oper at ion of a 5 t o 3.3V r egulat or /r efer ence using t he 3.3V REF-196 for U1, wit h a
Vs of 4.5V and a load cur r ent of 150mA.
The heat sink r equir ement s of Q1 depend upon t he maximum power . Wit h Vs = 5V
and a 300mA cur r ent limit , t he wor st case dissipat ion of Q1 is 1.5W, less t han t he
TO-220 package 2W limit . If TO-39 or TO-5 packaged devices such as t he 2N4033
ar e used, t he cur r ent limit should be r educed t o keep maximum dissipat ion below
t he package r at ing, by r aising R4. A t ant alum out put capacit or is used at C1 for it s
low ESR, and t he higher value is r equir ed for st abilit y. Capacit or C2 pr ovides input
bypassing, and can be an or dinar y elect r olyt ic.
Shut down cont r ol of t he boost er st age is shown as an opt ion, and when used, some
caut ions ar e in or der . To enable shut down cont r ol, t he connect ion t o U1-2 and U1-3
is br oken at X, and diode D1 allows a CMOS cont r ol sour ce t o dr ive U1-3 for
ON/OFF cont r ol. St ar t up fr om shut down is not as clean under heavy load as it is
wit h t he basic REF19X ser ies st and-alone, and can r equir e sever al milliseconds
under load. Never t heless, it is st ill effect ive, and can fully cont r ol 150mA loads.
When shut down cont r ol is used, heavy capacit ive loads should be minimized.
Dedicat ed low dr opout linear IC r egulat or s offer all t he vir t ues of t he discr et e
appr oaches, but in a easier -t o-use compact for mat . The ADP3367 is such a device,
pr oviding eit her a fixed out put of 5V t2%, or adjust able out put s over a r ange of 1.3
t o 16.5V, wit h cur r ent out put s up t o 300mA. Using a CMOS ar chit ect ur e wit h a
PNP pass t r ansist or , it has a quiescent cur r ent of 25A (max., unloaded), and a
dr opout volt age of 175mV (max.) wit h a 100mA out put .
Figur e 7.45 shows t he basic hookup for t he ADP3367, which uses t he "t her mal
coast line" 8 pin SOIC package, which is designed for power dissipat ion up t o
960mW. For fixed 5V out put s, R1 and R2 ar ent used, and t he SET pin is gr ounded
as shown. Wit h t he SHDN pin also gr ounded, t his simple hookup pr ovides a
const ant 5V at V
OUT
, wit h t he low dr opout feat ur es ment ioned.
25
R1
WITH R1, R2:
V
OUT
= V
REF
( )
WHERE V
REF
= +1.255V,
V
OUT
= +3.3V (VALUES SHOWN)
a
300mA LOW DROPOUT FIXED/VARIABLE
REGULATOR WITH OPTIONAL SHUTDOWN
7.45
R2
R2
162k
V
IN V
OUT
C1
0.1 F
C2
10 F
R1
100k
V
SHDN
IN OUT
SET
SHDN
+5.15V
TO
+16.5V
+5V
*
*
GND
+
1 +
ADP3367
The ADP3367s useful out put cur r ent capacit y will be dependent upon t he V
IN
-V
OUT
differ ent ial, such t hat t he r esult ing power it dissipat es is cont ained t o 960 mW or
less. For example, at low input -out put differ ences of 2.5V, up t o 300mA is available.
For higher input -out put differ ences, t he allowable cur r ent is r educed accor ding t o
t he cur ves shown in Figur e 7.46. The upper shaded cur ve cor r esponds t o t he out put
cur r ent which is consist ent wit h t he ADP3367s package limit at ions. Not e t hat t he
allowable out put cur r ent is appr eciably higher t han t hat of a st andar d SO package,
shown in t he lower shaded cur ve.
26
7.46
ADP3367 LOAD CURRENT VS. INPUT - OUTPUT VOLTAGE
a
VIN-VOUT - V
400
200
0
0 15 5 10
100
TA = +50C
300
GUARANTEED 300mA
ADP3367
DISSIPATION LIMIT
STANDARD
SO PACKAGE
DISSIPATION LIMIT
L
O
A
D

C
U
R
R
E
N
T

-

m
A
The ADP3367 can be placed in a shut down mode, which r educes t he out put volt age
t o zer o and dr ops t he st andby cur r ent t o less t han 1A. When implement ed,
shut down is accomplished by applying a cont r ol volt age of mor e t han 1.5V t o V
SHDN
.
Ot her wise, t his pin should be t ied t o gr ound as shown. The SET pin has a dual
funct ion, and can be used eit her t o select an int er nal divider (which pr ovides t he
fixed 5V out put ), or it can be used wit h an ext er nal divider , R1-R2. When t he SET
pin is gr ounded, t he int er nal divider is act ive, and t he 5 V out put r esult s. When t he
SET pin is used wit h t he ext er nal divider , V
OUT
is pr ogr ammed as:
V
OUT
V
REF
R2
R1
+

_
,

1
wher e V
REF
is 1.255V, t he int er nal r efer ence volt age of t he ADP3367. The divider s
absolut e r esist ance values ar e not cr it ical, since t he input cur r ent at t he SET pin is
low, t ypically 10pA. This allows r esist ances of 100k - 1meg, consist ent wit h t he
over all low st andby power object ives. The example 1% values shown pr ovide a 3.3V
out put . They can be fur t her incr eased, if it is desir ed t o lower st andby cur r ent
consumpt ion below t he 12A r esult ing wit h t he values shown.
C2, t he out put capacit or , is a 10F t ype, and is r equir ed for r egulat or st abilit y.
Lar ger sizes ar e per missible, and will help impr ove t r ansient r esponse. An input
bypass is also r ecommended, C1.
To achieve t he full power capabilit y inher ent t o t he design, t he ADP3367 should be
mount ed on a PCB in such as way t hat int er nally-gener at ed heat can flow out war d
easily fr om t he die t o t he PCB. Lar ge ar ea PCB copper t r aces should be used
beneat h and ar ound t he IC, and mount ing should be such t hat t he par t is exposed t o
unr est r ict ed air flow [see Refer ence 5].
27
28
REFERENCES: P OWER SUP P LY
REGULATI ON/CONDI TI ONI NG

1. Walt J ung, Build an Ultra-Low-Noise Voltage Reference,
Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e, J une 24, 1993.
2. Walt J ung, Getting the Most from IC Voltage References, An a log
Di a logu e 28-1, 1994.
3. Walt J ung, The Ins and Outs of Green Regulators/ References ,
Elect r on i c Desi gn An a log Ap p li ca t i on s I ssu e, J une 27, 1994.
4. Walt J ung, Very-Low-Noise 5-V Regulator, Elect r on i c Desi gn ,
J uly 25, 1994.
5. Power DissipationDiscussions, ADP 3367 Da t a Sh eet , Analog Devices.
29
THERMAL MANAGEMENT
Wa l t J u n g
For r eliabilit y r easons, moder n semiconduct or based syst ems ar e incr easingly called
upon t o obser ve some for m of thermal management. All semiconduct or s have some
specified safe upper limit t o junct ion t emper at ur e (T
J )
, usually on t he or der of 150C
(but somet imes 175). Like maximum power supply pot ent ials, maximum junct ion
t emper at ur e is a wor st case limit at ion which shouldnt be exceeded. In conser vat ive
designs, it wont be appr oached by less t han an ample safet y mar gin. This is a
cr it ical point , since t he lifet ime of all semiconduct or s is inver sely r elat ed t o t heir
oper at ing junct ion t emper at ur e. The cooler semiconduct or s can be kept dur ing
oper at ion, t he mor e closely t hey will appr oach maximum useful life.
Th er ma l ba si cs
The gener al symbol is used for thermal resistance, t hat is:
= t her mal r esist ance, in unit s of C/wat t (or , C/W).

J A
and
J C
ar e t wo mor e specific t er ms used in dealing wit h semiconduct or
t her mal issues, which ar e fur t her explained below.
In gener al, a device wit h a t her mal r esist ance equal t o 100C/W will exhibit a
t emper at ur e differ ent ial of 100C for a power dissipat ion of 1W, as measur ed
bet ween t wo r efer ence point s. Not e t hat t his is a linear r elat ion, so a 500mW
dissipat ion in t he same par t will pr oduce a 50C differ ent ial, and so for t h. For any
power P (in wat t s), calculat e t he effect ive t emper at ur e differ ent ial (T) in C as:
T = P
wher e is t he t ot al applicable t her mal r esist ance. Figur e 7.47 summar izes t hese
t her mal r elat ionships.
THERMAL BASICS
n n = Thermal Resistance (C/W)
n n T = P
n n
JA
= Junction - to - Ambient Thermal Resistance
n n
JC
= Junction - to - Case Thermal Resistance
n n
CA
= Case - to - Ambient Thermal Resistance
n n
JA
=
JC
+
CA
n n T
J
= T
A
+ (P
JA
)
,
P = Total Device Power Dissipation
n n T
J(Max)
= 150C (Sometimes 175C)
30
a 7.47
A r eal example illust r at ing t his r elat ionship is shown by Figur e 7.48. These cur ves
indicat e t he maximum power dissipat ion vs. t emper at ur e char act er ist ic for a device
using 8 pin DIP and SOIC packaging. For a T
J (max)
of 150C, t he upper cur ve
shows t he allowable power in a DIP package. This cor r esponds t o a which can be
calculat ed by dividing t he T by P at any point . For example, 1W of power is allowed
at a T
A
of 60C, so t he T is 150C 60C = 90C. Dividing by 1W gives t his DIP
packages of 90C/W. Similar ly, t he SOIC package yields 160C/W. These figur es
ar e in fact t he
J A
for t he AD823 op amp, but t hey also happen t o be quit e similar
t o ot her 8 pin devices. Given such dat a as t hese cur ves, t he
J A
for

a given device
can be r eadily det er mined, as above.
7.48
MAXIMUM POWER DISSIPATION VS. TEMPERATURE
FOR 8-PIN MINI-DIP AND 8-PIN SOIC PACKAGES
M
A
X
I
M
U
M

P
O
W
E
R

D
I
S
S
I
P
A
T
I
O
N

-

W
a
t
t
s
AMBIENT TEMPERATURE - C
2.0
1.5
0
-50 90 -40 -30 -20 -10 0 10 20 30 50 60 70 80 40
1.0
0.5
8-PIN MINI-DIP PACKAGE
8-PIN SOIC PACKAGE
TJ = +150C
As t he r elat ionship signifies, t o maint ain a low T
J
, eit her or t he power dissipat ed
(or bot h) must be kept low. A low T is t he key t o ext ending semiconduct or lifet imes,
as it leads t o low maximum junct ion t emper at ur es.
In semiconduct or s, one t emper at ur e r efer ence point is always t he device junct ion,
t aken t o mean t he hot t est spot inside t he chip oper at ing wit hin a given package.
The ot her r elevant r efer ence point will be eit her t he case of t he device, or t he
ambient temperature, T
A
, t hat of t he sur r ounding air . This t hen leads in t ur n t o t he
above ment ioned individual t her mal r esist ances,
J A
and
J C
.
31
Taking t he mor e simple case fir st ,
J A
is t he t her mal r esist ance of a given device
measur ed bet ween it s junction and t he ambient air . This t her mal r esist ance is most
oft en used wit h small, r elat ively low power ICs which do not dissipat e ser ious
amount s of power , t hat is 1W or less.
J A
figur es t ypical of op amps and ot her small
devices ar e on t he or der of 90-100C/W for a plast ic 8 pin DIP package. It must be
under st ood t hat t her mal r esist ances ar e highly package dependent , as differ ent
mat er ials have differ ing degr ees of t her mal conduct ivit y. As a gener al r ule of t humb,
t her mal r esist ance for t he conduct or s wit hin packaging mat er ials is closely
analogous t o elect r ical r esist ances, t hat is copper is t he best , followed by aluminum,
st eel, and so on. Thus copper lead fr ame packages offer t he highest per for mance
(lowest ).
A summar y of t he t her mal r esist ances of var ious IC packages is shown in Figur es
7.49 and 7.50. In gener al, most of t hese packages do not lend t hemselves t o easy
heat sink at t achment (wit h not able except ions, such as t he older r ound met al can
t ypes). Devices which are amenable t o heat sink at t achment will oft en be not ed by a

J C
dr amat ically lower t han t he
J A
. See for example t he 15 pin SIP package (used
by t he AD815).
STANDARD PACKAGE THERMAL RESISTANCES - 1
Package ADI
designation

JA
( C/W)

JC
( C/W)
Comment
8 pin plastic DIP N-8 90 AD823
8 pin ceramic DIP D-8 110 22 AD712
8 pin SOIC R-8 160 60
8 pin SOIC R-8 90 60 ADP3367 Thermal Coastline
8 pin metal can H-08A (TO-99) 150 45 OP07
10 pin metal can H-10A (TO-100) 150 25 AD582
12 pin metal can H-12A (TO-8) 100 30 AD841
14 pin plastic DIP N-14 150 AD713
14 pin ceramic DIP D-14 110 30 AD585
14 pin SOIC R-14 120 AD813
15 pin SIP Y-15 41 2 AD815 Through-Hole
16 pin plastic DIP N-16 120 40
16 pin ceramic DIP D-16 95 22 AD524
16 pin SOIC R-16 85 AD811
a 7.49
STANDARD PACKAGE THERMAL RESISTANCES - 2
Package ADI
designation

JA

( C/W)

JC
( C/W)
Comment
32
18 pin ceramic DIP D-18 120 35 AD7575
20 pin plastic DIP N-20 102 31
20 pin ceramic DIP D-20 70 10
20 pin SOIC R-20 74 24
24 pin plastic DIP N-24 105 35
24 pin ceramic DIP D-24 120 35 AD7547
28 pin plastic DIP N-28 74 24
28 pin ceramic DIP D-28 51 8
28 pin SOIC R-28 71 23
a 7.50

J C
is t he t her mal r esist ance of a given device as measur ed bet ween it s junction and
t he device case. This for m is most oft en used wit h lar ger power semiconduct or s
which do dissipat e significant amount s of power , t hat is t ypically mor e t han 1W. The
r eason for t his is t hat a heat sink gener ally must be used wit h such devices, t o
maint ain a sufficient ly low int er nal junct ion t emper at ur e. A heat sink is simply an
addit ional low t her mal r esist ance device at t ached ext er nally t o a semiconduct or par t
t o aid in heat r emoval. It will have some addit ional t her mal r esist ance of it s own,
also r at ed in C/W.
Rat her t han just a single number , in t his case will be composed of mor e t han one
component , i.e.,
1
,
2
, et c. Like ser ies r esist or s, t her mal impedances add, making a
net calculat ion r elat ively simple. For example, t o comput e a net
J A
given a
r elevant
J C
, t he t her mal r esist ance of t he heat sink,
CA
, or case t o ambient is
added t o t he
J C
as:

J A
=

J C +

CA
and

t he r esult is

t he
J A
for t hat specific cir cumst ance.
A second for m of t he gener al over all r elat ionship bet ween T
J
, T
A
, P and is:
T
J
=

T
A
+ (P )
To t ake a r eal wor ld example, t he AD815AVR power -t ab packaged op amp has a

J A
of 41C/W wit h no addit ional heat sinking (t he device simply oper at ing in st ill
air ). Using it just as t his would allow a power of:
P = (T
J


T
A
)
/

J A
or , (150C 70C)/41C /W, which r esult s in an allowable power of about 2W.
33
However , such a mode of oper at ion falls shor t of t he devices full power handling
capacit y. The AD815AVRs
J C
is quit e low at about 2C/W, and if a heat sink of
significant ly less t han 38C/W is used wit h it , t hen it can dissipat e much mor e
power for a given junct ion t emper at ur e. A 20C/W heat sink will allow almost t wice
t he power t o be dissipat ed by t he same device, simply because of t he lower net
J A
only 22C/W. This can be accomplished by a double-sided PCB copper plane ar ea of
1k mm
2
[see Refer ence 1].
To illust r at e, t he gener al r elat ionship of t he AD815AVR and PCB heat sink net
J A
is shown by Figur e 7.51. In t he fir st example cit ed above, full advant age of PCB
heat sink ar ea was not t aken, and as t he gr aph shows, t he net
J A
can be r educed
t o as low as 17C/W by incr easing t he heat sink ar ea fur t her . The t r adeoff is simply
one of boar d ar ea, and wit h a 2k mm
2
heat sink ar ea, near ly 5W of power can be
handled by t he same device, assuming t he same T and max T
J
. Of cour se, for t he
AD815 (and ot her devices) even mor e conser vat ive oper at ion is opt ionally possible
by holding t o a lower maximum T
J
.
Not e t hat for t he dat a of Figur e 7.51, t hese dat a assume t hat t he AD815AVR is
solder ed dir ect ly t o one of t he dual copper PCB planes.
The power t ab st yle package used wit h t he AD815AVR can also be used wit h
convent ional PC mount ed heat sinks, wit h
J C
of 20C/W and less. See Refer ence 2.
COPPER HEAT SINK AREA (TOP AND BOTTOM) - mm2
35
30
10
0 2.5k 0.5k 1k 1.5k 2k
25
20
15
AD815AVR, AY ( JC = 2C/W)
7.51
AD815AVR AND PCB HEAT SINK
JA
VS.
PCB HEAT SINK AREA

J
A

-

C
/
W
34
Ca lcu la t i n g P ower I n Va r i ou s Devi ces
In all inst ances of t her mal calculat ions, a basic assumpt ion is t hat t he power is t he
t ot al for a given package. Wit h many moder n devices now using mor e t han one
supply, t he net t ot al power dissipat ed will be t he sum of all individual supply
quiescent power s, plus any load dependent power . For many low out put cur r ent op
amps for example, t ot al power will t hen be essent ially t he same as t he quiescent . As
long as t his is safely less t han t he package can suppor t , t her e is lit t le wor r y.
However , wit h some devices oper able over a wide r ange of supply volt ages, t her e ar e
inst ances wher e high supply volt ages and a medium t o high quiescent cur r ent plus
load cur r ent can be a pr oblem.
The AD811 is such an example, being capable of oper at ion fr om t5V t o t15V, wit h a
quiescent cur r ent of about 16mA. If oper at ed at t15V, t he quiescent dissipat ion is
near ly 500mW, which wit h a 90C/W
J A
, will push T
J
t o about 115C in a 70C
ambient , high enough for concer n. If t he signal volt age out put for such an amplifier
doesnt r equir e t he t15V supplies, t hen r educing t he supplies will lower t he
quiescent power , and T
J
.
To illust r at e a gener al r elat ionship of t he power dissipat ed in an op amp and t he
power in a load for family of supply volt ages, Figur e 7.52 was pr epar ed. This is a
t est simulat ion of a st andar d gain-of-2 non inver t ing amplifier dr iving a 150 load,
wit h 1k gain and feedback r esist or s. Assuming an input volt age of 1V DC, t he 2V
out put acr oss t he net r esist or load of 150| | 2k=140 will pr oduce a power P
r
of
about 29mW. The AD817 amplifier oper at es over a supply r ange of t5V t o t15V,
which is t he Vs sweep r ange for t he t est cir cuit . The op amp quiescent power P
q
incr eases t o 210mW at t15V, while t he signal power P
s
dissipat ed by t he op amp
incr eases t o 187mW at t15V. The t ot al power in t he op amp is t heir sum, 397mW at
t15V. Clear ly, oper at ing r elat ively high cur r ent and low volt age loads fr om an op
amp does wast e consider able power , and lower volt age supplies will be much mor e
efficient , wher e allowable.
35
a
AD817 OP AMP POWER DISSIPATION VS. SUPPLY VOLTAGE
7.52
+
-
AD817
+2V
150
1k
+1V
1k
+V
S
-V
S
POWER
(mW)
V
S
, VOLTS
400
300
200
100
0
0 5 10 15
P
s
+ P
q
= TOTAL
OP AMP POWER
P
q
= QUIESCENT POWER
P
s
= SIGNAL POWER
P
r
= LOAD POWER
Wher e appr opr iat e, a clip on DIP compat ible heat sink such as t he AAVID 580100
can be used [Refer ence 3]. This ser ies has sinks compat ible wit h ICs of 8 t hr ough 40
pin sizes, using a st agger ed fin design. Per for mance of t hese (and all) heat sinks is
enhanced by air movement , eit her t hr ough for ced convect ion, or as a minimum, by
ar r anging PCB car ds ver t ically t o enhance nat ur al convect ion.
A/D conver t er s can consume consider able power , alt hough t he t r end is t owar ds
lower volt age and lower power dissipat ion. Like op amps, t hey ar e gener ally
analyzed by adding up t he t ot al power in t he package, which can t hen be used wit h
t he packages
J A
t o comput e junct ion t emper at ur e. In adding var ious power t ot als,
some car e should be made t o ascer t ain if any power is clock dependent. In some
CMOS based designs, t her e can be appr eciable differ ences in power as a funct ion
high/low clock speed as shown in Figur e 7.53 for t he AD9220 12-bit , 10MSPS ADC.
36
7.53
AD9220 12-BIT, 10MSPS CMOS ADC POWER DISSIPATION
VS. SAMPLING CLOCK FREQUENCY
a
CLOCK FREQUENCY - MHz
300
240
12 10
280
260
INPUT = 5Vp-p
INPUT = 2Vp-p
220
200
8 6 4 2 0 14
P
O
W
E
R

-

m
W
For example, t he AD9042 12 bit A/D consumes about 600mW t ot al on t wo 5V
supplies, and it s 28 pin DIP package has a
J A
of 34C/W. What will be t he max T
J
for t his par t in a T
A
of 70C? You should get a T
J
of 90.4C (T = 0.6W 34C/W =
20.4C, so T
J
for T
A
of 70C = 70C + 20.4C). This par t icular par t is t her efor e in
good shape for t his T
A
, assuming t hat t her e ar e no adjacent hot spot sour ces t o
incr ease t he devices effect ive T
A
.
Ai r flow Con t r ol
For lar ge power dissipat ions and/or t o maint ain low T
J
s, for ced air movement can
be used t o incr ease air flow and aid in heat r emoval. In it s most simple for m t his can
consist of a cont inuously or t her most at ically oper at ed fan, dir ect ed acr oss high
t emper at ur e, high wat t age dissipat ion devices such as CPUs, DSP chips, et c.
Quit e oft en however , mor e sophist icat ed t emper at ur e cont r ol is necessar y. Recent
t emper at ur e monit or ing and cont r ol ICs such as t he TMP12, an air flow t emper at ur e
sensor IC, lend t hemselves t o such applicat ions.
The TMP12 includes on chip t wo compar at or s, a volt age r efer ence, a t emper at ur e
sensor and a heat er . The heat er is used t o for ce a pr edict able int er nal t emper at ur e
r ise, t o mat ch a power IC such as a micr opr ocessor . The t emper at ur e sensing and
cont r ol por t ions of t he IC can t hen be pr ogr ammed t o r espond t o t he t emper at ur e
changes and cont r ol an ext er nal fan, so as t o maint ain some r ange of t emper at ur e.
Compar ed t o a simple t her most at , t his allows infinit e r esolut ion of user cont r ol for
cont r ol point s and ON/OFF hyst er esis.
The device is placed in an air st r eam near t he power IC, such t hat bot h see t he same
st r eam of air , and will t hus have like t emper at ur e pr ofiles, assuming pr oper cont r ol
of t he st r eam. This is shown in basic for m by t he layout diagr am of Figur e 7.54.
37
7.54
SYSTEM USE OF TMP12 AIRFLOW SENSOR
a
POWER I.C.
PGA
PACKAGE
PGA
SOCKET
PC BOARD
AIR FLOW
TMP12
Wit h t he TMP12s int er nal 250mW heat er ON and no air flow, t he TMP12 t her mal
pr ofile will look like t he cur ve A of Figur e 7.55, and will show a 20C r ise above
T
A
. When air flow is pr ovided, t his same dissipat ion r esult s in a lower t emper at ur e,
D. In pr ogr amming t he device for air speed cont r ol, t he designer can set up t o t wo
swit ch point s, shown her e symbolically by B and C, which ar e HIGH and LOW
set point s, r espect ively. The basic idea is t hat when t he IC subst r at e r eaches point B
in t emper at ur e, t he ext er nal fan will be t ur ned on t o cr eat e t he air st r eam, and lower
t he t emper at ur e. If t he over all syst em set up is r easonable in t er ms of t her mal
pr ofiling, t his small IC can t hus be used t o indir ect ly cont r ol anot her lar ger and
independent power sour ce wit h r egar d t o it s t emper at ur e. Not e t hat t he dual mode
cont r ol need not necessar ily be used, in all applicat ions. An unused compar at or is
simply wir ed high or low.
38
7.55
TMP12 TEMPERATURE RELATIONSHIPS
a
35
40
45
50
55
60
65
50 100 150 200 250
0
TMP12 P
D
(mW)
a. TMP12 DIE TEMP NO AIR FLOW
c. LOW SET POINT
b. HIGH SET POINT
d. TMP12 DIE TEMP MAX AIR FLOW
e. SYSTEM AMBIENT TEMPERATURE
a
b
c
d
e
D
I
E

T
E
M
P
E
R
A
T
U
R
E

(

C
)
Figur e 7.56 shows a cir cuit diagr am using t he TMP12 as a gener al pur pose
cont r oller . The device is connect ed t o a 5V supply, which is also used t o power a
cont r ol r elay and t he TMP12s int er nal heat er at pin 5. Set point pr ogr amming of t he
TMP12 is accomplished by t he r esist or st r ing at pins 4 t hr ough 1, R1

- R3. These
r esist or s est ablish a cur r ent dr ain fr om t he int er nal r efer ence sour ce at pin 4, which
set s up a r efer ence cur r ent , I
REF
, which is set as:
I
REF
= (5A/C T
HYS
)+ 7A
In t his expr ession, T
HYS
is t he hyst er esis

t emper at ur e swing desir ed about t he
set point , in C, and t he 7A is r ecommended minimum loading of t he r efer ence. For
a 2C hyst er esis for example, I
REF
is 17A; for 5C, it would be 32A.
Given a desir ed set point t emper at ur e in C, t he set point can be conver t ed t o a
cor r esponding volt age. Alt hough not available ext er nally, t he int er nal t emper at ur e
dependent volt age of t he TMP12 is scaled at 5mV/C, and is equal t o 1.49V at 25C.
To conver t a set point t emper at ur e t o a volt age V
SETPOINT
,
V
SETPOINT
= 1.49V + [ 5mV/C (T
SETPOINT
T
25
) ]
wher e T
SETPOINT
is t he desir ed set point t emper at ur e, and T
25
is 25C. For a
50C high set point , t his wor ks out t o be V
SETPOINT(HI)
= 1.615V. For a lower
set point of 35C, t he volt age V
SETPOINT(LO)
would be 1.59V.
39
The divider r esist or s ar e t hen chosen t o dr aw t he r equir ed cur r ent I
REF
while
set t ing t he t wo t ap volt ages cor r esponding t o V
SETPOINT(HI)
and
V
SETPOINT(LO)
.
R
TOTAL
= V
REF
/ I
REF

= 2.5V / I
REF
R1 = [ V
REF
V
SETPOINT(HI)
] / I
REF
= [ 2.5V V
SETPOINT(HI)
] / I
REF
R2= [ V
SETPOINT(HI)
V
SETPOINT(LO)
] / I
REF
R3 = V
SETPOINT(LO)
/ I
REF
In t he example of t he figur e, t he r esult ing st andar d values for R1 - R3 cor r espond t o
t he t emper at ur e/volt age set point examples not ed above. Ideal 1% values shown give
r esist or r elat ed er r or s of only 0.1C fr om ideal. Not e t hat t his is er r or is independent
of t he TMP12 t emper at ur e er r or s, which ar e t2C.
As not ed above, bot h compar at or s of t he device need not always be used, and in t his
case t he lower compar at or out put is not used. For a single point 50C cont r oller , t he
35C set point is super fluous. One r esist or can be eliminat ed by making R2 + R3 a
single value of 95.3k and connect ing pin 3 t o GND. Pin 6 should be left as a no-
connect . If a gr eat er hyst er esis is desir ed, t he r esist or values will be pr opor t ionally
lower ed.
It is also impor t ant t o minimize pot ent ial par asit ic t emper at ur e er r or s associat ed
wit h t he TMP12. Alt hough t he open-collect or out put s can sink up t o 20mA, it is
advised t hat cur r ent s be kept low at t his node, t o limit any addit ional t emper at ur e
r ise. The Q1 - Q2 t r ansist or buffer shown in t he figur e r aises t he cur r ent dr ive t o
100mA, allowing a 50/5V coil t o be dr iven. The r elay t ype shown is gener al
pur pose, and many ot her power int er faces ar e possible wit h t he TMP12. If used as
shown, t he r elay cont act s would be used t o t ur n on a fan for air flow when t he act ive
low out put at pin 7 changes, indicat ing t he upper set point t hr eshold.
A basic assumpt ion of t he TMP12s oper at ion is t hat it will mimic anot her device
in t emper at ur e r ise. Ther efor e, a pr act ical wor king syst em must be ar r anged and
t est ed for pr oper air flow channeling, minimal dist ur bances fr om adjacent devices,
et c. Some exper iment at ion should be expect ed befor e a final set up will r esult .
40
a
TMP12 50 SETPOINT CONTROLLER
7.56
Q2
R5
390
0.1 F
100
1
2
3
4 5
6
7
8
HYSTERESIS
GENERATOR
+
-
-
+
VPTAT
R1
R2
R3
VREF
TEMPERATURE
SENSOR AND
VOLTAGE
REFERENCE
TMP12
+5V
R4
10k
Q1
D1
IN4002
TO FAN OR
COOLING DEVICE
SPDT RELAY
5V COIL, 50 MIN
OMRON G2R-14-DC5
Q1, Q2 = 2N2222
FOR T
HYS
= 2C, I
REF
= 17 A
SETPOINT (HI) = 50C
SETPOINT (LO) = 35C (IF USED)
R1 = 52.3k
R2 = 4.42k
R3 = 90.9k
OR 95.3k
NC
I
REF

=
V
REF
R1 + R2 + R3
41
REF ERENCES: THERMAL MANAGEMENT

1. Power Consideration Discussions, AD815 Da t a Sh eet , Analog Devices.
2. Heat S inks for Multiwatt Packages, AAVI D En gi n eer i n g, I n c., One Kool
Pat h, Laconia, NH, 03246, (603) 528-3400.
3. General Catalog, AAVI D En gi n eer i n g, I n c., One Kool Pat h, Laconia, NH,
03246, (603) 528-3400.
42
EMI /RF I CONSI DERATI ONS
Ad ol f o A. Ga r ci a
Elect r omagnet ic int er fer ence (EMI) has become a hot t opic in t he last few year s
among cir cuit designer s and syst ems engineer s. Alt hough t he subject mat t er and
pr ior ar t have been in exist ence for over t he last 50 year s or so, t he advent of
por t able and high-fr equency indust r ial and consumer elect r onics has pr ovided a
comfor t able st andar d of living for many EMI t est ing engineer s, consult ant s, and
publisher s. Wit h t he help of EDN Magazine and Kimmel Ger ke Associat es, t his
sect ion will highlight gener al issues of EMC (elect r omagnet ic compat ibilit y) t o
familiar ize t he syst em/cir cuit designer wit h t his subject and t o illust r at e pr oven
t echniques for pr ot ect ion against EMI.
A P RI MER ON EMI REGULATI ONS
The int ent of t his sect ion is t o summar ize t he differ ent t ypes of elect r omagnet ic
compat ibilit y (EMC) r egulat ions imposed on equipment manufact ur er s, bot h
volunt ar y and mandat or y. Published EMC r egulat ions apply at t his t ime only t o
equipment and syst ems, and not t o component s. Thus, EMI hardened equipment
does not necessar ily imply t hat each of t he component s used (int egr at ed cir cuit s,
especially) in t he equipment must also be EMI hardened.
Commer ci a l Equ i p men t
The t wo dr iving for ces behind commer cial EMI r egulat ions ar e t he FCC (Feder al
Communicat ions Commission) in t he U. S. and t he VDE (Ver band Deut scher
Elect r ot echniker ) in Ger many. VDE r egulat ions ar e mor e r est r ict ive t han t he FCCs
wit h r egar d t o emissions and r adiat ion, but t he Eur opean Communit y will be
adding immunit y t o RF, elect r ost at ic dischar ge, and power -line dist ur bances t o t he
VDE r egulat ions, and now r equir es mandat or y compliance. In J apan, commer cial
EMC r egulat ions ar e cover ed under t he VCCI (Volunt ar y Cont r ol Council for
Int er fer ence) st andar ds and, implied by t he name, ar e much looser t han t heir FCC
and VDE count er par t s.
All commer cial EMI r egulat ions pr imar ily focus on radiated emissions, specifically t o
pr ot ect near by r adio and t elevision r eceiver s, alt hough bot h FCC and VDE
st andar ds ar e less st r ingent wit h r espect t o conducted int er fer ence (by a fact or of 10
over r adiat ed levels). The FCC Par t 15 and VDE 0871 r egulat ions gr oup commer cial
equipment int o t wo classes: Class A, for all pr oduct s int ended for business
envir onment s; and Class B, for all pr oduct s used in r esident ial applicat ions. For
example, Table 7.1 illust r at es t he elect r ic-field emission limit s of commer cial
comput er equipment for bot h FCC Par t 15 and VDE 0871 compliance.
Radiated Emission Limits for Commercial Computer Equipment
F r equ en cy (MHz) Cla ss A Cla ss B
43
( a t 3 m) (a t 3 m)
30 - 88 300 V/m 100 V/m
88 - 216 500 V/m 150 V/m
216 - 1000 700 V/m 200 V/m
Repr int ed fr om EDN Magazine (J anuar y 20, 1994), CAHNERS PUBLISHING
COMPANY 1995, A Division of Reed Publishing USA.
Table 7.1
In addit ion t o t he alr eady st r ingent VDE emission limit s, t he Eur opean Communit y
EMC st andar ds (IEC and IEEE) now r equir es mandat or y compliance t o t hese
addit ional EMI t hr eat s: Immunit y t o RF fields, elect r ost at ic dischar ge, and power -
line dist ur bances. All equipment /syst ems mar ket ed in Eur ope must exhibit an
immunit y t o RF field st r engt hs of 1-10V/m (IEC st andar d 801-3), elect r ost at ic
dischar ge (gener at ed by human cont act or t hr ough mat er ial movement ) in t he r ange
of 10-15kV (IEC st andar d 801-2), and power -line dist ur bances of 4kV EFTs
(ext r emely fast t r ansient s, IEC st andar d 801-4) and 6kV light ning sur ges (IEEE
st andar d C62.41).
Mi li t a r y Equ i p men t
The defining EMC specificat ion for milit ar y equipment is MIL-STD-461 which
applies t o r adiat ed equipment emissions and equipment suscept ibilit y t o
int er fer ence. Radiat ed emission limit s ar e ver y t ypically 10 t o 100 t imes mor e
st r ingent t han t he levels shown in Table 7.1. Requir ed limit s on immunit y t o RF
fields ar e t ypically 200 t imes mor e st r ingent (RF field st r engt hs of 5-50mV/m) t han
t he limit s for commer cial equipment .
Med i ca l Equ i p men t
Alt hough not yet mandat or y, EMC r egulat ions for medical equipment ar e pr esent ly
being defined by t he FDA (Food and Dr ug Administ r at ion) in t he USA and t he
Eur opean Communit y. The pr imar y focus of t hese EMC r egulat ions will be on
immunit y t o RF fields, elect r ost at ic dischar ge, and power -line dist ur bances, and
may ver y well be mor e st r ingent t han t he limit s spelled out in MIL-STD-461. The
pr imar y object ive of t he medical EMC r egulat ions is t o guar ant ee safet y t o humans.
I n d u st r i a l- a n d P r ocess-Con t r ol Equ i p men t
Pr esent ly, equipment designed and mar ket ed for indust r ial- and pr ocess-cont r ol
applicat ions ar e not r equir ed t o meet pr e-exist ing mandat or y EMC r egulat ions. In
fact , manufact ur er s ar e exempt fr om complying t o any st andar d in t he USA.
However , since indust r ial envir onment s ar e ver y much elect r ically hostile, all
equipment manufact ur er s will be r equir ed t o comply wit h all Eur opean Communit y
EMC r egulat ions in 1996.
Au t omot i ve Equ i p men t
Per haps t he most difficult and host ile envir onment in which elect r ical cir cuit s and
syst ems must oper at e is t hat found in t he aut omobile. All of t he key EMI t hr eat s t o
44
elect r ical syst ems exist her e. In addit ion, oper at ing t emper at ur e ext r emes, moist ur e,
dir t , and t oxic chemicals fur t her exacer bat e t he pr oblem. To complicat e mat t er s
fur t her , st andar d t echniques (fer r it e beads, feed-t hr ough capacit or s, induct or s,
r esist or s, shielded cables, wir es, and connect or s) used in ot her syst ems ar e not
gener ally used in aut omot ive applicat ions because of t he cost of t he addit ional
component s.
Pr esent ly, aut omot ive EMC r egulat ions, defined by t he ver y compr ehensive SAE
St andar ds J 551 and J 1113, ar e not yet mandat or y. They ar e, however , ver y
r igor ous. SAE st andar d J 551 applies t o vehicle-level EMC specificat ions, and
st andar d J 1113 (funct ionally similar t o MIL-STD-461) applies t o all aut omot ive
elect r onic modules. For example, t he J 1113 specificat ion r equir es t hat elect r onic
modules cannot r adiat e elect r ic fields gr eat er t han 300nV/m at a dist ance of 3
met er s. This is r oughly 1000 t imes mor e st r ingent t han t he FCC Par t 15 Class A
specificat ion. In many applicat ions, aut omot ive manufact ur er s ar e imposing J 1113
RF field immunit y limit s on each of the active components used in t hese modules.
Thus, in t he ver y near fut ur e, aut omot ive manufact ur er s will r equir e t hat IC
pr oduct s comply wit h exist ing EMC st andar ds and r egulat ions.
EMC Regu la t i on s I mp a ct on Desi gn
In all t hese applicat ions and many mor e, complying wit h mandat or y EMC
r egulat ions will r equir e car eful design of individual cir cuit s, modules, and syst ems
using est ablished t echniques for cable shielding, signal and power -line filt er ing
against bot h small- and lar ge-scale dist ur bances, and sound mult i-layer PCB
layout s. The key t o success is t o incor por at e sound EMC pr inciples ear ly in t he
design phase t o avoid t ime-consuming and expensive r edesign effor t s.
A DI AGNOSTI C FRAMEWORK FOR EMI /RF I P ROBLEM
SOLVI NG
Wit h any pr oblem, a st r at egy should be developed befor e any effor t is expended
t r ying t o solve it . This appr oach is similar t o t he scient ific met hod: init ial cir cuit
misbehavior is not ed, t heor ies ar e post ulat ed, exper iment s designed t o t est t he
t heor ies ar e conduct ed, and r esult s ar e again not ed. This pr ocess cont inues unt il all
t heor ies have been t est ed and expect ed r esult s achieved and r ecor ded. Wit h r espect
t o EMI, a pr oblem solving fr amewor k has been developed. As shown in Figur e 7.57,
t he model suggest ed by Kimmel-Ger ke in [Refer ence 1] illust r at es t hat all t hr ee
element s (a source, a receptor or victim, and a path bet ween t he t wo) must exist in
or der t o be consider ed an EMI pr oblem. The sour ces of elect r omagnet ic int er fer ence
can t ake on many for ms, and t he ever -incr easing number of por t able
inst r ument at ion and per sonal communicat ions/comput at ion equipment only adds
t he number of possible sour ces and r ecept or s.
A DIAGNOSTIC FRAMEWORK FOR EMI
Reprinted from EDN Magazine (January 20,1994), CAHNERS PUBLISHING COMPANY
1995, A Division of Reed Publishing USA
ANY INTERFERENCE PROBLEM CAN BE BROKEN DOWN INTO:
n n The SOURCE of interference
45
n n The RECEPTOR of interference
n n The PATH coupling the source to the receptor
SOURCES PATHS RECEPTORS
Microcontroller
u u Analog
u u Digital
ESD
Communications
Transmitters
Power Disturbances
Lightning
Radiated
u u EM Fields
u u Crosstalk
Capacitive
Inductive
Conducted
u u Signal
u u Power
u u Ground
Microcontroller
u u Analog
u u Digital
Communications
u u Receivers
Other Electronic
Systems
a 7.57
Int er fer ing signals r each t he r ecept or by conduction (t he cir cuit or syst em
int er connect ions) or radiation (par asit ic mut ual induct ance and/or par asit ic
capacit ance). In gener al, if t he fr equencies of t he int er fer ence ar e less t han 30MHz,
t he pr imar y means by which int er fer ence is coupled is t hr ough t he interconnects.
Bet ween 30MHz and 300MHz, t he pr imar y coupling mechanism is cable radiation
and connector leakage. At fr equencies gr eat er t han 300MHz, t he pr imar y
mechanism is slot and board radiation. Ther e ar e many cases wher e t he
int er fer ence is br oadband, and t he coupling mechanisms ar e combinat ions of t he
above.
When all t hr ee element s exist t oget her , a fr amewor k for solving any EMI pr oblem
can be dr awn fr om Figur e 7.58. Ther e ar e t hr ee t ypes of int er fer ence wit h which t he
cir cuit or syst em designer must cont end. The fir st t ype of int er fer ence is t hat
gener at ed by and emit t ed fr om an inst r ument ; t his is known as cir cuit /syst em
emission and can be eit her conducted or radiated. An example of t his would be t he
per sonal comput er . Por t able and deskt op comput er s must pass t he st r ingent FCC
Par t 15 specificat ions pr ior t o gener al use.
46
THREE TYPES OF INTERFERENCE
EMISSIONS - IMMUNITY - INTERNAL
7.58
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
RADIO
TRANSMITTER
HANDHELD
TRANSMITTER
RADIATED
EMISSIONS
CONDUCTED
EMISSIONS
LIGHTNING
HUMAN ESD
POWER
DISTURBANCE
INTERNAL
ELECTRONICS
The second t ype of int er fer ence is cir cuit or syst em immunity. This descr ibes t he
behavior of an inst r ument when it is exposed t o lar ge elect r omagnet ic fields,
pr imar ily elect r ic fields wit h an int ensit y in t he r ange of 1 t o 10V/m at a dist ance of
3 met er s. Anot her t er m for immunit y is susceptibility, and it descr ibes cir cuit /syst em
behavior against r adiat ed or conduct ed int er fer ence.
The t hir d t ype of int er fer ence is internal. Alt hough not dir ect ly shown on t he figur e,
int er nal int er fer ence can be high-speed digit al cir cuit r y wit hin t he equipment which
affect s sensit ive analog (or ot her digit al cir cuit r y), or noisy power supplies which can
cont aminat e bot h analog and digit al cir cuit s. Int er nal int er fer ence oft en occur s
bet ween digit al and analog cir cuit s, or bet ween mot or s or r elays and digit al cir cuit s.
In mixed signal envir onment s, t he digit al por t ion of t he syst em oft en int er fer es wit h
analog cir cuit r y. In some syst ems, t he int er nal int er fer ence r eaches such high levels
t hat even ver y high-speed digit al cir cuit r y can affect ot her low-speed digit al cir cuit r y
as well as analog cir cuit s.
In addit ion t o t he sour ce-pat h-r ecept or model for analyzing EMI-r elat ed pr oblems,
Kimmel Ger ke Associat es have also int r oduced t he FAT-ID concept [Refer ence 1].
FAT-ID is an acr onym t hat descr ibes t he five key element s inher ent in any EMI
pr oblem. These five key par amet er s ar e: frequency, amplitude, time, impedance, and
distance.
The frequency of t he offending signal suggest s it s pat h. For example, t he pat h of low-
fr equency int er fer ence is oft en t he cir cuit conduct or s. As t he int er fer ence fr equency
incr eases, it will t ake t he pat h of least impedance, usually st r ay capacit ance. In t his
case, t he coupling mechanism is r adiat ion.
Time and fr equency in EMI pr oblems ar e int er changeable. In fact , t he physics of
EMI have shows t hat t he t ime r esponse of signals cont ains all t he necessar y
47
infor mat ion t o const r uct t he spect r al r esponse of t he int er fer ence. In digit al syst ems,
bot h t he signal r ise t ime and pulse r epet it ion r at e pr oduce spect r al component s
accor ding t o t he following r elat ionship:
f
EMI
1
t
r ise


Eq. 7.1
For example, a pulse having a 1ns r ise t ime is equivalent t o an EMI fr equency of
over 300MHz. This t ime-fr equency r elat ionship can also be applied t o high-speed
analog cir cuit s, wher e slew r at es in excess of 1000V/s and gain-bandwidt h pr oduct s
gr eat er t han 500MHz ar e not uncommon.
When t his concept is applied t o inst r ument s and syst ems, EMI emissions ar e again
funct ions of signal r ise t ime and pulse r epet it ion r at es. Spect r um analyzer s and high
speed oscilloscopes used wit h volt age and cur r ent pr obes ar e ver y useful t ools in
quant ifying t he effect s of EMI on cir cuit s and syst ems.
Anot her impor t ant par amet er in t he analysis of EMI pr oblems is t he physical
dimensions of cables, wir es, and enclosur es. Cables can behave as eit her passive
ant ennas (r ecept or s) or ver y efficient t r ansmit t er s (sour ces) of int er fer ence. Their
physical lengt h and t heir shield must be car efully examined wher e EMI is a concer n.
As pr eviously ment ioned, t he behavior of simple conduct or s is a funct ion of lengt h,
cr oss-sect ional ar ea, and fr equency. Openings in equipment enclosur es can behave
as slot ant ennas, t her eby allowing EMI ener gy t o affect t he int er nal elect r onics.
P ASSI VE COMP ONENTS: YOUR ARSENAL AGAI NST EMI
Minimizing t he effect s of EMI r equir es t hat t he cir cuit /syst em designer be
complet ely awar e of t he pr imar y ar senal in t he bat t le against int er fer ence: passive
components. To use successfully t hese component s, t he designer must under st and
t heir non-ideal behavior . For example, Figur e 7.59 illust r at es t he real behavior of
t he passive component s used in cir cuit design. At ver y high fr equencies, wir es
become t r ansmission lines, capacit or s become induct or s, induct or s become
capacit or s, and r esist or s behave as r esonant cir cuit s.
48
ALL PASSIVE COMPONENTS EXHIBIT
"NON IDEAL" BEHAVIOR
7.59
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Divi sion of Reed Publishing USA
WIRE
COMPONENT LF BEHAVIOR HF BEHAVIOR
RESPONSE
CAPACITOR
INDUCTOR
RESISTOR
Z
Z
Z
Z
f
f
f
f
A specific case in point is t he fr equency r esponse of a simple wir e compar ed t o t hat
of a gr ound plane. In many cir cuit s, wir es ar e used as eit her power or signal r et ur ns,
and t her e is no gr ound plane. A wir e will behave as a ver y low r esist ance (less t han
0.02/ft for 22-gauge wir e) at low fr equencies, but because of it s par asit ic
induct ance of appr oximat ely 20nH/inch, it becomes induct ive at fr equencies above
13kHz. Fur t her mor e, depending on size and r out ing of t he wir e and t he fr equencies
involved, it ult imat ely becomes a t r ansmission line wit h an uncont r olled impedance.
Fr om our knowledge of RF, unt er minat ed t r ansmission lines become ant ennas wit h
gain. On t he ot her hand, lar ge ar ea gr ound planes ar e much mor e well-behaved, and
maint ain a low impedance over a wide r ange of fr equencies. Wit h a good
under st anding of t he behavior of real component s, a st r at egy can now be developed
t o find solut ions t o most EMI pr oblems.
RADI O FREQUENCY I NTERFERENCE
The wor ld is r ich in r adio t r ansmit t er s: r adio and TV st at ions, mobile r adios,
comput er s, elect r ic mot or s, gar age door opener s, elect r ic jackhammer s, and
count less ot her s. All t his elect r ical act ivit y can affect cir cuit /syst em per for mance
and, in ext r eme cases, may r ender it inoper able. Regar dless of t he locat ion and
magnit ude of t he int er fer ence, cir cuit s/syst ems must have a minimum level of
immunit y t o r adio fr equency int er fer ence (RFI). The next sect ion will cover t wo
gener al means by which RFI can disr upt nor mal inst r ument oper at ion: t he dir ect
effect s of RFI sensit ive analog cir cuit s, and t he effect s of RFI on shielded cables.
Two t er ms ar e t ypically used in descr ibing t he sensit ivit y of an elect r onic syst em t o
RF fields. In communicat ions, r adio engineer s define immunity t o be an
inst r ument s susceptibility to the applied RFI power density at the unit. In mor e
gener al EMI analysis, t he electric-field intensity is used t o descr ibe RFI st imulus.
49
For compar at ive pur poses, Equat ion 7.2 can be used t o conver t elect r ic-field
int ensit y t o power densit y and vice-ver sa:
r
E
V
m
61.4 P
T
mW
cm
2

_
,

_
,

Eq. 7.2
wher e E = Elect r ic Field St r engt h, in volt s per met er , and
P
T
= Tr ansmit t ed power , in milliwat t s per cm
2
.
Fr om t he st andpoint of t he sour ce-pat h-r ecept or model, t he strength of the electric
field, E, sur r ounding t he r ecept or is a funct ion of transmitted power, antenna gain,
and distance fr om t he sour ce of t he dist ur bance. An appr oximat ion for t he elect r ic-
field int ensit y (for bot h near - and far -field sour ces) in t hese t er ms is given by
Equat ion 7.3:
r
E
V
m
5.5
P
T

_
,

_
,

G
A
d
Eq. 7.3
wher e E = Elect r ic field int ensit y, in V/m;
P
T
= Tr ansmit t ed power , in mW/cm
2
;
G
A
= Ant enna gain (numer ical); and
d = dist ance fr om sour ce, in met er s
For example, a 1W hand-held r adio at a dist ance of 1 met er can gener at e an elect r ic-
field of 5.5V/m, wher eas a 10kW r adio t r ansmission st at ion locat ed 1km away
gener at es a field smaller t han 0.6V/m.
Analog cir cuit s ar e gener ally mor e sensit ive t o RF fields t han digit al cir cuit s because
analog cir cuit s, oper at ing at high gains, must be able t o r esolve signals in t he
micr ovolt /millivolt r egion. Digit al cir cuit s, on t he ot her hand, ar e mor e immune t o
RF fields because of t heir lar ger signal swings and noise mar gins. As shown in
Figur e 7.60, RF fields can use induct ive and/or capacit ive coupling pat hs t o gener at e
noise cur r ent s and volt ages which ar e amplified by high-impedance analog
inst r ument at ion. In many cases, out -of-band noise signals ar e det ect ed and r ect ified
by t hese cir cuit s. The r esult of t he RFI r ect ificat ion is usually unexplained offset
volt age shift s in t he cir cuit or in t he syst em.
50
RFI CAN CAUSE RECTIFICATION IN
SENSITIVE ANALOG CIRCUITS
7.60
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Divi sion of Reed Publi shing USA
V
CC
INPUTS PICK UP HIGH FREQUENCY ENERGY ON
SIGNAL LINE, WHICH IS DETECTED BY THE AMPLIFIER
OUTPUT DRIVERS CAN BE JAMMED, TOO: ENERGY
COUPLES BACK TO INPUT VIA V
CC
OR SIGNAL LINE
AND THEN IS DETECTED OR AMPLIFIED
Ther e ar e t echniques t hat can be used t o pr ot ect analog cir cuit s against int er fer ence
fr om RF fields (see Figur e 7.61). The t hr ee gener al point s of RFI coupling ar e signal
inputs, signal outputs, and power supplies. At a minimum, all power supply pin
connect ions on analog and digit al ICs should be decoupled wit h 0.1F cer amic
capacit or s. As was shown in Refer ence 3, low-pass filt er s, whose cut off fr equencies
ar e set no higher t han 10 t o 100 t imes t he signal bandwidt h, can be used at t he
input s and t he out put s of signal condit ioning cir cuit r y t o filt er noise.
51
V
POS
KEEPING RFI AWAY FROM ANALOG CIRCUITS
7.61
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
Decouple all voltage supplies to analog chip with high-frequency capacitors
Use high-frequency filters on all lines that leave the board
Use high-frequency filters on the voltage reference if it is not grounded
LOCAL
REMOTE
V
NEG
Car e must be t aken t o ensur e t hat t he low pass filt er s (LPFs) ar e effect ive at t he
highest RF int er fer ence fr equency expect ed. As illust r at ed in Figur e 7.62, r eal low-
pass filt er s may exhibit leakage at high fr equencies. Their induct or s can lose t heir
effect iveness due t o par asit ic capacit ance, and capacit or s can lose t heir effect iveness
due t o par asit ic induct ance. A r ule of t humb is t hat a convent ional low-pass filt er
(made up of a single capacit or and induct or ) can begin t o leak when t he applied
signal fr equency is 100 t o 1000 higher t han t he filt er s cut off fr equency. For
example, a 10kHz LPF would not be consider ed ver y efficient at filt er ing fr equencies
above 1MHz.
52
A SINGLE LOW PASS FILTER LOSES EFFECTIVENESS
AT 100 - 1000 f
3dB
7.62
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
TYPICALLY 100 - 1000 f
3dB
f
3dB
FREQUENCY
FILTER
ATTENUATION
Rat her t han use one LPF st age, it is r ecommended t hat t he int er fer ence fr equency
bands be separ at ed int o low-band, mid-band, and high-band, and t hen use
individual filt er s for each band. Kimmel Ger ke Associat es use t he st er eo speaker
analogy of woofer-midrange-tweeter for RFI low-pass filt er design illust r at ed in
Figur e 7.63. In t his appr oach, low fr equencies ar e gr ouped fr om 10kHz t o 1MHz,
mid-band fr equencies ar e gr ouped fr om 1MHz t o 100MHz, and high fr equencies
gr ouped fr om 100MHz t o 1GHz. In t he case of a shielded cable input /out put , t he
high fr equency sect ion should be locat ed close t o t he shield t o pr event high-
fr equency leakage at t he shield boundar y. This is commonly r efer r ed t o as feed-
through pr ot ect ion. For applicat ions wher e shields ar e not r equir ed at t he
input s/out put s, t hen t he pr efer r ed met hod is t o locat e t he high fr equency filt er
sect ion as close t he analog cir cuit as possible. This is t o pr event t he possibilit y of
pickup fr om ot her par t s of t he cir cuit .
53
MULTISTAGE FILTERS ARE MORE EFFECTIVE
7.63
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
FERRITE
BEAD
IRON
CORE
WOOFER
MIDRANGE
.01 F
.01 F
TWEETER
STEREO SPEAKER ANALOGY
FEEDTHROUGH
CAPACITOR
1 F
Anot her cause of filt er failur e is illust r at ed in Figur e 7.64. If t her e is any impedance
in t he gr ound connect ion (for example, a long wir e or nar r ow t r ace connect ed t o t he
gr ound plane), t hen t he high-fr equency noise uses t his impedance pat h t o bypass t he
filt er complet ely. Filt er gr ounds must be br oadband and t ied t o low-impedance
point s or planes for opt imum per for mance. High fr equency capacit or leads should be
kept as shor t as possible, and low-induct ance sur face-mount ed cer amic chip
capacit or s ar e pr efer able.
54
NON-ZERO (INDUCTIVE AND/OR RESISTIVE) FILTER
GROUND REDUCES EFFECTIVENESS
7.64
a
Reprint ed f rom EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publ ishing USA
HF
ENERGY
FILTER
BOND IMPEDANCE
HF
ENERGY
SOLUTI ONS FOR P OWER-LI NE DI STURBANCES
The goal of t his next sect ion is not t o descr ibe in det ail all t he cir cuit /syst em failur e
mechanisms which can r esult fr om power -line dist ur bances or fault s. Nor is it t he
int ent of t his sect ion t o descr ibe met hods by which power -line dist ur bances can be
pr event ed. Inst ead, t his sect ion will descr ibe t echniques t hat allow cir cuit s and
syst ems t o accommodat e transient power -line dist ur bances.
Figur e 7.65 is an example of a hybr id power t r ansient pr ot ect ion net wor k commonly
used in many applicat ions wher e light ning t r ansient s or ot her power -line
dist ur bances ar e pr evalent . These net wor ks can be designed t o pr ovide pr ot ect ion
against t r ansient s as high as 10kV and as fast as 10ns. Gas dischar ge t ubes
(cr owbar s) and lar ge geomet r y zener diodes (clamps) ar e used t o pr ovide bot h
differ ent ial and common-mode pr ot ect ion. Met al-oxide var ist or s (MOVs) can be
subst it ut ed for t he zener diodes in less cr it ical, or in mor e compact designs. Chokes
ar e used t o limit t he sur ge cur r ent unt il t he gas dischar ge t ubes fir e.
55
POWER LINE DISTURBANCES CAN GENERATE EMI
7.65
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
COMMON-MODE AND DIFFERENTIAL MODE PROTECTION
GAS DISCHARGE
TUBES
"CROWBARS"
CHOKES
TRANSIENT
SUPPRESSORS
BIG ZENERS
OR MOVs
V
N
G
LINE
LOAD
Commer cial EMI filt er s, as illust r at ed in Figur e 7.66, can be used t o filt er less
cat ast r ophic t r ansient s or high-fr equency int er fer ence. These EMI filt er s pr ovide
bot h common-mode and differ ent ial mode filt er ing as in Figur e 7.66. An opt ional
choke in t he safet y gr ound can pr ovide addit ional pr ot ect ion against common-mode
noise. The value of t his choke cannot be t oo lar ge, however , because it s r esist ance
may affect power -line fault clear ing. These filt er s wor k in bot h dir ect ions: t hey ar e
not only pr ot ect t he equipment fr om sur ges on t he power line but also pr event
t r ansient s fr om t he int er nal swit ching power supplies fr om cor r upt ing t he power
line.
56
SCHEMATIC FOR A COMMERCIAL POWER LINE FILTER
7.66
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
NOTE: OPTIONAL CHOKE ADDED FOR COMMON-MODE PROTECTION
HOT
NEU
GND
LINE
OPTIONAL
HOT
NEU
LOAD
Tr ansfor mer s pr ovide t he best common-mode power line isolat ion. They pr ovide good
pr ot ect ion at low fr equencies (<1MHz), or for t r ansient s wit h r ise and fall t imes
gr eat er t han 300ns. Most mot or noise and light ning t r ansient s ar e in t his r ange, so
isolat ion t r ansfor mer s wor k well for t hese t ypes of dist ur bances. Alt hough t he
isolat ion bet ween input and out put is galvanic, isolat ion t r ansfor mer s do not pr ovide
sufficient pr ot ect ion against ext r emely fast t r ansient s (<10ns) or t hose caused by
high-amplit ude elect r ost at ic dischar ge (1 t o 3ns). As illust r at ed in Figur e 7.67,
isolat ion t r ansfor mer s can be designed for var ious levels of differ ent ial- or common-
mode pr ot ect ion. For differ ent ial-mode noise r eject ion, t he Far aday shield is
connect ed t o t he neut r al, and for common-mode noise r eject ion, t he shield is
connect ed t o t he safet y gr ound.
57
FARADAY SHIELDS IN ISOLATION TRANSFORMERS
PROVIDE INCREASING LEVELS OF PROTECTION
7.67
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
SINGLE FARADAY SHIELD
STANDARD TRANSFORMER - NO SHIELD
SINGLE FARADAY SHIELD
TRIPLE FARADAY SHIELD
NOTE CONNECTION FROM SECONDARY
TO SAFETY GROUND TO ELIMINATE
GROUND-TO-NEUTRAL VOLTAGE
CONNECT TO SAFETY GROUND FOR
COMMON-MODE PROTECTION
CONNECT TO NOISY-SIDE NEUTRAL
WIRE FOR DIFFERENTIAL-MODE
PROTECTION
CONNECT TO SAFETY GROUND FOR
COMMON MODE
CONNECT TO NEUTRALS FOR
DIFFERENTIAL MODE
P RI NTED CI RCUI T BOARD DESI GN FOR EMI
P ROTECTI ON
This sect ion will summar ize gener al point s r egar ding t he most cr it ical por t ion of t he
design phase: t he pr int ed cir cuit boar d layout . It is at t his st age wher e t he
per for mance of t he syst em is most oft en compr omised. This is not only t r ue for
signal-pat h per for mance, but also for t he syst ems suscept ibilit y t o elect r omagnet ic
int er fer ence and t he amount of elect r omagnet ic ener gy r adiat ed by t he syst em.
Failur e t o implement sound PCB layout t echniques will ver y likely lead t o
syst em/inst r ument EMC failur es.
Figur e 7.68 is a r eal-wor ld pr int ed cir cuit boar d layout which shows all t he pat hs
t hr ough which high-fr equency noise can couple/r adiat e int o/out of t he cir cuit .
Alt hough t he diagr am shows digit al cir cuit r y, t he same point s ar e applicable t o
pr ecision analog, high-speed analog, or mixed analog/digit al cir cuit s. Ident ifying
cr it ical cir cuit s and pat hs helps in designing t he PCB layout for bot h low emissions
and suscept ibilit y t o r adiat ed and conduct ed ext er nal and int er nal noise sour ces.
58
METHODS BY WHICH HIGH FREQUENCY ENERGY
COUPLES AND RADIATES INTO CIRCUITRY VIA PLACEMENT
7.68
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
COUPLING TO I/O VIA
CROSSTALK OR RADIATION
COUPLING VIA COMMON
POWER IMPEDANCE
COUPLING VIA COMMON
GROUND IMPEDANCE
RADIATION FROM
POWER WIRING
RADIATION
FROM I/O
WIRING
A key point in minimizing noise pr oblems in a design is t o choose devices no faster
than actually required by the application. Many designer s assume t hat fast er is
bet t er : fast logic is bet t er t han slow, high bandwidt h amplifier s ar e clear ly bet t er
t han low bandwidt h ones, and fast DACs and ADCs ar e bet t er , even if t he speed is
not r equir ed by t he syst em. Unfor t unat ely, fast er is not bet t er , but wor se wher e
EMI is concer ned.
Many fast DACs and ADCs have digit al input s and out put s wit h r ise and fall t imes
in t he nanosecond r egion. Because of t heir wide bandwidt h, t he sampling clock and
t he digit al input s and can r espond t o any for m of high fr equency noise, even glit ches
as nar r ow as 1 t o 3ns. These high speed dat a conver t er s and amplifier s ar e easy
pr ey for t he high fr equency noise of micr opr ocessor s, digit al signal pr ocessor s,
mot or s, swit ching r egulat or s, hand-held r adios, elect r ic jackhammer s, et c. Wit h
some of t hese high-speed devices, a small amount of input /out put filt er ing may be
r equir ed t o desensit ize t he cir cuit fr om it s EMI/RFI envir onment . Adding a small
fer r it e bead just befor e t he decoupling capacit or as shown in Figur e 7.69 is ver y
effect ive in filt er ing high fr equency noise on t he supply lines. For t hose cir cuit s t hat
r equir e bipolar supplies, t his t echnique should be applied t o bot h posit ive and
negat ive supply lines.
To help r educe t he emissions gener at ed by ext r emely fast moving digit al signals at
DAC input s or ADC out put s, a small r esist or or fer r it e bead may be r equir ed at each
digit al input /out put .
59
POWER SUPPLY FILTERING AND SIGNAL LINE
SNUBBING GREATLY REDUCES EMI EMISSIONS
7.69
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
FERRITE
BEAD
GND
V
CC
MICROPROCESSOR
OR OTHER HIGH-SPEED
CLOCKED CIRCUIT
FERRITE BEAD OR
10 - 33 RESISTOR
Once t he syst ems cr it ical pat hs and cir cuit s have been ident ified, t he next st ep in
implement ing sound PCB layout is t o par t it ion t he pr int ed cir cuit boar d accor ding t o
cir cuit funct ion. This involves t he appr opr iat e use of power , gr ound, and signal
planes. Good PCB layout s also isolat e cr it ical analog pat hs fr om sour ces of high
int er fer ence (I/O lines and connect or s, for example). High fr equency cir cuit s (analog
and digit al) should be separ at ed fr om low fr equency ones. Fur t her mor e, aut omat ic
signal r out ing CAD layout soft war e should be used wit h ext r eme caut ion, and
cr it ical pat hs r out ed by hand.
Pr oper ly designed mult ilayer pr int ed cir cuit boar ds can r educe EMI emissions and
incr ease immunit y t o RF fields by a fact or of 10 or mor e compar ed t o double-sided
boar ds. A mult ilayer boar d allows a complet e layer t o be used for t he gr ound plane,
wher eas t he gr ound plane side of a double-sided boar d is oft en disr upt ed wit h signal
cr ossover s, et c. If t he syst em has separ at e analog and digit al gr ound and power
planes, t he analog gr ound plane should be under neat h t he analog power plane, and
similar ly, t he digit al gr ound plane should be under neat h t he digit al power plane.
Ther e should be no over lap bet ween analog and digit al gr ound planes nor analog
and digit al power planes.
The pr efer r ed mult i-layer boar d ar r angement is t o embed t he signal t r aces bet ween
t he power and gr ound planes, as shown in Figur e 7.70. These low-impedance planes
for m ver y high-fr equency stripline t r ansmission lines wit h t he signal t r aces. The
r et ur n cur r ent pat h for a high fr equency signal on a t r ace is locat ed dir ect ly above
and below t he t r ace on t he gr ound/power planes. The high fr equency signal is t hus
cont ained inside t he PCB, t her eby minimizing emissions. The embedded signal t r ace
appr oach has an obvious disadvant age: debugging cir cuit t r aces t hat ar e hidden
fr om plain view is difficult .
60
"TO EMBED OR NOT TO EMBED"
THAT IS THE QUESTION
7.70
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
BEFORE AFTER
Route
Power
Ground
Route
Power
Route
Route
Ground
Advantages of Embedding
Disadvantages of Embedding
Lower impedances, therefore lower emissions and crosstalk
Reduction in emissions and crosstalk is significant above 50MHz
Traces are protected
Lower interboard capacitance, harder to decouple
Impedances may be too low for matching
Hard to prototype and troubleshoot buried traces
Much has been wr it t en about t er minat ing pr int ed cir cuit boar d t r aces in t heir
char act er ist ic impedance t o avoid r eflect ions. A good r ule-of-t humb t o det er mine
when t his is necessar y is as follows: Terminate the line in its characteristic
impedance when the one-way propagation delay of the PCB track is equal to or
greater than one-half the applied signal rise/ fall time (whichever edge is faster). A
conser vat ive appr oach is t o use a 2 inch (PCB t r ack lengt h)/nanosecond (r ise-, fall-
t ime) cr it er ion. For example, PCB t r acks for high-speed logic wit h r ise/fall t ime of
5ns should be t er minat ed in t heir char act er ist ic impedance and if t he t r ack lengt h is
equal t o or gr eat er t han 10 inches (including any meander s). The 2 inch/nanosecond
t r ack lengt h cr it er ion is summar ized in Figur e 7.71 for a number of logic families.
LINE TERMINATION SHOULD BE USED WHEN
LENGTH OF PCB TRACK EXCEEDS 2 inches / ns
Reprinted from EDN Magazine (January 20,1994), CAHNERS PUBLISHING
COMPANY 1995, A Division of Reed Publishing USA
DIGITAL IC
FAMILY
t
r
, t
f
(ns)
PCB TRACK LENGTH
(inches)
PCB TRACK LENGTH
(cm)
GaAs 0.1 0.2 0.5
ECL 0.75 1.5 3.8
Schottky 3 6 15
FAST 3 6 15
AS 3 6 15
AC 4 8 20
ALS 6 12 30
LS 8 16 40
TTL 10 20 50
61
HC 18 36 90
t
r
= rise time of signal in ns
t
f
= fall time of signal in ns
n n For analog signals @ f
max
, calculate t
r
= t
f
= 0.35 / f
max
a 7.71
This same 2 inch/nanosecond r ule of t humb should be used wit h analog cir cuit s in
det er mining t he need for t r ansmission line t echniques. For inst ance, if an amplifier
must out put a maximum fr equency of f
max
, t hen t he equivalent r iset ime, t
r
, can be
calculat ed using t he equat ion t
r
= 0.35/f
max
. The maximum PCB t r ack lengt h is
t hen calculat ed by mult iplying t he r iset ime by 2 inch/nanosecond. For example, a
maximum out put fr equency of 100MHz cor r esponds t o a r iset ime of 3.5ns, and a
t r ack car r ying t his signal gr eat er t han 7 inches should be t r eat ed as a t r ansmission
line.
Equat ion 7.4 can be used t o det er mine t he char act er ist ic impedance of a PCB t r ack
separ at ed fr om a power /gr ound plane by t he boar ds dielect r ic (micr ost r ip
t r ansmission line):
( ) Z
o
r
+ 1.41
5.98d
0.89w + t

1
]
1
87

ln Eq. 7.4
wher e
r
= dielect r ic const ant of pr int ed cir cuit boar d mat er ial;
d = t hickness of t he boar d bet ween met al layer s, in mils;
w = widt h of met al t r ace, in mils; and
t = t hickness of met al t r ace, in mils.
The one-way t r ansit t ime for a single met al t r ace over a power /gr ound plane can be
det er mined fr om Eq. 7.5:
( ) t
pd
ns / ft 1.017 0.475
r
0.67 + Eq. 7.5
For example, a st andar d 4-layer PCB boar d might use 8-mil wide, 1 ounce (1.4 mils)
copper t r aces separ at ed by 0.021" FR-4 (
r
=4.7) dielect r ic mat er ial. The
char act er ist ic impedance and one-way t r ansit t ime of such a signal t r ace would be
88 and 1.7ns/ft (7"/ns), r espect ively. Tr ansmission lines can be effect ively
t er minat ed in sever al ways depending on t he applicat ion, as descr ibed in Sect ion 2
of t his book.
62
REFERENCES ON EMI /RFI
1. EDNs Designers Guide to Electromagnetic Compatibility, EDN,
J anuar y, 20, 1994, mat er ial r epr int ed by per mission of Cahner s Publishing
Company, 1995.
2. Designing for EMC (Workshop Notes), Kimmel Ger ke Associat es, Lt d., 1994.
3. Syst ems Ap p li ca t i on Gu i d e, Chapt er 1, pg. 21-55, Analog Devices,
Incor por at ed, Nor wood, MA, 1994.
4. Henr y Ot t , Noi se Red u ct i on Tech n i qu es I n Elect r on i c Syst ems,
Se con d Ed i t i on , New Yor k, J ohn Wiley & Sons, 1988.
5. Ralph Mor r ison, Gr ou n d i n g An d Sh i eld i n g Tech n i q u es I n
I n st r u men t a t i on , Th i r d Ed i t i on , New Yor k, J ohn Wiley & Sons, 1986.
6. Amp li fi er Ap p li ca t i on s Gu i d e, Chapt er XI, pg. 61, Analog Devices,
Incor por at ed, Nor wood, MA, 1992.
7. B.Slat t er y and J .Wynne, Design and Layout of a Video Graphics
S ystem for Reduced EMI, An a log Devi ces Ap p li ca t i on Not e AN-333.
8. Paul Br okaw, An IC Amplifier User Guide To Decoupling, Grounding,
And Making Things Go Right For A Change, An a log Devi ces
Ap p li ca t i on Not e, Or der Number E1393-5-590.
9. A. Rich, Understanding Interference-Type Noise, An a log Di a logu e, 16-3,
1982, pp. 16-19.
10. A. Rich, S hielding and Guarding, An a log Di a logu e, 17-1, 1983, pp. 8-13.
11. EMC Test & Desi gn , Car diff Publishing Company, Englewood, CO.
An excellent , gener al pur pose t r ade jour nal on issues of EMI and EMC.
63
SHI ELDI NG CONCEP TS
Ad ol f o Ga r ci a , J oh n McDon a l d
The concept s of shielding effect iveness pr esent ed next ar e backgr ound mat er ial.
Int er est ed r eader s should consult Refer ences 1,2, and 6 cit ed at t he end of t he
sect ion for mor e det ailed infor mat ion.
Applying t he concept s of shielding r equir es an under st anding of t he sour ce of t he
int er fer ence, t he envir onment sur r ounding t he sour ce, and t he dist ance bet ween t he
sour ce and point of obser vat ion (t he r ecept or or vict im). If t he cir cuit is oper at ing
close t o t he sour ce (in t he near -, or induct ion-field), t hen t he field char act er ist ics ar e
det er mined by t he sour ce. If t he cir cuit is r emot ely locat ed (in t he far -, or r adiat ion-
field), t hen t he field char act er ist ics ar e det er mined by t he t r ansmission medium.
A cir cuit oper at es in a near -field if it s dist ance fr om t he sour ce of t he int er fer ence is
less t han t he wavelengt h () of t he int er fer ence divided by 2, or /2. If t he dist ance
bet ween t he cir cuit and t he sour ce of t he int er fer ence is lar ger t han t his quant it y,
t hen t he cir cuit oper at es in t he far field. For inst ance, t he int er fer ence caused by a
1ns pulse edge has an upper bandwidt h of appr oximat ely 350MHz. The wavelengt h
of a 350MHz signal is appr oximat ely 32 inches (t he speed of light is appr oximat ely
12"/ns). Dividing t he wavelengt h by 2 yields a dist ance of appr oximat ely 5 inches,
t he boundar y bet ween near - and far -field. If a cir cuit is wit hin 5 inches of a 350MHz
int er fer ence sour ce, t hen t he cir cuit oper at es in t he near -field of t he int er fer ence. If
t he dist ance is gr eat er t han 5 inches, t he cir cuit oper at es in t he far -field of t he
int er fer ence.
Regar dless of t he t ype of int er fer ence, t her e is a char act er ist ic impedance associat ed
wit h it . The char act er ist ic, or wave impedance of a field is det er mined by t he r at io of
it s elect r ic (or E-) field t o it s magnet ic (or H-) field. In t he far field, t he r at io of t he
elect r ic field t o t he magnet ic field is t he char act er ist ic (wave impedance) of fr ee
space, given by Z
o
= 377. In t he near field, t he wave-impedance is det er mined by
t he nat ur e of t he int er fer ence and it s dist ance fr om t he sour ce. If t he int er fer ence
sour ce is high-cur r ent and low-volt age (for example, a loop ant enna or a power -line
t r ansfor mer ), t he field is pr edominat ely magnet ic and exhibit s a wave impedance
which is less t han 377. If t he sour ce is low-cur r ent and high-volt age (for example, a
r od ant enna or a high-speed digit al swit ching cir cuit ), t hen t he field is
pr edominat ely elect r ic and exhibit s a wave impedance which is gr eat er t han 377.
Conduct ive enclosur es can be used t o shield sensit ive cir cuit s fr om t he effect s of
t hese ext er nal fields. These mat er ials pr esent an impedance mismat ch t o t he
incident int er fer ence because t he impedance of t he shield is lower t han t he wave
impedance of t he incident field. The effect iveness of t he conduct ive shield depends on
t wo t hings: Fir st is t he loss due t o t he reflection of t he incident wave off t he
shielding mat er ial. Second is t he loss due t o t he absorption of t he t r ansmit t ed wave
within t he shielding mat er ial. Bot h concept s ar e illust r at ed in Figur e 7.72. The
amount of r eflect ion loss depends upon t he t ype of int er fer ence and it s wave
impedance. The amount of absor pt ion loss, however , is independent of t he t ype of
int er fer ence. It is t he same for near - and far -field r adiat ion, as well as for elect r ic or
magnet ic fields.
64
REFLECTION AND ABSORPTION ARE THE TWO
PRINCIPAL SHIELDING MECHANISMS
7.72
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vi sion of Reed Publi shing USA
INCIDENT RAY
REFLECTED RAY
ABSORPTIVE
REGION
SHIELD
MATERIAL
TRANSMITTED
RAY
Reflect ion loss at t he int er face bet ween t wo media depends on t he differ ence in t he
char act er ist ic impedances of t he t wo media. For elect r ic fields, r eflect ion loss
depends on t he fr equency of t he int er fer ence and t he shielding mat er ial. This loss
can be expr essed in dB, and is given by:
( ) R
e
dB = 322 + 10log
10
r
r
f
3
r
2

1
]
1
1
Eq. 7.6
wher e
r
= r elat ive conduct ivit y of t he shielding mat er ial, in Siemens per met er ;

r
= r elat ive per meabilit y of t he shielding mat er ial, in Henr ies per met er ;
f = fr equency of t he int er fer ence, and
r = dist ance fr om sour ce of t he int er fer ence, in met er s
For magnet ic fields, t he loss depends also on t he shielding mat er ial and t he
fr equency of t he int er fer ence. Reflect ion loss for magnet ic fields is given by:
( ) R
m
dB = 14.6 + 10log
10
f r
2
r
r

1
]
1
1
Eq. 7.7
and, for plane waves ( r > /2), t he r eflect ion loss is given by:
( ) R
pw
dB = 168 + 10log
10
r
r
f

1
]
1
Eq. 7.8
65
Absorption is t he second loss mechanism in shielding mat er ials. Wave at t enuat ion
due t o absor pt ion is given by:
( ) A dB = 3.34 t
r r
f Eq. 7.9
wher e t = t hickness of t he shield mat er ial, in inches. This expr ession is valid for
plane waves, elect r ic and magnet ic fields. Since t he int ensit y of a t r ansmit t ed field
decr eases exponent ially r elat ive t o t he t hickness of t he shielding mat er ial, t he
absor pt ion loss in a shield one skin-dept h () t hick is 9dB. Since absor pt ion loss is
pr opor t ional t o t hickness and inver sely pr opor t ional t o skin dept h, incr easing t he
t hickness of t he shielding mat er ial impr oves shielding effect iveness at high
fr equencies.
Reflect ion loss for plane waves in t he far field decr eases wit h incr easing fr equency
because t he shield impedance, Z
s
, incr eases wit h fr equency. Absor pt ion loss, on t he
ot her hand, incr eases wit h fr equency because skin dept h decr eases. For elect r ic
fields and plane waves, t he pr imar y shielding mechanism is r eflect ion loss, and at
high fr equencies, t he mechanism is absor pt ion loss. For t hese t ypes of int er fer ence,
high conduct ivit y mat er ials, such as copper or aluminum, pr ovide adequat e
shielding. At low fr equencies, bot h r eflect ion and absor pt ion loss t o magnet ic fields
is low; t hus, it is ver y difficult t o shield cir cuit s fr om low-fr equency magnet ic fields.
In t hese applicat ions, high-per meabilit y mat er ials t hat exhibit low-r eluct ance
pr ovide t he best pr ot ect ion. These low-r eluct ance mat er ials pr ovide a magnet ic
shunt pat h t hat diver t s t he magnet ic field away fr om t he pr ot ect ed cir cuit . Some
char act er ist ics of met allic mat er ials commonly used for shielded enclosur es ar e
shown in Figur e 7.73.
IMPEDANCE AND SKIN DEPTHS
FOR VARIOUS SHIELDING MATERIALS
Material Conductivity

r
Permeability

r
Shield Impedance
|Z
s
|
Skin Depth
(inch)
Cu 1 1
3.68E- 7 f

2.6
f

Al 1 0.61
4.71E- 7 f

3.3
f

Steel 0.1 1,000
3.68E- 5 f

0.26
f

Metal 0.03 20,000
3E- 4 f

0.11
f

where s
o
= 5.82 10
7
S/m

o
= 4p 10
-7
H/m
e
o
= 8.85 10
-12
F/m
66
a 7.73
A pr oper ly shielded enclosur e is ver y effect ive at pr event ing ext er nal int er fer ence
fr om disr upt ing it s cont ent s as well as confining any int er nally-gener at ed
int er fer ence. However , in t he r eal wor ld, openings in t he shield ar e oft en r equir ed t o
accommodat e adjust ment knobs, swit ches, connect or s, or t o pr ovide vent ilat ion (see
Figur e 7.74). Unfor t unat ely, t hese openings may compr omise shielding effect iveness
by pr oviding pat hs for high-fr equency int er fer ence t o ent er t he inst r ument .
ANY OPENING IN AN ENCLOSURE CAN ACT AS
AN EMI WAVEGUIDE BY COMPROMISING
SHIELDING EFFECTIVENESS
7.74
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
SEAMS
SWITCHES
DISPLAY
PANEL
DATA
CABLES
POWER
CABLES
VENTILATORS
The longest dimension (not t he t ot al ar ea) of an opening is used t o evaluat e t he
abilit y of ext er nal fields t o ent er t he enclosur e, because t he openings behave as slot
ant ennas. Equat ion 7.10 can be used t o calculat e t he shielding effect iveness, or t he
suscept ibilit y t o EMI leakage or penet r at ion, of an opening in an enclosur e:
( ) Shielding Effect iveness dB = 20 log
10
2 L

_
,

Eq. 7.10
wher e = wavelengt h of t he int er fer ence and
L = maximum dimension of t he opening
Maximum r adiat ion of EMI t hr ough an opening occur s when t he longest dimension
of t he opening is equal t o one half-wavelengt h of t he int er fer ence fr equency (0dB
shielding effect iveness). A r ule-of-t humb is t o keep t he longest dimension less t han
1/20 wavelengt h of t he int er fer ence signal, as t his pr ovides 20dB shielding
effect iveness. Fur t her mor e, a few small openings on each side of an enclosur e is
67
pr efer r ed over many openings on one side. This is because t he openings on differ ent
sides r adiat e ener gy in differ ent dir ect ions, and as a r esult , shielding effect iveness is
not compr omised. If openings and seams cannot be avoided, t hen conduct ive
gasket s, scr eens, and paint s alone or in combinat ion should be used judiciously t o
limit t he longest dimension of any opening t o less t han 1/20 wavelengt h. Any cables,
wir es, connect or s, indicat or s, or cont r ol shaft s penet r at ing t he enclosur e should have
cir cumfer ent ial met allic shields physically bonded t o t he enclosur e at t he point of
ent r y. In t hose applicat ions wher e unshielded cables/wir es ar e used, t hen filt er s ar e
r ecommended at t he point of shield ent r y.
Sen sor s a n d Ca ble Sh i eld i n g
The impr oper use of cables and t heir shields is a significant cont r ibut or t o bot h
r adiat ed and conduct ed int er fer ence. As illust r at ed in Figur e 7.75, effect ive cable
and enclosur e shielding confines sensit ive cir cuit r y and signals wit hin t he ent ir e
shield wit hout compr omising shielding effect iveness.
LENGTH OF SHIELDED CABLES DETERMINES AN
"ELECTRICALLY LONG" OR "ELECTRICALLY SHORT"
APPLICATION
7.75
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Di vision of Reed Publishing USA
SHIELDED ENCLOSURE A SHIELDED ENCLOSURE B
LENGTH
SHIELDED
CABLE
FULLY SHIELDED ENCLOSURES CONNECTED BY FULLY
SHIELDED CABLE KEEP ALL INTERNAL CIRCUITS AND
SIGNAL LINES INSIDE THE SHIELD.
TRANSITION REGION: 1/20 WAVELENGTH
Depending on t he t ype of int er fer ence (pickup/r adiat ed, low/high fr equency), pr oper
cable shielding is implement ed differ ent ly and is ver y dependent on t he lengt h of t he
cable. The fir st st ep is t o det er mine whet her t he lengt h of t he cable is electrically
short or electrically long at t he fr equency of concer n. A cable is consider ed
electrically short if t he lengt h of t he cable is less t han 1/20 wavelengt h of t he highest
fr equency of t he int er fer ence, ot her wise it is electrically long. For example, at
50/60Hz, an electrically short cable is any cable lengt h less t han 150 miles, wher e
t he pr imar y coupling mechanism for t hese low fr equency elect r ic fields is capacit ive.
As such, for any cable lengt h less t han 150 miles, t he amplit ude of t he int er fer ence
will be t he same over t he ent ir e lengt h of t he cable. To pr ot ect cir cuit s against low-
fr equency elect r ic-field pickup, only one end of t he shield should be r et ur ned t o a
68
low-impedance point . A gener alized example of t his mechanism is illust r at ed in
Figur e 7.76.
CONNECT THE SHIELD AT ONE POINT AT THE LOAD
TO PROTECT AGAINST LOW FREQUENCY (50/60Hz) THREATS
7.76
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
EQUIVALENT
CIRCUITS
RECEIVER
RECEIVER
CABLE SHIELD
GROUNDED AT LOAD
CAPACITIVE COUPLING
TO CABLE
e
n
e
n
e
n
e
n
In t his example, t he shield is gr ounded at t he r eceiver . An except ion t o t his
appr oach (which will be highlight ed again lat er ) is t he case wher e line-level
(>1Vr ms) audio signals ar e t r ansmit t ed over long dist ances using t wist ed pair ,
shielded cables. In t hese applicat ions, t he shield again offer s pr ot ect ion against low-
fr equency int er fer ence, and an accept ed appr oach is t o gr ound t he shield at t he
dr iver end (LF and HF gr ound) and gr ound it at t he r eceiver wit h a capacit or (HF
gr ound only).
In t hose applicat ions wher e t he lengt h of t he cable is electrically long, or pr ot ect ion
against high-fr equency int er fer ence is r equir ed, t hen t he pr efer r ed met hod is t o
connect t he cable shield t o low-impedance point s at bot h ends (dir ect connect ion at
t he dr iving end, and capacit ive connect ion at t he r eceiver ). Ot her wise, unt er minat ed
t r ansmission lines effect s can cause r eflect ions and st anding waves along t he cable.
At fr equencies of 10MHz and above, cir cumfer ent ial (360) shield bonds and met al
connect or s ar e r equir ed t o main low-impedance connect ions t o gr ound.
In summar y, for pr ot ect ion against low-fr equency (<1MHz), elect r ic-field
int er fer ence, gr ounding t he shield at one end is accept able. For high-fr equency
int er fer ence (>1MHz), t he pr efer r ed met hod is gr ounding t he shield at bot h ends,
using 360 cir cumfer ent ial bonds bet ween t he shield and t he connect or , and
maint aining met al-t o-met al cont inuit y bet ween t he connect or s and t he enclosur e.
Low-fr equency gr ound loops can be eliminat ed by r eplacing one of t he DC shield
connect ions t o gr ound wit h a low induct ance 0.01F capacit or . This capacit or
pr event s low fr equency gr ound loops and shunt s high fr equency int er fer ence t o
gr ound.
69
Sh i eld ed Twi st ed P a i r Ca ble Gr ou n d i n g Exa mp les
The envir onment s in which analog syst ems oper at e ar e oft en r ich in sour ces of EMI.
Common EMI noise sour ces include power lines, logic signals, swit ching power
supplies, r adio st at ions, elect r ic light ing, and mot or s. Noise fr om t hese sour ces can
easily couple int o long analog signal pat hs, such as cables, which act as efficient
ant ennas. Shielded cables pr ot ect signal conduct or s fr om elect r ic field (E-field)
int er fer ence by pr oviding low impedance pat hs t o gr ound at t he offending
fr equencies. Aluminum foil, copper , and br aided st ainless st eel ar e mat er ials ver y
commonly used for cable shields due t o t heir low impedance pr oper t ies.
Simply incr easing t he separ at ion bet ween t he noise sour ce and t he cable will yield
significant addit ional at t enuat ion due t o r educed coupling, but shielding is st ill
r equir ed in most applicat ions involving r emot e sensor s.
Ther e ar e t wo pat hs fr om an EMI sour ce t o a suscept ible cable: capacit ive (or E-
field) and magnet ic (or H-field) coupling. Capacit ive coupling occur s when par asit ic
capacit ance exist s bet ween a noise sour ce and t he cable. The amount of par asit ic
capacit ance is det er mined by t he separ at ion, shape, or ient at ion, and t he medium
bet ween t he sour ce and t he cable.
Magnet ic coupling occur s t hr ough par asit ic mut ual induct ance when a magnet ic
field is coupled fr om one conduct or t o anot her . Par asit ic mut ual induct ance depends
on t he shape and r elat ive or ient at ion of t he cir cuit s in quest ion, t he magnet ic
pr oper t ies of t he medium, and is dir ect ly pr opor t ional t o conduct or loop ar ea.
Minimizing conduct or loop ar ea r educes magnet ic coupling pr opor t ionally.
Shielded twisted pair cables offer fur t her noise immunit y t o magnet ic fields.
Twist ing t he conduct or s t oget her r educes t he net loop ar ea, which has t he effect of
canceling any magnet ic field pickup, because t he sum of posit ive and negat ive
incr ement al loop ar eas is ideally equal t o zer o.
To st udy t he shielding pr oblem, a pr ecision RTD (Resistance Temperature Detector)
amplifier cir cuit was used as t he basis for a ser ies of exper iment s. A r emot e 100
RTD was connect ed t o t he br idge, br idge dr iver , and t he br idge amplifier cir cuit
(Figur e 7.77) using 10 feet of a shielded t wist ed pair cable. The RTD is one element
of a 4-element br idge (t he t hr ee ot her r esist or element s ar e locat ed in t he br idge and
br idge dr iver cir cuit ). The gain of t he inst r ument at ion amplifier was adjust ed so
t hat t he sensit ivit y at t he out put was 10mV/C, wit h a 5V full scale. Measur ement s
wer e made at t he out put of t he inst r ument at ion amplifier wit h t he shield gr ounded
in var ious ways. The exper iment s wer e conduct ed in lab st andar d envir onment
wher e a consider able amount of elect r onic equipment was in oper at ion.
70
UNGROUNDED SHIELDED CABLES ACT AS ANTENNAS
7.77
a
IN-AMP
OUTPUT
VERTICAL SCALE: 2mV/div
HORIZONTAL SCALE: 10ms/div
BRIDGE
AND
BRIDGE
DRIVER
IN
AMP
R
G
5V FS
10mV/C
10 FEET
SHIELDED
TWISTED
PAIR
RTD
100
The fir st exper iment was conduct ed wit h t he shield ungr ounded. As shown in Figur e
7.77, shields left float ing ar e not useful and offer no at t enuat ion t o EMI-induced
noise, in fact , t hey act as ant ennas. Capacit ive coupling is unaffect ed, because t he
float ing shield pr ovides a coupling pat h t o t he signal conduct or s. Most cables exhibit
par asit ic capacit ances bet ween 10-30pF/ft . Likewise, HF magnet ically coupled noise
is not at t enuat ed because t he float ing cable shield does not alt er eit her t he geomet r y
or t he magnet ic pr oper t ies of t he cable conduct or s. LF magnet ic noise is not
at t enuat ed significant ly, because most shield mat er ials absor b ver y lit t le magnet ic
ener gy.
To implement effect ive EMI/RFI shielding, t he shield must be gr ounded. A gr ounded
shield r educes t he value of t he impedance of t he shield t o gr ound t o small values.
Implement ing t his change will r educe t he amplit ude of t he E-Field noise
subst ant ially.
Designer s oft en gr ound bot h ends of a shield in an at t empt t o r educe shield
impedance and gain fur t her E-Field at t enuat ion. Unfor t unat ely, t his appr oach can
cr eat e a new set of pot ent ial pr oblems. The AC and DC gr ound pot ent ials ar e
gener ally differ ent at each end of t he shield. Low-fr equency gr ound loop cur r ent is
cr eat ed when bot h ends of a shield ar e gr ounded. This low fr equency cur r ent flows
t hr ough t he lar ge loop ar ea of t he shield and couples int o t he cent er conduct or s
t hr ough t he par asit ic mut ual induct ance. If t he t wist ed pair s ar e pr ecisely balanced,
t he induced volt age will appear as a common-mode r at her t han a differ ent ial
volt age. Unfor t unat ely, t he conduct or s may not be per fect ly balanced, t he sensor
and excit at ion cir cuit may not be fully balanced, and t he common mode r eject ion at
t he r eceiver may not be sufficient . Ther e will t her efor e be some differ ent ial noise
volt age developed bet ween t he conduct or s at t he out put end, which is amplified and
71
appear s at t he final out put of t he inst r ument at ion amplifier . Wit h t he shields of t he
exper iment al cir cuit gr ounded at bot h ends, t he r esult s ar e shown in Figur e 7.78.
GROUNDING BOTH ENDS OF A SHIELD PRODUCES
LOW FREQUENCY GROUND LOOPS
7.78
a
IN-AMP
OUTPUT
VERTICAL SCALE: 2mV/div
HORIZONTAL SCALE: 10ms/div
BRIDGE
AND
BRIDGE
DRIVER
IN
AMP
R
G
5V FS
10mV/C
10 FEET
SHIELDED
TWISTED
PAIR
RTD
100
G2
Figur e 7.79 illust r at es a pr oper ly gr ounded syst em wit h good elect r ic field shielding.
Not ice t hat t he gr ound loop has been eliminat ed. The shield has a single point
gr ound, locat ed at t he signal condit ioning cir cuit r y, and noise coupled int o t he shield
is effect ively shunt ed int o t he r eceiver gr ound and does not appear at t he out put of
t he inst r ument at ion amplifier .
72
GROUNDING SHIELD AT RECEIVER END SHUNTS LOW- AND
HIGH-FREQUENCY NOISE INTO RECEIVER GROUND
7.79
a
IN-AMP
OUTPUT
VERTICAL SCALE: 2mV/div
HORIZONTAL SCALE: 10ms/div
BRIDGE
AND
BRIDGE
DRIVER
IN
AMP
R
G
5V FS
10mV/C
10 FEET
SHIELDED
TWISTED
PAIR
RTD
100
Figur e 7.80 shows an example of a r emot ely locat ed, ungr ounded, passive sensor
(ECG elect r odes) which is connect ed t o a high-gain, low power AD620
inst r ument at ion amplifier t hr ough a shielded t wist ed pair cable. Not e t hat t he
shield is pr oper ly gr ounded at t he signal condit ioning cir cuit r y. The AD620 gain is
1000 , and t he amplifier is oper at ed on 3V supplies. Not ice t he absence of 60Hz
int er fer ence in t he amplifier out put .
73
FOR UNGROUNDED PASSIVE SENSORS,
GROUND SHIELD AT THE RECEIVING END
7.80
a
IN-AMP
OUTPUT
VERTICAL SCALE: 10mV/div
HORIZONTAL SCALE: 0.2sec/div
AD620
R
G
SHIELDED
TWISTED
PAIR
G1
+
-
REF
OUTPUT
G = 1000
G2
EEG
ELECTRODES
+
-
Most high impedance sensor s gener at e low-level cur r ent or volt age out put s, such as
a phot odiode r esponding t o incident light . These low-level signals ar e especially
suscept ible t o EMI, and oft en ar e of t he same or der of magnit ude as t he par asit ic
par amet er s of t he cable and input amplifier .
Even pr oper ly shielded cables can degr ade t he signals by int r oducing par asit ic
capacit ance t hat limit s bandwidt h, and leakage cur r ent s t hat limit sensit ivit y. An
example is shown in Figur e 7.81, wher e a high-impedance phot odiode is connect ed t o
a pr eamp t hr ough a long shielded t wist ed pair cable. Not only will t he cable
capacit ance limit bandwidt h, but cable leakage cur r ent limit s sensit ivit y. A pr e-
amplifier , locat ed close t o t he high-impedance sensor , is r ecommended t o amplify t he
signal and t o minimize t he effect of cable par asit ics.
74
SHIELDS ARE NOT EFFECTIVE WITH
HIGH IMPEDANCE REMOTE SENSORS
7.81
a
C
COMP
SHIELDED
TWISTED
PAIR
+
-
PHOTODIODE
DETECTOR R
FB
HIGH
IMPEDANCE
>100M
20pF/ft
CABLE CAPACITANCE LIMITS BANDWIDTH
CABLE LEAKAGE CURRENT LIMITS SENSITIVITY
Figur e 7.82 is an example of a high-impedance phot odiode det ect or and pr e-
amplifier , dr iving a shielded t wist ed pair cable. Bot h t he amplifier and t he shield ar e
gr ounded at a r emot e locat ion. The shield is connect ed t o t he cable dr iver common,
G1, ensur ing t hat t he signal and t he shield at t he dr iving end ar e bot h r efer enced t o
t he same point . The capacit or on t he r eceiving side of t he cable shunt s high
fr equency noise on t he shield int o gr ound G2 wit hout int r oducing a low-fr equency
gr ound loop. This popular gr ounding scheme is known as hybrid gr ounding.
75
REMOTELY LOCATED HIGH IMPEDANCE
SENSOR WITH PREAMP
7.82
a
REF
IN-AMP
SHIELDED
TWISTED
PAIR
PHOTODIODE
PREAMP
-
+
G2
HF GROUND
R
G
G1
LF AND HF
GROUND
-
+
Figur e 7.83 illust r at es a balanced act ive line dr iver wit h a hybr id shield gr ound
implement at ion. When a syst ems oper at ion calls for a wide fr equency r ange, t he
hybr id gr ounding t echnique oft en pr ovides t he best choice (Refer ence 8). The
capacit or at t he r eceiving end shunt s high-fr equency noise on t he shield int o G2
wit hout int r oducing a low-fr equency gr ound loop. At t he r eceiver , a common-mode
choke can be used t o help pr event RF pickup ent er ing t he r eceiver , and subsequent
RFI r ect ificat ion (see Refer ences 9 and 10). Car e should be t aken t hat t he shields
ar e gr ounded t o t he chassis ent r y point s t o pr event cont aminat ion of t he signal
gr ound (Refer ence 11).
76
HYBRID (LF AND HF) GROUNDING WITH ACTIVE DRIVER
7.83
a
REF
SHIELDED
TWISTED
PAIR
-
G2
HF GROUND
G1
LF AND HF
GROUND
BALANCED
LINE
DRIVER
BALANCED
LINE
RECEIVER
CM
CHOKE
To summar ize t his discussion, shield gr ounding t echniques must t ake int o account
t he t ype and t he configur at ion of t he sensor as well as t he nat ur e of t he int er fer ence.
When a low-impedance passive sensor is used, gr ounding t he shield t o t he r eceiving
end is t he best choice. Act ive sensor shields should gener ally be gr ounded at t he
sour ce (dir ect connect ion t o sour ce gr ound) and at t he r eceiver (connect t o r eceiver
gr ound using a capacit or ). This hybr id appr oach minimizes high-fr equency
int er fer ence and pr event s low-fr equency gr ound loops. Shielded t wist ed conduct or s
offer addit ional pr ot ect ion against shield noise because t he coupled noise occur s as a
common-mode, and not a differ ent ial signal.
The best shield can be compr omised by poor connect ion t echniques. Shields oft en use
pig-t ail connect ions t o make t he connect ion t o gr ound. A pig-t ail connect ion is a
single wir e connect ion fr om shield t o eit her chassis or cir cuit gr ound. This t ype of
connect ion is inexpensive, but at high fr equency, it does not pr ovide low impedance.
Qualit y shields do not leave lar ge gaps in t he cable/inst r ument shielding syst em.
Shield gaps pr ovide pat hs for high fr equency EMI t o ent er t he syst em. The cable
shielding syst em should include t he cable end connect or s. Ideally, cable shield
connect or s should make 360 cont act wit h t he chassis gr ound.
As shown in Figur e 7.84, pigt ail t er minat ions on cables ver y oft en cause syst ems t o
fail r adiat ed emissions t est s because high-fr equency noise has coupled int o t he cable
shield, gener ally t hr ough st r ay capacit ance. If t he lengt h of t he cable is consider ed
electrically long at t he int er fer ence fr equency, t hen it can behave as a ver y efficient
quar t er -wave ant enna. The cable pigt ail for ms a mat ching net wor k, as shown in t he
figur e, t o r adiat e t he noise which coupled int o t he shield. In gener al, pigt ails ar e
only r ecommended for applicat ions below 10kHz, such as 50/60Hz int er fer ence
pr ot ect ion. For applicat ions wher e t he int er fer ence is gr eat er t han 10kHz, shielded
connect or s, elect r ically and physically connect ed t o t he chassis, should be used.
77
"SHIELDED" CABLE CAN CARRY HIGH FREQUENCY
CURRENT AND BEHAVES AS AN ANTENNA
7.84
a
Reprinted from EDN Magazine (January 20, 1994) CAHNERS PUBLISHING COMPANY 1995, A Division of Reed Publishing USA
I
CM
I
CM
I
CM
= COMMON-MODE CURRENT
SHIELD
EQUIVALENT
CIRCUIT
78
REFERENCES: CABLE SHI ELDI NG
1. H.W. Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
Se con d Ed i t i on , J ohn Wiley & Sons, Inc., New Yor k, 1988.
2. Ralph Mor r ison, Gr ou n d i n g a n d Sh i eld i n g Tech n i q u es i n
I n st r u men t a t i on , Th i r d Ed i t i on , J ohn Wiley & Sons, Inc.,
New Yor k, 1988.
3. Syst ems Ap p li ca t i on Gu i d e, Sect ion 1, Analog Devices, Inc.,
Nor wood, MA, 1993.
4. AD620 Inst r ument at ion Amplifier , Dat a Sheet , Analog Devices, Inc.
5. A. Rich, Understanding Interference-Type Noise, An a log Di a logu e,
16-3, 1982, pp. 16-19.
6. A. Rich, S hielding and Guarding, An a log Di a logu e, 17-1, 1983,
pp. 8-13.
7. EDNs Designers Guide to Electromagnetic Compatibility, EDN,
J anuar y, 20, 1994, mat er ial r epr int ed by per mission of Cahner s
Publishing Company, 1995.
8. Designing for EMC (Workshop Notes), Kimmel Ger ke Associat es,
Lt d., 1994.
9. J ames Br yant and Her man Gelbach, High Frequency S ignal
Contamination, An a log Di a logu e, Vol. 27-2, 1993.
10. Walt J ung, S ystem RF Interference Prevention, An a log Di a logu e,
Vol. 28-2, 1994.
11. Neil Muncy, Noise S usceptibility in Analog and Digital S ignal
Processing S ystems, pr esent ed at 97t h Au d i o En gi n eer i n g Soci et y
Con ven t i on , Nov. 1994.
79
GENERAL REFERENCES: HARDWARE
DESI GN TECHNI QUES
1. Li n ea r Desi gn Semi n a r , Sect ion 11, Analog Devices, Inc., 1995.
2. E.S.D. P r even t i on Ma n u a l
Available fr ee fr om Analog Devices, Inc.
3. B.I. & B. Bleaney, Elect r i ci t y & Ma gn et i sm, OUP 1957, pp 23,24, & 52.
4. Paul Br okaw, An I.C. Amplifier User's Guide to Decoupling, Grounding
and Making Things Go Right for a Change, An a log Devi ces Ap p li ca t i on
Not e, Available fr ee of char ge fr om Analog Devices, Inc.
5. J eff Bar r ow, Avoiding Ground Problems in High S peed Circuits,
R.F. Desi gn , J uly 1989.
AND
Paul Br okaw & J eff Bar r ow, Grounding for Low- and High-Frequency
Circuits, An a log Di a logu e, 23-3 1989.
Fr ee fr om Analog Devices.
6. Int er nat ional EMI Emission Regulat ions
Canada CSA C108.8-M1983 FDR VDE 0871/VDE 0875
J apan CISPR (VCCI)/PUB 22 USA FCC-15 Par t J
7. Bill Slat t er y & J ohn Wynne, Design & Layout of a Video Graphics S ystem
for Reduced EMI, Analog Devices Applicat ion Not e (E1309-15-10/89)
Fr ee fr om Analog Devices.
8. William R. Blood, J r ., MECL Syst em Desi gn Ha n d book
(HB205, Rev. 1), Mot or ola Semiconduct or Pr oduct s, Inc., 1988.
9. Wainwr ight Inst r ument s Inc., 69 Madison Ave., Telfor d, PA,
18969-1829, Tel. 215-723-4333, Fax. 215-723-4620.
Wainwr ight Inst r ument s GmbH, Widder sber ger St r asse 14,
DW-8138 Andechs-Fr ieding, Ger many. Tel: +49-8152-3162,
Fax: +49-8152-40525.
10. Ralph Mor r ison, Gr ou n d i n g a n d Sh i eld i n g Tech n i q u es i n
I n st r u men t a t i on , Th i r d Ed i t i on , J ohn Wiley, Inc., 1986.
11. Henr y W. Ot t , Noi se Red u ct i on Tech n i qu es i n Elect r on i c Syst ems,
Se con d Ed i t i on , J ohn Wiley, Inc., 1988.
12. Rober t A. Pease, Tr ou blesh oot i n g An a log Ci r cu i t s, But t er wor t h-
Heinemann, 1991.
80
13. J im Williams, Edit or , An a log Ci r cu i t Desi gn : Ar t , Sci en ce, a n d
P er son a li t i es, But t er wor t h-Heinemann, 1991.
14. Doug Gr ant and Scot t Wur cer , Avoiding Passive Component Pitfalls,
Th e Best of An a log Di a logu e, pp. 143-148, Analog Devices, Inc., 1991.
15. Walt J ung and Richar d Mar sh, Picking Capacitors, Part I., Au d i o,
Febr uar y, 1980.
16. Walt J ung and Richar d Mar sh, Picking Capacitors, Part II., Au d i o,
Mar ch, 1980.
17. Dar yl Ger ke and Bill Kimmel, The Designer's Guide to Electromagnetic
Compatibility, EDN Su p p lemen t , J anuar y 20, 1994.
18. Walt Kest er , Basic Characteristics Distinguish S ampling A/ D Converters,
EDN, Sept ember 3, 1992, pp.135-144.
19. Walt Kest er , Peripheral Circuits Can Make or Break S ampling ADC
S ystem, EDN, Oct ober 1, 1992, pp. 97-105.
20. Walt Kest er , Layout, Grounding, and Filtering Complete S ampling
ADC S ystem, EDN, Oct ober 15, 1992, pp. 127-134.
21. Howar d W. J ohnson and Mar t in Gr aham, Hi gh -Sp eed Di gi t a l Desi gn ,
PTR Pr ent ice Hall, 1993.