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ADI Wireless Seminar 2006

Contents
I. II. III. IV. V. VI. VII. VIII. IX. X. XI. XII. XIII. Wireless Systems Overview RF/IF Components and Specifications for Receivers RF/IF Components and Specifications for Transmitters RF/IF Components - Active and Passive Mixers Phase-locked loops for high-frequency receivers and transmitters A Detailed Look at Wireless Signal Chain Architectures Optimizing Receiver Performance through Error Vector Analysis Design and Operation of Automatic Gain Control Loops for Receivers in Modern Communications Systems Using Calibration and Temperature Compensation to improve RF Detector Accuracy Techniques for Measuring RF Gain and VSWR A 2.4-GHz Direct Conversion Transmitter for WiMAX and WiBro Applications Design a Direct 6-GHz Local Oscillator with a Wideband, Integer-N, PLL Synthesizer Short Range Wireless Devices - Building a global licensefree system at frequencies below 1GHz

ADI 2006 RF Seminar

Chapter I Wireless Systems Overview

Transmitters Requirements

The modulated carrier must be transmitted with adequate power (anywhere from 100 mW to 500 W). The distortion and noise in adjacent spectrum must be below a certain minimum set by the standard and the customers desired margin this specification is called adjacent channel protection ratio or ACPR Component-level margin is a big selling point. Some customers want 10-20 dB of margin, especially for distortion specifications
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Receivers must be very good Listeners.......even in the presence of large unwanted signals
Power (dBm) Transmit Signal Out-of-Band Blocker

In-Band Blockers

A
DC

Desired Signal

Freq
Tx Band Rx Band

In mobile wireless applications, the received signal voltage can vary in size by a factor of 1,000,000 (120 dB), depending on the proximity to the source Receivers must isolate and demodulate the desired signal, even in the presence of nearby signals (Blockers) that are up to 1 million times larger In-Band Blockers are generated by other users of the same standard or frequency Out-of-Band blockers Example: Co-located transceivers on one tower, cordless phones, WLAN Routers.
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Error Vector Magnitude - EVM

EVM =

Mean Error Vector Power Mean ReferenceP ower

Unit(%)

Noise and Imperfections in transmit and receive signal chains result in demodulated voltages which are displaced from their ideal location. Error Vector Magnitude expresses this dislocation Large EVM will result in Symbol/data Errors Higher Order Modulation Schemes Symbols Closer Together EVM More Critical Solution: Choose components with higher Signal-to-Noise Ratio. Choose Modulator and DeModulator products which have precise quadrature, low harmonics and low LO leakage

An IF-Based Wireless Transceiver


MIXER LNA DIFF AMP

ADC VGA
0 90

ADC
IQ DEMODULATOR

VCO/SYNT

RSSI/PHASE DETECT

DAC
HIGH POWER AMP RF VGA MIXER IQ MODULATOR

VGA

0 90

DAC

POWE R D E TE C T

POWER CONTROL

A Direct Conversion Wireless Transceiver


IQ DEMOD

ADC
0 90
RSSI /AGC

ADC

Duplexer/ Switch

VCO/SYNTH

DAC
HIGH POWER AMPLIFIER RF VGA

0 90

IQ MOD
RF POWER DETECTION & CONTROL

DAC

Transceiver Components
LNAs amplify the signal received at antenna while adding very little noise High Power Amplifiers drive the antenna Mixers Convert signal between Radio Frequency (RF) and baseband IQ Modulators convert baseband signals in Cartesian (X,Y) format to real Intermediate Frequencies or Radio Frequencies. Power Detectors measure and control received and transmitted RF power Filters remove unwanted signals Amplifiers amplify the received signal and compensate for the losses of other components Variable Gain/AGC adjusts gain of receiver to yield a fixed output power at baseband ADC samples spectrum either at Intermediate Frequency (IF) or at Baseband IQ Demodulator extracts I and Q baseband signals from RF or IF carrier

ADI 2006 RF Seminar

Chapter II RF/IF Components and Specifications for Receivers

RF/IF Components and Specifications for Receivers

Fixed Gain and Variable Gain Amplifiers IQ Demodulators Analog-to-Digital Converters

ADI 2006 RF Seminar

Fixed Gain and Variable Gain Amplifiers

RF Components LNAs

Low Noise Amplifiers (LNA) amplify very small signals and add very little noise to the signal chain. Gain = 12-18 dB typically Noise Figure = 1-3 dB typically
A lower noise figure reduces overall system gain and power

LNA must sometimes amplify a weak signal in the presence of a large blocker. So LNA must also have high IP3. Some LNAs have a bypass circuit which is engaged when the input signal is large LNAs are typically internally matched and specified for a narrow band of operation LNAs are often integrated with a receive mixer in portable applications
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AD8353 and AD8354 RF Gain Blocks


Silicon Bipolar 50 ohm input & output Gain Blocks

KEY SPECIFICATIONS KEY SPECIFICATIONS


Frequency Range: 1MHz to 2.7GHz Frequency Range: 1MHz to 2.7GHz P1dB: 9dBm / / 5dBm P1dB: 9dBm 5dBm OIP3: 23dBm / / 19dBm OIP3: 23dBm 19dBm NF: 5dB / / 4dB NF: 5dB 4dB Isupply: 41mA / / 23mA Isupply: 41mA 23mA Package: 3mm xx2mm 8-CSP Package: 3mm 2mm 8-CSP

FEATURES FEATURES

Fully characterized over frequency range Fully characterized over frequency range Fully characterized over temp 40 to +85 C Fully characterized over temp 40 to +85 C Output power stable over temperature <1dB Output power stable over temperature <1dB Excellent gain stability over temp: < 1dB Excellent gain stability over temp: < 1dB

AD8352 Lowest Distortion Differential Amplifier


Highest Performance Differential ADC Driver on the Market

KEY SPECIFICATIONS KEY SPECIFICATIONS


Wide 3dB Bandwidth: 2GHz Wide 3dB Bandwidth: 2GHz Low Distortion Low Distortion
10 MHz, -86dBc HD2 -82dBc HD3 10 MHz, -86dBc HD2 -82dBc HD3 70 MHz, -84dBc HD2 -82dBc HD3 70 MHz, -84dBc HD2 -82dBc HD3 190Mhz, -81dBc HD2 -87dBc HD3 190Mhz, -81dBc HD2 -87dBc HD3

High Linearity: Output IP3 +41dBm @ High Linearity: Output IP3 +41dBm @ 150MHz 150MHz Low Input Noise: 2.6nV/Hz (Gain Low Input Noise: 2.6nV/Hz (Gain 10dB) 10dB)

FEATURES FEATURES

Single Resistor sets Gain 3dB to 21dB Single Resistor sets Gain 3dB to 21dB Single Resistor & Capacitor distortion Single Resistor & Capacitor distortion adjustment adjustment Small 3x3 mm 16-lead LFCSP Small 3x3 mm 16-lead LFCSP
Slide 5 (of 8)

AD8352 Superior Distortion Specs


Lower Distortion @ Higher Frequencies
The highest, the best

The lowest, the best

Closest competition

Slide 2 (of 8)

ADI 2006 RF Seminar

Receive VGAs

RF Components Variable Gain Amplifiers


In Receivers, VGAs adjust gain as received signal strength varies and present a constant signal level to the ADC In Transmitters, VGAs adjust for gain variations in the signal chain and set the output power to the desired level. Analog vs. Digital Control, Serial Control vs. Parallel Control choice often depends on control interface that is available in the system. The AGC detector may be in DSP (after an ADC) or hardware or both
a hardware AGC detector has a much faster response time A receiver with DSP-based AGC can be blinded by a strong signal while the system is responding

AD8368 RF/IF 800MHz Analog VGA


Features Single ended 50 input / output Analog Variable Gain Range: -11 to 22.5dB Linear-in-dB Scaling: ~35dB/V Integrated RMS AGC Detector Single +5V supply Small 4 x 4 mm 24-lead LFCSP Specifications Wide 3dB Bandwidth: 800MHz High Linearity Output IP3 +34dBm High Output Compression P1dB: +16dBm Low Noise Figure: 8dB max gain

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AD8370 Fine Resolution DGA


KEY SPECIFICATIONS KEY SPECIFICATIONS
Bandwidth 750MHz Bandwidth 750MHz Differential Input and Output Differential Input and Output Impedances: Impedances:
Zin ==200 , ,Zout ==100 Zin 200 Zout 100

P1dB 17dBm (70Mhz) P1dB 17dBm (70Mhz) OIP3 35 dBm (70MHz) (1K load) OIP3 35 dBm (70MHz) (1K load) OIP3 31dBm (70 MHz) (100 ohm load) OIP3 31dBm (70 MHz) (100 ohm load) Noise Figure 7dB (max gain) Noise Figure 7dB (max gain) Package 16-TSSOP Package 16-TSSOP

FEATURES FEATURES

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Serial 8-bit digital interface Serial 8-bit digital interface Wide gain control range Wide gain control range Linear-in-dB Operation using Look Up Table Linear-in-dB Operation using Look Up Table Power-down feature Power-down feature

AD8370 Fine Resolution DGA: Gain Range


40

High Gain Mode


30

20

Gain - dB

10

Low Gain Mode

-10

-20

-30 0 20 40 60 80 100 120 140

Gain Code

Two Operating Modes, High Gain and Low Gain, set by MSB Code Fine step size at the higher gain settings allows precise signal leveling Step size less than 1dB over-11 to 34dB gain range
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AD8370 DGA - Linear-in-dB Gain Code Mapping Mapping of AD8370 Gain versus Gain Code Linear-in-dB
35.0 30.0 25.0
True Gain in dB

1.000 0.800 0.600


Error

20.0 G a in in d B 15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0


5 7 10 14 20

0.400 0.200 0.000 -0.200 -0.400 -0.600 -0.800 -1.000 G a i n E r r o r (d B )

28

40

57

80

113

150

159

172

191

217

254

Gain Code

Gain Control can be made Linear-in-dB using simple look up table


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Receive Amplifiers Fixed Gain and Variable Gain


Part No. Control Type Analog Variable Analog Variable Digital Variable Digital Variable Fixed Gain Fixed Gain Fixed Gain Fixed Gain Fixed Gain Frequency Range (MHz) dc to 500 LF to 800 LF to 600 LF to 700 Gain (dB) -2.5 to +42.5 -11 to +22 -5 to +40 -11 to +17 +6 to +34 Output IP3 (dBm) 27.5 (70MHz) 34 19.5 (70MHz) 31 (70MHz) Noise Figure (dB) 6.2 8 7 7.4 Comments Single ended input/output Single ended input/output Differential input/output Differential input/output Differential ADC Driver Differential ADC Driver Differential ADC Driver Tx or Rx Gain Block Tx or Rx Gain Block

AD8367 AD8368 AD8369 AD8370

AD8350 AD8351 AD8352 AD8353 AD8354 14

LF-700 LF-1000 LF - 2000 1 to 2700 1 to 2700

20 26 24 20 20

28 33 41 23.6 19

6.8 9.5 15.5 5.3 4.2

ADI 2006 RF Seminar

IQ Demodulators

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RF Components IQ Demodulators
LO IN I Output RF/IF IN Q Output

Reverse Function to IQ Modulator IQ demodulation, extracts digital bits or symbols from a modulated carrier Local Oscillator (from PLL) at the same frequency as the center frequency of the carrier is split into Quadrature components of equal amplitude but 90 degrees out of phase Modulated signal is split and multiplied with Quadrature LO components (demodulation) to yield original IQ data/symbols For QPSK, digital data can be extracted using I and Q comparators For QAM, an ADC must be used to extract digital data Some IQ Demodulators have variable gain amplifiers at input and/or output
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RF Components IQ Demodulators
LO IN I Out RF IN Q Out

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Critical IQ Demodulator Specifications Noise Figure determines achievable sensitivity of receiver Input IP3 determines maximum acceptable input signal and/or blocker I and Q output bandwidth determines maximum receivable bandwidth and symbol rate LO to RF leakage generates output dc offsets which add to I and Q outputs Required LO Drive level Lower LO input power results in less leakage IIP3 low IIP3 can cause blockers to intermodulate and produce distortion at the carrier frequency, reducing receiver sensitivity IP2 low IIP2 will cause RF Input to intermodulate with itself and produce unwanted dc offsets at output

LO to RF Leakage Causes Self-Mixing and DC Offset Voltages at I and Q Outputs


LO GEN LO IN I Out LNA RF IN Q Out DC Offsets

Big Problem in Direct Conversion Receivers

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Solution Monitor and Null out DC Offsets at Baseband

LO GEN LO IN

LNA RF IN

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AD8348 I/Q Demodulator


KEY SPECIFICATIONS KEY SPECIFICATIONS
Phase accuracy 0.5 Phase accuracy 0.5 Amplitude balance 0.25 dB Amplitude balance 0.25 dB

Frequency Range 50MHz to 1000MHz Frequency Range 50MHz to 1000MHz Accuracy Accuracy

Demodulation bandwidth 75 MHz Demodulation bandwidth 75 MHz IIP3 +28 dBm @ min gain IIP3 +28 dBm @ min gain IIP3 8 dBm @ max gain IIP3 8 dBm @ max gain Amplitude balance 0.25 dB Amplitude balance 0.25 dB Noise figure 11 dB @ max gain Noise figure 11 dB @ max gain Package 28-lead TSSOP Package 28-lead TSSOP

FEATURES FEATURES

Power-Down Mode Power-Down Mode Integrated DC offset-nulling Integrated DC offset-nulling


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Integrated I/Q demodulator with IF VGA amplifier Integrated I/Q demodulator with IF VGA amplifier Linear-in-dB AGC range 44 dB Linear-in-dB AGC range 44 dB

ADI 2006 RF Seminar

ADCs

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RF Components ADCs
Baseband ADCs (usually sold as duals) sample QAM outputs from an IQ demodulator.
Higher order modulation schemes higher resolution ADCs Higher ADC resolution lower noise increased sensitivity Higher symbol rates higher ADC sampling rates

IF Sampling ADCs capture signal at Intermediate Frequency and mix it down into the first Nyquist band.
Require high input (analog) bandwidth typically more expensive than baseband ADCs eliminate down conversion analog circuitry (PLL, Mixer)

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ADI 2006 RF Seminar

Chapter III RF/IF Components and Specifications for Transmitters

RF/IF Components and Specifications for Transmitters


Transmit DACs IQ Modulators Amplifiers Synthesizers RF Power Detectors Gain/Phase Detectors Vector Modulators

Transmit DACs
Baseband DACS (usually sold in duals) generate baseband modulated drive signals for IQ Modulators
Higher order modulation schemes higher resolution DACs Higher symbol rates higher DAC sampling rates

IF Synthesizing DACS digitally up convert the baseband signal and produce a low Intermediate Frequency either in real form (single DAC) or in complex form (dual DAC)
IF Synthesizing DACs higher performance than Baseband DACs Eliminate the need for one PLL and one mixer Produce better modulation quality (lower EVM)

ADI 2006 RF Seminar

IQ Modulators

RF Components IQ Modulators
I IN
0

LO
90

RF OUT

Q IN

An un-Modulated Sinewave drives LO input (from PLL). LO is split into Quadrature components of equal amplitude but 90 degrees out of phase I and Q drive signals are multiplied by LO Quadrature Components and then combined to make IF or RF output The phase and amplitude of the output carrier can be adjusted continuously if the amplitude of the I and Q signals is varied (vector modulation) For QPSK Modulation, input to I and Q can be a (filtered) Digital Bit Streams of +1 and -1 (not 1 and 0) For QAM Modulation, I and Q will be multi-level (driven from DAC)
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RF Components IQ Modulators
I IN
0

LO
90

RF OUT

Q IN

Critical IQ Mod Specifications


Baseband Bandwidth higher bandwidth allows higher data rate Output Compression Point and Noise Floor set SNR Quadrature balance of LO Splitter affects EVM Amplitude balance of LO Splitter affects EVM LO to RF Out Leakage adds unwanted component to modulated signal and degrades EVM (is caused by offset voltages on I and Q inputs) Amplitude Balance of I and Q Channels affects EVM IP2 and IP3 determine distortion Products that appear in adjacent channels. Amplitude and phase imbalance of any signals affects image suppression in image-reject upconverter
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Quadrature Modulation Refresher


800 600 400 800 600 400

IIout1, mV

IIout3, mV

0 -20

200 0 -200 -400 -600 -800

200 0 -200 -400 -600 -800 800 600 400

800 600 400

dBm(Mod_Spectrum)

-40 -60 -80 -100 -120 -140 69.85 69.90 69.95 70.00 70.05 70.10 70.15

DataOut, mV

200 0

800 -200 -400 600 400

QQout1, mV

-600 -800 1.0 1.5 2.0

200 0 -200 -400 -600 -800 1.0 1.5 2.0

QQout3, mV

200 0 -200 -400 -600 -800 1.329 1.829 2.329

ti m e , m s e c

ti m e , m s e c

ti m e , m s e c

freq, MHz

Baseband Data

Bit to Symbol Encoder

Pulse Shaping Filter

DAC 90 0 DAC

RF(t)

RF(t)=A(t)cos(ct+(t)) = I(t)cosct + Q(t)sinct


Polar representation 7 Cartesian representation

Example - Digital Modulation - QPSK


time

1 -1

Multiplier

90

2 bits/symbol
90

CW
1 -1

180

270
Delta 1 [T1 FXD] RBW VBW SWT 30 kHz 30 kHz 76 ms Unit dBm RF Att 30 dB

Input Data

Multiplier

Ref Lvl 35 dBm


35 30

0.50 dB -25.25050100 kHz

1 LIMIT CHECK 1 FXD 27.032 dBm

: PASSED

20

SGL TRG

10

1AVG

1SA

-10

-20

-30

XG_MM35
-40

-50

-60 -65

FXD Center 900 MHz 360 kHz/ 21:25:38 Span 3.6 MHz

Date:

6.SEP.2002

In Practice bit stream is low pass filtered before modulation to limit the bandwidth of the modulated spectrum

Digital Phase Modulation Schemes


m=2, n=1 m=4, n=2 m=8, n=3

BPSK 1 bit/symbol

QPSK- 2 bits/symbol m=16, n=4

8-PSK 3 bits/symbol m=64, n=8

64 QAM 6 bits/symbol 16 QAM 4 bits/symbol

Higher Order Modulation Schemes Higher Data Rate. But Symbols are closer together Requires higher Signal-toNoise Ratio for demodulation Increasing Symbol Rate increases data rate but widens Spectrum
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Symbolic Representation of Quadrature Modulator


Cos(2t)
I IN
0

Cos((1-2)t)
RF Out

Sin(2t)

Q IN LO

90

Cos(1t) Vout = Cos(1t)Cos(2t) + Sin(2t)Sin(1t) = Cos((1-2)t)

Local Oscillator signal is split into quadrature components Mix with quadrature baseband components and you get a single tone at the difference frequency (w1 -w2)
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Symbolic Representation of Quadrature Modulator with Errors and Baseband Offset Errors
Cos(2t)
I IN
Vos
0+

Cos((1-2)t) + LO Leakage + Unwanted Sideband


RF Out

Sin(2t)

Q IN

Vos

90-

LO

Cos(1t) Vout = (Cos(2t)+Vos)Cos(1t+) + (Sin(2t)-Vos)Sin(1t-) = = Cos((21)t - ) + Cos((21)t + ) + 2

Lower Sideband Unwanted Upper Sideband

LO Leakage

Vos(Cos(1t + ) - Sin(1t - )) + Cos((2+1)t + ) - Cos((2+1)t - ) 2

Baseband amplitude, offset and phase errors along with LO quadrature errors will produce unwanted components at the LO and image frequencies
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Upconverted Single Side Band Signal with Lo Leakage and upper Sideband Leakage

12

Baseband Offset Compensation can be used to remove LO Leakage To remove upper sideband, baseband amplitude and phase compensation is required. 2nd and 3rd order harmonics cannot be easily removed While Single Sideband Modulation is not used in end-applications, an SSB spectrum gives valuable information about the quality of the WCDMA, CDMA, GMSK, etc spectrum Excessive LO leakage, Sideband Leakage and harmonics will increase Error Vector Magnitude (EVM)

Modulator Noise Floor


Out -of -Band Noise F loor A djac ent Adjac ent Channel Channel Channel P ower P ower Power I n-Band Nois e F loor B and-P ass Filt er

2110 MHz

2170 MHz

Noise of a modulator is typically specified in dBm/Hz (output referred) Noise (dBm) = Noise floor + 10 log(RBW) e.g. Noise Floor of 150 dBm/Hz becomes 90 dBm when measured in a 1 MHz Resolution Bandwidth In-Band Noise cannot be filtered in a Direct Conversion Architecture (Zero IF or Low IF) Direct Conversion Modulators must be designed for high output power, low distortion and low noise floor GSM spec calls for a noise floor of 36 dBm (peak-hold, in 100 KHz BW) at the antenna. Toughest WCDMA spec calls for 30 dBm (in 1MHz BW) noise floor at the antenna CDMA calls for <-13 dBm dBm (in 1 MHz BW) at either 4 MHz (cell band) or 2.25 MHz (PCS band) carrier offset. Need to know how much gain (and noise) comes after the modulator to relate modulator noise specs to system requirement 13

AD8349 Direct I/Q Modulator


KEY SPECIFICATIONS KEY SPECIFICATIONS
Frequency Range: 700 to 2700 MHz Frequency Range: 700 to 2700 MHz Modulation Bandwidth DC-160Mhz Modulation Bandwidth DC-160Mhz Accuracy: Accuracy:
Phase Error: 0.7 Phase Error: 0.7 Amplitude Error: 0.1dB Amplitude Error: 0.1dB

Sideband Suppression -40dBc Sideband Suppression -40dBc Noise Floor -156dBm/Hz Noise Floor -156dBm/Hz P1dB 7.6 dBm (1900MHz) P1dB 7.6 dBm (1900MHz) Package 16-TSSOP Package 16-TSSOP

FEATURES FEATURES

Matched 50 ohm output Matched 50 ohm output TxDAC compatible base band inputs TxDAC compatible base band inputs Output disable function Output disable function

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Direct Conversion I/Q Modulators


FMOD Family of I/Q Modulators
ADL5370 250MHz 1.3GHz ADL5371 700MHz 1.3GHz ADL5372 1.6GHz 2.4GHz ADL5373 2.4GHz 2.7GHz ADL5374 3.3GHz 3.8GHz
QIP QIN COM COM IIP COM COM ENOP VPL VPL VPL 5V IIN VPB VPB VPA VPA 5V Qin 0.5V0.5V Iin 0.5V0.5V

OIP3: 24dBm Output Noise: -158dBm/Hz OP1dB: 11dBm Sideband Rejection: >40dBc LO leakage: <-40dBm LO power: 0dBm I/Q Bandwidth: >500MHz
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0/90o

VPA OUT RFout 50

CML LOP LON CML CMS CMS

DC power: 5V, 190mA

Loin 50

I/Q Modulators
Part No. RF Freq (MHz) 140 to 1000 800 to 2500 700 to 2700 20 to 2400 50 to 1000 2503800 IQ Bandwidth (MHz) 80 70 160 230 700 500 Carrier Suppress (dBm) -42 -42 -42 N/A -41 -40 Sideband Suppress (dBc) -42 -36 -43 N/A -40 -40 Noise Floor (dBm/Hz) -155 -147 -156 -150 -158 -158 P1dB (dBm) Power Supply (mA) 65 45 135 130 250 190 Package

AD8345 AD8346 AD8349 ADL5390 ADL5385* ADL537074*

2.5 -3 6 +13 +9 +11

16-lead TSSOP 16-lead TSSOP 16-lead TSSOP 24-Lead LFCSP 24-Lead LFCSP 24-Lead LFCSP

* Preliminary Data
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ADI 2006 RF Seminar

Amplifiers

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RF Components Amplifiers
RF Amps
Input and Output Impedance is 50-1000 Fixed or Variable Gain Specify Noise as Noise Figure (dB) Specify power-handling capability as P1dB Specify Intermodulation Distortion as IP2 and IP3

Op Amps
High Input Impedance Very Low Output Impedance Gain set using Feedback Specify Noise in nV/Hz Specify Voltage Swing (railto-rail, etc.) Specify Harmonic Distortion in dBc

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Intermodulation Distortion*
2 tones 2nd harmonics F2 2F2-F1 3rd 2F1 2F2 2nd F1+F2

F1

F2
2nd F2-F1

F1

AMP

2F1-F2

IMD products are produced by all active components (mixers, amps, ADCs, DACs) Third Order IMD Products (close to carrier, nF1+-mF2, n+m=3) are most troublesome
In Transmitters: IMD causes interference in adjacent channels In Receivers: Blocker inter-mod products can fall on the desired signal and desensitize the receiver

Second Order IMD Products (F2-F1, n=m=1) cause problems in Direct Conversion Receivers
Example: Two RF tones 20 kHz apart produce a 20 kHz product at baseband

Two-Tone test is commonly used to predict behavior


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Noise
A background noise power of -174 dBm/Hz is present at every point in a signal chain NF = Noise Figure (dB) = 10 log (Noise Factor) Noise Power: P = kT (Watts)
k = 1.38 x 10-23 J/K (Boltzmans constant) T = Kelvin Temperature 298K (25 degC)

Noise Power (dBm) = 10 log (kT/1mW)


= 10 log kT + 30 = -173.9 dBm -174 dBm

Noise in a bandwidth B in Hz
= -174 dBm/Hz + 10 log B

Noise Floor, or minimum discernable signal (MDS)


= -174 dBm + 10 log B + NF

Receiver Sensitivity for demodulation at a given carrier to noise (C/N) ratio


= -174 dBm + 10 log B + NF + C/N This is the customers design specification!
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Noise & IP3 combine to yield Spurious Free Dynamic Range (SFDR)
SFDR

Required SNR

SFDR =

2 3

[IP3 Noise Floor ]

Bottom end of SFDR is defined by the required signal-to-noise ratio (to demodulate signal) Top end of SFDR is defined by point at which IMD products become equal to noise floor SFDR is defined differently for ADCs and DACs
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ADL5322/5323 1/2W Driver Amplifiers


GaAs-based PA drivers with internal matching. Operating Frequencies 700-1000 MHz, 1700-2400 MHz Gain: 20 dB Gain Stable vs. Temp (0.5dB) and Freq (0.25dB in-band) OIP3: +40/42 dBm OP1dB: +27 dBm Noise Figure: 4.3/5.1 dB

Bias control

VCC 5
GND 6 GND 7
Input Match
Output M at ch

4 RFOUT 3 GND 2 VCC 1 VCC

RFIN 8

ADL5322

22

ADL5323 Single Carrier ACPR

Low and Noise and Low Distortion results in very low Adjacent Channel Power Leakage Reducing Output Power will improve Distortion but will degrade SNR

23

ADL5330 1MHz to 3GHz Variable Gain Amplifier


KEY SPECIFICATIONS KEY SPECIFICATIONS
Frequency Range 1MHz to 3GHz Frequency Range 1MHz to 3GHz OIP3 31 dBm @ 900 MHz OIP3 31 dBm @ 900 MHz Output Noise Floor -150 dBm/Hz Output Noise Floor -150 dBm/Hz

50 Differential or Single-Ended 50 Differential or Single-Ended Input Input Gain Control Range: -34 dB to Gain Control Range: -34 dB to +22 dB @ 900 MHz +22 dB @ 900 MHz Package 4x4mm 24-LFCSP Package 4x4mm 24-LFCSP

FEATURES FEATURES

Voltage-Controlled Amplifier/Attenuator Voltage-Controlled Amplifier/Attenuator Optimized for Controlling Output Power Optimized for Controlling Output Power Fully-Balanced Differential Signal Path Fully-Balanced Differential Signal Path Linear-in-dB Gain Control Function, 20 mV/dB Linear-in-dB Gain Control Function, 20 mV/dB

24

ADL5330: 1MHz to 3GHz VGA


Gain vs. Gain Control Voltage
40 30 20 10 0 -10 -20 -30 -40 0
25

Gain - dB

100 MHz 900 MHz 1900 MHz 2200 MHz


0.2 0.4 0.6 0.8 1 Vgain - Volts 1.2 1.4 1.6

ADL5330: 1MHz to 3GHz VGA


OIP3, P1dB and Noise Floor vs. Gain @ 900 MHz

26

RF/IF Transmit Amplifiers


Freq Range (MHz) 1 to 2700 1 to 2700 700-1000 1700-2400 1-3000 Noise Figure (dB) 5.3 4.2 5.1 4.3 8

Part# AD8353 AD8354 ADL5322 ADL5323 ADL5330

Gain (dB) 20 20 20 20 -34 to +22

Output IP3 (dBm) 23.6 19 42 40 31

Output P1dB (dBm) 9.1 (900 MHz) 4.8 (900 MHz) 27 27 22

Comments Rx or Tx Rx or Tx Matched Driver Amp Matched Driver Amp Tx VGA

27

ADI 2006 RF Seminar

Oscillators and PLLs

28

RF Components Oscillators and PLLs

Phase Noise

fREF/R = f0/N

fLO

Phase Locked Loops convert a reference frequency fREF to a higher frequency f0, which is highly stable Integer-N PLLs produce an output frequency that is an integer multiple of the reference frequency Fractional-N PLLs can produce an output which is not an integer multiple of the reference frequency (N can now have a fractional component) Phase noise and lock time are a PLLs most critical specifications Output frequency is generated by a Voltage Controlled Oscillator (VCO) which may be integrated with the PLL (ADF4360) at the cost of degraded phase noise
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Why is PLL phase noise so important?


Blocker Strong blocker is modulated by phase noise of LO and interferes with desired signal

Wanted Signal

RF LO

IF
fIF

fRF

Phase Noise
fLO

Reciprocal mixing occurs when the phase noise (side-skirts) of the LO mixes with an unwanted signal and produces an unwanted interference on top of the desired signal
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Phase noise vs. Thermal noise

Strong blocker is modulated by phase noise of LO and interferes with desire signal

Wanted Signal

RF
fRF

IF LO

10dB

fIF

Phase Noise (dBc)

Thermal and Device Noise (dBm/Hz)

fLO Phase noise spreads the desired carrier and is usually specified in dBc/Hz at a particular offset from the LO (usually 1 or 10 KHz) Background or Thermal noise which is present at all points in the signal chain will be amplified if there is gain in the signal chain. Amplifier/Mixer Noise Figure will add additional noise to the output of the signal chain (see slide 26). This resulting noise is usually specified in dBm/Hz. 31

ADI 2006 RF Seminar

RF Power Detectors

32

Why measure RF/IF power?


Thermal Dimensioning (mostly HPA) Signal Leveling in receivers (high precision generally not required, usually done at IF) Set mobiles power level (RSSI measurement in BTS receiver) Prevent interference with other systems and other users in same cell (mobile handset). Improve mobile talk time (operate at low end of permissible range, reduce SAR). Improve network robustness (operate at high end of permissible range).

33

Transmit Power Measurement/Control Options


RF INPUT
RF INPUT

RF DETECT

RF DETECT DAC SETPOINT INPUT


DSP or uController ADC DAC

(a)

(b)

RF INPUT DSP or ADC uController MIXER PLL SAW ADC

RSSI OUTPUT RECEIVER BASEBAND OUTPUT DUPL

RF INPUT DSP or uController IF SAMPLING ADC DAC DAC

(c)

(d)

34

Receiver Power Measurement/Control Options

Received Power Measurement


AD8361/62 AD8318/14

Received Power Control


AD8367

ADC

ADC

ADC
LO2

AD8361
Vagc

Vgain for RSSI

LO2

Measure received power to ensure that the received signal is not too big or not too small when it reaches the end of the signal chain Precision requirements for detectors in receivers are generally not as critical as in transmitters
35

RF Detectors Critical Specifications


Linearity and Temperature Stability of Output Dynamic Range Pulse Response Variations due to Power Supply and Frequency Changes Ease of Use and Calibration Change in response vs. signal crest factor Size and overall Component Count

36

ADI 2006 RF Seminar

RF Power Measurement Techniques

37

Power Measurement Techniques Diode Detection

RFI N

D1

Vout

68

100pF

R1

Source: A Supressed Harmonic Power Detector for Dual Band Phones Alan Rixon and Raymond Waugh Applied Microwave and Wireless, November 1999

38

Transfer Function of Diode Detector


Vout vs. Pinput
10

0.1

Vout-Volts

0.01

0.001

0.0 001

0 .00001 -25

-20

-15

-10

-5

10

15

20

25

Pinput-dBm

-25 deg C

25 deg c

+85 deg C

-30 DEG C

-40 DEG C

39

Diode Detector with Temperature Compensation

RFIN

D1

R1

Vout

68

100pF

R2 D2

Source: A Supressed Harmonic Power Detector for Dual Band Phones Alan Rixon and Raymond Waugh Applied Microwave and Wireless, November 1999

40

Transfer Function of Temperature Compensated Diode Detector


3 2.5 2 1.5 1 -40 degC 1 Vout - Volts 0.1 0.01 -20 -10 0 10 20 10

Error-dB

0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 +25 degC +85 degC

Pin - dBm

Excellent temperature stability at high power Limited Dynamic Range and poor low end temp. stability High Resolution ADC required for low end power measurement Lots of patented techniques which probably improve this performance
41

Thermal Detection
VOUT A2 HEATER PROT ECT ION A1 KVIN KVOUT HEATER PROT ECT ION

VIN

R1

S1

S2

R2

THERMAL BA RR IER

Technique is mostly confined to Instrumentation Applications

42

ADI 2006 RF Seminar

Logarithmic Amplifiers

43

Log Amp Transfer Function in Time Domain

44

Slope = (VO2-VO1)/(PI2-PI1)

Log Amp Transfer Function - Slope and Intercept


2.0 1.8 1.6 1.4 40 degC +25 degC
e op Sl

5 4 3 2 1 0 1 2 3 4 5
ER R OR dB

Intercept = PI1 - VO1/Slope Vout = Slope(Pin-Intercept)

V S = +5V

Pin = (Vout/Slope) + Intercept 1.2


Vou t - Vo lts

1.0 0.8 0.6 0.4 0.2 0

+85degC

100

90

80

70

60

Intercept
45

30 20 50 40 IN PUT AMPLITUDE dBm

10

10

RF Power Detector Calibration


VOUTIDEAL = SLOPE x (PIN - INTERCEPT) SLOPE = (VOUT1-VOUT2)/(PIN1-PIN2) INTERCEPT = PIN1-(VOUT1/SLOPE) Error (dB) = (VOUT-VOUTIDEAL)/SLOPE

VOUT2

VOUT1

PIN2

PIN1

INTERCEPT

46

1 dB Dynamic Range

55 dB Dynamic Range

Temperature Drift can reduce Dynamic Range


47

Detector Calibration Procedure


Factory Calibration: Using a precise power source, measure output voltage from the detector with two known input powers at top and bottom of desired input range Perform calibration measurements only at room temperature Calculate SLOPE and INTERCEPT and store in non-volatile memory When equipment is in operation measure detector output voltage using ADC Calculate power using Pin = (Vout/Slope) + Intercept No temperature compensation necessary

48

Adjust Calibration Points for optimal accuracy over a narrow range

VOUT2

VOUT1

PIN2

PIN1

Calibrate for highest accuracy at max RF power and degraded accuracy at lower powers
49

Temperature drift vs. Output Voltage at 25C


2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -65 -60 -55 -50 -45 -40 -35 -30 Pin-dBm -25 -20 -15 -10 -5 0 5
Vout +25 degC Vout -40 degC Vout +85 degC Error +25 degC Error -40 degC Error +85 degC

2.5 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 Error - dB

Calibration eliminates error due to non-linearity at 25 C


50

Vout - Volts

Temperature drift vs. Output Voltage at 25C


Removes error due to non-linearity at 25C Provides larger dynamic range and improved accuracy Method however does not account for non-linearity in the transfer function at room temperature For practical implementation, calibration measurements must be taken at multiple input powers (multi-point calibration vs. 2-point calibration)

51

AD8318: Highest Performance Log Amp


KEY SPECIFICATIONS KEY SPECIFICATIONS

Bandwidth 1MHz to 8Ghz Bandwidth 1MHz to 8Ghz Stability over temperature: 0.5 dB Stability over temperature: 0.5 dB Pulse response time 10 ns Pulse response time 10 ns Package: 4mm4mm, 16-pin LFCSP Package: 4mm4mm, 16-pin LFCSP

FEATURES FEATURES

Integrated temperature sensor Integrated temperature sensor Low noise measurement/controller output VOUT Low noise measurement/controller output VOUT Power-down feature: <1.5 mW at 55V Power-down feature: <1.5 mW at V Fabricated using high speed SiGe process Fabricated using high speed SiGe process

52

AD8318 High Performance Log Amp


< 0.5 dB accuracy over temperature
2.2
Vout +25 degC

2.5
Vout +85 degC Vout -40 degC

2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 -65 -60 -55 -50 -45 -40 -35 -30 PIN - dBm -25 -20

2 1.5 1 0.5 0 -0.5 -1 -1.5 Error - dB

Error +25 degC Error +85 degC Error -40 degC

VOUT - Volts

HIGH Linearity OVER 55dB


-15 -10 -5 0 5

-2 -2.5

53

5.8 GHz

Log Amp Pulse Response Time


10ns Response Time (10% - 90%)

54

Typical and Maximum Errors vs. Temperature


Production testing of drift over temperature is generally not economical for IC manufacture (or for end equipment manufacture) Guaranteed-not-Tested (GNT) specs rely too much on statistics and are much too conservative Solution: Show performance data from multiple devices drawn from multiple factory lots

55

Typical and Maximum Errors vs. Temperature

56

Log Amp Detectors vs. Diode Detectors

RFI N

D 1

Vout

LOG

68

100pF

R 1

2.5 2 Voltage Out 1.5 1 0.5 0 5 -70 -55 -40 -25 Input Pow er (dBm ) -10 20

57

Log Amp Detectors vs. Diode Detectors


Log Amps have a higher dynamic range (40 dB or greater vs. 20-30 dB for a diode detector) Log Amps provide good temperature stability over a wide dynamic range. Diode detectors only provide good temperature stability at max input power (typically +15 dBm)

58

Log Amp Detectors


Part No.
AD8309 AD8310 AD8318

RF Freq (MHz)
5 to 500 dc to 440

Dynamic Range (dB)


100 95

Temp Drift (dB)


1 1

Response Time (ns)


67 15 8

Package
16-lead TSSOP 8-lead MSOP 16-LEAD 3x3 mm CSP 8-LEAD 3x2 mm CSP 8-LEAD 3x2 mm CSP 14-LEAD TSSOP 24-LEAD LFCSP

Comments
Amplitude and Limiter Outputs

1 to 8000

60

0.5

AD8317

1 to 10000

50

0.5

AD8319

1 to 10000

40

0.5

AD8302

LF to 2700

60

50

Dual Gain and Phase Detection Dual Power and Gain Detection

ADL5519 59

1 to 10000

50

0.5

Log Amps - Summary


Provide power detection over large dynamic range (up to 100 dB) Operation from DC to 10 GHz With 2-Point Calibration, measurement accuracy of << 1 dB is achievable. Devices are generally configured to provide a broadband 50 match Pulse Response times of <10 ns are achievable. Power consumption varies from 5 mA to 70 mA

60

ADI 2006 RF Seminar

RMS-Responding RF Detectors

61

Response of a Successive Detection Log Amp to Varying Signals with Various Crest Factors
1.2 3.0

2.0

Vout - Volts

0.8

1.0

0.6

0.0

0.4

-1.0

0.2

-2.0

-3.0

-45

-35

-25

-15

-5

Pin-dBm
62

Error - dB

Using a Successive Detection Log Amp to Measure Signals with Varying Crest Factors
Successive Detection Log Amps produce varying output voltages with varying crest factors Intercept varies but slope is unaffected Not an issue in systems with constant crest factor If the system knows which signal types are being transmitted, a correction factor (from a look-up table) can be applied. If the crest factor of the signal is unknown, an RMSresponding detector must be used.

63

An RMS-Responding RF Detector
VPOS
OUTPUT DC BIAS CONTROL

SREF

IREF

X2

6.4R
VRMS

RFIN

X2

+
50 pF

FLTR

PWDN

POWER UP/DOWN

AD8361

COM M

64

Transfer Function and Temperature Drift of AD8361 RMS-To-DC Converter

Output Voltage increases exponentially as input increases in dB (i.e. response is linear in V/V, not logarithmic Device achieves best temperature stability at max power (desirable for most applications)
65

ADL5501 RMS / TruPwr Detector


Linear in Volts +/- 0.25dB accuracy and temperature stability +/- 0.1dB accuracy and temperature stability at the top end of the input power range where it counts most. 100 MHz to 4.0GHz SC-70 Package Ideal for Measuring Complex Waveforms with varying crest factors (WCDMA, HSDPA, HSUPA, CDMA2000, TDSCDMA, WiMax).

ADL5501
RFIN x2 i

INTERNAL FILTER CAPACITOR

VPOS FLTR

TRANSCONDUCTANCE CELLS x2 i

ERROR AMP BUFFER 100O VRMS

BAND-GAP REFERENCE

ENBL COMM

66

Log Amps vs. Low Range RMS-to-DC Detector


RFIN LOG Vout RMS

6 5 Voltage Out 4 3 2 1 0 -70 -60 -50 -40 -30 -20 -10 Input Power (dBm) 0 10 20

67

Log Amps vs. Low Range RMS-to-DC Detector


Log Amps have higher dynamic range but rms-to-dc converters have more resolution at the high end. Measurement precision is often most critical at high output power (Emissions Regulations, SAR, etc.) Log Amps consume constant supply current independent of input level. RMS-to-DC converters supply current increases with input signal power.

68

ADI 2006 RF Seminar

High Dynamic Range RMS Detection

69

AD8362 60 dB TruPwr RMS Detector


KEY SPECIFICATIONS KEY SPECIFICATIONS
Dynamic Range: >60dB Dynamic Range: >60dB Temperature Stability: +/-1dB Temperature Stability: +/-1dB Frequency Range: LF to 2.7GHz Frequency Range: LF to 2.7GHz Package: 16 Lead TSSOP Package: 16 Lead TSSOP

FEATURES FEATURES
True RMS responding power detector True RMS responding power detector Waveform and Modulation Independent Waveform and Modulation Independent Linear-in-dB output Linear-in-dB output

70

Response of AD8362 RMS Detector to CW, QPSK and QAM Signals


4 4 3.5

2.5 Vout (V)

Vout CW Vout QPSK Vout 64QAM Vout 256QAM Vout WCDMA TM1-64 Error CW Error QPSK 4dB CF Error 64QAM 7.7dB CF Error 256QAM 8.2dB CF Error WCDMA TM1-64 10.6dB CF

1
Error (dB)

1.5

-1

-2

0.5

-3

0 -70 -60 -50 -40 -30 -20 -10 0 10 20 Pin (dBm)

-4

@1.9 GHz, Vtgt = 0.625 V


71

AD8364 Dual Channel TruPwr Detector


KEY SPECIFICATIONS KEY SPECIFICATIONS
Dynamic Range: >60dB Dynamic Range: >60dB Temperature Stability: +/-0.5dB Temperature Stability: +/-0.5dB Frequency Range: LF to 2.7GHz Frequency Range: LF to 2.7GHz Package: 5x5mm 32 Lead LFCSP Package: 5x5mm 32 Lead LFCSP

FEATURES FEATURES

Dual channel and Difference Output Ports Dual channel and Difference Output Ports Integrated accurately scaled Temperature Sensor Integrated accurately scaled Temperature Sensor Linear-in-dB output Linear-in-dB output

72

AD8364 RMS-DC Accuracy @ 2140 MHz -40 degC to +85 degC

Vout 25deg
3.5

Vout -40deg Vo +85deg Error +25deg

2.5

Error -40deg Error +85deg

1.5

-1

-2

0.5

-3

0 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15

-4

Pin (dBm)

73

Error(dB)

Vout (V)

TruPwr RMS Detectors


Modulation Independent RF Measurements
Dynamic Range (dB) Temp Stability (dB) Supply Current (mA)

Part#

RF Freq (MHz)

Voltage Supply (V)

Package

AD8361 ADL5501 AD8362 AD8364 (Dual Channel)

2500 4000 2700 2700

30 30 60 60

0.25 0.25 1 0.5

2.7 to 5.5 2.7 to 5.5 4.5 to 5.5 4.5 to 5.5

1.1 1 20
72

6-Lead SOT-23 8-Lead uSOIC 6-Lead SC-70 16-Lead SOP 32-Lead LFCSP

74

ADI 2006 RF Seminar

Controlling AGC Loops with RF Detectors

75

A Typical AGC Loop


Gain Vcontrol

Vin

VGA

Vout

Vout (dc)

I C dV/dt = I/C

Detector
Vin (ac)

Vref (e.g. 1V)

Detector measures output power from a variable gain amplifier or power amplifier Measured result is compared to a setpoint value Error amplifier/Integrator adjusts gain so that output power corresponds to setpoint Integrator capacitor/resistor set response time of loop Many of ADIs detectors have an integrated Controller Mode
76

A Practical AGC Loop using a Log Amp

Setpoint is applied to Detector VSET input Vout varies up or down to balance loop Use to set output to a fixed value (fixed VSET, variable input power) or to vary output power (variable VSET, fixed or variable input power) Set response time of loop by varying Cflt
77

Controlling Gain with a Dual RMS Detector

Dual RMS Detector can also operate in Controller Mode Detector measures and controls VGA in an analog loop Detector tries to balance input power at its two RF inputs Gain setpoint is controlled by difference in external attenuators
78

Gain vs. Input Power for Analog Gain Control Loop

Gain varies by only +/-0.25 over a 60 dB input range Excellent stability over temperature
79

RF Detectors for Analog AGC Loops


Part No.
AD8311 AD8315 AD8316 AD8318 AD8317 AD8319 AD8362 AD8364 80

RF Freq (MHz)
100 to 2500 100 to 2500

Dynamic Range (dB)


50 50 50 60 50 40 60

Setpoint Voltage Range (V)


0.4 to 1.4 0.4 to 1.4 0.4 to 1.4 0.5 to 2 0.3 to 1.6 0.3 to 1.5 0.4 to 3.5 0.25 to 3.5

Comments
Wafer-Level CSP Package

100 to 2500 1 to 8000 1 to 10000 1 to 10000 Low Freq to 2700 MHz Low Freq to 2700 MHz

Fast Responding Fast Responding Fast Responding RMS Responding Dual RMS Responding

60

ADI 2006 RF Seminar

RF Components in High Power Amplifiers

81

High Power Amplifiers

Transmitter is usually segmented into a Radio and a Power Amplifier In order to operate as close as possible to the amplifiers compression point (higher efficiency), many HPAs incorporate circuitry which reduces distortion (Linearization) Popular Linearization techniques are Feed Forward, Feedback, Digital Pre Distortion and Analog PreDistortion
82

A Simplified FFLA System Carrier Cancellation


HPA + O u tpu t

C arrier C ancella tion Lo op

D isto rtion C ance llation Loop

+
Inpu t

EA

Input signal is split onto two paths One path goes to input of High Power Amplifier (HPA) Output of amplifier comprised of amplified input signal and distortion generated within the HPA Distorted output signal fo the HPA is sampled and conveyed to one input of a differencing node Other input of the differencing node is the undistorted input signal, delayed by an interval equal to the delay of the HPA/sampled output path Output of the differencing node is distortion signal only
83

A Simplified FFLA System Distortion Cancellation


HPA + O u tpu t

C arrier C ancella tion Lo op

D isto rtion C ance llation Loop

+
Inpu t

EA

Distortion signal is amplified by a very linear error amplifier (EA) Output of EA is applied to one input of another differencing node Other input to differencing node is the distorted output of the HPA, delayed by an interval equal to the carrier cancellation sampling path and the EA path Distortion present in the output of the HPA is cancelled in this differencing node Ideal output of differencing node is amplified, undistorted carrier
84

A Practical FFLA with Adjustments 1st Loop

In the Carrier Cancellation Loop, a voltage variable attenuator (VVA) and a variable phase shifter (VPS) are put in cascade with the input to the HPA VVA and VPS are used to optimize carrier cancellation at the input to the EA Control voltages to VVA and VPS are often static voltages, set at the factory, but may be adaptively controlled1
85

A Practical FFLA with Adjustments 2nd Loop

In the Distortion Cancellation Loop, a VVA and a VPS are put in cascade with the input to the EA VVA and VPS are used to optimize distortion cancellation at the output of the FFLA system Control voltages to VVA and VPS are often static voltages, set at the factory, but may be adaptively controlled1

86

AD8302 Gain / Phase Detector


KEY SPECIFICATIONS KEY SPECIFICATIONS

Frequency Range: LF to 2.7 GHz Frequency Range: LF to 2.7 GHz Gain range: 60 dB, 30mV/dB, 00to 1.8V Gain range: 60 dB, 30mV/dB, to 1.8V Phase range: 180 deg, 10 mV/deg, 00to 1.8V Phase range: 180 deg, 10 mV/deg, to 1.8V Package: 14-TSSOP Package: 14-TSSOP

FEATURES FEATURES

Matched Log Amps for Temperature Stability Matched Log Amps for Temperature Stability Measurement and Control of Gain or VSWR Measurement and Control of Gain or VSWR

87

AD8302 Gain/Phase Detector Gain and Phase Transfer Functions

88

A Complete Feedforward Linearized Amplifier

AD8302 GPD can be used to control both loops of the FFLA AD8302 used to control VVA and VPS in Carrier Cancellation loop to control cancellation of carrier at the input to the EA AD8302 used to control VVA and VPS in Distortion Cancellation loop to control cancellation of intermodulation sidebands at FFLA Output

89

AD8340 and AD8341 Vector Modulator


KEY SPECIFICATIONS KEY SPECIFICATIONS
RF Bandwidth 0.7 1.0GHz / /1.5 2.4 GHz RF Bandwidth 0.7 1.0GHz 1.5 2.4 GHz Gain control range: -32dB to -2dB Gain control range: -32dB to -2dB Phase control range: continuous 360 Phase control range: continuous 360 Output IP3: 24dBm / /22dBm (max gain) Output IP3: 24dBm 22dBm (max gain) Output Noise: -149 dBm/-151Hz Output Noise: -149 dBm/-151Hz Package 4x4mm 24-LFCSP Package 4x4mm 24-LFCSP

FEATURES FEATURES

Amplitude and Phase Modulator inputs Amplitude and Phase Modulator inputs Modulation by Cartesian I Iand Q Modulation by Cartesian and Q Output power disable function: 40dB, 10ns Output power disable function: 40dB, 10ns

90

AD8340 Vector Modulator Gain and Phase Control

880 MHz

30 dB Gain Control Range 360 degree Phase Control Range


91

ADL5390 RF / IF Vector Multiplier


KEY SPECIFICATIONS KEY SPECIFICATIONS
Bandwidth 20MHz to 2.4GHz Bandwidth 20MHz to 2.4GHz Continuous Amplitude Control +5 to 30dB Continuous Amplitude Control +5 to 30dB Wide band 230MHz Cartesian Interface Wide band 230MHz Cartesian Interface OIP3 +25dBm OIP3 +25dBm Output P1dB +13dBm Output P1dB +13dBm Output Noise Floor 150dBm/Hz Output Noise Floor 150dBm/Hz Package 4x4mm LFCSP Package 4x4mm LFCSP

FEATURES FEATURES

Output Switch Disable 40dB, 10ns Output Switch Disable 40dB, 10ns

92

Components for PA Feedforward Linearization Vector Modulators


Part No.
AD8340 AD8341 ADL5390

RF Freq (MHz)
700 to 1000 1500 to 2400 20 to 2400

IQ Bandwidth (MHz)
230 230 230

Noise Floor (dBm/Hz)


-149 -151 -150

P1dB (dBm)
11 8.5 +13

Power Supply (mA)


130 130 130

Package
24-lead CSP 24-lead CSP 24-Lead LFCSP

Gain/Phase Detector
Part No.
AD8302

RF Freq (MHz)
>0 to 2700

Dynamic Range (dB)


60

Accuracy (dB)
0.2

Response Time (ns)


60

Package Type
14-lead TSSOP

Comments
Dual channel gain and phase detector

93

ADI 2006 RF Seminar

Chapter IV RF Components Active and Passive Mixers

RF Components Mixers
Modulated Input Sum and difference products plus LO feed-through

RF

Freq Local oscillator (LO)

LO- RF LO LO+ RF Freq

LO

Freq

Mixers translate modulated carriers from one frequency to another by multiplying the input by a square wave (a sum of odd harmonics) In addition to generating sum and difference components, mixer will also generate unwanted spurs at multiples of the LO and Carrier frequencies Mixers also add noise, IMD products and LO leakage to the output spectrum
2

Mixer Spurious Distortion Components


High Side LO Injection Low Side LO Injection

Mixer Spurious Trajectory Maps are often used to find optimum IFs for a given mixer architecture A Mixer Spur table helps to provide systems engineers with knowledge of the mfRF nfLO rejection capability of a given mixer
3

Noise Figure of a Mixer


A(t)ej(t)

USBA(t)ej((t)+(t))

SNRUSB

SNRINPUT

RF

IF

fRF + fLO

fRF fLO

LO

LSBA(t)ej((t)-(t))

SNRLSB

fRF - fLO Input signal is split between upper and lower side-bands, not necessarily with equal gain or loss. Need to consider conversion gain or loss relationship versus frequency. Noise figure can be different for upper and lower sidebands. This may result in a slight difference between conversion loss and NF for a passive mixer
4

Many Different Mixer Architectures


AD8343 AD8342 , AD8344

Gilbert Cells

Single-Ended
RF IF

Singly-Balanced
RF IF

Doubly-Balanced
RF

LO

LO

IF LO

RF+

IF+

SingleEnded Resistive FET

RF-

IF-

ADL5350
VDD VSS LO GND

DoublyBalanced Quad FET

Single-Ended Passive Mixers

Band Pass Filter is used to pass RF signal and Isolate RF port from presented IF load impedance

Band Reject Filter is used to reject RF and LO signal

Single-Ended Mixers share a common node for the RF and IF ports The RF Envelope is Modulated by the switching action of a diode of FET junction at the rate of the applied oscillator It is desirable to switch the RFIF node impedance between a short and open to provide maximum frequency conversion to the sum and difference frequencies Sharp switching also has a positive impact on inter-modulation performance Often an LO buffer is employed to ensure adequate On/Off switching of the RFIF node

Single-Ended Mixer Implementation

Desired LO frequency 750 MHz 1000 MHz 1750 MHz 2000 MHz

Recommended LO bias inductor (L4) 24 nH 18 nH 3.8 nH 2.7 nH 850 MHz 1950 MHz 6.8 nH 1.7 nH 4.7 pF 1.5 pF 4.7 nH 1.7 nH 5.6 pF 1.2 pF 8.2 nH 3.5 nH 100 pF 100 pF RF Frequency L1 C1 L2 C2 L3 C3

Step 1. Tune the LO buffer supply inductor for minimum supply current. Step 2. Tune the LO port input network for optimum return loss. Steps 3 and 4. Design the RF and IF filter networks.
7

Doubly Balanced Passive Mixers


FET Based Ring Mixer Diode Based Ring Mixer
RF

IF LO

Passive Ring Mixers are the most popular type All Passive Mixers require Balun/Transformer structures on RF and LO ports in order to achieve good performance Balanced LO and RF drive results in improved even order spurious performance and improved LO to RF and LO to IF leakage Less popular balanced passive mixers include Star Mixers and Double-Doubly Balanced Mixers
8

Simple Active Mixers Using BJTs


Poor Isolation Poor Linearity
LO
LO

IF

IF

Poor Isolation Better Linearity Poor NF

RF
RF

Better Isolation Poor Linearity Better NF


RF LO

IF+
IF

IF-

RF+

RF-

Better Isolation Better Linearity Better NF

LO

Gilbert Cell Mixers


Basic Textbook Gilbert Cell AD8344 Gilbert Cell

Several varieties. The AD8343 is very generic, requires some off-chip biasing and matching, but can be used over a broad range of frequencies. The AD8344 is optimized for 900MHz cellular applications and provides matched RF and LO ports. The AD8342 provides matched ports and is more broadband than the AD8344.
10

A Low Frequency to 500 MHz Active Mixer

3.7 dB Conversion Gain Integrated LO Drive Single Ended RL and LO Drive Differential IF Output +8 dBm IP1dB, 12 dB Noise Figure, +23 dBm IIP3
11

Active vs Passive Mixers


Pros Balanced Active Mixers SingleEnded Passive Mixers Balanced Passive Mixers
Provides Some Gain Requires no balun/transformers Good LO to RF Isolation Requires low LO drive Small and Low-Cost Good Input Linearity Low Noise Low LO drive when includes integrated LO Buffer Offers the best Input Linearity Reasonably Low Noise Good LO to RF Isolation

Cons
Tend to have higher NF than passive mixers Tend to have lower input linearity than passive mixers Requires DC Power Poor LO to RF Isolation Poor 2nd Order Distortion Performance Requires Off-Chip Diplexer Networks to separate RF and IF ports Requires Strong LO Drive unless LO Buffer is included Requires Off-Chip Baluns May be size and cost prohibitive due to required magnetics

12

High Linearity Mixers


Part No. RF Freq (MHz) dc to 500 dc to 2500 400 to 1200 200 to 3000 IF Freq (MHz) dc to 400 dc to 2500 70 to 400 LF to 3000 LO Freq (MHz) LF to 850 dc to 2500 470 to 1600 LF to 3000 Conversion Gain (dB) 4 7 4 -7 IP3 (dBm) 24 16.5 24 26 P1dB (dBm) 9 2.8 8 18 NF (dB) 11 14 11 7 Package Type 16-lead CSP 14-lead TSSOP 16-lead CSP 8-lead LFCSP

AD8342 AD8343 AD8344 ADL5350

13

Chapter V Phase Locked Loops for High Frequency Transmitters and Receivers
By Mike Curtin

PLL Basics A phase-locked loop is a feedback system combining a voltage controlled oscillator and a phase comparator so connected that the oscillator frequency (or phase) accurately tracks that of an applied frequency- or phase-modulated signal. Phase-locked loops can be used, for example, to generate stable output frequency signals from a fixed low-frequency signal. The phase locked loop can be analyzed in general as a negative feedback system with a forward gain term and a feedback term. A simple block diagram of a voltage-based negative-feedback system is shown in Figure 1.

the steady state. The usual equations for a negative-feedback system apply.
= G (s )
= j = j 2f

Forward Gain Loop Gain

= G( s) . H ( s)
= G(s) 1 + G( s) . H ( s)

Closed Loop Gain

Because of the integration in the loop, at low frequencies, the steady state gain, G(s), is high and

VO , Closed Loop Gain = VI

1 H

The components of a PLL which contribute to the loop gain are as follows: 1. 2. 3. The Phase Detector (PD) and Charge Pump (CP). The Loop Filter with a transfer function of Z(s) The Voltage Controlled Oscillator (VCO) with a sensitivity of KV/s 4. The Feedback Divider, 1/N

Figure 1. Standard Negative-Feedback Control System Model In a phase-locked loop, the error signal from the phase comparator is the difference between the input frequency or phase and that of the signal fed back. The system will force the frequency or phase error signal to zero in
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Figure 2. Basic Phase Locked Loop Model

If a linear element like a four-quadrant multiplier is used as the phase detector, and the loop filter and VCO are also analog elements, this is called an analog, or linear PLL (LPLL). If a digital phase detector (EXOR gate or J-K flip flop) is used, and everything else stays the same, the system is called a digital PLL (DPLL). If the PLL is built exclusively from digital blocks, without any passive components or linear elements, it becomes an all-digital PLL (ADPLL). Finally, with information in digital form, and the availability of sufficiently fast processing, it is also possible to develop PLLs in the software domain. The PLL function is performed by software and runs on a DSP. This is called a software PLL (SPLL). Referring to Figure 2, a system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of D. A portion of this frequency/phase signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided-down frequency is fed to one input of the error detector. The other input in this example is a fixed reference frequency/phase. The error detector compares the signals at both inputs. When the two signal inputs are equal in phase and frequency, the error will be zero and the loop is said to be in a locked condition. If we simply look at the error signal, the following equations may be developed.

e( s ) = When

FREF

FO N FO N FO = = FREF

e( s ) = 0

N FREF

In commercial PLLs, the phase detector and charge pump together form the error detector block. When F (N FREF), the error detector will output source/sink current pulses to the low pass loop filter. This smoothes the current pulses into a voltage which in turn drives the VCO. The VCO frequency will then increase or decrease as necessary, by (KV V), where KV is the VCO sensitivity in MHz/Volt and V is the change in VCO input voltage. This will continue until e(s) is zero and the loop is locked. The charge pump and VCO thus serves as an integrator, seeking to increase or decrease its output frequency to the value required so as to restore its input (from the phase detector) to zero.

Figure 3. VCO Transfer Function The overall transfer function (CLG or Closed Loop Gain) of the PLL can be expressed simply by using the CLG expression for a negative feedback system as given above.
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It is possible to break up the PLL synthesizer

FO FREF

Forward Gain 1 + Loop Gain


K d .K v .Z ( s ) Ns K d .K v .Z ( s ) s

into a number of basic building blocks. These have already been touched upon, but we will now deal with them in greater detail.

Loop Gain, GH

(i) Detector, PFD

The Phase Frequency

Forward Gain, G =

(ii) (iii)

The Reference Counter, R The Feedback Counter, N

When GH is much greater than 1, we can say that the closed loop transfer function for the PLL system is N and so FOUT = N .FREF . The loop filter is of a low-pass nature. It usually has one pole and one zero. The transient response of the loop depends on; 1) 2) 3) 4) the magnitude of the pole/zero, the charge pump magnitude, the VCO sensitivity, the feedback factor, N.

The Phase Frequency Detector or PFD The heart of a synthesizer is the phase detector or phase frequency detector. This is where the reference frequency signal is compared with the signal fed back from the VCO output and the resultant error is used to drive the loop filter and VCO. In a Digital PLL (DPLL) the phase detector or phase frequency detector is a logical element. The three most common implementations are :

(i) All of the above must be taken into account when designing the loop filter. In addition, the filter must be designed to be stable (usually a phase margin of /4 is recommended). The 3-dB cutoff frequency of the response is usually called the loop bandwidth, Bw. Large loop bandwidths result in fast transient response. However, this is not always advantageous, as we shall see later, since there is a trade off between fast transient response and reference spur attenuation. (ii) (iii)

The EXOR gate The J-K flip-flop The phase frequency (PFD)

PLL Synthesizer Basic Building Blocks


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Figure 4. Typical PFD Using D-Type Flip Flops Here we will consider only the PFD since this is the element used in the ADF41XX family of PLL synthesizers. The PFD differs from the EXOR gate and the J-K flip flop in that, its output is a function of both the frequency difference and phase difference between the two inputs. Figure 4 shows one implementation of a PFD. It basically consists of two D-type flip flops, with one Q output enabling a positive current source and the other Q output enabling a negative current source. Lets assume in this design that the D-type flip flop is positive edge triggered. There are three possible states for the combination of UP and DOWN from the D-type flip flops. The state of 11, where both outputs are high, is disabled by the AND gate (U3) back to the CLR pins on the flip flops. The state of 00 (Q1, Q2) means that both P1 and N1 are turned off and the output , OUT is essentially in a high impedance state. The state 10 means that P1 is turned on, N1 is turned off and the output is at V+. The state of 01 means P1 is turned off, N1 is turned on and the output is at V-. Lets consider how the circuit behaves if the system is out of lock and the frequency on +IN is much higher than the frequency on IN. Figure 5 is a diagram which shows the relevant waveforms. Figure 5. PFD Waveforms, Out of Frequency and Phase Lock Since the frequency on +IN is much higher than on IN, the output spends most of its time in the high state. The first rising edge on +IN sends the output high and this is maintained until the first rising edge occurs on IN. In a practical system this means that the output to the VCO is driven higher resulting in an increase in frequency at IN. This is exactly what we want. If the frequency on +IN was much lower than on IN, then we would get the opposite effect. The output at OUT would spend most of its time in the low condition. This would have the effect of driving the VCO in the negative direction and bringing the frequency at IN much closer to that at +IN. In this way, locking is achieved. Now lets look at the waveforms when the inputs are frequency locked and almost phase locked. Figure 6 is the diagram.

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Figure 6. PFD Waveforms, Out of Phase Lock, In Frequency Lock Since the phase on +IN is leading that on IN, the output is a series of positive current pulses. These pulses will tend to drive the VCO so that the IN signal become phase aligned with the +IN signal. When this occurs, if there was no delay element between U3 and the CLR inputs of U1 and U2, it would be possible for the OUT signal to be in high impedance mode, with neither positive or negative current pulses on the output. This would not be a good thing to happen. The VCO would drift until a significant phase error developed and started producing either positive or negative current pulses once again. Looked at over a relatively long period of time, the effect of this would be to have the output of the charge pump modulated by a signal that is a sub-harmonic of the PFD input reference frequency. Since this could be a low frequency signal it would not be attenuated by the loop filter and would result in very significant spurs in the VCO output spectrum. The phenomenon is known as the backlash effect and the delay element between the output of U3 and the CLR inputs of U1 and U2 ensures that it does not happen. With the delay element, even when the +IN and IN are perfectly phase-aligned, there will still be a current pulse generated at the charge pump output. The duration of this delay is equal to the delay inserted at the output of U3 and is known as the anti-backlash pulse width.
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The Reference Counter In the classical Integer-N synthesizer, the resolution of the output frequency is determined by the reference frequency applied to the Phase Detector. So, for example, if 200kHz spacing is required (as in GSM phones), then the reference frequency must be 200kHz. However, getting a stable 200kHz frequency source is not easy and it makes more sense to take a good crystal-based high frequency source and divide it down. So, we could have a 10MHz Frequency Reference, divide this down by 50 and have the desired frequency spacing. This is shown in the diagram in Figure 7.

Figure 7. Using a Reference Counter in a PLL Synthesizer

The Feedback Counter, N The N counter or N divider, as it is sometimes called, is the programmable element that sets the output frequency in the PLL. In fact, the N counter has become quite complex over the years . Instead of being a straightforward N counter it has evolved to include a prescaler which can have a dual modulus. If we confine ourselves to the basic divide-byN structure to feed back to the phase detector, we can run into problems if very high

frequency outputs are required. For example, lets assume that a 900MHz output is required with 10kHz spacing. We can use a 10MHz Reference Frequency, and set the R-Divider at 1000. Then, the N-value in the feedback would need to be around 90,000. This would mean at least a 17-bit counter. This counter would have to be capable of dealing with an input frequency of 900MHz. It makes sense to precede the programmable counter with a fixed counter element to bring the very high input frequency down to a range at which standard CMOS will operate. This is called the prescaler and is shown in Figure 8. 3. 2. 1. The output signal of both counters is HIGH if the counters have not timed out. When the B counter times out, its output goes LOW and it immediately loads both counters to their preset values. The value loaded to the B counter must always be greater than that loaded to the A counter.

Figure 8. Basic Prescaler Figure 9. The Dual-Modulus Prescaler However, using a standard prescaler introduces other complications. The system resolution is now degraded (F1 x P). The dualmodulus prescaler addresses this issue. The dual-modulus prescaler, shown below in Figure 9, gives the advantages of the standard prescaler without any loss in system resolution. A dual-modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. By using the dual-modulus prescaler with an A and B counter one can still maintain output resolution of F1. However, the following conditions must be met:
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Assume that the B counter has just timed out and both counters have been reloaded with the values A and B. Lets find the number of VCO cycles necessary to get to the same state again. As long as the A counter has not timed out, the prescaler is dividing down by P+1. So, both the A and B counters will count down by 1 every time the prescaler counts (P + 1) VCO cycles. This means the A counter will time out after {(P + 1) A)} VCO cycles. At this point the prescaler is switched to (divide-byP). It is also possible to say that at this time

the B counter still has (B - A) cycles to go before it times out. How long will it take to do this: {(B - A) P}. The system is now back to the initial condition where we started. The total number of VCO cycles needed for this to happen is : {(P + 1) A } + {(B - A) P} = AP + A + BP - AP = {(P B) + A} When using a dual modulus prescaler, it is important to consider the lowest and highest value of N possible . What we really want here is the range over which it is possible to change N is discrete integer steps .Consider our expression for N: N = BP + A. To ensure a continuous integer spacing for N, A must be in the range 0 to (P - 1). Then, every time B is incremented there is enough resolution to fill in the all the integer values. As we have already said for the dual modulus prescaler, B must be greater than or equal to A for the dual modulus prescaler to work. From these two conditions, we can say that the smallest division ratio possible while being able to increment in discrete integer steps is: NMIN = (Bmin x P) + Amin = ((P-1) x P ) + 0 =P P The highest value of N is given by NMAX = (Bmax x P) + Amax In this case Amax and Bmax are simply
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2

determined by the size of the A and B counters. Now, lets take a practical example using the ADF4111. Lets assume the prescaler is programmed to 32/33. A counter: 6 bits means A can be 26 - 1 = 63 B counter : 13 bits means B can be 213 - 1 = 8191 NMIN NMAX = P2 - P = 992 = (Bmax x P) + Amax = (8191 x 32) + 63 = 262175

Fractional-N Synthesizers Many of the emerging wireless communication systems have a need for faster switching and lower phase noise in the Local Oscillator. This is particularly true in GSM systems. We have seen that Integer-N synthesizers require a PFD frequency which is equal to the channel spacing. This can be quite low and thus necessitates a high N. This high N produces a phase noise that is proportionately high. The low PFD frequency in turn means a low loop bandwidth which limits the PLL lock time. If we could divide by a fraction in the feedback, then it would be possible to use a higher reference frequency and still achieve the desired channel spacing. This lower number would also mean lower phase noise. So, in theory, fractional-N

synthesis offer a means of improving both phase noise and lock time in PLLs. If fact it is possible to implement division by a fraction over a long period of time by alternately dividing by two integers (divide by 2.5 can be achieved by dividing successively by 2 and 3). So, how do we decide to divide by X or (X+1) (assuming that our fractional number is between these two values)? Well, we can take the fractional part of the number and allow it to accumulate at the Reference Frequency rate.

This is the essence of fractional-N synthesis. It means that the PFD frequency can be larger than the RF channel resolution. In relation to the GSM-900 example, it may be instructive to examine how the fractional-N approach handles the generation of 900-MHz output signals with 200-kHz channel resolution. If a modulus M of 10 is available, FPFD can be set to 2 MHz. N is programmed to 450, f is 0, and M is 10. To tune to 900.2 MHz RFOUT, NAVERAGE must be 450.1, N is programmed to 450, f is 1, and M is 10. To achieve this, the N-divider is toggled under the control of the interpolator between N and N+1 and the average taken. What effectively occurs is that the N-divider divides by 450 nine times, and then divides by 451 once every 10 PFD cycles. The average over the 10 cycles of 450.1 is taken as NAVERAGE, which is fed to the PFD. However, much complex circuitry is needed to implement this. Interpolators can be implemented using the overflow bit of an accumulator. Alternatively, sigma-delta modulators are often employed for this task due to their averaging function and noise-shaping characteristics. In this case, every time an N value is presented to the PFD, it has been modulated by the sigma-delta modulator. This introduces spurs to the loop at FPFD/M.

Figure 10. The Fractional-N Synthesizer Since it is based on integer-N, the fractional-N PLL inherits many of the building blocks of its predecessor. The PFD, charge pump, loop filter, and VCO all work in the same way on both platforms. The N-divider is different, however. In a fractional-N PLL, the N-divider is broken up into the integer divider (N) and a modulus-M interpolator (M), which acts as the fraction function by toggling the N-divider. The interpolator is programmed with some value (f). The average division factor is now N + f/M where: 0<f<M (N + f/M) = RFOUT / FPFD

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IMPORTANT SPECIFICATIONS IN PLL SYNTHESIZERS Noise In any oscillator design, frequency stability is of critical importance. In general, it is possible to separate stability into long-term stability and short-term stability. Long-term frequency stability is concerned with how the output signal varies over a long period of time (this can be hours, days or months). It is usually specified in Df/f for a given period of time and can be linear or exponential in nature. Short-term stability, on the other hand, is concerned with variations that occur over a period of seconds or less. These variations can be random or periodic. We can use a spectrum analyzer to look at short-term stability of a signal. Figure 1 shows a typical spectrum.

The random noise fluctuation shown in Figure 11 is called phase noise. It can be due to thermal noise, shot noise or flicker noise in active and passive devices.

Phase Noise In Voltage Controlled Oscillators Before we look at phase noise in a PLL system, it is worth considering the phase noise in a VCO. An ideal VCO would have no phase noise. If we looked at the output on a spectrum analyzer, we would see only one spectral line. In practice of course, this is not the case. There will be jitter on the output and, looked at on a spectrum analyzer, this will give rise to what we call phase noise. In terms of understanding phase noise it is useful to consider a phasor representation. Figure 2 shows the effect of superimposed noise voltages on a carrier signal. We call this effect phase noise.

Figure 11. Short-term stability in oscillators The discrete spurious components are nonrandom in nature and can be the result of known clock frequencies in the signal source, power line interference or mixer products. Figure 12. Phasor Representation of Phase Noise A signal of angular velocity, v0, and peak amplitude VSpk is shown. Superimposed on
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this is an error signal of angular velocity, vm. Durms represents the rms value of the phase fluctuations and is expressed in rms degress . In many radio systems there is an overall integrated phase error specification which must be met. This overall phase error is made up of the PLL phase error, the modulator phase error and the phase error due to base band components. In GSM, for example, the total allowed is 5 degrees rms. It is important that each of the contributing components are minimized. GSM designers like to keep the PLL phase error below 1 degree rms in the 200kHz frequency band around the carrier.

For Leesons equation to be valid, the following must be true: fm, the offset frequency from the carrier is greater than the 1/f flicker corner frequency; the noise factor at the operating power level is known; the device operation is linear; Q includes the effects of component losses, device loading and buffer loading; A single resonator is used in the oscillator.

Leesons Equation Leeson developed an equation to describe the different noise components in a VCO. Figure 13. Phase Noise in a VCO vs.

LPM
Where

FkT 1 10 log 2 A 8QL

f O Frequency Offset Leesons equation only applies between the f m 1/f flicker noise frequency (f1) and a frequency
2

past which amplified white noise dominates (f2). This is shown in Figure 3. Typically, f1 is less than 1kHz and should be as low as possible. The frequency f2 is in the region of a few MHz. High-performance oscillators require devices specially selected for low 1/f
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LPM is single-sideband phase noise density (dBc/Hz) F is the device noise factor at operating power level A (linear) k is Boltzmanns constant, 1.38 x 10 T is temperature (K) A is oscillator output power (W) QL is loaded Q (dimensionless) fO is the oscillator carrier frequency fm is the frequency offset from the carrier ((J/K))

transition frequency. Some guidelines to minimizing the phase noise in VCOs are: 1. Keep the tuning voltage of the varactor sufficiently high (typically between 3 and 3.8V) 2.
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Use filtering on the dc voltage supply.

3.

Keep the inductor Q as high as possible. Typical off-the-shelf coils provide a Q of between 50 and 60.
Closed Loop Gain = G 1 + GH

4.

Choose an active device that has minimal noise figure as well as low flicker frequency. The flicker noise can be reduced by the use of feedback elements

G =
H =

K d . K v . Z (s) s
1 N

5.

Most active device exhibit a bowlshaped Noise Figue vs Bias Current curve. Use this information to choose the optimal operating bias current for the device.

K d . K v . Z ( s) s Closed Loop Gain = K . K v . Z ( s) 1+ d N .s

The term, SREF, is the noise that appears on the reference input to the phase detector. It is dependent on the reference divider circuitry and the spectral purity of the main reference signal. The term, SN, is the noise due to the feedback divider appearing at the frequency input to the PD. The term, SCP, is the noise due to the phase detector implementation. The last term, SVCO, is the phase noise of the VCO as described by equations developed earlier . The overall phase noise performance at the output is dependent on each of the terms described above. All the effects at the output are added in an rms fashion to give the total noise of the system. It is possible to write the following:

6. 7.

Maximize the average power at the tank circuit output. When buffering the VCO, use devices with the lowest possible Noise Figure.

Closing The Loop We have looked at phase noise in a freerunning VCO and considered how it can be minimized. Now, we will look at closing the loop and consider what effect this will have on phase noise.

STOT = X 2 + Y 2 + Z 2
Figure 14. PLL - Phase Noise contributors Figure 14 shows the main phase noise contributors in a PLL as well as the system transfer function equations. The system may be described by the following equations. STOT2 is the total phase noise power at the output X2 is the noise power at the output due to SN and SREF. Y2 is the noise power at the output due to SCP
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Z2 is the noise power at the output due to SVCO. It can be clearly seen that the noise terms at the PD inputs, SREF and SN, will be operated on in the same fashion as FREF and will be multiplied by the closed loop gain of the system.
2

G, the forward loop gain of the closed loop response, is usually a low pass function and it is very large at low frequencies and small at high frequencies. H is a constant, 1/N. The bottom term of the above expression is therefore low pass. Therefore SVCO is actually high pass filtered by the closed loop. A similar description of the noise contributors in a PLL/VCO is described in Reference 1. Recall that the closed loop response is a low pass filter with a 3 dB cutoff frequency, Bw, denoted the loop bandwidth. For frequency offsets at the output less than Bw, the dominant terms in the output phase noise response are X and Y, the noise terms due to reference noise, N counter noise and charge pump noise. Keeping SN and SREF to a minimum, keeping Kd large and keeping N small will thus minimize the phase noise inside the loop bandwidth, Bw. Of course, keeping N small will not always be possible since this is what programs the output frequency. For frequency offsets much greater than Bw, the dominant noise term is that due to the VCO, SVCO. This is due to the high pass filtering of the VCO phase noise by the loop. A small value of Bw would be desirable as it would minimize the total integrated output noise (phase error). However a small Bw results in a slow transient response and increased contribution from the VCO phase noise inside the loop bandwidth. The loop bandwidth calculation therefore must trade off transient response versus total output integrated phase noise.

X = S REF + S N
2

G . 1 + GH

At low frequencies, inside the loop bandwidth,

GH >> 1 and

X = ( S REF + S N ) . N
2

At high frequencies, outside the loop bandwidth,

G << 1 and

X2 0

The contribution to the overall output noise due to the phase detector noise, SCP, can be calculated by referencing SCP back to the input of the PFD. The equivalent noise at the PD input is SCP/Kd. This is then multiplied by the Closed Loop Gain. So:
2

= S CP

1 . K d

2 G . 1 + GH

Finally, the contribution of the VCO noise, SVCO, to the output phase noise is calculated in a similar manner. The forward gain this time is simply 1. Therefore the final output noise term can be described as:

Z2

1 2 = SVCO . 1 + GH

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To show the effect of closing the loop in a PLL, it is possible to overlay the output of a free-running VCO with the output of a VCO as part of a PLL. This is shown in Figure 15 below. Note that the in-band noise of the PLL has been attenuated compared to the freerunning VCO.

With the Spectrum Analyzer we can measure the one-sided spectral density of phase fluctuations per unit bandwidth. VCO phase noise is best described in the frequency domain where the spectral density is characterized by measuring the noise sidebands on either side of the output signal center frequency. Single sideband phase noise is specified in decibels relative to the carrier (dBc/Hz) at a given frequency offset from the carrier. The following equation describes this SSB phase noise.

Figure 15. Phase Noise on a Free-Running VCO vs. VCO in a PLL

P SC ( f ) = 10 log S , dBc / Hz P SSB

Phase Noise Measurement One of the most common ways of measuring phase noise is with a high frequency spectrum analyzer. Figure 16 is a representation of what would be seen. Figure 7. Measuring Phase Noise with a Spectrum Analyzer The 10 MHz, 0dBm reference oscillator is available on the spectrum analyzer rear panel connector and it has excellent phase noise performance. The R divider, N divider and the phase detector are part of ADF4112 frequency synthesizer. These dividers are Figure 16. Phase Noise Definition programmed serially under the control of a PC. The frequency and phase noise
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performance are observed on the spectrum analyzer.

in a 1 Hz bandwidth. This value is made up of the following:

(i).

Relative power in dBc between the carrier and the sideband noise at 1kHz offset

(ii). The spectrum analyzer displays the power for a certain resolution bandwidth (RBW). In the plot, a 10Hz RBW is used. To represent this power in a 1Hz bandwidth, 10log(RBW) must be Figure 18. Typical Spectrum Analyzer Output Figure 18 illustrates a typical phase noise plot of a PLL synthesizer using an ADF4112 PLL with a Murata VCO, MQE520-1880. The frequency and phase noise were measured in a 5 kHz span. The reference frequency used was FREF = 200 kHz (R=50) and the output frequency was 1880 MHz (N=9400) . If this was an ideal-world PLL synthesizer then a single discrete tone would be displayed along with the spectrum analyzers noise floor. What is displayed here is the tone and the phase noise due to the loop components. The loop filter values were chosen to give a loop bandwidth of approximately 20 kHz. The flat part of the phase noise for frequency offsets less than the loop bandwidth is actually the phase noise as described by X2 and Y2 in the section Closing The Loop for cases where f is inside the loop bandwidth. It is specified at a 1 kHz offset. The value measured was 85.86 dBc/Hz. This is the phase noise power Phase noise measurement with the HP 8561E can be made quickly by using the marker noise function, MKR NOISE. This function takes into account the above three factors and displays the phase noise in dBc/Hz. The phase noise measurement above is the total output phase noise at the VCO output. If we want to estimate the contribution of the PLL device (noise due to phase detector, R&N dividers and the phase detector gain constant), we must divide our result by N2 (or subtract 20*logN from the above result). This gives a phase noise floor of {-85.86 -20*log(9400)} = -165.3 dBc/ Hz. subtracted from the value in (i). (iii) A correction factor which takes into account the implementation of the RBW, the log display mode and detector characteristic must be added to the result in (ii).

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When the PLL is in lock, the phase and Normalized Phase Noise Floor The PLL synthesizer Normalized Phase Noise Floor (or Figure of Merit, as it is sometimes known) in the phase noise normalized for a 1 Hz PFD frequency and is defined by the following equation: frequency inputs to the PFD (fREF and fN) are essentially equal. In theory, one would expect that there would be no output from the PFD, in this case. However, this can create problems and so the PFD is designed so that, in the locked condition, the current pulses from the 20. PNSYNTH is the Normalized Phase Noise Floor PNTOT is the measured phase noise at the PLL output FPFD is the PFD frequency N is the value in the N counter The Normalized Phase Noise Floor is a quick and convenient way of comparing the noise performance of PLL synthesizers. Figure 20. Output current pulses from the Reference Spurs In an integer-N PLL (where the output frequency is an integer multiple of the reference input), reference spurs are caused by the fact that there is continuous update of the charge pump output at the reference frequency rate. Lets once again consider the basic model for the PLL. This is shown again in Figure 19, below. These pulses have a very narrow width but the fact that they exist means that the dc voltage driving the VCO is modulated by a signal of frequency fREF. This produces what we call Reference Spurs in the RF output and these will occur at offset frequencies which are integer multiples of fREF. It is possible to detect reference spurs using a spectrum analyzer. Simply increase the span to greater than twice the reference frequency. A typical plot is shown in Figure 11. In this case the reference frequency is 200kHz and the Figure 19. Basic PLL Model diagram clearly shows reference spurs at 6 200kHz from the RF output of 1880MHz. The level of these spurs is 90dB. If we increased the span to greater than four times the
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PN SYNTH

= PN TOT 10 log FPFD 20 log N charge pump will typically look like Figure

PFD Charge Pump

reference frequency then we would also see the spurs at (2 x fREF).

Wireless Handsets, Pagers, CATV Systems, Clock Recovery and Generation Systems. A good example of a PLL application is a GSM Handset or Basestation. Figure 22 shows the receive section of a GSM Basestation.

Figure 21. Output Spectrum showing Reference Spurs Figure 22. Signal Chain For GSM Base Station Receiver

Charge Pump Leakage Current


When the CP output from the synthesizer is programmed to the high impedance state, there should, in theory, be no leakage current flowing. In practice, of course, this is not the case and there are applications where the level of leakage current will have an impact on overall system performance. It is important to note that leakage current has a direct bearing on reference (PFD) spur level at the output of the PLL. In the GSM system, there are 124 channels (8 users per channel) of 200kHz width in the RF Band. The total bandwidth occupied is 24.8MHz, which must be scanned for activity. The handset has a TX range of 880MHz to 915MHz and an RX range of 925MHz to 960MHz. Conversely, the base station has a TX range of 925MHz to 960 MHz and an RX range of 880MHz to 915MHz. For our example lets just consider the base station transmit and receive sections. The frequency PLL Applications: Up-Conversion and Down-Conversion in Base Stations The Phase Locked Loop allows stable high frequencies to be generated from a lowfrequency reference. Any system that requires stable high frequency tuning can benefit from the PLL technique. The stable high frequency generated by the PLL is commonly known as a Local Oscillator (LO) and these are used in many systems like Wireless Basestations,
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bands for GSM900 and DCS1800 Base Station Systems are shown in Table 1. Table 2 shows the channel numbers for the carrier frequencies (RF channels) within the frequency bands of Table 1. Fl (n) is the center frequency of the RF channel in the lower band (RX) and Fu(n) is the corresponding frequency in the upper band (TX).

TX P-GSM900 DCS1800 E-GSM900 935 960MHz 1805-1880MHz 925-960MHz 890-915MHz 1710-1785MHz 880-915MHz

RX

Table 1. Frequency Bands for GSM900 and DCS1800 Base Station Systems

RX PGSM900 EGSM900 Fl(n) = 890 + 0.2 x (n) Fl(n) = 890 + 0.2 x (n) Fl(n) = 890 + 0.2 x (n-1024) DCS1800 Fl(n) = 1710.2 + 0.2 x (n 512) 1 n 124 0 n 124 975 n 1023 512 n 885

TX Fu(n) = Fl(n) + 45 Fu(n) = Fl(n) +45

Fu(n) = Fl(n) + 95

Table 2. Channel Numbering for GSM900 and DCS1800 Base Station Systems The 900MHz RF input is filtered, amplified and applied to the first stage mixer. The other mixer input is driven from a tuned Local Oscillator (LO). This must scan the input frequency range to search for activity on any of the channels. The actual implementation of the LO is by means of the PLL technique already described. If the 1st Intermediate Frequency (IF) stage is centered at 240MHz, then the LO must have a range of 640MHz to 675MHz in order to cover the RF Input Band. When a 200kHz Reference Frequency is chosen, then it will be possible to sequence the VCO output through the full frequency range in steps of 200kHz. For example, when an output frequency of 650MHz is desired then N will have a value of 3250. This 650MHz LO will effectively check the 890MHz RF channel (FRF FLO = FIF or FRF = FLO + FIF) When N is incremented to 3251, the LO frequency will
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now be 650.2MHz and the RF channel checked will be 890.2MHz. This is shown graphically in Figure 23.

Figure 23. Tuning Frequencies For GSM Base Station Receiver

It is worth noting that, in addition to the tunable RF LO, the receiver section also uses a fixed IF (in the example shown this is 240MHz). Even though frequency tuning is not needed on this IF, the PLL technique is still used. The reason for this is that it is an affordable way of using the stable system reference frequency to produce the high frequency IF signal. Several synthesizers manufacturers recognize this fact by offering dual versions of the devices: one operating at the high RF frequency (>800MHz) and one operating at the lower IF frequency (500MHz or less). On the transmit side of the GSM system, similar requirements exist. However, it is

more common to go directly from Base-band to the final RF in the Transmit Section and this means that the typical TX VCO for a base station has a range of 925MHz 960MHz (RF Band for the Transmit Section). Circuit Example Figure 24 shows an actual implementation of the local oscillator for the transmit section of a GSM base station. We are assuming direct Base Band to RF up-conversion . This circuit uses the ADF4111 PLL Frequency Synthesizer from ADI and the VCO190-902T Voltage Controlled Oscillator from Sirenza Corporation.

Figure 24. Transmitter Local Oscillator for GSM The reference input signal is applied to the circuit at FREFIN and is terminated in 50V. This reference input frequency is typically 13MHz in a GSM system. In order to have a
V-18

channel spacing of 200kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference divider of the ADF4111. The ADF4111 is an integer-N PLL frequency synthesizer, capable of operating up to an RF frequency of 1.2GHz. In this integer-N type of synthesizer, N can be programmed from 96 to 262,000 in discrete integer steps. In the case of the handset transmitter, where we need an output range of 880MHz to 915MHz., and where the internal reference frequency is 200kHz, the desired N values will range from 4400 to 4575. The charge pump output of the ADF4111 (pin 2) drives the loop filter. This filter is a 1st Order lag lead type and it represented by Z(s) in the block diagram of Figure 2. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. Other PLL system specifications are given below: Kd = 5mA Kv = 8.66MHz/Volt Loop Bandwidth = 12kHz. FREF = 200kHz N = 4500 Extra Reference Spur Attenuation of 10dB All of these specifications are needed and used to come up with the loop filter components values shown in Figure 24. The loop filter output drives the VCO which, in turn, is fed back to the RF input of the PLL

synthesizer and also drives the RF Output terminal. A T-circuit configuration with 18 ohm resistors is used to provide 50 ohm matching between the VCO output, the RF output and the RFIN terminal of the ADF4111. In a PLL system, it is important to know when the system is in lock. In Figure 6, this is accomplished by using the MUXOUT signal from the ADF4111. The MUXOUT pin can be programmed to monitor various internal signal in the synthesizer. One of these is the LD or lock detect signal. When MUXOUT is chosen to select Lock Detect, it can be used in the system to trigger the output power amplifier, for example. The ADF4111 uses a simple 4-wire serial interface to communicate with the system controller. The reference counter, the N counter and various other on-chip functions are programmed via this interface. Receiver Sensitivity Receiver sensitivity is the ability of the receiver to respond to a weak signal. Digital receivers use maximum bit error rate (BER) at a certain RF level to specify performance. In general, it is possible to say that device gains, noise figures, image noise and LO wideband noise all combine to produce an overall equivalent noise figure. This is then used to calculate the overall receiver sensitivity. Wideband noise in the LO can elevate the IF noise level and thus degrade the overall noise factor. For example, wideband phase noise at
V-19

FLO + FIF will produce noise products at FIF. This directly impacts the receiver sensitivity. This wideband phase noise is primarily dependant on the VCO phase noise. Close in phase noise in the LO will also impact sensitivity. Obviously, any noise close to FLO will produce noise products close to FIF and impact sensitivity directly. Receiver Selectivity Receiver selectivity describes the tendency of a receiver to respond to channels adjacent to the desired reception channel. Adjacent Channel Interference (ACI) is a commonly used term in wireless systems which is also used to describe this phenomenon. When considering the LO section, the reference spurs are of particular importance with regard to selectivity. Figure 25 is an attempt to illustrate how a spurious signal at the LO, occurring at the channel spacing, can transform energy from an adjacent radio channel directly onto FIF. This is of particular concern if the desired received signal is weak and the unwanted adjacent channel is strong, which can often be the case. So, the lower the reference spurs in the PLL, the better it will be for system selectivity.

Open Loop Modulation Open Loop Modulation is a simple and inexpensive way of implementing FM. It also allows higher data rates than modulating in closed loop mode. For FM modulation, a closed loop method works fine but the data rate is limited by the loop bandwidth. A system which uses open loop modulation is the European cordless telephone system, DECT. The output carrier frequencies are in a range of 1.77GHz to 1.90GHz and the data rate is high; 1.152Mbps. A block diagram of open loop modulation is shown in Figure 26. The principle of operation is as follows: The loop is closed to lock the RF output, fOUT = N. fREF. The modulating signal is turned on and initially the modulation signal is simply the dc mean of the modulation. The loop is then opened, by putting the CP output of the synthesizer into high-impedance mode and the modulation data is fed to the Gaussian filter. The modulating voltage then appears at the VCO where it is multiplied by KV. When the data burst finishes, the loop is returned to the closed loop mode of operation.

Figure 26. Block Diagram of Open Loop Figure 25. Adjacent Channel Interference Modulation.
V-20

As the VCO usually has a high sensitivity (typical figures are between 20 and 80MHz/volt) any small voltage drift before the VCO will cause the output carrier frequency to drift. This voltage drift and hence the system frequency drift is directly dependant on the leakage current of the charge pump, CP, when in the high impedance state. This leakage will cause the loop capacitor to charge or discharge depending on the polarity of the leakage current. For example, a leakage current of 1nA would cause the voltage on the loop capacitor (1000pF for example) to charge by dV/dT. This, in turn, would cause the VCO to drift. So, if the loop is open for 1ms and the KV of the VCO is 50MHz/Volt, then the frequency drift caused by 1nA leakage into a 1000pF loop capacitor would be 50kHz. In fact the DECT bursts are generally shorter (0.5ms) and so the drift will be even less in practice for the loop capacitance and leakage current used in our example. However, the example does serve to illustrate the importance of Charge Pump Leakage in this type of application

lengthy measurements. Using ADIsimPLL both streamlines and improves upon the traditional design process. ADIsimPLL is extremely user friendly and easy to use. Starting with the new PLL wizard a designer constructs a PLL by specifying the frequency requirements of the PLL, selecting an integer_N or Fractional-N implementation and then choosing from a library of PLL chips, library or custom VCO data, and a loop filter from a range of topologies. The wizard designs a loop filter and sets up the simulation program to display key parameters including phase noise, reference spurs, lock time, lock detect performance and others. ADIsimPLL operates with spreadsheet-like simplicity and interactivity. The full range of design parameters such as loop bandwidth, phase margin, VCO sensitivity and component values can be altered with real-time update of the simulation results. This allows the user to easily tailor and optimise the design for their specific requirements. Varying the bandwidth, for example, enables the user to observe the trade-off between lock time and phase noise in real-time and with bench-measurement accuracy. ADIsimPLL includes accurate models for phase noise, enabling reliable prediction of the synthesizer closed-loop phase noise. Users report excellent correlation between simulation and measurement. ADIsimPLL also accurately simulates locking behaviour in the PLL, including the most significant non-linear effects. Unlike simple
V-21

ADIsimPLL Traditionally, PLL Synthesizer design relied on published application notes to assist in the design of the PLL loop filter. It was necessary to build prototype circuits to determine key performance parameters such as lock time, phase noise and reference spurious levels. Optimisation was limited to tweaking component values on the bench and repeating

linear simulators based on Laplace transform solutions, ADIsimPLL includes the effects of phase detector cycle slipping, charge pump saturation, curvature in the VCO tuning law and the sampling nature of the phasefrequency detector. As well as providing accurate simulation of frequency transients, giving detailed lock-time predictions for frequency and phase lock, ADIsimPLL also simulates the lock detect circuit. For the first time, designers can easily predict how the lock detect circuit will perform without having to resort to measurements. The simulation engine in ADIsimPLL is fast, with all results typically updating instantaneously, even transient simulations. As well as providing an interactive environment that enables the design to be easily optimised, it also encourages the designer to explore the wide range of design options and parameters available. Contrary to the traditional methods where to design, build and then measure parameters takes days, ADIsimPLL enables the user to change the PLL circuit design and observe instantly the performance changes. ADIsimPLL allows the designer to work at a higher level and directly modify derived parameters such as the loop bandwidth, phase margin, pole locations, and the effects of the changes on performance are shown instantly (and without burning fingers with a soldering iron!). If need be the designer can work directly at the component level and observe the effects of

varying individual component values. ADIsimPLL Version 2 includes many enhancements including: - the new PLL wizard now includes a shortform selector guide for choosing the PLL chip, displaying short-form data for all chips, with inbuilt links to the product pages on the Analog Devices website. - Similar short-form selector guides are available for choosing the VCO device, and these contain links to detailed device data on vendors websites. The data in the selector guides can be sorted by any parameter. - The chip-programming assistant enables rapid calculation of programming register values to set the chip any specified frequency. This is also great for checking channels that cannot be reached due to prescaler restrictions - The range of loop filters has been expanded to include a 4-pole passive filter and a noninverting active filter. As with all loop filter designs in ADIsimPLL, these models accurately include the thermal noise from resistors, the op-amp voltage and current noise, as well as predicting reference spurs resulting from the op-amp bias current. - Phase jitter results can now be displayed in degrees, seconds or Error Vector Magnitude (EVM) - It is now possible to simulate the power-up frequency transient. - Support has been included for the new Analog Devices PLL chips with integrated VCOs

V-22

With traditional design techniques, the evaluation of new devices requires construction, measurement and hand optimization of a prototype, which is a significant barrier to change and is often a key reason for the continual use of old PLL chips. ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. ADIsimPLL is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed in ADIsimPLL include

all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- tomarket. With ADIsimPLL you will get most PLL Synthesizer designs right first time - even the tough ones! Download your ADIsimPLL Software from http://www.analog.com/pll

V-23

The ADI Synthesizer Family

Figure 27. Block Diagram for the ADF4106 Below is a listing of the current ADI synthesizer family. In includes both single and dual integer-N and fractional-N devices. It also includes the new integrated VCO family (ADF4360 family). ADF4110 Family ADF4001 ADF4110 ADF4111 ADF4112 ADF4113 ADF4106 ADF4107 ADF4007 Single Proprietary Integer-N Synthesizers This single synthesizer operates up to 200 MHz This single synthesizer operates up to 550 MHz This single synthesizer operates up to 1.2 GHz This single synthesizer operates up to 3.0 GHz. This single synthesizer operates up to 3.8 GHz. This single synthesizer operates up to 6.0 GHz This single synthesizer operates up to 7.0 GHz This single synthesizer operates up to 7.5 GHz

ADF4116 Family ADF4116 ADF4117

Single Second Source Integer-N Synthesizers This single synthesizer operates up to 550 MHz. It is a second source to the LMX2306. This single synthesizer operates up to 1.2 GHz. It is a second source to the LMX2316 .

V-24

ADF4118

This single synthesizer operates up to 3.0 GHz. It is a second source to the LMX2326.

ADF4212L ADF4212L

Dual Proprietary Integer-N Synthesizer This dual synthesizer operates up to 510 MHz/2.4 GHz

ADF4218L ADF4218L

Dual Second Source Integer-N Synthesizer This dual synthesizer operates up to 510 MHz/ 3.0 GHz. It is a second source to the LMX2330L from National Semiconductor.

ADF4153 Family ADF4153 ADF4154 ADF4156

Single Proprietary Fractional-N Synthesizer This single synthesizer operates up to 4.0 GHz (16-pin package). This single synthesizer operates up to 4.0 GHz (16-pin package). This single synthesizer operates up to 6.4 GHz (16-pin package).

ADF4252 ADF4252

Dual Proprietary Fractional-N/Integer-N Synthesizer This dual synthesizer operates up to 550MHz (Integer)/3.0 GHz (Fractional).

ADF4360 Family ADF4360-0 ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-7 ADF4360-8

Single Proprietary Integrated PLL Synthesizer and VCO This single synthesizer operates from 2400 MHz to 2725 MHz This single synthesizer operates from 2050 MHz to 2450 MHz This single synthesizer operates from 1850 MHz to 2150 MHz This single synthesizer operates from 1600 MHz to 1950 MHz This single synthesizer operates from 1450 MHz to 1750 MHz This single synthesizer operates from 1200 MHz to 1400 MHz This single synthesizer operates from 1050 MHz to 1250 MHz This single synthesizer operates from 350 MHz to 1800 MHz This single synthesizer operates from 65 MHz to 400 MHz

References 1. 2. Mini-Circuits Corporation, "VCO Designers Handbook", 1996. L.W. Couch, "Digital and Analog Communications Systems" Macmillan Publishing Company, New York, 1990. 3. P. Vizmuller, "RF Design Guide", Artech House, 1995.
V-25

4.

R.L. Best, "Phase Locked Loops: Design, Simulation and Applications", 3rd Edition, McGraw Hill, 1997.

5.

Brendan Daly, Comparing Integer-N And Fractional-N Synthesizers, Microwaves & RF, September 2001.

6.

D.E. Fague, Open Loop Modulation of VCOs for Cordless Telecommunications, RF Design, July 1994

V-26

ADI 2006 RF Seminar

Chapter VI A Detailed Look at Wireless Signal Chain Architectures

Receiver Architectures
Receivers are designed to detect and demodulate the desired signal and remove unwanted blockers Receiver must also get rid of unwanted signals that it generates (e.g. mixer spurs) Receiver uses variable gain and power detection Most Receivers will have some form of Automatic Gain Control Diversity: Some Receiver Systems have two separate Receive Paths (Antennas separated by a quarter wavelength). A Diversity Receiver will either pick the strongest signal or intelligently combine both signals to increase signal power

Blockers a closer look


Power (dBm) Transmit Signal Out-of-Band Blocker

In-Band Blockers

A
DC

Desired Signal

Freq
Tx Band Rx Band

Blockers can be orders of magnitude larger than the desired signal Large Blockers can jam a receiver Blockers can inter-modulate with each other and produce IMD products right at the frequency of the desired signal Some Blockers can be filtered (e.g. out-of-band) but others must be tolerated.
3

A Superheterodyne (Single Conversion) IF Sampling Receiver


Band/Image Filter Channel Select Filter

MIXER

I G H
IF SAMPLING ADC

VGA

DUPLEXER

RSSI /AGC
TRANSMITTER

Mixes the received signal from RF down to a single IF Uses SAW filters to remove blockers and unwanted mixing components Detects signal power and implements AGC at the IF Reduces number of down-conversions by sampling the spectrum at an Intermediate Frequency but requires a high performance ADC Is the most popular architecture in non-cellular applications
4

IF Sampling Signal Flow


Power (dBm) Transmit Signal Out-of-Band Blocker Power (dBm) In-Band Blockers

A
DC
Power (dBm)

F
Desired Signal

Channel Select Filter

Freq
D DC Tx Band Rx Band
Out-of-Band Blocker AGC & Nqyuist Filter Power (dBm)

Freq

In-Band Blockers

SAMPLING CLOCK

Transmit Signal Desired Signal

H
Freq
D DC
FIF FS

2nd Harmonic

Freq

DC

Tx Band

Rx Band
In-Band Blockers Power (dBm) Blocker IMD Product

Power (dBm)

FFT

C/D
D DC Tx Band
FLO-FRF Power (dBm)

Desired Signal

I
Freq
D DC
FS-FIF FS/2

Freq
Rx Band
FLO+FRF

Desired Signal

LO Leakage

E
Freq

D DC

FLO

How IF sampling works


The receiver uses RF and IF filters to eliminate the transmit signal and blockers so that only the desired signal is sampled The ADC must sample at twice the signal bandwidth to meet Nyquist criteria Oversampling can be used to improve the signal to noise ratio by 3 dB for each doubling of the sample frequency Harmonics of ADC driver amp that are not filtered will degrade performance There is usually a clock recovery loop in an FPGA or DSP or both that locks the sampling rate to a multiple of the symbol rate
6

Direct Conversion Receiver


IQ DEMOD Band Filter

ADC C D
VGA

0 90

G ADC

RSSI /AGC DUPLEXER

TRANSMITTER

Saves money by mixing RF spectrum to baseband in a single step Reduces component count and eliminates IF SAW filters There is a reason why RF engineers have not tried this sooner removing DC offsets at baseband
7

Direct Conversion Receiver


Power (dBm) Transmit Signal In-Band Blockers

Desired Signal

Blocker IMD Product

In-Band Blockers

A
DC
Power (dBm)

Desired Signal

F
Freq

DC Offset from LO Self Mixing & IP2 Intermodulation

Freq
DC
BB Amp Distortion
FS/2 FS

Tx Band

Rx Band

In-Band Blockers

C
Transmit Signal

G
Desired Signal

Desired Carrier

Nqyuist Filter

Freq
DC Tx Band Rx Band DC
FS/2

Freq
FS

Power (dBm)

In-Band Blockers Blocker IMD Product Desired Signal Transmit Signal

Freq
DC Tx Band Rx Band

Direct Conversion Receiver


In-Band Blockers can only be eliminated at the end of the signal chain or in the digital domain. In-Band Blockers can mix in the Front End (before mixer) to produce an unwanted product at baseband LO leakage to the RF input causes self-mixing and produces an unwanted dc offset at dc (right in the middle of the desired signal) Non-Ideal 90 degree balance in the Demodulator produces unwanted images of blockers which can be close to the carrier Direct Conversion Receivers are cheaper and smaller (no IF SAW filters, cheaper ADCs, only one mixer)

Transmitter Architectures
Super Heterodyne with IQ Modulator Super Heterodyne with Real IF DAC Synthesis Direct Conversion Low IF to RF Conversion

10

Superheterodyne Transmitter using IQ Modulator


-15 dBm 380 MHz -25 dBm

Gain=10dB NF=12 dB OIP3=20 dBm P1 dB=10 dBm


ACTIVE MIXER IF AMP Diff to SE

-15 dBm

-18 dBm

-3 dBm

+45 dBm

DAC
SAW

BAND FILTER

PA DRIVER PA +15dB 48 dB

-10 dB

0 to -20dB

-3 dB

DAC TxDAC

A B

AD8345

+10dB -5 dBm

F
AD8362 60 dB RMS Detector

G
AD8362 60 dB RMS Detector

380 MHz

ADF4212L (Int-N) ADF4252 (Frac-N)

1760 +/-30 MHz 1580 +/-30 MHz 1462.5 +/-37.5 MHz

Superheterodyne Transmitter uses one or more Intermediate Frequencies. DAC constructs the baseband signal, centered either at dc or at a low Intermediate Frequency (IF) Gain control and filtering may be implemented at RF, IF, and baseband. Lots of power back-off to avoid distortion in non-constant envelope systems
11

Superheterodyne Transmitter using IQ Modulator


A
DC IF Tx Band

E F

IMAGE

LO

Tx Band

B
DC IF Tx Band

Tx Band

C
F
IF Tx Band

D
F
IF Tx Band

G
DC Tx Band

12

Superheterodyne Transmitter using IQ Modulator


Noise and Spurs generated in the IF stage can be filtered After mix to RF, band filtering removes out of band noise along with the image In-Band noise generated in mix to RF cannot be removed

13

Example: Superhet with IF Synthesis of signal in IQ format


AD8345
16-bit AD9777 16-bit 22 Mhz

AD8343

Step Attenuator

Power Amplifier
40dB

C A B
402 MHz

380 MHz

Band F Filter

1.52 GHz

Driving IQ mod with a low IF creates a single-sideband-like spectrum at the modulator output. Once IF has been filtered (removing unwanted sideband and LO), modulation quality (EVM) is excellent.
14

Example: Superheterodyne Receiver with IF Synthesis of signal in IQ format


A
LOW IF
IMAGES

E F

LO LEAKAGE

Tx Band

B
LOW IF
UNDESIRED LO UPPER LEAKAGE SIDEBAND

Tx Band

C
IF

D
F
IF

G
DC Tx Band

Unwanted LO leakage and Upper Sideband are filtered at IF, resulting in excellent EVM If low IF is high enough, do a single up-conversion to RF
15

Direct Conversion Zero IF Architecture


-15 dBm -18 dBm -3 dBm +45 dBm

DAC

BAND FILTER

PA DRIVER PA +15dB 48 dB

0 to -20dB

-3 dB

DAC
AD8349

AD9767 TxDAC
-5 dBm

1760 +/-30 MHz 1580 +/-30 MHz 1462.5 +/-37.5 MHz

AD8362 60 dB RMS Detector

AD8362 60 dB RMS Detector

Direct Conversion mixes a base-band signal from a dual DAC up to the transmission frequency in a single step. With no IF, gain control, filtering, and equalization must be performed either in the digital backend, at the reconstructed analog base-band output or at RF. Effects of LO leakage and Upper Sideband Leakage occur in-band potentially interfering with the signals EVM. Dual channels are required to generate the complex signal, any channel mismatch causes In-band distortion which cannot be filtered. High quality components are required to generate an accurate signal In-Band Modulator Noise cannot be filtered Calibration of LO leakage and Quadrature balance is generally necessary PA to LO leakage can modulate or pull the PLL

16

Example: Direct Conversion Transmitter


-15 dBm -18 dBm -3 dBm +45 dBm

DAC

BAND FILTER

PA DRIVER PA +15dB 48 dB

DAC AD9767 TxDAC

C A B
AD8349 -5 dBm

0 to -20dB

-3 dB

1760 +/-30 MHz 1580 +/-30 MHz 1462.5 +/-37.5 MHz

AD8362 60 dB RMS Detector

AD8362 60 dB RMS Detector

A
DC Tx Band

Freq

D
DC Tx Band

Freq

B
DC Tx Band

Freq

C
Tx Band

E
Freq
DC Tx Band

Freq

17

Poor OIP3 causes Adjacent Channel Leakage


Adjacent Channel Leakage

SNR

Think of a broadband spectrum multiple tones inter-modulating with each other IM3 products produce Adjacent Channel Power/Leakage/Distortion Use 3-to-1 decay of IMD products to reduce dBc IMD but this degrades SNR
18

ACPR and Noise vs. Output Power


-55.0 -150 -56.0 ACP 2140 MHz Noise Floor 2140 MHz -151

-58.0

-153

-59.0

-154

-60.0

-155

-61.0

-156

-62.0

-157

-63.0

-158

-64.0

-159

-65.0 -30 -28 -26 -24 -22 -20 -18

-160

Per-Carrier Output Power - dBm

ACP degrades with increased output power due to IMD Noise is independent of input and output power At low power levels ACP degrades because of falling SNR
19

Noise Floor - dBm /Hz (25 M hz Carrier Offset)

-57.0

-152

ACP - dBc

Example: Low IF to RF Transmitter using IF Synthesizing DAC and Passive Mixer


-16 dBm -6 dBm

Gain= -5 dB NF= 5 dB OIP3= +35 dBm P1 dB= 25 dBm


PASSIVE MIXER

-11 dBm

-14 dBm

+1 dBm

+45 dBm

Pout -15 dBm 190 MHz

ANTI ALIAS IF AMP -1 dB

BAND FILTER

PA DRIVER PA +15dB 44 dB

AD9786 DAC

0 to -20dB 10 dB

-3 dB

+5 dB

-5 dBm

2.33 GHz 2.15 GHz 2.03 GHz

AD8362 60 dB RMS Detector

AD8362 60 dB RMS Detector

Baseband DAC, IQ Modulator and PLL are replaced by an IF Synthesizing DAC or DDS modulator Trade Off: High Performance DDS/DAC + SAW + Mixer + PLL vs. IQ DAC + Modulator + PLL None of the problems typically associated with Direct Conversion Probably more expensive than Direct Conversion
20

Low IF to RF Architecture
LO

A
DC

IF

Tx Band

LO LO+ IF

LO-IF

B
DC

IF

Tx Band

High Performance DAC generates real IF at a low IF (100-200 MHz) Mixer performs Double Sideband Modulation Advantage: Unwanted LO and Sideband are removed -> excellent EVM Challenge: To move unwanted LO and upper sideband out of band means that the IF must be quite high
21

Chapter VII Receiver Optimization Using Error Vector Magnitude Analysis By Eric Newman
Figure 1 depicts a signal space constellation containing two vectors, a reference vector, R(k), and the actual measured vector, Z(k), which indicates the recorded symbol trajectory. The reference vector defines the coordinates of an ideal error-free symbol trajectory. The difference between the reference vector and the actual measured symbol vector is defined as the error vector. o EVM Introduction o Bit-Error-Rate and Probability of Error o SNR and EVM Relationships o Optimization Example: AD8348/AD8362 IF to Baseband Sub-System o Using RSSI to Estimate EVM and BER Performance The error vector magnitude represents the Euclidian distance between the ideal symbol coordinate and the actual recorded symbol. In general EVM is averaged over an ensemble of symbol trajectories and can be defined numerically as
Q (quadrature)

otherwise create signal distortion, the measured vector and reference vector would be identical, and the EVM would be zero. Consider the signal-to-noise-ratio (SNR) of the symbol trajectory. If the SNR was very good, then the displacement of the measured vector from the reference vector due to noise and distortion effects would be very small, and the resultant EVM would approach zero. Conversely, a large EVM suggests that the measured symbol is significantly displaced from the ideal reference vector, which can only be the result of noise and distortion effects unless the reference vector is somehow in error. This suggests that the SNR and EVM of a modulated signal share an inverse relationship. Numerically this relationship can be expressed as

EVM =

1 SNR L

(2)

where L is the coding gain Coding gain accounts for any benefits due to signal coding. In general the baseband information may be encoded using a number of techniques. For instance, in a spread-spectrum system the baseband data is spread by multiplying each transmitted bit by a direct sequence. The direct sequence consists of a random series of ones and zeros. The sequence is carefully selected so that it is unique and weakly correlated to other sequences used to encode other data-streams that will share the same carrier frequency. The ratio of the number of chips used to encode each bit is the coding gain. In decibels, it is expressed as 10Log10(chiprate/data-rate). For example, a UMTS transceiver may be transmitting a 12.2 kbps data stream using a chip-rate of 3.84 Mchips/s, resulting in a coding gain of 3.84106/12.2103=314.75, or 25 dB. In order to link EVM to BER, it is necessary to determine the dependency of SNR on the probability of a symbol error for a given modulation scheme. For quadrature amplitude modulations (QAM), the probability of a symbol error can be expressed as:

Ideal point

Error vector

k) R(
k) Z(

actual point

I (in-phase)

Figure 1. IQ signal space illustrating reference vector, R(k), and measurement vector, Z(k).

EVM =

Z (k ) R(k )
k =1

R(k )
k =1

(1)

EVM provides a measure of the ratio of the error vector to the reference vector. In a perfect system, free of noise and non-linearities that would

VII-1

1 1 3 1 3 PM = 21 k b 1 1 k b erfc erfc 2( M 1) 2( M 1) M M 2
where M is the order of the modulation (i.e. 64 for 64-QAM) b is the average signal to noise ratio per bit k is the number of bits per symbol (i.e. 6 bits per complex symbol for 64-QAM) Using equations 2 and 3, the symbol-error-rate (SER) and EVM can be derived for varying SNR. SER versus SNR is presented in figure 2a. This provides the classic waterfall patterns for various
1

(3)

order QAM modulation schemes. The EVM versus SNR is presented in figure 2b for the same modulations. This allows designers to predict the bit error rate performance of a given receiver using error vector analysis techniques. For example, if the EVM is measured to be 3% for un-coded 256-QAM modulation, the anticipated symbol error rate would be 600 ppm. In other words, on average 6 symbols could be expected to be erroneous out of a 10,000 symbol sequence, corresponding to a bit error rate of 75 bits in a 1 million bit sequence, or a BER of 7.510-5.

0.1

Probability of a Symbol Error

16QAM 0.01

64QAM

256QAM

0.001

0.0001

0.00001

0.000001 0 5 10 15 20 25 30 35

SNR - dB

(a)
1 256QAM 0.1

Probability of a Symbol Error

64QAM 0.01 16QAM

0.001

0.0001

0.00001

0.000001 0 5 10 15 20 25 30 35 40 45 50

EVM - %

(b) Figure 2 a) The theoretical probability of a symbol error for un-coded 16-, 64-, and 256-QAM modulations versus SNR. b) The corresponding symbol error probability versus measured EVM.

VII-2

Using the data in figures 2a and 2b along with an appropriate vector signal analyzer, designers can optimize performance in a timely manner. Parameters such as filter selection, inter-stage matching and conversion gain can all be adjusted while observing EVM performance. This allows designers to quickly optimize their signal chains. Figure 3 illustrates some of the possible signal impairments that can occur in a real-world system. By monitoring the signal space it is possible to identify the noise or distortion mechanisms that may be degrading EVM performance.
Nois CW IQ Gain

insensitivity to varying crest factor waveforms, making it an ideal solution for measuring the true rms power of digitally modulated signals. The circuit in Figure 4 is configured to measure the rms power of the baseband signal present on the in-phase channel. The choice of in-phase or quadrature detection is arbitrary assuming that I and Q vectors are pseudo-random, a valid assumption for most digital modulation schemes. The on-board error amplifier uses the baseband rms power measurement to generate a control signal that drives the gain-control port on the quadrature demodulator. The conversion gain of the demodulator is adaptively adjusted in a closed-loop fashion to maintain a constant baseband rms power level, regardless of waveshape. The output level is set by applying the appropriate set-point control voltage to the VSET pin. Error vector analysis was used to find the optimum ALC output set-point and to determine a suitable filter for a 256-QAM 1Msymbol/sec digital modulation. The demodulator provides a single-ended interface for application of a low pass filter. Fourth-order Bessel filters were employed on both I and Q channels to minimize wideband noise and to help reject unwanted adjacent signals. The Bessel filter was selected for its low group delay characteristics, a necessary attribute to ensure low inter-symbol-interference. Initially Butterworth and Chebyshev filter designs were tested, but the greater group delay in the passband resulted in degraded EVM performance. The subtle differences in receiver performance with the various filter selections would have been difficult to measure using classical methods. The VSA quickly measures the performance, allowing the filter networks to be optimized in a short period of time. The baseband EVM was measured using an FSQ8 vector signal analyzer from Rohde & Schwarz. While observing the EVM, the setpoint control voltage was varied to find the optimum setting. With the appropriate set-point voltage the EVM remains better than 2% over more than a 40 dB input range as indicated in Figure 5. The measured IQ baseband constellation for a 256-QAM modulation scheme is presented in Figure 6. The variable conversion gain of the demodulator allows receiver designs with optimum BER performance over a wider dynamic range than a fixed gain demodulator.

Phase

Compressio

IQ Phase

Figure 3. A variety of possible signal pairments. By recognizing the tell-tale signs of different signal impairments, receiver problems can be more easily isolated and debug simplified. Optimization Example: AD8348/AD8362 IF to Baseband Sub-System A quadrature demodulator and rms-accurate power detector are presented in Figure 4 as a closed-loop ALC (Automatic Level Control) IFto-baseband receiver subsystem. The AD8348 provides accurate quadrature demodulation from 50 MHz to 1 GHz. An internal LO frequency divider allows an LO that is twice the desired carrier frequency to be used, easing LO-pulling issues associated with a full duplex transceiver. In the example, the IF input frequency was 190 MHz with an LO drive of 10 dBm at 380 MHz. An integrated front-end variable gain amplifier (VGA) comprised of a resistive variableattenuator and high intercept-point post amplifier provides variable conversion gain while preserving a constant spurious free dynamic range. The AD8362 is a highly accurate RF power measurement device capable of measuring the rms power of signals from arbitrarily low frequencies out to 2.7 GHz. The device exhibits

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Figure 4. The AD8348 IQ Demodulator in combination with the AD8362 TruPwr Detector can be configured to provide highly accurate automatic level control IF-to-baseband receiver subsystem.
10 9 8 7

EVM - %

6 5 4 3 2 1 0 -45 -40 -35 -30


VSET=1.3V VSET=1.4V VSET=1.2V

require less SNR for adequate BER performance. It is no surprise that the lower order modulation schemes result in even better EVM performance over a slightly broader input power range. By monitoring the RSSI (Received Signal Strength Indication) voltage of the AD8362 it is possible to predict EVM performance. Figure 8 provides the measured RSSI voltage for several modulation schemes. It is possible to use the RSSI voltage to estimate the input power presented at the demodulator input within a reasonable error. The input power estimate can then be used to predict the EVM performance at that input power level.

-25

-20

-15

-10

-5

10

15

Power In - dBm

Figure 5. Error Vector Magnitude (EVM) versus input power level for 256-QAM at 1-Msymbol/sec. Figure 7 illustrates the performance for lower order QAM modulations of the same signal bandwidth. The lower order modulation schemes

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Figure 6. IQ constellation of baseband output for 256QAM modulation at 1 Msymbol/sec.


2
10 9 8 7
WAVEFORMS: QPSK 16, 64, and 256 QAM @ 1MSps =0.35

5
WAVEFORMS: QPSK 16, 64, and 256 QAM @ 1MSps =0.35

1.8 1.6 1.4 1.2 1 0.8

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RSSI - V

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m=18mV/dB

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1 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15

0.2 0

Power In - dBm (re 200 Ohms)

Figure 7. EVM versus input power for 16, 64, and 256QAM. Summary By measuring the EVM over the desired input signal range, one can readily estimate symbol error rate performance. Using the measured EVM data in combination with the plots in figure 2, the dynamic performance of the receiver can be predicted. For a 256-QAM modulation the EVM must be better than ~2% to ensure the

Power In - dBm (re 200 Ohms)

Figure 8. By understanding the EVM versus input power relationships, an rms-accurate RSSI measurement can be used to predict receiver performance. symbol error rate is less than 10-6. The measured results of the IF-to-baseband receiver subsystem indicates that the receiver could tolerate more than a 40 dB range of input power variation before SER is degraded to an unacceptable level. EVM analysis is a useful tool for signal chain optimization and prediction of dynamic performance.

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Error - dB

Chapter VIII Design and Operation of Automatic Gain Control Loops for Receivers in Modern Communications Systems By Dana Whitlow
Introduction This chapter will provide insight into effective operations of a Variable Gain Amplifier (VGA) in Automatic Gain Control (AGC) applications. Throughout this chapter, several key issues will be addressed. For further discussion, an example application revolving around the AD8367 IF VGA will also be presented. AGC Loop Design Key Issues VGA types Loop dynamics Detector types Operating level of VGA Operating level of Detector Figure 1 is a general block diagram for an AGC loop. The input signal passes through the VGA to produce a signal output whose level will be stabilized. The output level is measured by a detector, whose output is compared against a setpoint voltage to produce an error signal. The error signal is then integrated to produce a gain control voltage that is applied to the control input of the VGA. It may be desirable to align the maximum output level of the VGA with the maximum input level of the detector with the attenuator shown between the VGA and the detector. VGA types: There are two major classes of VGAs in use today. The first is the IVGA (Input VGA) that can be regarded as a passive variable attenuator followed by a fixed gain amplifier. The second type is the OVGA (Output VGA) that is equivalent to a fixed gain amplifier followed by a passive attenuator. VGA Types IVGA Variable attenuator with fixed gain post-amplifier OVGA Fixed gain amplifier followed by a passive attenuator IVGAs - Generally used in receivers and focus on generating a constant output level with variable input OVGAs - Generally used in transmitters to generate variable output levels with a fixed input level IVGAs - For AGC applications where constant output level is desired For a receive AGC system, an IVGA is the preferred choice because the available output level at low distortion is independent of the gain setting. Since the very object of the AGC loop is to maintain constant output in the face of a varying input signal amplitude, this is the desired trait for an AGC system. The OVGA (whose maximum available output level decreases dramatically with decreasing gain) is ill suited to AGC applications because the undistorted output capability of the device would fall below the desired output level under some particular gain setting, thereby limiting the useful control range. OVGAs are more suited to power control applications where the objective is to vary the output level (for example, a transmitter) from a more or less constant input. This application note is devoted to AGC systems; therefore chapter will focus on the application of IVGAs. Fig. 1 VGA-Based AGC Loop Block Diagram. Analog Devices markets a wide selection of IVGAs, in which most use some variant of the

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patented X-Amp architecture. In the description given above for the IVGA, the X-amp is a very close approximation in which the variable passive attenuator is a resistive ladder network with taps at equal dB intervals. Gain control is achieved by a mechanism that picks off signals from different taps as the desired gain setting is changed. Continuous variation in gain without steps or significant nonlinearity is achieved by an interpolation scheme that uses a weighted combination of signals from a few consecutive taps. As the gain is adjusted, there is a smooth handoff between tap combinations. The output from the interpolation mechanism is then passed through a low noise fixed gain amplifier. For a ladder whose taps are equally spaced in dB, this approach provides a very accurate and predictable linear-in-dB gain control with only a very small residual ripple in the gain versus the control voltage function. Analog Devices AD8367 is a high-performance, 45 dB input variable gain amplifier with linearin-dB gain control for use from low frequencies up to several hundred megahertz (see Figure 2). The input is applied to a 200 resistive ladder network, having nine sections each of 5 dB loss, for a total attenuation of 45 dB. At maximum gain the first tap is selected; while at progressively lower gains the tap moves smoothly and continuously toward higher attenuation values. The attenuator is followed by a 42.5 dB fixed gain feedback amplifier. The output third order intercept is +27 dBm (re 200 ) at 100 MHz.

operation, selected by a simple pin-strap, the gain decreases from +42.5 dB at VGAIN = 50 mV to 2.5 dB at VGAIN = 950 mV. This inverse mode is needed in AGC applications that are supported by the integrated square-law detector, while the set point is chosen to level the output to 354 mV rms, regardless of the waveshape. A single external capacitor sets up the loop averaging time. AD8367 500 MHz Linear-in-dB IVGA Key Features 45 dB analog variable gain range Reversible gain control sense Linear-in-dB gain control scaled 20 mV/dB On-chip square-law detector Single-supply operation: 2.7 V to 5.5 V When a single device is used in an AGC system, the IVGA is often criticized because the output Signal-to-Noise Ratio (SNR) may not improve with increasing input level. This is because the attenuation preceding the amplifier changes by the same amount that the signal level changes, so the input to the amplifier (which is presumed to set the noise floor) does not change, leaving the S/N unimproved. If necessary, this behavior can be improved by cascading two VGAs and properly coordinating the gain control inputs of the two devices. If the gain control of only the second stage VGA is manipulated in the weak signal regime the signal level to the first stage VGAs amplifier does increase with increasing input level, so the output SNR improves. It is not necessary to begin reducing the first stage VGAs gain control input until the input level approaches the point at which the first stage would cause excessive distortion if left at full gain. At this point the gain control would be handed off to the first stage from the second stage. Alternatively, the two gain control inputs may simply be driven in parallel, in which case the output S/N (expressed in dB) improves at half the rate at which the input level (also expressed in dB) rises. In this case each VGA is changing its gain (dB) at half the rate required to accommodate the changing input signal level. An additional benefit of this approach can be obtained if the two gain control input signals are intentionally offset by half the period of the residual ripple in the gain versus control voltage

Figure 2. AD8367 500 MHz Linear-in-dB IVGA With On-Board AGC Detector The analog gain-control interface is very simple to use. It is scaled at 20 mV/dB, and the control voltage, VGAIN, runs from 50 mV at 2.5 dB to 950 mV at +42.5 dB. In the inverse-gain mode of

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curve. This would lead to a considerable reduction of the ripple. Either of the above approaches to cascading VGAs leads to an increased overall gain control range, potentially twice the range of a single VGA. (For practical details of cascading VGAs, please refer to the application section of the AD603 data sheet.) A very useful feature when using an X-ampbased IVGA in an AGC loop is the VGAs gain control voltage bears an accurate logarithmic relationship to the input signal level when the loop is in equilibrium. This means the gain control voltage may also be used as an excellent RSSI (Received Signal Strength Indicator). Loop Dynamics: When designing any AGC loop, response time is an important issue. There is usually a compromise that must be made between having the loop respond to undesired input level fluctuations and having it modify the legitimate amplitude modulation on the signal. Additionally, large and/or abrupt changes in the input level may lead to unwanted recovery behavior, necessitating further adjustments of the response time. Because the behavior for abrupt and/or large changes may also be strongly influenced by the detectors type, much of the discussion of this area will be deferred to the following section on detectors. The issue of excessive loop bandwidth deserves a bit more explanation. If the loop responds too quickly, it will create undesired gain modulation arising from the loops efforts to stabilize the output level of a signal containing legitimate amplitude modulation. This phenomenon is known as gain pumping and should be distinguished from the desirable gain variations made to accommodate drift and path loss variation in an AGC loop. In the case of classic AM signals, the effect of excessive AGC bandwidth is to reduce the low frequency response of the detected audio and to introduce audio IM distortion. The AGC loop is continually adjusting the gain in an attempt to stabilize the signal amplitude; in doing so it is effectively stripping off the low frequency modulation. At the same time the gain pumping is effectively introducing fast fading, which varies the amplitude of the surviving modulation components coming out of the demodulator.

The resulting amplitude variation of some (high frequency) components in time with other (low frequency) components is the classic form of audio intermodulation distortion. Loop Dynamics AGC loop must respond to input power level changes Input level changes can be relatively slow (fading) or abrupt (pulsed applications) Excessive AGC loop bandwidth causes loop to respond to the changing envelope of input signal (gain pumping) Excessive gain pumping causes modulation errors and spectral regrowth In context of modern digital modulation, the presence of appreciable gain pumping can result in significant modulation errors and perhaps even noticeable spectral re-growth in extreme cases. Figure 3 shows measured gain variation over time for an AGC loop whose bandwidth was intentionally made too high for the type of signal modulation employed, in that the gain is being varied by about 1.5 dB p-p by the loop. This plot was obtained by viewing the gain control voltage of the VGA with an oscilloscope and rescaling the result to dB units. A tolerable value of gain pumping would normally be only a small fraction of 1 dB.

Figure 3. An AGC Loop with excessive loop bandwidth will result in gain pumping where the loop incorrectly responds to the instantaneous input power which changes on a symbol-tosymbol basis. Generally, gain pumping should be limited to a fraction of a dB.

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Figure 4 shows the effect of gain pumping on a signal space constellation. This shows the demodulated constellation of a 64 QAM modulated carrier (500 kSymbols/Sec). This shows how the AGC circuit improperly responds to the varying input signal level that results from the varying levels of the symbols. In designing an AGC loop, ensure that it is fast enough to respond to average input power variations while keeping gain pumping reduced to a minimum so that it does not degrade EVM.

Envelope detector (full-wave rectifier): The output of an envelope detector (usually a half-wave or full-wave diode circuit) is proportional to the absolute magnitude of the instantaneous RF input voltage. Assuming that sufficient low-pass filtering is applied at its output to eliminate ripple at twice the RF frequency, this detector produces a voltage proportional to the envelope amplitude of the RF signal. Assuming that the loops bandwidth is made small enough to avoid measurable gain pumping, the effect of the loop using an envelope detector is to stabilize the average rectified voltage of the signal. The exact result in terms of power is therefore dependent on the RF signals envelope waveform. Such a loop acting on a constantenvelope signal such as FM will produce an average output power which is different than that for a heavily-amplitude-modulated signal, such as CDMA or 64 QAM, for example. The output of the envelope detector cannot be negative no matter how weak the input signal, but even practical realizations are essentially unbounded in their response to very strong signals. The maximum detector output is likely to be determined by saturation of the VGAs output. Starting with the AGC loop in equilibrium, a sudden large increase in input amplitude causes a very large initial increase in detector output, which drives the loop rapidly towards lower gain. On the other hand, an abrupt reduction of the input signal level (regardless of how many dB) cannot reduce the detector output below zero. The loops best response is to slew towards equilibrium at a fairly low rate until the detector output begins to change by a significant fraction of the reference voltage. At this point the recovery trends towards an exponential decay. In the slew rate limited region, the gain of the signal path is varying at a constant number of dB per second.

Figure 4 Excessive gain pumping in a 64 QAM Signal Space Constellation will result in degraded EVM. Detector types One convenient aspect of an AGC loop is that the detector does not have to have a very wide dynamic range. This is because the detector operates at a constant average level when the AGC loop is settled; thus the detector only needs to measure modulated signal levels over narrow range. However, as mentioned earlier, the detectors response law (e.g. linear, log, square law, etc) can play a significant role in determining the loops dynamic response during large, abrupt changes in signal level. Furthermore, the choice of detector will affect the level at which the loop reaches equilibrium. Detector Types Envelope Detector Square-Law Detector True-RMS Detector Log Detector

Envelope Detectors in AGC Loops Usually a diode-based half-wave or full-wave rectifier Output power of an AGC Loop will vary with signal crest factor Fast response to fast increases in input signal to AGC Loop Slow exponential response to fast decreases in input signal

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Figure 5 shows the simulated time domain output power profile of an envelope detector based AGC loop to small input steps. (Curves for all four detector types are superimposed on this plot.) This suggests that the choice of detector has little influence on the small signal settling time of the loop.

Figure 5. Simulated AGC Loop Response to Small Amplitude Steps with Log, Envelope, RMS and Square Law Detectors Figure 6 shows the time domain output power profile of the same AGC loop to a 40 dB input step and suggests that the choice of detector has a more significant effect on settling time for large input steps. These results were obtained from simulations in which the VGA has representative limits on the gain range and on the maximum output level. The detectors contrived for these simulations have no particular limits. The theory is that in most practical situations, the designer will scale the circuit so that the detector does not limit appreciably before the VGA does.

Square-Law Detectors This type of detector has an instantaneous output that is proportional to the square of the instantaneous RF input voltage. This is equivalent to saying that its output is proportional to input power. This behavior, when incorporated into an AGC loop of reasonable bandwidth, makes the loops equilibrium average output power independent of the input waveform. As with the envelope detector, the output can never go negative. This would result in the loop having a similar tendency towards slew rate limited behavior when reacting to abrupt decreases in input amplitude. The response to large abrupt increases in input amplitude can be even more striking, however, because the square-law detector response exaggerates the effect of the input increase. The extent to which this happens depends on the clipping level of either the VGA or the detector, whichever happens at a lower level. True-RMS Detectors This detector is a square-law detector followed by a low-pass filter followed by a square-root function. The low-pass filter performs the mean operation associated with the RMS (Root-Mean-Square) function, and it should have a sufficiently long time constant to smooth the output variations of the squaring detector that would otherwise arise from the legitimate modulation of the signal. Because of the square-root element in this detector, the average output is proportional to signal voltage, not power. Therefore the loops response to small abrupt decreases or increases of signal level should be basically the same as that for an envelope detector, provided that the added filter pole within the RMS detector is compensated correctly elsewhere in the loop. The fact that the added pole is located in a region of the signal path that is square law brings forth the possibility of the large-step response being different from that of the simple envelope detector, as seen in Figure 6. Note that the RMS detector has a slightly slower recovery from a large downward amplitude step than does the standard envelope detector, but a slightly faster recovery (and a bit of overshoot) from a step up in input amplitude. In common with the square-law detector, the true-RMS detector will make the AGC loops

Figure 6. Simulated Response of an AGC Loop to 40 dB Input Power Steps

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equilibrium point independent of the RF signal waveform. It should be noted that the presence of the longtime-constant low-pass filter in this detector may have a marked influence on loop dynamics. This filter may even provide the dominant pole in some designs. Usually the time constant must be coordinated with that of the remainder of the loop for optimum loop stability. Square Law and RMS Detectors Instantaneous output of Square Law Detector proportional to the square of the instantaneous RF input voltage Output voltage of RMS Detector is proportional to (averaged) RMS input voltage Output power of AGC Loop using RMS or Square Law Detector is independent of signal crest factor Time constant of RMS Detector must be coordinated with time constant of error amplifier in AGC Loop Figure 7 shows the block diagram of the ADL5500, an rms-responding power detector for use in high frequency receiver and transmitter signal chains from 100 MHz to 6 GHz. It is easy to apply, requiring only a single supply between 2.7 V and 5.5 V and a power supply decoupling capacitor. The input is internally ac-coupled with an input impedance of 50 . The output is a linear-responding dc voltage with a conversion gain of 6.4 V/V rms at 900 MHz. The on-chip, 1 k series resistance at the output combined with an external shunt capacitor, creates a low-pass filter response that reduces the residual ripple in the dc output voltage.

The ADL5500 offers excellent temperature stability with near 0 dB measurement error across temperature. The high accuracy range, centered around +3 dBm at 900 MHz, offers 0.1 dB error from 40C to +85C over an 8.5 dB range. The ADL5500 reduces calibration requirements with low drift across a 30 dB range over temperature and process variations. Log Detectors This type of detector produces an output proportional to the logarithm of the RF input voltage. Because this behavior is complementary to that of the linear-in-dB VGA in the loop, the resulting loop dynamics are those of a linear system, assuming that signal level fluctuations during transients remain within the measurement range of the Log detector. Subject to that assumption, the AGC loops response to abrupt and large changes in input level will not be slewrate limited. As with the envelope detector, the equilibrium point of an AGC loop using the Log detector will depend on the RF input waveform. Log Detectors Output proportional to the logarithm of the RF input voltage Linear-in-dB transfer function of Log Detector is complementary to gain control transfer function of Linear-indB X-Amp Output power of AGC Loop using Log Detector will vary with signal crest factor

Figure 7. ADL5500 100 MHz to 6 GHz RMS Detector with Integrated Averaging Capacitor.

Figure 8. AD8317 1 MHz to 10 GHz, 50 dB Log Detector/Controller

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The AD8317 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibelscaled output. The device can be used in either measurement or AGC modes where it incorporates the error amplifier/integrator. The input dynamic range is typically 50 dB with error less than 1 dB. The AD8317 has 8/10 ns response time (fall time/rise time) that enables RF burst detection to a pulse rate beyond 50 MHz. The device provides unprecedented temperature stability vs. ambient temperature conditions. Because the output can be used for AGC applications, special attention has been given to minimize wideband noise. In this mode, the setpoint control voltage is applied to the VSET pin. The feedback loop through an RF amplifier is closed via VOUT. The output of this regulates the amplifiers output to a magnitude corresponding to VSET. The AD8317 provides 0 V to 4.9 V output swing at the VOUT pin (on a 5 V supply), suitable for controller applications. AD8317 1 MHz to 10 GHz Log Detector/Controller 50 dB detection range Built-in error amplifier for operation in AGC mode 10 ns step response time Temperature stable to within 0.5 dB AGC amplifier output swing from 0 V to 4.9 V (5 V supply) Comparison of responses with different detectors: The AGC loops whose simulation results are shown in Figures 5 and 6 were designed so that the small-signal response speeds are identical. Figure 5 confirms that the AGC loops response is independent of the detector type for small steps in amplitude. This reflects the fact that small steps traverse such a small part of the nonlinearities that slopes dont change noticeably as the response progresses. On the other hand, Figure 6 shows that the loops large-step transient response is markedly dependent on the type of detector. At one extreme, the Log detector gives the fastest response to large, abrupt decreases in input level because the logarithmic curve has a very steep

slope for low inputs, which exaggerates the loops response. However, the Log detector has a shallow slope for high input levels, resulting in a diminished response rate to sudden increases in signal level. At the other extreme, the square law detectors small slope, near zero input level, gives it a very sluggish response to large decreases in input amplitude. Conversely, the square law detector exaggerates the response to large signals, giving the fastest response to increasing signals. The envelope and RMS detectors, having intermediate characteristics, give response speeds in between. Detector Comparisons When Used in AGC Loops Small signal response of different detectors are similar Log detectors respond quickly to decreases in input power to AGC circuits Square Law Detectors respond quickly to increasing input signals RMS Detectors have intermediate response characteristics Operating Level of Detector: Ideally the operating level of the detector should be set as high as possible in order to minimize error due to residual DC offsets. Also, the temperature stability of many detectors is best at high input power levels. However, other considerations often rule. For modulation types that involve amplitude modulation, the average input to the detector, when the loop is in equilibrium, must be lower than its maximum level. In order to form an error signal to drive the loop back towards equilibrium, even for constant-envelope signals, the settled input level must be lower than the maximum so that there is room for the detector level to increase if the system input level increases. Setting Operating Level of Detector in AGC Loops Set input level to detector as high as possible to minimize DC errors and temperature drift Setpoint level should be set below maximum input level to allow loop to settle in response to positive input steps Settling time for positive and negative input changes will be unequal

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Note that there will generally be unequal amounts of room for the detector output to swing up from the design equilibrium level as opposed to down, which will make the apparent attack and decay speeds of the loop differ. Design Example of a Working AGC Loop Now put the above considerations to work in a practical AGC loop. This design will use the AD8367 VGA. While the AD8367 VGA has an internal rms detector and AGC mode, the output setpoint level cannot be varied. As a result, in this example and external rms detector, AD8361 is used to provide a stable output. We will establish reasonable constraints for operating levels to maximize ACPR and AGC loop bandwidth, to avoid excessive gain pumping. Design Example AGC Loop constructed using AD8367 VGA and AD8361 RMS detector Modulated carrier with 18 dB peak-toaverage ratio IF frequency: 380 MHz Power supply: 5 VDC

noise. In order to achieve the best ratio of inband signal to noise plus distortion, reduce the power to the level that brings the in-band distortion down to the noise level, which requires about 3 dB level reduction (assuming reasonably well-behaved 3rd order distortion). We therefore choose an average output level of 12 dBm from the VGA (into a total load of about 200 ), which is 112 mV rms. Detector operating level For this modulation type, the peak-to-average power ratio is about 18 dB. When operating from a 5 V supply, the maximum output level of the AD8361 is about 4.8 volts. We will presume that the squarer in the detector goes into clipping at the same input level that results in maximum output, for a CW signal (this is a slightly conservative assumption). Assuming that we dont want the peaks of our modulated signal to drive the squarer into clipping, when the loop is in equilibrium, the average output level of the detector must be at least 18 dB below 4.8 V; 4.8 * 10 ^ (-18 / 20) = 604 mV. Since the conversion gain of the detector is 7.5 V/V rms, the loop-equilibrium input level should be 604 mV / 7.5 = 80 mV rms. This level can be obtained from the desired output level of the VGA by adding a series resistor of 90 , which combines with the 225 input resistance of the detector to form a voltage divider that achieves the desired result. Note that this loads the output of the VGA with 315 . This means that the lowest additional parallel load impedance on the VGA would be 547 in order to satisfy its design minimum load impedance of 200 . In effect, more than half of the VGAs power output is going to feeding the detector, which is not very satisfying. This could be remedied by driving the VGA end of the 90 resistor with an emitter follower, raising the input impedance of the overall detector by the beta of the transistor used in the follower. This would free up almost all the output drive capability of the VGA for use by the useful load. Estimation of target AGC Loop Bandwidth To establish the maximum loop bandwidth that will avoid intolerable gain pumping, we must make a judgment call based on an empirical measurement. In this example, we estimate that 0.5 dB p-p gain pumping is acceptable. Using a spectrum analyzer with very wide resolution bandwidth, zero span, and a linear detector, we

Insert figure 9. AGC Loop Design Example VGA output level By doing a sweep of ACP vs. output power it can be verified that the best ACPR for the chosen frequency occurs at a VGA output level of 9 dBm, which means that the IMD3 power in the adjacent channel roughly equals the noise power in the adjacent channel. From an earlier discussion, the distortion power within the channel is about 9 dB higher than the in-channel

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can estimate the desired loop bandwidth by passing a modulated signal through the spectrum analyzer to see the video bandwidth results in 0.5 dB p-p output variation. In this instance, result is 200 Hz. If necessary, this 200 Hz loop bandwidth can be re-adjusted later. RMS Detector Filter The RMS detectors mean value filter comprises an internal filter resistance combined with an external shunt capacitance. The effective value of the filter resistance varies with drive level, from about 2000 at a very low drive level down to about 500 at a maximum drive level. For this example we will work with a value of 1.8 K. In general, we should ascertain a suitable filter capacitance for the AD8361 rms detector by driving the circuit with a WCDMA signal. However, the previous measurement for loop bandwidth allows us to make a reasonable estimate of the required value. We found that a loop bandwidth of 200 Hz resulted in a 0.5 dB (~6%) p-p variation of detector output. This is roughly the maximum acceptable variation of RMS filter level that still gives good RMS accuracy. So, simply make the bandwidth of this filter equal to 200 Hz, which requires a filter capacitor of about 0.44 uF against the 1.8 K filter resistance. AGC Loop Design AD8367 VGA delivers optimum noise and distortion at an output power of 12 dBm Set attenuation between VGA and detector to prevent clipping Set RMS detector bandwidth and AGC Loop bandwidth to 200 Hz Loop bandwidth only applies for small input deviations Loop Dynamics Design We will be developing a first order loop with a small-signal bandwidth of 200 Hz. Note that the RMS detectors filter already contributes one pole at 200 Hz, so the remainder of the loop needs to take this into account. This will be achieved by choosing RCOMP to create a zero at 200 Hz in conjunction with CINTEG. The response speed of all the other elements in the loop is so much faster than that of the desired loop that we can safely ignore all other poles.

Remember that the loop bandwidth we are designing will apply only for small deviations from the AGC loops equilibrium level. Large transients will behave differently because of the nonlinear character of the loop. VGA Gain From a loop dynamics perspective, the next step is to determine the incremental gains of the VGA and of the detector. In the case of the VGA and in this context, gain refers the relationship between the gain control voltage and the gain of the VGA. Use Vin and Vout to represent rms values of the VGAs RF input and output, respectively and Vg represents the gain control voltage. After reviewing the data sheet for data performance of the AD8367 for 240 MHz combined with a bit of extrapolation and rounding, it can be said that 0 dB of gain occurs at a control voltage of 0.1 V and that the control slope is exactly 50 dB/V. First write the equation relating Vout to Vin and Vg, then differentiate Vout with respect to Vg to obtain the incremental slope needed. Notice that the slope can be expressed as a function of Vout (when the equilibrium value is known) and Vg, without direct knowledge of Vin. (1) GAIN = 10(50 * (Vg 0.1) / 20) where: 50 is the VGA control slope in dB/V, and 0.1 is the gain intercept (the control voltage giving unity gain) (2) VOUT = VIN * GAIN Combining (1) with (2), rearranging and multiplying yields: (3) VOUT = VIN * 10(-0.25) * 10(2.5 * Vg) Now differentiate Vout with respect to Vg to obtain the incremental slope: (4) dVout/dVg = Vin*10(-0.25) * 10(2.5*Vg) * ln(10) * 2.5 Next substitute (3) into (4) and evaluate ln(10) * 2.5 to get: (5) dVout/dVg = Vout*ln(10) * 2.5 = Vout * 5.75646

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At equilibrium, Vout is 112 mV (explained earlier); the incremental slope then evaluates to 0.112 * 5.756 = 0.6447 Vrms/V.
GAIN = 10(50 * (Vg 0.1) / 20) VOUT = VIN * GAIN VOUT = VIN * 10(-0.25) * 10(2.5 * Vg) dVOUT/dVg = VIN*10
(-0.25)

(1) (2)

There is a practical constraint which is the AD8361 cannot source very much current, and can sink even less. Therefore make the value of Rin fairly high, and also provide a pulldown at the AD8361s output to improve current sinking. Choose a rather high value of 50 k for Rin in order to minimize total loading on the AD8361s output that leads to a value of 12.78 nF for Cinteg. Finally, choose the value of Rcomp to provide a loop zero at 200 Hz with Cinteg, which requires a value of 62.3 k. Circuit Tests The exact circuit that was implemented is shown in Figure 10. The measured step response shows excellent agreement with simulation (Figure 11). Figure 12 shows the measured gain pumping, obtained by capturing the signal at the gaincontrol input of the VGA with an oscilloscope and scaling into dB.

* 10

(2.5*Vg)

* ln(10)* 2.5

(3) (4) (5)

dVOUT/dVg = Vout*ln(10) * 2.5 = Vout * 5.75646 Incremental Slope = 0.112 * 5.756 = 0.6447 Vrms/V

The nominal conversion gain of the AD8361 rms detector is 7.5, from the rms value of the input to the DC output. However, remember a 90 series resistor was placed at the input of the detector in order to help obtain the desired alignment of signal levels at various points in the system. This has the effect of reducing the detectors effective gain to 5.357, which is the value used in the loop analysis. Overdrive Recovery Recovery time from overload can be adversely affected if the output of the integrator stage is permitted to severely overdrive the gain control input of the VGA. This situation would arise if the loop is left sitting for a while with a very low (or zero) input signal level. In an effort by the loop to find more gain, the output voltage of the integrator would continue to rise until it reached saturation of the op amp. A big problem arises when a significant signal does finally arrive at the system input. Before the loop can begin reducing the gain, wait for the integrators output to ramp back down to 1 V, which takes a while. In our circuit the maximum output voltage of the integrator is nearly 5 V, while the maximum useful control input to the AD8367 VGA is about 1.0 V. Therefore insert a resistive voltage divider of slightly less than 5:1 in the AGC path. Calculation Of Component Values In the loop there is a net gain (momentarily excluding the integrator) of 0.644 (VGA incremental slope) * 5.357 (effective detector slope) / 4.3 (Vagc atten) = 0.803. For a loop bandwidth of 200 Hz the loop gain should be unity at that frequency. If the rest of the loop has a gain of 0.803, the integrator must have have a gain of 1.0 / 0.803 = 1.245, which requires that the reactance of Cinteg at 200 Hz be 1.245 times the value of Rin. Mathematically, 1 / (2 * 200 * Cinteg) = 1.245 * Rin; Rin * Cinteg = 639.2 s.

Figure 10. Complete AGC Circuit


Figure 17. Measured Breadboard AGC Response to 30 dB Steps
25 20 15 10 5 0 Po (dBx) -5 -10 -15 -20 -25 -30 -35 0 0.005 0.01 Time (sec) 0.015 0.02

Figure 11. Measured AGC Response to 30 dB Positive and Negative Input Steps

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Figure 18. Measured Gain Pumping for Breadboard AGC Loop


0.15

AD8368 IF VGA Key Features Analog Variable Gain Range: -12 to 22dB Linear-in-dB Scaling: 40dB/V 3dB Bandwidth: 800 MHz Integrated RMS Detector and AGC Mode Output 1dB Compression: 17 dBm Output IP3: 33 dBm Noise Figure: 9 dB Input and Output Impedances: 50
0 0.02 0.04 Time (sec) 0.06 0.08 0.1

0.1

dB Gain Variation

0.05

-0.05

-0.1

Figure 12. Gain pumping of AGC Example Circuit Fine Tuning The Circuit When the circuit was first tested, some unexpected overshoot (a few percent) was noted on the recovery from small amplitude steps. This was traced to an unexpectedly long detector time constant, suggesting that the rms filter capacitor had too large a value. The capacitors value was originally calculated from an assumed value of 1.0 K for the detectors internal filter resistance, which was too low. Reducing the capacitor to 0.44 uF in the circuit solved the problem. AD8368 - A VGA With A Built-In Variable Setpoint AGC The Analog Devices AD8368 is a variable gain amplifier with analog linear-in-dB gain control that can be used from low frequencies to a few hundred MHz. Its excellent gain control range, conformance and flatness are attributed to Analog Devices X-AMP TM architecture. The gain range of -12 to 22 dB is scaled accurately to 40 dB/V with low conformance error. The AD8368 has a 3-dB bandwidth of 800 MHz that is independent of gain setting. At 70 MHz, the OIP3 and P1dB are 33 dBm and 17 dBm, respectively. The output noise floor is 143 dBm/Hz, which corresponds to 9 dB noise figure at maximum gain. The single-ended input and output impedances are 50 . The gain of the AD8368 can be configured to be an increasing or decreasing function of the gain control voltage depending on whether the MODE pin is pulled to the positive supply or to ground, respectively.

The AD8368 may be used as an AGC amplifier as shown in Figure 13. For this application, the accurate internal square-law detector is employed. The output of this detector is a current that varies in polarity depending on whether the rms value of the output is greater or less than its internally determined set point of -11 dBm. This is 178mV pk-pk for sine-wave signals, but the peak amplitude for other signals, such as Gaussian noise or those carrying complex modulation, will invariably be somewhat greater. However, for all waveforms having a reasonable crest factor (less than 13 dB), the rms value will be correctly measured and delivered at VOUT. The output setpoint may be adjusted using an external resistive divider network as depicted in Figure 13. In this configuration the RMS output voltage will be equal to (1+n)63mVrms, where n=R2/R1. For the default set-point of 63mVrms simply short R1 (direct connection from OUTP to DETI) and remove R2.

Figure 13. AD8368 IVGA with 34dB Gain Control Range with on-board AGC Detector

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The AGC mode of operation requires choosing the correct gain direction. Specifically, the gain must fall as VAGC increases to restore the needed balance against the set-point. Therefore, the MODE pin must be pulled low. This very accurate leveling function is shown in Figure 14, where the rms output is held to within 0.2 dB of the set point for >30 dB range of input levels. This measurement was made using R1 = 100 and R2 = 226 to achieve 0 dBm output level.

AD8368 IF VGA AGC Mode On-board AGC circuit settles to -11 dBm rms AGC setpoint can be increased using attenuator between IF output and detector input Sense of VGA gain control can be reversed to enable AGC mode AGC gain control voltage provides RMS RSSI output A valuable feature of using a square law detector is that the RSSI voltage is a true reflection of signal power, and may be converted to an absolute power measurement for any given source impedance. The AD8368 may be employed as a true-power meter by monitoring the voltage present at the DETO/GAIN interface (Figure 15). Figure 16 illustrates the measured error-vectormagnitude (EVM) performance for a 16-QAM modulation at 10MSymbols/sec using CDETO=1000pF. At lower symbol rates the AGC loop could start to track the peak to peak transitions due to the modulation (gain pumping). At lower symbol rates it may be necessary to slow down the response of the AGC loop by increasing the value of CDETO .

Figure 14. Output Power versus Input Power in AGC Mode at 140MHz.

Figure 15. Monitoring the GAIN/DETO RSSI Voltage versus Input Power.

Figure 16. Error Vector Magnitude vs. Input Power for 16-QAM Carrier at 10Msymbols/sec.

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Chapter IX Using Calibration and Temperature Compensation to improve RF Power Detector Accuracy
By Carlos Calvo and Anthony Mazzei Introduction Accurate RF power management is a critical issue in modern wireless transmitters, offering a variety of benefits ranging from power amplifier protection in base-stations to battery conservation in mobile applications. RF power detectors, such as logarithmic amplifiers, allow RF power management systems to monitor and dynamically adjust the transmitted power over a wide range. Although the accuracy of power detection has significantly improved in recent years, applications such as those requiring high power transmission are dramatically affected even by fractions of a dB of power detection error. As a result, there is a continuous push for tighter detector performance. Using a combination of a logarithmic amplifier and a temperature sensor it is possible to design a temperature compensation scheme to significantly reduce the contributions of the two major error factors in RF power management, temperature and process variations. In some cases, the temperature compensation hardware is integrated onto the power detector chip. RF Power Management RF Power Management is Critical in Modern Wireless Transmitters Preserves Battery Current in Terminals Protects High Power Amplifiers RF Detectors Enable Measurement and Control of RF Power High RF Power Measurement Precision Can Be Achieved Using Temperature Sensors and On-Board Temperature Compensation RF Power Management at a Glance Accurate RF power management in base-stations is of high importance. Overdriving the transmitting power amplifier beyond the necessary output power level can be costly. Excessive current usage will result in higher expenses and also introduces thermal dissipation issues requiring more thermal relief. In the extreme case, overdriving the power amplifier can lead to reliability issues resulting from burnout failures. The added benefits of accurate RF power management in base-stations also transcend to mobile transmitters as they have similar demands. With the ability to accurately control the output power, the mobile device can minimize supply current expenditures. For instance, RF power management allows the transmitted power to be precisely limited to the minimum required power level reducing battery current Accurately controlling the power will extend talk time while still permitting the mobile transmitters to meet the cellular standard requirements. A Typical Wireless Transmitter with RF Power Control Figure 1 shows a block diagram of a typical RF transmitter with integrated power management. The transmit signal path consists three consecutive stages base-band, radio, and power amplifier.

Figure 1. RF power management circuits use logarithmic amplifiers to take advantage of the their wide linear-in-dB detection range. A portion of the transmitted signal is sampled by the directional coupler before it reaches the antenna. The sampled RF power is delivered to the power detector where it is converted to a DC voltage. The output voltage of the power detector is digitized and fed to the digital signal processor (DSP) or the microcontroller. Once the power measurement is available as a digital

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level, a decision is made based on the measured output power versus the desired output power. The microcontroller will adjust the output power using a digital to analog converter (DAC) and a variable gain amplifier (VGA) to drive the signal path power control either at the base-band, radio, or power amplifier. The RF power management loop will reach steady-state once the measured output power and the desired output power are balanced. A temperature sensor can also be introduce as an input to the microcontroller to add temperature compensation capabilities. A similar RF power management loop can be implemented using only analog circuitry in transmitters. Implementing RF Power Control With Digital Control, Detector Output Is Sampled By An ADC DAC Adjusts Gain In Signal Chain To Achieve Desired Output Power External Temperature Sensor Helps Compensate For Drift of Detector Analog Control Loop Can Also Be Implemented Historically, diode detectors have been used in RF power management circuitry to regulate transmitted power. They offer good temperature stability at high input power levels, but have poor performance at low power levels. Even with temperature compensation circuitry, a diode detector can only offer a small detection range with worsening temperature performance at low input powers. A popular alternative to the diode detector is the demodulating logarithmic amplifier. The logarithmic amplifier offers an easy to use linear-in-dB RF power detection response with a wide dynamic range.

In the block diagram, there are four 10 dB cascaded limiting amplifiers that make up the progressive compression chain. Five full-wave rectifier detector cells convert the RF signal voltages to currents one detector cell at the RF input and four at the outputs of the amplifier stages. The currents generated by the detector cells are proportional to the average of the voltage signal levels and are added together to approximate a logarithmic function. The sum of currents in converted to a voltage with a highgain stage. The five detector cells across the four 10 dB amplifier stages allow the logarithmic amplifier to have a 50 dB detection range.

Figure 2. Five detector cells across four 10 dB amplifier stages allow the progressive compression logarithmic amplifier to have a 50 dB detection range. Figure 3 shows the transfer function a 60 dB logarithmic amplifier. There is a linear relationship between the RF input power and the output voltage, that is, as the input power increases, the output voltage follows in a linearin-dB fashion. The figure also includes a logarithmic conformance error curve. The conformance error curve serves to more closely examine the logarithmic amplifiers performance. The slope and x-axis intercept of the curve are calculated over the linear part of the detection range, highlighted in grey. This information provides a simple linear model to compare with the actual response of the logarithmic amplifier. The ideal linear reference model is represented by the dashed-line in the plot. The comparison of the ideal linear model to the transfer function yields the logarithmic conformance error curves scaled in dB.

A 50 dB Log Amp With Operation Up To 3.5 GHz Figure 2 shows the block diagram of a progressive compression logarithmic amplifier. This is a complete, low cost subsystem for the measurement of RF signals in the frequency range of 50 MHz to 3.5 GHz. It has a typical dynamic range of 45 dB and is intended for use in a wide variety of cellular handsets and other wireless devices. It provides a wider dynamic range and better accuracy than using discrete diode detectors. In particular, its temperature stability is excellent over the full operating range of 40C to +85C.

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Figure 3. An ideal reference model calculated over the linear part of the detection range is used to compare with the actual response of the logarithmic amplifier. The comparison yields a logarithmic conformance error curve. The method of calculating logarithmic conformance error is similar to the two-point calibration technique used in RF power management system calibration. During production testing, two known RF signal strengths are chosen in the linear range of the detector. Using the resulting voltage outputs, the slope and intercept characteristics of the response are calculated and stored in non-volatile memory to form a simple linear equation. The transmitted power in the field can then be easily calculated using the linear-in-dB function and the measured detector voltage. There are the considerable benefits of reduced cost and trimmed test time by using only two points at calibration. However, this calibration practice is only possible due to the log amps linear performance. Log Conformance Calculations Conformance error curves serve to examine the log amp's performance The slope and intercept are calculated over the linear part of the detection range The comparison of the ideal linear model to the transfer function yields the logarithmic conformance error curves scaled in dB Error calculation method is similar to the two-point calibration technique used in system calibration Once ideal model is established, transmitted power can be calculated using the linear-in-dB function and the measured detector voltage

Because calibration is generally done at a single temperature, the effects of temperature on the detector are important to quantify. The accuracy of a detector over temperature can be expressed in terms of conformance error. Figure 4 shows the transfer function at 900 MHz. The plot includes the transfer functions at -40C and +85C, as well as the logarithmic conformance error curves over temperature. As would be the case with two-point calibration, the same 25C linear reference is used to generate the three linear conformance error curves.

Figure 4. The logarithmic conformance error at 900 MHz of a single log detector device shows an accuracy of 0.5 dB over temperature. The transfer function of the logarithmic amplifier at 25C ambient temperature has a slope of 50.25 dB/V and a -51.6 dBm intercept (the point at which the extrapolated linear reference would intersect with the x-axis). The curve at 25C hovers around the 0 dB error line, while the temperate extremes have minor slope and intercept shifts. The logarithmic conformance error of this single device across temperature stays within 0.5 dB across a 40 dB detection range. The temperature drift at +85C is the limitation to the dynamic range. Individual devices may have excellent accuracy over temperature, however, minor part-to-part variations inherent in semiconductor processing can prove to be an obstacle to precise RF power management. Figure 5 shows the distribution of logarithmic conformance error curves of 70 multiple devices. The sampling of devices spans across various lots to demonstrate process variations. Each device has three temperature curves calibrated to its 25C linear reference. Although there is a

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clear variation from part-to-part, the distribution is very tight. The population of device over temperature has an accuracy of 1 dB over more than 40 dB of detection range. Temperature compensation can be introduced due to the repeatable drift from part-to-part.

Figure 6 shows the logarithmic conformance error curves for a large number devices. At 3.5 GHz, the temperature drift is spread out from +1 dB to -4 dB. The population at -40C follows the 25C curves closely. In contrast, the distribution at +85C is shifted by 2.5 dB and is no longer parallel to the 25C distribution. Although the temperature drift at this frequency is sizeable, the distribution at each particular temperature remains very tight. Because of this drift repeatability, a compensation scheme can be implemented to dramatically improve the accuracy.

Figure 5. There is a clear variation in logarithmic conformance error curves from partto-part, however, the distribution is very tight. Temperature compensation can be introduced due to the repeatable temperature drift. Typically wireless communication standards require 1 dB and 2 dB accuracy from transmit power detection schemes with relaxed limits at extreme temperatures. The raw accuracy of the logarithmic amplifier is sufficient to meet most standards without any fine tuning. Still, there are clear advantages associated with exceeding the RF power management requirements set by the different standards. Digital Compensation Of Errors As previously discussed, the microcontroller can actively adjust the transmitted power by biasing the transmit signal path. By adding a temperature sensor, the microcontroller can further increase the accuracy of a RF power management system. As long as the detector has repeatable temperature drift, some level of error compensation is possible. Compensation routines taking into account environmental changes can be integrated in the microcontrollers decision making to significantly reduce or eliminate process and temperature variations. For example, if a power detector repeatedly drifts with temperature, a compensation algorithm can be implement to remove the expected error at the known temperature.

Figure 6. At 3.5 GHz, the temperature drift distribution at +85C is shifted and no longer parallel to the 25C distribution. A trend line through the linear region of the +85C logarithmic conformance curves represents the error model at that temperature. Over temperature there are slope and intercept variations that lead to temperature drift. With this in mind, an error model can be derived by analyzing the population of devices. An error function expressing the movement of the population over temperature can be created, as shown in Figure 6. A trend line is drawn through the linear region of the +85C log conformance curves to represent the error model at +85C, error+85 C. Using the slope and intercept characteristics of the error line, a complimentary function can be used to cancel out the temperature variation. Still, the model only represents the error introduced by the +85C temperature drift. The majority of the temperature drift occurs linearly between 25C and +85C. A generalized error function for all temperatures in that range can be created using a scaling factor, k(T), which is a function of temperature. The combination of

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the complimentary error function and the temperature scaling function are combined as shown in Figure 7. As the temperature increases, the scaling factor will track and eliminate the error caused by the rising temperature drift.

Figure 7. A complimentary error function is used to cancel out temperature variation. The logarithmic conformance error over the full temperature range is improved with error compensation. Figure 7 shows the distribution of logarithmic conformance using the error compensation scheme described. Before compensation, the logarithmic conformance error spanned 5 dB. With the incorporation of error compensation, the logarithmic conformance error over the full temperature range is improved to approximately 0.5 dB from -30 dBm to 0 dBm. The achievable accuracy of a RF power management system is determined by the distribution of the population of devices. Similar results are also possible at lower temperatures and lower frequencies where temperature drift is not as significant. Error Compensation Method Over temperature, slope and intercept variations lead to temperature drift. An error function can be created to express the movement of the distribution over temperature A function complimentary to the error is used to cancel out the temperature variation

A 60 dB Log Amp with Analog Temperature Compensation Figure 8 shows the block diagram of the AD8318, a demodulating logarithmic amplifier capable of accurately converting an RF input signal to a corresponding decibel-scaled output voltage. It also employs a progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in measurement or controller mode. The AD8318 maintains accurate log conformance for signals of 1 MHz to 6 GHz and provides useful operation to 8 GHz. The input range is typically 60 dB (re: 50 ) with error less than 1 dB. The AD8318 has a 10 ns response time that enables RF burst detection to beyond 60 MHz. The device provides unprecedented logarithmic intercept stability versus ambient temperature conditions. A 2 mV/K slope temperature sensor output is also provided for additional system monitoring.
VPSI ENBL TADJ VPSO

TEMP

TEMP SENSOR

GAIN BIAS

SLOPE

VSET

I DET INHI INLO DET DET DET

VOUT

CLPF

CMIP

CMOP

Figure 8. Block diagram of the AD8318 progressive compression logarithmic amplifier with 60 dB log conformance for signals of 1 MHz to 8 GHz Through the life span of a semiconductor process there are variations in its parameters, such as sheet resistance, capacitance, and beta. All of these variants influence the slope, intercept, and temperature performance of the detectors. A method to mitigate the influence of process variation is to use a laser-trimmed logarithmic amplifier. Figure 9 shows a distribution of logarithmic conformance of the AD8318, a trimmed 60 dB logarithmic amplifier, at 1.9 GHz. Instead of digital compensation, the device uses on-board temperature circuitry and an external resistor to optimize temperature performance. The value of the resistor is dependant on the required magnitude of the correction coefficient. The analog compensation circuit alone achieves a tight distribution with 0.5 dB in the central detection range.

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04853-001

Figure 9. Instead of digital compensation, a laser-trimmed logarithmic amplifier using analog compensation circuitry can achieve accurate RF power management.

Summary With accurate RF power management, basestations and mobile transmitters can benefit from power amplifier protection and reduced power consumption while dramatically surpassing cellular standard requirements. Using a stable logarithmic amplifier and a temperature sensor, microcontrollers can compensate for temperature drift errors to improve the overall accuracy of a RF power management system. Logarithmic amplifiers with tight temperature distributions allow for simple error compensation. Two point calibration with a moderate amount of temperature drift characterization can set the stage for accurate RF power management of 0.5 dB over temperature.

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Chapter X Measuring VSWR and Gain in Wireless Systems


By Eamon Nash Introduction Measurement and control of gain and reflected power in wireless transmitters are critical auxiliary functions that are often overlooked. The power reflected back from an antenna is specified using either the Voltage Standing Wave Ratio (VSWR) or Reflection Coefficient (also referred to as Return Loss). Poor VSWR can cause shadowing in a TV broadcast system as the signal reflected off the antenna reflects again off the power amplifier and is then rebroadcast. In wireless communications systems, shadowing will produce multi-path-like phenomena. While poor VSWR can degrade transmission quality, the catastrophic VSWR that results from damage to co-axial cable or to an antenna can, at its worst, destroy the transmitter. The gain of a signal chain is measured and controlled as part of the overall effort to regulate the transmitted power level. If too much or too little power is transmitted, the result will be either violation of emissions regulations or a poor quality link. Reflection Coefficient is calculated by measuring the ratio between forward and reverse power. Gain, on the other hand, is calculated by measuring input and output power. The high commonality of hardware used to measure gain and VSWR can reduce overall component count. This article will focus on techniques that can be used to perform these insitu measurements in wireless transmitters. A typical Wireless Transmitter Figure 1 shows a typical wireless transmitter. This consists of mixed-signal baseband circuitry, an up-converter (which generally includes one or more intermediate frequencies or IFs), amplifiers, filters and a power amplifier. These components may be located on different PCBs or may even be physically separated. In Figure 1, for example, an indoor unit is connected to an outdoor unit with a cable. In such a configuration both units may be expected to have well defined, temperature stable gains (this is especially true if the two units were made by different vendors). Alternatively, each unit might be expected to deliver a well defined output power.

Figure 1. Output Power is regulated by measuring output power and then adjusting the VGA gain. Gain is regulated by measuring both input and output power and then adjusting the VGA gain. So, there are two different approaches to the ultimate goal of delivering a known power level to the antenna; Power Control or Gain Control. With Power Control, the system relies on being able to precisely measure output power (using Detector D in this example). Once output power has been measured, the gain of some component in the system (in this case it might be the IF VGA) is varied until the correct output power is measured at the antenna. It is not necessary to know the gain of the circuit or the exact input signal amplitude; it's just a matter of varying gain or input signal until the output power is correct. This approach is often (incorrectly) referred to as Automatic Gain Control or AGC. To be correct, it should be referred to as Automatic Power Control or APC since it is power not gain that is being precisely regulated. Gain Control takes a different approach. Here, at least two power detectors are used to precisely regulate the gain of the complete signal chain or a part thereof. The ultimate goal of precisely setting the output power is then achieved by applying a known input signal to the signal chain. A number of factors ultimately determine which approach is used. Power control requires only one power detector and makes sense in a nonconfigurable transmitter whose components are fixed. So, for example, power could be measured

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at the output of the RF HPA but adjustments would be made using the IF VGA. Gain Control, on the other hand, may make more sense in a reconfigurable system whose components come from different vendors. In Figure 1 the input power and output power at the HPA are being measured (using Detectors C and D) so the gain can be regulated independent of the other blocks in the circuit. Note that the power/gain control loops can be all-analog or microprocessor based. Using Gain Control to regulate the gain of the complete signal chain in Figure 1 would be less practical since the two required detector signals (Detector A and Detector D) are physically remote from one another. A more practical approach would be to independently control the gain of the Indoor and Outdoor units. RF Detectors Until recently, most RF power detectors were built using a temperature-compensated half-wave rectifying diode circuit. These devices deliver an output voltage that is proportional to the input voltage over a limited dynamic range (typically 20 to 30 dB). As a result, the relationship between output voltage and input power in dBm is exponential (Figure 2). While the temperature stability of a temperature-compensated diode detector is excellent at high input powers (+10 to +15 dBm), it degrades significantly as input drive is reduced.

input signal over a large dynamic range (up to 100 dB). Temperature stability is usually constant over the complete dynamic range. A log-responding device offers a key advantage in gain and VSWR measurement applications. In order to compute gain or reflection loss, the ratio of the two signal powers (either OUTPUT/INPUT or REVERSE/FORWARD) must be calculated (Figure 3). An analog divider must be used to perform this calculation with a linear-responding diode detector, but only simple subtraction is required when using a logresponding detector (since Log (A/B) = Log(A) Log (B)).

Figure 3. To perform a ratio (gain) calculation using linear in V/V responding diode detectors, analog division must be performed. Using logresponding detectors (log-amps), a ratio calculation can be performed using simple subtraction. A dual RF Detector has an additional advantage compared to a discrete implementation. There is a natural tendency for two devices (RF Detectors in this case) to behave similarly when they are fabricated on a single piece of silicon, with both devices having similar temperature drift characteristics, for example. At the summing node, this drift will cancel to yield a more temperature-stable result. A Dual RMS Responding RF Detector The AD8364 is a true rms, responding, dualchannel RF power measurement subsystem for the precise measurement and control of signal power. The flexibility of the AD8364 allows communications systems, such as RF power amplifiers and radio transceiver AGC circuits, to be monitored and controlled with ease. Operating on a single 5 V supply, each channel is fully specified for operation up to 2.7 GHz over a dynamic range of 60 dB. The AD8364 provides accurately scaled, independent, rms outputs of both RF measurement channels. Difference output ports, which measure the difference between the two channels, are also available. The on-chip channel matching makes the rms channel

Figure 2. Diode Detectors measure signal strength over a narrow range and provide an output voltage which is exponentially related to input power in dBm. Log detectors provide an output voltage which is directly proportional to the input power in dBm. A log detector, on the other hand, delivers an output voltage proportional to the log of the

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difference outputs extremely stable with temperature and process variations. The device also includes a useful temperature sensor with an accurately scaled voltage proportional to temperature, specified over the device operating temperature range. The AD8364 can be used with input signals having rms values from 55 dBm to +5 dBm referred to 50 and large crest factors with no accuracy degradation.

and OUTB is available as differential or singleended signals at OUTP and OUTN. An optional voltage applied to VLVL provides a common mode reference level to offset OUTP and OUTN above ground. Gain Measurement Example Figure 5 shows a transmitter whose gain is regulated using a dual power detector. The simplified transmit signal chain shown consists of a high-performance IF-synthesizing DAC, VGA, mixer/upconverter, and High-Power Amplifier. High-performance DACs, such as the AD9786 and AD9779, that run at sampling frequencies up to 500 MSPS and beyond are capable of synthesizing Intermediate Frequency outputs (100 MHz in this example). The output of the DAC is Nyquist filtered using a band-pass filter before being applied to a ADL5330 variable gain amplifier. Conveniently, the amplifier accepts a differential input that can be tied directly to the output of the differential filter. This, in turn, is tied to the DAC output. The VGA output is converted from differential to single-ended using a balun transformer, and is then applied to the ADL5350 mixer . After appropriate filtering (not shown), the signal is amplified and transmitted at a maximum output power level of 30 watts (approximately +45 dBm).

Figure 4. AD8364 Dual RMS Responding 60 dB RF Detector Functional Block Diagram The device can easily be configured to provide four rms measurements simultaneously. Linearin-dB rms measurements are supplied at OUTA and OUTB, with conveniently scaled slopes of 50 mV/dB. The rms difference between OUTA

Figure 5. A dual Power Detector can be used to measure and control the gain of a signal chain even when the input and output frequencies are different.

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The gain of the signal chain is measured by detecting the power at the DAC output and at the output of the HPA. Gain is then regulated by adjusting the gain of a VGA. At the DAC and PA outputs, a sample of the signal is taken and fed to the detectors. At the HPA output, a directional coupler is used to tap off some of the power going to the antenna. While an asymmetrical power splitter could also be used, a directional coupler results in lower insertion loss (little or no power is consumed in the coupler) and tends to reject any signals that are received on the antenna (in-band or out-ofband blockers). A 20 dB directional coupler is be used in this example, but the coupling factor could be much lower, since the signal must be attenuated before being applied to the power detector. Directional couplers with lower coupling factors have the added advantage of even lower insertion loss. The transfer function of the AD8364 dual detector shows that at the output frequency used (2140 MHz in this case), the detector has the best linearity and most stable temperature drift at power levels below 10 dBm. Thus, the power coming from the directional coupler (+25 dBm max) must be attenuated before being applied to the detector. If maximizing detector dynamic range is not critical to the application, the attenuation can be conservatively set at 41 dB so that the detector sees a maximum input power of 16 dBm. This still leaves about 34 dB of useful dynamic range over which the gain can be controlled. When using single-chip dual power detectors, attention must be paid to RF feed through. In general, when one input power is about 40 dB below the other, measurement accuracy suffers. In this application, the input power levels to both detectors are equal when the system is at full power. So, the maximum power level at the input detector has also been set to 16 dBm. To detect the input Power level at the DAC output, a directional coupler is impractical at this low frequency. In addition, directional coupling is not necessary since there will be little or no reflected signal at this point in the circuit. Furthermore, the power being delivered to the VGA is 10 dBm, so the power to be delivered to the detector is only 6 dB lower. The detector

has an input impedance of 200 ohms and the VGA has an input impedance of 50 ohms, so it quickly becomes clear that the two devices can simply be connected in parallel. With the same voltage present at both inputs, the 50-to-200 ohm impedance ratio will result in a convenient 6 dB power difference. Where high measurement precision is required, care must be paid to the temperature stability of the power detectors. This issue is further complicated if the temperature drift characteristics of the detectors change with frequency. The dual detector shown provides temperature compensation nodes.

Figure 6. The operating input range of a detector should be chosen so that the detector always sees a power level which is well within its linear operating range, between 10 dBm and 50 dBm in this case. Temperature compensation is activated by connecting a voltage to the ADJ pins of each detector (this voltage can be conveniently derived using a resistor divider from the 2.5 V on-chip reference). No compensation is required for the low frequency input (ADJB is grounded), while a 1.0-V compensation voltage is required at ADJA to minimize temperature drift at 2.1 GHz. While the focus of the application circuit in Figure 5 is gain measurement, it should be noted that input power and output power can also be measured. The outputs of the individual detectors are available and can be separately sampled. Because the detectors are log-responding, their outputs can be simply subtracted to yield gain. This subtraction is performed on chip and the gain result is delivered as a differential voltage. The full-scale differential voltage is

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Gain(dB)

approximately 4 V (biased up to 2.5 V) with a slope of 100 mV/dB. Digitizing with a 10-bit ADC with an LSB size of ~10 mV (5 V fullscale), 0.1-dB measurement resolution is achievable. An Analog Gain Control Loop A dual RMS-responding detector operating in Controller Mode can also be used to control the gain of an HPA very accurately vs. input power, temperature, and crest factor. If the gain of an HPA module is controlled with enough accuracy over input power, temperature, and crest factor, the HPA modules output power would not have to be reported but would be directly related to the power feeding it. If both inputs of a dual detector are put in Controller Mode, the detector determines the power at each input and adjusts the gain of a VGA until the power detected on one input is equal to the power on the other. Figure 7 shows a basic schematic of the AD8364 (dual RMS detector) used to control the gain of a system. Figure 8 shows the performance of this setup. Everything that needs to be accurately controlled should be included between the two couplers. Note that a VGA, variable attenuator, or even the bias of the HPA can be used to control the gain. If the control levels between the detector and VGA are set properly and power levels are properly designed for, the usable input power range will be close to the detectable power range of the detector (60 dB, in the case of the AD8364).

22 21 21 21 21 20 20 20 20 19 19 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15
Gain -40 Deg C Gain -20 Deg C Gain 25 Deg C Gain 85 Deg C

Pin(dBm)

Figure 8. When both inputs of Analog Devices dual RMS detector (AD8364) are put in Controller Mode, the gain is controlled to better than .15 dB vs. temperature and input power, with a dynamic range almost equal to the dynamic range of the RMS detector. A 60 dB Gain/Phase Detector The AD8302 is a fully integrated system for measuring gain/loss and phase in receive, transmit, and instrumentation applications. It requires few external components and a single supply of 2.7 V5.5 V. The ac-coupled input signals can range from 60 dBm to 0 dBm from low frequencies up to 2.7 GHz. The outputs provide an accurate measurement of either gain or loss over a 30 dB range scaled to 30 mV/dB, and of phase over a 0180 range scaled to 10 mV/degree. The AD8302 can be used in controller mode to force the gain and phase of a signal chain toward predetermined setpoints.

Figure 7. When both inputs of a dual detector are used in Controller Mode, the detector will control a VGA (or VVA, etc.) in such a way as to equalize the power it detects at both RF inputs. The gain of the system will be determined by the couplers and attenuators used to set the power being detected by the dual detector.

Figure 9. AD8302 60 dB Gain/Phase Detector The AD8302 comprises a closely matched pair of demodulating logarithmic amplifiers, each having a 60 dB measurement range. By taking the difference of their outputs, a measurement of

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the magnitude ratio or gain between the two input signals is available. These signals may even be at different frequencies, allowing the measurement of conversion gain or loss. The AD8302 may be used to determine absolute signal level by applying the unknown signal to one input and a calibrated ac reference signal to the other. With the output stage feedback connection disabled, a comparator may be realized, using the setpoint pins MSET and PSET to program the thresholds. The AD8302 includes a phase detector of the multiplier type, but with precise phase balance driven by the fully limited signals appearing at the outputs of the two logarithmic amplifiers. Thus, the phase accuracy measurement is independent of signal level over a wide range. In controller applications, the connection between the gain output pin VMAG and the setpoint control pin MSET is broken. The desired setpoint is presented to MSET and the VMAG control signal drives an appropriate external variable gain device. Likewise, the

feedback path between the phase output pin VPHS and its setpoint control pin PSET may be broken to allow operation as a phase controller. VSWR Measurement Example A dual log detector can also be used to measure the reflection coefficient of an antenna. In Figure 10, two directional couplers are used, one to measure forward power and one to measure reverse power. Additional attenuation is required before applying these signals to the detectors. The AD8302 dual detector has a measurement range of 30 dB. Each detector has a recommended input power range for good linearity and temperature stability, and care must be taken in setting the attenuation levels so the reflection coefficient can be measured over the desired output power range. The level planning used in this example is graphically depicted in Figure 11.

Figure 10. A dual log detector can be used to measure reflection coefficient of an antenna. The detector also provides a reading of the phase between forward and reverse power over a 180 degree range . Each of the AD8302's detectors has a nominal In this example, the expected output power range input range from 0 dBm to 60 dBm. In this from the HPA is 30 dB, from +20 dBm to +50 example, the maximum forward power of +50 dBm. Over this power range, we would like to be dBm is padded down to 10 dBm at the detector able to accurately measure reflection coefficients input (this is achieved through the combined from 0 dB (short or open load) up to 20 dB. coupling factor of the directional coupler and the

X-6

subsequent attenuation). This puts the maximum power at the detector comfortably within its linear operating range. Also, when the HPA is transmitting at its lowest power level of +20 dBm, the detector sees a power of 40 dBm, still well within its input range.

operating point of 90 degrees. In a VSWR application, this information constitutes the phase angle of the reflected signal (with respect to the incident signal) and may be of use in optimizing power delivered to the antenna. A Single 1 MHz to 10 GHz 60 dB Log Detector The AD8318 is a demodulating logarithmic amplifier, capable of accurately converting an RF input signal to a corresponding decibelscaled output voltage. It employs the progressive compression technique over a cascaded amplifier chain, each stage of which is equipped with a detector cell. The device can be used in measurement or controller mode. The AD8318 maintains accurate log conformance for signals of 1 MHz to 6 GHz and provides useful operation to 8 GHz. The input range is typically 60 dB with error less than 1 dB. The AD8318 has a 10 ns response time that enables RF burst detection to beyond 60 MHz. The device provides unprecedented logarithmic intercept stability versus ambient temperature conditions. A 2 mV/K slope temperature sensor output is also provided for additional system monitoring. A single supply of +5 V is required. Current consumption is typically 68 mA. Power consumption decreases to <1.5 mW when the device is disabled.

Figure 11. Careful level planning should be used to match the input power levels in a dual detector and to place these power levels within the linear operating range of the detectors. The power from the reverse path is padded down by the same amount. This means that the system is capable of measuring reflected power up to 0 dB. This may not be necessary if the system is designed to shut down when the reflection coefficient degrades below a certain minimum (e.g. 10 dB), but it is permissible because the detector has so much dynamic range. For example, when the HPA is transmitting +20 dBm, the reverse path detector will see an input power of 60 dBm if the antenna has a return loss of 20 dB. The application circuit in Figure 10 provides a direct reading of return loss, but no information is provided about the absolute forward or reverse power. If this information is required, the dual detector used in Figure 4 would be more useful because it would provide a measure of absolute forward and reflected power along with the reflection coefficient. The AD8302 dual detector used in Figure 10 also provides a phase output. Because of the large gain in the main signal path of a progressive compression log amp, a limited (amplitude saturated) version of the input signal is a natural by product. These limiter outputs are multiplied together to yield a phase detected output with a range of 180 degrees centered around an ideal

Figure 12. 8318 Dual RMS Responding 60 dB RF Detector Functional Block Diagram The AD8318 can be configured to provide a control voltage to a VGA, such as a power amplifier or a measurement output, from pin VOUT. Since the output can be used for controller applications, special attention has been paid to minimize wideband noise. In this mode, the setpoint control voltage is applied to VSET. The feedback loop through an RF amplifier is closed via VOUT; the output of which regulates the amplifiers output to a magnitude

X-7

corresponding to VSET. The AD8318 provides 0 V to 4.9 V output capability at the VOUT pin, suitable for controller applications. As a measurement device, VOUT is externally connected to VSET to produce an output voltage VOUT that is a decreasing linear-in-dB function of the RF input signal amplitude. Amplifier Gain Measurement Using a Single Log Detector and an RF Switch Figure 13 shows an alternative approach to Gain measurement which is also applicable to VSWR measurement. In this application, we again want to measure and control the gain of a PA. The PA in the example is running at 8 GHz and has an output power range from +20 dBm to +50 dBm. This is a fixed-gain PA, so the output power is adjusted by changing input power.

Two directional couplers are used to detect input and output power. There is only a single log detector, however, so the two signals are alternately connected to the detector using a single-pole, double-throw RF switch. The AD8317 detector has a 0 dBm to 50 dBm input range at this frequency. To measure Gain, the input and output powers are alternately measured and digitized. The results are then simply subtracted to yield gain. Once gain is known, this digital control loop is completed by making any necessary adjustments to the gain of the PA via a bias adjustment. The level planning for this example is shown in Figure 14. Attenuation is used so that the two input power levels at the RF switch are close together and within the input range of the detector.

Figure 13. A single detector and RF switch can be used to measure gain.

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To figure out the unknown, PIN, the equation can be rewritten as PIN1 = (VOUT1/SLOPE) - INTERCEPT Since gain is the difference in the measured input powers (we still have to factor in the different attenuation levels of the two paths), we can write GAIN = (VOUT1-VOUT2)/SLOPE So the Intercept of the detector is not required to calculate the gain. Even though the slope of a detector will change from device to device and over temperature, if Vout1 and Vout2 are close to one another (we endeavor to do this with good level planning and because of the finite input range of the detector), a typical value for the slope can be taken directly from the datasheet and used in the above calculation. Output Power Monitoring In Figure 13, power is being measured in order to calculate gain, so the system shown can also be used to monitor output power. However, this cannot be done precisely without factory calibration. To calibrate the circuit, the antenna must be temporarily replaced with a power meter. Output power and detector voltage are then be measured at two points within the linear range of the detector. These numbers would then be used to calculate the Slope and Intercept of the detector. For optimum precision, the detector includes a temperature compensation pin. A resistor is connected between this pin and ground to reduce the temperature drift to approximately 0.5 dB at the frequency of operation (8 GHz in the example shown). As a result, it is not necessary to do any additional calibration over temperature. Conclusions Because of their linear-in-dB transfer function, log amps can be easily used to measure gain and return loss. When dual devices are used very high measurement precision is achievable. In some cases, this can be achieved without factory calibration. In all cases, careful power level planning is necessary so that the power detectors are driven at power levels that offer good linearity and temperature stability.

Figure 14. The signal detected at the output of the PA is heavily attenuated so that it maps into the input range of the detector. The signal levels at the switch inputs will always be close together, making RF feed through unlikely. Precise Gain Measurement without Factory Calibration In addition to reducing component count, this gain measurement method shown in Figure 13 has a number of interesting features. Because the same circuit is being used to measure input and output power, it is possible to make precise, temperature-stable gain measurements without ever calibrating the circuit. To understand why, let's take a look at the nominal transfer function of a log detector (Figure 15).

Figure 15. Log detectors provide a convenient y=mx+b transfer function within their linear operating range at frequencies up to 10 GHz. Slope and Intercept can be calculated if necessary using a simple two-point calibration We know the standard equation that describes the operation of the device in its linear region. VOUT1 = SLOPE x (PIN1 INTERCEPT)

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Chapter XI A 2.4-GHz Direct Conversion Transmitter for WiMAX and WiBro Applications By Cecile Masse
As the 802.11 Wireless LAN market matures and with the adoption of the 802.16 WiMAX Standard, there has been a growing interest in technologies that allow delivery of higher data rates over large geographical areas. The IEEE 802.16 family of standards (802.162004 and 802.16e) are intended to provide high bandwidth wireless voice and data for residential and enterprise use. The modulation used to achieve these high data rates is OFDM (Orthogonal Frequency Division Multiplexing). WiMAX OFDM features a minimum of 256 sub-carriers up to 2048 sub-carriers, each modulated with either BPSK, QPSK, 16QAM or 64QAM modulation. Self interference is minimized by having these carriers orthogonal to each other. This standard also supports different signal bandwidths, from 1.25 MHz to 20 MHz to facilitate transmission over longer ranges and to accommodate different multipath environments. This represents a significant increase in systems profiles complexity as compared to the Wi-Fi 802.11 standard, mostly to guarantee a wider, more efficient, more robust network. More subcarriers and variable length guard intervals contribute to this enhancement. The composite signal envelope amplitude of the OFDM signal can exhibit significant peaks and valleys, so, theoretically, there is a possibility that the signals on each individual carrier reach their peaks at the same time, contributing to a peak-to-average ratio (PAR) of 10 * log(256) = 24 dB. In practice, WiMAX 256OFDM exhibits a PAR of about 12 dB. Still, this imposes significant constraints on the transmitters linearity, and requires large power back-off. On the other hand, the higher the transmitted signal data rate is, the higher the signal-to-noise ratio (SNR) requirement for the transmitter and receiver becomes. In 64QAM OFDM, the limited symbol decision area dictates an SNR of at least 30 dB. This SNR requirement can easily be translated into an EVM specification equivalent to the total amount of amplitude and phase distortion. For 64QAM, the equivalent EVM specification is 31.4dB or 2.7%. This challenging specification imposes very low phase noise for the LO, as well as tight I and Q matching before the up-conversion. Many licensed or un-licensed RF bands, ranging from 0.7 GHz to 5.8 GHz, have been identified for WiMAX applications. But most of the initial designs are targeting frequency bands at 2.5 GHz and 3.5 GHz. WiBro is the Korean WiMAX mobile standard in the 2.3 GHz to 2.4 GHz band. This article proposes a direct-conversion transmit signal chain for this particular band of interest. Measurement results are also presented which demonstrate system level performance for WiMAX applications. Architecture To address the challenging requirements of the 802.16 standard, the transmit signal chain may be based on radio architectures like superheterodyne, IF sampling or zero-IF.
Dual DACs
AD9862

IQ MODULATOR
AD8349

RF VGA
ADL5330
0o 90o

DAC DAC

RMS POWER DETECTOR


AD8362

FRACTIONAL-N SYNTHESIZER
ADF4153

Fig 1. Architectural Block diagram At 2.35 GHz, a direct up-conversion architecture is attractive for the following reasons: state of the art synthesizers and IQ modulators still perform well at this frequency, WiMAX OFDM has no active subcarrier at the origin, direct up-conversion produces less mixing product spurs, it requires fewer filters which is important when dealing with wideband signals, and the lower number of parts helps minimize the current consumption. Finally, in multi-carrier modulation schemes like WiMAX OFDM, reducing the number of LO mixes is critical. The high number of sub-carriers within the OFDM signal actually makes this modulation quite sensitive to phase noise, as each of the N sub-carriers will be modulated by the phase noise of the LO. Figure 1 shows a block diagram of the proposed TX signal chain architecture. The I and Q analog baseband signals are generated by a dual 14-bit DAC. The direct RF up-conversion is done using an IQ modulator. Lowpass filters are required at the DAC output to remove

XI 1

the alias at the sampling frequency before the upconversion. The LO is generated by an external fractional-N synthesizer, which provides a continuous wave signal with minimal phase error. Finally, the composite RF output signal is amplified or attenuated through a variable gain amplifier (VGA) with a 50-dB of gain control range. An rms power detector ensures precise control of the output power. Transmitter Implementation BASEBAND SIGNAL GENERATION The performance of the DAC is critical when dealing with the wideband OFDM signal. The signal-to-noiseratio (SNR) and sampling rate define the spectral purity and signal quality of the modulated signal driving the IQ modulator.

sin(fT ) Vout ( f ) = Vsampled ( f ). fT


The off-chip anti-alias low-pass filter can then be designed with a relatively low order. Bessel filters are ideal for their flat in-band group delay, flat pass-band response, and limited in-band distortion. The order is chosen depending on the sampling frequency (Fs) and the required rejection at n*Fs.
Port I_or_Q A R R3 R=40.2 Ohm R R4 R=40.2 Ohm L L6 C L=680 nH C8 C=68 pF C C9 C=470 pF Port Iout_or_Qout R R5 R=240 Ohm

Port Ib_or_Qb Num=2

L L7 L=680 nH

Port Ib_out_or_Qb_out

0 -10 dB(S(3,4)) -30 -40 -50 -60 1E4 1E5 1E6 1E7 1E8
delay(3,4)

4E-8

-20

3E-8

The DAC resolution should provide sufficient dynamic range to meet the spectral mask at maximum output power and EVM at the lowest power levels. For instance, a SNR of 31.4 dB + margin is required for 64QAM OFDM, even at the minimum output power at the antenna. The target SNR for this design is 60 dB or better, and the chosen AD9862 14-bit DAC provides better than 70 dB SNR. The maximum modulation bandwidth addressed in these WiMAX applications also dictates the appropriate sampling frequency. In this design, a 10 MHz complex OFDM signal requires a sampling frequency of at least 20 MHz. But all sampling images would be at N*20 MHz (N>0), which would fall inband for an RF system with bandwidth higher than 20 MHz.
Without interpolation
0
0

2E-8

1E-8

0 1E4 1E5 1E6 1E7 1E8

freq, Hz 3dB cut-off frequency = 7.5MHz (Max OFDM signal BW here is +/5MHz)

freq, Hz

Group delay slope within +/-5MHz = 462ps/MHz

Figure 3. Baseband Bessel Low Pass Filter At a sampling frequency of 80 MHz, the measured levels of the sampling images were 33 dBc for the first image and 40 dBc for the second image. A third-order anti-alias low pass filter with a 3dB cut-off frequency of 8 MHz provides 50 dB of rejection at 80 MHz, bringing the sampling images down to 80 dBc.
UPCONVERTER

With 4x interpolation
-20

-20

-40 Magnitude [dBm]


Magnitude [dBm]

-40

-60

-60

-80

-80

-100

-100

-120 0 20 40 60 80 100 120 140 Frequency [MHz]

-120 0 20 40 60 80 100 120 140 Frequency [MHz]

Figure 2. DAC Images with and without Interpolation Choosing a DAC with an integrated interpolation filters helps relax the design of the off-chip reconstruction filter. For this architecture, while the TX digital data is updated at a rate of 20 MHz, the 4 interpolation filter effectively increases the overall sampling rate to 80 MHz. On the other hand, the relative level of the images at N*Fs also drops as a result of this increase in sampling rate. These amplitude levels are determined by the sin(x)/x roll-off from the sample-and-hold action of the DAC.

The AD8349 is a fixed gain silicon, monolithic, RF quadrature modulator that is designed for use from 700 MHz to 2700 MHz. The differential or single-ended LO input signal is buffered, and then split into an inphase (I) signal and a quadrature-phase (Q) signal using a polyphase phase splitter. These two LO signals are further buffered and then mixed with the corresponding I channel and Q channel baseband signals in two Gilbert cell mixers. The mixers outputs are then summed together in the output amplifier. The output amplifier is designed to drive 50 loads.The RF output can be switched on and off within 50 ns by applying a control pulse to the ENOP pin. The AD8349 can be used as a direct-to-RF modulator in digital communication systems such as GSM, CDMA, and WCDMA base stations, and QPSK or QAM broadband wireless access transmitters. Its high dynamic range and high modulation accuracy also

XI - 2 -

make it a perfect IF modulator in local multipoint distribution systems (LMDS) using complex modulation formats.

phase mismatches between I and Q signals, and an imprecise 90 LO phase shift within the IQ modulator, will result in an unwanted upper sideband image at LO+BB, when the wanted signal is at LOBB. When the TX DACs are configured for complex outputs, good image rejection at the modulator output is critical because this spur falls inside the wanted channel. Phase mismatches cannot easily be compensated for, but amplitude matching can be achieved through independent gain correction at the DAC level. In this design, the DAC integrates a gain calibration function that allows the output current on either I or Q channels to be changed by up to 20 dB with a fine resolution of 4%. A total image rejection of 50 dBc minimum is required to guarantee good EVM performance, and this gain correction circuit meets the requirement with margin.
LOCAL OSCILLATOR

Figure 4. AD8349 700 MHz to 2700 MHz Quadrature Modulator The Peak-to-Average Ratio of the 256-OFDM WiMAX modulation can reach 12 dB. For optimum spectrum quality out of the modulator, the appropriate peak voltage for the I and Q signals needs to be determined. The modulator used in this signal chain provides 0 dBm of rms output power for 1.2 Vpp of I and Q input drive level. Besides, the OP1dB of the modulator is 5 dBm. A 15 dB back-off provides optimum spectrum performance for the WiMAX OFDM signal, equivalent to an ac input level for the IQ modulator of about 750 mVpp differential.

Because the transmitter uses a zero-IF topology, the most appropriate synthesizer architecture for LO generation is a fractional-N PLL. Performance such as phase noise at 2.35 GHz, frequency resolution, and settling time drive the choice of the synthesizer architecture. In the up-conversion, phase noise is superimposed on each of the N sub-carriers of the WiMAX OFDM signal when mixed to the local oscillator.
OFDM subcarriers

LO

Fig 6. LO phase noise modulation of the OFDM subcarriers Compared to 802.11 Wi-Fi systems, the carrier spacing is also much narrower because of the higher number of sub-carriers within a given channel bandwidth. As an example, for a 20-MHz channel bandwidth, the carrier spacing in 802.11 is 385 kHz, compared to 78 kHz in 802.16d. Integrated phase error within the OFDM signal then becomes significantly higher, which directly contribute to the degradation of EVM. Although the OFDM symbol contains eight pilot tones that help a receiver track and remove most of the closein phase noise generated by the LO, the standard still requires stringent EVM to be met at the antenna. For a 64QAM modulated OFDM, the EVM specification at the transmitter output is 2.7% rms. The PLL loop bandwidth and total integrated phase error are thus critical to the design of this PLL. A total phase error

Figure 5. I/Q DC offset correction and sideband nulling. With modulation schemes such as WiMAX OFDM, it is important to correct for the modulator mismatches that directly impact EVM performance. Amplitude and

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lower than 1 degree rms has been used as a criteria for choosing and designing the LO synthesizer. A fractional-N synthesizer inherently has very good phase noise compared to an integer-N architecture. Very high frequency resolution can be achieved while using a higher comparison frequency, therefore helping reduce the total phase noise. For a frequency resolution of 125 kHz, an output frequency of 2350.125 MHz could be synthesized with a 10 MHz reference frequency:
125kHz N + K F = = 235 + 1. .10 MHz = 2350.125MHz FPFD PFD 10 MHz FRES

2.7 V to 3.3 V and can be powered down when not in use. In this particular system, the PLL has been designed with a closed loop bandwidth of about 20 kHz. For a 10-MHz WiMAX OFDM signal, the symbol duration is 25.6 s, which corresponds to a sub-carrier spacing of 39 kHz. The PLL loop has deliberately been designed slower than the symbol duration so that most of its phase noise can be tracked and removed by the pilot tracking algorithm within the demodulator. For non frequency-hopping TDD applications, PLL lock time is not that critical, as both transmitter and receiver operate at the same channel frequency. Therefore, designing a fast wideband PLL loop is not necessarily required. Figure 3 shows the simulated closed loop phase noise performance.

Fout

The typical phase noise error for these fractional-N synthesizers can be less or equal to 0.5 degree rms, which is appropriate for this application. The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a - based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phaselocked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).

Phase Noise at 2.35GHz


-80 P h ase N o ise ( d B c/H z) -90 -100 -110 -120 -130 -140 100 1k 10k 100k 1M Frequency (Hz)

Figure 8. Closed loop phase noise simulation at 2.35 GHz The PLL closed-loop in-band phase noise is 95 dBc/Hz and the rms phase error is only 0.35 degrees rms, equivalent to an EVM contribution of 0.6%.
POWER CONTROL AND RF POWER DETECTION

Because WiMAX systems can be used for non-line-ofsight applications, gain control of the transmitter is necessary to adjust the output TX level depending on the channel quality. The VGA should provide linear high gain control range, with limited signal distortion and noise. The ADL5330 is a high performance, voltagecontrolled, variable-gain amplifier/attenuator for use in applications with frequencies up to 3 GHz. The balanced structure of the signal path minimizes distortion while it also reduces the risk of spurious feed-forward at low gains and high frequencies caused by parasitic coupling. While operation between a

Figure 7. ADF4153 4 GHz Fractional-N Synthesizer. A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from

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balanced source and load is recommended, a singlesided input is internally converted to differential form.

Figure 9. ADL5330 1 MHz to 3 GHz 60 dB Linear-indB VGA. The input impedance is 50 from INHI to INLO. The outputs are usually coupled into a 50 grounded load via a 1:1 balun. A single-supply of 4.75 V to 5.25 V is required. The 50 input system converts the applied voltage to a pair of differential currents. The signal currents are then applied to a proprietary voltage-controlled attenuator providing precise definition of the overall gain under the control of the linear-in-dB interface. The GAIN pin accepts a voltage from 0 V at minimum gain to 1.4 V at full gain with a 20 mV/dB scaling factor. The output of the high accuracy wideband attenuator is applied to a differential transimpedance output stage. The output stage sets the 50 differential output impedances and drives Pin OPHI and Pin OPLO. The ADL5330 has a power-down function. It can be powered down by a Logic LO input on the ENBL pin. The current consumption in power-down mode is 250 A. In most cases, the VGA gain control is achieved through a closed loop system including a linear power detector. This helps relax the VGA linearity of the gain response. A single VGA in the transmit chain can achieve the required range of gain control. The part chosen for this purpose can maintain 50 dB of gain range, from 35 dB to +15 dB.

Figure 10. AD8362 50 Hz to 2.7 GHz 60 dB TruPwr Detector The AD8362 is a true rms-responding power detector that has a 60 dB measurement range. It is intended for use in a variety of high frequency communication systems and in instrumentation requiring an accurate response to signal power. It is easy to use, requiring only a single supply of 5 V and a few capacitors. It can operate from arbitrarily low frequencies to over 2.7 GHz and can accept inputs that have rms values from 1 mV to at least 1 Vrms, with large crest factors, exceeding the requirements for accurate measurement of CDMA signals. Used as a power measurement device, VOUT is strapped to VSET. The output is then proportional to the logarithm of the rms value of the input. In other words, the reading is presented directly in decibels and is conveniently scaled 1 V per decade, or 50 mV/dB; other slopes are easily arranged. In controller modes, the voltage applied to VSET determines the power level required at the input to null the deviation from the setpoint. The output buffer can provide high load currents. For accurate and fast power control, an rms power detector is the most appropriate function to extract the rms power level of a non-constant envelope modulation signal with a variable peak-to-average ratio. It usually measures the output signal level of the power amplifier through a low loss directional coupler. The detector used here is a high accuracy, wideband rms-to-dc square law detector It achieves 40 dB (driven singleended) to 60 dB (driven differentially) of detection range. Figure 11. shows the rms power measurement configuration technique which uses a directional coupler.

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Switch

PA
RMS power detector 2
-10dBm

EVM (%rms)

2.5

-31 -33 -35

1.5
-37

ADC
1
-39

CLPF

-45 -40 -35 -30 -25 -20 -15 -10 Total output power (dBm)

-5

Figure 11. Power detection Circuit Measured System Performance The OFDM signal has been generated using ADS system/circuit simulation software from Agilent. Only 802.16d OFDM signal generation and demodulation capabilities were available at the time of the evaluation. EVM performance has been measured using the Agilent 89600 VSA software. The equalization was done using the channel estimation sequence only (the preamble) and the EVM results shown are higher than what they would actually be with equalization training on both preamble and data sequence.

Figure 13. EVM function of gain control


2.5 3

QPSK, Rate 1/2 64QAM, Rate 2/3


2

16QAM, Rate 1/2 QPSK, Rate 3/4 64QAM, Rate 3/4


2

16QAM, Rate 3/4

1.5 VOUT (V)

1 ERROR (dB)

0.5

-1

-2

-0.5 -50 -40 -30 -20 -10 0 POUT (dBm)

-3

Figure 14. AD8362 RMS Detector Output Voltage and linearity error vs. System Output Power and Signal Type Table 1

Figure 12. Spectral quality at 2.35GHz The complete signal chain EVM performance as a function of the VGA gain or total output power level is given in Figure 13. Table 1 summarizes the measured performance of the complete signal chain for a 10 MHz, 64QAM, 256OFDM signal. The ADF4153 fractional-N PLL circuit used for this reference design has a total phase error due to phase noise of 0.35 degrees. This degrades the overall system EVM by 0.2%. Spectral quality is quite good for output power levels up to 0 dBm. As a reference, the WiBro mask is met with better than 15 dB margin at 3 dBm. The quality of these measured results demonstrates that this direct conversion architecture is viable to address the 2.5 GHz WiMAX systems requirements.

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Constellation error (dB)

VGA

-29

Chapter XII Use a Wideband, Integer-N, PLL Synthesizer as a Direct 6-GHz Local Oscillator
By Mike Curtin

INTRODUCTION Establishing a new benchmark for speed and RF phase-noise performance, the ADF4106 Phase-Locked-Loop Synthesizer is fully specified to operate at frequencies up to 6.0 GHz. This allows designs for the upper ISM band of 5.4 GHz-to-5.8 GHz to be greatly simplified. Fabricated on an advanced 0.35-m BiCMOS process, it

displaces the pin- and software-compatible 4-GHz ADF4113 as the fastest available integer-N synthesizerand can achieve 3-dB lower phase noise to boot! It requires only a 3.3-V supply, yet its VP pin is specified at up to 5.5 V, for compatibility with tuning voltage levels often required by modular VCOs used in base stations.

Figure 1. Functional block diagram of the ADF4106

XII - 1

The ADF4106 frequency synthesizer (Figure 1) can be used to implement local oscillators (LOs) in the up- and down-conversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase-frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A and B counters and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction with the dualmodulus prescaler (P/P+1), implement an Ndivider (N = BP+A).
In addition, the 14-bit reference (R) counter, allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage-controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in

many high-frequency systems, simplifying system architecture and lowering cost.

The standard PLL system architecture, used by the ADF4106and its predecessor, the ADF4113is shown in Figure 2. Since the maximum operating frequency of the ADF4113 is about 4 GHz, higher frequencies require the use of a frequency doublerwhich usually calls for an extra RF amplifier to produce an adequate level for the doubler. Use of the ADF4106 eliminates the frequency doubler and its associated circuitry, achieving a much simpler and more power-efficient LO. For example, the design shown in Figure 3 generates RF output frequencies, with 1MHz channel separation, from 5.4 GHz up to 6.0 GHz. The phase noise measured at the upper end was -83 dBc/Hz.

Figure 2. Standard PLL architecture

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Figure 3. The ADF4106 used to implement a 6.0-GHz local oscillator. Because the input impedance of the ADF4106 at this high operating frequency is very close to 50 ohms, a 50-ohm terminating resistor at the RF input is not needed for maximum power transfer efficiency. When operating at lower frequencies, the sparameters in the data sheet give the impedance values needed for matching. Low phase noise allows it to work as a lownoise, fast-settling 1.5-GHz local oscillator The ADF4106, in conjunction with a widebandwidth divider, can improve the phase noise and lock time of a standard local oscillator circuit at frequencies below 2.0 GHz.

Figure 4. Architecture for improved lock time, phase noise and reference spurs.

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A typical wireless system might be generating frequencies in 200-kHz increments from 1450 MHz to 1500 MHz. Using an integer-N architecture to do this, a phase/frequency-detector reference frequency of 200 kHz is needed, and the N value would vary from 7250 (1450 MHz) to 7500 (1500 MHz). Using the ADF4106 for best performance would give a phase noise figure of 88 dBc/Hz. Typical reference spurs in such a system would be 88 dBc at 200 kHz and 90 dBc at 400 kHz. Implementing a loop bandwidth of 20 kHz, typical lock time to 10 degrees of phase error would be 250 s.

Some consequences of using this architecture are outlined below. Phase-noise reduction The synthesizer phase noise has a 10 logFPFD relationship. This means that for every doubling of the PFD frequency, there will be 3-dB degradation in the synthesizer phase noise. However, the output from the VCO will be divided down, and its phase noise obeys a 20 logX rule. So, for every doubling of X, there will be a gain of 6 dB in phase-noise performance. If the PFD frequency is quadrupled, as above, FVCO is divided by four, to end up with the correct FOUT. Thus 6 dB will be lost due to the quadrupling of FPFD and 12 dB is gained due

However, the wideband operation possible with the ADF4106 allows an alternative architecture to be considered, shown in Figure 4. In this configuration, the core PLL is operated at a multiple of the final desired output frequency. In the example given above, the final desired frequency range is 1450 MHz to 1500 MHz. A multiple within the devices frequency range is to 5800 MHz to 6000 MHz (4 times the desired output band). In the proposed scheme, shown in Figure 4, FPFD operates at 800 kHz, the FVCO band is 5800 MHz to 6000 MHz, and the final system LO output is obtained by dividing FVCO by 4. FOUT = (FPFD N)/X (3)

to the division by four, resulting in an overall gain of 6 dB in phase-noise performance, using Figure 4, compared to the use of the standard architecture. In the above example, the resulting phase noise would be 94 dBc/Hz. Reference-spur reduction In an integer-N PLL, output reference spurs occur at the PFD frequency. In Figure 4, if you consider FVCO, the reference spurs will be at FPFD, 2FPFD, 3FPFD, etc. However, this gets divided down by X. In the specific example where X = 4, FOUT = FVCO/4 In this case, the spurs would remain at FPFD, 2FPFD, 3FPFD, etc., but would decrease by 12 dB due to the 20 logX relationship.

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However, the output channel spacing in Figure 4 is FPFD/X, or FPFD/4, in this example. So, using the architecture of Figure 4 with X = 4, and generating an output frequency of 1450 MHz to 1500 MHz with 200-kHz spacing, the reference spurs would not exist at 200 kHz, 400 kHz and 600 kHz. At 800 kHz, the spur level would be 90 dBc. Shorter lock time Since the PFD in Figure 4 is operating at a higher frequency, phase comparisons are

occurring at a higher rate; this will cause the loop to lock faster. In addition, because of the higher PFD frequency, a wider loop bandwidth is possible, and this too helps in improving the lock time. In this example, the lock time is about 70 s to within 10 of phase error for a PLL loop-bandwidth of 80 kHz. The actual implementation of Figure 4 is shown in Figure 5.

Figure 5. Using the ADF4106 with an output divider to generate a 1.5-GHz local oscillator.

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To summarize, the circuit of Figure 5 will provide the following performance: Phase Noise 94 dBc/Hz @ 1-kHz offset

limits of the device with signals below 15 dBm.


0 -5 - 10

V D D = +3 V V = +3V

Reference Spurs <100 dBc (system noise floor) @ 200-kHz, 400-kHz, 600-kHz offsets 90 dBc @ 800-kHz offset Lock Time 70 s to within 10 phase error The price of this improved performance is the extra cost of the output divider and the extra power consumption of the system as a whole (the HMC typically adds 68 mA to the ADF4106s 13-mA current requirement). So improved performance must be a critical requirement for going with this architecture. The extra board space needed for implementation is minimal, since the HMC comes in an 8-lead SOIC package. BANDWIDTH The 0.35-m BiCMOS fabrication process and careful application of RF design techniques permit the prescaler section of the ADF4106 to operate at up to 6.0 GHz with an input level of 10 dBm (referred to 50 ohms), guaranteed over the industrial temperature range (40 to +85C). Figure 6 below shows a typical sensitivity plot for the ADF4106 in a TSSOP package at 40C, +25C and +85C. It can clearly be seen that performance to 6 GHz is well within the

- 15 - 20
T
A

= +8 5 C

- 25 - 30 0 2

= +2 5 C T

= - 4 0 C

R F I n p u t F r e q u e n c y ( GH z )

Figure 6. ADF4106 sensitivity vs. frequency. PHASE NOISE Phase noise, a measure of the purity of the local oscillator signal, is the single most critical specification in the local oscillator section of radioswith a direct bearing on receiver sensitivity. It is the ratio, to output carrier power, of the noise power in a 1-Hz bandwidth at a given offset from the carrier. Expressed as a log ratio, the units of phase noise are dBc/Hz. Phase noise is typically measured with a spectrum analyzer.

Figure 7. Basic phase-locked-loop model. The circuit of Figure 7 establishes the circuit model for the following discussion of phase noise,

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Total phase noise in a phase-locked loop (dB) can be expressed as follows:

This provides a figure of merit for the PLL Synthesizer circuit itself, irrespective of the noise contributed by PLL N value and PFD frequency, since these would be the same for any similar circuit being compared. For the ADF4106, this figure comes out to 219

PN = PN + 20 N + 10 F log log PFD (1) TOTAL SYNTH


where PNTOTAL is the total phase noise of the PLL PNSYNTH is the phase noise due to the PLL synthesizer circuit itself 20 log N is the increase of phase noise due to the frequency magnification associated with the feedback ratio, 1/N. 10 logFPFD is the increase of noise associated with the incoming PFD frequency. The graph in Figure 8 shows the ADF4106s phase noise characteristics as a function of PFD frequency, FPFD.
- 12 0

dBc/Hza 3 dB improvement on the ADF4113, which had been the best available integer-N synthesizer in terms of phase noise. With this phase noise figure of merit, an engineer can work out the total PLL phase noise for any given PFD frequency and RF output frequency. For example, consider generation of a local oscillator signal with frequencies from 1700 MHz to 1800 MHz, and channel spacing of 200 kHz. Using equation (1), the close-in phase noise using the ADF4106 as the PLL synthesizer is
ADF4 10 6 ADF4 113

- 13 0

- 14 0

- 15 0

PNTOTAL = 219

+ 20log(9000 + 10log(200 x 103 ) )

- 16 0

- 17 0

- 18 0 10 10 0 10 0 0 Fr e que n c y ( k H z ) 10 0 0 0 10 0 0 0 0

= =

(219 + 79 + 53) dBc/Hz 87 dBc/Hz

Figure 8. ADF4106 Phase Noise vs. PFD Frequency. With a given measured total noise, synthesizer noise can be inferred as:

Figure 8 shows that the ADF4106 obeys the 10 logFPFD rule (PFD phase noise substantially linear with log frequency) fairly consistently all the way to 30 MHz. Some integer-N devices begin to degrade rapidly once the PFD frequency goes above 1 MHz.

PN log log PFD(2) SYNTH = PN TOTAL 20 N 10 F

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References [1]. Mini-Circuits Corporation, VCO Designers Handbook 1996. [2]. L.W.Couch, Digital and Analog Communications Systems Macmillan Publishing Company,New York,1990. [3]. P.Vizmuller,RF Design Guide Artech House,1995. [4]. R.L.Best,Phase Locked Loops: Design, Simulation and Applications 3 rd Edition,McGraw Hill,1997. [5]. Bannerjee, Dean PLL Performance, Simulation and Design National Semiconductor Website [6]. Analog Devices Inc. Data Sheet for ADF4106 [7]. Hittite Microwave Corporation. Data Sheet for HMC362S8G [8] Curtin, Mike Phase-Locked Loops, 3-part series in Analog Dialogue 33-3, 33-5, and 33-7 (1999). Also in hard copy: Analog Dialogue Volume 33, 1999. [9] Goldberg, Bar-Giora, Digital Frequency Synthesis Demystified (LLH, 1999)

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Chapter XIII Short Range Wireless Devices - Building a global license-free system at frequencies below 1GHz
By Austin Harney and Conor OMahony

Introduction:
The term Short Range Device (SRD) is intended to cover radio transmitters which provide either unidirectional or bi-directional communication and which have a low capability of causing interference to other radio equipment. Due to the many different services provided by these devices, there is no exhaustive list covering the SRD application space, however, the following categories are amongst those covered: Tele-control for Home/Building Automation systems Wireless sensor applications Alarms Automotive, including Remote Keyless Entry & Remote car start applications Wireless Speech and Video. When designing a SRD wireless system, careful consideration needs to be paid to the choice of frequency on which your radio will be communicating over. In most cases, the designer is limited to those portions of the spectrum which allow license-free operation once certain specifications and conditions on usage are met. Table 1 lists the frequency bands available globally. For designers who are hoping to build systems which can operate world-wide, the obvious choice has been 2.4GHz, which has become the frequency of choice for such standards as Bluetooth, WLAN and Zigbee.

5.8GHz has also attracted some attention, for example in cordless phones or the 802.11a version of WLAN. However for systems which require both range and low power, the sub-1GHz bands remain compelling due to reduced co-existence issues and greater transmission range, both of which impact on power consumption an important consideration in battery powered applications. The improved propagation range for lower frequency radiators can be seen from a simplified version of Friis Transmission Equation which states that:

Pr =

Pt 2 Pt c 2 = (4d )2 (4d )2 f 2

Where Pr is the available power at the receive antenna and Pt is the power delivered to the transmit antenna. In this case we are assuming a unity gain for both antennas. The equation shows that for a fixed distance d and transmit power Pt, the received power will increase with the square of the wavelength or alternatively will decrease with the square of the frequency, f. If the received power goes below the minimum power needed to demodulate the signal correctly (called the sensitivity point), the link will break down.

Global Frequency Allocations 13.56MHz 40MHz 433MHz 2.4GHz 5.8GHz Other common allocations 868MHz/915MHz Table1

Comments Used for near-field communications Not often used Need to reduce power for U.S. Popular global band Some systems up-banding from 2.4GHz Europe/US only

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Worldwide Frequency allocations below 1GHz


A more detailed description of the various sub1GHz standards are given in Table2. This is not an exhaustive list but more detail can be found by following the links provided in the table. The 433MHz is one option for global usage, with a slight frequency modification required for Japan which is easily handled by most modern Region Europe Relevant Standards ERC REC 70-03 EN 300 220 (Sept. 00) EN 300 220 (Feb.06) FCC Title 47 Part. 15.231 Part 15.247 RSS-210 ARIB STD-T67 RADIO REGULATIONS OF THE PEOPLE'S REPUBLIC OF CHINA Frequency Bands (MHz) 433.05 434.79 868.0 870 863.0 870 260 470 902 928

frequency flexible transceivers, like the ADF7020 or ADF7021. A block diagram is shown in Figure1. However less than 2MHz of bandwidth is available and in addition applications like voice, video, audio or continuous data transmission are typically not allowed in this band, somewhat restricting its use. Thus it is most commonly used for keyless entry systems and basic tele-control.

Relevant links http://www.ero.dk/ http://www.etsi.org

U.S.

http://www.access.gpo.gov/nara/cfr/waisidx_04/47 cfr15_04.html

Canada Japan China

260 470 902 928 426.0375 426.1125 429.175 429.7375 315.0 - 316.0 430.0 - 432.0

http://strategis.ic.gc.ca/epic/internet/insm t-gst.nsf/en/sf01320e.html http://www.arib.or.jp/english/ http://ce.cei.gov.cn/elaw/law/lb93i1e.txt

Table2 A more useful band is either around 868MHz in Europe or 902MHz to 928MHz in the U.S. This does not provide restrictions on applications as well as allowing a more compact antenna implementation. Prior to the latest EN 300-220 specification however, the U.S. and European bodies took vastly different approaches to regulate usage. The U.S. adopted a frequency hopping approach while in Europe duty-cycle limits were applied in each of the sub-bands as described in the ERC REC-70 document. While both of these implementations are useful in minimizing interference, it meant that a manufacturer who was designing a system for both regions, needed to completely re-write the Media Access Layer (MAC) in his communication protocol. However the latest European EN 300-200 regulations which were due for release at the time of writing in February 2006 has extended the frequency bands to allow for frequency hopping spread spectrum (FHSS) or Direct Sequence Spread Spectrum (DSSS) making the MAC implementations similar to those designed for the U.S, although some fine-tuning will still be required. We will discuss some of the aspects of the new specification and areas the SRD system designer needs to be aware of in the below sections.

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Figure1. A block diagram of the ADF7020 SRD transceiver during any single hop) of 400 ms and a similar number of hopping channels. Table 3 shows the extended frequency band in Europe below 870MHz when either FHSS or DSSS is used. This compares to the 2MHz available previously. In fact, up to 7MHz is now available once either the Listen Before Talk (LBT) or duty-cycle limits are met. Listen Before Talk is a polite communication protocol which scans the channel for activity before initiating a transmission. It is also often called a Clear Channel Assessment (CCA) operation. The key point here is that for systems using Listen Before Talk with frequency hopping there are no duty cycle limitations. Power/Magnetic Field 25 mW e.r.p. Other requirements LBT or <1% Tx Duty cycle

Frequency Hopping Systems


Frequency Hopping Spread Spectrum (FHSS) is a transmission technology which spreads energy in the time domain by dividing up the spectrum into several channels and switching between these, using a pseudorandom sequence. This pseudo-random sequence or hopping code must be known by both the receiver and transmitter. To facilitate new nodes joining the network the controller node typically sends out a beacon signal at regular intervals which the new node can synchronize onto. This synchronization time depends on both the beacon interval and number of hopping channels. Both the U.S. and European standards specify a maximum dwell time (the time spent at a particular frequency Sub-band 865MHz to 870MHz Number of Hop Channels 60

863MHz to 870MHz

47

25 mW e.r.p.

LBT or <0.1% Tx Duty cycle

Table 3

Wide Band Modulation: DSSS


In Direct Sequence Spread Sprectrum (DSSS) systems, a narrow band signal is multiplied by a

high speed pseudo random (PR) sequence to generate a spread signal. The bit rate (known as chip rate) determines the bandwidth over which the signal is spread. The bandwidth of this spread signal is much wider than the original

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data bandwidth with a corresponding reduction in peak spectral density (see Figure 2). On the receive side, the incoming spread spectrum signal is multiplied with the same PR code which de-spreads the signal. This allows the original narrow band signal to be extracted. At the same time, any narrow band interferers at the receiver are spread and appear as wideband noise to the demodulator. The allocation of different PR codes to each user in the system allows isolation between users in the same frequency band. This is known as Code Division Multiple Access (CDMA). DSSS modulation is used in the IEEE802.15.4, IEEE802.11 and GPS systems to name but a few. The main advantages of DSSS are: 1) Interference resilience: The essence behind the interference rejection capabilities of DSSS is that the useful signal gets multiplied twice (spread and de-spread) by the PN code while any interferes are just multiplied once (spread). 2) Low power density and therefore minimal interference with existing narrowband systems. 3) Security: Very resilient to jamming due to spreading/de-spreading. Also each unit is allocated an individual PN code. Sub-band

4) Mitigation of multi-path effects. 5) No network synchronization needed as in the FHSS case. This minimizes power consumption.

Figure 2: Power Spectral Density for FHSS and DSSS

Wideband Modulation other than DSSS or FHSS.


An interesting aspect of provisions for spread spectrum in the regulations is that wideband modulation schemes other than FHSS and DSSS are also provided for. FSK/GFSK modulation with an occupied bandwidth greater than 200kHz is considered wideband modulation under the European regulations. Table 4 highlights the main specifications which apply to wideband modulation schemes (including DSSS) in Europe:

Occupied Max radiated power Requirements Bandwidth density e.r.p. 865 MHz to 868 MHz 0.6 MHz 6.2 dBm/100 kHz 1 % TX duty cycle or LBT 865 MHz to 870 MHz 3.0 MHz -0.8 dBm/100 kHz 0.1 % TX duty cycle or LBT 863 MHz to 870 MHz 7.0 MHz -4.5 dBm/100 kHz 0.1 % TX duty cycle or LBT Table 4: Maximum radiated Power density, bandwidth and duty Cycle Limits for spread spectrum modulation (other than FHSS) and wideband modulation.
An example of a device that can take advantage of this wideband standard using FSK modulation is the ADF7025. To operate in the sub-band 865870MHz the maximum occupied bandwidth (99%) and maximum power density limits must be complied with. An edge of channel (or band) maximum power limit of -36dBm is also specified. With the ADF7025 setup as shown in Table 5, all three of these limits were met. Figure 3 shows the occupied bandwidth as 1.7569MHz and the spectral density as -1.41dBm/100kHz . The edge of band (=/- 1.5MHz) requirement of -36dBm can be seen to be easily met in the first plot. Frequency Modulation Frequency Deviation Data Rate 867.5MHz FSK +/- 250kHz 384kbps

Table 5: ADF7025 parameters for Wideband Modulation Experiment

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Figure 3: Results for Wideband Modulation Experiment on ADF7025: Occupied Bandwidth, Power Spectral Density/100kHz & Band Edge Power Limit. no greater than 8dBm in any 3kHz b/w of the The advantage of using the ADF7025 under modulation (maximum will be at the one/zero wideband modulation is the extra data rate possible peaks in the FSK/GFSK modulated signal).
(in this case 384kbps) without the need for complex DSSS transceivers. These higher data rates allow the transmission of audio and medium quality video (a few frames/s). In the US, FCC Part 15.247 has a very similar allocation which gives provisions for frequency hopping systems operating in the 902-928 MHz, 2400-2483.5 MHz and 5725-5850MHz, while also giving provisions for digitally modulated signals. This is a loose term and covers both spread spectrum (DSSS) and other simpler forms of modulation (FSK, GFSK), thus similar to the Wideband Modulation specification in the ETSI regulations. The two main requirements are listed below:

So similar wideband modulated systems can now be employed in both the US and Europe, thus simplifying engineering of products intended for worldwide markets. The ADF7025 transceiver architecture lends itself to operation in both the digital modulation mode as defined in the US standards and the Wideband Modulation mode as defined in the new European regulations.

Transient Power Requirements


A new specification which engineers should be aware of is the restrictions put on transient power. Transient power is defined as the power falling into adjacent spectrum due to the switching of the transmitter on and off during normal operation. A transient power limit has been added to the latest regulations to prevent spectral splatter when a transmitter is turning on and off. The increase (turning on) or decrease (turning off) in current to the PA causes the load seen by the Voltage Controlled Oscillator (VCO) to change causing the PLL to unlock for an instant, producing spurious emissions or spectral splatter, as the loop acts to re-acquire. In systems where a unit is transmitting at intervals the splatter can significantly increase the power falling into neighbouring channels. Figure 4 highlights the problem of spectral splatter. The yellow trace shows the PA output from the ADF7020 with the PA being turned on and off once every second while the spectrum analyzer is kept on max hold. The blue trace shows an un-modulated continuous wave signal from the ADF7020 transmitter. It can be seen that significant power is falling into channels either side of the carrier. Specification 8.5 of

1. 2.

The minimum 6 dB bandwidth shall be at least 500kHz. For digitally modulated systems, the power spectral density conducted from the intentional radiator to the antenna shall not be greater than 8 dBm in any 3 kHz band during any time interval of continuous transmission.

If one does not wish to employ a FHSS system then normally they would have to abide by section 15.249 which limits the field strength (@3m) to 50mV/m (-1.5dBm ERP). What makes this digital modulation so attractive is that the maximum output power is 1 Watt (while still complying with < 8dBm in any 3kHz bandwidth). Also, with the wider signal bandwidths, higher data rates are possible. Thus to operate a simple FSK/GFSK transceiver under these regulations a wide enough FSK/GFSK frequency deviation is chosen to ensure the 6dB bandwidth is greater than 500kHz. The output power can then be 1 Watt, ensuring that there is

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ETSI EN 300 220-1 puts a limit on the amount of power falling into these adjacent channels.

on and off. This is normally accomplished by manually turning on/off the PA in stages. With the ADF7020 transceiver, it is possible to step the PA from off to +14dBm in a maximum of 63 steps. An even simpler approach is to use a transceiver with an automatic PA ramp. The ADF7021 has a programmable ramp where both the number of steps and duration of each step can be set by the user.

Communication Protocol Considerations


The new European regulations impose very specific requirements for over-the-air protocols in the 863-870 MHz bands. Whether a system uses a single channel protocol, FHSS or DSSS there are very specific rules which must be abided by. This of course complicates the protocol design. However, the upside to these new ETSI regulations is that they mirror the FCC Part 15.247 regulations in a lot of aspects, thus simplifying the design of a protocol intended for worldwide use. ADI are currently in the process of updating their ADIismLINK (Version 2.0) protocol which can be used with any of the ADF702X transceivers. This protocol is intended for use in the worldwide sub-1GHz bands, and incorporates the new European regulations. It is based on a star based network as highlighted in Figure 4.

Figure 4 The measurement procedure requires that the transmitter be turned on and off five times at maximum output power and the power falling into the channels located 2, 4 and 10 channels either side of the carrier are measured. The limits are shown in Table 6. Channel 2 4, 10 Table 6 To simplest way to ensure compliance with this specification is to ramp the PA when turning it Limit 40dBc with out the need to be below -27dBm 50dBc with out the need to be below -36dBm

Figure 1: Star Network Topology At the heart of the protocol is a non-slotted, nonpersistent Carrier Sense Multiple Access scheme with Collision Avoidance (CSMA-CA). The

End-point (EP) listens to the channel (LBT) before transmitting, thereby avoiding collisions. The non-slotted aspect of the protocol means that EPs can transmit as soon as they have data, subject to first performing a Listen Before Talk

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operation. This also ensures no synchronization is required. If an EP senses the channel is busy, it backs off for a random period before performing another LBT. The number of times this back-off can occur is limited, hence the non-persistent nature of the protocol. In FHSS mode the protocol uses this CSMA-CA system on each hopping channel, thus fulfilling the LBT requirement for the new European regulations.

The Physical Layer (PHY) parameters and Media Access Layer (MAC) parameters of the ADIismLINK protocol are highly configurable thus allowing thorough device and system evaluation. Source code is also provided simplifying the system development procedure. The protocol comes as part of the ADF702x Development Kit (ADF70xxMB2). A system overview of ADIismLINK is shown in Figure 5. More information on this is available through the ADI website (ADF702X Development Kit).

Figure5. ADIismLINK system Overview

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