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KILPATRICK TOWNSEND & STOCKTON LLP THEODORE G. BROWN, III (SBN 114672) 1080 Marsh Road Menlo Park, California 94025 Telephone: (650) 326-2400 Facsimile: (650) 326-2422 Email: tbrown@kilpatricktownsend.com O’MELVENY & MYERS LLP KENNETH L. NISSLY (SBN 77589) SUSAN van KEULEN (SBN 136060) SUSAN ROEDER (SBN 160897) 2765 Sand Hill Road Menlo Park, California 94025 Telephone: (650) 473-2600 Facsimile: (650) 473-2601 Email: knissly@omm.com svankeulen@omm.com sroeder@omm.com Attorneys for Plaintiffs, HYNIX SEMICONDUCTOR INC., HYNIX SEMICONDUCTOR AMERICA INC., HYNIX SEMICONDUCTOR U.K. LTD., and HYNIX SEMICONDUCTOR DEUTSCHLAND GmbH UNITED STATES DISTRICT COURT FOR THE NORTHERN DISTRICT OF CALIFORNIA SAN JOSE DIVISION HYNIX SEMICONDUCTOR INC., HYNIX SEMICONDUCTOR AMERICA INC., HYNIX SEMICONDUCTOR U.K. LTD., and HYNIX SEMICONDUCTOR DEUTSCHLAND GmbH, Plaintiffs, v. RAMBUS INC., Defendant. Case No. CV 00-20905 RMW DECLARATION OF DAVID L. TAYLOR IN SUPPORT OF (1) MOTION FOR SUMMARY JUDGMENT ON THE ISSUE OF THE COLLATERAL ESTOPPEL EFFECT OF REEXAMINATIONS OF RAMBUS’S PATENTS; (2) MOTION FOR LEAVE TO FILE SUPPLEMENTAL REPLY TO DEFENDANT AND COUNTERCLAIM OF PLAINTIFF RAMBUS INC.’S AMENDED COUNTERCLAIM; AND (3) MOTION FOR NEW TRIAL AND MOTION FOR STAY Date: November 30, 2012 Time: 9:00 a.m. Ctrm: 6 (Hon. Ronald M. Whyte) ///
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I, David L. Taylor, declare: 1. I am the same David L. Taylor that has been deposed in conjunction with this

litigation on the following dates: March 8, 2004; April 27-28, 2005, and January 4, 2006. I also testified at Markman hearing on March 23, 2004. I testified in the trial proceedings (“the 2006 patent trial”) in this case on March 29-30, 2006; April 3, 2006; and April 12, 2006. A complete listing of my deposition and testifying history is also shown in my resume attached as Exhibit A. 2. I have previously prepared and submitted a number of expert reports and

declarations concerning the validity and/or infringement of the patents involved in this litigation and in connection with Case No. C-05-00334 RMW, which involves patents from the same “Farmwald/Horowitz” family of patents at issue in this case, all of which name Michael Farmwald and Mark Horowitz as inventors and are based on an application, Serial No. 510,898, first filed in April 1990. All of the patents in the Farmwald/Horowitz family of patents share substantively the same specification and drawings, with only minor, formal differences. 3. I have been asked to review a number of decisions rendered during 2012 by the

Board of Patent Appeals and Interferences (“the BPAI”)1 in connection with a number of inter partes reexaminations of various patents in the Farmwald/Horowitz family asserted in this and/or related litigation, to compare the claims at issue in those BPAI decisions with the claims that were asserted in the 2006 patent trial in this litigation, and to assess the validity of the claims tried in the 2006 patent trial in view of these decisions from the BPAI. I have reviewed and am familiar with the relevant patents in the Farmwald/Horowitz patent family, their claims, the BPAI decisions, and the prior art referenced in those decisions. If called to testify as a witness, I would testify as to the statements and opinions set forth in this Declaration. 4. As shown in my resume attached as Exhibit A, I received a BSEE degree from The

Citadel in 1970 and a MSEE from Stanford University in 1972. In my master’s program I focused on integrated circuit design and solid-state physics. This focus enabled me to understand I understand that, effective September 16, 2012, the BPAI was renamed the Patent Trial and Appeal Board (“PTAB”), under recent amendments to the patent laws that, among many other changes, eliminated interferences. Since the decisions of most relevance here issued under the former name, I will continue to refer to this appeal board as the BPAI or “the Board.” -1-

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semiconductor design methods and technologies which I used in my future design activities. 5. I have accumulated significant knowledge and experience in the design and

manufacture of semiconductor devices; this is summarized in my resume, Exhibit A. My work experience has primarily been in the area of semiconductor memory products including DRAM, SRAM, EPROM, EEPROM, and ROM. I have been directly responsible for the design of approximately 75 commercially successful products including, for example, 1M, 4M, and 8M synchronous DRAMs (at Silicon Access), a 1M synchronous SRAM (at Hyundai Electronics America), and a 4M synchronous DRAM-based ATM switch and 4M DRAM-based FIFO, both at Integrated Device Technologies. I also hold 21 patents in the semiconductor field, most of which deal with semiconductor memory circuits and products; a list of these patents is included in Exhibit A. 6. For convenience and because the exhibits referenced in this declaration are not

numbered sequentially, a list of the exhibits to this declaration is included in Exhibit B. 7. These were: US 5,915,105 – claim 34; US 6,034,918 – claims 24 and 33; US 6,324,120 – claim 33; US 6,378,020 – claims 32 and 36; US 6,426,916 – claims 9, 28, and 40; and US 6,452,863 – claim 16. For convenience, the patents will be referenced by the last three digits in the patent number. A copy of the text of all ten claims is attached in Exhibit 1. 8. I understand that, as a result of the trial and other proceedings in the litigation, all Ten claims of the Farmwald/Horowitz patents were tried in the 2006 patent trial.

ten claims were found infringed and none of the claims were found invalid, and that judgment was entered against Hynix Semiconductor Inc. and the related subsidiaries that are parties to the case (collectively, “Hynix”). 2 9. These claims recite, using various wording, memory devices and methods of

2

I understand that, in March 2012, Hynix Semiconductor Inc. was renamed SK hynix Inc., and that the names of its subsidiaries have also changed accordingly. However, for ease of reference, I will continue to refer to “Hynix”. -2-

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operating or controlling memory devices that incorporate one or more of five “technologies” or features: programmable CAS latency (also referenced as “access time register” or programmable “read latency”), programmable burst length (or variable “block size”), autoprecharge (“precharge information”), dual-edge clocking (inputting and outputting data on both the rising and falling edges of a clock signal), and on-chip DLL.3 The claims and the technologies to which features of the claims are directed are summarized in the following table: Patent/Claim Dual-edge Clocking X X X X X X X X X X X X X X X X X X X Access Time Register Block Size DLL Autoprecharge

’105/34 ’918/24 ’918/33 ’120/33 ’020/32 ’020/36 ’916/9 ’916/28 ’916/40 ’863/16 10.

X

Beginning in 2007, a number of reexaminations were requested for many of the

claims of the Farmwald/Horowitz patents. Requests were filed on behalf of Hynix, Samsung Electronics Co., Ltd. (“Samsung”), Micron Technology Inc. (“Micron”), and by Nvidia Corporation (“Nvidia”). Some of these requests were for ex parte reexaminations while others requested inter partes reexaminations.4 Most of these requests were granted, and most of the
3

This is only a summary, in general terms; for evaluating both validity and infringement, I understand that the precise claim language governs and must be consulted. The descriptions of the five “technologies” are also only general shorthand descriptions of the features in the claims and the features the SDRAM and DDR SDRAM memories that were found to infringe Rambus’s claims. It is my understanding that, except in unusual circumstances, a third party that requests ex parte reexamination is not entitled to participate substantively in the proceedings after the reexamination request is filed. The patent owner, on the other hand, can respond to actions by -3-

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proceedings requesting reexamination of claims in the same patent were merged. It is not necessary for the purposes of this declaration to describe all of the reexamination proceedings in detail. 11. The BPAI has issued a number of decisions, beginning in January 2012, regarding

appeals by Rambus and/or Micron in connection with inter partes reexaminations requested by Micron and Samsung.5 The decisions that are particularly relevant to the issues discussed in this declaration are those regarding certain claims of the ’120 and ’916 patents (which are involved in this litigation) and claims of three additional Farmwald/Horowitz patents, US 6,182,184 (“the ’184 patent”), US 6,584,037 (“the ’037 patent”), and US 6,546,446 (“the ’446 patent”). 6 12. These BPAI decisions are based on a relatively small number of prior art

references, several of which were admitted in the 2006 patent trial. These references, with the shorthand name used in the BPAI decisions and the number of the exhibit to this declaration, are: “iAPX”, the Intel iAPX432 Interconnect Architecture Reference Manual, published in 1982, which was Exhibit No. 1109 in the 2006 patent trial (Exhibit 30); “Bennett,” US 4,734,909, March 29, 1988 (Exhibit 31), which was the subject of a summary judgment motion and decision of December 15, 2008 in Case No. C-05-00334 RMW; the examiner, provide additional evidence, meet with the examiner, and appeal any adverse decisions by the examiner to the BPAI and to the Court of Appeals for the Federal Circuit. I understand that, in contrast, in inter partes reexamination proceedings, the party that made the request can respond to all arguments submitted by the patent owner and can appeal decisions by the examiner that are favorable to patentability to the BPAI and the Federal Circuit as well as respond to any appeals filed by the patent owner. I understand that, in each case, Samsung and Micron filed separate inter partes reexamination requests regarding various claims of the same patent, and the proceedings on these requests were merged by the Patent Office into a single proceeding for each patent. I understand that the BPAI has held hearings in additional appeals regarding inter partes reexaminations of additional patents in the Farmwald/Horowitz family, but has not yet issued its decisions. I may supplement this declaration resulting decisions by the BPAI that are relevant to the subject matter of this declaration. These additional, pending appeals are in the following merged reexamination proceedings: serial numbers 95/000,250 and 95/001,124 regarding the ’863 patent, in which the BPAI oral hearing was held July 11, 2012; serial numbers 95/001,026 and 95/001,128 regarding the ’020 patent, in which the BPAI oral hearing was held September 12, 2012; and serial numbers 95/001,133 and 95/001,105 regarding US 6,751,696, in which the BPAI oral hearing was also held September 12, 2012. In addition, I understand that there are additional appeals to the BPAI that are pending in which no oral hearing has as yet been held. -4-

5

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“Inagaki,” Japanese patent publication JP 57-210495, published December 24, 1982 (Exhibit 32, which includes the English translation submitted in the reexaminations); “Lofgren,” Great Britain patent publication GB 2 197 553 A, published May 18, 1988, which was Exhibit 2012 in the 2006 patent trial (Exhibit 33); “Bowater,” US 5,301,278, issued April 5, 1994, on an application originally filed April 29, 1988 (Exhibit 34); “Olson,” US 4,933,910, issued June 12, 1990, on an application filed July 6, 1988 (Exhibit 35); “Wicklund,” US 5,159,676, issued October 27, 1992, on an application originally filed December 5, 1988 (Exhibit 36); “iRAM,” Intel Memory Components Handbook Ch. 1, 3 (1985), which was Exhibit 2385 in the 2006 patent trial (Exhibit 37); and “Bazes,” US 4,496,861, issued January 29, 1985, on an application filed December 6, 1982 (Exhibit 38). 13. The BPAI issued its decision regarding the ’120 patent on January 19, 2012; a copy

of the decision is attached as Exhibit 10. The BPAI affirmed the examiner’s rejections of claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 and reversed the examiner’s decision confirming claims 26, 29, and 33. (Exhibit 10, page 3) The BPAI agreed that claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 were all anticipated by iAPX. (Exhibit 10 page 11) The BPAI also agreed that the examiner erred in failing to reject: claims 26 and 29 as anticipated by Bennett (Exhibit 10, page 17), claim 33 as obvious over Bennett in combination with Wicklund, Bowater, or Olson (Exhibit 10, page 18); claims 26 and 29 as obvious over iAPX in combination with iRAM (Exhibit 10, page 20); and claim 29 as obvious over iAPX in combination with iRAM and Olson (Exhibit 10, page 22). The BPAI denied Micron’s request for rehearing of its appeal on July 25, 2012. (Exhibit 11) Rambus’s request for rehearing was denied July 30, 2012 (Exhibit 12), but the BPAI designated this decision as a “new decision,” which I understand meant that Rambus could request another rehearing. Rambus’s second request for rehearing was filed August 30, 2012. (Exhibit 13) 14. The BPAI issued its decision regarding the ’916 patent on June 14, 2012; a copy of

the decision is attached as Exhibit 14. Although the decision states that the BPAI reversed the
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examiner’s decision rejecting claims 26 and 28 (Exhibit 14, pages 2 and 26), from the Board’s analysis and statement on page 22, the BPAI concluded that the examiner erred in failing to reject these claims as anticipated by Bennett. Rambus requested rehearing of this decision on July 16, 2012 (Exhibit 15), in which it stated that: Specifically, although the Board repeatedly states that it reverses the Examiner’s decision rejecting claims 26 and 28 (Decision at 2, 26), it actually reversed the Examiner’s confirmation of claims 26 and 28 and rejected claims 26 and 28 based on Bennett. (Exhibit 15, page 1) I understand that the BPAI has not yet acted on Rambus’s request for rehearing. 15. The BPAI issued its decision regarding the ’184 patent on January 19, 2012; a copy

of the decision is attached as Exhibit 16. The BPAI affirmed the examiner’s rejection of claims 123. The BPAI agreed that claims 1-10, 13, 15, 16, 18, 19, and 21 were anticipated by iAPX (Exhibit 16, page 26); claims 11, 12, 14, 17, 20, and 23 were obvious based on a combination of iAPX and Inagaki (Exhibit 16, page 30); and claim 22 was obvious in view of the combination of iAPX and Lofgren (Exhibit 16, page 31. The BPAI denied Micron’s request for rehearing on July 25, 2012. (Exhibit 17) I understand that Rambus did not request a rehearing in this case. 16. The BPAI issued its decision regarding the ’037 patent on January 27, 2012; a copy

of the decision is attached as Exhibit 18. The BPAI reversed the examiner’s decision confirming claim 34 and found that this claim was obvious over Bennett in combination with Wicklund or Bowater. (Exhibit 18, page 12) The BPAI denied Micron’s request for rehearing on July 26, 2012 (Exhibit 19) and denied Rambus’s request for rehearing on August 16, 2012. (Exhibit 20) 17. The (newly-renamed) PTAB issued its decision regarding the ’446 patent on

September 27, 2012; a copy of this decision is attached as Exhibit 21. The Board reversed the examiner’s decision to confirm claims 1-4, and determined that these claims were each obvious over combinations of Bennett with Wicklund or Bowater, Inagaki or Novak (US 4,663,735), and Lofgren or Bazes. (Exhibit 21, pages 16, 25, and 29) ///
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18.

In summary, two of the ten claims tried in this litigation – ’120 claim 33 and ’916

claim 28 - have been invalidated by the BPAI. 19. I understand that other claims in litigation but not adjudicated by the BPAI may be

invalidated based on the results of the BPAI decisions, where the differences between the claims that the BPAI has invalidated and claims that the BPAI has not decided raise no new or different issues of patentability than the claims that the BPAI has invalidated. I understand that the methodology for determining these issues is that: … the inquiry should be whether the nonlitigated claims present new issues as to the art pertinent to the nonlitigated claims; as to the scope and content of that art; as to the differences between the prior art and the nonlitigated claims; and as to the level of ordinary skill in that art. If none of these inquiries raises any new triable issues, then the obviousness determination in the prior proceeding should be equally applicable to the nonlitigated claims. I understand that an analogous inquiry is applicable to determining anticipation – whether, under the decisions of the BPAI, all elements of a nonlitigated claim are present in a single prior art reference. 20. In addition to reviewing the BPAI decisions themselves, I have studied the claims

invalidated by the BPAI in the decisions mentioned above and have prepared charts comparing the eight claims in this suit (that were not invalidated in the BPAI decisions) to claims that were invalidated by the BPAI with the same or similar features. These charts are attached as Exhibits 2 - 9. 21. I then identified the potentially significant differences between the eight claims in

this case and the claims invalidated by the BPAI as anticipated by or obvious in view of the prior art. Finally, I considered whether those differences in the claims represented differences that would be significant to one of ordinary skill in the art between each of the eight claims and the prior art used by the BPAI to invalidate those claims. 22. In some cases, the differences in the claims relate to terms that have been construed

by this Court; in these cases, I have used the Court’s constructions as applicable. 23. As I indicated in my prior expert reports in this case, in my opinion, in the 1989-

1990 time frame (at or shortly before the time the initial application for the patents in the Farmwald/Horowitz patents was filed), one of ordinary skill in the art to which the Rambus
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patents pertain would have had a B.S. or M.S. in Electrical Engineering or Physics and 3-7 years of experience in the design of integrated circuit products, including substantial experience in the design of DRAMs and DRAM circuits. However, my opinions and conclusions would not change if I were to consider one of ordinary skill to have, as indicated in the prior reports of Robert Murphy, Rambus’s expert in this case, a Bachelor of Science degree in Electrical Engineering and 3-5 years’ experience designing memory circuits such as DRAMs. 24. In preparing these charts, I noted that there were features or limitations in the

claims invalidated by the BPAI that were not present in the most similar of the eight claims in the case that were not the subject of these BPAI decisions. Since all of the claims are written in the open-ended “comprising” format, I ignored these additional limitations in the BPAI-invalidated claims. To pick a simple example, if the BPAI decided a claim with elements A, B and C was anticipated by a particular prior art reference, the same prior art reference would anticipate a claim that only required elements A and B or A and C. In the attached charts, these additional elements in the claims invalidated by the BPAI but not in the most similar of the eight claims are in italics. 25. In some of the attached charts, I compare one of the eight claims to two or more of

the claims invalidated by the BPAI. Again, a simple example illustrates why this type of comparison is possible. Assume the BPAI held two claims anticipated by a prior art reference, one with elements A, B, and C and the other with elements A, D, and F. Logically, these decisions mean that the same reference anticipates a claim with elements A, B, C and F as well as a claim that recites all five elements. 26. Some of the elements in the various claims in the attached charts appear in different

orders. In order to make some of the comparisons easier to follow, I have moved some of the claim elements of the BPAI-invalidated claims; the original positions of these elements in the issued claims is indicated by strikeout; the elements that have been re-inserted in different locations are [bracketed]. US 5,915,105 – claim 34 27. All of the basic elements of ’105 claim 34 are present in ’184 claims 22 and 23,

each of which is dependent on ’184 claim 13. The BPAI invalidated ’184 claim 22 in its January
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19, 2012 decision (Exhibit 16) as obvious over iAPX (Exhibit 30) in view of Lofgren (Exhibit 33); ’184 claim 23 was invalidated over iAPX in view of Inagaki (Exhibit 32). These claims are compared in Exhibit 2. 28. The differences in the wording of these claims are underlined in Exhibit 2 and are

summarized below: ’105 claim 34 feature synchronous memory device device claim internal clock generation circuitry to generate a first internal clock signal and a second internal clock signal using the first external clock output driver outputs data data is output in response to first and second internal clocks and synchronously with respect to the external clock signal clock receiver circuitry to receive the first external clock and the internal clock generation circuitry includes delay locked loop circuitry coupled to the clock receiver circuitry to generate the first and second internal clock signals using the external clock signal ’184 claims 22 and 23 features memory device method claim generating first and second internal clock signals using clock generation circuitry and the external clock signal sampling data data is sampled synchronously with respect to first and second external clock signal transitions generating an internal clock signal using a delay locked loop circuit and the external clock signal

In my opinion, these differences do not raise any new or different issues of patentability over the prior art that the BPAI determined invalidated ’184 claims 22 and 23. 29. iAPX discloses a “memory device” that is a “synchronous memory device.” I

understand that, in an appeal arising from another reexamination proceeding, the Federal Circuit has recently affirmed a BPAI decision that ’918 patent claim 18 is anticipated by iAPX. In re Rambus (Federal Circuit August 15, 2012); a copy of this decision is attached as Exhibit 25. In that case, the court construed the term “memory device” (page *15) as: a component of a memory subsystem, not limited to a single chip, where the device may have a controller that, at least, provides the logic necessary to receive and output specific data, but does not perform the control function of a CPU or bus controller.
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In addition, the Federal Circuit (pages *15-*16) affirmed the BPAI rejection of claim 18 as anticipated by iAPX (the same prior art reference attached here as Exhibit 30) which disclosed a “memory device” and anticipated claim 18 of the ’918 patent. This claim is included in Exhibit 25 (page 3), and actually recites a “synchronous memory device,’ so the Federal Circuit agreed that the “memory module” shown in Exhibit 30, Figure 1-2 (page 1-3) (and reproduced at page *5 of the Federal Circuit opinion) is both a “memory device” and a “synchronous memory device.” 30. This analysis is fully consistent with this Court’s construction of “synchronous

memory device”, which is “a memory device that receives an external clock signal which governs the timing of the response to a transaction request.”7 In iAPX, data is input into and output from the memory module, via the MACD bus (indicated in the same Figure 1-2), governed by (and synchronously with respect to) an external clock. For example, iAPX (Exhibit 30) Tables F-1 (page F-5) and F-2 (page F-6) show the bus (clock) cycle number “T” for each set of 16 bits (address, control, read data, and write data) transmitted on the bus in read, write, and other operations.8 A typical clock speed is 5 MHz.9 One of ordinary skill would understand from iAPX that the input and output of data is governed by this clock, and that the iAPX memory module is thus a “synchronous memory device” as well as a “memory device.” 31. In addition to its disclosure of a “synchronous memory device,” the above citations

are also examples that show not only that iAPX discloses a memory device, but also, as found by the BPAI, a method of operating this memory device. 32. iAPX mentions that “TTL drivers” are used to interface to the memory bus, and

one of skill would understand that this is a reference to “output drivers”10 In addition, as agreed between Hynix and Rambus, an “output driver” is simply “an element that outputs information from the device.”11 Since the iAPX memory module outputs data to the bus, one of ordinary skill
7

See Exhibit 26, the Court’s Claim Construction Order of November 15, 2004, page 14, lines 2224. iAPX (Exhibit 30), page F-2 (“The progression of time (0…C-1) where C is the number of bus cycles require to complete the message, is indicated in the T field of the tables…”). iAPX (Exhibit 30) page C-25. iAPX (Exhibit 30) page 4-1. See Exhibit 27, Joint Claim Construction and Prehearing Statement Pursuant to Patent Local - 10 -

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would understand the memory module has output drivers. 33. As discussed above, iAPX discloses both read operations and write operations. In

its decision regarding the ’184 patent, claim 23 (Exhibit 16, pages 26-30), the BPAI found that, in view of Inagaki, it would have been obvious to sample data from the bus synchronously with respect to both clock edges (some citations omitted): Skilled artisans at the time of the invention expected and pushed for higher speeds, reduced bus sizes would have been desirable simply to minimize parts, and even if the iAPX (modified) components (e.g., integrated DRAMS based on iRAM) could not have handled faster speeds prior to the invention, the iAPX system could have benefitted, at the time of the invention, from a slower clock’s dual pulses to double speed as a mere substitute to a faster clock, as Inagaki teaches. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Inagaki discloses use of both, complementary internal clocks (or sets of clock pulses) φ1 and φ2 to both sample data and to output data.12 Inagaki also discloses output circuitry for outputting data (Data Output Buffer). See Inagaki Figures 1, 3, 5, 7 and 9. For the same reasons given by the Board, it would have been obvious to combine the disclosures of iAPX and Inagaki and output data, at double the rate, in response to first and second internal clocks, as required by ’105 claim 31, from which claim 34 depends. 34. In addition, in rejecting claim 22 of the ’184 patent, the BPAI decided that it would

have been obvious to combine the teachings of Lofgren (Exhibit 33), which discloses delay locked loops, with iAPX. (Exhibit 16, page 30-31). The BPAI’s reasons are summarized at page 31 (some citations omitted): . . . Such delay loops simply provide finer tuning of clocks in the nature of an internal clock as produced from known external clocks, and would have been an obvious advantage in the iAPX clocked system, as Micron and the Examiner persuasively demonstrate, contrary to Rambus’s arguments. Such a finely tuned clock known in the art would have been obvious to employ in the iAPX clocked systems simply to provide better timing. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”). The same reasoning applies to claim 34 of the ’105 patent. In addition, Lofgren discloses that, using its disclosed delay locked loop, several internal delayed clocks with different delays can be Rule 4-3, September 12, 2003, page 4. See, for example, Inagaki (Exhibit 32), Figure 2. - 11 -

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generated from delay line 18 “for application to subsequent logic circuitry.” (Exhibit 33, Figure 5 and page 6, lines 13-18). Thus, the requirement in ’105 claim 34 that the delay locked loop circuitry generate two internal clocks, rather than the one internal clock recited in ’184 claim 22, is not a distinction over the prior art cited by the BPAI. 35. For these reasons, it is my opinion that ’105 claim 34 raises no new or different

issues of patentability over the prior art from those the BPAI determined invalidated ’184 claims 22 and 23. US 6,034,918 – claim 24 36. All of the basic elements of ’918 claim 24 are present in ’916 claim 26. The BPAI

invalidated ’916 claim 26 in its June 14, 2012 decision (Exhibit 14) as anticipated by Bennett (Exhibit 31) These claims are compared in Exhibit 3. 37. The differences in the wording of these claims are underlined in Exhibit 3 and are

summarized below: ’918 claim 24 feature synchronous memory device device claim receiving an external clock signal block size information is received from a bus controller read request is received from a bus controller register stores a delay time code representative of a number of clock cycles to transpire outputting data synchronously with respect to the external clock 38. ’916 claim 26 feature synchronous semiconductor memory device method claim clock receiver circuitry to receive an external clock signal block size information sampled synchronously with respect to external clock in response to a first (read) operation code to output data register stores a value that is representative of an amount of time to transpire data output

In my opinion, these differences do not raise any new or different issues of

patentability over the prior art that the BPAI determined invalidated ’916 claim 26.
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39.

The BPAI determined that Bennett discloses a “synchronous semiconductor

memory device” which is, according to the prior agreed construction of the parties (Exhibit 31, page 2)13 simply: “A synchronous memory device constructed with semiconductor material” Therefore, Bennett also discloses a “synchronous memory device.” (See Exhibit 14, pages

40.

Further, since the BPAI agreed that Bennett discloses a method of operating a

synchronous semiconductor memory, it follows that Bennett discloses a “synchronous memory device” itself. 41. As the BPAI found, Bennett also discloses “block size information” sampled by

input receiver circuitry that is part of the synchronous semiconductor memory device; the input receiver circuitry “receives” block size information. The BPAI determined that Bennett discloses two forms of block size information: first, in the programming of the configuration register to specify the size of the data word (Exhibit 14, pages 18-20) in, for example, single word read or write operations, and second, in the use of the “busy signal” to signify that additional data transfers are to be made in multiple word read and write operations. (Exhibit 14, pages 20-21) 42. I understand that this Court has also previously analyzed whether Bennett discloses

block size information in its December 15, 2008 Order regarding two motions for summary judgment. (Exhibit 28, Docket No. 1832 in Case No. C-05-00334 RMW.) In that decision, the Court agreed that Bennett’s parameters VII and VIII, stored in a configuration register in the versatile bus interface of a “VSLIC device,” represented “block size information,” as construed by the Court. (E.g., Exhibit 28, pages 31:24 – 32:21.) While this Court disagreed that the “busy signal” represented block size information (id., pages 31:13-23), in my opinion one instance of “block size information” is sufficient. 43. In ’918 claim 18, both “block size information” and a “read request” are received

by the memory device from a “bus controller.” The term “bus controller” is used only once in the ’918 specification, at column 6, line 6, and is simply an alternate term for a “master”, which sends
13

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control signals to “slave” devices such as DRAMs and SRAMs. “Bus controller” has not been construed in this litigation. 44. The term “master” in the ’918 patent is referred to as a microprocessor. The only

reference to the term “controller” in the ’918 patent other than in the claims is with respect to a disk controller or a DMA controller. See ’918 patent, col. 6:13-15 and 21-23. Neither of these controllers is referenced with respect to setting of registers to configure devices during an initialization process. In the disclosure of the ’918 patent, internal registers in devices on the bus are configured in an initialization process using what is referred to as a “configuration master.” This is described, for example, at column 14, lines 55-67 of the ’918 patent. One of ordinary skill in the art would understand from reading this description that, after the system is initialized, the “configuration master” operates like any other master in the system, sending read and write requests and receiving and sending data. 45. In the preferred embodiment of Bennett, parameters VII and VIII are received from

a “maintenance processor”, separate from the VSLIC devices that may communicate with Bennett memory devices in read or write operations by (for example) sending read and write requests. The Bennett maintenance processor (in the preferred embodiment) is responsible for configuring all devices in the Bennett systems through their “VM nodes.” The Bennett maintenance processor provides block size information to all devices in the Bennett systems in the same manner as in the ’918 patent. That is, configuration registers are loaded with data provided by the processor during an initialization process. The maintenance processor in the Bennett system is contrasted with a central processor, since the function of the maintenance processor is to provide information to the Bennett memory devices to determine how the memory devices will operate, while the address, data, and control signals for read and write operations are managed by separate (multiple) “ masters”, typically processors 46. In Bennett, the tasks of initialization of the system (including loading the registers

in the individual devices) and of managing read and write transactions are divided between the single maintenance processor and multiple “master” processors. In the ’918 patent, “configuration master” combines the functionality of the Bennett maintenance processor with that of one of the
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“masters” (such as one of the CPUs). The difference is that, in Bennett, the combined functionality is divided between two components of the system rather than the single component “configuration master.” 47. By analogy to the reasoning of the Federal Circuit in In re Rambus (Exhibit 25),

which held that “memory device” was not limited to a single chip device, there is no reason why a “bus controller” should be limited to a single device, such as either a Bennett processor or a Bennett master processor. I understand that, in an additional pending Rambus litigation, involving claims of infringement of several Farmwald/Horowitz patents by LSI Corporation and STMicroelectronics N.V., a very similar issue – whether a “controller” was limited to a singlechip device – was decided against such a limitation. (Exhibit 29, pages 6-9) In my view, the “bus controller” in Bennett is distributed between two VSLIC devices – the maintenance processor and one of the master processors. This Bennett bus controller provides both block size information and a read request to the Bennett memory, as required by the claim. 48. Claim 26 of the ’916 patent refers to an operation code that causes a read operation

(i.e., one in which data is output from the memory device). In contrast, ’918 claim 24 recites a “read request.” I understand that, consistent with the Federal Circuit decision in the Infineon litigation, the parties agreed that a “read request” is: “a series of bits used to request a read of data from a memory device where the request identifies what type of read to perform” (Exhibit 27, page numbered “1”). This is more specific than an “operation code,” which is simply “one or more bits to specify a type of action.” (Exhibit 26, page 31) Nevertheless, Bennett discloses a “read request” under this construction. 49. Bennett discloses several types of read operations, including both a (single word)

read operation and a “read-modify-write” operation. (Exhibit 31, Figure 31 and col. 90:43-91:23.) A read-modify-write operation was well known by 1982, when the Bennett application was filed, and was an operation in which a word was read from memory, modified (in the CPU, for example) and written back into the same memory location from which it was read. Such an operation allowed efficient modification of part of the word without conducting separate (and thus more time-consuming) read and write operations. Bennett therefore discloses a “read request”; both a
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single word read and a read modify write operation start with a read of data, but Bennett has at least two types of “read” that may be conducted, and thus are “identified.” 50. The register recited in claim 26 of the ’916 patent stores a value that is

representative of “of an amount of time” to transpire, while ’918 claim 24 is more specific and recites that the code stored in the register is representative of “a number of clock cycles” to transpire. The BPAI only actually decided that the former was satisfied on Bennett (Exhibit 14, page 11-18), but the “amount of time” identified in Bennett (as Rambus’s arguments admitted) was a delay time of either 0 or 1 (external clock) cycle. (Exhibit 14, page 13, footnote 7) Bennett thus discloses the storage of a value that represents “a number of clock cycles,” and this difference in language does not distinguish the Bennett disclosure. In Bennett a clock frequency of 25 Mhz translates directly to a time of 40 nanoseconds for each clock cycle. A delay of 1 clock cycle in Bennett is clearly “representative” of an amount of time of 40 nanoseconds or 1 clock cycle that is stored in a register in Bennett. 51. Finally, claim 24 of the ’918 patent recites data is output “synchronously with

respect to the external clock signal”, whereas ’916 claim 24 does not explicitly mention such a relationship. However, since a “synchronous memory device” is "a memory device that receives an external clock signal which governs the timing of the response to a transaction request" (Exhibit 26, page 14), this means that the timing of data output in ’916 claim 24 is “governed” by the external clock. Moreover, data output (as well as input) in Bennett is clearly synchronous with the external clock, as can be seen by simple inspection of, for example, Fig. 52b or other figures. (Exhibit 31, sheet 35.) 52. In summary, these differences between ’918 claim 24 and ’916 claim 26 do not

raise any new or different issues of patentability over the prior art (Bennett) that the BPAI determined invalidated ’916 claim 26. US 6,034,918 – claim 33 53. All of the basic elements of ’918 claim 33 are present in ’120 claim 4, which is

dependent on claim 1, and ’184 claim 22. The BPAI invalidated ’120 claim 4 in its January 19, 2012 decision (Exhibit 10) as anticipated by iAPX (Exhibit 30). The BPAI invalidated ’184 claim
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22 in its January 19, 2012 decision (Exhibit 16, page 30-31) as obvious over iAPX (Exhibit 30) in view of Lofgren (Exhibit 33) These claims are compared in Exhibit 4. 54. The differences in the wording of these claims are underlined in Exhibit 4 and

summarized below: ’918 claim 33 feature synchronous memory device receiving block size information from a bus controller receiving a read request from a bus controller outputting data synchronously with respect to the external clock signal generating at least one internal clock signal using a delay locked loop and the external clock signal wherein data corresponding to the block size information is output synchronously with respect to at least one internal clock signal 55. ’120 claim 4 features synchronous memory device receiving block size information receiving a first (read) operation code outputting data synchronously with respect to the external clock signal ’184 claim 22 features memory device receiving block size information from a master receiving a first write request from the master sampling data synchronously with respect to an external clock signal generating an internal clock signal using a delay locked loop circuit and the external clock signal wherein the amount of data corresponding to the block size information is sampled synchronously with respect to the first and second internal clock signals.

In my opinion, these differences do not raise any new or different issues of

patentability over the prior art that the BPAI determined invalidated ’120 claim 4 and ’184 claim 22. 56. As discussed above (paragraph 29), the Federal Circuit has agreed that iAPX

discloses a “memory device” that is “synchronous.” 57. In iAPX, memory requests (and write data) from the GDP processor are sent on the

MACD bus to the memory module by the Bus Interface Unit (BIU). (Exhibit 30, Figure 1-2 and page 1-3) Data is returned (for read operations) to the BIU from the memory module; the BIU is a “master” on the MACD bus and a bus controller for that bus. Further, each request to the memory module contains both an instruction as to the type of operation to be performed and the block size

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– “LLLL”, the number of bytes of data to be transferred. 58. The “read request” of ’918 claim 33 is a narrower term than the (read) operation

code of ’120 claim 1, as discussed above in paragraphs 48 and 49. However, iAPX discloses both a “read request” (with operation code “0000”) and an “RMW read request” (with operation code “0010”). (Exhibit 30, page F-5) (“RMW” stands for read-modify-write; see Exhibit 1, page 4-7.) Thus, similarly to Bennett (see paragraphs 48 and 49, above), iAPX disclosed a read request as construed in this case. 59. As is apparent from its rejections of both ’120 claim 4 and ’184 claim 22, the BPAI

has determined that iAPX discloses both read and write operations over the synchronous MACD bus and that iAPX discloses (at least) both outputting data synchronously with respect to an external clock signal and sampling data in response to an internal clock signal. In such a synchronous system, all data output to such a synchronous bus is actually output using an internal clock signal derived from an external clock, and is therefore synchronous with respect to the external clock and to the internal clock signal that is derived from the external signal. An example is disclosed in the ’918 patent; the circuitry that generates the internal clock is more complex than is typical, but it is still the internal clocks that are used to send the data to the output drivers that actually output the data. See ’918 Figure 10 and column 21:42-50. Since data is output synchronously with respect to the external clock signal, data necessarily must also be output synchronously with respect to the internal signal. The same internal clock(s) that are used to output data, as in the circuitry disclosed in the ’918 patent, are also used to sample data during write operations. In a synchronous system, data is both read (output) and written (sampled) in response to and synchronously with respect to an internal clock and synchronously with respect to the external clock 60. Further, the Board agreed (Exhibit 16, page 31) that it would be obvious in view of

the teachings of Lofgren (Exhibit 33) to use a delay locked loop with the iAPX memory module: . . . Such delay loops simply provide finer tuning of clocks in the nature of an internal clock as produced from known external clocks, and would have been an obvious advantage in the iAPX clocked system, as Micron and the Examiner persuasively demonstrate, contrary to Rambus’s arguments. Such a finely tuned clock known in the art would have been obvious to employ in the iAPX clocked
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systems simply to provide better timing. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”). The same reasoning applies to the read operation of claim 33 of the ’918 as the write operation of claim 22 of the ’184 patent. 61. For these reasons, the differences between ’918 claim 33, ’120 claim 4, and ’184

claim 22 do not raise any new or different issues of patentability over the prior art (iAPX and Lofgren) that the BPAI determined invalidated ’120 claim 4, and ’184 claim 22. US 6,378,020 – claim 32 62. As noted above (in footnote 6), the examiner’s decisions in the ’020 inter partes

reexaminations are currently on appeal by Micron before the PTAB (formerly called the BPAI). Micron could have, but chose not to appeal the examiners confirmance of claim 32. Nevertheless, it is my opinion that, based on prior BPAI decisions, claim 32 of the ’020 patent is invalid. 63. All of the basic elements of ’020 claim 32 are present in ’120 claim 4, which is

dependent on claim 1, and ’184 claim 14, which depends on claim 13. The BPAI invalidated ’120 claim 4 in its January 19, 2012 decision (Exhibit 10) as anticipated by iAPX (Exhibit 30). The BPAI invalidated ’184 claim 14 (which depends on ’184 claim 13) in another January 19, 2012 decision (Exhibit 16, pages 26-30) as obvious over the combination of iAPX (Exhibit 30) and Inagaki (Exhibit 32). These claims are compared in Exhibit 5. 64. The differences in the wording of these claims are underlined in Exhibit 5 and are

summarized below: ’020 claim 32 feature integrated circuit device device claim input receiver circuitry to sample a (read) operation code sampled synchronous with respect to a first transition of an external clock ’120 claim 4 features synchronous memory device method claim sampling the first (read) operation code sampled synchronously with respect to an external clock ’184 claim 14 features memory device method claim receiving a write request from the master

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’020 claim 32 feature output driver circuitry to output data in response to the operation code the output driver circuitry outputs data in response to rising and falling edges of the external clock input receiver circuitry receives address information synchronously with respect to the external clock signal. 65.

’120 claim 4 features data is output in response to the first operation code (via output driver circuitry)

’184 claim 14 features

data sampled synchronously with respect to first and second transitions of the external clock

In my opinion, these differences do not raise any new or different issues of

patentability over the prior art that the BPAI determined invalidated in ’120 claim 4 and ’184 claim 14. 66. The term “integrated circuit device” is not present in the ’020 patent except in the

claims (and the later-added abstract). The integrated circuit device recited in claim 32 is a memory device as disclosed in the specification. No other type of device is disclosed or suggested, and the claim is to be read in view of this specification. Additionally, the claimed device claimed in claim 32 has addressing, memory cells for storage of data and reading (outputting) data using output drivers. Such a device is a memory device. Further, as noted above, the BPAI invalidated ’184 claim 14 as obvious over the combination of iAPX (Exhibit 30) and Inagaki (Exhibit 32). The MOS RAM in Inagaki would have been known by one of ordinary skill in the art to be a single chip or more formally an “integrated circuit device.” See Inagaki Figure 1. There is no difference between the memory device of the ’184 patent and the integrated circuit device of the ’020 patent. 67. For reasons analogous to those discussed above (see paragraphs 31 and 40, for

example), the BPAI found that iAPX disclosed a method of operating a device, and thus implicitly determined that iAPX discloses the device itself. 68. The Board also determined, as is evident from its holdings regarding ’120 claim 4

and ’184 claim 13, iAPX also discloses both read and write operations. In addition, I understand

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that the Federal Circuit in its Infineon decision construed “write request” as “a series of bits used to request a write of data to a memory device,” without requiring that it identify a “type of write.” Other than the direction in which data is (later) transferred, a write request is essentially the same as a (read) operation code. 69. In its decision regarding the ’184 patent, claim 14 (Exhibit 16, pages 26-30), the

BPAI found that, in view of Inagaki, it would have been obvious to sample data from the bus synchronously with respect to both clock edges (Exhibit 16, page 31; some citations omitted): Skilled artisans at the time of the invention expected and pushed for higher speeds, reduced bus sizes would have been desirable simply to minimize parts, and even if the iAPX (modified) components (e.g., integrated DRAMS based on iRAM) could not have handled faster speeds prior to the invention, the iAPX system could have benefitted, at the time of the invention, from a slower clock’s dual pulses to double speed as a mere substitute to a faster clock, as Inagaki teaches. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). 70. Inagaki discloses use of both, complementary internal clocks (or sets of clock

pulses) φ1 and φ2 to both sample data and to output data.14 For the same reasons given by the Board, it would have been obvious to combine the disclosures of iAPX and Inagaki and output data, at double the rate, in response to first and second internal clocks, as required by ’020 claim 32. Further, it would make no sense to input data in a write operation on both the rising and falling edges of the external clock and not output data (in a read operation) in response to both rising and falling edges of the external clock, at least where the same set of lines is used for the data in both read and write operations. 71. The BPAI has not been asked (and has not decided) whether iAPX discloses

“address information received synchronously with respect to the external clock.” However, in a synchronous system, address information is presented to the memory in the same manner as all other data inputs, data outputs, read requests or write requests; that is, synchronously with respect to the external clock. Otherwise, a read or write operation would be meaningless without definition of where to read data from or where to write data to. Further, it is readily apparent that iAPX does disclose this limitation. In most of the types of requests used in iAPX, including all

14

See, for example, Inagaki (Exhibit 3), Figure 2. - 21 -

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

claim 14 do not raise any new or different issues of patentability over the prior art (iAPX and Lofgren) that the BPAI determined invalidated ’120 claim 4 and ’184 claim 14. US 6,378,020 – claim 36 73. As noted above (in footnote 6 and paragraph 62), the examiner’s decisions in the

’020 inter partes reexaminations, including his decision to confirm claim 36, are currently on appeal by Micron before the PTAB. Nevertheless, it is my opinion that claim 36 is invalid based on BPAI decisions that have already issued. 74. All of the basic elements of ’020 claim 36 are present in ’184 claims 22 and 23,

each of which is dependent on ’184 claim 13, and ’120 claim 4, which depends on claim 1. The BPAI invalidated ’184 claim 22 in its January 19, 2012 decision (Exhibit 16) as obvious over iAPX (Exhibit 30) in view of Inagaki (Exhibit 32); ’184 claim 23 was invalidated over iAPX in view of Lofgren (Exhibit 33). The BPAI invalidated ’120 claim 4 in its January 19, 2012 decision (Exhibit 10) as anticipated by iAPX (Exhibit 30). These claims are compared in Exhibit 6. 75. The differences in the wording of these claims are underlined in Exhibit 6 and

summarized below: ’020 claim 32 feature integrated circuit device device claim input receiver circuitry to sample a (read) operation code sampled synchronous with respect to a first transition of an external clock
15

’120 claim 4 features synchronous memory device method claim sampling the first (read) operation code sampled synchronously with respect to an external clock

’184 claim 14 features memory device method claim receiving a write request from the master

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’020 claim 32 feature output driver circuitry to output data in response to the operation code the output driver circuitry outputs data in response to rising and falling edges of the external clock input receiver circuitry receives address information synchronously with respect to the external clock signal. 76.

’120 claim 4 features data is output in response to the first operation code (via output driver circuitry)

’184 claim 14 features

data sampled synchronously with respect to first and second transitions of the external clock

In my opinion, these differences do not raise any new or different issues of

patentability over the prior art that the BPAI determined invalidated ’120 claim 4 and ’184 claims 22 and 23. 77. The term “integrated circuit device” is not present in the ’020 patent except in the

claims (and the later-added abstract). The integrated circuit device recited in claim 32 is a memory device as disclosed in the specification. No other type of device is disclosed or suggested, and the claim is to be read in view of this specification. Additionally, the claimed device claimed in claim 32 has addressing, memory cells for storage of data and reading (outputting) data using output drivers. Such a device is a memory device. Further, as noted above, the BPAI invalidated ’184 claim 14 as obvious over the combination of iAPX (Exhibit 30) and Inagaki (Exhibit 32). The MOS RAM in Inagaki would have been known by one of ordinary skill in the art to be a single chip or more formally an “integrated circuit device.” See Inagaki Figure 1. There is no difference between the memory device of the ’184 patent and the integrated circuit device of the ’020 patent. As discussed above (for example, paragraphs 31, 40, and 67), the recitations of a “device” rather than a “method” and a read operation code (and read operation) instead of a write request (and write operation) do not distinguish the prior art considered by the BPAI in connection with its analysis of the ’184 claims. 78. Also, analogously to the discussion in paragraphs 33, 69, and 70, the difference

between outputting data in response to both external clock edges and sampling data synchronously

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with respect to both external clock transitions is not significant, based on the Board’s reasoning regarding the combination of iAPX and Lofgren. The same internal clocks are used to both input data for a write operation and output data for a read operation. And, since the Board agreed that iAPX discloses both read and write operations, the recitation of an output driver in ’020 claim 36 does not distinguish the iAPX, as discussed above in paragraph 33. 79. The Board also determined, as is evident from its holdings regarding ’120 claim 4

and ’184 claim 13, iAPX also discloses both read and write operations. In addition, I understand that the Federal Circuit in its Infineon decision construed “write request” as “a series of bits used to request a write of data to a memory device,” without requiring that it identify a “type of write.” Other than the direction in which data is (later) transferred, a write request is essentially the same as a (read) operation code. 80. In its decision regarding the ’184 patent, claim 14 (Exhibit 16, pages 26-30), the

BPAI found that, in view of Inagaki, it would have been obvious to sample data from the bus synchronously with respect to both clock edges (Exhibit 16, page 31; some citations omitted): Skilled artisans at the time of the invention expected and pushed for higher speeds, reduced bus sizes would have been desirable simply to minimize parts, and even if the iAPX (modified) components (e.g., integrated DRAMS based on iRAM) could not have handled faster speeds prior to the invention, the iAPX system could have benefitted, at the time of the invention, from a slower clock’s dual pulses to double speed as a mere substitute to a faster clock, as Inagaki teaches. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). 81. Inagaki discloses use of both, complementary internal clocks (or sets of clock

pulses) φ1 and φ2 to both sample data and to output data.16 For the same reasons given by the Board, it would have been obvious to combine the disclosures of iAPX and Inagaki and output data, at double the rate, in response to first and second internal clocks, as required by ’020 claim 32. Further, it would make no sense to input data in a write operation on both the rising and falling edges of the external clock and not output data (in a read operation) in response to both rising and falling edges of the external clock, at least where the same set of lines is used for the data in both read and write operations. In any event, Inagaki discloses output circuitry to output data on both the rising and falling edges of the external clock – Data Output Buffer 60.
16

See, for example, Inagaki (Exhibit 32), Figure 2. - 24 -

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82.

The parties agreed that a “clock alignment circuit” is “a circuit for adjusting the

timing relationship between a clock signal and another signal.” (Exhibit 27, page numbered 3) This same function is performed by a delay locked loop circuit, and Rambus contended in the 2006 patent trial that Hynix’s DDR SDRAM chips satisfied the “clock alignment circuit” limitation because they have a delay locked loop circuit. (Exhibit 39, 2006 patent trial transcript, March 20, 2006, pages 502, line 6 – 503, line 6) While “clock alignment circuit” may be a broader term than “delay locked loop circuit”, the former is present where, as the BPAI determined, it would have been obvious to combine the delay locked loop circuit concept of Lofgren (Exhibit 33) in iAPX (Exhibit 30). 83. As discussed above in paragraph 33, the difference between outputting data in

response to internal clocks and sampling data synchronously with respect to internal clocks does not serve to distinguish ’020 claim 36 from the Board’s analysis of the combination of iAPX and Lofgren. 84. In summary, the differences between ’020 claim 36 and ’184 claims 22 and 23 as

well as ’120 claim 4 do not raise any new or different issues of patentability over the prior art (iAPX and Lofgren) that the BPAI determined invalidated ’184 claims 22 and 23 and ’120 claim 4. US 6,426,916 – claim 9 85. All of the basic elements of ’916 claim 9 are present in ’916 claim 26 and ’120

claim 33, which is dependent on claim 26. The BPAI invalidated ’916 claim 26 in its June 14, 2012 decision (Exhibit 14) as anticipated by Bennett (Exhibit 31) and invalidated ’120 claim 33 in its January 19, 2012 decision (Exhibit 10) as obvious over the combination of Bennett and Wicklund (Exhibit 36), Olson (Exhibit 35), or Bowater (Exhibit 34). These claims are compared in Exhibit 7. /// /// /// ///
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86.

The differences in the wording of these claims are underlined in Exhibit 7 and

summarized below: ’916 claim 9 features synchronous memory device method claim receiving a value that is representative of a number of external clock signal cycles to transpire after which the memory device responds to a first operation code receiving block size information ’916 claim 26 features synchronous semiconductor memory device device claim a register which stores a value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data input receiver circuitry to sample block size information synchronously with respect to the external clock signal block size information is sampled synchronously with respect to the external clock signal in response to a first operation code output drivers output data in response to the first operation code after the amount of time transpires input receiver circuitry with a plurality of input receivers to sample block size information the input receiver circuitry samples the first operation code synchronously with respect to the external clock signal output drivers output data in response to the first operation code operation code includes precharge information ’120 claim 33 features synchronous dynamic random access memory device device claim

sampling the first operation code synchronously with respect to a transition of the external clock signal data output after the number of clock cycles transpire

operation code includes precharge information 87.

In my opinion, these differences do not raise any new or different issues of

patentability over the prior art that the BPAI determined invalidated ’916 claim 26 and ’120 claim 33. 88. The BPAI agreed with the examiner that Bennett disclosed both a “synchronous

semiconductor memory device” and a “synchronous dynamic random access memory device.” Each of these is a type of “synchronous memory device” under the agreed claim constructions in this case (Exhibit 27, page numbered 2); as a result, Bennett discloses a “synchronous memory device.”
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89.

Bennett also discloses a method of operating a “synchronous dynamic random

access memory device,” as the Board implicitly found in its decision invalidating claim 34 of the ’037 patent. (Exhibit 18, pages 3 and 12.) 90. In its decision regarding the ’916 patent (Exhibit 14) the Board determined that

Bennett discloses the register storing a “value representing an amount of time to transpire” before outputting data. As discussed above in paragraph 50, the configuration register values can be set such that the delay time is either zero or one clock cycle. Since Bennett discloses the “value” recited in claim 9, the difference in language between claims 9 and 26 of the ’916 patent cannot patentably distinguish claim 9 over Bennett. In Bennett a clock frequency of 25 Mhz translates directly to a time of 40 nanoseconds for each clock cycle. A delay of 1 clock cycle in Bennett is clearly “representative” of an amount of time of 40 nanoseconds or 1 clock cycle that is stored in a register in Bennett. In order for the register storing a “value representing an amount of time to transpire” to be stored, the data for such register must be received by the Bennett circuits. Additionally, outputting of data is in response to a read operation code in Bennett is the common and expected result of a read operation in a memory device. 91. All transactions in Bennett (determined by operation codes) are synchronous with

respect to the external clock. See, for example, Figures 13; 25a,b,c,d.; 30; 52a-1; 52e-1; 129a; and 134. Also see col. 67, lines 1-5 and 17-18. 92. Claim 9 of the ’916 patent does not mention input receivers, but these are just

“element[s] on the device to receive one or more signals from an external source” (Exhibit 31, page numbered 4), and the “block size information” in Bennett (configuration parameters VII and VIII; see paragraphs 41-42, above) is received from an external source – the maintenance processor, in the preferred embodiment. As result, the device of claim 9 implicitly includes input receiver circuitry to receive the block size information; in any event, the language in claim 9, to the extent it can be read to be broader than the language in ’916 claim 26 or ’120 claim 33, is satisfied by Bennett. 93. Finally, although the “precharge information” limitation is not included in ’916

claim 26, the BPAI found in its ’120 decision that “the Examiner erred in refusing to maintain the
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obviousness rejection of claim 33 based on Bennett and Wicklund, Bowater, or Olson.” (Exhibit 10, page 18). In my opinion, there is no reason why the analogous conclusion would not apply to claim 9, since precharge information was found in the obviousness combinations based on Bennett and Wicklund, Bowater, or Olson. 94. For these reasons, the differences between ’916 claim 9 and ’916 claim 26 and ’120

claim 33 do not raise any new or different issues of patentability over the prior art (Bennett and Wicklund, Bowater, or Olson) that the BPAI determined invalidated ’916 claim 26 and ’120 claim 33. US 6,426,916 – claim 40 95. All of the basic elements of ’916 claim 40 are present in ’916 claim 26 and ’184

claim 22, which depends on claim 13. The BPAI invalidated ’916 claim 26 in its June 14, 2012 decision (Exhibit 14) as anticipated by Bennett (Exhibit 31). BPAI invalidated ’184 claim 22 in its January 19, 2012 decision (Exhibit 16) as obvious over iAPX (Exhibit 30) in view of Lofgren (Exhibit 33). These claims are compared in Exhibit 8. 96. Claim 40 of the ’916 patent is dependent on claim 26, which the BPAI invalidated

as anticipated by Bennett. (Exhibit 14, page 22). Claim 40 was not at issue before the BPAI because Micron did not seek reexamination of that claim, but only sought reexamination of claims 26 and 28 and did not appeal any other claims to the BPAI. (Exhibit 14, page 2) 97. As shown in Exhibit 8, the differences between ’916 claim 40 and ’916 claim 26

are the added limitations that the memory device of claim 26 further includes: delay lock loop circuitry, coupled to the clock receiver circuitry, to generate an internal clock signal, wherein the plurality of output drivers output the amount of data in response to the internal clock signal. In my opinion, these additional limitations of claim 40 do not raise any new or different issues of patentability over the prior art that the BPAI determined invalidated ’916 claim 26 and ’184 claim 22. 98. Claim 22 of the ’184 patent recites generating an internal clock signal using a delay

locked loop (and the external clock) and using the internal clock to sample write data. Claim 40 of the ’916 patent recite essentially the same thing, except that the internal clock is used to cause data
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output. The same internal clock is used to both sample write data and to output data. The BPAI invalidated claim 22 of the ’184 patent over a combination of iAPX (Exhibit 30) and Lofgren (Exhibit 33), reasoning: . . . Such delay loops simply provide finer tuning of clocks in the nature of an internal clock as produced from known external clocks, and would have been an obvious advantage in the iAPX clocked system, as Micron and the Examiner persuasively demonstrate, contrary to Rambus’s arguments. Such a finely tuned clock known in the art would have been obvious to employ in the iAPX clocked systems simply to provide better timing. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”). The same reasoning applies to the read operation and, in particular, the read operation in Bennett. The external clocking system disclosed as part of Bennett’s preferred embodiment (see Exhibit 31, Figure 84 and column 105, lines 50-65) is different from the external clocking disclosed in iAPX. However, the well-known function and purpose of a delay locked loop is to correct for internal clocking delays within a device, and does not affect the external clocking except, by reducing or eliminating internal delays, to allow for a faster external clock because the external clocking no longer needs to compensate for the internal delays. In Bennett, the internal clocks are generated from the external clock with a “clock tree” that involves passing the external clock signal through a minimum of two inverters. (Exhibit 31, Figure 134 and column 34, lines 1-3.) In 1982, when Bennett was filed, a typical inverter delay (the time between inputting a signal into an inverter and providing an inverted output) exceeded 2 ns, and the delay through two inverters would have exceeded 4 ns, a significant fraction of the 40 ns clock period of Bennett’s preferred embodiment. The load on each of the clock drivers can add another 4ns to the clock delay of some drivers. Although inverter delays have decreased as semiconductor processes have improved, reducing or eliminating these delays has always had known benefits in the design of CMOS integrated circuits. In my view, it would have been obvious to use delay locked loop circuitry in Bennett just as it was found to be obvious by the Board with respect to iAPX. Similarly, the benefits of using a delay locked loop to reduce or eliminate internal delays between the external and the internally generated clocks would be the same for the timing of data output in a read operation and for data sampling or input in a write operation.

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99.

In fact, in its September 27, 2012 decision (Exhibit 21) regarding another

Farmwald/Horowitz patent, the ’446 patent”, the Board confirmed the obviousness of using a delay-locked loop with Bennett. (In Exhibit 33, the text of claims 1-4 of the ’446 patent is set out on page 4 of this decision.) In summary, claim 4 of the ’446 patent is directed to a “synchronous integrated circuit device” having autoprecharge, output drivers, and a delay locked loop to synchronize data output to the external clock. The Board reversed the Examiner’s decision to confirm claim 4 (as well as claims 1-3), and determined that claim 4 was obvious over Bennett (Exhibit 31), in combination with Wicklund (Exhibit 36) and Lofgren or Bazes (Exhibits 33 and 38). (See Exhibit 21, pages 25-29) In particular, the Board stated, similarly to its reasoning regarding the combination of iAPX and Lofgren (quoted above), that: While Rambus asserts that Micron does not explain how the DLL would be implemented with Bennett’s timing scheme, Micron’s explanation shows that, on this record, since Bennett discloses internal clock delays implemented with that scheme, providing a DLL to better control the internal timing synchronization and account for wafer process variations would have been obvious. (Exhibit 21, page 25) 100. In my opinion, accepting the reasoning and result of the BPAI in invalidating claim

22 of the ’184 patent over the combination of iAPX and Lofgren, claim 40 of the ’916 patent presents no new or different issues of patentability over the prior art considered by the BPAI in invalidating ’916 claim 26 and ’184 claim 22. US 6,452,863 – claim 16 101. This claim is currently on appeal before the PTAB (formerly, the BPAI), as noted

in footnote 6, above, in Rambus’s appeal from the rejection of this (and other) claims of the ’863 patent. Nevertheless, in my opinion, ’863 claim 16 is invalid based on decisions the BPAI has already issued. 102. All of the basic elements of ’863 claim 16 are present in ’184 claim 10, which is

dependent on claim 1, and ’184 claim 13 . The BPAI invalidated ’184 claim 10 in its January 19, 2012 decision (Exhibit 16) as obvious over iAPX (Exhibit 30) in view of Inagaki (Exhibit 33). The BPAI also invalidated ’184 claim 13 in its January 19, 2012 decision (Exhibit 16) as anticipated by iAPX (Exhibit 30) in view of Inagaki (Exhibit 32); ’184 claim 23 was invalidated
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over iAPX in view of Lofgren (Exhibit 33). These claims are compared in Exhibit 9. The differences in the wording of these claims are summarized below and underlined in Exhibit 9: ’863 claim 16 feature synchronous memory device method of operation receiving block size information from a memory controller memory device is capable of processing block size information wherein the block size information represents a first amount of data to be input by the memory device in response to an operation code receiving the (write) operation code from the memory controller synchronously with respect to an external clock signal inputting data in response to the operation code ’184 claim 10 feature memory device method of controlling providing block size information block size information defines data to be sampled by the memory device in response to a write request (operation code) ’184 claim 13 features memory device method of operation receiving block size information from a master receiving a first write request from the master (a controller)

issuing a write request (operation code) to the memory device

receiving a first write request from the master

write data is provided synchronously with respect to first transition of external clock the first amount of data corresponding to the first block size information is provided synchronously during a plurality of clock cycles of the external clock signal.

sampling data synchronously with respect to an external clock signal

data is sampled over a plurality of clock cycles of the external clock signal

103.

In my opinion, these differences do not raise any new or different issues of

patentability over the prior art that the BPAI determined invalidated ’184 claim 10. 104. As discussed above (paragraph 29), the Federal Circuit affirmed the invalidity of

claim 18 of the ’918 patent over iAPX; although the focus of the appeal was the construction of “memory device”, claim 18 in fact recited a “synchronous memory device.” This difference in the language between ’863 claim 16 and ’184 claim 10 is thus not one that raises any new issue of the
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patentability of claim 16. 105. The main differences between the claims arise from the phrasing (in ’184 claim 10)

of signals provided to the memory device, while claim 16 of the ’863 patent is written in terms of the (same) signals received by the memory device. This difference is one only of perspective and not of the steps performed. 106. Claim 16 of the ’863 patent recite receipt of block size information from a memory

controller, but this is the same, in the context of the patent specifications, as receiving block size information from a “master”, as required by ’184 claim 13. The only masters disclosed in the patent that can send block size information are microprocessors that are also ”bus controllers.” 107. In iAPX, memory requests (and write data) from the GDP processor are sent on the

MACD bus to the memory module by the Bus Interface Unit (BIU). (Exhibit 30, Figure 1-2 and page 1-3) Data is returned (for read operations) to the BIU from the memory module; the BIU is a “master” on the MACD bus and a bus controller for that bus. Further, each request to the memory module contains both an instruction as to the type of operation to be performed and the block size – “LLLL”, the number of bytes of data to be transferred. 108. There is no significant difference between an “operation code” directing a write

operation and a write request. The Federal Circuit, in its Infineon decision, construed “write request” as “a series of bits used to request a write of data to a memory device.” On the other hand, an “operation code” is simply "one or more bits to specify a type of action.” (Exhibit 30, page 19:15-16) The words “a series of bits” and “one or more bits” address precisely the same issue. The words “used to request a write of data” and “to specify a type of action” address precisely the same issue. Reading and writing to a memory device are types of actions. Since iAPX has a “write request” under the BPAI decision, iAPX also discloses a (write) “operation code.” 109. Data input “synchronously with respect to a first transition of the external clock”

is, at least for present purposes, the same concept as “synchronously with respect to the external clock.”(See Exhibit 30, page F-3) ///
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110.

In addition, both ’863 claim 16 and ’184 claim 10 recite transmission of write data

over (“during”) a plurality of clock cycles of the external clock signal; the only difference between these aspects of the claims is, again, whether the step is viewed from the perspective of the memory device (which receives or samples write data) or from that of the controller (which provides write data). 111. In my view, therefore, there are no differences between ’863 claim 16 and ’184

claims 10 and 13 that present any new or different issues of patentability over the prior art considered by the BPAI in invalidating ’184 claim 10. 112. I understand that several of the above claims at issue in the 2006 patent trial were

the subject of additional, ex parte, reexamination requests, filed on behalf of Hynix, in which the claims were confirmed. Because these other reexaminations were ex parte proceedings, my understanding is that Hynix had no right to participate in those proceedings after the initial request was filed and had no right to appeal the examiner’s decision to the BPAI or the Federal Circuit. In addition, the results of these other, ex parte reexaminations are not relevant here because either different prior art was considered or because the examiner’s decisions were based on determinations that were reversed by the BPAI in the decisions discussed above, which resulted from either Rambus’s or Micron’s appeals in the course of inter partes reexamination proceedings. 113. Claim 34 of the ’105 patent was confirmed by the examiner in the course of each of

three ex parte reexaminations filed by Hynix. The first, serial number 90/010,419, was based on Redwine, US 4,330,852, and Ono, JP 64-043894, Lofgren (Exhibit 33), and Bazes (Exhibit 38); this request was granted, but claim 34 was ultimately confirmed; the main references in the BPAI decisions discussed above, iAPX (Exhibit 30) and Bennett (Exhibit 31), were not submitted with or considered in this first reexamination. The second, serial number 90/010,872, was based on Bennett (Exhibit 31), Inagaki (32), Lofgren (Exhibit 33), and Bazes (Exhibit 38); this request was denied for lack of a presentation of a substantial new question of patentability. The third, serial number 90/010,975, also based on Bennett, Inagaki, Lofgren, and Bazes, was granted, but claim 34 was again confirmed. Because these were all ex parte requests, Hynix had no right to
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participate in the proceedings after the requests were made, and had no right of appeal. 114. In the Notice of Intent to Issue Reexamination Certificate in the third of these

reexaminations of the ’105 patent, serial number 90/010,975 (Exhibit 40), the examiner agreed that Bennett received an external clock and generated two internal clocks (page 4), but determined (1) that Inagaki would not be combined with Bennett, on the ground that it would render Bennett inoperable for its intended purpose (id., page 7) and that (2) Bennett would have to be modified to work with Lofgren to output data in accordance with the first and second internal clocks (id., page 10) or that Bazes would be usable in the Bennett system (id. Page 12-13). These determinations were rejected by the BPAI in its decision regarding the ’446 patent. (Exhibit 21, pages 18-20 and 27-29) 115. Claims 24 and 33 of the ’918 patent were confirmed by the examiner in the course

of ex parte reexamination 90/010,420, requested by Hynix, based on various prior art references and combinations of references, including iAPX. Since this was an ex parte reexamination, Hynix had no right to appeal the confirmation of these claims. However, ’918 claim 18 (from which both claims 24 and 33 depend) was rejected as anticipated by iAPX; this rejection was appealed (by Rambus) and was affirmed by both the BPAI and the Federal Circuit. 116. In this ex parte ’918 reexamination, Hynix contended (among other issues) that

claim 33 would have been obvious over the combination of iAPX and either Lofgren or Bazes; and that claims 24 and 33 were invalid over Bennett (claim 24) or Bennett in combination with either Lofgren or Bazes. The examiner rejected these claims in a Final Rejection issued December 11, 2009 (Exhibit 41, page 1 and 90), but, after a personal interview with Rambus representatives, withdrew his rejections of claims 24 and 33 (but not claim 18). (Exhibit 42, Advisory Acton of March 26, 2010, page 2) 117. The examiner withdrew the rejections based on Bennett since the register contents

and the requests/responses were communicated on different buses (VM vs. versatile) from different processors (maintenance processor vs. regular master/processor). (Exhibit 42, pages 2829) As discussed above, particularly in paragraphs 45-47, in my opinion, this was not correct. Lofgren was withdrawn on the ground that, while Lofgren disclosed generating precise delays of
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sending data to memories, it did not disclose generating an internal clock for outputting data. (Id., pages 32-33) Regarding Bazes, the examiner stated: The Examiner maintains that it would have been obvious to include a delay locked loop circuit into memory module of iAPX Manual, however, the combination does not show whether data will be output from the memory module with respect to the generated internal clock signal. Id., page 36. These determinations have been effectively reversed by the BPAI in its decisions regarding the ’184 patent (Exhibit 16, page 31) and the ’446 patent (Exhibit 31, pages 26-29). 118. Hynix requested ex parte reexamination serial number 90/010,993, of ’020 claims

31 and 32 based on Bennett in combination with Inagaki. Reexamination was ordered, but the examiner found that “one of ordinary skill would not have used the teachings of Inagaki in the system of Bennett” (Exhibit 43, page 7) and confirmed both claims. The basis of the examiner confirmation has now been reversed by the BPAI in its decision of September 27, 2012, regarding the ’446 patent (Exhibit 21, page 16). 119. Hynix also requested an ex parte reexamination, serial number 90/010,924, of ’916

claims 9 and 40 based on Bennett in combination with a number of secondary prior art references, including Lofgren and Bazes to show the DLL recited by claim 40 and different references than previously submitted by Micron to show the precharge information recited in claim 9. The request was denied on the ground that Bennett did not disclose “receiving ‘a value that is representative of an amount of time to transpire’ after which the memory device responds to a first operation code” (as recited in claim 1, on which claim 9 depends) or “a register which stores ‘a value that is representative of an amount of time to transpire’ after which the memory device outputs the first amount of data” (as recited in claim 26, from which claim 40 depends). (Exhibit 44, pages 13 and 15) Hynix had no right to appeal. However, in connection with Micron’s inter partes reexamination of other claims of the ’916 patent, the BPAI held that the examiner was incorrect on this issue. (Exhibit 14, page 22) /// /// ///
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