Freescale Semiconductor Application Note

AN2865 Rev. 4, 04/2010

Qorivva Simple Cookbook
“Hello World” Programs to Exercise Common Features on MPC5500 & MPC5600 Microcontrollers
by: Steve Mihalik Field Applications

This application note contains software examples to use when getting started using MPC5500 and MPC5600 family devices. Complete code is available for downloading to target such as an evaluation board.
Table 1. MPC5500 & MPC5600 Family Definitions for this Application Note
Family Name MPC551x MPC555x Devices Included MPC5514, MPC5515, MPC5516, MPC5517 MPC5533, MPC5534, MPC5553, MPC5554, MPC5561, MPC5565, MPC5566, MPC5567, MPC5632M, MPC5633M, MPC5634M

Contents
1 Time Base: Time Measurement . . . . . . . . . . . . . . . . . . . 5 2 Interrupts: Decrementer. . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Interrupts: Fixed-Interval Timer . . . . . . . . . . . . . . . . . . . 14 4 INTC: Software Vector Mode. . . . . . . . . . . . . . . . . . . . . 22 5 INTC: Hardware Vector Mode . . . . . . . . . . . . . . . . . . . . 35 6 INTC: Software Vector Mode, VLE Instructions . . . . . . 48 7 INTC: Hardware Vector Mode, VLE Instructions . . . . . . 66 8 MMU: Create TLB Entry . . . . . . . . . . . . . . . . . . . . . . . . 84 9 Cache: Cache as RAM . . . . . . . . . . . . . . . . . . . . . . . . . 87 10 PLL: Initializing System Clock (MPC551x, MPC55xx). . 91 11 PLL: Initializing System Clock (MPC56xxB/P/S) . . . . . . 98 12 FMPLL: Frequency Modulation . . . . . . . . . . . . . . . . . . 107 13 Modes: Low Power (MPC56xxB/S) . . . . . . . . . . . . . . . 110 14 eDMA: Block Move . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 15 eSCI: Simple Transmit and Receive . . . . . . . . . . . . . . 130 16 eSCI: LIN Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 17 LINFlex: LIN Transmit . . . . . . . . . . . . . . . . . . . . . . . . . 139 18 eMIOS: Modulus Counter, OPWM Functions . . . . . . . 147 19 eMIOS: PEC, OPWFM Functions . . . . . . . . . . . . . . . . 156 20 eTPU: Set 1 PWM Function . . . . . . . . . . . . . . . . . . . . 162 21 eQADC: Single Software Scan . . . . . . . . . . . . . . . . . . 168 22 ADC: Software Trigger, Continuous Scan . . . . . . . . . . 171 23 ADC - CTU: eMIOS Trigger (MPC560xB) . . . . . . . . . . 178 24 DSPI: SPI to SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 25 FlexCAN Transmit and Receive . . . . . . . . . . . . . . . . . 201 26 Flash: Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Appendix AInterrupt Alignment Summary . . . . . . . . . . . . . . 229 Appendix BSingle Core Build Files . . . . . . . . . . . . . . . . . . . 230 Appendix CMPC56xxB/P/S Peripheral Clocks . . . . . . . . . . 246

MPC56xxB/P/S MPC5602B or C, MPC5603B, MPC5604 B or C, MPC5604P, MPC5602S, MPC5604S, MPC5606S

The family definitions in Table 1 are used to categorize the different devices discussed in this document. Examples included here will illustrate any differences between families, and between the different members in a family.

© Freescale Semiconductor, Inc., 2005–2010. All rights reserved.

Source code, necessary build files, and debugger scripts are available for all examples. Example code provides two executable outputs: one that locates the program in internal flash, and another that locates the program in internal RAM. For RAM-based programs, debugger scripts are provided to initialize the MMU, initialize SRAM, and set the instruction pointer to the beginning of main code. For flash-based programs: • The MMU is initialized by Boot Assist Module (BAM) code that generally executes after reset. • SRAM is initialized by added code to a modified startup (“crt0”) file. • The instruction pointer (as well as some reset configuration settings) is defined by the Reset Configuration Half Word (RCHW) in the boot section of the startup file for flash. NOTE For EVBs with 40 MHz Crystal: MPC5561 and MPC5567 EVBs use 40 MHz crystals instead of the usual 8 MHz crystal. In this case, the default frequency will be 30 MHz instead of 12 MHz. Examples that alter the PLL frequency will need software modification for proper operation using a 40 MHz crystal. (For more information, see Section 10.2.2, “MPC555x,” part of Section 8.2, “Design,” in Section 8, “PLL: Initializing System Clock,” for code changes when using 40 MHz crystal.)

Qorivva Simple Cookbook, Rev. 4 2 Freescale Semiconductor

Table 2. Devices and Applicable Examples
MPC551x Devices Example MPC5514, MPC5515, MPC5516, MPC5517 MPC555x Devices MPC56xxBPS Devices

MPC5533, MPC5553 MPC5632M, MPC560xB, MPC5534 MPC5554, MPC5633M, MPC560xP, MPC5561, MPC5634M MPC560xS MPC5565, MPC5566, MPC5567 x x x x x x x x x x x x x x x x x x x x x x x

1 2 3 4 5 6 7 8 9

Time Base: Time Measurement Interrupts: Decrementer Interrupts: Fixed-Interval Timer INTC: Software Vector Mode INTC: Hardware Vector Mode INTC: Software Vector Mode, VLE INTC: Hardware Vector Mode, VLE MMU: Create TLB Entry Cache: Cache as RAM

x x x x x x x x

10 PLL: Initializing System Clock 11 PLL: Initializing System Clock 12 FMPLL: Frequency Modulation 13 Modes: Low Power 14 eDMA: Block Move 15 eSCI: SImple Transmit & Receive 16 eSCI: LIN 17 LINFlex: LIN Transmit 18 eMIOS: Modulus Counter, OPWM 19 eMIOS: PEC, OPWFM 20 eTPU: Set 1 PWM Function 21 eQADC: Single Software Scan 22 ADC: SW Trigger, Cont Scan 23 ADC-CTU: eMIOS Trigger 24 DSPI: SPI to SPI 25 FlexCAN: Transmit and Receive 26 Flash: Configuration

x

x

x

x x

x x x x x x x x x x x x x x x x x x x x x x x (except MPC5561) x x x x MPC560xB x x x x x x x x x x x x x x x x x (except MPC56xxP) x

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 3

Revision History Revision 2 (Earlier revisions not tracked) Revision 3 Minor text changes in various examples, plus code modifications for example 2, “Interrupts: Decrementer,” and example 19, “Flash: Configuration.” • Added 3 new examples: PLL: System Clock (MPC56xxB/P/S), INTC: SW Vector Mode, VLE Instructions, INTC: HW Vector Mode, VLE Instructions • Expanded and updated Flash: Configuration • Updated 5 other examples to support MPC560xB, MPC560xP, MPC560xS (“MPC56xxB/P/S”) • Revised FlexCAN example • Minor text changes in other examples • Added 4 new examples: Modes: Low Power LINFlex: LIN Transmit ADC: Software trigger, Continuous Scan CTU: eMIOS Trigger • Updated other MPC56xxB/P/S examples • Minor text changes in other examples The revision number was not incremented because no substantive changes were made to the content. • Front page: Add SafeAssure branding. • Title and first page: Add Qorivva branding. • Back page: Apply new back page format. 11/2008

07/2009

Revision 4

04/2010

04/2012

Qorivva Simple Cookbook, Rev. 4 4 Freescale Semiconductor

1 Time Base: Time Measurement Description Task: Using the Time Base (TB). It is enabled by setting the Time Base Enable (TBE) bit in the Hardware Implementation Register 0 (spr HID0). 4 Freescale Semiconductor 5 . If sysclk = 12 MHz (the default for MPC555x devices with an 8 MHz crystal). and move their values to spr SPRG0 and spr SPRG1. This program demonstrates how to manage special purpose registers (spr’s). Qorivva Simple Cookbook. it would take about six minutes for TBL to overflow to TBU. Examine these registers and calculate the time difference. and are read or written using a general purpose register (gpr). Only two instructions are used with spr’s: move to spr (mtspr) and move from spr (mfspr). after some initial delay due to pipelining. NOTE Debuggers may or may not stop the time base when code is not running. Special purpose registers are not memory-mapped. Put the result into a register. The 64-bit Time Base consists of two 32-bit special purpose registers: TBL for the lower 32 bits and TBU for the upper 32 bits. such as at a breakpoint. Rev.1 1. measure the number of system clocks to execute a section of code in any type of memory. MPC5500 Time Base Crystal 8 MHz Clocks and PLL sysclk spr TBU spr TBL Enable spr HID0 TBE Figure 1. At the end of the measured code. When enabled it counts at system clock frequency. record both again and move their values to spr SPRG2 and spr SPRG3. MPC551x devices have a default frequency of 16 MHz. Time Base Example Exercise: Modify the program to record the TBL and TBU at the start of the desired code sequence.

r5 r5 # Load immediate data of 0 to r4 # Move r4 to TBU # Move r4 to TBL # Move from spr HID0 to r5 # Load immediate data of 0x4000 to r4 # OR r4 (0x4000 0000) with r4 (HID0 value) # Move result to HID0 2 Enable Time Base: set HID0[TBE]=1 3 Execute some code 4 Record TBL 1. r4. Rev. 0x4000 r5.3 li mttbu mttbl Code r4. 0 r4 r4 r5 r4.1. r5 r5 # # # # # # # # # # INITIALIZE TIME BASE=0 Load immediate data of 0 to r4 Move r4 to TBU Move r4 to TBL ENABLE TIME BASE Move from spr HID0 to r5 (copies HID0) Load immed. r4. 4 6 Freescale Semiconductor . Time Base: Time Measurement Step 1 Initialize Time Base = 0 li mttbu mttbl mfhid0 li or mthid0 nop nop nop nop nop mftbl r5 # Move TBL to r5 to store TBL value Code r4. 0x4000 r5.2 Design Table 3. data of 0x4000 to r4 OR r4 (0x0000 4000) with r5 (HID0 value) Move result to HID0 EXECUTE SOME CODE mfhid0 li or mthid0 nop nop nop nop nop mftbl r5 # RECORD TBL # Move TBL to r5 to store TBL value Qorivva Simple Cookbook. 0 r4 r4 r5 r4.

toggles a GPIO output. Exercise: Connect the output to an LED on an MPC55xx evaluation board or oscilloscope. 144 QFP 22 176 QFP 30 208 BGA L1 Function Name GPIO[114] SIU PCR No.2 2. MPC5500 Decrementer Automatic Reload (spr DECAR) Crystal 8 MHz Clocks and PLL Default sysclk: 16 MHz (MPC551x) 12 MHz (MPC555x) 8 MHz (MPC563x) spr HID0 Decrementer (spr DEC) Enable GPIO TBE DEC interrupt request to CPU core caused by the Decrementer passing through zero Figure 2.1 Interrupts: Decrementer Description Task: Use the Decrementer (DEC) exception to generate a periodic interrupt roughly every second. 114 Package Pin No. to be written entirely in assembler without enabling nested interrupts. 4 Freescale Semiconductor 7 .5  8 MHz crystal). Design the interrupt handler. including interrupt service routine (ISR). change the Decrementer timeout to 1 kHz. 496 BGA M5 416 BGA N3 324 BGA L3 208 BGA N3 144 QFP 52 EVB xPC 563M PJ9–1 Signal GPIO PH2 Qorivva Simple Cookbook. After verifying proper operation. Signals for Decrementer Example MPC551x Family Pin Name SIU PCR No. Decrementer Example Table 4. The ISR simply counts the number of Decrementer interrupts. Rev. and clears the Decrementer interrupt flag. Assume the system clock runs at the default frequency of 16 MHz for MPC551x (16 MHz Internal Reference Clock) or 12 MHz for MPC555x (1. 114 MPC555x Family Package Pin No.

s file IVOR Branch Table b IVOR0trap b IVOR1trap . Rev. which is 16 bytes times the IVOR number...2. b IVOR10Handler . MPC551x Program Flow For MPC555x. The MPC555x program flow is shown below.. MPC555x Program Flow Qorivva Simple Cookbook. the DEC interrupt causes the CPU to vector to the sum of the common Interrupt Vector Prefix (IVPR0:15) plus the interrupt’s individual Interrupt Vector Offset (IVOR1016:27).s file IVOR10Handler: prologue (save registers) execute DecISR (increment ctr. the DEC interrupt causes the CPU to vector to the sum of the common Interrupt Vector Prefix (IVPR0:19) plus a fixed offset for each interrupt.2 Design For MPC551x. IVOR10 init Decrementer init GPIO enable interrupts wait forever } Decrementer interrupt taken vector to IVPR0:15 + IVOR1016:27 handlers. toggle pin. The MPC551x program flow is shown below.c file main { init IVPR.s file IVOR10Handler: prologue (save registers) execute DecISR (increment ctr. handlers. followed by design steps and a stack frame implementation. main. return) Figure 3. clear flag) epilogue (restore registers. clear flag) epilogue (restore registers. 4 8 Freescale Semiconductor . main.c file main { init IVPR init Decrementer init GPIO enable interrupts wait forever } Decrementer interrupt taken vector to IVPR0:19 + (10 16) bytes ivor_branch_table. toggle pin. return) Figure 4..

enabled by MSR[EE]. only the registers that are used will need to be saved in the stack. Stack Frame for Decrementer Interrupt (16 bytes) Stack Frame Area 32-bit GPRs r4 r3 LR area back chain LR placeholder r1 (which is sp) Register Location in Stack sp + 0x0C sp + 0x08 sp + 0x04 sp Qorivva Simple Cookbook. Enable decrementer interrupt. (MPC551x note: Each core has its own spr IVPR. 4 Freescale Semiconductor 9 . IBE = 1 Enable external interrupts by setting MSR[EE] = 1. Initialization Steps Step Global variable Counter for decrementer initIrqVectors Load the common interrupt prefix to IVPR. (Enables requests from INTC. DIE = 1 Enable decrementer automatic reload on timeout. so SRR0:1 need not be saved in the stack frame. Load decrementer automatic reload value of 12M.) wait forever enableExtIrq wrteei 1 waitloop while 1 Because the program’s interrupt handler is entirely in assembler. are not re-enabled in the interrupt handler.75 sec timeout for 16 MHz sysclk. ARE = 1 Start DEC (and Time Base) counting. PA = 0 (default) Output buffer is enabled. initGPIO TBEN = 1 Relevant Bit Fields Pseudo Code MPC551x MPC555x int DECctr = 0 spr IVPR = __IVPR_VALUE – spr IVOR10 = IVOR10Handler@l spr DEC = 0x00B7 1B00 spr DECAR = 0x00B7 1B00 spr TCR = 0x0000 0440 spr HID0 = 0x0000 4000 SIU_PCR[114] = 0x0303 Initialize GPIO as output: Pad assignment is GPIO (default). External input interrupts. Rev. and 0. FIT to be recognized if enabled and pending. DEC. This provides 1 sec timeout for 12 MHz sysclk. Table 6. so only these two registers are saved and restored in the prologue and epilogue. besides the stack pointer (r1). OBE = 1 Input buffer is also enabled (allows monitoring pad).) initDEC Load initial DEC value of 12M = 0xB71B00. Prefix value is defined in the link file. Two registers are used in the interrupt service routine. MPC555x: Initialize decrementer interrupt offset to the lower half of IVOR10 handler’s address.Table 5.

4 10 Freescale Semiconductor . sp. –0x10 (sp) store required registers DECctr++ SIU_GPDO[114] = SIU_GPDI[114]++ spr TSR = 0x0800 0000 restore registers addi sp.Table 7. IVOR10 (Decrementer) Interrupt Handler Steps (MPC555x: Must be 16 byte aligned and within 64KB of address in IVPR.) Step prolog Create stack frame Save registers in stack frame DecISR Increment DECctr Toggle GPIO Clear decrementer interrupt flag epilog Restore registers from stack frame Restore stack frame space Return DIS = 1 Relevant Bit Fields Pseudo Code (MPC551x & MPC555x) stwu sp. MPC551x does not require alignment because it is the destination of a branch instruction. 0x50 rfi Qorivva Simple Cookbook. Rev.

FIT) */ Loop forever */ Qorivva Simple Cookbook. SIU. must be done by debug scripts or BAM */ 2. 2007 All Rights Reserved */ Rev 1. r0. pin for GPIO output that can be read as input */ Enable external interrupts (INTC.2. initDEC(). and are not used for MPC551x*/ li r0. 0x4000 mthid0 r0 } void main (void) { volatile uint32_t i=0. DEC.R.R. MMU not initialized.h */ extern IVOR10Handler(). 4 Freescale Semiconductor 11 .h or mpc5554.Made variable i volatile */ Rev 1. changed GPIO pin */ and for MPC551x removed code to load spr IVOR10 */ Notes: */ 1. /* Interrupt Vector Prefix value from link file */ uint32_t DECctr = 0. Copyright Freescale.0 April 19. } } /* Load initial DEC value of 12M (0x00B7 1B00) */ /* Load same initial value to DECAR */ /* Enable DEC interrupt and auto-reload*/ /* Enable Time Base and Decrementer (set TBEN) */ /* /* /* /* /* /* Dummy idle counter */ Initialize interrupt vectors registers*/ Initialize Decrementer routine */ Init. 0x1B00 mtdec r0 mtdecar r0 lis r0. SRAM not initialized. addr.Changed GPIO205 to GPIO195 for use in 324.Passed spr IVPR value from link file. /* GPDO[114] reg.R = 0x0303. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r0. /* Counter for Decrementer interrupts */ vuint32_t GPDI_114_ADDR = (vuint32_t)&SIU.c file main.__IVPR_VALUE@l /* Note: IVPR lower bits are unused in MPC555x*/ mtivpr r0 /* The following two lines are required for MPC555x.c . extern uint32_t __IVPR_VALUE.Decrementer interrupt example */ Rev 1. */ asm void initIrqVectors(void) { lis r0. while (1) { i++.Mihalik.GPDI[114]. 2004 S. Rev.1 May 15 2006 SM.3 Jun 13 2007 SM.3 2. 0x00B7 ori r0.PCR[114]. */ vuint32_t GPDO_114_ADDR = (vuint32_t)&SIU. initIrqVectors(). must be done by debug scripts or in a crt0 type file */ #include "mpc563m. 208 packages */ Rev 1.3. /* GPDI[114] reg.1 /* /* /* /* /* /* /* /* /* Code main. 0x0440 mttcr r0 li r0. addr.h" /* Use proper include file such as mpc5510.GPDO[114]. asm (" wrteei 1"). IVOR10Handler@l /* IVOR10(Dec) = lower half of handler address */ mtivor10 r0 } asm void initDEC(void) { lis r0. r0.2 Aug 12 2006 SM.

or 16 bytes) # ************* ______________ # 0x0C * r4 * |GPR Save Area # 0x08 * r3 * ___|__________ # 0x04 * resvd. GPDI_114_ADDR@l(r3) r4.section .s .. 2007. 0x08 (r1) r4.2: Jun 13.align 16 # PROLOGUE # Create stack frame and store back chain # Counter of Decrementer interrupts taken # GPDI[114] register address # GPDO[114] register address IVOR10Handler: r1.globl IVOR10Handler . All rights reserved # STACK FRAME DESIGN: Depth: 4 words (0x10.M.LR * Reserved for calling function # 0x00 * SP(GPR1) * Backchain (same as gpr1 in GPRs) # ************* . 0 (r3) # Output toggled GPIO 114 pin state to reg. DECctr@ha DECctr@l (r3) r4.Used r4 instead of r0 to clear DIS flag in spr TSR# Copyright Freescale Semiconductor.Use GPIO[195] instead of GPIO[205] # Rev 1. 2006 S. Added . 1 # Add one to state for toggle effect r3. Inc.section . r1. 0x10 # Write "1" clear Dec Interrupt Status (DIS) flag # DIS flag is in spr TSR (spr 336) # EPILOGUE # Restore gprs # Restore space on stack # End of Interrupt Qorivva Simple Cookbook. 4 12 Freescale Semiconductor . Diab(default) use . 2007 S. GPDO_114_ADDR@ha # Get pointer to memory containing GPDO[114] address r3.2.extern DECctr . # Rev 1. 0 (r3) # Read pin input state from register GPDI[114] r4. 0x08 (r1) r1.2 handler.ivor_handlers # # . Rev. 0x0C (r1) r3. 0x1 DECctr@l (r3) # Read DECctr # Increment DECctr # Write back new DECctr r3. S Mihalik.M.1: May 15. r4.3 Nov 1 2008 SM . r4. r4. GPDO[114] r4.align 16 prolog: stwu stw stw DECisr: lis lwz addi stw lis lwz lbz addi lis lwz stb lis mtspr epilog: lwz lwz addi rfi # Align IVOR handlers on a 16 byte boundary for MPC555x # GHS. -0x10 (r1) r3. GPDO_114_ADDR@l(r3) r4. Cygnus. r4.s file # handlers.3.extern GPDO_114_ADDR . 2004.ivor_handlers for linking # and changed GPIO address to global variable # Rev 1.Decrementer (IVOR10) interrupt example # Rev 1.align 4 . 0x0800 336. r4 r4. 0x0C (r1) r3. GPDI_114_ADDR@ha # Get pointer to memory containing GPDI[114] address r3.extern GPDI_114_ADDR .align 4 # CodeWarrior requires .0: Sept 2.

equ SIXTEEN_BYTES.3.align SIXTEEN_BYTES IVOR13trap: b IVOR13trap # IVOR 13 interrupt handler . Rev.align SIXTEEN_BYTES IVOR8trap: b IVOR8trap # IVOR 8 interrupt handler .s file (MPC551x only) ivor_branch_table. 16 # 16 byte alignment required for table entries # Diab compiler uses value of 4 (2**4=16) # CodeWarrior. All Rights Reserved Rev 1.2.Made IVOR10Handler extern . 4 Freescale Semiconductor 13 .align SIXTEEN_BYTES IVOR2trap: b IVOR2trap # IVOR 2 interrupt handler .3 # # # # # ivor_branch_table.section .align SIXTEEN_BYTES IVOR12trap: b IVOR12trap # IVOR 12 interrupt handler .for use with MPC551x only Description: Branch table for 16 MPC551x core interrupts Copyright Freescale 2007.align SIXTEEN_BYTES IVOR5trap: b IVOR5trap # IVOR 5 interrupt handler .ivor_branch_table .align SIXTEEN_BYTES IVOR4trap: b IVOR4trap # IVOR 4 interrupt handler .align SIXTEEN_BYTES IVOR9trap: b IVOR9trap # IVOR 9 interrupt handler . Cygnus use 16 .align SIXTEEN_BYTES IVOR14trap: b IVOR14trap # IVOR 14 interrupt handler .0 Jul 6 2007 S Mihalik .1 Aug 30 2007 SM .align SIXTEEN_BYTES b IVOR0trap # IVOR 0 interrupt handler .align SIXTEEN_BYTES IVOR11trap: b IVOR11trap # IVOR 11 interrupt handler .align SIXTEEN_BYTES IVOR1trap: b IVOR1trap # IVOR 1 interrupt handler .s .extern IVOR10Handler .Initial version Rev 1.align SIXTEEN_BYTES IVOR3trap: b IVOR3trap # IVOR 3 interrupt handler .align SIXTEEN_BYTES b IVOR10Handler # IVOR 10 interrupt handler (Decrementer) .align SIXTEEN_BYTES IVOR7trap: b IVOR7trap # IVOR 7 interrupt handler . GHS.align SIXTEEN_BYTES IVOR6trap: b IVOR6trap # IVOR 6 interrupt handler .align SIXTEEN_BYTES IVOR15trap: b IVOR15trap # IVOR15 interrupt handler IVOR0trap: Qorivva Simple Cookbook.

Exercise: Connect the GPIO to an LED on an MPC55xx evaluation board or oscilloscope.1 Interrupts: Fixed-Interval Timer Description Task: Use the Fixed-Interval Timer (FIT) exception to generate a periodic interrupt roughly every second. The interrupt handler will not enable nested interrupts. The FIT’s ISR simply counts interrupts and toggles a GPIO output. MPC5500 Default sysclk: 16 MHz (MPC551x) 12 MHz (MPC555x) 8 MHz (MPC563x) spr HID0 Crystal 8 MHz Clocks and PLL spr TBU Enable TBE spr TBL GPIO FIT interrupt request to CPU core caused by zero to one transition of selected Time Base bit Figure 5. Design the FIT’s interrupt handler to allow the interrupt service routine (ISR) to be written in C. and start up file are the same as for the Decrementer example except for the output file names. Signals for Fixed-Interrupt Example MPC551x Family Pin Name SIU PCR No. change the FIT timeout rate to about 4 Hz. 114 Package Pin No. The link files. Rev. which is 16 MHz for an MPC551x and 12 MHz for an MPC555x with an 8 MHz crystal. Fixed-Interval Interrupt Example Table 8. 4 14 Freescale Semiconductor . Assume the system clock runs at the default frequency. 144 QFP 22 176 QFP 30 208 BGA L1 Function Name GPIO[114] SIU PCR No. After verifying proper operation. 114 MPC555x Family Package Pin No.3 3. make file. 496 BGA M5 416 BGA N3 324 BGA L3 208 BGA N3 EVB xPC 563M PJ9–1 Signal GPIO PH2 Qorivva Simple Cookbook.

toggle pin.. return) main { init IVPR init Fixed Interval Timer init GPIO enable interrupts wait forever } FitISR { increment counter toggle pin clear FIT interrupt flag } Figure 6.c file Fixed Interval Timer interrupt taken vector to IVPR0:19 + (11  16) bytes ivor_branch_table. This n = 22 corresponds to TBL bit 31 – n = TBL bit 9. clear flag) epilogue (restore registers. The MPC551x program flow is shown below. MPC551x Program Flow For MPC555x.7 second timeout. we find when n=22.. followed by design steps and a stack frame implementation. Rev. As the Time Base continues to increment. there is about a 0. return) main { init IVPR.s file IVOR11Handler: prologue (save registers) branch to FitISR (increment ctr. For MPC551x. toggle pin. Therefore for Time Base bit n (n is counted from the least significant bit of TBL). IVOR11 init Fixed Interval Timer init GPIO enable interrupts wait forever } FitISR { increment counter toggle pin clear FIT interrupt flag } Figure 7. The MPC555x program flow is shown below.3. 1 second = 2  2n  83 1/3 ns.s file IVOR Branch Table b IVOR0trap b IVOR1trap . main. b IVOR11Handler . the DEC interrupt causes the CPU to vector to the sum of the common Interrupt Vector Prefix (IVPR0:15) plus the interrupt’s individual Interrupt Vector Offset (IVOR1116:27). clear flag) epilogue (restore registers.s file IVOR11Handler: prologue (save registers) branch to FitISR (increment ctr. the timeout period is: 2  2n  sysclock periods. the FIT interrupt causes the CPU to vector to the sum of the common Interrupt Vector Prefix (IVPR0:19) plus a fixed offset for each interrupt. the selected Time Base bit must transition from 0 to 1. which is 16 bytes times the IVOR number. Solving for integer n. 4 Freescale Semiconductor 15 . main.2 Design For a FIT timeout to occur. For one second timeout using a 12 MHz sysclk.. MPC555x Program Flow Qorivva Simple Cookbook. handlers.c file Fixed Interval Timer interrupt taken vector to IVPR0:15 + IVOR1116:27 handlers. the bit will transition back to 0 then to 1 again before the next timeout..

are not re-enabled in the interrupt handler. (MPC551x note: Each core has its own spr IVPR. Qorivva Simple Cookbook. enabled by MSR[EE].7 sec (12 MHz sysclk): use TBLb bit 9 • Enable FIT interrupt Initialize Time Base = 0 Start Time Base (and Decrementer) counting initGPIO Initialize GPIO as output: Pad assignment is GPIO (default) Output buffer is enabled Input buffer is also enabled (allows monitoring pad) Enable external interrupts by setting MSR[EE] = 1 (Enables requests from INTC. Initialization Steps Pseudo Code Step Global variable initIrqVectors Counter for Fixed Interval Timer Load the common interrupt prefix to IVPR. It is assumed SPE instructions are not used in this example. 1.Table 9. FP = 1 FIE = 1 Relevant Bit Fields MPC551x MPC555x int FITctr = 0 spr IVPR = __IVPR_VALUE – spr IVOR11 = IVOR11Handler@l spr TCR = 0x0181 4000 spr TBL = spr TBU = 0 spr HID0 = 0x0000 4000 SIU_PCR[114] = 0x0303 enableExtIrq waitloop while 1 The ISR will be written in C. FIT to be recognized if enabled and pending) wait forever TBEN = 1 PA = 0 (default) OBE = 1 IBE = 1 wrteei 1 FPEXT= 0xA.) initFIT Initialize Timer ControlB • FIT Timeout = 0. DEC. MPC555x: Initialize decrementer interrupt offset to the lower half of IVOR11 handler’s address.1 External input interrupts. Prefix value is defined in the link file. Rev. so SRR0:1 need not be saved in the stack frame. 4 16 Freescale Semiconductor . The SPE’s accumulator is not saved in the MPC555x prologue. namely the volatile registers as defined in the e500 ABI. so the handler’s prologue will save all the registers the compiler might use.

sp. Interrupt Handler (IVOR11Handler): Fixed-Interval Timer (MPC555x: Must be 16-byte aligned and within 64 KB of address in IVPR. 4 Freescale Semiconductor 17 . –0x50 (sp) store required registers FITctr++ SIU_GPDO[114] = ~SIU_GPDI[114] spr TSR = 0x0400 0000 restore registers addi sp. Stack Frame for FIT Interrupt Handler (80 bytes) Stack Frame Area 32-bit GPRs r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r0 CR locals and padding CR XER CTR LR padding padding padding LR area back chain LR placeholder r1 (which is sp) Register Location in Stack sp + 0x4C sp + 0x48 sp + 0x44 sp + 0x40 sp + 0x3C sp + 0x38 sp + 0x34 sp + 0x30 sp + 0x2C sp + 0x28 sp + 0x24 sp + 0x20 sp + 0x1C sp + 0x18 sp + 0x14 sp + 0x10 sp + 0x0C sp + 0x08 sp + 0x04 sp Table 11.Table 10. Rev. MPC551x does not require alignment because it is the destination of a branch instruction. 0x50 rfi Qorivva Simple Cookbook.) Step prolog Create stack frame Save registers in stack frame FitISR Increment FITctr Toggle GPIO114 Clear FIT interrupt status flag epilog Restore registers from stack frame Restore stack frame space Return FIS = 1 Relevant Bit Fields Pseudo Code (MPC551x & MPC555x) stwu sp.

GPDI[114]. and are not used for MPC551x */ li r0. Copyright Freescale. 0 mttbu r0 mttbl r0 lis r0. must be done by debug scripts or BAM */ 2.4 Jun 18 2007 SM . initFIT().1 /* /* /* /* /* /* /* /* /* /* Code main.Mihalik.3 Aug 12 2006 SM . IVOR11Handler@l /* IVOR11 = lower half of handler address */ mtivor11 r0 } asm void initFIT(void) { li r0. DEC. FIT) */ Loop forever */ } asm void ClrFitFlag(void) { lis r0. 2004 All Rights Reserved */ Rev 1.h" /* Use proper include file such as mpc5510.R = ~SIU. extern uint32_t __IVPR_VALUE. while (1) { i++. */ Enable external interrupts (INTC.2 May 15 2006 SM. must be done by debug scripts or in crt0 type file */ /* Needed for MPC555x only */ /* Interrupt Vector Prefix value from link file */ /* Counter for Fixed Interval Timer interrupts */ #include "mpc563m.1 Sept 1. } /* Dummy idle counter */ /* /* /* /* /* Initialize interrupt vectors registers*/ Initialize FIT routine */ Initialize GPIO as output. Rev. changed GPIO pin */ and f0r MPC551x removed code to load spr IVOR11 */ Notes: */ 1. /* Toggle GPIO output */ ClrFitFlag().h */ extern IVOR11Handler(). 0x4000 mthid0 r0 } /* Initialize time base to 0 */ /* Enable FIT interrupt and set*/ /* FP=0.simplfied. r0.7 sec timeout */ /* Enable Time Base and Decrementer (set TBEN) */ void main (void) { volatile uint32_t i = 0. 4 18 Freescale Semiconductor .c . __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r0. FPEXT=A for 0.h or mpc5554. SRAM not initialized. 2004 S.GPDO[114]. asm (" wrteei 1").Passed spr IVPR value from link file.c file main. MMU not initialized.3. 2004 SM . /* Increment interrupt counter */ SIU.3. SIU. 0x0400 mttsr r0 /* Write "1" clear FIT Interrupt Status flag */ } void FitISR(void) { FITctr++. syntax changes */ Rev 1. asm void initIrqVectors(void) { lis r0. 0x0181 ori r0.0 April 19. uint32_t FITctr = 0. 0x4000 mttcr r0 li r0.Changed variable i to volatile */ Rev 1.Fixed Interval Timer interrupt example */ Rev 1. /* Clear FIT's flag */ } Qorivva Simple Cookbook.R. r0. __IVPR_VALUE@l /* Note: IVPR lower bits are unused in MPC555x */ mtivpr r0 /* The following two lines are required for MPC555x.Changed GPIO205 to GPIO195 for use in 324. 208 packages */ Rev 1. initIrqVectors().3 3.PCR[114].R= 0x0303.

section .2: Aug 23 2007 DF: Made FitISR .3.align 4.3. 0x44 r9.file handlers. 0x2C r3. but return here Qorivva Simple Cookbook. 2007.align 16 prolog: stwu stw stw stw stw stw stw stw stw stw stw stw mfCR stw mfXER stw mfCTR stw mfLR stw bl r1. 2004. 0x48 r10. S Mihalik. Rev 1. 2007 SM Added . 0x38 r6. Diab(default) use . 0x18 r0 r0.section . or 80 bytes) # ************* ______________ # 0x4C * GPR12 * ^ # 0x48 * GPR11 * | # 0x44 * GPR10 * | # 0x40 * GPR9 * | # 0x3C * GPR8 * | # 0x38 * GPR7 * GPRs (32 bit) # 0x34 * GPR6 * | # 0x30 * GPR5 * | # 0x2C * GPR4 * | # 0x28 * GPR3 * | # 0x24 * GPR0 * ___v__________ # 0x20 * CR * __CR__________ # 0x1C * XER * ^ # 0x18 * CTR * | # 0x14 * LR * locals & padding for 16 B alignment # 0x10 * padding * | # 0x0C * padding * | # 0x08 * padding * ___v__________ # 0x04 * resvd. All rights reserved # STACK FRAME DESIGN: Depth: 20 words (0xA0. 0x14 FitISR # Align IVOR handlers on a 16 byte (2**4) boundary # GHS. 4 Freescale Semiconductor 19 . 0x40 r8. Inc.LR * Reserved for calling function # 0x00 * SP * Backchain (same as gpr1 in GPRs) # ************* .0: April 9.align 16 # PROLOGUE (r1) # Create stack frame and store back chain (r1) # Store gprs (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) # Store CR (r1) # Store XER (r1) # Store CTR (r1) # Store LR (r1) # Execute FIT ISR.ivor_handlers . 0x1C r0 r0.extern Copyright Freescale Semiconductor. 0x34 r5.globl IVOR11Handler .FIT (IVOR11) interrupt example Rev 1.1: June 18.s . 0x30 r4. 0x3C r7. Rev. 0x20 r0 r0. Cygnus. 0x4C r11. 0x24 r0 r0. -0x50 r12.extern FitISR . CodeWarrior .2 # # # # # handlers.ivor_handlers for linking Rev 1. 0x28 r0.

r1. 0x38 (r1) r8.epilog: lwz mtLR lwz mtCTR lwz mtXER lwz mtcrf lwz lwz lwz lwz lwz lwz lwz lwz lwz lwz lwz addi rfi r0. 0x1C (r1) r0 r0. r0 r0. 0x14 (r1) r0 r0. 0x30 (r1) r6. 0x20 (r1) 0xff. 0x18 (r1) r0 r0. 0x24 (r1) r3. 0x40 (r1) r10. 4 20 Freescale Semiconductor . 0x28 (r1) r4. 0x50 # EPILOGUE # Restore LR # Restore CTR # Restore XER # Restore CR # Restore gprs # Restore space on stack # End of Interrupt Qorivva Simple Cookbook. 0x48 (r1) r12. 0x34 (r1) r7. 0x2C (r1) r5. Rev. 0x4C (r1) r1. 0x3C (r1) r9. 0x44 (r1) r11.

align SIXTEEN_BYTES IVOR9trap: b IVOR9trap # IVOR 9 interrupt handler .0 Jul 6 2007 S Mihalik .align SIXTEEN_BYTES IVOR4trap: b IVOR4trap # IVOR 4 interrupt handler .3.align SIXTEEN_BYTES IVOR5trap: b IVOR5trap # IVOR 5 interrupt handler .extern .equ SIXTEEN_BYTES. GHS.align SIXTEEN_BYTES IVOR3trap: b IVOR3trap # IVOR 3 interrupt handler .Initial version Rev 1.s file (MPC551x only) ivor_branch_table.align SIXTEEN_BYTES IVOR8trap: b IVOR8trap # IVOR 8 interrupt handler . Rev.Made IVOR11Handler . 16 # 16 byte alignment required for table entries # Diab compiler uses value of 4 (2**4=16) # CodeWarrior.3. 4 Freescale Semiconductor 21 .align SIXTEEN_BYTES IVOR6trap: b IVOR6trap # IVOR 6 interrupt handler .align SIXTEEN_BYTES IVOR2trap: b IVOR2trap # IVOR 2 interrupt handler .align SIXTEEN_BYTES IVOR12trap: b IVOR12trap # IVOR 12 interrupt handler .align SIXTEEN_BYTES IVOR10trap: b IVOR10trap # IVOR 10 interrupt handler .1 Aug 23 2007 DF .align SIXTEEN_BYTES IVOR14trap: b IVOR14trap # IVOR 14 interrupt handler .ivor_branch_table .align SIXTEEN_BYTES b IVOR11Handler # IVOR 11 interrupt handler (Fixed Interval Timer) .align SIXTEEN_BYTES IVOR13trap: b IVOR13trap # IVOR 13 interrupt handler .align SIXTEEN_BYTES IVOR15trap: b IVOR15trap # IVOR15 interrupt handler IVOR0trap: Qorivva Simple Cookbook.for use with MPC551x only Description: Branch table for 16 MPC551x core interrupts Copyright Freescale 2007.s .align SIXTEEN_BYTES IVOR7trap: b IVOR7trap # IVOR 7 interrupt handler . All Rights Reserved Rev 1. Cygnus use 16 .align SIXTEEN_BYTES b IVOR0trap # IVOR 0 interrupt handler .align SIXTEEN_BYTES IVOR1trap: b IVOR1trap # IVOR 1 interrupt handler .3 # # # # # ivor_branch_table.section .extern IVOR11Handler .

1 INTC: Software Vector Mode Description Task: Using the Interrupt Controller (INTC) in software vector mode. Note: eMIOS channel 0 interrupt vector numbers are different on MPC551x and MPC555x devices. Invoke this new software interrupt from one of the other ISRs. Software Vector Mode Example Qorivva Simple Cookbook.4 4.33 kHz. MPC5500 SIU_SYSCLK (MPC551x only) Divide sysclk by 1 for eMIOS eMIOS eMIOS Prescaler (Divide by 12) eMIOS Channel 0 Mod. This provides an approximate 1 millisecond task (ISR) from the eMIOS channel and an approximate 2 millisecond task (ISR) from the software interrupt. The interrupt handler will re-enable interrupts and later. Both ISRs will have a counter. Exercise: Write a third interrupt handler that uses a software interrupt of a higher priority than the others. the eMIOS channel mode will be the modulus counter for MPC555x devices that have that mode. 4 22 Freescale Semiconductor . so the 1 eMIOS ISR is preempted by the software interrupt. in its interrupt service routine (ISR). invoke a second interrupt every other time. Rev. 4 (set in eMIOS channel 0 interrupt service routine) Interrupt Request to INTC Crystal 8 MHz Clocks and PLL INTC (Software Vector Mode) Default sysclk: 16 MHz (MPC551x) 12 MHz (MPC555x) 8 MHz (MPC563x) Interrupt Request to INTC Common INTC interrupt request to CPU core Figure 8. The SPE will not be used. This example is identical to INTC: Hardware Vector Mode except for the differences between software and hardware vector modes. Also. so its accumulator will not be saved in the stack frame of the interrupt handler. The first interrupt is generated from an eMIOS channel at a 1 kHz rate using the MPC555x default system clock. Counter: (Divide by 1 & count to 1000) Software settable interrupt req. this program provides two interrupts that show nesting. The software interrupt will have a higher priority. the faster default system clock produces an eMIOS channel timeout rate of approximately 1 kHz  16/12 = 1. For the MPC551x. The ISRs will be written in C. or the newer modulus counter buffered mode. to generate the timed interrupt. so the appropriate registers will be saved and restored in the handler.

c file main { init IVPR. The Vector Table Base Address is defined in each core’s INTC_ACKR. IVPR. b IVOR4Handler . that is. it is routed to either or both cores.s file IVOR4Handler: prologue: save SRR0:1.. processor 0 (e200z1). re-enable interrupts save registers branch to fetched ISR vector epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return Figure 9.. IntcIsrVectors.4. MPC551x Program Flow Qorivva Simple Cookbook. When an interrupt occurs. . . Rev. IVOR4 init INTC init eMIOS Chan 0 init SW 4 interrupt enable interrupts wait forever } emiosCh0ISR { increment counter if odd count.. For MPC551x. there can be a different ISR Vector table for each core because each core has its own special purpose register. eMIOS Ch 0 ISR addr .c file ISR Vector Table: ....... 4 Freescale Semiconductor 23 . This example uses only the e200z1 core. which here is eMIOS channel 0 and software interrupt 4. invoke SW 4 IRQ clear flag } SwIrq4ISR { increment counter clear flag } handlers.... fetch ISR vector.. either INTC_ACK_PRC0 for e200z1 and INTC_IACK_PRC1 for e200z0. SW IRQ 4 ISR addr . In this example only one processor is selected in the MPC551x for interrupts.s file IVOR Branch Table b IVOR0trap b IVOR1trap . External input interrupt taken for selected processor vector to IVPR0:19 + 4 (for IVOR4) 16 bytes ivor_branch_table.. as defined in the INTC_PSR for that vector. The selection is defined in INTC_PSR for each enabled interrupt.2 Design The overall program flow for MPC551x is shown below. main.

. IVOR4 init INTC init eMIOS Chan 0 init SW 4 interrupt enable interrupts wait forever } emiosCh0ISR { increment counter if odd count.. .c file main { init IVPR. 4 24 Freescale Semiconductor . MPC555x Program Flow Qorivva Simple Cookbook. eMIOS Ch 0 ISR addr . External input interrupt taken vector to IVPR0:15 + IVOR416:27 handlers.... Figure 10. SW IRQ 4 ISR addr . re-enable interrupts save registers branch to fetched ISR vector epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return main. fetch ISR vector.s file IVOR4Handler: prologue: save SRR0:1... invoke SW 4 IRQ clear flag } SwIrq4ISR { increment counter clear flag } IntcIsrVectors..c file ISR Vector Table: .. Rev. .The overall program flow for MPC555x is shown below..

Rev. is used here) HVEN_PRC0=0(551x) VTES_PRC0=0(551x) HVEN = 0 (MPC555x) VTES = 0 (MPC555x) VTBA = passed from linker INTC_MCR = 0 INTC_IACKR INTC_IACKR _PRC 0 = = __IACKR_ __IACKR_ VTBA_VALUE VTBA_VALUE EMIOS_MCR = 0x3400 B000 initEMIOS Initialize eMIOS global settings for all channels: • Prescale sysclk by 12 for eMIOS clk • Enable eMIOS clock • Enable global time base • Enable stopping channels in debug mode MPC551x: Ensure channel is not disabled Channel 0 Interrupt: raise priority to 1 • MPC551x: Select processor(s) to interrupt Channel 0: set max count = 1. up counter buffered • Mode (MPC555x) = modulus up counter • Counter bus select = internal counter • Channel prescaler = 1 • Enable channel prescaler • Enable freezing count in debug mode • Assign flag to assert IRQ (instead of DMA) • Enable flag to request IRQ GPRE = 11 (0xB) GPREN = 1 GTBE = 1 FRZ=1 EMIOS_ UCDIS = 0 – PRI = 1 INTC_PSR[58] INTC_PSR[51] PRC_SEL=0 (e200z1) = 0x01 = 0x01 A = 999 MODE=0x50 or MODE=0x10 BSL=3 UCPRE=0 (default) UCPREN=1 FREN=1 DMA=0 (default) FEN=1 PRI = 2 PRC_SEL=0 (e200z1) EMIOS_A[0] = 999 EMIOS_ CCR[0] = 0x8202 0650 MPC555x: EMIOS_ CCR[0] = 0x8202 0610 MPC563x: EMIOS_ CCR[0] = 0x8202 0650 INTC_PSR[4] = 0x02 INTC_CPR _PRC0[PRI]= 0 INTC_CPR [PRI]= 0 initSwIrq4 Software Interrupt 4: raise priority to 2 • MPC551x: Specify which processor(s) to interrupt enableExtIrq Enable recognition of requests to INTC by lowering the PRI = 0 INTC’s current priority to 0 from default of 15 Enable external interrupts by setting MSR[EE] = 1 waitloop wait forever wrteei 1 while 1 Qorivva Simple Cookbook. 563x) = mod.000 clks ( ~1 s each) Channel 0: Enable channel as up counter & enable IRQ • Mode (MPC551x.2. 4 Freescale Semiconductor 25 .1 Initialization Table 12. e200z1 is used here) Initialize ISR vector table base address per link file (MPC551x note: only proc’r 0.4. Initialization: INTC in Software Vector Mode Pseudo Code Step Relevant Bit Fields MPC551x MPC555x int emiosCh0Ctr = 0 int SWirq4Ctr = 0 &SwIrq4ISR &emiosCh0ISR spr IVPR =__IVPR_VALUE – spr IVOR4 = IVOR4Handler @l Variable Counter for eMIOS channel 0 interrupts Initializations Counter for software 4 interrupts Table Load INTC’s ISR vector table with addresses for: Initializations INTC Vector 4 ISR (SW interrupt request 4) INTC Vector 51 ISR (eMIOS channel 0) initIrqVectors Load the common interrupt vector prefix to spr IVPR MPC555x: Initialize external input interrupt offset to the lower half of IVROR4 handler’s address initINTC Initialize INTC: • Configure for software vector mode (HVEN=0) • Keep vector offset (VTES) at four bytes (MPC551x note: only proc’r 0. e200z1.

Stack Frame for INTC Interrupt Handler Stack Frame Area 32-bit GPRs r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r0 CR locals and padding CR XER CTR LR SRR1 SRR0 padding LR area back chain LR placeholder r1 Register Location in Stack sp + 0x4C sp + 0x48 sp + 0x44 sp + 0x40 sp + 0x3C sp + 0x38 sp + 0x34 sp + 0x30 sp + 0x2C sp + 0x28 sp + 0x24 sp + 0x20 sp + 0x1C sp + 0x18 sp + 0x14 sp + 0x10 sp + 0x0C sp + 0x08 sp + 0x04 sp Qorivva Simple Cookbook.2. 4 26 Freescale Semiconductor . Rev.4.2 Interrupt Handler Table 13.

ISR for eMIOS Channel 0 Step Relevant Bit Fields Pseudo Code emiosCh0Ctr ++ SET = 1 if ((emosCh0Ctr&1)). MPC551x does not require alignment because it is the destination of a branch instruction. sp.2. working registers from stack frame addi sp. invoke Software Interrupt 4 Clear eMIOS Ch 0 interrupt flag by writing 1 to it FLAG = 1 Table 16. saving return address epilog Restore registers from stack frame except SRR0:1 and two working registers Ensure interrupt flag in ISR has completed clearing before writing to INTC_EOIR Disable external interrupts by clearing MSR[EE] Restore former INTC’s Current Priority Restore SRR0:1 and working registers Restore stack frame space Return EE = 0 EE = 1 Relevant Bit Fields Pseudo Code MPC551x MPC555x stwu sp. INTC_SSCIR[4] = 2 EMIOS_CSR0[FLAG] = 1 emiosCh0ISR Increment emiosCh0Ctr If emiosCh0Ctr is even. r3 registers to stack frame r3 = INTC_IACKR_PRC0 wrteei 1 lwz r3. 0x50 rfi 4. 0x0 (r3) mtLR r3 store other registers to stack frame blrl load most registers from stack frame mbar wrteei 0 write 0 to INTC_EOIR_PRC0 write 0 to INTC_EOIR r3 = INTC_IACKR restore SRR0:1. 4 Freescale Semiconductor 27 .Table 14.) Step prolog Create stack frame Save SRR0:1 because nested interrupts will be allowed Read pointer into ISR Vector Table Re-enable external interrupts by setting MSR[EE] Read ISR address from ISR Vector Table and store into LR Save other appropriate registers for C ISR Branch to ISR. ISR for Software Interrupt 4 Step swIRQ4ISR Increment SWirq4ctr Clear Software IRQ 4 CLR = 1 Relevant Bit Fields Pseudo Code SWirq4ctr++ INTC_SSCIR[4] = 1 Qorivva Simple Cookbook.3 Interrupt Service Routines (ISRs) Table 15. –0x50 (sp) store SRR0:1. Rev. IVOR4 Interrupt Handler (INTC in Software Vector Mode) (MPC555x: Must be 16 byte aligned and within 64KB of address in IVPR.

SRAM not initialized.MCR.CCR.PSR[58].Software vector mode program using C isr */ Jan 15. */ /* Ensure all channels are enabled */ /* Use one of the following two lines: */ /*INTC.M. uses default divide by 1 */ EMIOS. /* MPC555x: initialize for SW vector mode */ INTC.B.CH[0].removed unused cache init & enabled eMIOS FREEZE */ Mar 4.CCR.B.renamed SWirq7Ctr to SWirq4Ctr for consistency */ Aug 12 2006 S. /* Freeze channel registers when in debug mode */ EMIOS.GPRE= 11.FRZ = 1. /* Interrupt Vector Prefix value from link file*/ extern const vuint32_t IntcIsrVectorTable[]. /* Use internal counter */ EMIOS. All Rights Reserved */ Feb 9.c file main.HVEN_PRC0 = 0.MCR.c .GPREN = 1. IVOR4Handler@l /* IVOR4 = lower half of handler address */ mtivor4r3 } void initINTC(void) { /* /* /* /* } /* Use the first 3 or next 3 lines: */ Use the first 3 or next 3 lines for MPC551x or MPC555x: */ INTC.VTES = 0.*/ /* MPC551x Proc'r 0: initialize for SW vector mode */ INTC. . int emiosCh0Ctr = 0.MCR.R = 1. /* Enable eMIOS clock */ EMIOS.CH[0].R = (uint32_t) &IntcIsrVectorTable[0].PSR[51].R= (uint32_t) &IntcIsrVectorTable[0]. changed timeout to 1 msec*/ and changed EMIOS_MCR[PRE] & EMIOS Chan 0 A Register values */ Copyright Freescale Semiconductor. In.GTBE = 1.MODE = 0x10.CH[0].CADR. /* MPC555x INTC ISR table base */ void initEMIOS(void) { EMIOS.MCR.CH[0].FEN=1.VTES_PRC0 = 0. /* Divide sysclk by (11+1) for eMIOS clock */ EMIOS.CH[0]. /* MPC555x: Use default vector table 4B offsets */ INTC.*//*MPC551x ISR table base*/ INTC.M.CH[0].B.B.*/ /* MPC551x Proc'r 0: default vector table 4B offsets*/ ITC. /* Period will be 999+1 = 1000 channel clocks */ /* Use one of the next two lines: MCB mode is not in all MPC555x devices */ EMIOS.*/ /* MPC555x: Modulus Counter (MC).UCDIS.R = 999. /* Flag enables interrupt */ } Qorivva Simple Cookbook.CCR.MCR.UCPREN = 1.CH[0].h" /* Use proper include file like mpc5510. MMU not initialized.M. */ Notes: */ 1.made i volatile (to get fewer Nexus messages in loop) */ Jul 17 2007 SM .B. 4 28 Freescale Semiconductor . Rev.h */ extern IVOR4Handler(). /* Enable stopping channels when in debug mode */ /* Following for MPC551x only: */ /* EMIOS. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r3. 2004 S. Buffered (MCB) */ /*EMIOS.CCR.MCR.c 2007 All rights reserved. used relevant names */ for MPC551x bit fields & registers.IACKR.MCR. r3. must be done by debug scripts or BAM */ 2. __IVPR_VALUE@l mtivpr r3 /* The following two lines are required for MPC555x. Ctr.1 /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* Code main.HVEN = 0.IACKR_PRC0.B. Cache is not used */ #include "mpc563m. extern uint32_t __IVPR_VALUE. 2004 S.Passed IVPR value from link file.2006 S.R = 0. .CCR.h or mpc5554. /* Enable prescaler. */ /* MPC551x: Raise eMIOS chan 0 IRQ priority = 1 */ INTC.B. invoked SW interrupt*/ on even count eMIOS Ch 0 ISRs.4.B. internal clk */ EMIOS.added software interrupt 7 code */ May 19.FREN = 1.MODE = 0x50.3.BSL = 0x3.B.B. .B. /* MPC551x or MPC563x: Mod. /* Enable global time base */ EMIOS. 2004.3 4.R = 1. must be done by debug scripts or in a crt0 type file */ 3. and are not used for MPC551x*/ li r3.M.B. /* Counter for software interrupt 4 */ asm void initIrqVectors(void) { lis r3. 2004 S.CCR.MCR.Mihalik -.Copyright Freescale. /* Counter for eMIOS channel 0 interrupts */ int SWirq4Ctr = 0.B. /* MPC555x: Raise eMIOS chan 0 IRQ priority = 1 */ EMIOS..B.

R = 2. } EMIOS.CSR. while (1) { i++. } Qorivva Simple Cookbook. */ /* MPC551x Proc'r 0: Lower INTC's current priority */ INTC.CPR. initEMIOS().B. } void SwIrq4ISR(void) { SWirq4Ctr++. if ((emiosCh0Ctr & 1)==0) { INTC. initIrqVectors(). initINTC().CH[0].R = 1. } /* Increment interrupt counter */ /* If emiosCh0Ctr is even*/ /* then nvoke software interrupt 4 */ /* Clear channel's flag */ /* Increment interrupt counter */ /* Clear channel's flag */ /* Dummy idle counter */ /* /* /* /* /* Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize eMIOS channel 0 for 1kHz IRQ.void initSwIrq4(void) { INTC.B.B. } /* Software interrupt 4 IRQ priority = 2 */ void enableIrq(void) { /* Use one of the following two lines to lower the INTC current priority */ /*INTC. /* MPC555x: Lower INTC's current priority */ asm(" wrteei 1").SSCIR[4]. Rev.PSR[4].CPR_PRC0.PRI = 0. enableIrq().PRI = 0.R = 2.FLAG=1. priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void emiosCh0ISR(void) { emiosCh0Ctr++.SSCIR[4]. initSwIrq4(). /* Enable external interrupts */ } void main (void) { vuint32_t i = 0. INTC. 4 Freescale Semiconductor 29 .

r4 r4.0: April 23. 0xfff48010# INTC_EOIR_PRC0. -0x50 (r1) stw r3. IVOR4Handler: prolog: stwu r1. Cygnus.LR * Reserved for calling function # 0x00 * SP * Backchain (same as gpr1 in GPRs) # ************* . 0x0(r3) # Read ISR address from ISR Vector Table using pointer wrteei stw mflr stw mtlr 1 r4. 0x0C (r1) mfsrr1 r3 stw r3.optimized by minimizing time interrupts are disabled Rev 1. INTC_IACKR_PRC0@ha # Read proc'0 ptr into ISR Vector Table. 2007. epilog for C ISR and enables nested interrupts Rev 1.align 16 # Align IVOR handlers on a 16 byte boundary for MPC555x # GHS. 0xfff48010 # INTC_EOIR. CodeWarrior .2 Sept 8 2004 SM . addr.INTC software vector mode example Description: Creates prolog. S Mihalik.align 16 . 0xfff48018 # INTC_IACKR.r4 restore sequence from rev 1. store in r3 lwz r3.3 Jul 2 2007 SM .equ . Inc. Rev 1. INTC_IACKR@ha # Read pointer into ISR Vector Table & store in r3 lwz r3.3. 4 30 Freescale Semiconductor .Changes for MPC551x and mapped to . 0x28 (r1) mfsrr0 r3 stw r3.ivor_handlers section Copyright Freescale Semiconductor.align 4.optimized & corrected r3. Rev. Diab(default) use . INTC_IACKR@l(r3) lwz r3. r3 # Set MSR[EE]=1(must wait a couple clocks after reading IACKR) 0x2C (r1) # Store a second working register # Store LR (LR will be used for ISR Vector) 0x14 (r1) # Store ISR address to LR to use for branching later Qorivva Simple Cookbook.1 Rev 1.1 Aug 2.2 Sept 21 2004 SM .2 # # # # # # # # handlers. INTC_IACKR_PRC0@l(r3) The following two lines are for MPC555x processors: */ lis r3.globl IVOR4Handler .ivor_handlers . addr Interrupt Acknowledge Reg. 2004 SM .s . 0xfff48018 # # # # # MPC551x: MPC551x: MPC555x: MPC555x: Proc'r 0 Interrupt Acknowledge Reg addr Proc'r 0 End Of Interrupt Reg. End Of Interrupt Reg.equ . 2004. 0x10 (r1) # # # # PROLOGUE Create stack frame and store back chain Store a working register Store SRR0:1 (must be done before enabling EE) The following two lines are for MPC551x processors: */ lis r3. or 80 bytes) # ************* ______________ # 0x4C * GPR12 * ^ # 0x48 * GPR11 * | # 0x44 * GPR10 * | # 0x40 * GPR9 * | # 0x3C * GPR8 * | # 0x38 * GPR7 * GPRs (32 bit) # 0x34 * GPR6 * | # 0x30 * GPR5 * | # 0x2C * GPR4 * | # 0x28 * GPR3 * | # 0x24 * GPR0 * ___v__________ # 0x20 * CR * __CR__________ # 0x1C * XER * ^ # 0x18 * CTR * | # 0x14 * LR * locals & padding for 16 B alignment # 0x10 * SRR1 * | # 0x0C * SRR0 * | # 0x08 * padding * ___v__________ # 0x04 * resvd.equ INTC_IACKR_PRC0.s file handlers. addr. All rights reserved # STACK FRAME DESIGN: Depth: 20 words (0xA0.equ .delayed writing to EOIR until after disabling EE in epilog Rev 1.section .4.

0x28 (r1) addi r1. 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x24 (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) # Store rest of gprs 0x20 (r1) 0x1C (r1) 0x18 (r1) # Store CR # Store XER # Store CTR # Branch to ISR. r1. r0. r6. 0x1C (r1) # Restore XER mtxer r3 lwz r3. 0x48 (r1) lwz r12. 0x44 (r1) lwz r11.stw stw stw stw stw stw stw stw stw mfcr stw mfxer stw mfctr stw blrl r12. 0x14 (r1) # Restore LR mtlr r3 lwz r3. Rev. 0x0C (r1) # Restore SRR0 mtsrr0 r3 lwz r3. 0x4C (r1) mbar 0 # Ensure store to clear interrupt's flag bit completed # The following line is for the MPC551x: # lis r3. r7. 0x2C (r1) # Restore working registers lwz r3. r5. r8. 0x20 (r1) # Restore CR mtcrf 0xff. 4 Freescale Semiconductor 31 . r11. INTC_EOIR@l(r3)# MPC555x: Write 0 to INTC_EOIR lwz r3. r3 r3. r9. INTC_EOIR_PRC0@l(r3)# MPC551x: Write 0 to proc'r 0 INTC_EOIR # The following line is for MPC555x: stw r4. 0x24 (r1) # Restore other gprs except working registers lwz r5. r3 lwz r0. 0x34 (r1) lwz r7. 0x3C (r1) lwz r9. 0x18 (r1) # Restore CTR mtctr r3 lwz r3. 0x38 (r1) lwz r8. r3 r3. INTC_EOIR@ha# MPC555x: Load upper half of EIOR address to r3 li r4. r3 r3. 0x10 (r1) # Restore SRR1 mtsrr1 r3 lwz r4. but return here epilog: # EPILOGUE lwz r3. INTC_EOIR_PRC0@ha# MPC551x: Load upper half of proc'r 0 EIOR addr to r3 # The following line is for the MPC555x: lis r3. r10. 0x50 # Delete stack frame rfi # End of Interrupt Qorivva Simple Cookbook. 0 wrteei 0 # Disable interrupts for rest of handler # The following line is for MPC551x: # stw r4. 0x40 (r1) lwz r10. 0x30 (r1) lwz r6.

(uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 15 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. changes for MPC551x */ Aug 30 2007 SM . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs 100 105 110 115 120 125 130 135 140 145 150 155 160 155 170 175 180 185 190 195 200 205 210 215 220 225 230 235 104 109 114 119 124 129 134 139 144 149 154 159 164 169 174 179 184 189 194 199 204 209 214 219 224 229 234 239 */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ Qorivva Simple Cookbook.54 */ /*(uint32_t)&dummy. /* ISRs 45 . (uint32_t)&dummy. extern void SwIrq4ISR(void). (uint32_t)&dummy. (uint32_t)&dummy. 2006 S.99 */ (uint32_t)&dummy. /* ISRs 60 . (uint32_t)&dummy. (uint32_t)&SwIrq4ISR. (uint32_t)&dummy.89 */ (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 55 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* Use pragma next two lines with CodeWarrior compile */ uint32_t IntcIsrVectorTable[] = { #pragma section data_type ". (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 55 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.3 /* /* /* /* /* /* /* /* /* /* IntcIsrVectors. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 40 . */ /* ISRs 55 . (uint32_t)&dummy. */ /* ISRs 50 .34 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. All rights reserved. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.h" /* Use proper include file like mpc5510. /* ISRs 10 . (uint32_t)&dummy. /* ISRs 50 . (uint32_t)&dummy. (uint32_t)&dummy. Mihalik */ March 16. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.alignment now done in link file. (uint32_t)&dummy. /* ISRs 70 . (uint32_t)&dummy. (uint32_t)&dummy.54 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.94 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 90 . Mihalik .79 */ (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 05 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 85 . (uint32_t)&dummy. (uint32_t)&dummy. Rev. (uint32_t)&dummy.Added pragma for CodeWarrior */ #include "mpc563m. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.intc_sw_isr_vector_table" */ /* Diab compiler pragma */ /* const uint32_t IntcIsrVectorTable[] = { */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.h */ void dummy (void). (uint32_t)&dummy.04 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.c .59 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.c file IntcIsrVectors. (uint32_t)&dummy.table of ISRs for INTC in SW vector Mode */ Description: Contains addresses for 310 ISR vectors */ Table address gets loaded to INTC_IACKR */ Alignment: MPC551x: 2 KB after a 4KB boundary. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.09 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.intc_sw_isr_vector_table" data_mode=far_abs /* Use next two lines with Diab compile */ /* #pragma section CONST ".19 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.4. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 00 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&emiosCh0ISR. (uint32_t)&dummy. (uint32_t)&dummy.3 */ Jun 29 2006 SM .3. (uint32_t)&dummy.h or mpc5554. 2004 S. (uint32_t)&dummy.24 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. 4 32 Freescale Semiconductor .29 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.Modified for compile with Diab 5. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 75 . (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 30 . (uint32_t)&dummy. (uint32_t)&dummy.74 */ (uint32_t)&dummy. extern void emiosCh0ISR(void). (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.14 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. */ April 22. (uint32_t)&dummy. (uint32_t)&dummy.64 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.intc_sw_isr_vector_table" ". (uint32_t)&dummy. (uint32_t)&dummy.39 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 95 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.59 */ /* Use next 2 lines for MPC555x: */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.44 */ (uint32_t)&dummy. /* ISRs 20 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.84 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 80 . (uint32_t)&dummy. /* ISRs 25 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.69 */ (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 35 . (uint32_t)&dummy. MPC555x: 64 KB*/ Copyright Freescale Semiconductor Inc 2007. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.49 */ /* Use next 2 lines for MPC551x: */ /*(uint32_t)&dummy. (uint32_t)&emiosCh0ISR. (uint32_t)&dummy.Used pragma align instead of hard coding address */ Jul 5 2007 SM .

(uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.309 */ }. (uint32_t)&dummy. /* ISRs 305 . (uint32_t)&dummy. (uint32_t)&dummy. /* /* /* /* /* /* /* /* /* /* /* /* ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs ISRs 240 245 250 255 260 255 270 275 280 285 290 295 - 244 249 254 259 264 269 274 279 284 289 294 299 */ */ */ */ */ */ */ */ */ */ */ */ (uint32_t)&dummy. void dummy (void) { while (1) {}. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 300 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* Wait forever or for watchdog timeout */ } Qorivva Simple Cookbook. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. 4 Freescale Semiconductor 33 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.(uint32_t)&dummy.304 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. Rev. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.

align SIXTEEN_BYTES b IVOR15trap # IVOR15 interrupt handler Qorivva Simple Cookbook.1 Aug 30 2007 SM .align SIXTEEN_BYTES b IVOR13trap # IVOR 13 interrupt handler . GHS.align SIXTEEN_BYTES b IVOR6trap # IVOR 6 interrupt handler .ivor_branch_table .4. All Rights Reserved Rev 1.align SIXTEEN_BYTES b IVOR2trap # IVOR 2 interrupt handler . Rev.align SIXTEEN_BYTES b IVOR5trap # IVOR 5 interrupt handler .align SIXTEEN_BYTES b IVOR9trap # IVOR 9 interrupt handler .align SIXTEEN_BYTES b IVOR7trap # IVOR 7 interrupt handler .equ SIXTEEN_BYTES.Initial version Rev 1.align SIXTEEN_BYTES b IVOR14trap # IVOR 14 interrupt handler .s .align SIXTEEN_BYTES b IVOR8trap # IVOR 8 interrupt handler .align SIXTEEN_BYTES b IVOR0trap # IVOR 0 interrupt handler .s file (MPC551x only) ivor_branch_table.3.align SIXTEEN_BYTES b IVOR11trap # IVOR 11 interrupt handler .align SIXTEEN_BYTES IVOR4Handler # IVOR 4 interrupt handler (External Interrupt) . Cygnus use 16 IVOR0trap: IVOR1trap: IVOR2trap: IVOR3trap: b IVOR5trap: IVOR6trap: IVOR7trap: IVOR8trap: IVOR9trap: IVOR10trap: IVOR11trap: IVOR12trap: IVOR13trap: IVOR14trap: IVOR15trap: .0 Jul 6 2007 S Mihalik .Made IVOR4Handler extern .for use with MPC551x only Description: Branch table for 16 MPC551x core interrupts Copyright Freescale 2007.section . 16 # 16 byte alignment required for table entries # Diab compiler uses value of 4 (2**4=16) # CodeWarrior.align SIXTEEN_BYTES b IVOR3trap # IVOR 3 interrupt handler .align SIXTEEN_BYTES b IVOR1trap # IVOR 1 interrupt handler .4 # # # # # ivor_branch_table.align SIXTEEN_BYTES b IVOR12trap # IVOR 12 interrupt handler .align SIXTEEN_BYTES b IVOR10trap # IVOR 10 interrupt handler .extern IVOR4Handler . 4 34 Freescale Semiconductor .

The ISRs will be written in C. 4 Freescale Semiconductor 35 . so its accumulator will not be saved in the stack frame of the interrupt handler. Counter: (Divide by 1 & count to 1000) Software settable interrupt req. Qorivva Simple Cookbook. except for the differences between software and hardware vector modes.33 kHz. Invoke this new software interrupt from one of the other ISRs. the eMIOS channel mode will be the modulus counter for MPC555x devices that have that mode. It is assumed SPE instructions are not used in this example. so the appropriate registers will be saved and restored in the handler. 4 (set in eMIOS channel 0 interrupt service routine) Interrupt Request to INTC INTC (Hardware Vector Mode) Crystal 8 MHz Clocks and PLL Default sysclk: 16 MHz (MPC551x) 12 MHz (MPC555x) 8 MHz (MPC563x) Interrupt Request to INTC Unique INTC interrupt request to CPU core Figure 11. invoke a second interrupt every other time.1 INTC: Hardware Vector Mode Description Task: Using the Interrupt Controller (INTC) in hardware vector mode. Rev. this program provides two interrupts that show nesting. Hardware Vector Mode Example 1.. The software interrupt will have a higher priority. MPC5500 SIU_SYSCLK (MPC551x only) Divide sysclk by 1 for eMIOS eMIOS eMIOS Prescaler (Divide by 12) eMIOS Channel 0 Mod. or the newer modulus counter buffered mode. The interrupt handler will re-enable interrupts and later. For the MPC551x. Also. Both ISRs will have a counter. The SPE’s accumulator is not saved in the prologue. This example is identical to INTC: Software Vector Mode.5 5. the faster default system clock produces an eMIOS channel timeout rate of approximately 1 kHz  16/12 = 1. to generate the timed interrupt.1 Exercise: Write a third interrupt handler that uses a software interrupt of a higher priority than the others. The first interrupt is generated from an eMIOS channel at a 1 kHz rate using the MPC555x default system clock. so the one eMIOS ISR is preempted by the software interrupt. in its interrupt service routine (ISR). Note: eMIOS channel 0 interrupt vector numbers are different on MPC551x and MPC555x devices. This provides an approximate 1 millisecond task (ISR) from the eMIOS channel and an approximate 2 millisecond task (ISR) from the software interrupt. The SPE will not be used.

5.2

Design

The overall program flow is shown below, followed by design steps and a stack frame implementation. The INTC when used in hardware vector mode uses a branch table for getting to each INTC vector’s handler. These are shown as handler_0, handler_1, etc. (Note: the code in this example does not have handlers for each INTC vector, so a common dummy trap address is used.) For MPC551x, the second core has its own special purpose register, IVPR, so the second core would have its own IntcHanderBranchTable (not included in this example). Also for MPC551x, either or both processors can receive the interrupt request from the Interrupt Controller. In this example only one processor is selected in the MPC551x, processor 0 (e200z1). The selection is defined in INTC_PSR for each enabled interrupt, which here is eMIOS channel 0 and software interrupt 4.
INTC vector for eMIOS Channel 0 interrupt taken vector to MPC551x: IVPR0:19 + 0x800 + 51 (0x4) MPC555x: IVPR0:15 + 51 (0x10) handlers.s file intc_hw_branch_table.s file IntcHandlerBranchTable b handler_0 ... b handler_1 ... b handler_2 ... b handler_3 ... b SwIrq4Handler ... ... ... ... b emiosCh0Handler ... ... ... emiosCh0Handler: prologue: save registers re-enable interrupts branch to emiosCh0ISR epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return SwIrq4Handler: prologue: save registers re-enable interrupts branch to SwIrq4ISR epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return main.c file main { init IVPR init INTC init SwIrq4 init eMIOS Chan 0 enable interrupts wait forever } emiosCh0ISR { increment counter if odd count, invoke SW 4 IRQ clear flag } SwIrq4ISR { increment counter clear flag }

Figure 12. Overall Program Flow (Shown for MPC555x which uses INTC vector 51 for eMIOS channel 0. MPC551x uses INTC vector 58 for eMIOS channel 0.)

Qorivva Simple Cookbook, Rev. 4 36 Freescale Semiconductor

5.2.1

Initialization
Table 17. Initialization: INTC in Hardware Vector Mode
Pseudo Code Step Relevant Bit Fields MPC551x MPC555x int emiosCh0Ctr = 0 int SWirq4Ctr = 0 b SwIrq4ISR b emiosCh0ISR spr IVPR =__IVPR_VALUE HVEN_PRC0 = 0(551x) INTC_MCR INTC_MCR HVEN = 0 (MPC555x) [HVEN_PRC0] [HVEN] =1 =1 GPRE = 11 (0xB) GPREN = 1 GTBE = 1 FRZ = 1 EMIOS_MCR = 0x3400 B000

Variable Counter for eMIOS channel 0 interrupts Initializations Counter for software 4 interrupts Table Load INTC HW Branch Table with ISR names for: Initializations INTC Vector 4 ISR (SW interrupt request 4) INTC Vector 51 ISR (eMIOS channel 0) initIrqVectors Load the common interrupt vector prefix to spr IVPR. Value is defined in the link file. initINTC Initialize INTC: • Configure for hardware vector mode (MPC551x note: only proc’r 0, e200z1, is used here) Initialize EMIOS global settings for all channels: • Prescale sysclk by 12 for eMIOS clock • Enable eMIOS clock • Enable global time base • Enable stopping channels in debug mode MPC551x: Ensure channel is not disabled Channel 0 Interrupt: • Raise priority to 1 • MPC551x: Select processor(s) to interrupt Channel 0: set max count = 1,000 clks ( ~ 1 s each) Channel 0: Enable channel as up counter & enable IRQ • Mode (MPC551x, 563x) = modulus up counter buffered • Mode (MPC555x) = modulus up counter • Counter bus select = internal counter • Channel prescaler = 1 • Enable channel prescaler • Enable freezing count in debug mode • Assign flag to assert IRQ (instead of DMA) • Enable flag to request IRQ initSwIrq4 Software Interrupt 4: • Raise priority to 2 • MPC551x: Specify which processor(s) to interrupt

initEMIOS

EMIOS_ UCDIS = 0 PRI = 1 PRC_SEL = 0 (e200z1) A = 999 INTC_PSR [58] = 0x01

– INTC_PSR [51] = 0x01

EMIOS_A[0] = 999 EMIOS_ CCR[0] = 0x8202 0650 MPC555x: EMIOS_ CCR[0] = 0x8202 0610 MPC563x: EMIOS_ CCR[0] = 0x8202 0650 INTC_PSR[4] = 0x02

MODE = 0x50 or MODE = 0x10 BSL = 3 UCPRE = 0 (default) UCPREN = 1 FREN = 1 DMA = 0 (default) FEN = 1

PRI = 2 PRC_SEL = 0 (e200z1) INTC_CPR _PRC0[PRI] =0 INTC_CPR [PRI] =0

enableExtIrq Enable recognition of requests to INTC by lowering the PRI = 0 INTC’s current priority to 0 from default of 15 (MPC551x note: only proc’r 0, e200z1, is used here) Enable external interrupts by setting MSR[EE] = 1 waitloop wait forever

wrteei 1 while 1

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 37

5.2.2

Interrupt Handlers
Table 18. Stack Frame for INTC Interrupt Handler (Same as for Software Vector Mode Example)
Stack Frame Area 32-bit GPRs r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r0 CR locals and padding CR XER CTR LR SRR1 SRR0 padding LR area back chain LR placeholder r1 Register Location in Stack sp + 0x4C sp + 0x48 sp + 0x44 sp + 0x40 sp + 0x3C sp + 0x38 sp + 0x34 sp + 0x30 sp + 0x2C sp + 0x28 sp + 0x24 sp + 0x20 sp + 0x1C sp + 0x18 sp + 0x14 sp + 0x10 sp + 0x0C sp + 0x08 sp + 0x04 sp

Qorivva Simple Cookbook, Rev. 4 38 Freescale Semiconductor

Table 19. eMIOS Channel 0 Interrupt Handler (INTC in Hardware Vector Mode)
Step prolog Create stack frame Save SRR0:1 because nested interrupts will be allowed Re-enable external interrupts by setting MSR[EE] Save other appropriate registers for C ISR Branch to ISR, saving return address emiosCh0 Increment emiosCh0Ctr ISR If emiosCh0Ctr is even, invoke software Interrupt 4 Clear eMIOS Ch 0 interrupt flag by writing 1 to it epilog Restore registers from stack frame except SRR0:1 and two working registers Ensure interrupt flag in ISR has completed clearing before writing to INTC_EOIR Disable external interrupts by clearing MSR[EE] Restore former INTC’s current priority Restore SRR0:1 and working registers Restore stack frame space Return EE = 0 EE = 1 Relevant Bit Fields Pseudo Code MPC551x MPC555x

stwu sp, – 0x50 (sp) store SRR0:1, r3 registers to stack frame wrteei 1 store other registers to stack frame bl emiosCh0ISR emiosCh0Ctr++ SET = 1 FLAG = 1 if ((emiosCh0Ctr&1), INTC_SSCIR[4] = 1 EMIOS_CSR0[FLAG] = 1 load most registers from stack frame mbar wrteei 0 write 0 to INTC_EOIR_PRC0 write 0 to INTC_EOIR

restore SRR0:1, working registers from stack frame addi sp, sp, 0x50 rfi

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 39

Software 4 Interrupt Handler (INTC in Hardware Vector Mode) Step prolog Create stack frame Save SRR0:1 because nested interrupts will be allowed Re-enable external interrupts by setting MSR[EE] Save other appropriate registers for C ISR Branch to ISR. sp. – 0x50 (sp) store SRR0:1.Table 20. working registers from stack frame addi sp. Rev. r3 registers to stack frame wrteei 1 store other registers to stack frame bl SWIrq4ISR SWirq4Ctr++ INTC_SSCIR4 = 1 load most registers from stack frame mbar wrteei 0 write 0 to INTC_EOIR_PRC0 write 0 to INTC_EOIR restore SRR0:1. 4 40 Freescale Semiconductor . 0x50 rfi Qorivva Simple Cookbook. saving return address SWIrq4 ISR epilog Increment SWirq4Ctr Clear software IRQ 4 interrupt flag by writing 1 to it Restore registers from stack frame except SRR0:1 and two working registers Ensure interrupt flag in ISR has completed clearing before writing to INTC_EOIR Disable external interrupts by clearing MSR[EE] Restore former INTC’s current priority Restore SRR0:1 and working registers Restore stack frame space Return EE = 0 CLR = 1 EE = 1 Relevant Bit Fields Pseudo Code MPC551x MPC555x stwu sp.

HVEN_PRC0 = 1. */ /* MPC551x: Ensure all channels are enabled */ /* Use one of the following two lines: */ /* INTC. __IVPR_VALUE@l mtivpr r3 } /* IVPR value is passed from link file */ /* Note: IVPR lower bits are unused in MPC555x */ void initINTC(void) { /* Use one of the next two lines: */ /*INTC.B.B.PSR[58].INTC in Hardware vector mode using C ISRs */ Copyright Freescale Semiconductor. /* MPC551x or MPC563x: Mod.PSR[4].R = 2.UCDIS.GPRE= 11.B. 2007.1 Oct 1 2004 Steve Mihalik */ Rev 1.CPR_PRC0. MMU not initialized.MCR.CCR.*/ /* MPC555x: Modulus Counter (MC) */ EMIOS.FRZ = 1.MCR. r3. /* Interrupt Vector Prefix value from link file*/ int emiosCh0Ctr = 0.B.renamed SWirq7Ctr to SWirq4Ctr for consistency */ Rev 1. /* MPC555x: Lower INTC's current priority */ asm(" wrteei 1").CH[0].CH[0].Made i volatile (to get fewer Nexus msgs in loop)*/ Jul 17 2007 SM . Rev.2006 S.CH[0]. Counter Buffered (MCB*/ /*EMIOS.FEN=1.CCR..R = 1. used relevant names */ for MPC551x bit fields & registers.CH[0].CCR.1 Aug 12 1006 SM .CH[0].CPR. /* Enable eMIOS clock */ EMIOS.FREN = 1.B.CADR.CCR.M.BSL = 0x3.B. must be done by debug scripts or BAM */ 2.h" /* Use proper include file such as mpc5510. Inc. /*Enable prescaler.B.c file main.MODE = 0x50. /* Enable stopping channels when in debug mode */ /* Following for MPC551x only: */ /*EMIOS.h */ extern uint32_t __IVPR_VALUE.R = 999. must be done by debug scripts or in a crt0 type file */ 3.MCR. /* Enable global time base */ EMIOS.Passed IVPR value from link file. /* Counter for eMIOS channel 0 interrupts */ int SWirq4Ctr = 0.B. 4 Freescale Semiconductor 41 .CH[0]. /* MPC551x: Raise eMIOS chan 0 IRQ priority = 1 */ INTC.B.CH[0].MODE = 0x10. /* Period will be 999+1=1000 channel clocks */ /* Use one of the following two lines for mode:*/ /*(Note: MCB mode is not in all MPC555x devices)*/ EMIOS.R = 0. */ /* MPC555x: Raise eMIOS chan 0 IRQ priority = 1 */ EMIOS. uses default divide by 1*/ EMIOS. invoked SW interrupt*/ on even count eMIOS Ch 0 ISRs. /* MPC555x: initialize for HW vector mode */ } void initEMIOS(void) { EMIOS.B. /* Flag enables interrupt */ } void initSwIrq4(void) { INTC. /* Divide sysclk by (11+1) for eMIOS clock */ EMIOS.h or mpc5554.R = 1. /* /* MPC551x Proc'r 0: Lower INTC's current priority*/ INTC.PRI = 0.UCPREN = 1. */ /* MPC551x: Proc'r 0: initialize for HW vector mode*/ INTC.CCR.B. Cache is not used */ #include "mpc563m.3 5. /* Enable external interrupts */ } Qorivva Simple Cookbook. __IVPR_VALUE@h ori r3.PSR[51].PRI = 0.0 May 19.MCR.c .1 /* /* /* /* /* /* /* /* /* /* /* /* /* Code main.B. /* Use internal counter */ EMIOS.3. SRAM not initialized.GTBE = 1.MCR. /*Freeze channel registers when in debug mode*/ EMIOS.HVEN = 1.CCR.B.B.MCR. All Rights Reserved */ Rev 0./* Software interrupt 4 IRQ priority = 2 */ } void enableIrq(void) { /* Use one of the following two lines: */ /*INTC.5. changed timeout to 1 msec*/ and changed EMIOS_MCR[PRE] & EMIOS Chan 0 A Register values */ Notes: */ 1. /* Counter for software interrupt 4 */ asm void initIrqVectors(void) { lis r3.GPREN = 1.

/* then nvoke software interrupt 4 */ } EMIOS. } /* Increment interrupt counter */ /* Clear channel's flag */ Qorivva Simple Cookbook.B. while (1) { i++. initIrqVectors(). enableIrq(). priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void emiosCh0ISR(void) { emiosCh0Ctr++. 4 42 Freescale Semiconductor .SSCIR[4]. initSwIrq4().CSR. INTC.FLAG=1. initEMIOS(). Rev.SSCIR[4]. /* Clear channel's flag */ } void SwIrq4ISR(void) { SWirq4Ctr++. /* Increment interrupt counter */ if ((emiosCh0Ctr & 1)==0) { /* If emiosCh0Ctr is even*/ INTC. initINTC(). } /* Dummy idle counter */ /* /* /* /* /* Initialize exceptions: only need to load IVPR */ Initialize INTC for hardware vector mode */ Initialize eMIOS channel 0 for 1kHz IRQ.R = 1.void main (void) { vuint32_t i = 0.R = 2.CH[0].

0xfff48018 # MPC551x: Proc'r 0 End Of Interrupt Reg. 4 Freescale Semiconductor 43 . addr. addr. or 80 bytes) # ************* ______________ # 0x4C * GPR12 * ^ # 0x48 * GPR11 * | # 0x44 * GPR10 * | # 0x40 * GPR9 * | # 0x3C * GPR8 * | # 0x38 * GPR7 * GPRs (32 bit) # 0x34 * GPR6 * | # 0x30 * GPR5 * | # 0x2C * GPR4 * | # 0x28 * GPR3 * | # 0x24 * GPR0 * ___v__________ # 0x20 * CR * __CR__________ # 0x1C * XER * ^ # 0x18 * CTR * | # 0x14 * LR * locals & padding for 16 B alignment # 0x10 * SRR1 * | # 0x0C * SRR0 * | # 0x08 * padding * ___v__________ # 0x04 * resvd.extern changes for CodeWarrior 1. Inc. added new 551x EOIR Rev 1.LR * Reserved for calling function # 0x00 * SP * Backchain (same as gpr1 in GPRs) # ************* . 2004 SM .3.4 Aug 30 2007 SM .3 Jul 6. All rights reserved # STACK FRAME DESIGN: Depth: 20 words (0xA0.Moved isr_hw_bracnh_table to new file.2 # # # # # # # # handlers.5..INTC hardware vector mode example Description: Creates prolog.text directive Copyright Freescale Semiconductor.0xfff48018 # MPC555x: End Of Interrupt Reg. epilog for C ISR and enables nested interrupts Rev 1.s . .globl SwIrq4Handler . 2007.extern SwIrq4ISR . Rev. 2007 SM .5 Rev 1. 2005 SM .section & . .equINTC_EOIR_PRC0. 2004 S Mihalik Rev 1.globl emiosCh0Handler .1 Aug 2.2 Jul 18.org.delayed writing to EOIR until after EE is disabled Rev 1. .text Qorivva Simple Cookbook.s file handlers.equINTC_EOIR.0 Jan 5.Added .extern emiosCh0ISR .

0x44 (r1) lwz r11.emiosCh0Handler: stwu stw mfsrr0 stw mfsrr1 stw wrteei stw stw stw stw stw stw stw stw stw stw mfcr stw mfxer stw mfctr stw mflr stw bl r1. 0x18 (r1) # Restore CTR mtctr r3 lwz r3. 0x30 (r1) lwz r6. -0x50 (r1) r3. r3 r3. 0x0C (r1) # Restore SRR0 mtsrr0 r3 lwz r3. r0. 0x24 (r1) # Restore other gprs except working registers lwz r5. r10. 0x28 (r1) addi r1. r3 r3. INTC_EOIR@ha# MPC555x: Load upper half of EIOR address to r3 li r4. 4 44 Freescale Semiconductor . r6. r1. r7. INTC_EOIR@l(r3)# MPC555x: Write 0 to INTC_EOIR lwz r3. r3 r3. 0x48 (r1) lwz r12. r5. 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x24 (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) 0x28 (r1) 0x0C (r1) 0x10 (r1) # PROLOGUE # Create stack frame and store back chain # Store a working register # Store SRR0:1 (must be done before enabling EE) # Set MSR[EE]=1 # Store rest of gprs 0x20 (r1) 0x1C (r1) 0x18 (r1) 0x14 (r1) # Store CR # Store XER # Store CTR # Store LR # EPILOGUE lwz r3. 0 wrteei 0 # Disable interrupts for rest of handler # The following line is for MPC551x: # stw r4. INTC_EOIR_PRC0@ha# MPC551x: Load upper half of proc'r 0 EIOR addr to r3 # The following line is for the MPC555x: lis r3. 0x14 (r1) # Restore LR mtlr r3 lwz r3. r11. r3 lwz r0. Rev. 0x40 (r1) lwz r10. r3 r3. 0x38 (r1) lwz r8. 0x1C (r1) # Restore XER mtxer r3 lwz r3. 0x50 # Delete stack frame rfi # End of Interrupt emiosCh0ISR Qorivva Simple Cookbook. 0x10 (r1) # Restore SRR1 mtsrr1 r3 lwz r4. 0x2C (r1) # Restore working registers lwz r3. INTC_EOIR_PRC0@l(r3)# MPC551x: Write 0 to proc'r 0 INTC_EOIR # The following line is for MPC555x: stw r4. 0x34 (r1) lwz r7. r3 r3. 0x3C (r1) lwz r9. r8. 0x20 (r1) # Restore CR mtcrf 0xff. 1 r12. 0x4C (r1) mbar 0 # Ensure store to clear flag bit has completed # The following line is for the MPC551x: # lis r3. r3 r3. r9. r4.

0x48 (r1) lwz r12. 0x34 (r1) lwz r7. r3 r3. r9. 4 Freescale Semiconductor 45 . 0x28 (r1) addi r1. 0x0C (r1) # Restore SRR0 mtsrr0 r3 lwz r3. 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x24 (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) 0x28 (r1) 0x0C (r1) 0x10 (r1) # PROLOGUE # Create stack frame and store back chain # Store a working register # Store SRR0:1 (must be done before enabling EE) # Set MSR[EE]=1 # Store rest of gprs 0x20 (r1) 0x1C (r1) 0x18 (r1) 0x14 (r1) # Store CR # Store XER # Store CTR # Store LR # EPILOGUE lwz r3. r10. INTC_EOIR_PRC0@ha# MPC551x: Load upper half of proc'r 0 EIOR addr to r3 # The following line is for the MPC555x: lis r3. r5. 0x30 (r1) lwz r6. 0 wrteei 0 # Disable interrupts for rest of handler # The following line is for MPC551x: # stw r4. 0x1C (r1) # Restore XER mtxer r3 lwz r3. r3 lwz r0. Rev. INTC_EOIR@l(r3)# MPC555x: Write 0 to INTC_EOIR lwz r3. r0. r3 r3. r11. r7. r4. 0x14 (r1) # Restore LR mtlr r3 lwz r3. 0x20 (r1) # Restore CR mtcrf 0xff. 0x50 # Delete stack frame rfi # End of Interrupt SwIrq4ISR Qorivva Simple Cookbook. 0x2C (r1) # Restore working registers lwz r3. r8. 0x18 (r1) # Restore CTR mtctr r3 lwz r3. 0x3C (r1) lwz r9. r6. 0x24 (r1) # Restore other gprs except working registers lwz r5. 0x40 (r1) lwz r10. 0x38 (r1) lwz r8. 0x10 (r1) # Restore SRR1 mtsrr1 r3 lwz r4. INTC_EOIR_PRC0@l(r3)# MPC551x: Write 0 to proc'r 0 INTC_EOIR # The following line is for MPC555x: stw r4. r3 r3. 0x44 (r1) lwz r11. r3 r3. -0x50 (r1) r3. r1. r3 r3.SwIrq4Handler: stwu stw mfsrr0 stw mfsrr1 stw wrteei stw stw stw stw stw stw stw stw stw stw mfcr stw mfxer stw mfctr stw mflr stw bl r1. INTC_EOIR@ha# MPC555x: Load upper half of EIOR address to r3 li r4. r3 r3. 0x4C (r1) mbar 0 # Ensure store to clear flag bit has completed # The following line is for the MPC551x: # lis r3. 1 r12.

All rights reserved .intc_hw_branch_table . Rev. 2007 S Mihalik Rev 1.0 Jul 2.align ALIGN_OFFSET . for other vectors Qorivva Simple Cookbook.align ALIGN_OFFSET hw_vect59: b hw_vect59 #INTC HW vector 59 .INTC hardware vector mode branch table example Description: INTC vector branch table when using INTC in HW vector mode **** NOTE **** ONLY 100 EXAMPLE VECTORS ARE IMPLEMENTED HERE Rev 1.align ALIGN_OFFSET hw_vect53: b hw_vect53 #INTC HW vector 53 .extern emiosCh0Handler #. Inc.s (partial) file (MPC555x shown) intc_hw_branch_table. emiosCh0Handler ..align ALIGN_OFFSET hw_vect55: b hw_vect55 #INTC HW vector 55 .align ALIGN_OFFSET # Use 1 of the next 2 lines #hw_vect58: b emiosCh0Handler #MPC551x: eMIOS Ch 0 hw_vect58: b hw_vect58 #INTC HW vector 58 . 16 # MPC555x: 16 byte branch alignments (Diab. etc. 4 46 Freescale Semiconductor .equ ALIGN_OFFSET..1 Aug 30 1007 SM .align ALIGN_OFFSET hw_vect54: b hw_vect54 #INTC HW vector 54 .align ALIGN_OFFSET hw_vect5: b hw_vect5 #INTC HW vector 5 . for other vectors hw_vect50: b hw_vect50 #INTC HW vector 50 .5. CodeWarrior 16) IntcHandlerBranchTable: # Only 100 example vectors are implemented here # MPC555x: This table must have 64 KB alignment # MPC551x: Requires 2 KB alignment after 4KB boundary . CodeWarrior 4) .Made SwIrq4Handler.equ ALIGN_OFFSET.s . etc.extern SwIrq4Handler . 2007.align ALIGN_OFFSET hw_vect0: b hw_vect0 #INTC HW vector 0 .align ALIGN_OFFSET hw_vect52: b hw_vect52 #INTC HW vector 52 . GHS use 4.align ALIGN_OFFSET hw_vect57: b hw_vect57 #INTC HW vector 57 . GHS use 2.align ALIGN_OFFSET hw_vect4: b SwIrq4Handler # SW IRQ 4 .section ..align ALIGN_OFFSET hw_vect1: b hw_vect1 #INTC HW vector 1 .align ALIGN_OFFSET # Use 1 of the next 2 lines hw_vect51: b emiosCh0Handler #MPC555x: eMIOS Ch 0 #hw_vect51: b hw_vect51 #INTC HW vector 51 ..3.extern Copyright Freescale Semiconductor. 4 # MPC551x: 4 byte branch alignments (Diab.align ALIGN_OFFSET hw_vect2: b hw_vect2 #INTC HW vector 2 .3 # # # # # # intc_hw_branch_table.align ALIGN_OFFSET hw_vect3: b hw_vect3 #INTC HW vector 3 .align ALIGN_OFFSET hw_vect56: b hw_vect56 #INTC HW vector 56 .

ivor_branch_table . All Rights Reserved Rev 1. GHS.align SIXTEEN_BYTES IVOR12trap: b IVOR12trap # IVOR 12 interrupt handler .0 Jul 6 2007 S Mihalik .align SIXTEEN_BYTES IVOR3trap: b IVOR3trap # IVOR 3 interrupt handler .align SIXTEEN_BYTES IVOR4trap: b IVOR4trap # IVOR 4 interrupt handler .for use with MPC551x only Description: Branch table for 16 MPC551x core interrupts Copyright Freescale 2007. Rev.align SIXTEEN_BYTES IVOR8trap: b IVOR8trap # IVOR 8 interrupt handler .5.section .align SIXTEEN_BYTES IVOR5trap: b IVOR5trap # IVOR 5 interrupt handler .align SIXTEEN_BYTES IVOR11trap: b IVOR11trap # IVOR 11 interrupt handler .align SIXTEEN_BYTES IVOR13trap: b IVOR13trap # IVOR 13 interrupt handler .4 # # # # ivor_branch_table.equ SIXTEEN_BYTES.s .3.s file (MPC551x only) ivor_branch_table.align SIXTEEN_BYTES IVOR14trap: b IVOR14trap # IVOR 14 interrupt handler .align SIXTEEN_BYTES IVOR9trap: b IVOR9trap # IVOR 9 interrupt handler .align SIXTEEN_BYTES IVOR15trap: b IVOR15trap # IVOR15 interrupt handler IVOR0trap: Qorivva Simple Cookbook.align SIXTEEN_BYTES IVOR2trap: b IVOR2trap # IVOR 2 interrupt handler . Cygnus use 16 .align SIXTEEN_BYTES IVOR10trap: b IVORtrap # IVOR 10 interrupt handler . 4 Freescale Semiconductor 47 .align SIXTEEN_BYTES IVOR7trap: b IVOR7trap # IVOR 7 interrupt handler .align SIXTEEN_BYTES b IVOR0trap # IVOR 0 interrupt handler . 16 # 16 byte alignment required for table entries # Diab compiler uses value of 4 (2**4=16) # CodeWarrior.align SIXTEEN_BYTES IVOR1trap: b IVOR1trap # IVOR 1 interrupt handler .align SIXTEEN_BYTES IVOR6trap: b IVOR6trap # IVOR 6 interrupt handler .Initial version .

Crystal 8 MHz Clocks and PLL SIU_SYSCLK (MPC551x only) Divide sysclk by 1 for PIT PIT PIT 1 Timer Load Value PIT 1 Timer Interrupt Request to INTC Interrupt Request to INTC INTC (Software Vector Mode) sysclk set to 64 MHz Software settable interrupt request 4 (set in PIT interrupt service routine) MPC5500 / MPC5600 Common INTC interrupt request to CPU core Figure 13. so the 1 PIT ISR is preempted by the software interrupt. An alternate method is to put a breakpoint in the beginning of the service routine and to read the count register.1 INTC: Software Vector Mode. additional software is needed to initialize branch target buffers. in its interrupt service routine (ISR). are: • VLE instructions are used (not available in MPC5553. MPC5554) • Prologue/epilogue uses VLE assembly instructions • Programmable Interrupt Timer (PIT) is used as the interrupt timer (note: PIT is not available in some MPC55xx devices. invoke a second interrupt every other time. The SPE will not be used. 4 48 Freescale Semiconductor .6 6. VLE Instructions Example Qorivva Simple Cookbook. Both ISRs will have a counter. Software Vector Mode. Rev. as shown in other examples in this application note. this program provides two interrupts that show nesting. so its accumulator will not be saved in the stack frame of the interrupt handler. Exercise: Write a third interrupt handler which uses a software interrupt of a higher priority than the others. VLE Instructions Description Task: Using the Interrupt Controller (INTC) in software vector mode. The ISRs will be written in C. The interrupt handler will re-enable interrupts and later. Classic Instructions example. The main differences from the other INTC SW Mode. so the appropriate registers will be saved and restored in the handler. Invoke this new software interrupt from one of the other ISRs. but an eMIOS channel could be used) • The timer will count at the system clock rate (causing an interrupt at a count value of 0) • System clock is set to 64 MHz A relative interrupt response can be measured by reading the PIT count value in the first line of the interrupt service routine. The software interrupt will have a higher priority. and enable cache (if implemented). configure flash. NOTE: to get a true interrupt performance measurement. This will provide an approximate 1 ms task (ISR) from the PIT and an approximate 2 ms task (ISR) from the software interrupt.

4 Freescale Semiconductor 49 . either INTC_ACK_PRC0 (for e200z1) or INTC_IACK_PRC1 (for e200z0). as defined in the INTC_PSR for that vector. PIT 1 ISR addr .... IntcIsrVectors...c file main { init Modes (MPC56xxBPS only) init IVPR. IVOR4 (MPC551x only) init INTC init PIT1 init SW 4 interrupt enable interrupts wait forever } Pit1ISR { increment counter if odd count.. MPC56xxPBS Program Flow Qorivva Simple Cookbook. Rev.c file ISR Vector Table: . For MPC551x. there can be a different ISR vector table for each core because each core has its own special purpose register. MPC551x. External Input interrupt taken vector to IVPR0:19 + 4(for IVOR4)16 bytes ivor_branch_table_vle. IVPR. This example only uses the e200z1 core. main. . in this example only one processor is selected for interrupts: processor 0 (e200z1).2 Design The overall program flow for MPC551x and MPC56xxB/P/S is shown below. re-enable interrupts save registers branch to fetched ISR vector epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return Figure 14. it is routed to either or both cores..s or handlers_new_vle.. that is. For MPC551x..s file IVOR4Handler: prologue: save SRR0:1.. When an interrupt occurs.. fetch ISR vector. SW IRQ 4 ISR addr .6. The selection is defined in INTC_PSR for each enabled interrupt — in this case PIT 1 and software interrupt 4..s file IVOR Branch Table e_b IVOR0trap e_b IVOR1trap ... invoke SW 4 IRQ clear flag } SwIrq4ISR { increment counter clear flag } handlers_VLE. . e_b IVOR4Handler . The Vector Table Base Address is defined in each core’s INTC_ACKR.

fetch ISR vector.s file IntcIsrVectors.The overall program flow for MPC555x is shown below.s or handlers_new_vle.... .. External Input interrupt taken handlers_vle..c file main { init IVPR. PIT 1 ISR addr . 4 50 Freescale Semiconductor .. vector to IVPR0:15 + IVOR416:27 main. .c file ISR Vector Table: . re-enable interrupts save registers branch to fetched ISR vector epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return Figure 15.. invoke SW 4 IRQ clear flag } SwIrq4ISR { increment counter clear flag } IVOR4Handler: prologue: save SRR0:1. MPC555x Program Flow Qorivva Simple Cookbook. SW IRQ 4 ISR addr . IVOR4 init INTC init PIT1 init SW 4 interrupt enable interrupts wait forever } Pit1ISR { increment counter if odd count.... Rev.

VLE Example Low power modes are not used in example. The following table summarizes the mode settings used. enabling low power. the mode is switched in this example from the default mode (DRUN) to RUN0 mode. Mode Configurations for MPC56xxB/P/S INTC SW Mode. Register Clock Sources Mode Config. Config. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral PIT.1 Modes Use Summary (MPC56xxB/P/S only) Mode Transition is required for changing mode entry registers. PeriPeri. Mode I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 (default) RUN0 ME_RUN0_MC 0x001F 007D 16 MHz IRC PLL0 Normal Normal Normal Normal On On Off Off Other modes are not used in example Peripherals also have configurations to gate clocks on and off. Rev. Hence even enabling the crystal oscillator to be active in the default mode (DRUN) requires enabling the crystal oscillator in appropriate mode configuration register (ME_xxxx_MC) then initiating a mode transition. Table 22. Register Value sysclk Selection PLL1 16MHz XOSC0 PLL0 (MPC IRC 56xxP/S only) On On Off On Off On Off Off Memory Power Mode Data Flash Code Flash Main Voltage Reg. Settings Mode Config. # 92 Other peripheral configurations are not used in example Qorivva Simple Cookbook. Enabled Modes pheral Config. VLE Instructions Example Modes are enabled in ME_ME Register.6. Table 21.2. RTI PCTL Reg. The following table summarizes the peripheral configurations used in this example. After reset. Peripheral Configurations for MPC56xxB/P/S INTC SW Vector Mode. 4 Freescale Semiconductor 51 .

) Configure RUN0 Mode: • I/O Output power-down: no safe gating (default) • Main Voltage regulator is on (default) • Data. RUN0 = 1 Modes And Clock Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: (MPC • 8 MHz xtal: FMPLL[0]_CR=0x02400100 56xxPBS • 40 MHz xtal: FMPLL[0]_CR=0x12400100 only) (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value. then clearing WEN (MPC56xxBPS only) PDO=0 MVRON=1 DFLAON. See PLL example. Rev. running from PLL disable Watchdog Disable watchdog by writing keys to Status Register. CFLAON=3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0 = 1 RUN_CFG = 0 TARGET_MODE = RUN0 S_TRANS - &SwIrq4ISR &Pit1ISR ME_ME = 0x0000 001D 8 MHz Crystal: CGM_ FMPLL[0]_CR =0x02400100 - ME_ RUN0_MC = 0x001F 0070 ME_RUN_PC1 = 0000 0010 ME_PCTL92 = 0x01 ME_MCTL =0x4000 5AF0. code flash in normal mode (default) • PLL0 is switched on • Crystal oscillator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk MPC56xxB/S: • Peri. =0x4000 A50F wait ME_GS [S_TRANS] = 0 verify 4 = ME_GS [CURRENTMODE] See PLL Initialization example (See example PLL: Initializing System Clock) - Qorivva Simple Cookbook. 4 52 Freescale Semiconductor .Table 23. VLE Instructions Pseudo Code Step Variable Init Counter for PIT 1 interrupts Counter for software 4 interrupts Relevant Bit Fields MPC551x MPC555x int Pit1Ctr = 0 int SWirq4Ctr = 0 MPC56xxBPS Table Init Load INTC’s ISR vector table with addresses for: • SWirq4ISR: INTC vector #4 • Pit1ISR: INTC vector: MPC551x: #149. RTI: select ME_RUN_PC1 Initiate software mode transition to RUN0 mode • Mode & key.1: run in DRUN mode only Assign peripheral configuration to peripherals: • PIT. Initialization: INTC in Software Vector Mode. MPC563x: #302. Config. MPC56xxB/P/S: #60 init Enable desired modes DRUN=1. then mode & inverted key • Wait for transition to complete • Verify current mode is RUN0 CURRENTMODE init Sysclk Initialize sysclk to 64 MHz.

56xxPBS)=1 0x0000 0002 PIT_TIMER1_ TIE1 or TIE = 1 PIT_INTEN = TCTRL = Enable PIT 1 to request IRQ 0x0000 0002 0x00000003 PIT_INTSEL = MPC551x: Assign PIT 1 flag for IRQ instead ISEL = 1 0x0000 0002 of DMA Configure PIT1 interrupts: • MPC551x: Select processor 0 (e200z1) • Select priority 1 init SwIrq4 enable ExtIrq PRC_SEL= 0 (z1) PRI = 1 INTC_PSR [149] = 0x01 INTC_PSR [302] = 0x01 PIT_CH1_ TCTRL = 0x0000 0003 INTC_PSR [60] = 0x01 Software Interrupt 4: • Raise priority to 2 PRI = 2 • MPC551x: Select processor(s) to interrupt PRC_SEL=0 (e200z1) Enable recognition of requests to INTC by PRI = 0 lowering the INTC’s current priority to 0 from default of 15 Enable external interrupts: set MSR[EE] = 1 INTC_CPR _PRC0[PRI]= 0 INTC_PSR[4] = 0x02 INTC_CPR [PRI]= 0 wrteei 1 while 1 waitloop wait forever Qorivva Simple Cookbook. 56xxBPS: Freeze in debug mode Load a start count values for 64 MHz sysclk (PITs count down from value at sysclk rate) • PIT 1 Timeout = 64M/(64M sysclk/sec)=1ms Enable PIT 1 timer to count (counts down) MDIS = 0 FRZ = 1 PIT_TVAL1 = 64. e200z1.000 PIT_TIMER1_ LDVAL1 = 64. MPC555x: Initialize external input interrupt offset to the lower half of IVROR4 handler’s address Initialize INTC: • Configure for software vector mode (HVEN=0) • Keep vector offset (VTES) at 4 bytes (MPC551x note: only proc’r 0. Initialization: INTC in Software Vector Mode.Table 23.000 PIT_CH1_ LDVAL = 64. is used here) init PIT HVEN_PRC0=0(551x) VTES_PRC0=0(551x) HVEN = 0 (MPC555x) VTES = 0 (MPC555x) Relevant Bit Fields MPC551x MPC555x MPC56xxBPS spr IVPR =__IVPR_VALUE spr IVOR4 = IVOR4Handler @l - init INTC INTC_MCR = 0x0 VTBA = passed from linker INTC_IACKR _PRC 0 = __IACKR_ VTBA_VALUE SIU_SYSCLK [LPCLKDIV1] =0 PIT_CTRL = 0x0000 0000 INTC_IACKR = __IACKR_ VTBA_VALUE PIT_PITMCR = 0x0000 0001 MPC551x: Init system clock divider for PIT. IIC) Global controls: • Enable module • MPC555x. Rev. VLE Instructions (continued) Pseudo Code Step init Irq Vectors Load the common interrupt vector prefix to spr IVPR. e200z1 is used) Initialize ISR vector table base address per link file (MPC551x note: only proc’r 0. 4 Freescale Semiconductor 53 .000 PIT_PITEN = PEN1(551x) = 1 or TEN(555x. LPCLKDIV1 = 0 RTI to divide by 1 (also applies to other Group (default) 1 peripherals of eSCI A.

Rev.6. Stack Frame for INTC Interrupt Handler Stack Frame Area 32 bit GPRs r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r0 CR locals and padding CR XER CTR LR SRR1 SRR0 padding LR area back chain LR placeholder r1 Register Location in Stack sp + 0x4C sp + 0x48 sp + 0x44 sp + 0x40 sp + 0x3C sp + 0x38 sp + 0x34 sp + 0x30 sp + 0x2C sp + 0x28 sp + 0x24 sp + 0x20 sp + 0x1C sp + 0x18 sp + 0x14 sp + 0x10 sp + 0x0C sp + 0x08 sp + 0x04 sp Qorivva Simple Cookbook. 4 54 Freescale Semiconductor .2.2 Interrupt Handler Table 24.

Rev. sp. r3 registers to stack frame r3 = INTC_IACKR_PRC0 wrteei 1 se_lwz r3. 0x50 se_rfi Qorivva Simple Cookbook.Table 25. IVOR4 Interrupt Handler (INTC in Software Vector Mode. 4 Freescale Semiconductor 55 . saving return address EE = 1 e_stwu sp. MPC551x does not require alignment because it is the destination of a branch instruction. VLE Instructions) (MPC555x: Must be 16-byte aligned and within 64 KB of address in IVPR. -0x50 (sp) store SRR0:1. 0x0 (r3) mtLR r3 store other registers to stack frame se_blrl load most registers from stack frame mbar EE = 0 wrteei 0 write 0 to INTC_EOIR_PRC0 write 0 to INTC_EOIR r3 = INTC_IACKR epilog Restore registers from stack frame except SRR0:1 and two working registers Ensure interrupt flag in ISR has completed clearing before writing to INTC_EOIR Disable external interrupts by clearing MSR[EE] Restore former INTC’s Current Priority Restore SRR0:1 and working registers Restore stack frame space Return restore SRR0:1. working registers from stack frame e_add16i sp.) Relevant Bit Fields Pseudo Code MPC551x MPC555x MPC56xxBPS Step prolog Create stack frame Save SRR0:1 because nested interrupts will be allowed Read pointer into ISR Vector Table Re-enable external interrupts by setting MSR[EE] Read ISR address from ISR Vector Table and store into LR Save other appropriate registers for C ISR Branch to ISR.

6. Rev.3 Interrupt Service Routines (ISRs) Table 26.2. ISR for PIT1 Step Relevant Bit Fields Pseudo Code MPC551x MPC555x Pit1Ctr ++ SET=1 if ((Pit1Ctr&1) ==0). invoke Software Interrupt 4 Clear Pit1Ctr interrupt flag by writing 1 to it TIF1 = 1 or PIT_PITFLG[TIF1] PIT_TFLG1[TIF] PIT_CH1_TFLG[TIF] TIF = 1 =1 =1 =1 Table 27. 4 56 Freescale Semiconductor . INTC_SSCIR[4] = 2 MPC56xxB/P/S Pit1ISR Increment Pit1Ctr If Pit1Ctr is even. ISR for Software Interrupt 4 Step swIRQ4ISR Increment SWirq4ctr Clear Software IRQ 4 CLR=1 Relevant Bit Fields Pseudo Code SWirq4ctr++ INTC_SSCIR[4] = 1 Qorivva Simple Cookbook.

ESYNCR1.c (MPC551x shown with 8 MHz crystal) main. */ /* 12MHz xtal: CLKCFG=PLL.B.LOCK != 1) {}. */ /* 12MHz xtal: ERFD to initial value of 5 */ /*FMPLL.R = 0. __IVPR_VALUE@l mtivpr r3 } /* IVPR value is passed from link file */ void initINTC(void) { INTC. /* MPC551x: ISR table base*/ } void initPIT(void) { SIU. */ /* 12MHz xtal: ERFD change for 64 MHz sysclk */ SIU. In.PITINTEN. SWT.B. /* Enable external oscillator */ while (FMPLL. /* Clear watchdog enable (WEN) */ } asm void initIrqVectors(void) { lis r3. 4 Freescale Semiconductor 57 .3. /* MPC551x Proc'r 0: default vector table 4B offsets */ INTC.R = 0x00000006.R = 0x00000007.Software vector mode program using C isr */ Feb 03 2009 SM . EPREDIV=2. /* Wait for PLL to LOCK */ /* Use 1 of the next 2 lines: */ FMPLL. not DMA req. PIT. /* Counter for PIT 1 interrupts */ uint32_t SWirq4Ctr = 0.R = 0x00000003. INTC. EMFD=0x20 */ /*FMPLL.SR. /* 8MHz xtal: ERFD to initial value of 7 */ FMPLL. EPREDIV=0.MCR. __IVPR_VALUE@h ori r3.R = 0x00000005. /* 8MHz xtal: ERFD change for 64 MHz sysclk */ /*FMPLL.PSR[4]. } /* /* /* /* /* /* /* Divide sysclk by 1 for Group 1 modules */ Ensure PIT is not disbaled */ Timeout= 64K sysclks x 1sec/64M sysclks= 1 ms */ Enable PIT 1 flag to request INTC or DMA */ Assign PIT 1 flag to select IRQ.1. /* Select PLL for sysclk */ } void disableWatchdog(void) { SWT.c 2009 All rights reserved.R = 0xF0000020.B. EMFD=0x30*/ CRP. r3. PIT. PIT.MCR.R = 0xF0020030.B.PITEN.PITINTSEL.h */ extern IVOR4Handler().R = 0x01.PEN1 = 1.B. */ #include "mpc5510.1 /* /* /* /* Code main. /* MPC551x Proc'r 0: initialize for SW vector mode*/ INTC.PITCTRL.ESYNCR2.h or mpc5554.h" /* Use proper include file such as mpc5510.SYSCLK.R = 2.PSR[149].ESYNCR2.Based on AN2865 INTC Software Vector Mode example*/ Aug 12 2009 SM .VTES_PRC0 = 0.3 6.R = 0x00000005.1 6.HVEN_PRC0 = 0. PIT.TLVAL[1]./* Software interrupt 4 IRQ priority = 2 */ } Qorivva Simple Cookbook.LPCLKDIV1 = 0.R = 64000.SR. */ Start PIT counting */ PIT 1 interrupt selects proc'r 0 & priority 1 */ void initSwIrq4(void) { INTC./* Counter for software interrupt 4 */ void initSysclk(void) { /* Use 2 of the next 4 lines: */ FMPLL.B.SYNSR.ESYNCR2.IACKR_PRC0.B. /* Interrupt Vector Prefix value from link file*/ extern const vuint32_t IntcIsrVectorTable[].SYSCLKSEL = 2.Changed initial ERFD value.R = 0x00000002.c . PIT.R = 0x0000c520. uint32_t Pit1Ctr = 0.R = 0x8000010A. extern uint32_t __IVPR_VALUE. /* Write keys to clear soft lock bit */ SWT. Rev.XOSCEN = 1.6.R = 0x0000d928.c files main.ESYNCR1.CLKSRC.R = (uint32_t) &IntcIsrVectorTable[0].CR.ESYNCR2.3.SYSCLK. added 12MHz crystal numbers */ Copyright Freescale Semiconductor. /* 8MHz xtal: CLKCFG=PLL.

PITFLG. 4 58 Freescale Semiconductor .SSCIR[4].CPR_PRC0. initINTC(). } void main (void) { vuint32_t i = 0. } /* MPC551x Proc'r 0: Lower INTC's current priority */ /* Enable external interrupts */ /* Dummy idle counter */ /* /* /* /* /* /* Set sysclk to 64 MHz */ Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize PIT1 for 1kHz IRQ. Rev. while (1) { i++.R = 1.B. if ((Pit1Ctr & 1)==0) { INTC.B. initSysclk(). } void SwIrq4ISR(void) { SWirq4Ctr++.TIF1 = 1. initPIT().void enableIrq(void) { INTC.SSCIR[4]. } PIT.R = 2. INTC. initSwIrq4(). asm(" wrteei 1"). } /* Increment interrupt counter */ /* If PIT1Ctr is even*/ /* then invoke software interrupt 4 */ /* Clear PIT 1 flag by writing 1 */ /* Increment interrupt counter */ /* Clear channel's flag */ Qorivva Simple Cookbook. initIrqVectors(). priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void Pit1ISR(void) { Pit1Ctr++. enableIrq().PRI = 0.

TIMER[1].6.c .LDVAL.SSCIR[4].ESYNCR1. /* Software interrupt 4 IRQ priority = 2 */ } void enableIrq(void) { INTC.B.B. initSwIrq4().SYNCR. */ #include "mpc563m.1.TIMER[1].B.2 main.TCTRL. IVOR4Handler@l /* IVOR4 = lower half of handler address */ mtivor4r3 } void initINTC(void) { INTC. } /* Dummy idle counter */ /* /* /* /* /* /* Set sysclk to 64 MHz */ Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize PIT1 for 1kHz IRQ.c 2009 All rights reserved. In. /* Increment interrupt counter */ if ((Pit1Ctr & 1)==0) { /* If PIT1Ctr is even*/ INTC. /* Timeout= 64K sysclks x 1sec/64M sysclks= 1 ms */ PIT. while (1) { i++.IACKR. /* Use default vector table 4B offsets */ INTC.B.R = 1.B. initPIT(). /* Initial values: PREDIV=1.B.c (MPC555x: MPC563xM shown with 8 MHz crystal) /* main.h or mpc5554. /* PIT 1 interrupt has priority 1 */ } void initSwIrq4(void) { INTC.PSR[4]. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r3. /* Clear PIT 1 flag by writing 1 */ } void SwIrq4ISR(void) { SWirq4Ctr++.h */ extern IVOR4Handler(). 4 Freescale Semiconductor 59 . /* Enable external interrupts */ } void main (void) { vuint32_t i = 0. priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void Pit1ISR(void) { Pit1Ctr++.Based on AN2865 INTC Software Vector Mode example*/ /* Copyright Freescale Semiconductor. /* Initialize for SW vector mode */ INTC.SSCIR[4].R = 2. initINTC().CPR.HVEN = 0.MCR. RFD=1 */ while (FMPLL.VTES = 0.MCR.PSR[302]. MFD=12. /* Enable PIT module & freeze count during debug */ PIT.TIF = 1.R = 0x16080000.R=(uint32_t) &IntcIsrVectorTable[0]. /* Increment interrupt counter */ INTC.TFLG. /* Interrupt Vector Prefix value from link file*/ extern const vuint32_t IntcIsrVectorTable[]. /* Counter for software interrupt 4 */ void initSysclk(void) { /* Intialize sysclk to 64MHz for 8 MHz crystal*/ FMPLL.R = 64000. /* Counter for PIT 1 interrupts */ uint32_t SWirq4Ctr = 0.R = 0x1.3.R = 0x16000000. /* Clear channel's flag */ } Qorivva Simple Cookbook. initIrqVectors().SYNCR. extern uint32_t __IVPR_VALUE. __IVPR_VALUE@l mtivpr r3 li r3. initSysclk(). Rev.R = 0x00000001.CLKCFG = 0X7.PRI = 0.Software vector mode program using C isr */ /* Feb 03 2009 SM . /* Change clk to PLL normal mode from crystal */ FMPLL. /* INTC ISR table base */ } void initPIT(void) { PIT. r3. /* Lower INTC's current priority */ asm(" wrteei 1"). /* Start timer counting & freeze during debug */ INTC.h" /* Use proper include file such as mpc5510.LOCK != 1) {}. enableIrq().SYNSR. /* then nvoke software interrupt 4 */ } PIT. uint32_t Pit1Ctr = 0.TIMER[1].R = 2.R = 0x00000003.MCR. /* Wait for FMPLL to LOCK */ FMPLL. /* Final value for 64 MHz: RFD=0 */ } asm void initIrqVectors(void) { lis r3.

GS. RESET modes */ /* Initialize PLL before turning it on: */ CGM.SR. 2010. */ #include "56xxS_0204. /* Clear watchdog enable (WEN) */ } asm void initIrqVectors(void) { lis r3. /* Write keys to clear soft lock bit */ SWT.c . /* 8 MHz xtal: Set PLL0 to 64 MHz */ ME. /* Initialize for SW vector mode */ INTC.B.6. /* Enter RUN0 Mode & Inverted Key */ while (ME.modified initModesAndClks.R = 0x0000d928.B. SAFE. /* RUN0 cfg: 16MHzIRCON.MCR. /* Enable PIT and configure stop in debug mode */ PIT.MCR.CR. /* Timeout= 64K sysclks x 1sec/64M sysclks= 1 ms */ PIT.GS.RUN[0].Simplified code */ Mar 15 2010 SM .FMPLL[0]. Mihalik. /* INTC ISR table base */ } void initPIT(void) { PIT.PRI = 0. /* Counter for software interrupt 4 */ void initModesAndClock(void) { ME. extern uint32_t __IVPR_VALUE. /* Enable PIT1 interrupt & start PIT counting */ INTC. PCTL code */ Jul 03 2009 S Mihalik .PCTL[92].R = 64000.R = 2. RUN0. 2009.1.R = 0x0000001D.RUNPC[1].R = 0x000000003. All rights reserved.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void disableWatchdog(void) { SWT. RTI: select ME_RUN_PC[1] */ /* Mode Transition to enter RUN0 mode: */ ME. /* PIT.PSR[4].MCR.R = 0x40005AF0.3.CR.MPC56xxS shown with 8 MHz crystal) main.Simplifed by removing unneeded sysclk. uint32_t Pit1Ctr = 0.CH[1]. /* Counter for PIT 1 interrupts */ uint32_t SWirq4Ctr = 0.R = 0x001F0074.CPR. Rev.VTES = 0. /* PIT 1 interrupt vector with priority 1 */ } void initSwIrq4(void) { INTC.Software vector mode program using C isr */ Jan 15.R = (uint32_t) &IntcIsrVectorTable[0].OSC0ON. r3.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME. 2009 S.R = 0x01.R = 0x4000A50F.MER.TCTRL. /* Use default vector table 4B offsets */ INTC.Initial version based on previous AN2865 example */ May 22 2009 S.PLL0ON.B.R = 0x8000010A. Cfg.Mihalik. Inc.PSR[60]. } /* Software interrupt 4 IRQ priority = 2 */ /* Lower INTC's current priority */ /* Enable external interrupts */ Qorivva Simple Cookbook.syclk=PLL */ ME.c file (MPC56xxB/P/S .h" /* Use proper include file */ extern IVOR4Handler().HVEN = 0.IACKR. 1 settings: only run in RUN0 mode */ ME. } void enableIrq(void) { INTC. updated header */ Copyright Freescale Semiconductor. 4 60 Freescale Semiconductor .MCTL. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r3.CH[1].R = 0x00000010. SWT.B. /* Peri. /* Enable DRUN. /* Interrupt Vector Prefix vaue from link file*/ extern const vuint32_t IntcIsrVectorTable[]. __IVPR_VALUE@l mtivpr r3 } void initINTC(void) { INTC.R = 0x00000001.SR.MCTL.LDVAL.R = 0x0000c520.R = 0x01. asm(" wrteei 1"). /* Enter RUN0 Mode & Key */ ME.3 /* /* /* /* /* /* main.R = 0x02400100.B.

INTC. priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void Pit1ISR(void) { Pit1Ctr++. } /* /* /* /* /* /* /* /* Dummy idle counter */ MPC56xxP/B/S: Initialize mode entries. initIrqVectors(). 4 Freescale Semiconductor 61 .TIF = 1. while (1) { i++. initPIT().CH[1].SSCIR[4]. disableWatchdog().void main (void) { vuint32_t i = 0. initSwIrq4(). initINTC(). initModesAndClock(). Rev.R = 1. set sysclk=64 MHz*/ Disable watchdog */ Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize PIT1 for 1kHz IRQ. } /* Increment interrupt counter */ /* If PIT1Ctr is even*/ /* then nvoke software interrupt 4 */ /* CLear PIT 1 flag by writing 1 */ /* Increment interrupt counter */ /* Clear channel's flag */ Qorivva Simple Cookbook. if ((Pit1Ctr & 1)==0) { INTC.R = 2.B. } void SwIrq4ISR(void) { SWirq4Ctr++. enableIrq().TFLG.SSCIR[4]. } PIT.

4 Jan 22 2009 SM . 0x0(r3) 1 r4.equINTC_IACKR.0xfff48018 IVOR4Handler: prolog: e_stwu se_stw mfsrr0 se_stw mfsrr1 se_stw e_lis e_lwz # e_lis # e_lwz se_lwz wrteei se_stw se_mflr se_stw r1. 2007. 0xfff48010 .delayed writing to EOIR until after disabling EE in epilog Rev 1.2 # # # # # # # # # handlers_vle.align 16 # Align IVOR handlers on a 16 byte boundary for MPC555x # GHS. 0xfff48018 . INTC_IACKR@l(r3) # Single core r3.s file handlers_vle. Single Core: Interrupt AcknowledgeReg.globlIVOR4Handler . INTC_IACKR@ha # Single core: Read pointer into ISR Vector Table r3. 0x28 (r1) r3 r3. epilog for C ISR and enables nested interrupts Rev 1. addr.section . addr.align 4. addr.equINTC_EOIR.1 Rev 1.optimized by minimizing time interrupts are disabled Rev 1.3 Jul 2 2007 SM .2 Sept 21 2004 SM .equINTC_IACKR_PRC0.align 16 . S Mihalik.ivor_handlers. Inc. Single Core: End Of Intterrupt Reg. 0x2C (r1) 0x14 (r1) # Read ISR address from ISR Vector Table using pointer # Set MSR[EE]=1(wait a couple clocks after reading IACKR) # Store a second working register # Store LR (LR will be used for ISR Vector) Qorivva Simple Cookbook.Modified for VLE instructions. 2004 SM .s . -0x50 (r1) r3.Changes for MPC551x and mapped to . All rights reserved # STACK FRAME DESIGN: Depth: 20 words (0xA0. MPC551x: Proc 0 End Of Interrupt Reg.0: April 23. r3 r3. 4 62 Freescale Semiconductor .optimized & corrected r3.LR * Reserved for calling function # 0x00 * SP * Backchain (same as gpr1 in GPRs) # ************* .r4 restore sequence from rev 1.1 Aug 2. addr.4 alpha Copyright Freescale Semiconductor. 2004.ivor_handlers section Rev 1. Diab(default) use . Metrowerks .2 Sept 8 2004 SM . 0xfff48010 . or\ 80 bytes) # ************* ______________ # 0x4C * GPR12 * ^ # 0x48 * GPR11 * | # 0x44 * GPR10 * | # 0x40 * GPR9 * | # 0x3C * GPR8 * | # 0x38 * GPR7 * GPRs (32 bit) # 0x34 * GPR6 * | # 0x30 * GPR5 * | # 0x2C * GPR4 * | # 0x28 * GPR3 * | # 0x24 * GPR0 * ___v__________ # 0x20 * CR * __CR__________ # 0x1C * XER * ^ # 0x18 * CTR * | # 0x14 * LR * locals & padding for 16 B alignment # 0x10 * SRR1 * | # 0x0C * SRR0 * | # 0x08 * padding * ___v__________ # 0x04 * resvd. # Use 2 of the next 4 lines for appropriate processor: r3.3. Rev.6. r24-31 with positive offset # Store SRR0:1 (must be done before enabling EE) # # # # MPC551x: Proc 0 Interrupt Acknowledge Reg. r4 r4. CodeWarrior 2. Rev 1. INTC_IACKR_PRC0@ha # MPC551x: Read proc'0 pointer into ISR Vector Table r3. 0x0C (r1) 0x10 (r1) # PROLOGUE # Create stack frame and store back chain # Store a working register # Note: use se_ form for r0-7. Cygnus.text_vle . INTC_IACKR_PRC0@l(r3) # MPC551x r3.equINTC_EOIR_PRC0.INTC software vector mode example using VLE instructions Description: Creates prolog.

0x18 se_mtctr r3 se_lwz r3. 0x34 se_lwz r7. 0x44 e_stw r9. 0x3C e_lwz r9. 0x24 mfcr r3 se_stw r3. 0x44 e_lwz r11. 0x14 se_mtlr r3 se_lwz r3. 0x40 e_stw r8. 0x4C e_stw r11. 0x3C se_stw r7. INTC_EOIR@l(r3) # Single Core . 0 # Disable interrupts for rest of handler # Use 1 of the following 2 lines: r4. 0x50 # Restore SRR0 # Restore SRR1 # Restore working registers # Delete stack frame # End of Interrupt se_lwz r3. 4 Freescale Semiconductor 63 . se_rfi Qorivva Simple Cookbook.Write 0 to proc'r 0 INTC_EIOR r4. se_lwz r3. 0x18 se_blrl epilog: se_lwz r3. 0x40 e_lwz r10. INTC_EOIR_PRC0@l(r3) # MPC551x . r3 se_lwz r0. Rev. 0x48 e_stw r10. 0x30 se_lwz r6. 0x4C mbar # e_lis e_lis se_li wrteei # e_stw e_stw 0 0 (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) # Store ISR address to LR to use for branching later # Store rest of gprs # Store CR # Store XER # Store CTR # Branch to ISR. INTC_EOIR_PRC0@ha # MPC551x: Load upper half of proc'r 0 EIOR address r3. 0x34 se_stw r5. mtsrr1 r3 se_lwz r4. e_add16i r1. 0x48 e_lwz r12. 0x1C mtxer r3 se_lwz r3. INTC_EOIR@ha # Single Core: Load upper half of EIOR address to r3 r4. mtsrr0 r3 se_lwz r3. 0x30 se_stw r0. 0x38 se_stw r6. 0x38 e_lwz r8.Write 0 to proc'r 0 INTC_EIOR 0x0C (r1) 0x10 (r1) 0x2C (r1) 0x28 (r1) r1. 0x1C se_mfctr r3 se_stw r3.se_mtlr r3 e_stw r12. but return here # EPILOGUE # Restore LR # Restore CTR # Restore XER # Restore CR # Restore other gprs except working registers # Ensure store to clear interrupt's flag bit completed # Use 1 of the following 2 lines: r3. 0x24 se_lwz r5. 0x20 mfxer r3 se_stw r3. 0x20 mtcrf 0xff.

(uint32_t)&dummy.159 */ (uint32_t)&dummy. (uint32_t)&dummy. MPC56xS. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 65 . /* ISRs 185 . MPC56xxP. (uint32_t)&dummy. /* Wait forever or for watchdog timeout */ } Qorivva Simple Cookbook. (uint32_t)&dummy. /* ISRs 200 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.h" void dummy (void). (uint32_t)&dummy.Added pragma for CodeWarrior */ Oct 22 2008 SM . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.224 */ (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 45 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.34 */ (uint32_t)&dummy. /* ISRs 75 . /* ISRs 160 .*/ /* ISRs 145 . /* ISRs 180 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.214 */ (uint32_t)&dummy. /* ISRs 155 . (uint32_t)&dummy.194 */ (uint32_t)&dummy. (uint32_t)&dummy.6. (uint32_t)&dummy.94 */ (uint32_t)&dummy. (uint32_t)&dummy.*/ /* ISRs 60 . (uint32_t)&dummy.29 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.74 */ (uint32_t)&dummy. /* ISRs 00 . /* ISRs 15 . (uint32_t)&dummy. /* ISRs 170 . (uint32_t)&dummy.04 */ (uint32_t)&dummy. Mihalik . (uint32_t)&dummy. (uint32_t)&dummy.54 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.64 */ /* Use the next line for MPC56xB. (uint32_t)&dummy. /* ISRs 205 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. MPC555x: 64 KB*/ April 22.149 */ /* Use the next line for MPC551x. (uint32_t)&dummy. /* ISRs 225 .intc_sw_isr_vector_table" ". (uint32_t)&dummy. (uint32_t)&dummy /* ISRs 245 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.14 */ (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 235 . (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 230 . /* ISRs 105 .239 */ (uint32_t)&dummy.229 */ (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 05 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&Pit1ISR.104 */ (uint32_t)&dummy.64 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.179 */ (uint32_t)&dummy. /* ISRs 25 . /* ISRs 90 . /* ISRs 95 . /* ISRs 20 . /* ISRs 115 .189 */ (uint32_t)&dummy. (uint32_t)&dummy.59 */ /* Use the next line for MPC551x or MPC563x: */ /* (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 210 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 35 . (uint32_t)&dummy. (uint32_t)&dummy.249 */ /* For MPC563x. (uint32_t)&dummy. /* ISRs 10 .174 */ (uint32_t)&dummy. /* ISRs 70 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.114 */ (uint32_t)&dummy. (uint32_t)&dummy.164 */ (uint32_t)&dummy.89 */ (uint32_t)&dummy.204 */ (uint32_t)&dummy.199 */ (uint32_t)&dummy. /* ISRs 240 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. changes for MPC551x */ Aug 30 2007 SM . (uint32_t)&dummy.79 */ (uint32_t)&dummy.44 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. MPC56xxP. /* ISRs 85 .219 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 40 . where PIT1 vector number is 60: */ (uint32_t)&Pit1ISR. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.19 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.244 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.09 */ (uint32_t)&dummy.Used pragma align instead of hard coding address */ Jul 5 2007 SM . (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 60 . /* ISRs 120 . (uint32_t)&dummy. (uint32_t)&dummy. void dummy (void) { while (1) {}. (uint32_t)&dummy. /* ISRs 100 . Mihalik */ March 16.69 */ (uint32_t)&dummy. (uint32_t)&dummy.intc_sw_isr_vector_table" data_mode=far_abs uint32_t IntcIsrVectorTable[] = { (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.c file IntcIsrVectors. /* ISRs 220 . (uint32_t)&dummy.3 /* /* /* /* /* /* /* /* /* /* IntcIsrVectors. (uint32_t)&dummy. extern void SwIrq4ISR(void). (uint32_t)&dummy. /* ISRs 145 . 4 64 Freescale Semiconductor . (uint32_t)&dummy.49 */ (uint32_t)&dummy.3 */ Jun 29 2006 SM . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.99 */ (uint32_t)&dummy.119 */ (uint32_t)&dummy. /* ISRs 155 . /* ISRs 215 . /* ISRs 140 . (uint32_t)&dummy.39 */ (uint32_t)&dummy.154 */ (uint32_t)&dummy. (uint32_t)&dummy.24 */ (uint32_t)&dummy.intc_sw_isr_vector_table" */ /* Diab compiler pragma */ /*const uint32_t IntcIsrVectorTable[] = { */ /* Use pragma next two lines with CodeWarrior compile */ #pragma section data_type ". (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 195 . (uint32_t)&dummy.109 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. extern void Pit1ISR(void). (uint32_t)&dummy. (uint32_t)&SwIrq4ISR.84 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.234 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.134 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.144 */ /* Use the next line for MPC563x or MPC56xxB. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 50 . (uint32_t)&dummy.149 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. 2006 S. where PIT1 vector number is 149: */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 80 . (uint32_t)&dummy.Modified for compile with Diab 5. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.184 */ (uint32_t)&dummy. /* ISRs 190 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.c . (uint32_t)&dummy. (uint32_t)&dummy.209 */ (uint32_t)&dummy. /* ISRs 110 . (uint32_t)&dummy.Changed to use PIT1 ISR instead of eMIOS Ch 0 ISR */ #include "typedefs. (uint32_t)&dummy. (uint32_t)&dummy.3. /* ISRs 135 . (uint32_t)&dummy. (uint32_t)&dummy.alignment now done in link file. (uint32_t)&dummy.139 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 175 .124 */ (uint32_t)&dummy.129 */ (uint32_t)&dummy. (uint32_t)&dummy. continue vectors and add Pit1ISR address for INTC vector number 302 */ }. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.table of ISRs for INTC in SW vector Mode */ Description: Contains addresses for first 250 ISR vectors */ Table address gets loaded to INTC_IACKR */ Alignment: MPC551x &MPC56xxP/B/S: 2 KB after a 4KB boundary. (uint32_t)&dummy. /* ISRs 30 . /* ISRs 150 . /* ISRs 55 . MPC56xxS: */ /* (uint32_t)&dummy. (uint32_t)&dummy.169 */ (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. /* ISRs 130 . (uint32_t)&dummy. /* ISRs 125 . (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy. 2004 S. Rev. /* Use next two lines with Diab compile */ /*#pragma section CONST ". (uint32_t)&dummy. (uint32_t)&dummy. (uint32_t)&dummy.

0 Jul 6 2007 S Mihalik .align SIXTEEN_BYTES e_b IVOR4Handler # IVOR 4 interrupt handler (External Interrupt) .6.align SIXTEEN_BYTES e_b IVOR7trap # IVOR 7 interrupt handler .3.align SIXTEEN_BYTES e_b IVOR6trap # IVOR 6 interrupt handler .for use with MPC551x.4 # # # # # # ivor_branch_table.align SIXTEEN_BYTES e_b IVOR3trap # IVOR 3 interrupt handler .align SIXTEEN_BYTES e_b IVOR1trap # IVOR 1 interrupt handler .align SIXTEEN_BYTES e_b IVOR0trap # IVOR 0 interrupt handler . MPC56xxP.align SIXTEEN_BYTES e_b IVOR5trap # IVOR 5 interrupt handler .align SIXTEEN_BYTES e_b IVOR13trap # IVOR 13 interrupt handler .section .Initial version Rev 1.align SIXTEEN_BYTES e_b IVOR2trap # IVOR 2 interrupt handler . MPC56xxS only Description: Branch table for 16 MPC551x core interrupts Copyright Freescale 2007. Rev.align SIXTEEN_BYTES e_b IVOR14trap # IVOR 14 interrupt handler .text_vle .1 Aug 30 2007 SM .align SIXTEEN_BYTES e_b IVOR8trap # IVOR 8 interrupt handler . MPC56xxPBS) ivor_branch_table.Converted assembly to VLE syntax .align SIXTEEN_BYTES e_b IVOR12trap # IVOR 12 interrupt handler . All Rights Reserved Rev 1.extern IVOR4Handler . 16 # 16 byte alignment required for table entries # Diab compiler uses value of 4 (2**4=16) # CodeWarrior.equ SIXTEEN_BYTES. 4 Freescale Semiconductor 65 .Made IVOR4Handler extern Rev 1.s .align SIXTEEN_BYTES e_b IVOR10trap # IVOR 10 interrupt handler . Cygnus use 16 IVOR0trap: IVOR1trap: IVOR2trap: IVOR3trap: IVOR5trap: IVOR6trap: IVOR7trap: IVOR8trap: IVOR9trap: IVOR10trap: IVOR11trap: IVOR12trap: IVOR13trap: IVOR14trap: IVOR15trap: .align SIXTEEN_BYTES e_b IVOR11trap # IVOR 11 interrupt handler . GHS.align SIXTEEN_BYTES e_b IVOR9trap # IVOR 9 interrupt handler .s file (MPC551x.2 Sep 9 2008 SM .align SIXTEEN_BYTES e_b IVOR15trap # IVOR15 interrupt handler Qorivva Simple Cookbook.ivor_branch_table. MPC56xxB.

Classic Instructions example. configure flash. The interrupt handler will re-enable interrupts and later. are: • VLE instructions are used (not available on MPC5553. NOTE: to get a true interrupt performance measurement. PIT PIT 1 Timer Load Value PIT 1 Timer Interrupt Request to INTC INTC (Hardware Interrupt Vector Request to Mode) INTC Crystal 8 MHz Clocks and PLL SIU_SYSCLK (MPC551x only) Divide sysclk by 1 for PIT sysclk set to 64 MHz Software settable interrupt request 4 (set in PIT interrupt service routine) MPC5500 / MPC5600 Unique INTC interrupt request to CPU core Figure 16. Exercise: Write a third interrupt handler which uses a software interrupt of a higher priority than the others. The software interrupt will have a higher priority. but an eMIOS channel could be used) • Timer will count at the system clock rate (causing an interrupt at a count value of 0) • System clock is set to 64 MHz A relative interrupt response can be measured by reading the PIT count value in the first line of the interrupt service routine. this program provides two interrupts that show nesting. as shown in other examples in this application note. Invoke this new software interrupt from one of the other ISRs. MPC5554) • Prologue/epilogue uses VLE assembly instructions • Programmable Interrupt Timer (PIT) is used as the interrupt timer (note: PIT is not available in some MPC55xx devices. The ISRs will be written in C. The main differences from the other INTC SW Mode.1 INTC: Hardware Vector Mode. 4 66 Freescale Semiconductor . The SPE will not be used. This provides an approximate 1 ms task (ISR) from the PIT and an approximate 2 ms task (ISR) from the software interrupt. so its accumulator will not be saved in the stack frame of the interrupt handler. Rev. An alternate method is to put a breakpoint in the beginning of the service routine and read the count register. so the appropriate registers will be saved and restored in the handler. in its interrupt service routine (ISR). invoke a second interrupt every other time. VLE Instructions Description Task: Using the Interrupt Controller (INTC) in hardware vector mode. VLE Instructions Example Qorivva Simple Cookbook. so the 1 PIT ISR is preempted by the software interrupt. Hardware Vector Mode. additional software is needed to initialize branch target buffers. Both ISRs will have a counter. and enable cache (if implemented).7 7.

These are shown as handler_0. either or both processors can receive the interrupt request from the Interrupt Controller.. b SwIrq4Handler .. Overall Program Flow showing PIT 1 Interrupt Qorivva Simple Cookbook.s file intc_hw_branch_table. b handler_2 . invoke SW 4 IRQ clear flag } SwIrq4ISR { increment counter clear flag } . . The selection is defined in INTC_PSR for each enabled interrupt. In this example... Pit1Handler: prologue: save registers re-enable interrupts branch to Pit1ISR epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return SwIrq4Handler: prologue: save registers re-enable interrupts branch to SwIrq4ISR epilogue (return from ISR): restore most registers ensure prior stores completed disable interrupts write to EOIR to restore priority restore SRR0:1 return main.. INTC HW Vector Mode.7.. so a common dummy trap address is used. b handler_3 . only one processor is selected in the MPC551x: processor 0 (e200z1).. which here is PIT1 and software interrupt 4.. Rev.c file main { init IVPR init INTC init SwIrq4 init PIT1 enable interrupts wait forever } Pit1ISR { increment counter if odd count. 4 Freescale Semiconductor 67 . followed by design steps and a stack frame implementation.. handler_1. b Pit1Handler . .s file IntcHandlerBranchTable b handler_0 . The INTC when used in hardware vector mode uses a branch table for getting to each INTC vector’s handler..2 Design The overall program flow is shown below. INTC vector for PIT1 interrupt taken vector to: MPC551x: IVPR0:19 + 0x800 + 149 (0x4) MPC555x: IVPR0:15 + 302 (0x10) MPC56xxBPS: IVPR0:19 + 0x800 + 60 (0x4) handlers. Figure 17. (Note: the code in this example does not have handlers for each INTC vector.. Also for MPC551x. VLE Instructions. b handler_1 . so the second core would have its own IntcHanderBranchTable (not included in this example)..... etc.... the second core has its own special purpose register IVPR.) For MPC551x.

Table 28. Hence even enabling the crystal oscillator to be active in the default mode (DRUN) requires enabling the crystal oscillator in appropriate mode configuration register (ME_xxxx_MC) then initiating a mode transition. Settings Clock Sources Mode Mode Config.1 Modes Use Summary (MPC56xxB/P/S only) Mode Transition is required for changing mode entry registers. The following table summarizes the mode settings used. After reset. 4 68 Freescale Semiconductor . enabling low power. PeriPeri. # 92 Other peripheral configurations are not used in example Qorivva Simple Cookbook. I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 (default) RUN0 ME_RUN0_MC 0x001F 007D 16 MHz IRC PLL0 Normal Normal Normal Normal On On Off Off Other modes are not used in example Peripherals also have configurations to gate clocks on and off. The following table summarizes the peripheral configurations used in this example. Mode Configurations for MPC56xxB/P/S INTC HW Vector Mode VLE Example Modes are enabled in ME_ME Register. Table 29. Rev. RTI PCTL Reg. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral PIT. the mode is switched in this example from the default mode (DRUN) to RUN0 mode. Enabled Modes pheral Config. Register Value sysclk Selection PLL1 16MHz XOSC0 PLL0 (MPC IRC 56xxP/S only) On On Off On Off On Off Off Memory Power Mode Data Flash Code Flash Main Voltage Reg. Config.7.2. Register Mode Config. Peripheral Configurations for MPC56xxB/P/S INTC HW Vector Mode VLE Example Low power modes are not used in example.

Config. then mode & inverted key TARGET_MODE = • Wait for transition to complete RUN0 • Verify current mode is RUN0 S_TRANS CURRENTMODE init Sysclk Initialize sysclk to 64 MHz. 4 Freescale Semiconductor 69 . code flash in normal mode (default) • • • • PLL0 is switched on Crystal oscillator is switched on 16 MHz IRC is switched on (default) Select PLL0 (system pll) as sysclk — PDO=0 MVRON=1 DFLAON. running from PLL (See Section 10. CFLAON= 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 — RUN0=1 — RUN_CFG = 0 - ME_ RUN0_MC = 0x001F 0070 MPC56xxB/S: • Peri.) Configure RUN0 Mode: • I/O Output power-down: no safe gating (default) • Main Voltage regulator is on (default) • Data. 01: run in DRUN mode only Assign peripheral configuration to peripherals: PIT. =0x4000 A50F wait ME_GS [S_TRANS] = 0 verify 4 = ME_GS [CURRENTMODE] - Initiate software mode transition to RUN0 mode • Mode & key. See PLL example.Initialization Table 30. RUN0 = 1 — — ME_ME = 0x0000 001D 8 MHz Crystal: CGM_ FMPLL[0]_CR =0x02400100 MPC56xx BPS Table Init Load INTC HW Branch Table with ISR names for: INTC Vector for SW interrupt request 4 INTC Vector for PIT 1 init Enable desired modes Modes And Clock Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: (MPC • 8 MHz xtal: FMPLL[0]_CR=0x02400100 56xxPBS • 40 MHz xtal: FMPLL[0]_CR=0x12400100 only) (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value. RTI: select ME_RUN_PC1 ME_RUN_PC11 = 0000 0010 ME_PCTL92 = 0x01 ME_MCTL =0x4000 5AF0. VLE Instructions Pseudo Code Step Relevant Bit Fields MPC551x Variable Init Counter for PIT 1interrupts Counter for software 4 interrupts MPC555x int Pit1Ctr = 0 int SWirq4Ctr = 0 e_b SwIrq4ISR e_b Pit1ISR DRUN=1. Initialization: INTC in Hardware Vector Mode. “PLL: Initializing System Clock (MPC551x. then clearing WEN (MPC56xxBPS only) See PLL Initialization example Qorivva Simple Cookbook. Rev. MPC55xx)”) — disable Watchdog Disable watchdog by writing keys to Status Register.

000 1_LDVAL1 = 64.Table 30. 56xxPBS)=1 TIE1 or TIE = 1 ISEL = 1 PRC_SEL= 0 (z1) PRI = 1 PRI = 2 PRC_SEL=0 (z1) PRI = 0 MDIS = 0 FRZ = 1 PIT_PITMCR = 0x0000 0001 PIT_TVAL1 = PIT_TIMER 64. Initialize INTC: • Configure for Hardware vector mode (MPC551x note: only proc’r 0.000 PIT_PITEN = 0x0000 0002 PIT_TIMER PIT_INTEN = 1_TCTRL = 0x0000 0002 0x0000000 PIT_INTSEL = 3 0x0000 0002 INTC_PSR [149] = 0x01 INTC_PSR [302] = 0x01 PIT_CH1_ LDVAL = 64. Initialization: INTC in Hardware Vector Mode. Value is defined in the link file. TEN (555x. VLE Instructions (continued) Pseudo Code Step Relevant Bit Fields MPC551x init Irq Vectors init INTC Load the common interrupt vector prefix to spr IVPR.000 PIT_CH1_ TCTRL = 0x0000 0003 INTC_PSR [60] = 0x01 init SwIrq4 enable ExtIrq Software Interrupt 4: • Raise priority to 2 • MPC551x: Select processor(s) to interrupt Enable recognition of requests to INTC by lowering the INTC’s current priority to 0 from default of 15 Enable external interrupts: set MSR[EE] = 1 INTC_PSR[4] = 0x02 INTC_CPR _PRC0[PRI]= 0 INTC_CPR [PRI]= 0 wrteei 1 while 1 waitloop wait forever Qorivva Simple Cookbook. IIC) Global controls: • Enable module • MPC555x. Rev. is used here) MPC555x MPC56xx BPS spr IVPR =__IVPR_VALUE HVEN_PRC0(551x) INTC_MCR . e200z1. RTI to LPCLKDIV1 = 0 divide by 1 (also applies to other Group 1 (default) peripherals of eSCI A. 56xxBPS: Freeze in debug mode Load a start count value for 64 MHz sysclk (PITs count down from value at sysclk rate) • PIT 1 Timeout = 64 M / (64 M sysclk/sec) = 1 ms Enable PIT 1 timer to count (counts down) Enable PIT 1 to request IRQ MPC551x: Assign PIT 1 flag for IRQ instead of DMA Configure PIT1 interrupts: • MPC551x: Select processor 0 (e200z1) • Select priority 1 PEN1(551x) = 1. [HVEN_PRC0] HVEN (555x) = 0 =1 SIU_SYSCLK [LPCLKDIV1] = 0 PIT_CTRL = 0x0000 0000 INTC_MCR [HVEN] =1 init PIT MPC551x: Init system clock divider for PIT. 4 70 Freescale Semiconductor .

Stack Frame for INTC Interrupt Handler (same as for Software Vector Mode example) Qorivva Simple Cookbook. 4 Freescale Semiconductor 71 . Rev.2.7.2 Interrupt Handlers Stack Frame Area 32 bit GPRs r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r0 CR locals and padding CR XER CTR LR SRR1 SRR0 padding LR area back chain LR placeholder r1 Register Location in Stack sp + 0x4C sp + 0x48 sp + 0x44 sp + 0x40 sp + 0x3C sp + 0x38 sp + 0x34 sp + 0x30 sp + 0x2C sp + 0x28 sp + 0x24 sp + 0x20 sp + 0x1C sp + 0x18 sp + 0x14 sp + 0x10 sp + 0x0C sp + 0x08 sp + 0x04 sp Table 31.

working registers from stack frame e_add16i sp. VLE Instructions) Step prolog Create stack frame Save SRR0:1 because nested interrupts will be allowed Re-enable external interrupts by setting MSR[EE] Save other appropriate registers for C ISR Branch to ISR. -0x50 (sp) store SRR0:1. r3 registers to stack frame wrteei 1 store other registers to stack frame e_bl Pit1ISR Pit1Ctr ++ if ((Pit1Ctr&1) ==0). 0x50 se_rfi Qorivva Simple Cookbook. Pit 1 Interrupt Handler (INTC in Hardware Vector Mode. invoke Software Interrupt 4 Clear Pit1Ctr interrupt flag by writing 1 to it SET=1 TIF1 or TIF=1 EE = 1 Relevant Bit Fields Pseudo Code MPC551x MPC555x e_stwu sp. 4 72 Freescale Semiconductor . INTC_SSCIR[4] = 2 PIT_PITFLG[TIF1] PIT_TFLG1[TIF PIT_CH1_TFLG[TIF =1 ] ] =1 =1 load most registers from stack frame mbar EE = 0 write 0 to INTC_EOIR_PRC 0 wrteei 0 write 0 to INTC_EOIR MPC56xxBPS epilog Restore registers from stack frame except SRR0:1 and two working registers Ensure interrupt flag in ISR has completed clearing before writing to INTC_EOIR Disable external interrupts by clearing MSR[EE] Restore former INTC’s Current Priority Restore SRR0:1 and working registers Restore stack frame space Return restore SRR0:1. saving return address Pit1ISR Increment Pit1Ctr If Pit1Ctr is even. Rev. sp.Table 32.

VLE Instructions) Step prolog Create stack frame Save SRR0:1 because nested interrupts will be allowed Re-enable external interrupts by setting MSR[EE] Save other appropriate registers for C ISR Branch to ISR. saving return address SWIrq4 ISR epilog Increment SWirq4Ctr Clear Software IRQ 4 interrupt flag by writing 1 to it Restore registers from stack frame except SRR0:1 and two working registers Ensure interrupt flag in ISR has completed clearing before writing to INTC_EOIR Disable external interrupts by clearing MSR[EE] Restore former INTC’s Current Priority Restore SRR0:1 and working registers Restore stack frame space Return EE = 0 CLR = 1 EE = 1 Relevant Bit Fields Pseudo Code MPC551x MPC555x e_stwu sp. sp. Software 4 Interrupt Handler (INTC in Hardware Vector Mode. 0x50 se_rfi Qorivva Simple Cookbook. Rev. working registers from stack frame e_add16i sp.Table 33. r3 registers to stack frame wrteei 1 store other registers to stack frame bl SWIrq4ISR SWirq4Ctr++ INTC_SSCIR4 = 1 load most registers from stack frame mbar wrteei 0 write 0 to INTC_EOIR_PRC0 write 0 to INTC_EOIR restore SRR0:1. 4 Freescale Semiconductor 73 . -0x50 (sp) store SRR0:1.

ESYNCR2.R = 0x00000007.Based on AN2865 INTC Hardware Vector Mode example*/ Aug 12 2009 SM .B.MCR. EMFD=0x30*/ CRP. /* Wait for PLL to LOCK */ /* Use 1 of the next 2 lines: */ FMPLL. /* MPC551x Proc'r 0: initialize for HW vector mode*/ } void initPIT(void) { SIU. EPREDIV=0.SYSCLK.PITINTEN.LPCLKDIV1 = 0.h" /* Use proper include file such as mpc5510.HVEN_PRC0 = 1.B.c files mainc.R = 0x00000005.ESYNCR2.ESYNCR2. } /* /* /* /* /* /* /* Divide sysclk by 1 for Group 1 modules */ Ensure PIT is not disbaled */ Timeout= 64K sysclks x 1sec/64M sysclks= 1 ms */ Enable PIT 1 flag to request INTC or DMA */ Assign PIT 1 flag to select IRQ. */ /* 12MHz xtal: ERFD to initial value of 5 */ /*FMPLL.R = 0x00000003. __IVPR_VALUE@l mtivpr r3 } void initINTC(void) { INTC. /* Enable external oscillator */ while (FMPLL.3 7.SYSCLKSEL = 2. */ /* 12MHz xtal: CLKCFG=PLL.R = 0x00000002.B.B.Changed PLL initial ERFD value.c (MPC551x shown with 8 MHz crystal) main. Rev.1 /* /* /* /* Code main. uint32_t Pit1Ctr = 0.ESYNCR1./* Counter for software interrupt 4 */ void initSysclk(void) { /* Initialize PLL and sysclk to 64 MHz */ /* Use 2 of the next 4 lines: */ FMPLL.B. asm(" wrteei 1").R = 0xF0000020.c 2009 All rights reserved.PITINTSEL. PIT. In. r3. */ /* 12MHz xtal: ERFD change for 64 MHz sysclk */ SIU. */ #include "mpc5510.TLVAL[1].Hardware vector mode program using C isr */ Feb 12 2009 SM . EPREDIV=2. /* Counter for PIT 1 interrupts */ uint32_t SWirq4Ctr = 0. /* Select PLL for sysclk */ } asm void initIrqVectors(void) { lis r3.c .R = 0.B. /* 8MHz xtal: ERFD change for 64 MHz sysclk */ /*FMPLL.B.SYNSR. PIT.PEN1 = 1. */ Start PIT counting */ PIT 1 interrupt selects proc'r 0 & priority 1 */ void initSwIrq4(void) { INTC. /* 8MHz xtal: ERFD to initial value of 7 */ FMPLL.CLKSRC. /* Interrupt Vector Prefix value from link file*/ extern const vuint32_t IntcIsrVectorTable[].R = 0x00000006. 4 74 Freescale Semiconductor .1 7.CPR_PRC0.SYSCLK. PIT.PITEN. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r3./* Software interrupt 4 IRQ priority = 2 */ } void enableIrq(void) { INTC. INTC.ESYNCR2. EMFD=0x20*/ /*FMPLL.XOSCEN = 1.R = 2.R = 0x01.1.7.3.PSR[4].R = 0xF0020030.PRI = 0.h or mpc5554. added 12MHz crystal numbers */ Copyright Freescale Semiconductor.ESYNCR1.LOCK != 1) {}.PITCTRL.3. PIT. not DMA req.h */ extern uint32_t __IVPR_VALUE. } /* MPC551x Proc'r 0: Lower INTC's current priority */ /* Enable external interrupts */ Qorivva Simple Cookbook. /* 8MHz xtal: CLKCFG=PLL. PIT.R = 0x00000005.PSR[149].R = 64000.

TIF1 = 1.B. while (1) { i++. enableIrq().SSCIR[4].void main (void) { vuint32_t i = 0. Rev. 4 Freescale Semiconductor 75 . INTC. initINTC(). initSwIrq4().R = 1. } /* Increment interrupt counter */ /* If PIT1Ctr is even*/ /* then invoke software interrupt 4 */ /* Clear PIT 1 flag by writing 1 */ /* Increment interrupt counter */ /* Clear channel's flag */ Qorivva Simple Cookbook. } void SwIrq4ISR(void) { SWirq4Ctr++. initSysclk(). initIrqVectors().SSCIR[4].R = 2.PITFLG. initPIT(). if ((Pit1Ctr & 1)==0) { INTC. } PIT. } /* Dummy idle counter */ /* /* /* /* /* /* Set sysclk to 64 MHz */ Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize PIT1 for 1kHz IRQ. priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void Pit1ISR(void) { Pit1Ctr++.

B. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r3.PSR[4]. } /* Single core: Initialize for HW vector mosde */ void initPIT(void) { PIT.CLKCFG = 0X7.LOCK != 1) {}. priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void Pit1ISR(void) { Pit1Ctr++.R = 0x16080000. __IVPR_VALUE@l /* Note: IVPR lower bits are unused in MPC555x */ mtivprr3 } void initINTC(void) { INTC.B.Based on AN2865 INTC Software Vector Mode example*/ /* Copyright Freescale Semiconductor. if ((Pit1Ctr & 1)==0) { INTC. /* Enable PIT module & freeze count during debug */ PIT.R = 0x00000003. /* Final value for 64 MHz: RFD=0 */ } asm void initIrqVectors(void) { lisr3.TIMER[1].3. /* Interrupt Vector Prefix value from link file*/ uint32_t Pit1Ctr = 0. /* Software interrupt 4 IRQ priority = 2 */ } void enableIrq(void) { INTC.c . In.2 main.ESYNCR1.1. } /* /* /* /* /* /* Set sysclk to 64 MHz */ Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize PIT1 for 1kHz IRQ. initPIT(). asm(" wrteei 1")./* Dummy idle counter */ initSysclk(). initINTC(). */ #include "mpc563m.LDVAL.TIMER[1]. RFD=1 */ while (FMPLL.h */ extern uint32_t __IVPR_VALUE./* Counter for software interrupt 4 */ void initSysclk(void) { /* Intialize sysclk to 64MHz for 8 MHz crystal*/ FMPLL. MFD=12. /* PIT 1 interrupt has priority 1 */ } void initSwIrq4(void) { INTC. /* Initial values: PREDIV=1. } PIT. INTC.B.B.R = 64000. while (1) { i++. 4 76 Freescale Semiconductor . initIrqVectors(). enableIrq().SYNSR.B.CPR.R = 0x00000001.R = 1.TIMER[1].R = 0x16000000. r3.h" /* Use proper include file such as mpc5510.SYNCR. /* Timeout= 64K sysclks x 1sec/64M sysclks= 1 ms */ PIT. /* Change clk to PLL normal mode from crystal */ FMPLL.TIF = 1.SSCIR[4]. /* Counter for PIT 1 interrupts */ uint32_t SWirq4Ctr = 0.TFLG.c (MPC555x MPC563xM shown with 8 MHz crystal) /* main.SSCIR[4].c 2009 All rights reserved.MCR. /* Start timer counting & freeze during debug */ INTC.R = 2. /* Wait for FMPLL to LOCK */ FMPLL.7.PSR[302].R = 2. } void SwIrq4ISR(void) { SWirq4Ctr++.Hardware vector mode program using C isr */ /* Feb 03 2009 SM .R = 0x1. initSwIrq4().HVEN = 1. } /* Increment interrupt counter */ /* If PIT1Ctr is even*/ /* then nvoke software interrupt 4 */ /* Clear PIT 1 flag by writing 1 */ /* Increment interrupt counter */ /* Clear channel's flag */ Qorivva Simple Cookbook.TCTRL.MCR. } /* Lower INTC's current priority */ /* Enable external interrupts */ void main (void) { vuint32_t i = 0.SYNCR. Rev.PRI = 0.h or mpc5554.

PSR[60]. Mihalik. /* PIT 1 interrupt vector with priority 1 */ } void initSwIrq4(void) { INTC.Mihalik Initial version based on previous AN2865 example */ May 22 2009 S.R = 64000. } /* Single core: initialize for HW vector mode */ void initPIT(void) { PIT.MCR.R = 0x01.R = 0x8000010A. /* Peri.Simplifed by removing unneeded sysclk.Simplified code */ Mar 15 2010 SM . updated header */ Copyright Freescale Semiconductor.R = 0x01.7. } /* Software interrupt 4 IRQ priority = 2 */ /* Single Core: Lower INTC's current priority */ /* Enable external interrupts */ Qorivva Simple Cookbook. 2010.B.R = 0x001F0074.MPC56xxS shown with 8 MHz crystal) main.CR.h" /* Use proper include file */ extern uint32_t __IVPR_VALUE.PLL0ON.FMPLL[0].OSC0ON. */ #include "56xxS_0204.PRI = 0.syclk=PLL */ ME.R = 0x40005AF0. asm(" wrteei 1").c (MPC56xB/P/S . /* 8 MHz xtal: Set PLL0 to 64 MHz */ ME.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void disableWatchdog(void) { SWT. Cfg. /* Enable PIT and configure to stop in debug mode */ PIT. 1 settings: only run in RUN0 mode */ ME.TCTRL.PCTL[92].3 /* /* /* /* /* /* main.CR.MCTL. 2009./* Counter for software interrupt 4 */ void initModesAndClock(void) { ME. /* Enter RUN0 Mode & Key */ ME.GS. __IVPR_VALUE@h /* IVPR value is passed from link file */ ori r3.MCR.R = 2. /* RUN0 cfg: 16MHzIRCON. RUN0. Rev.B.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME.1.RUN[0].R = 0x0000001D. Inc.RUNPC[1]. /* Clear watchdog enable (WEN) */ } asm void initIrqVectors(void) { lis r3.Hardware vector mode program using C isr */ Feb 12. 4 Freescale Semiconductor 77 . /* Enable DRUN.MCTL.SR.R = 0x0000d928.LDVAL. } void enableIrq(void) { INTC. RESET modes */ /* Initialize PLL before turning it on: */ CGM. /* PIT. RTI: select ME_RUN_PC[1] */ /* Mode Transition to enter RUN0 mode: */ ME. /* Timeout= 64000 sysclks x 1sec/64M sysclks = 1 ms*/ PIT. /* Write keys to clear soft lock bit */ SWT.PSR[4].c . PCTL code */ Jul 03 2009 S Mihalik .MER.R = 0x000000003.CPR.3.modified initModesAndClks.B.HVEN = 1. r3. SWT.R = 0x4000A50F. /* Enter RUN0 Mode & Inverted Key */ while (ME.B.R = 0x00000001. SAFE.SR. /* Interrupt Vector Prefix value from link file*/ uint32_t Pit1Ctr = 0.R = 0x02400100.CH[1]. /* Enable PIT1 interrupt & start PIT counting */ INTC. __IVPR_VALUE@l mtivpr r3 } void initINTC(void) { INTC. 2009 S.CH[1].R = 0x0000c520.GS. /* Counter for PIT 1 interrupts */ uint32_t SWirq4Ctr = 0.R = 0x00000010. All rights reserved.

initModesAndClock().B.R = 2. initSwIrq4().SSCIR[4].void main (void) { vuint32_t i = 0. if ((Pit1Ctr & 1)==0) { INTC. } /* Increment interrupt counter */ /* If PIT1Ctr is even*/ /* then nvoke software interrupt 4 */ /* MPC56xxP/B/S: CLear PIT 1 flag by writing 1 */ /* Increment interrupt counter */ /* Clear channel's flag */ Qorivva Simple Cookbook.CH[1].TIF = 1. priority 2 */ Initialize software interrupt 4 */ Ensure INTC current prority=0 & enable IRQ */ } void Pit1ISR(void) { Pit1Ctr++. set sysclk=64 MHz*/ Disable watchdog */ Initialize exceptions: only need to load IVPR */ Initialize INTC for software vector mode */ Initialize PIT1 for 1kHz IRQ. } /* Dummy idle counter */ /* /* /* /* /* /* /* MPC56xxP/B/S: Initialize mode entries.TFLG. Rev. initIrqVectors(). disableWatchdog().SSCIR[4]. } PIT. initINTC(). enableIrq().R = 1. 4 78 Freescale Semiconductor . } void SwIrq4ISR(void) { SWirq4Ctr++. while (1) { i++. initPIT(). INTC.

extern SwIrq4ISR .4 alpha Rev 1. All rights reserved # STACK FRAME DESIGN: Depth: 20 words (0xA0. epilog for C ISR and enables nested interrupts Rev 1.1 Aug 2.5 Mar 09 2010 SM .4 Jan 22 2009 SM .s .globl Pit1Handler .LR * Reserved for calling function # 0x00 * SP * Backchain (same as gpr1 in GPRs) # ************* . S Mihalik. Inc.section .delayed writing to EOIR until after disabling EE in epilog Rev 1. 2004.1 Rev 1.optimized & corrected r3.3.Removed unneeded Epilogue instruction: se_mtlr r3 Copyright Freescale Semiconductor.s file handlers_vle.INTC hardware vector mode example using VLE instructions Description: Creates prolog.ivor_handlers section Rev 1. 4 Freescale Semiconductor 79 . addr. or 80 bytes) # ************* ______________ # 0x4C * GPR12 * ^ # 0x48 * GPR11 * | # 0x44 * GPR10 * | # 0x40 * GPR9 * | # 0x3C * GPR8 * | # 0x38 * GPR7 * GPRs (32 bit) # 0x34 * GPR6 * | # 0x30 * GPR5 * | # 0x2C * GPR4 * | # 0x28 * GPR3 * | # 0x24 * GPR0 * ___v__________ # 0x20 * CR * __CR__________ # 0x1C * XER * ^ # 0x18 * CTR * | # 0x14 * LR * locals & padding for 16 B alignment # 0x10 * SRR1 * | # 0x0C * SRR0 * | # 0x08 * padding * ___v__________ # 0x04 * resvd.2 Sept 8 2004 SM . .Modified for VLE instructions. .2 # # # # # # # # # # handlers_vle.equINTC_EOIR.3 Jul 2 2007 SM .equINTC_EOIR_PRC0.7.globl SwIrq4Handler Qorivva Simple Cookbook.text_vle . Rev. 0xfff48018 # Dual Core: Proc 0 End Of Interrupt Reg.0: April 23. Rev 1. 2004 SM .ivor_handlers.optimized by minimizing time interrupts are disabled Rev 1.2 Sept 21 2004 SM . addr. 2010.r4 restore sequence from rev 1.extern Pit1ISR .Changes for MPC551x and mapped to . 2009. CodeWarrior 2. 0xfff48018 # Single Core: End Of Interrupt Reg.

0x50 se_lwz r3. 0x38 e_lwz r8. se_rfi # Restore SRR0 # Restore SRR1 # Restore working registers # Delete stack frame # End of Interrupt Qorivva Simple Cookbook. e_bl # Set MSR[EE]=1 # Store rest of gprs 0x20 (r1) 0x1C (r1) 0x18 (r1) 0x14 (r1) # Store CR # Store XER # Store CTR # Store LR # Branch to ISR. se_stw r0. INTC_EOIR_PRC0@l(r3) # r4. 0x4C mbar 0 # e_lis e_lis se_li wrteei # e_stw e_stw # EPILOGUE # Restore LR # Restore CTR # Restore XER # Restore CR # Restore other gprs except working registers # # r3. 0x44 e_lwz r11. e_stw r10. -0x50 (r1) r3.Pit1Handler: e_stwu se_stw mfsrr0 se_stw mfsrr1 se_stw r1. but return here Pit1ISR (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) se_lwz r3. e_stw r8. se_stw r6. se_lwz r3. 0x18 se_mtctr r3 se_lwz r3. e_stw r9. r3 se_lwz r0. 0x28 (r1) r3 r3. 0x0C (r1) 0x10 (r1) 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x24 (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) # PROLOGUE # Create stack frame and store back chain # Store a working register # Note: use se_ form for r0-7. 0x20 mtcrf 0xff.Write 0 to proc'r 0 INTC_EIOR Single Core . se_mfctr r3 se_stw r3. 0x30 se_lwz r6. se_stw r7. 4 80 Freescale Semiconductor . e_stw r11. 0x34 se_lwz r7. 0x40 e_lwz r10. 0x48 e_lwz r12. mtsrr0 r3 se_lwz r3. mfcr r3 se_stw r3. 0 0 Ensure store to clear interrupt flag bit completed Use 1 of the following 2 lines: Dual Core: Load upper half proc 0 EIOR addr to r3 Single Core: Load upper half of EIOR address to r3 Disable interrupts for rest of handler Use 1 or 2 of the next appropriate lines: Dual Core . e_add16i r1. Rev. mtsrr1 r3 se_lwz r4. INTC_EOIR@l(r3) # 0x0C (r1) 0x10 (r1) 0x2C (r1) 0x28 (r1) r1. r3 r3. se_stw r5. r24-31 with positive offset # Store SRR0:1 (must be done before enabling EE) wrteei 1 e_stw r12. se_stw r4. INTC_EOIR@ha # r4. 0x3C e_lwz r9. 0x14 se_mtlr r3 se_lwz r3. mfxer r3 se_stw r3. INTC_EOIR_PRC0@ha # r3.Write 0 to proc'r 0 INTC_EIOR # # r4. se_mflr r4 se_stw r4. 0x24 se_lwz r5. 0x1C mtxer r3 se_lwz r3.

e_stw r9. -0x50 (r1) r3. 0x34 se_lwz r7. r3 r3. se_stw r7. se_mfctr r3 se_stw r3. e_stw r10. 4 Freescale Semiconductor 81 . se_stw r4. se_stw r6. 0x20 mtcrf 0xff.Write 0 to proc'r 0 INTC_EIOR Single Core . INTC_EOIR@l(r3) # 0x0C (r1) 0x10 (r1) 0x2C (r1) 0x28 (r1) r1. but return here SwIrq4ISR (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) se_lwz r3. 0x30 se_lwz r6. INTC_EOIR_PRC0@l(r3) # r4. INTC_EOIR_PRC0@ha # r3. mtsrr0 r3 se_lwz r3. Rev. e_add16i r1. 0x50 se_lwz r3.Write 0 to proc'r 0 INTC_EIOR # # r4. mfxer r3 se_stw r3.SwIrq4Handler: e_stwu se_stw mfsrr0 se_stw mfsrr1 se_stw r1. se_lwz r3. 0x4C mbar 0 # e_lis e_lis se_li wrteei # e_stw e_stw # EPILOGUE # Restore LR # Restore CTR # Restore XER # Restore CR # Restore other gprs except working registers # # r3. r24-31 with positive offset # Store SRR0:1 (must be done before enabling EE) wrteei 1 e_stw r12. 0x48 e_lwz r12. e_bl # Set MSR[EE]=1 # Store rest of gprs 0x20 (r1) 0x1C (r1) 0x18 (r1) 0x14 (r1) # Store CR # Store XER # Store CTR # Store LR # Branch to ISR. e_stw r8. 0x3C e_lwz r9. mtsrr1 r3 se_lwz r4. se_stw r0. INTC_EOIR@ha # r4. 0x14 se_mtlr r3 se_lwz r3. 0x1C mtxer r3 se_lwz r3. 0x18 se_mtctr r3 se_lwz r3. se_rfi # Restore SRR0 # Restore SRR1 # Restore working registers # Delete stack frame # End of Interrupt Qorivva Simple Cookbook. mfcr r3 se_stw r3. 0 0 Ensure store to clear interrupt flag bit completed Use 1 of the following 2 lines: Dual Core: Load upper half proc 0 EIOR addr to r3 Single Core: Load upper half of EIOR address to r3 Disable interrupts for rest of handler Use 1 or 2 of the next appropriate lines: Dual Core . 0x44 e_lwz r11. 0x28 (r1) r3 r3. se_mflr r4 se_stw r4. r3 se_lwz r0. se_stw r5. e_stw r11. 0x0C (r1) 0x10 (r1) 0x4C 0x48 0x44 0x40 0x3C 0x38 0x34 0x30 0x2C 0x24 (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) (r1) # PROLOGUE # Create stack frame and store back chain # Store a working register # Note: use se_ form for r0-7. 0x40 e_lwz r10. 0x38 e_lwz r8. 0x24 se_lwz r5.

align ALIGN_OFFSET e_b Pit1Handler #INTC HW vector 60 .......... Rev...........align ALIGN_OFFSET e_b hw_vect61 #INTC HW vector 61 . .intc_hw_branch_table.7.section .....Made SwIrq4Handler.. 4 # MPC551x...........align ALIGN_OFFSET e_b hw_vect64 #INTC HW vector 64 hw_vect57: hw_vect58: hw_vect59: hw_vect61: hw_vect62: hw_vect63: hw_vect64: ..align ALIGN_OFFSET e_b hw_vect63 #INTC HW vector 63 ...equ ALIGN_OFFSET.1 Aug 30 1007 SM ....... CW 4) #...align ALIGN_OFFSET e_b hw_vect62 #INTC HW vector 62 .MPC56xxB/P/S: 4 byte branch alignments (Diab/GHS use 2..align ALIGN_OFFSET e_b hw_vect3 ....0 Jan 22 2009 SM .........align ALIGN_OFFSET e_b SwIrq4Handler .....0 Jul 2.3..3 # # # # intc_hw_branch_table.. All rights reserved ...align ALIGN_OFFSET e_b hw_vect59 #INTC HW vector 59 .align ALIGN_OFFSET e_b hw_vect0 ....align ALIGN_OFFSET e_b hw_vect58 #INTC HW vector 58 ....extern Pit1Handler .. for contiguous vectors .Modified for VLE and MPC56xxB/P/S INTC vector numbers Copyright Freescale Semiconductor.align ALIGN_OFFSET e_b hw_vect5 hw_vect0: hw_vect1: hw_vect2: hw_vect3: hw_vect4: hw_vect5: #INTC HW vector 0 #INTC HW vector 1 #INTC HW vector 2 #INTC HW vector 3 # SW IRQ 4 #INTC HW vector 5 .. Inc....align ALIGN_OFFSET e_b hw_vect2 ... Qorivva Simple Cookbook.. 4 # MPC555x: 16 byte branch alignments (Diab/GHS use 4.equ ALIGN_OFFSET.. emiosCh0Handler . CW 16) IntcHandlerBranchTable: # Only 100 example vectors are implemented here # MPC555x: This table must have 64 KB alignment # MPC551x......extern Rev 2....extern SwIrq4Handler ..s file (MPC56xxB/P/S vectors shown) Rev 1. etc.align ALIGN_OFFSET e_b hw_vect1 ..... for other vectors ...... 4 82 Freescale Semiconductor ....text_vle ... etc......... MPC56xxB/P/S: Requires 2 KB alignment after 4KB boundary .. 2007 S Mihalik Rev 1...align ALIGN_OFFSET e_b hw_vect57 #INTC HW vector 57 . 2007.

align SIXTEEN_BYTES e_b IVOR9trap # IVOR 9 interrupt handler .section .align SIXTEEN_BYTES e_b IVOR13trap # IVOR 13 interrupt handler .align SIXTEEN_BYTES e_b IVOR14trap # IVOR 14 interrupt handler . MPC56xxS only Description: Branch table for 16 ore interrupts Copyright Freescale 2007.s . Rev.align SIXTEEN_BYTES e_b IVOR0trap # IVOR 0 interrupt handler .for use with MPC551x.ivor_branch_table.0 Jul 6 2007 S Mihalik .equ SIXTEEN_BYTES.align SIXTEEN_BYTES e_b IVOR6trap # IVOR 6 interrupt handler .align SIXTEEN_BYTES e_b IVOR8trap # IVOR 8 interrupt handler .3.align SIXTEEN_BYTES e_b IVOR11trap # IVOR 11 interrupt handler . 16 # 16 byte alignment required for table entries # Diab compiler uses value of 4 (2**4=16) # CodeWarrior.7.Made IVOR4Handler extern (for SW vector mode) Rev 1. All Rights Reserved Rev 1.text_vle .1 Aug 30 2007 SM .align SIXTEEN_BYTES e_b IVOR15trap # IVOR15 interrupt handler Qorivva Simple Cookbook.align SIXTEEN_BYTES e_b IVOR3trap # IVOR 3 interrupt handler . 4 Freescale Semiconductor 83 .align SIXTEEN_BYTES e_b IVOR7trap # IVOR 7 interrupt handler . MPC56xxB/P/S only) ivor_branch_table.Initial version Rev 1. MPC56xxB.align SIXTEEN_BYTES e_b IVOR2trap # IVOR 2 interrupt handler . GHS.extern IVOR4Handler .Converted assembly to VLE syntax . MPC56xxP.4 # # # # # # ivor_branch_table. 2009.align SIXTEEN_BYTES e_b IVOR12trap # IVOR 12 interrupt handler . Cygnus use 16 IVOR0trap: IVOR1trap: IVOR2trap: IVOR3trap: IVOR3trap: IVOR5trap: IVOR6trap: IVOR7trap: IVOR8trap: IVOR9trap: IVOR10trap: IVOR11trap: IVOR12trap: IVOR13trap: IVOR14trap: IVOR15trap: .align SIXTEEN_BYTES e_b IVOR1trap # IVOR 1 interrupt handler .2 Sep 9 2008 SM .align SIXTEEN_BYTES e_b IVOR10trap # IVOR 10 interrupt handler .align SIXTEEN_BYTES e_b IVOR4trap # IVOR 4 interrupt handler .align SIXTEEN_BYTES e_b IVOR5trap # IVOR 5 interrupt handler .s file (MPC551x.

L1CSR0[CWM].1 MMU: Create TLB Entry Description Task: Initialize translation lookaside buffer (TLB) entry number six to define a memory page defined below. This program shows how MMU entries are created. SR. Guarded. both R + W for all Executable Not write through Not inhibited Default Default EPN Relevant BIt Field SIZE RPN = EPN UR. The cache program will later use this entry to allocate part of cache as SRAM. must be set to 1. Table 34. there is not any memory or I/O on current MPC5500 devices for the effective address range of this entry. TLB Entry 6 Summary Page Attribute Starting Effective Address Size Translation Access allowed Access not allowed Write Mode Policy1 Cache Inhibit Global Process ID Translation Space 1 Value 0x4004 0000 4 KB No translation Data. MMU TLB Entry Example Qorivva Simple Cookbook. as shown below. G. MPC5500 gpr mtspr spr’s MAS1:3 tlbwe (entry number defined in MAS0[ESEL]) MMU Entry 00 Entry 01 ••• Entry n TLB Table V TS TID EPN RPN SIZE Permissions Memory/Cache Attributes User Attributes IPROT V TS TID EPN RPN SIZE Permissions Memory/Cache Attributes User Attributes IPROT ••• V TS TID EPN RPN SIZE Permissions Memory/Cache Attributes User Attributes IPROT gpr mfspr spr’s MAS1:3 tlbre* Figure 18. Endianness Default To allow MMU entries to specify the write mode policy. Accessing the MMU’s TLB entries is done using sprs MAS0:3. 4 84 Freescale Semiconductor . the cache write mode. so nothing can be accessed yet. UW. However. Rev. SW = 1 UX. SX = 0 W=0 I=0 M.8 8. E = 0 TID = 0 TS = 0 Coherency.

Create a new MMU entry seven that starts at address 0x4009 0000 and has a size of 16 KB.Exercise: If your debugger supports viewing the MMU TLB table. Similarly a CSI. 8.7” from the command prompt for TLB entries 0 to 7. use cache inhibit. UW. SW] = 1 spr MAS1 = 0x8000 0100 spr MAS2 = 0x4004 0000 spr MAS3 = 0x4004 000F tlbwe1 Per Book E. G. Initialization: MMU TLB Entry 6 Step Initialize MMU Select TLB entry number and define MMU R/W & TLB entry 6 Replacement Control: • Select TLB entry 6 • Select TLB 1 (required) • Null replacement Define Descriptor Context and Configuration Control: • Set page as valid • No invalidation protection • Use global process ID • Use default translation space • Size = 4KB Define EPN and Page Attributes: • EPN = 0x40 0400 for address 0x4004 0000 • WIMAGE = all 0’s. Lauterbach — select “MMU TLB1 Table” from the MPC5554 menu. MMU Assist Registers 0–3 Summary Table 35. SX] = 0 MAS3[UR. no write-thru Define RPN and Access Control (here as RW data) • RPN = 0x40 0400 for address 0x4004 0000 • Set user bits to 0 (unused) • Disable both user & supervisor execution • Enable both user and supervisor data R and W Write TLB entry fields in MAS1:3 to the entry per MAS0[ESEL] 1 Relevant Bit Fields Pseudo Code spr MAS0 = 0x1006 0000 MAS0[ESEL] = 6 MAS0[TBLSEL] = 1 MAS0[NVCAM] = 0 MAS1[VALID] = 1 MAS1[IPROT] = 0 MAS1[TID] = 0 MAS1[TS] = 0 MAS1[TSIZE] – 0x1 MAS2[EPN] = 0x40 0400 MAS2[W.2 00 MAS0 Design 01 0 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TBSEL 0 TID EPN RPN 0 ESEL 0 TS 0 TSIZ 0 VLE Below is a version of figure 6-6 of the e200z6 PowerPC™ Core Reference Manual Rev. a context synchronizing instruction (CSI). such as isync or mbar. 4 Freescale Semiconductor 85 .” Qorivva Simple Cookbook. would be needed before the tlbwe instruction if there were uncompleted preceding storage accesses. To display the current MMU table in a debugger: Green Hills — type “target tlbr 0. view the table entries before and after running the code1. NV 0 W I M G E MAS1 VALID IPROT MAS2 MAS3 U0 U1 U2 U3 UX SX UW SW UR SR Figure 19. I. would be needed after the tlbwe to ensure that any immediate subsequent storage accesses use the updated TLB entry values. PEMicro — hit the MMU button or type “showmmu. SR. M. such as an isync. 0 for reference.. 1. Rev. E] = 0 MAS3[RPN] = 0X40 0400 MAS3[U0:3] = 0 MAS3[UX.

3 /* /* /* /* /* /* Code main.h" /* Use proper include file such as mpc5510. while (1) { i++. WIMAGE = all 0's */ /* Load MAS2 with 0x4004 0000 */ /* Define RPN and access control for data R/W */ /* RPN = 0x4004 0000. TSIZE=1 (4KB size) */ /* Load MAS 1 with 0x8000 0100 */ /* Define EPN and page attributes: */ /* EPN = 0x4004 0000.MMU . All Rights Reserved */ Notes: */ 1. must be done by debug scripts or BAM */ 2. 0x1006 /* Select TLB entry #. r3. TS=0. 0x4004 ori r3. 4 86 Freescale Semiconductor . 2003 S. MMU not initialized. Rev. } Qorivva Simple Cookbook. UR/SR/UW/SW=1 */ /* Load MAS3 with 0x4004 000F */ /* Write entry defined in MAS0 (entry 6 here) to MMU TLB */ /* Dummy idle counter */ /* Define 4KB R/W space starting at 0x4004 0000 */ /* Loop forever */ void main (void) { int i = 0.h or mpc5554. Copyright Freescale. L2SRAM not initialized. 0x8000 ori r3.0 Sept 28.h */ asm void MMU_init_TLB6(void) { lis r3. 2004.create TLB entry example */ Description: Creates a new entry to the TLB table in the MMU */ Rev 1. must be done by debug scripts */ #include "mpc563m. 0x0100 mtMAS1 r3 lis r3. define R/W replacment control */ mtMAS0 r3 /* Load MAS0 with 0x1006 0000 for TLB entry #6 */ lis r3. UX/SX=0. U0:3=0. TID=0. IPROT=0.c .8. r3. 0x4004 mtMAS2 r3 lis r3. } MMU_init_TLB6(). 0x000F mtMAS3 r3 } tlbwe /* Define description context and configuration control:*/ /* VALID=1.Mihalik.

See AN2789. then have LockingLoop use either dcbtls or icbtls instruction for each cache line.” that uses memory starting at address 0x4004 0000 and that is 4 KB in size. Although this example is implemented in a C program. the cache as well as MMU entries would normally be initialized in an assembler program as part of initialization. Cache invalidation takes approximately 134 cycles for the 32 KB cache of the MPC5554. This example shows how to turn the cache on (enable) based on information from the e200z6 PowerPCTM Core Reference Manual. It is available on those with the e200z6 core.9 9.1 Cache: Cache as RAM Description Task: Use 4 KB of cache as RAM.e. Use the memory page created in Section 8. “MMU: Create TLB Entry.. However. Rev 0. MPC5500 Configuration and Initialization. Note that cache is not available on all MPC555x devices. View the MMU entry created (if your debugger supports this feature). part of the cache is allocated to be used as RAM. (Hint: Point a gpr to the address of data or code to be locked. View and modify memory created in cache1. Cache as RAM Example 1. L1SR0[CINV] = 0. Add instructions to lock some data or code in cache. Normally cache initialization is done shortly after reset. Exercise: Execute the code.) MPC5500 e200z6 Core Effective Address CPU Core Data/Instructions Real Address Cache Inhibit = 1 Cache Inhibit = 0 Cache Real Address Memory MMU Data/ Instructions Cache Bypassed Figure 20. Rev. 4 Freescale Semiconductor 87 . for further information. Qorivva Simple Cookbook. or use other resources such as DMA. during this time it would be possible to perform some other task. This design simply polls the INV bit to wait for an indication that invalidation completed. Use the debugger’s memory display window with the address of the new memory created. The advantages of using cache as RAM is that it increases available memory to a program and is the fastest type of memory. i. well before main and C code execution. After it is enabled.

Solution: Before enabling cache. Invalidate cache. • Use sync instructions before writing to L1CSR0 • Set mode to copyback • Enable cache CINV = 1 CINV = 0 ABT= 1 CWM = 1 CE = 1 Initialize (See previous example. so flash is temporarily cache inhibited. Section 8.2 Design Table 36. • Use sync instructions before writing to L1CSR0 • Set cache invalidation bit Wait until cache invalidation completes. Out of reset.9. Possible result: If the code just happens to be in the cache line that is being converted to be used as SRAM. 4. then try to invalidate cache again msync isync L1SCR0 = 0x0010 0001 spr MAS0 = 0x1006 0000 spr MAS1 = 0x8000 0100 spr MAS2 = 0x4004 0000 spr MAS3 = 0x4004 000F tlbwe1 spr CTR = 0x80 r3 = 0x4004 0000 Locking Loop: dcbz instruction for line’s address dcbtls instruction for line’s address Enable cache If cache is already being invalidated. Enable cache in copyback mode. keeping other control bits at 0. 4 88 Freescale Semiconductor . Cache: Configure Part as RAM Step Relevant Bit Fields CINV = 0 Pseudo Code Wait for L1SCR0[CINV] = 0 msync isync spr L1CSR0[CINV] = 1 Wait for L1SCR0[CINV] = 0 if L1SCR0[ABT] = 1. then attempt another cache invalidation. Cache is enabled. If cache invalidation was aborted.”) MMU TLB entry 6 Lock 4KB Initialize loop counter for 4 KB block size / 32 byte line size = 128 in cache Load a register with start address of new address space. Cache line addresses are established and locked into cache. wait until done. such as an isync. MMU TLB entry is initialized as above example. Qorivva Simple Cookbook. “MMU: Create TLB Entry. so when the cache is enabled code will be put in cache 2. the flash MMU page has Cache Inhibit = 0. Similarly a CSI. then that code could be erased. then change the flash MMU page back to CI = 0. would be needed before the tlbwe instruction if there were uncompleted preceding storage accesses. a context synchronizing instruction (CSI). change the flash MMU page from CI = 0 to CI = 1. After the cache is enabled and configured. would be needed after the tlbwe to ensure that any immediate subsequent storage accesses use the updated TLB entry values. CAUTION: Do not execute cache-based code that reconfigures the cache which could overwrite the cached code being executed! Example improper sequence is: 1. Rev. such as isync or mbar. For each 32-byte cache line in the 4 KB space: • Establish line address in cache (and zero out line) • Lock line in cache 1 Per Book E. 3.

0x0100 mtMAS1 r3 /* Define EPN and page attributes: */ /* EPN = 0x4004 0000.1 Sept 27. r3. r3. other bits 0 */ Mask out all bits except CABT*/ Compare if CABT. r4 /* Mask out all bits except CINV*/ cmpli r3. 4 Freescale Semiconductor 89 . other bits 0 */ and r3. = 1 */ If there was an aborted invalidation. l1csr0 /* Get current status of cache from spr L1CSR0*/ li r4. 0x0010 r3. 0x1 l1csr0. r3. 0x0002 /* In a scratch register set bit 30 to 1. L2SRAM not initialized. 0x4004 /* Point r3 to start of desired address (r3=0x40040000)*/ LockingLoop: Qorivva Simple Cookbook.9. UR/SR/UW/SW=1 */ lis r3.Configure part of cache as SRAM */ /* Rev 0.h or mpc5554. l1csr0 r4. =1 */ beq WaitForInvalidationComplete2 mfspr li and cmpli beq lis ori msync isync mtspr r3. r3 /* /* /* /* /* /* Branch to error if cache invalidation was aborted */ Get current status of cache from spr L1CSR0*/ In a scratch register set bit 29 to 1. r3. 0x4004 /* Load MAS2 with 0x4004 0000 */ mtMAS2 r3 /* Define RPN and access control for data R/W */ /* RPN = 0x4004 0000. 0x1006 /* Select TLB entry #. l1csr0 /* Get current status of cache from spr L1CSR0*/ and r3. define R/W replacment control */ mtMAS0 r3 /* Load MAS0 with 0x1006 0000 for TLB entry #6 */ /* Define description context and configuration control:*/ /* VALID=1. r4 /* Before writing to L1CSR0. 0x4004 /* Load MAS3 with 0x4004 000F */ ori r3. bit 30. must be done by debug scripts or BAM */ /* 2. execute msync & isync */ /* Invalidate cache: Set L1CSR0[CINV]=1. 0x0002 /* Compare if CINV. 0x0004 r3. U0:3=0. bit 29. UX/SX=0. 0x80 /* Load r3 with loop count = 4KB/32B = 128 = 0x80 */ r3 /* Move loop count to spr CTR */ r3.c . wait until it clears */ mfspr r3. 0x8000 /* Load MAS 1 with 0x8000 0100 */ ori r3.Mihalik. TS=0. TSIZE=1 (4KB size) */ lis r3. 0x0004 InvalidateCache r3. 2004 S.h */ asm void cache_enable(void) { WaitForInvalidationComplete1: /* If CINV is already set. 2004. Rev. 0x0002 /* Compare if CINV. r4 /* Mask out all bits except CINV */ cmpli r3. attempt again */ /* Enable cache */ /* In a scratch register set bit 12 = 0 (used to set CWM)*/ /* Also set bit 31 =1 (used for setting CE) */ /* Before writing to L1CSR0. r3. bit 30. MMU not initialized.3 Code /* main. 0x000F mtMAS3 r3 tlbwe /* Write entry defined in MAS0 (entry 6 here) to MMU TLB */ } asm void li mtCTR lis cache_lock_4KB(void) { r3. execute msync & isync */ /* Enable cache with Cache others to 0 */ } asm void MMU_init_TLB6(void) { lis r3. other fields=0*/ WaitForInvalidationComplete2: mfspr r3.h" /* Use proper include file such as mpc5510. Copyright Freescale. r4 r3. IPROT=0. WIMAGE = all 0's */ lis r3. r3. All Rights Reserved */ /* Notes: */ /* 1. TID=0. must be done by debug scripts */ #include "mpc563m. =1 */ beq WaitForInvalidationComplete1 InvalidateCache: msync isync mtspr l1csr0.

and in cache for 32B cache line of 0's */ cache */ pointer by 32 B */ loop back if it is not yet zero */ void main (void) { int i = 0. no transl’n*/ /* Lock 4KB R/W space starting at 0x4004 0000 in cache */ /* Loop forever */ Qorivva Simple Cookbook. 0x20 LockingLoop /* /* /* /* Establish Lock that Increment Decrement address line in address CTR. r3. } /* Dummy idle counter */ /* Invalidate then enable cache in copyback mode */ /* Define 4KB R/W space starting at 0x4004 0000. } while (1) { i++. r3 r3. 4 90 Freescale Semiconductor . cache_lock_4KB(). r0.} dcbz dcbtls addi bdnz r0. cache_enable(). r3 0. MMU_init_TLB6(). Rev.

Exercise: Measure CLKOUT frequency. Therefore two frequency increases are used.1 PLL: Initializing System Clock (MPC551x. After initializing the PLL predivider. 12 MHz for MPC555x with 8 MHz crystal. MPC55xx) Description Task: Initialize the system clock to run at 64 MHz from the PLL (FMPLL on MPC555x) whose input is an 8 MHz crystal. For this example. divider. Current Controlled Oscillator Divider: ERFD (MPC551x) RFD (MPC555x) fvco (MPC551x) fico (MPC555x) Fsys (sysclk) = 64 MHz SIU EBDF PLL 8 MHz Crystal Predivider: EPREDIV (MPC551x) PREDIV (MPC555x) CLKOUT = 16 MHz Fref Predivider Output Frequency Figure 21. Then modify code to produce a new frequency. The second increase only changes the divider after the PLL feedback loop. 496 BGA AF25 416 BGA AE24 324 BGA AA20 208 BGA T141 144 QFP – PJ8–8 EVB xPC 563M Signal CLKOUT eMIOS Ch 12 1 PE6 CLKOUT (used for test only if no CLKOUT) Available only on MPC563x 208 BGA. and multiplier. then you can log an error message and reset the part. CLKOUT. Enable. PLL Example Block Diagram (sysclk reset default values: 16 MHz for MPC551x. 70 Package Pin No. If LOCK was not achieved in a maximum time. 144 QFP 67 176 QFP 83 208 BGA P13 Function Name SIU PCR No. In a real system. hence sysclk has an external bus division factor (EBDF) before sysclk reaches CLKOUT. CLKOUT has a maximum specified value. Attempting to increase the frequency in one step may cause overshoot of the PLL beyond the maximum sysclk specification and briefly cause a sharp increase in current demand from the power supply. – MPC555x Family Package Pin No. the PLL LOCK is tested by simply polling for the desired status to occur. Rev. 16 MHz CLKOUT will be used. which does not cause change of lock because the divider is after the feedback path. Filter. 4 Freescale Semiconductor 91 . if necessary.10 10. Signals for PLL Example MPC551x Family Pin Name SIU PCR No. a maximum timeout mechanism would be implemented. Qorivva Simple Cookbook. 8 MHz for MPC563x with 8 MHz crystal) Table 37. MPC5500 Multiplier: EMFD (MPC551x) MFD (MPC555x) PFD / Charge Pumps.

Output Freq range is 4 MHz to 10 MHz. and use the directions given in the PLL chapter of the MPC5510 Microcontroller Family Reference Manual (June 2007). and ERFD = 5. the loss-of-lock circuitry and interrupts would not normally be enabled until after these steps are executed. the above formula is used below with values chosen for final MPC551x multiplier and dividers as shown. EPREDIV = 0.= -----------------.1 MPC551x (EMFD + 16) Fsys = Fref  -----------------------------((EPREDIV + 1) (ERFD+1) MPC551x devices have a system clock frequency formula from the PLL of: For an 8 MHz crystal (Fref) and a target frequency of 64 MHz (Fsys).2. Rev. to accommodate the frequency overshoot. producing CLKOUT at 16 MHz. In devices that do not exit reset with PLL enabled as system clock. (See the MPC551x Reference Manual for allowed values for the multiplier and dividers. such as PLL or an internal reference clock. Otherwise the reset default values may try to force the PLL to run beyond its frequency specifications. MPC563x note: some packages do not have CLKOUT. Note: ERFD should values. Qorivva Simple Cookbook. Because changing the predivider or multiplier can cause loss of lock. that is not turned on and ready. These documented steps are used even though we are using conservative frequencies in this example. eMIOS channel 12’s output frequency is sysclk divided by 16. SIU_SYSCLK[SYSCLKSEL] on MPC551x or FMPLL_ESYNCR1[CLKCFG] on MPC563xM is used to specify the system clock. For example. so EBDF will be used to divide the 64 MHz sysclk by 4. 10.= ---. Do not initialize this field to a source.2 Design Loss of lock and loss of clock detection is not enabled in this example. 4 92 Freescale Semiconductor .) Note: Prediv. Fsys (EMFD + 16) (32 + 16) 64 MHz 8 -----. Be careful not to select a system clock that is not enabled.= -----------. The steps below show the effect on these frequencies. We must be careful the maximum system clock frequency and VCO minimum/maximum frequencies are within the specification in the Data Sheet as the multiplier and dividers are changed. The preliminary specification for MPC5516 has a maximum CLKOUT frequency of 25 MHz.10. so eMIOS channel 12 is configured as OPWFMB to verify sysclk frequency. it is often good practice to initialize PLL registers with the multiplier and dividers before turning on the oscillator.= ----------------------------(0+1) (5+1) (EPREDIV + 1) (ERFD+1) 1 Fref 8 MHz For this MPC551x example we have final values of EMFD = 32. are mostly odd numbers. per the reference manual.

5 MHz) 8 MHz Reset Default Values Write > final ERFD value to PLL_ESYNCR2 (0x000 0007) Write final EPREDIV and EMFD values to PLL_ESYNCR1 (0xF000 0020) Turn on OSC and wait for PLL to LOCK Write final ERFD value to PLL_ESYNCR2 (0x0000 0005) 12 MHz Reset Default Values Write > final ERFD value to PLL_ESYNCR2 (0x000 0005) Write final EPREDIV and EMFD values to PLL_ESYNCR1 (0xF002 0030) Turn on OSC and wait for PLL to LOCK Write final ERFD value to PLL_ESYNCR2 (0x0000 0003) 0 32 7 8 MHz (384 MHz) (45.5 MHz) – 0 – 32 – 5 – 8 MHz – 384 MHz – 64 MHz 1 1 83 83 5 5 6 MHz 6 MHz (594 MHz) (594 MHz) (99 MHz) (99 MHz) 2 48 5 4 MHz (256 MHz) (42.2. Step EPREDI V 1 1 EMF D 83 83 PLL_ESYNCR Predivider VCO Freq.) Qorivva Simple Cookbook.6 MHz) – 2 – 48 – 3 – 4 MHz – 256 MHz – 64 MHz 10.Table 38. Data prelim.2 MPC555x (MFD + 4) Fsys = Fref  -----------------------------((PREDIV + 1)  2RFD) MPC555x devices have a system clock frequency formula of: For an 8 MHz crystal (Fref) and a target frequency of 64 MHz (Fsys). 4 Freescale Semiconductor 93 . Rev. (See the MPC555x Reference Manual for allowed values for the multiplier and dividers. Data Sheet) (4 MHz ERFD Sheet) 10 MHz) 5 7 4 MHz 4 MHz (396 MHz) (396 MHz) (66 MHz) (49. MPC551x Steps for Programming Enhanced PLL PLL_ESYNCR1 Crystal Freq. 2 Output Fsys (192 MHz–680 MHz (3 MHz–66 MHz per Frequency per prelim. the above formula is used below with values chosen for MPC555x multiplier and dividers as shown.

(Be sure to check your microcontroller’s latest data sheet for actual specified values. 4 94 Freescale Semiconductor . which uses a different formula offering more frequency choices.= -----------. PREDIV = 4.) • Predivider output frequency: 4 MHz to the maximum frequency. and RFD = 0.= -----------------. which could lead to unpredictable results.= -----------------.= -----------.= ---. For example. We will use the same pattern of setting sysclk in two stages: the RFD value is initially set to the final RFD value + 1. (See the reference manual for that device to learn the allowed values for multiplier and dividers. Another difference is that the PLL exits reset in the bypass mode. Rev. the MPC5554 Microcontroller Data Sheet.4. which is more compatible with existing MPC555x code.) • ICO frequency (fico): 48 MHz to the maximum Fsys.2. then wait for LOCK before setting the final RFD value. 10. where PLL output frequency uses the MPC555x formula. This example uses the legacy mode.= ----------------------------((1 + 1)  20) ((PREDIV + 1)  2RFD) 1 Fref 8 MHz For this example with an 8 MHz crystal. there is the benefit that the transient demand to the circuit board’ s power is reduced and we can eliminate the potential risk of overclocking the CPU and peripherals. (64 MHz is used here. bit field FMPLL_ESYNCR1[CLKCFG] must be changed.= ----------------------------((4 + 1)  21) ((PREDIV + 1)  2RFD) 5 Fref 40 MHz For this example with a 40 MHz crystal. Rev 1. and an enhanced mode. so no writing to its SIU_PCR is required. Qorivva Simple Cookbook. we have final values of MFD = 12.Fsys (MFD + 4) (12 + 4) 64 MHz 8 -----. To have sysclk be based on the PLL output. One must ensure the PLL specifications are not violated for the individual processor’s data sheet.) Fsys (MFD + 4) (12 + 4) 64 MHz 8 -----. If a 40 MHz crystal (Fref) is used. contains the specifications given here. so sysclk operates at the crystal frequency.= ---. and RFD = 1. By waiting to achieve LOCK before increasing to the final frequency.2. we have final values of MFD = 12.1 MPC563xM Differences MPC563xM implements both a legacy mode. such as on Freescale’s MPC5561 and MPC5567 EVBs. the formula for 64 MHz sysclk is shown below. However. its SIU_PCR does have controls for disabling the pad’s output buffer and drive strength. PREDIV = 1. CLKOUT is assigned to the pad by default after reset.

Rev. = 0x4610 0000 for 40 MHz crystal Enable external oscillator (MPC551x only) XOSCEN = 1 [NOTE: Make sure there is a delay such as waiting to lock before changing clock to run on PLL. for 8 MHz crystal. Relevant Bit Fields MPC551x PA = 1 OBE = 1 SRC = 3 EBDF = 3 SIU_PCR[70] = 0x060C MPC555x – SIU_ECCR [EBDF] = 3 Change clock to normal mode with crystal reference. use: • Predivider = 2 + 1 = 3 • Multiple = 48+ 16 = 4 • Divider+1 = 5 + 1 = 6 MPC555x with an 8 MHz crystal input. 4 Freescale Semiconductor 95 . use: • Predivider = 0 + 1 = 1 • Multiple = 32 + 16 = 48 • Divider+1 = 7 + 1 = 8 MPC551x with a 12 MHz crystal input. use: • Predivider = 0 + 1 = 1 • Multiplier = 12 + 4 = 16 • Divider = 21 = 2 MPC555x with a 40 MHz crystal input. 8 MHz: • RFD = 0 MPC555x. 8 MHz: • PREDIV = 1 • MFD = 12 (0xC) • RFD = 1 MPC555x 40 MHz: • PREDIV = 4 • MFD = 12 (0xC) • RFD = 2 PLL_ESYNCR2 = 0x0000 0007 for 8 MHz crystal.Table 39. sysclk • Pad assignment — CLKOUT • Output buffer is enabled • Slew rate control = max.] Wait for PLL to lock Wait for LOCK = 1 CRP_CLKSRC [XOSCEN] = 1 Wait for PLL_SYNSR [LOCK] = 1 – Wait for FMPLL_SYNSR [LOCK] = 1 Set final divider after feedback loop: MPC551x with an 8 MHz crystal: • Divider = 1 + 5 = 6 MPC551x with a 12 MHz crystal: • Divider = 1 + 3 = 4 MPC555x with 8 MHz crystal: • Divider = 20 = 1 MPC555x with 40 MHz crystal: • Divider = 21 = 2 Select PLL for sysclk [and optionally could divide sysclk to peripherals for lower power] (MPC551x only) MPC551x. 40 MHz: • RFD = 1 SYSCLKSEL = 2 PLL_ESYNCR2 FMPLL_SYNCR = 0x0000 0005 = 0x1600 000 for 8 MHz crystal. MPC555x Steps for PLL Example Pseudo Code Step Init Assign pad CLKOUT signal (MPC551x only). (fastest slew rate) Initialize External Bus Divider Factor from default divide by 2 value to desired divide by 4 value. Desired final CLKOUT = 16 MHz = 64 MHz / (3+1). = 0xF002 0030 for 12 MHz crystal FMPLL_SYNCR = 0x1608 000 for 8 MHz crystal. 12 MHz: • EPREDIV = 2 • EMFD = 48 (0x30) • ERFD = 5 MPC555x. = 0x0000 0005 for 12 MHz crystal PLL_ESYNCR1 = 0xF000 0020 for 8 MHz crystal. CLKCFG = 7 (MPC551x and MPC563x only) Set initial multiplier and dividers for 64 MHz sysclk: MPC551x with an 8 MHz crystal input. = 0x0000 0003 = 0x4608 0000 for 12 MHz crystal for 40 MHz crystal SIU_SYSCLK [SYSCLKSEL] = 2 – Qorivva Simple Cookbook. 8 MHz: • EFRD = 5 MPC551x 12 MHz: • EFRD = 3 MPC555x. use: • Predivider = 4 +1 = 5 • Multiplier = 12 + 4 = 16 • Divider = 22 = 4 MPC563x: FMPLL_ESYNCR1 [CLKCFG] = 7 MPC551x: 8 MHz • EPREDIV = 0 • EMFD = 32 (0x20) • ERFD = 7 MPC551x. MPC551x.

/* Dummy idle counter */ SIU. use the next 3 lines */ /* FMPLL. */ Rev 1. /* Assign pad PortE[6] as CLKOUT signal */ SIU.R = 0x16080000.3 10.PLL-sysclk example for MPC555x*/ Description: Set PLL to run at 64 MHz based on 8 MHz crystal */ Copyright Freescale Semiconductor.SYSCLK.R = 0x00000005. /* Select PLL for sysclk */ } while (1) { i++. /* 8MHz xtal: ERFD to initial value of 7 */ FMPLL.c .R = 0x00000003. */ /* 12MHz xtal: CLKCFG=PLL. RFD=1 */ while (FMPLL.Updated to also show 12 MHz crystal implementation */ Rev 1.LOCK != 1) {}. MMU not initialized.SYNCR. Inc 2007.Initial version */ Rev 1.LOCK != 1) {}. /* Enable external oscillator */ while (FMPLL. must be done by debug scripts or in a crt0 type file */ #include "mpc5554.Initial version */ Rev 1.3.2 May 5 2008 SM . /* Initial values: PREDIV=1.0 Jul 11 2007 SM. EPREDIV=2.B.R = 0x46100000.SYSCLKSEL = 2.ECCR.Added alternate code if 40 MHz crystal is used */ Notes: */ 1. 4 96 Freescale Semiconductor . */ /* 12MHz xtal: ERFD to initial value of 5 */ /*FMPLL.SYNSR.SYNCR.SYNCR. 2007. } /* Loop forever */ Qorivva Simple Cookbook. MMU not initialized.ESYNCR1. MFD=12.Changed initial ERFD value to be an odd number */ Notes: */ 1. must be done by debug scripts or BAM */ 2. EPREDIV=0. /* Wait for PLL to LOCK */ /* Use 1 of the next 2 lines: */ FMPLL.B.ESYNCR1.B. /* 8MHz xtal: ERFD change for 64 MHz sysclk */ /*FMPLL. L2SRAM not initialized. */ /* 12MHz xtal: ERFD change for 64 MHz sysclk */ SIU.R = 0x00000007. must be done by debug scripts or in a crt0 type file */ #include "mpc5510.PLL-sysclk example */ Description: Change sysclk to run from PLL 64 MHz based on 8 MHz crystal. /* 8MHz xtal: CLKCFG=PLL.10.ESYNCR2.B.SYNSR. /* Final value for 64 MHz: RFD=0 */ /* For 40 MHz crystal.CLKSRC.ESYNCR2. All Rights Reserved */ Rev 1.ECCR.R = 0x16000000. /* Wait for FMPLL to LOCK */ FMPLL.3. MFD=12.PCR[70]. */ Copyright Freescale Semiconductor.2 /* /* /* /* /* /* /* /* /* MPC555x with 8 MHz crystal main. EMFD=0x20*/ /*FMPLL. RFD=1 */ /* while (FMPLL. All rights reserved.SYNSR.B. *//* Final value for 64 MHz: RFD=0 */ } while (1) { i++.ESYNCR2.R = 0x060C.EBDF = 3.1 Aug 14 2007 SM .Changed sysclk to 64 MHz */ Rev 1.3 Aug 12 2009 SM . use the next 3 lines */ FMPLL. *//* Initial values: PREDIV=4.B. SRAM not initialized.c . must be done by debug scripts or BAM */ 2.ESYNCR2.h" void main (void) { volatile uint32_t i=0.R = 0xF0000020. /* Divide sysclk by 3+1 for CLKOUT */ /* For 8 MHz crystal.1 Aug 08 2007 SM .1 /* /* /* /* /* /* /* /* /* /* Code MPC551x with 8 MHz crystal main. } /* Loop forever */ 10.EBDF = 3.0 Jul 12 2007 SM .h" void main (void) { volatile uint32_t i=0.B. Rev. EMFD=0x30*/ CRP. /* Dummy idle counter */ SIU.R = 0x00000005.Changed sysclk to run at 64 MHz */ Rev 1.SYNCR.R = 0x46080000.R = 0xF0020030.LOCK != 1) {}.2 May 18 2009 SM . /* Divide sysclk by 3+1 for CLKOUT */ /* Use 2 of the next 4 lines: */ FMPLL. *//* Wait for FMPLL to LOCK */ /* FMPLL.XOSCEN = 1.

OBE = 1. RFD=1 */ while (FMPLL.CCR.CH[12].B.FRZ = } void initEMIOSch12(void) { /* EMIOS CH 12:Output Pulse Width & Freq Modl'n Buf*/ /* Period = 4 emios clks.B.B. /* Initialize pad for eMIOS channel.B. Rev.B.PLL-sysclk example */ Description: Set PLL to run at 64 MHz based on 8 MHz crystal for MPC563x */ For testing devices without CLKOUT. time base is disabled./* eMIOS clk= sysclk/(GPRE+1)= sysclk/4 */ 0. Ch 23 drives ctr bus A */ = 1.CH[12].PCR[191].MODE= 0x58.CCR.4usec for 8M.B. MMU not initialized.)*/ /* If 64MHz sysclk./* Enable eMIOS clock */ 0.SYNCR. /* Duty cycle in emios clks */ EMIOS.R = 0x16080000. /* Ext. initEMIOS(). /* Init.MCR.ECCR./* Disable freezing channel counters in debug mode */ #include "mpc563m. an eMIOS channel is used */ Copyright Freescale Semiconductor.CH[12].PCR[191]. /* Init.10.c .1 Aug 14 2007 SM -Changed sysclk to 64 MHz */ Rev 1.R = 4. */ SIU. MFD=12.Initial version */ Rev 1.CCR.R = 3.GTBE = 1.R = 0x16000000. flag on B match*/ SIU.Modified for MPC563x including adding EMIOS OPWFM output*/ Notes: */ 1. must be done by debug scripts or BAM */ 2.B. All rights reserved.64Msysclk) */ EMIOS. /* Start timers/counters by enabling global time base */ SIU. 4 Freescale Semiconductor 97 .ETB = EMIOS.LOCK != 1) {}.B.EDPOL = 1.ESYNCR1.CH[12]. } /* Loop forever */ Qorivva Simple Cookbook./* Mode= 0PWFMB.CH[12].CH[12]. eMIOS to provide sysclk/4 to eMIOS channels */ initEMIOSch12(). /* Channel counter uses divide by (0+1) prescaler */ EMIOS.SYNCR. /* Divide sysclk by 3+1 for CLKOUT */ FMPLL.2 Apr 30 2008 SM. /* Channel counter's prescaler is loaded & enabled*/ EMIOS.0 Jul 12 2007 SM.h" void initEMIOS(void) { EMIOS. /* Final value for 64 MHz: RFD=0 */ } while (1) { i++.B. */ Rev 1.UCPRE = 0.SYNSR.CLKCFG = 0X7.MCR.GPRE= EMIOS.CADR.B.PA = 1. /* Polarity is active high */ EMIOS. /* Change clk to PLL normal mode from crystal */ FMPLL.B.)*/ EMIOS. /* Initialize pad for output */ } /* Dummy idle counter */ void main (void) { volatile uint32_t i=0.CBDR. Duty = 2 eMIOS clks */ /* If 8MHz sysclk. eMIOS channel 12 for sysclk/16 OPWFMB */ EMIOS.GPREN EMIOS.B. /* Period= 4 emios clocks= 16 sysclks */ /* (32usec. 2008.MCR.B.B.MCR.CCR.EBDF = 3. Freq= 8MHz/4/4 = 500Kz (2us per. must be done by debug scripts or in a crt0 type file*/ /* Used for MPC563m devices */ 0x3.UCPREN = 1. Freq= 64MHz/4/4= 4MHz (250ns per. /* Wait for FMPLL to LOCK */ FMPLL.3.MCR. L2SRAM not initialized.3 /* /* /* /* /* /* /* /* /* /* MPC563x with 8 MHz crystal main. /* Initial values: PREDIV=1.

LQFP LQFP 22 96 138 Port MPC56xxS Family SIU PCR No. Signals for PLL Example MPC56xxB Family Port Signal SIU PCR No. MPC56xxB/P/S mode transition logic simplifies software by not requiring checking the status bits for external oscillator stable and PLL locked. MPC56xxB/P/S Clock Generation Module 16 MHz IRC Crystal OSC0 FMPLL0 System Clock Selector (may have more inputs) Fsys (sysclk) = 64 MHz Output Clock Selector (may have more inputs) Divide by 1. then FMPLL0. the PLL is locked (if the PLLON bit was also set in the targeted mode’s configuration). PLL Example Block Diagram Table 40. Rev. 2.1 PLL: Initializing System Clock (MPC56xxB/P/S) Description Task: Initialize the system clock to run at 64 MHz from the PLL whose input is an 8 MHz or 40 MHz crystal. 4 or 8 Output Clock SIU Pad Assignment CLKOUT = 16 MHz Figure 22. Enable CLKOUT to observe frequency of 16 MHz IRC. PCR 100 144 No. A mode transition is until not complete until: 1. 4 98 Freescale Semiconductor . the external oscillator is stable (if the XOSCON bit is set in the targeted mode’s configuration) & 2. Exercise: Measure CLKOUT frequency while stepping through code and verify proper frequencies. 100 144 176 LQFP LQFP BGA 12 16 G4 PB[6] Port MPC56xxP Family SIU Package Pin No. 0 Package Pin No. 144 176 LQFP LQFP 47 136 61 166 208 BGA R5 B1 CLKOUT eMIOS Ch 21 PA[0] PH[4] PA[1] (used on cut 1 MPC56xxS because cut 1did not have CLKOUT) Qorivva Simple Cookbook. external oscillator (crystal).11 11. 103 1 Package Pin No.

can be used generate an interrupt request upon a SAFE mode transition. The following table summarizes the peripheral configurations used in this example for MPC56xxB and MPC56xxS.2. One could also loop code on incrementing a software counter to some maximum value as a timeout. which is the normal. Register Value sysclk Selection Memory Power Mode PLL1 (MPC Data 56xxP/S Flash only) Off Off Code Flash Main Voltage Reg.1 Design Mode Use Mode Transition is required for changing mode entry registers. Peripherals also have configurations to gate clocks on and off.) requires enabling the crystal oscillator in DRUN mode configuration register (ME_DRUN_MC) then initiating a mode transition to the same DRUN mode. a SAFE mode transition could preempt the desired mode transition. Mode Configurations Summary for MPC56xxB/P/S PLL Example Modes are enabled in ME_ME Register. Because initial silicon for MPC56xxS did not include CLKOUT. Settings Mode Config. if enabled. However. MPC56xxP does not require any peripheral clock gating configuration for this example.11. expected use after power up. Rev. If there was a hardware failure. for example default mode (DRUN. It is normal to use a timer when waiting for a status bit to change. There is an interrupt that.2 11. the status bit could instead be enabled to generate an interrupt request (assuming the INTC is initialized beforehand). hence no code is needed for these. enabling low power. then an error condition could be recorded in EEPROM or elsewhere. Mode 16MHz IRC On On XOSC0 PLL0 I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 (default) RUN0 ME_RUN0_MC 0x001F 0074 16 MHz IRC PLL0 Off On Off On Normal Normal Normal Normal On On Off Off Other modes are not used in example It is good practice after a mode transition to verify the desired mode was entered by checking the ME_GS[S_CURRENTMODE] field. This example changes from DRUN mode to RUN0 mode. If a timeout was reached. This example by default would have a watchdog timer expire if for some reason the mode transition never completed. This minimal example simply polls a status bit to wait for the targeted mode transition to complete. MPC56xxP does not have peripheral configurations for XOSC0 nor PLL0. Register Clock Sources Mode Config. This would allow software to complete other initialization tasks instead of brute force polling of the status bit. ce t Table 41. Hence even enabling the crystal oscillator to be active in the current mode. 4 Freescale Semiconductor 99 . an eMIOS channel is used to indicate final sysclk frequency. Qorivva Simple Cookbook.

4 100 Freescale Semiconductor . MPC5604B RM.2.14 0 4 Fvco Range: 256 .96 64 64 IDF Range: 0 . Verify range values in microcontroller reference manual. Table 43. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral SIUL (MPC56xxB/S) used for enabling pad for output clock PCTL Reg. Ranges shown are per MPC5604B Reference Manual.2 PLL Calculations ldf FPLL output clock= Fxtal  ----------------(idf  odf) The formula for PLL output clock (also called PHI) in normal mode is: which in terms of the PLL’s Control Register field names is equivalent to: FPLL NDIV = Fxtal  -----------------------------output clock ((IDIF + 1)  2ODIF+1) Also Fvco must be within a range of 256 MHz and 512 MHz.512 MHz 512 MHz 512 MHz ODF Range: 0-3 2 2 FPLL output clock 64 MHz 64 MHz CR value 0x0240 0100 0x1240 0100 11. Peripheral Configurations for MPC56xxB/P/S PLL Example Low power modes are not used in example. Fvco is defined as: NDIV Fvco = Fxtal  --------------(IDIF + 1) The following table summaries calculations to obtain desired 64 MHz frequency for different crystal frequencies. Fxtal 8 MHz 40 MHz NDIV Range: 32 .3 Progressive Clock Switching Progressive clock switching is expected to be used on system clock. then gradually decreases the division until Qorivva Simple Cookbook. PeriPeri. 4/2008. # 68 Other peripheral configurations are not used in example 11. IDF and ODF are bit field values in GCM FMPLL0 Control Register. Rev.Table 42. Config.2. Rev. Enabled Modes pheral Config. MPC56xxB/P/S PLL0 Calculations (NDIV. the PLL locks at a divided frequency. When changing the system clock to run on a PLL frequency. 1.

4 Clock Monitor Unit (CMU) — XOSC Frequency Monitor One feature of the CMU is monitoring the XOSC frequency with respect to the 16 MHz FIRC. If the crystal frequency is less than FIRC  2RCDIV then. so as long as FXOSC > 16 MHz  23 (2 MHz) no action takes place. after the mode transition several microseconds are needed before the PLL output clock. which takes 3 usec. (See illustration below. Rev. The number of system clock cycles before running at full frequency is 8 + 16 + 32 = 56 sysclks. is initially divided by 8 then changes gradually to the programmed frequency without losing lock. RCDIV defaults to a value of three. For MPC56xxB/S. Qorivva Simple Cookbook. for example. 2 then 1 PLL lock frequency PLL output clock In this example.2. When the PLL locks. Progressive clock switching is enabled in the Clock Generation Module’s (MC_CGM’s) FMPLL Control Register (CR). Table 44. Division factor of 8.it is divided by 1. 11. which may have a 40 MHz crystal for FlexRAY operation. an 8 MHz crystal is used instead of a 40 MHz crystal. 4. MPC56xxP. (sysclk in this example) is running at full frequency. sysclk in this example. However with progressive clock switching. CMU_CSR[RCDIV] must change before turning on XOSC in the mode configuration register. a reset occurs. Therefore the threshold is 16 MHz  20 (16 MHz). the mode transition can complete. Progressive Clock Switching for 64 MHz PLL operation PLL lock frequency 64 MHz 64 MHz 64 MHz 64 MHz Division PLL output clock Factor frequency 8 4 2 1 8 MHz 16 MHz 32 MHz 64 MHz Number of PLL output clock cycles during division 8 16 32 onward Number of Accumulated time PLL lock frequency cycles (for 64 MHz PLL during division lock frequency) 8 x 8 = 64 4 x 16 = 64 2 x 32 = 64 1 usec 2 usec 3 usec - As shown above. RCDIV is a programmable field in the CMU_CSR register. the system clock changes from 16 MHz internal reference clock to a PLL output clock running at 64 MHz. 4 Freescale Semiconductor 101 . en_pll_sw bit. However. The table below illustrates how long this gradual increase takes. by reset default settings.) The effect is to gradually increase current consumption instead of a single large increase. the PLL output frequency. has a reset default of RCDIV = 0. If.

11. and is also not on the other devices covered here. TARGET_MODE= RUN0 S_TRANS ME_MCTL =0x4000 5AF0 ME_MCTL =0x4000 A50F wait for ME_GS[S_TRANS] = 0 S_ CURRENTMODE verify ME_GS[S_CURRENTMODE] = RUN0 1. DRUN=1 RCDIV=4 RCDIV=0 Pseudo Code MPC56xxB MPC56xxP MPC56xxS ME_ME = 0x0000 001D 40 MHz Crystal: CGM_ CMU_CSR = 0x0000 0000 (default value for MPC56xxP) - Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration. Rev. check status flags such as ME_GS[XOSC] for cause.5 Oscillator Stabilization Counter Both FIRC and SIRC have counting periods that are used after reset and when the oscillator is switched on. PDO=0 MVRON=1 DFLAON.2. Rev. MPC5604B/S Microcontroller Reference Manual. Table 45. using progressive clock switching: • 8MHz Crystal: FMPLL_CR=0x02400100 • 40MHz Crystal: FMPLL_CR=0x12400100 Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data. the reset default value in CGM_FXOSC_CTL[EOCV] for FIRC or CGM_SXOSC_CTL[EOCV] for SIRC may need to be changed before the oscillator is turned on. Config. MPC5606B. Table 3-9. On MPC56xxS “cut 1. • Verify current mode is desired mode NOTE: This step ensures a SAFE mode transition did not occur at this point. MPC56xxS Steps for PLL Example Step Init Modes and Clock Enable desired modes If necessary. code flash in normal mode (default) • PLL0 is switched on • Crystal oscillator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk MPC56xxB/S: • Peri.1: run in RUN0 mode only. This counting period ensures that the external oscillator clock signal is stable before it can be selected by the system.” CGM_FXOSC_CTL contained an oscillator enable bit which was disabled after reset. This control has been removed from MPC56xxS.EOCV description. MPC56xxP. adjust XOSC clock monitor frequency: • 8MHz Crystal: monitor Fxosc > 4 MHz • 40MHz Crystal: monitor Fxosc > 16 MHz Relevant Bit Fields RUN0. 4 102 Freescale Semiconductor .1 Depending on the crystal. CFLAON= 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0=1 8 MHz Crystal: 40 MHz Crystal: 8 MHz Crystal: CGM_ CGM_ CGM_ FMPLL_CR FMPLL[0]_CR FMPLL[0]_CR = 0x0240 0100 = 0x1240 0100 = 0x0240 0100 ME_RUN0_MC = 0x001F 0070 ME_RUN_PC1 = 0x0000 0010 Assign peripheral configuration to peripherals: • SIUL (MPC5500B/S) ME_PCTL68 = 0x01 Initiate software mode transition to RUN0 mode • Mode and key • Mode and inverted key • Wait for transition complete status flag NOTE: if transition does not complete.4 12 Aug 2009 Qorivva Simple Cookbook.

then to 16 MHz) Relevant Bit Fields EN=1 SELDIV = 2 SELCTL = 1 (MPC56xxB) 0 (MPC56xxP/S) Pseudo Code MPC56xxB MPC56xxP CGM_OCEN[EN] = 1 CGM_OCDSSC[SELDIV] = 2 CGM_OCDSSC [SELCTL] = 1 SIU_PCR[0] = 0x0800 CGM_OCDSSC [SELCTL] = 0 SIU_PCR[22] = 0x0400 SIU_PCR[103] = 0x0E00 MPC56xxS Assign output clock (CLKOUT) to pad: • MPC56xxB: PA[0] pad assignmt = alt func 2 • MPC56xxP: PB[6] pad assignmt = alt func 1 • MPC56xxS: PH[4] pad assignmt =option 3 Select crystal oscillator as output clock SELCTL = 0 (MPC56xxB) 1 (MPC56xxP/S) SELCTL = 2 CGM_OCDSSC [SELCTL] = 0 CGM_OCDSSC [SELCTL] = 1 Select PLL0 as output clock Disable Watchdog • Write keys to clear soft lock bit • Clear watchdog enable bit CGM_OCDSSC[SELCTL] = 2 SWT_SR = 0x000 0C520 SWT_SR = 0x0000 D928 SWT_CR = 0x8000 010A WEN = 0 Qorivva Simple Cookbook. MPC5606B. 4 Freescale Semiconductor 103 . then to XTAL/4.Table 45. MPC56xxS Steps for PLL Example (continued) Step Initialize Output Clock /4 Enable Output Clock to pin Select division of output clock by 4 Select 16 MHz IRC as output clock (CLKOUT goes from about 4 MHz. MPC56xxP. Rev.

GS.GS.R = 0x001F0074. /* Enter RUN0 Mode & Key */ ME.S_CURRENTMODE != 4){} /* Verify RUN0 is the current mode */ /* Note: This verification ensures a SAFE mode */ /* tranistion did not occur.R = 0x4000A50F. /* Initialize mode entries and system clock */ initOutputClock(). /* CGM. /* Assign output clock to FMPLL[0] */ /* CLKOUT = 64 MHz/4 = 4MHz */ void disableWatchdog(void) { SWT. */ /* 2. /* Enter RUN0 Mode & Inverted Key */ while (ME. Cfg.OCDS_SC.R = 0x40005AF0.R = 0x0800.h" /* Use proper include file */ void initModesAndClock(void) { ME. /* CGM. SAFE. SWT.SELCTL = 0.CR. /* SIU. 4 104 Freescale Semiconductor .c . 2010.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME. A timer could be used to prevent waiting forever. All rights reserved. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 1 of the next 2 lines depending on crystal frequency: */ CGM.MER.OC_EN.SR.simplified code */ Jun 24 2009 S Mihalik .RUN[0].SELCTL = 1. /* MPC56xxB/S: select ME.OCDS_SC.PCR[0].MCTL. /* Initialize Output Clock to 16 M.syclk=PLL0 */ ME.R = 0x8000010A.R = 0x02400100.SR. /* 8 MHz xtal: Set PLL0 to 64 MHz */ /*CGM.OSC0ON. /* Dummy idle counter */ } initModesAndClock().11.B.3. Rev.SELDIV = 2.*/ /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME.R = 0x0000001D.1 /* /* /* /* /* /* /* Code MPC56xxB with 8 MHz crystal main.RUNPC[1]. /* Write keys to clear soft lock bit */ SWT.FMPLL_CR.OCDS_SC. Inc 2009.B.PLL0ON.B.R = 0x0000c520.3 11.EN = 1.R = 0x0000d928. /* RUN0 cfg: 16MHzIRCON.R = 0x01. /* Peri.B.PCTL[68]. 1 settings: only run in RUN0 mode */ ME.R = 0x00000010.PLL example for MPC56xxB */ Description: Set sysclk to FMPLL0 running at 64 MHz & enable CLKOUT */ Jan 14 2009 S Mihalik .*/ while(ME.R = 0x12400100.MCTL. } Qorivva Simple Cookbook. RUN0. /* Clear watchdog enable (WEN) */ } void main (void) { vuint32_t i = 0. */ #include "MPC5604B_0M27V_0102. /* Disable watchdog */ while (1) { i++. SW could instead */ /* enable the safe mode tranision interupt */ } void initOutputClock(void) { CGM.B.Initial version */ May 22 2009 S Mihalik .B. XOSC.B.SELCTL = 2. /* MPC56xxB: Assign output clock to XTAL */ /* CLKOUT = Fxtal/4 = 2 or 10 MHz for 8 or 40 MHx XTAL*/ } CGM. I_TC IRQ could be used here instead of polling */ /* to allow software to complete other init.Modified initModesAndClock & updated header file */ Copyright Freescale Semiconductor.S_MTRANS == 1) {} /* Wait for mode transition to complete */ /* Notes: */ /* 1. /* /* Output Clock enabled (to go to pin) */ Output Clock’s selected division is 2**2 = 4 */ MPC56xxB: Output clock select 16 MHz int RC osc */ MPC56xxB: assign port PA[0] pad to Alt Func 2 */ CLKOUT = 16 MHz IRC/4 = 4MHz */ CGM.FMPLL_CR.OCDS_SC. /* Enable DRUN.Simplified code */ Mar 10 2010 S Mihalik . then PLL */ disableWatchdog().

B.OCDSSC.SR.R = 0x0000d928.B. SAFE. /* Initialize Output Clock to 16 M.R = 0x0400.B. /* Initialize mode entries and system clock */ initOutputClock(). /* Clear watchdog enable (WEN) */ } void main (void) { vuint32_t i = 0. no PLL monitor */ /*CGM.3.MCTL.SELCTL = 1.2 /* /* /* /* /* /* /* MPC56xxP with 40 MHz crystal main. Inc 2010 All rights reserved.EN = 1.Initial version */ May 11 2009 S.*/ /* 8 MHz xtal: Set PLL0 to 64 MHz */ CGM.R = 0x40005AF0. */ /* 2.MER. SW could instead */ /* enable the safe mode tranision interupt */ } void initOutputClock(void) { CGM. Rev. RUN0.R = 0x0000001D. /* Enable DRUN.PLL0ON.PLL example for MPC56xxP */ Description: Set sysclk to FMPLL0 running at 64 MHz & enable CLKOUT */ Jan 14 2009 S. } Qorivva Simple Cookbook.CMU_0_CSR. /* Enter RUN0 Mode & Inverted Key */ while (ME. CGM.B.GS.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ /* Note: This verification ensures a SAFE mode */ /* tranistion did not occur.h" /* Use proper include file */ void initModesAndClock(void) { ME.R = 0x12400100. Mihalik .SR.CR. XOSC.Modified initModesAndClock & updated header file */ Copyright Freescale Semiconductor.Simplified code */ Jun 24 2009 S. /* RUN0 cfg: 16MHzIRCON. */ #include "Pictus_Header_v1_09. /* Output Clock’s selected division is 2**2 = 4 */ CGM.CR.SELCTL = 0. /* Dummy idle counter */ } initModesAndClock(). A timer could be used to prevent waiting forever*/ while(ME.CR. /* Output Clock enabled (to go to pin) */ CGM. I_TC IRQ could be used here instead of polling */ /* to allow software to complete other init.S_MTRANS == 1) {} /* Wait for mode transition to complete */ /* Notes: */ /* 1. Mihalik . /* Monitor FXOSC > FIRC/1 (16MHz).GS. SWT. /* Enter RUN0 Mode & Key */ ME.OCDSSC. Mihalik . /* Write keys to clear soft lock bit */ SWT.R = 0x0000c520.*/ /*Monitor FXOSC > FIRC/4 (4MHz).CMU_0_CSR.FMPLL[0].syclk=PLL0*/ /* Mode Transition to enter RUN0 mode: */ ME.R = 0x4000A50F.SELDIV = 2.B.OCDSSC.RUN[0]. /* MPC56xxP: assign port PB[6] pad to Alt Func 1 */ /* CLKOUT = 16 MHz IRC/4 = 4MHz */ CGM. no PLL monitor*/ CGM.OCEN. /* MPC56xxP/S: Output clock select 16 MHz int RC osc */ SIU.PCR[22].c .Simplified code */ Mar 10 2010 S Mihalik . /* Disable watchdog */ while (1) { i++.R = 0x8000010A.MCTL. 4 Freescale Semiconductor 105 .R = 0x02400100.SELCTL = 2. } /* MPC56xxP/S: Assign output clock to XTAL */ /* CLKOUT= Fxtal/4 = 2 or 10 MHz for 8 or 40 MHx XTAL*/ /* Assign output clock to FMPLL[0] */ /* CLKOUT = 64 MHz/4 = 4MHz */ void disableWatchdog(void) { SWT.R = 0x000000004.FMPLL[0]. /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 2 of the next 4 lines depending on crystal frequency: */ /*CGM.R = 0x001F0074. then PLL */ disableWatchdog().B.11.B.OSC0ON.R = 0x000000000.OCDSSC.

CR. I_TC IRQ could be used here instead of polling */ /* to allow software to complete other init. /* Assign output clock to FMPLL[0] */ /* CLKOUT = 64 MHz/4 = 4MHz */ void disableWatchdog(void) { SWT.Initial version */ May 22 2009 S Mihalik .B.R = 0x0E00. Inc 2010 All rights reserved. XOSC.RUN[0]. /* Write keys to clear soft lock bit */ SWT.Simplified and verified for cut 2 silicon */ Mar 10 2010 S Mihalik .MCTL.OCDS_SC.OSC0ON. /* Disable watchdog */ while (1) { i++.R = 0x001F0074.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ /* Note: This verification ensures a SAFE mode */ /* tranistion did not occur. then PLL */ disableWatchdog().SELCTL = 1. RUN0.3 /* /* /* /* /* /* /* MPC56xxS with 8 MHz crystal main.Simplified code */ Jun 24 2009 S Mihalik .R = 0x01. Rev.R = 0x0000d928. /* SIU. /* MPC56xxB/S: select ME. A timer could be used to prevent waiting forever*/ while(ME.CR. /* CGM. /* Dummy idle counter */ initModesAndClock().MCTL.MER. } } Qorivva Simple Cookbook. /* Enter RUN0 Mode & Key */ ME.B.B. /* Enter RUN0 Mode & Inverted Key */ while (ME. 4 106 Freescale Semiconductor .B.R = 0x4000A50F.R = 0x8000010A. /* /* Output Clock enabled (to go to pin) */ Output Clock’s selected division is 2**2 = 4 */ MPC56xxP/S: Output clock select 16 MHz int RC osc */ MPC56xxS: assign port PH[4] pad to Opt 3 (untested)*/ CLKOUT = 16 MHz IRC/4 = 4MHz */ CGM.OCDS_SC.R = 0x40005AF0.RUNPC[1].PCTL[68].PLL example for MPC56xxS */ Description: Set sysclk to FMPLL0 running at 64 MHz & enable CLKOUT */ Jan 14 2009 S Mihalik .PCR[103].OCDS_SC. SW could instead */ /* enable the safe mode tranision interupt */ } void initOutputClock(void) { CGM. /* Enable DRUN.R = 0x02400100.GS. /* Initialize mode entries and system clock */ initOutputClock().R = 0x12400100.Modified initModesAndClock & updated header file */ Copyright Freescale Semiconductor.c .PLL0ON.GS.OC_EN. Cfg.FMPLL[0].B.SELDIV = 2.B.B.SELCTL = 0.SR. /* Initialize Output Clock to 16 M.R = 0x0000001D.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 1 of the next 2 lines depending on crystal frequency: */ CGM.R = 0x00000010.*/ /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME.EN = 1. /* 8 MHz xtal: Set PLL0 to 64 MHz */ /*CGM.11. */ /* 2.R = 0x0000c520. SAFE.FMPLL[0]. /* Clear watchdog enable (WEN) */ } void main (void) { vuint32_t i = 0.S_MTRANS == 1) {} /* Wait for mode transition to complete */ /* Notes: */ /* 1.OCDS_SC. /* Peri. SWT.h" /* Use proper include file */ void initModesAndClock(void) { ME. 1 settings: only run in RUN0 mode */ ME. */ #include "56xxS_0204.SR.syclk=PLL0 */ ME.SELCTL = 2. /* MPC56xxP/S: Assign output clock to XTAL */ /* CLKOUT = Fxtal/4 = 2 or 10 MHz for 8 or 40 MHx XTAL */ } CGM.3. /* RUN0 cfg: 16MHzIRCON. /* CGM.CR.

4 Freescale Semiconductor 107 . with a depth of 1% and a rate of sysclk/40. which varies with the amount of frequency change. This implementation is done using C code in the main function for illustration. FMPLL Example Table 46.12 12. Enable frequency modulation (FM). ramping up in two steps. Initially CLKOUT will be 1/2 of the 12 MHz reset default frequency (163 ns). CLKOUT default frequency is one half of sysclk frequency (Fsys) as defined by SIU_ECCR[EBDF]. In real life a maximum timeout mechanism would be implemented. initialize the FMPLL to provide an 80 MHz system clock. The program simply waits for the desired status to occur. This example uses two frequency increases and therefore has lower immediate current increase than if it were done in one step. This example tests the PLL for LOCK and FM status.1 FMPLL: Frequency Modulation Description Task: Assuming an 8 MHz crystal. Increasing the PLL frequency produces a brief current demand from the power supply. CLKOUT at Fsys = 40 MHz is 50 ns. Filter. If LOCK was not achieved in a maximum time. to speed up the rest of initialization. then one might log an error message and reset the part. which does not cause change of lock because the divider is after the feedback path. Normally the PLL would be initialized in assembly language soon after reset. Current Controlled Oscillator fico FM Control Fsys (sysclk) RFD SIU CLKOUT EBDF Crystal 8 MHz Fref PREDIV Figure 23. Exercise: Measure CLKOUT frequency. Rev. at Fsys = 80 MHz is 25 ns. – Package Pin No. MPC5500 MFD FMPLL PFD / Charge Pumps. 496 BGA AF25 416 BGA AE24 324 BGA AA20 208 BGA – Signal CLKOUT CLKOUT Qorivva Simple Cookbook. Signals for FMPLL Example MPC555x Family Function Name SIU PCR No. The second increase changes only the RFD. for a selected number of iterations. If FM status is not correct then software could loop back and try again.

PREDIV=0. The expected difference value (EXP) is calculated per the formula in the MPC5554 Reference Manual.4.1: (MFD + 4)  M  P (6 + 4)  480  1 EXP = -------------------------. RFD = 0. M = 480. but not MPC563x.= ----------------------------((0 + 1)  20) ((PREDIV + 1)  2RFD) 1 Fref 8 MHz From this we can see that in this case.4. the loss-of-lock circuitry and interrupts would not be enabled until after these steps. The PLL will not exit reset until it has locked. Rev 1.= -----------. Qorivva Simple Cookbook.= ---.= ----------------------. the system frequency plus the 1% or 2% depth must not exceed the device’s rated maximum system frequency. derive target values as shown below using the formula for Fsys: Fsys (MFD + 4) (6 + 4) 80 MHz 10 -----. for Fsys the target values are: MFD = 6. The formula for system clock is: (MFD + 4) Fsys = Fref  -----------------------------((PREDIV + 1)  2RFD) NOTE When using Frequency Modulation.12. 4 108 Freescale Semiconductor . Because changing PREDIV or MFD. then it is lowered in a second step to the target frequency. For a target MFD of 6. These values provide an ICO frequency (fico) of 80 MHz. section 11.4. The percent depth (P) is 1.= -----------------. Now the bit field values for Frequency Modulation can be determined. which is within the specification of the MPC5554 Data Sheet. or enabling FM. Initially software will set the RFD to the next higher value (RFD = 1). For an 8 MHz crystal (Fref) and a target frequency of 80 MHz (Fsys). can cause loss of lock.2 Design This example applies to MPC555x devices.= 48 100 100 Loss of lock and loss of clock detection is not enabled in this example. Rev.

FMPLL example */ Rev 1.LOCK != 1) {}.wait forever */ void initFMPLL(void) { FMPLL. } /* Wait forever */ } Qorivva Simple Cookbook. Wait for PLL to lock. /* Wait for FMPLL to LOCK again */ if ((FMPLL.SYNCR. Verify calibration completed and successful.CALDONE != 1) | (FMPLL.B. Rev. 4 Freescale Semiconductor 109 . 5.SYNCR. 3.3 /* /* /* /* /* /* Code main.B. Go to target frequency (80 MHz).LOCK != 1) {}.SYNSR. Cache is not used */ */ #include "mpc5554.SYNSR.0 Sept 21 2004 S. /* Dummy counter */ initFMPLL(). */ Notes: */ 1.R = 0x03080430. ECC in L2SRAM is not initialized here.R = 0x03080030.B.c .SYNSR. Mihalik Copyright Freescale Semiconductor.Table 47. FMPLL: Frequency Modulation Design Steps Step 1. /* Initial setting: 40 MHz for 8 MHz crystal*/ while (FMPLL. /* Final setting: 80 MHz for 8 MHz crystal */ } void main (void){ int i=0.h" void errorLog (void){ while (1) {} } /* Placeholder for FMPLL error .R = 0x03000430. /* Error if calibration is not done or did not pass */ } FMPLL.SYNCR. Enable FM: • Set DEPTH to 1% • Set RATE 4.B.CALPASS != 1)) { errorLog(). /* Initialize FMPLL for 80 MHz & 1% Frequency Modulation depth */ while (1) {i++. /* Enable FM */ while (FMPLL. /* Wait for LOCK = 1 */ FMPLL. Relevant Bit Fields EXP = 0x30 MFD = 6 PREDIV = 0 (default) RFD = 1 DEPTH = 0 (default) wait for LOCK = 1 DEPTH = 1 RATE = 1 (Fref / 40) wait for LOCK = 1 CALDONE = 1 CALPASS = 1 RFD = 0 wait for FMPLL_SYNSR[LOCK] = 1 if ((FMPLL_SYNSR[CALDONE != 1) or (FMPLL_SYNSR[CALPASS] != 1)) then log an error FMPLL_SYNCR = 0x0300 0430 wait for FMPLL_SYNSR[LOCK] = 1 FMPLL_SYNCR = 0x0308 0430 Pseudo Code FMPLL_SYNCR = 0x0308 0030 6. Wait for PLL to re-lock (relocks after CALDONE = 1). 12. Inc. Initialize PLL for less than desired frequency (40 MHz).SYNSR. • EXP value based on calculation = 48 (0x30) • Multiplication Factor Divider = 6 • PREDIVider = 0 • Initial Reduced Frequency Divider = 1 • Keep Frequency Modulation disabled for now 2. 2004 All rights reserved. must be done by debug scripts 2.

you cannot go back to STANDBY. because the pad would enter high impedance and be pulled up or down depending on the external resistor. Software will configure STOP mode to maintain the I/O pin states (using MC_STOP_MC[PDO] field). In STANDBY mode. At this point. the output goes to the high impedance state so the pad is pulled back up or down according to the circuit. After the first wakeup timeout (WT1). By entering STANDBY. Repeat until a pin transition occurs. After the WT2 wakeup timeout. Modes and Wakeup Timeouts WT1 & WT2 DRUN RUN3 DRUN Current (approx. the processor is in DRUN mode and software should verify that the reason for entering DRUN was the desired wakeup event. This example uses RTC. Therefore. Exercise: Change timeouts for a new period and duty cycle. pulse an output pin to a 10% “on” duty cycle approximately every second (~0. Software here simply re-initializes the wakeup timer to the first value and then re-enters STANDBY mode.13 13. a single longer timeout. STOP mode exits back to the previous RUNx mode with the instruction pointer unchanged. then ~0. relative levels) RUN3 DRUN RUN3 DRUN pin transition wakeup event STOP STANDBY WT1 WT2 STANDBY WT1 Time STOP WT2 WT1 Qorivva Simple Cookbook. STANDBY mode exits and the processor goes to the RESET vector or 0x4000 0000 in SRAM if RGM_STDBY[BOOTFROM_BKP_RAM] is set. There are two wakeup event timer choices: Autonomous Periodic Interrupt (API) for multiple regular (periodic) short timeouts. However. Figure 24.9 seconds off. and Real Time Counter (RTC).1 seconds on). 4 110 Freescale Semiconductor . outputs other than wakeup inputs with enabled pullups are always in high impedance state. Therefore STOP mode is used instead of STANDBY for this second shorter wake up timeout (WT2). Software then turns on the LED and sets up the new wakeup timeout (WT2).1 Modes: Low Power (MPC56xxB/S) Description Task: Using lowest power modes. STANDBY should be used for the longer of the two wakeup timeouts (WT1 in this example) with possibly either a pullup or pulldown resistor externally connected to acheive the desired ON or OFF output state such as to an LED. Rev. then enter STOP mode from a RUNx mode. because the new output state must be maintained at the pad.

2. Unlike power domains PD0 and PD1. 13. Hence we need to re-initialize registers in PD0 and PD1 when exiting STANDBY mode. peripherals ME_DRUN_MC register DRUN RUN3 STOP STANDBY 1 Power Domain PD1 Configuration Register PCU_PCONF1 Power Domain PD2 Configuration Register PCU_PCONF2 Domain Modules: Additional SRAM Powered Powered Powered Powered Powered Powered Powered Not Powered Configurable Configurable Configurable Configurable ME module exception: ME_DRUN_MC register is powered during STANDBY. Table 48. Powered Domains vs. Modules Hardware is used to control switching power on and off to primary power domains (PD0 and PD1) based on the mode being entered to conserve current. FIRC. Summary of Powered Modules by Mode and Domain for MPC56xxB/S Mode Entry Low Power example (See chapters in reference manual on “Power Control Unit and Voltage Regulators” and “Power Supplies”) Power Domain PD0 Configuration Register PCU_PCONF0 Mode Domain Modules: Domain Modules: PCU. WKPU. • RTCVAL: for longer timeouts. (See RTC/API block diagram in the device reference manual chapter. SIUL.2 • • • • RTC/API Clock Selection and Configuration One of three clock sources below can be selected for the RTC counter clock source: 128 kHz SIRC (Slow Internal Reference Clock) with optional divider in CGM_SIRC_CTL 16 MHz FIRC (Fast Internal Reference Clock) with optional divder in CGM_FIRC_CTL 32 kHz SXOSC (“Slow” External Oscillator) MPC56xxS only: 4–16 MHz FXOSC (“Fast” External Oscillator) The selected clock can be also divided by 512 and/or 32 in RTC_RTCC before clocking the 32-bit RTC counter. is always enabled when RTC counter is running Qorivva Simple Cookbook.13. Flash. power for PD2 is configurable by software writing to the PCU_PCONF2 register. Core. “Real Time Clock / Autonomous Periodic Interrupt. 4 Freescale Semiconductor 111 . MC_ME1. When a domain is powered off. MC_CGM.2. most peripherals. RGM. mode entry configurations. Each timeout compares a programmable value to the 32-bit RTC counter. CAN Sampler. FMPLL.”) There are two timeouts that can occur and each can generate a wakeup event or interrupt request. etc. From the table below we can see that going to STANDBY mode cuts power to core. Rev. then of course all initialization or other data is lost for registers and memory in that domain. but not other modes such as STOP mode. clocks. SIRC.1 Design Modes vs. other 8K SRAM.2 13.

Other resets do not change its value.9 seconds and WT2 = 0.25 sec 8 sec ~2. set the RTC value in RTC_RTCC[RTCVAL] to its current RTCVAL plus an offset.25 kHz ~977 Hz 32 kHz 1 kHz 62.024 msec 31.3 min ~2.1 seconds. We will use the 128 kHz SIRC divided by 4 (32 kHz) for a clock source without other dividers.023 sec ~16 sec ~524 sec ~128 sec ~4.5 days ~1. or GGM_LPRC_CTL[LPRCDIV] for MPC56xxS. FXOSC as RTC/API option avaialble only in MPC56xxS.)) period) div512 div 32 128 kHz SIRC1 with SIRCDIV =0 16 MHz FIRC2 (125 x SIRC) 0 0 1 1 0 0 1 1 32 kHz SXOSC3 or 128 kHz SIRC/44 FXOSC 5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 128 kHz 4 kHz 250 Hz 7. 4 112 Freescale Semiconductor .5 sec 16 sec ~4. where the offset is the next desired delay in terms of appropriate RTCCNT units.5 days ~1.1 min ~1.5 Hz ~2 Hz 8 MHz 250 kHz 15.048 msec ~33 msec ~1049 sec 32 msec 1.6 hrs ~3 days ~3. not available in STANDBY mode.25 sec 1 msec 16 msec 512 msec 125 nsec 4 sec 64 sec 2.2 mo 0 0 1 1 0 0 1 1 1 2 3 4 5 SIRC is divided by 4 to 32 kHz using reset default value in CGM_SIRC_CTL[SIRCDIV] for MPC56xxB.6 mo ~1.8125 Hz 16 MHz 500 kHz 31.048 msec ~ 8 msec ~ 256 msec ~ 4.1 hrs ~2. 32 kHz SXOSC not available in STANDBY mode.• APIVAL: for shorter regular timeouts.09 sec ~131 sec ~64 sec ~2 msec ~33 msec ~1048 sec ~32 msec 1. Table 49.3 min ~2.8 hrs ~1.5 nsec 2 sec 32 sec 1.4 hrs ~6 days 0.1 min ~1.1 hrs ~18 hrs ~24 days 0. and Timeout Examples for MPC56xxB/S RTC Counter RTC Counter Min. Note that the RTC Counter Register (RTCCNT) only clears on Power On Reset. Our target wakeup timeouts are WT1= 0. API Max.3 hr ~8. RTC Max.1 msec ~66 msec ~2.8 sec 250 sec 4 msec 128 msec 62.9 seconds and SIRC uses less power than FIRC.1 sec ~31 sec ~17 min ~4.1 yrs ~67 yrs ~8. RTC RTC Rollover Min. Divider. and whether to use the 512 and/or 32 clock dividers.25 sec 1 msec 16 msec 512 msec 125 nsec 4 sec 64 sec 2.048 msec ~7.10 sec ~131 sec 64 sec 2.6 min ~4.6 mo ~2. SIRC is divided by 4 to 32 kHz using reset default value in CGM_SIRC_CTL[SIRCDIV] for MPC56xxB.8 sec 250 sec 4 msec 128 msec 62. Once we know our wakeup timeout(s).9 hrs ~12 days ~6. since the range of min to max RTC timeouts meets our criteria of 0. or GGM_LPRC_CTL[LPRCDIV] for MPC56xxS.1 sec ~ 8 msec 256 msec ~4. Rev.024 msec 31.024 sec ~16 sec ~524 sec ~128 sec ~4. Wakekup source is RTC. must be enabled separately The following table provides useful calculations for various clock sources and dividers for RTC and API timeouts. When using the RTC.5 nsec 2 sec 32 sec 1. Also.1 msec ~65 msec ~2. API Input Clock Input Clock Timeout Timeout Timeout Timeout Timeout Clock Frequency Period (2 10  ((2 22 – 1) x (2 32  (1  ((2 10 – 1) x RTC_ RTC_ Source (1 / (RTC RTC Counter RTC Counter RTC Counter RTC Counter RTC Counter RTCC RTCC input clock input clock input clock input clock Counter Input input clock [div512] [div32] period) period) period) period) Clock Freq. whether to use API or RTC wakeup.3 mo ~17 yrs ~4. we can use this table to decide on a clock source. Qorivva Simple Cookbook.1 and 0.625 kHz ~488 Hz ~7. FIRC is divided by 1 using reset default value in CGM_RC_CTL[RCDIV] for MPC56xxB. RTC/API Clock. MPC56xxS.

13. Wakeup IRQ to INTC WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 One or more pins can be selected for generating a wakeup per the following table.a.3 Pin Transition Selection and Configuration Table 50. 5. input pulses less than 40 ns (WFI) are filtered (rejected). These ports can be configured for rising and/or falling edge detection. Reference: MPC5604BC Data Sheet. 4 Freescale Semiconductor 113 .a. November 2009.2. Rev. “I/O Input DC electrical characteristics. PCR1 PCR2 PCR17 PCR43 PCR64 PCR73 PCR26 PCR4 PCR15 PCR19 PCR39 PCR41 PCR75 PCR91 PCR93 PCR99 PCR101 PCR0 (none) Wakeup IRQ to INTC WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_0 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_1 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 WakeUp_IRQ_2 (none) Port PA0 PB1 PB3 PB4 PB9 PB10 PB12 PC0 PC10 PF0 PF2 PF3 PF5 PF6 PF8 PF11 PF13 PJ4 PJ6 API RTC MPC560xS SIU_PCR PCR0 PCR17 PCR19 PCR20 PCR25 PCR26 PCR28 PCR30 PCR40 PCR70 PCR72 PCR73 PCR75 PCR76 PCR78 PCR81 PCR83 PCR108 PCR111 n. Rev. greater than 1000 ns (WNFI) are not filtered.” Qorivva Simple Cookbook. When the filter is enabled. 1. n. Wakeup Sources (Not all ports are available in all packages — see device reference manual) MPC560xB Wakeup Number WKUP0 WKUP1 WKUP2 WKUP3 WKUP4 WKUP5 WKUP6 WKUP7 WKUP8 WKUP9 WKUP10 WKUP11 WKUP12 WKUP13 WKUP14 WKUP15 WKUP16 WKUP17 WKUP18 WKUP19 WKUP20 Port API RTC PA1 PA2 PB1 PC11 PE0 PE9 PB10 PA4 PA15 PB3 PC7 PC9 PE11 PF11 PF13 PG3 PG5 PA0 (none) SIU_PCR # n.a. n. WFI and WNFI parameters. An analog filter can be enabled in WKUP_WIFER which prevents glitches on those pins. Table 12.a. and those with widths in between may or may not get filtered1.

2. this could be written in assembly and have a shorter boot sequence. If booting from SRAM and writing C code. if booting from SRAM and only writing a small amount of code. configure RTC wakeup of WT1 and enter STANDBY mode (outputs return to high impedance in STANDBY mode). Rev. This example is implemented using the RTC and takes the key actions below based on the following reset causes: • Reset event: Configure RTC wakeup of WT1 duration and enter STANDBY mode (outputs are in high impedance in STANDBY mode). there needs to be an initialization (such as initializing the stack pointer and small data areas). 13. STANDBY exit with API 1/10th second wakeup Simply increment an API wakeup counter in SRAM that is kept alive (in Power domain 0). set up a 1/10th second PIT interrupt and execute a WAIT instruction (instead of going back to a low power mode). Alternative implementations could be based on using the API. Two options are: 1. • Wakeup event: Set an output pin. On STOP mode exit (from RTC timeout of WT2). The amount of power savings when booting from RAM and STANDBY wakeup varies by application. there are two options for code execution depending on the configuration of RGM_STDBY[BOOT_FROM_BKP_RAM]: • System boots from flash on STANDBY exit (reset default) • System boots from backup RAM on STANDBY exit Configuring system boot from backup RAM has two advantages: 1.2. 4 114 Freescale Semiconductor . so instruction execution resumes in that mode from the next instruction. At the PIT interrupt go back to STANDBY and wait for STANDBY wakeup. Reason: flash does not need to be power sequenced. 2. power the desired pad.13. Faster startup time. This example does not use the feature to boot from backup RAM on standby wakeup. 2. However. On the next API wakeup.4 STANDBY Wakeup: Execute from Flash or RAM? When exiting STANDBY mode by pin transition or timer wakeup. configure RTC wakeup of WT2 duration and enter STOP mode. Qorivva Simple Cookbook. • Pin wakeup event (final wakeup for this example): wait forever (do not enter more low power modes). STANDBY exit with API 1 second wakeup On API wakeup from STANDBY. reset the counter and go back to STANDBY. Wakeup from STOP mode exits to the RUNx MODE that was used previously. Enables lower power consumption. At the 9th wakeup. go into STOP mode with the desired pad powered. Reason: the flash does not need to be fully powered.5 Reset and Wakeup Strategy Summary After reset. which is part of a normal compiler initialization on reset. but boots from flash after reset and BAM code execution. without any reset. the processor is in DRUN mode and software must determine the cause of reset.

To avoid the debugger losing connection. or 8. then an error condition could be recorded in EEPROM or elsewhere.7 Mode Use This example simply polls a status bit to wait for the targeted mode transition to complete. When enabled. not all registers are reset as in a power-up reset. 13. However. ME _DRUN_MC register and PCU registers. low power exit takes longer because the state machine adds steps to wait until after a handshake to the debugger and the debugger response to the handshake completes. including to the debugger connection. It is normal to use a timer when waiting for a status bit to change. etc.2. Options are SYSCLK divided by 1 (default). To maintain a debugger connection. CAN SAMPLER registers. the Nexus Development Interface (NDI) module contains features to maintain a debugger connection.NOTE Some MPC56xx device documentation list more than one STOP0. This would allow software to complete other intialization tasks instead of brute force polling of the status bit. 13. NOTE Although STANDBY exit causes a reset. and therefore possibly asserting a reset. so the “0” suffix is not used in this write up. Debuggers may or may not implement this feature. but must be used for coding register names if applicable.2. These registers are not memory mapped. The controls to maintain the debugger connection are in the Port Configuration Register (PCR) of the Nexus Development Interface module. Rev. One could also loop code on incrementing a software counter to some maximum value as a timeout.6 Debugging with Low Power Modes By default. 2. etc. 4. low power modes shut off as much power as possible. This example by default would have a watchdog timer expire if for some reason the mode transition never completes. or STANDBY0 mode. including: RGM registers. the debugger should set the following: • PCR[LP_DBG_EN] Low Power Debug Enable: Enables debug functionality to support exit from any low power mode. Qorivva Simple Cookbook. the status bit could instead be enabled to generate an interrupt request (assuming the INTC is intialized beforehand). HALT0. • PCR[MCKO_DIV] MCKO Divistion Factor: Determines MCK0 relative to system clock frequency. Users should use appropriate debugger scripts to configure these settings. 4 Freescale Semiconductor 115 . The devices for this example only have one such mode each. • PCR[MCKO_EN] MCKO Enable: Enables clock which will be used in debugger connection. If a timeout was reached. Power domain 0 registers are not reset. Debug functionality is immediately available for breakpoints. RTC registers. and are only accessible through the debugger.

& Main Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET Use PC7: Low Pwr Wake up ME_ RUNPC_ 7 1 0 0 0 1 0 0 0 Peripherals Selecting Configuration Peripheral SIUL WKPU RTC/API PCTL Reg. 4 116 Freescale Semiconductor . The following table summarizes the peripheral configurations used here.ME_STANDBY 0x0085 000F BY0 _MC Other modes are not used in example. Config. Low Power Peripheral Configurations for MPC56xxB/S Mode Entry Low Power Example PeriPeri. # 68 69 91 Other peripheral configurations are not used in example. Register Value sysclk Selection PLL1 (MPC 56xxP/ S only) Off Off — Memory Power Mode Data Flash 16 MHz XOSC0 PLL IRC 0 On On Off Off Off Off Off Off Off I/O Main Power Voltage Down Code Reg. Disabled Off — — — Pwr Dn Pwr Dn Off On Peripherals also have configurations to gate clocks on and off. # 68 69 91 Other peripheral configurations are not used in example. Register STANDBY0 PC7: Low Pwr I/O ME_ LPPC_ 7 0 1 Peripherals Selecting Configuration HALT 0 Peripheral SIUL WKPU RTC/API PCTL Reg. Table 53. Run Peripheral Configurations for MPC56xxB/S Mode Entry Low Power Example PeriEnabled Modes pheral Peri. Ctrl Flash On On Off Off Off Off DRUN ME_DRUN_MC 0x001F 0010 (default) 16 MHz IRC 16 MHz IRC Disabled Normal Normal Pwr Dn Normal Pwr Dn Pwr Dn RUN3: ME_RUN3_MC 0x001F 0010 Wakeup STOP: ME_STOP_MC 0x0005 000F Hold Pin States: STAND. Rev. Register Clock Sources Mode Config. Qorivva Simple Cookbook. Enabled Modes pheral Config. enabling low power. Config. STOP Config. Mode Configurations Summary for MPC56xxB/S Mode Entry Low Power Example Modes are enabled in ME_ME register Settings Mode & Main Use Mode Config. Table 52.Table 51.

CFLAON=1 • 16 MHz IRC is switched off 16MHz_IRCON=0 • sysclk is disabled SYSCLK=0xF Configure STANDBY Mode: • Main Voltage regulator is (always) off • 16 MHz IRC is switched off • sysclk is (always) disabled MVRON=0 16MHz_IRCON=0 SYSCLK=0xF ME_STOP0_MC = 0x0005 000F ME_STOP_MC = 0x0005 000F ME_STANDBY0_MC = 0x0085 000F ME_STANDBY_MC = 0x0085 000F Peripheral Configurations: • Run Peri.13. Cfg. check status flags such as ME_GS[XOSC] • Verify desired target mode was entered ME_MCTL =0x7000 5AF0 ME_MCTL =0x7000 A50F wait for ME_GS[S_MTRANS] = 1 verify ME_GS[S_CURRENT_MODE] = RUN3 Qorivva Simple Cookbook. 7: run in STOP STOP = 1 Assign peripheral configuration to peripherals: • SIUL: select ME_RUN_PC7. STOP WEN = 0 SWT_SR = 0x000 0C520 SWT_SR = 0x0000 D928 SWT_CR = 0x8000 010A ME_ME = 0x0000 248D ME_DRUN_MC = 0x001F 0010 ME_RUN3_MC = 0x001F 0010 Configure DRUN. RUN3 Modes: • I/O Output power-down: outputs not disabled PDO=0 • Main Voltage regulator is on MVRON=1 • Data. CFLAON = 3 • PLL0 is switched off PLL0ON=0 • Crystal oscilator is switched off XOSC0ON=0 • 16 MHz IRC is switched on (default) 16MHz_IRCON=1 • Select FIRC (16 MHz) as sysclk SYSCLK=0x0 Configure STOP Mode: • I/O Output power-down: outputs not disabled PDO=0 • Main Voltage regulator is off MVRON=o • Data. 7: run in DRUN. RUN3 = 1 • Low Pwr Peri. RUN_PC.8 Steps and Pseudo Code Table 54. wait for mode transition from STANDBY to complete. RUN3.2. 4 Freescale Semiconductor 117 . LP_PC to latch • Mode and key TARGETMODE = • Mode and inverted key RUN3 • Wait for mode transition complete status flag S_MTRANS NOTE: if transition does not complete. code flash in power-down mode DFLAON=1. Cfg. Rev. RUN3 modes DRUN. ME_LP_PC7 LP_CFG = 7 • RTC/API: select ME_RUN_PC7. ME_LP_PC7 If necessary. Initial Steps for MPC56xxB/S Mode Entry Low Power Example Step Relevant Bit Fields Pseudo Code MPC56xxB MPC56xxS Disable • Write keys to clear soft lock bit Watchdog • Clear watchdog enable bit Init Modes and sysclk Enable desired modes: DRUN. ME_LP_PC7 RUN_CFG = 7 • WKPU: select ME_RUN_PC7. code flash in normal mode DFLAON = 3. STANDBY. S_MTRANS ME_RUN_PC7 = 0x0000 0088 ME_LP_PC7 = 0x0000 0400 ME_PCTL68 = 0x3F ME_PCTL69 = 0x3F ME_PCTL91 = 0x3F while MS_GS[S_MTRANS] = 1 Initiate software mode transition to same mode to enable PCTLs.

Initial Steps for MPC56xxB/S Mode Entry Low Power Example (continued) Step Reset Source Determination and Action If destructive reset event. call function: ResetEvent If functional reset event.Table 54. call function: RTCWakeup function If pin transition wakeup from: • MPC56xxB: PE[0] • MPC56xxS: PA[0] wait forever else wait forever (should never get here!) 56xxB: EIF6 56xxS: EIF0 Relevant Bit Fields RGM_DES flags RGM_FES flags 56xxB: EIF1 56xxS: EIF20 Pseudo Code MPC56xxB MPC56xxS if (RGM_DES != 0) ResetEvent if (RGM_FES != 0) ResetEvent if WKUP_WISR[EIF1] RTCWakekupEvent if WKUP_WISR[EIF6] while 1 while 1 if WKUP_WISR[EIF20] RTCWakekupEvent if WKUP_WISR[EIF0] while 1 Qorivva Simple Cookbook. Rev. 4 118 Freescale Semiconductor . call function: ResetEvent If RTC wakeup.

_WIREER = = 0x0000 0002 0x0010 0001 WKUP_WIFER = 0x0000 0002 WKUP_WRER = 0x0000 0002 WKUP_WIPUER =0x000F FFFF WKUP_WISR = 0x0000 FFFF WKUP_WIFER = 0x0000 0001 WKUP_WRER = 0x0010 0001 WKUP_WIPUER =0x001F FFFF WKUP_WISR = 0x0001 FFFF clear RGM_DES & RGM_FES flags ME_MCTL = 0xD000 5AF0 ME_MCTL = 0xD000 A50F while 1 Qorivva Simple Cookbook._WIREER WKUP. 4 Freescale Semiconductor 119 . then use WAIT instruction Processor now in STANDY mode Relevant Bit Fields MPC56xxB SIRCON_STDBY=1 SIRCDIV = 3 CNTEN = 0 CGM_SIRC_CTL = 0x0000 0301 MPC56xxS CGM_LPRC_CTL = 0x0000 0300 RTC_RTCC = 0x0000 0000 RTC_RTCC = 0xA01B 1000 CNTEN = 1 FRZEN = 1 CLKSEL =1 RTCVAL = 27 WKUP. RTCVAL or APIVAL Initialize RTC wakeup timer • Enable RTC counter • Enable counter freeze during debug • Select clock source 128 kHz SIRC / 4 • Initialize initial RTCVAL to WT1 of 0.Table 55. if any Clear reset’s destructive & functional event flags Transision Initiate software mode transition to STANDBY mode to • Mode and key TARGET_MODE= STANDBY • Mode and inverted key STANDBY Wait for low power mode transition to complete Note: Alternative is to implement a timeout interrupt during a mode instruction. ResetEvent Function Steps for MPC56xxB/S Mode Entry Low Power Example Pseudo Code Step Init Wakeup Events Initialize SIRC clock used for wakeup: divide 128 kHz clock by 4 Clear RTC and enable writing to. Rev.9 sec RTCVAL = 900 msec 1 count/33 msec = ~27 Enable Wakeup Rising Edge Event from RTC and: • MPC56xxB: Pin PE[0] • MPC56xxS: Pin PA[0] Enable analog filter for pad: • MPC56xxB: Pin PE[0] • MPC56xxS: Pin PA[0] Enable wakeup event rom RTC and: • MPC56xxB: Pin PE[0] • MPC56xxS: Pin PA[0] Enable WKUP pin pullups to minimize leakage Clear flags Clear all prior wakeup flags.

Verify RUN Verify mode transition from STOP mode completed mode back to RUN3 mode Re-init RTC wakeup Clear RTC and enable writing to RTCVAL or APIVAL CNTEN = 0 Initialize RTC wakeup timer • Enable RTC counter • Enable counter freeze during debug • Select clock source 128 kHz SIRC / 4 • Initialize initial RTCVAL to WT1 of 0. port PE[6] Configure pad as input (to be used for wakeup): • MPC56xxB: Port E[0] • MPC56xxS: Port PA[0]. Qorivva Simple Cookbook. the processor configures the next timeout.) CNTEN = 0 Relevant Bit Fields MPC56xxB MPC56xxS SIU_GPDO[68]= 0 SIU_PCR[68] = 0x0200 SIU_PCR[64] = 0x0103 SIU_PCR[0] = 0x0103 RTC_RTCC = 0x0000 0000 RTC_RTCC = 0xA01B 1000 CNTEN = 1 FRZEN = 1 CLKSEL =1 RTCVAL =0x1B WKUP_WISR = 0x0000 0002 WKUP_WISR [= 0x0010 0000 Clear flag Transition to STOP mode ME_MCTL = 0xA000 5AF0 = 0xA000 A50F Wait for ME_GS[S_MTRANS] STOP mode active. Initialize RTC wakeup timer • Enable RTC counter • Enable counter freeze during debug • Select clock source 128 kHz SIRC / 4 • Initialize initial RTCVAL to WT1 of 0.9sec RTCVAL = 900 msec  1 count/33 msec = ~10 Clear RTC wakeup event flag CNTEN = 1 FRZEN = 1 CLKSEL =1 RTCVAL = 10 WKUP_WISR = 0x0000 0002 WKUP_WISR [= 0x0010 0000 Verify ME_GS[CURRENTMODE] = RUN3 RTC_RTCC = 0x0000 0000 RTC_RTCC = 0xA01B 1000 Clear flag Transision Initiate software mode transition to STANDBY mode to • Mode and key TARGET_MODE= STANDBY • Mode and inverted key STANDBY mode Wait to enter STANDBY (could have timeout) STANDBY mode active. Configure pad GPIO68 to output 0 to turn on LED • GPIO68 on 56xxB EVB: LED 1. port PE[4] • GPIO68 on 56xxS EVB: LED 3. Can be wired to EVB key Re-init RTC wakeup Clear RTC and enable writing to. configures next wakeup timeout. Upon wakeup timeout from STOP mode. Code continues on wakeup from STOP mode back into same RUN3 mode. reset vector is taken. and transitions to STOP mode. 4 120 Freescale Semiconductor . then transitions to STANDBY mode. software outputs a logic signal to turn on an Evaluation Board (EVB) LED. 1 ME_MCTL = 0xD000 5AF0 = 0xD000 A50F while 1 After RTC wakeup timeout. RTC Wakeup Event Function Steps for MPC56xxB/S Mode Entry Low Power Example1 Pseudo Code Step Pad config.Table 56. RTCVAL or APIVAL. On exit. Rev.9sec RTCVAL = 900 msec x 1 count/33 msec = ~27 Clear RTC wakeup event flag (write 1 to clear) Initiate software mode transition to STOP mode • Mode and key TARGET_MODE= • Mode and inverted key STOP • Wait for STOP mode transtion to complete (could have timeout interrupt for timeout.

while (ME. ME. /* RUN3 cfg: 16MHIRCON=1.R = 0x0085000F. void ResetEvent(). syclk=16 MHz FIRC */ ME. /* MPC56xxB/S RTC/API: select ME. ME. syclk=16 MHz FIRC */ ME.R = 0x3F.STOP0. 7 settings: run in STOP */ ME.h" void disableWatchdog(). 13.3.S_MTRANS) {} ME. ME.R. /* Prototypes */ /* Placeholder for reset cause status bits */ disableWatchdog().13. STOP modes and exits at timeout */ Mar 13 2010 S Mihalik .S_MTRANS) {} /* Ensure any STANDBY to DRUN mode trans.RUNPC[7].PCTL[68].RUNPC[7]. /* and execute ResetEvent function */ } if (WKUP.LPPC[7] */ while (ME.R = 0x70005AF0.B.R = 0x001F0010.R = 0x7000A50F. /* Test for functional reset event: */ if ((uint16_t)ResetCause16 != 0) { /* If functional reset event */ ResetEvent().GS.LPPC[7] */ ME.R = 0x00000088. /* 56xxB STOP: FIRCON=0 MVRON=0. ME. /* Test for destructive reset event: */ if ((uint16_t)ResetCause16 != 0) { /* If destructive reset event */ ResetEvent().R = 0x3F.MCTL. void main (void) { uint16_t ResetCause16 =0U.S_CURRENTMODE != 7) {} /* Verify RUN3 (0x7) is the current mode */ ResetCause16 = RGM.RUNPC[7].MCTL.GS.B.PCTL[69]. /* LP Peri. DRUN.LPPC[7]. /* MPC56xxB/S SIU: select ME.3 Code The following includes the main.WISR.LPPC[7] */ ME.R.STANDBY0.DES.MER.Changed STOP mode config MVRON=0. /* Enable RUN3.FES.R = 0x0015000F. RUN3 modes*/ ME. /* Disable watchdog */ ME. plus two preliminary standalone test programs: one for testing only RTC. /* Run Peri.c code used in the example.DRUN.R = 0x001F0010. /* and execute ResetEvent function */ } ResetCause16 = RGM. no sysclk*/ ME. other modes */ ME. /* wait forever */ } } while (1) { } /* else wait forever */ Qorivva Simple Cookbook. Cfg 7 settings: run in DRUN.WISR. STOP. /* MPC56xxB/S WKPU: select ME.GS. flash LP. */ /* Use proper header file */ #include "MPC5604B_0M27V_0101.RUN[3].R = 0x00000400.R && 0x00000040) { /*MPC56xxB: If wake up event PE[6] causing reset*/ while(1). Inc 2010 All rights reserved. /* DRUN cfg: 16MHIRCON=1.c . /* 56xxB STANDBY cfg: FIRCON = 0 */ ME.B.c: Complete Example (MPC56xxB) main. completed*/ /* Enter RUN3 Mode & Key */ /* Enter RUN3 Mode & Inverted Key */ /* Wait for RUN3 mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME.RUNPC[7]. and the other for RTC with STOP mode. Rev.PCTL[91]. not 1 */ Copyright Freescale Semiconductor. Cfg.1 /* /* /* /* /* main. STANDBY.Modes: Low Power example for MPC56xxB/S */ Description: Enters STANDBY.R = 0x3F.R = 0x0000248D. void RTCWakeupEvent().R && 0x00000002) { /* MPC56xxB: If wake up event RTC causing reset*/ RTCWakeupEvent().initial version */ Apr 07 2010 S Mihalik . /* execute RTCWakeupEvent function */ } if (WKUP. 4 Freescale Semiconductor 121 .

RTC. /* CLKSEL=SIRC div.R = 0xA000A50F.WIPUER.RTCC. WKUP.GPDO[68].R = 0xD000A50F. ME. RESET VECTOR IS TAKEN IN THIS EXAMPLE */ void disableWatchdog(void) { SWT.R = 0x00000000.MCTL.R = 0x8000010A.R = 0x00000002.RTCC. ON STANDBY EXIT. SIU. WKUP.R = 0x000FFFFF.R = 0x00000002. ME.MCTL. while (1) {} } /* /* /* /* /* /* /* /* MPC56xxB: Div.void ResetEvent(void) { CGM. 4 122 Freescale Semiconductor .R = 0x0103.GS. FRZEN=CNTEN=1.WRER.PCR[64].WISR.SR.R = 0. ME.MCTL.WIFER.R = 0x000FFFFF.SR.MCTL.R = 0x00000040. /* Clear CNTEN to reset RTC. enable reloading RTCVAL*/ RTC. WKUP. WKUP.R = 0xD000A50F.FES.R = 0xFFFF. ON STANDBY EXIT.. while (ME. RTCVAL=27 */ WKUP.R = 0xD0005AF0.KEY 1 on MPC56xxB EVB*/ /* MPC56xxB/S EVB LED: data output: LED on */ /* Clear CNTEN to reset RTC.MCTL.B.R = 0xA0005AF0. ME. while (1) {} } /* Enter STANDBY mode and key */ /* Enter STANDBY mode and inverted key */ /* Wait to enter STANDBY mode (could use timeout) */ /* ENTER STANDBY MODE.R = 0xFFFF. RTCVAL=27 */ MPC56xxB: Enable rising edge events on RTC. turn SIRC on in STANDBY*/ Clear CNTEN to reset RTC */ CLKSEL=SIRC div.S_MTRANS) {} /* MPC56xxB/S EVB LED: enable as output */ /* MPC56xxB: Cfg PE[0]input. ME. Rev. WKUP. by 4. /* Clear watchdog enable (WEN) */ } Qorivva Simple Cookbook. RGM.R = 0xA01B1000.B. enable reloading RTCVAL*/ /* CLKSEL=SIRC div.R = 0x00000000. WKUP.MCTL. RGM. FRZEN=CNTEN=1.R = 0xA0031000. /* Write keys to clear soft lock bit */ SWT.R = 0x0000c520. RESET VECTOR IS TAKEN IN THIS EXAMPLE */ void RTCWakeupEvent(void) { SIU. RTC.R = 0x0200.R = 0x00000042. FRZEN=CNTEN=1.PCR[68]. PE[0] */ MPC56xxB: Enable WKUP pins to stop leakage*/ MPC56xxB: Clear all wake up flags */ /* Clear destructive reset flags */ /* & clear functional reset flags */ /* Enter STANDBY mode and key */ /* Enter STANDBY mode and inverted key */ /* Wait to enter STANDBY mode (could use timeout) */ /* ENTER STANDBY MODE. by 4. PE[0] */ MPC56xxB: Enable wakeup events for RTC. CODE CONTINUES HERE:*/ while(ME. /* MPC56xxB: Clear wake up flag RTC */ ME.CR.R = 0x00000000. RTC.WIREER.R = 0x0000d928.DES.RTCC.S_CURRENTMODE != 7) {} /* Verify RUN3 (0x7) is still current mode */ RTC. by 4. PE[0]*/ MPC56xxB: Enable analog filters .R = 0x00000042.R = 0xD0005AF0. RTCVAL=3 */ /* MPC56xxB: Clear wake up flag RTC */ /* Enter STOP mode and key */ /* Enter STOP mode and inverted key */ /* Wait for STOP mode transition to complete */ /* STOP HERE FOR STOP MODE! ON STOP MODE EXIT.R = 0xA01B1000.WISR.WISR. RTC.R = 0x00000301.RTCC.GS.RTCC.SIRC_CTL. SIU. SIRC by 4.RTCC. SWT.

GPDO[68]. by 4.SIRC_CTL. /* Enter RUN3 Mode & Inverted Key */ while (ME.2 /* /* /* /* /* Test Program 1: Exercise RTC Function only (MPC56xxB) main.RUNPC[7].R = 0xA01B1000. /* Prototypes */ /* RTC timeouts */ void main (void) { disableWatchdog().RTCF == wakeupCtr++. /* RTC.R = 0xA0031000. RTC. STOP. syclk=16 MHz FIRC */ ME. RTC. FRZEN=CNTEN=1.RTCC.R = 0x00000088. /* SIU.LPPC[7]*/ /* Mode Transition to enter RUN3 mode: */ ME.RTCS. RUN3 modes */ ME.RTCS. RTC.LPPC[7] */ ME. /* Enable RUN3.PCR[68]. RTCVAL=3 */ Clear RTC flag */ {} /* Wait for RTC timeout */ MPC56xxB/S EVB LED: data output: LED off */ Clear CNTEN to reset RTC. Rev. Inc 2010 All rights reserved. RTC.SR.PCTL[91].GPDO[68].SR. SIU. RTCVAL=27*/ {} /* Wait for RTC timeout */ Increment wakeup counter */ MPC56xxB/S EVB LED: data output: LED on */ Clear CNTEN to reset RTC.GPDO[68].RUNPC[7]. RTC. /* Write keys to clear soft lock bit */ SWT. /* while (1) { while (RTC. /* MPC56xxB/S RTC/API: select ME. SWT.RTCC.B. /* DRUN cfg: 16MHIRCON=1. /* Run Peri Cfg 7 settings: run in DRUN.RTCF == SIU.h" void disableWatchdog(). enable reloading RTCVAL*/ CLKSEL=SIRC div.R = 0x00000000.R = 0x0000d928. 4 Freescale Semiconductor 123 .R = 0x7000A50F.MCTL.RTCS. DRUN.RTCC.DRUN.13. 0) /* /* /* /* /* 0) /* /* /* /* MPC56xxB/S EVB LED: data output: LED off */ MPC56xxB/S EVB LED: enable as outputt */ MPC56xxB: Div.RTCC.GS. ME. syclk=16 MHz FIRC */ ME.R = 0x70005AF0.R = 0x001F0010. while (RTC. /* Enter RUN3 Mode & Key */ ME. /* CGM.B.3.S_MTRANS) {} /* Wait for RUN3 mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ*/ while(ME./* RTC.R = 0x00000000. uint32_t wakeupCtr = 0.R = 0x0000c520.R = 0x3F.RUN[3]. FRZEN=CNTEN=1.B.S_CURRENTMODE != 7) {} /* Verify RUN3 (0x7) is the current mode */ SIU.R = 0x001F0010.MCTL.R = 1.MER.RUNPC[7]. */ /* Use proper header file */ #include "MPC5604B_0M27V_0101.CR.B. SIRC by 4 & turn SIRC on in STANDBY*/ Clear CNTEN to reset RTC (counter) */ CLKSEL=SIRC (div. RTC.RTC FUNCTION ONLY */ Description: Toggles output based on RTC timeouts */ NOTE: RTCCNT only clears on power up reset.PCTL[68].Initial version */ Copyright Freescale Semiconductor. not debugger reset or RESET input */ Mar 12 2010 S Mihalik . ME. /* MPC56xxB/S SIU: select ME.R = 0x8000010A. /* Disable watchdog */ ME.Modes: Low Power example for MPC56xxB/S .R = 0x0200.GS.R = 0x20000000.R = 0x0000248D. other modes */ ME.R = 0x00000000.R = 1. /* Clear watchdog enable (WEN) */ } Qorivva Simple Cookbook.R = 0x20000000.R = 0.RTCS.RTCC.R = 0xA01B1000.RTCC. enable reloading RTCVAL*/ CLKSEL=SIRC div. RTCVAL=27*/ Clear RTC flag */ } } void disableWatchdog(void) { SWT. FRZEN=CNTEN=1. by 4).c .R = 0x00000301. STANDBY. /* RUN3 cfg: 16MHIRCON. by 4.R = 0x3F.

syclk=16 MHz FIRC */ ME.MCTL.Modes: Low Power example for MPC56xxB/S .S_CURRENTMODE != 7) {} /* Verify RUN3 (0x7) is the current mode */ wakeupCtr++. /* Enable RUN3. WKUP pins pullups to stop leakage*/ /* Enter STOP mode and key */ /* Enter STOP mode and inverted key */ /* Wait STOP mode transition to complete */ /* STOP HERE FOR STOP MODE! ON STOP MODE EXIT.B.R = 0x3F.R = 0x00000002.R = 0x0015001F.RTCC. STANDBY. FRZEN=CNTEN=1. STOP.WRER.SIRC_CTL.RUNPC[7].S_CURRENTMODE != 7) {} /* Verify RUN3 (0x7) is the current mode */ CGM. uint32_t temp = 0.GS.WIPUER. no sysclk*/ ME. CODE CONTINUES HERE:*/ Qorivva Simple Cookbook.PCTL[91].R = 0x00000002.R = 0xA000A50F. while (ME. /* CLKSEL=SIRC div.WIFER.R = 0x70005AF0. RTCVAL=3 */ WKUP. /* Enter STOP mode and key */ ME.MCTL.GS.WIREER.S_MTRANS) {} /* Wait STOP mode transition to complete */ /* STOP HERE FOR STOP MODE! ON STOP MODE EXIT.LPPC[7]*/ ME. uint32_t wakeupCtr = 0. ME. SIU.RUNPC[7].WISR.R = 0x00000000. Rev. */ /* Use proper header file */ #include "MPC5604B_0M27V_0101.STOP0. not debugger reset or RESET input */ Mar 13 2010 S Mihalik . /* MPC56xxB/S WKPU: select ME.R = 0xA000A50F.RTC.R = 0x3F. ME. 4 124 Freescale Semiconductor . by 4.R = 0x0200. syclk=16 MHz FIRC */ ME.R = 0x001F0010. RTC.3 /* /* /* /* /* Test Program 2: Exercise RTC Wakeup in STOP mode (MPC56xxB) main.Initial version */ Copyright Freescale Semiconductor.R = 0x0000248D.R = 0x00000002. WAKEUP. /* Enter RUN3 Mode & Key */ ME.R = 0x001F0010.S_MTRANS) {} /* /* /* /* /* /* /* MPC56xxB: Div SIRC by 4 & turn SIRC on in STANDBY*/ Clear CNTEN to reset RTC (counter) */ CLKSEL=SIRC div. STOP MODE ONLY */ Description: Toggles output on RTC timeouts */ NOTE: RTCCNT only clears on power up reset.R = 0xA01B1000.MER.R = 0xA0005AF0. /* MPC56xxB: Clear wake up flag RTC */ ME. /* Run Peri.GS. /* RUN3 cfg: 16MHIRCON.R = 0.GS.DRUN. WKUP. RUN3 modes*/ ME. RTC.R = 0x00000400.MCTL.R = 0xA0031000.PCTL[68]. /* Prototypes */ /* wake up counter incremented on STANDBY exit */ void main (void) { disableWatchdog().RUNPC[7].R = 0x00000301.h" void disableWatchdog(). Cfg 7 settings: run in STOP */ ME.c .R = 0x7000A50F. /* LP Peri. FRZEN=CNTEN=1.MCTL.B.R = 0x000FFFFF. /* MPC56xxB/S SIU: select ME.R = 0x00000000. /* MPC56xxB/S RTC/API: select ME. enable reloading RTCVAL*/ RTC.PCTL[69].PCR[68].RTCC. ME>LPPC[7] */ ME. /* Clear CNTEN to reset RTC.R = 0x00000088.none */ MPC56xxB: Enable wakeup events for RTC */ MPC56xxB: Ena. WKUP.MCTL. Cfg 7 settings: run in DRUN. DRUN.RUNPC[7].R = 0x00000000.RTCC.3. WKUP. ME>LPPC[7] */ ME. RTCVAL=27 */ MPC56xxB: Enable rising edge events on RTC */ MPC56xxB: Enable analog filters . WKUP.B.B. /* MPC56xxB/S EVB LED: data output: LED on */ /* MPC56xxB/S EVB LED: enable as output */ RTC. /* Increment wakeup counter */ SIU.13. Inc 2010 All rights reserved. /* Enter STOP mode and inverted key */ while (ME.RUN[3]. /* DRUN cfg: 16MHIRCON=1. by 4.RTCC.GPDO[68]. other modes */ ME.LPPC[7].S_MTRANS) {} /* Wait for RUN3 mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ*/ while(ME.GS.R = 0xA0005AF0. /* Enter RUN3 Mode & Inverted Key */ while (ME.R = 0x3F. ME. CODE CONTINUES HERE:*/ while (1) { while(ME. /* 56xxB STOP cfg: FIRCON=MVRON=1. flashLP. /* Disable watchdog */ ME.B.MCTL.

RTCVAL=27*/ MPC56xxB: Clear wake up flag RTC */ ME. /* /* /* /* MPC56xxB/S EVB LED: data output: LED off */ Clear CNTEN to reset RTC.S_MTRANS) {} /* Wait STOP mode transition to complete */ } /* STOP HERE FOR STOP MODE! ON STOP MODE EXIT.R = 0xA0005AF0.S_CURRENTMODE != 7) {} /* Verify RUN3 (0x7) is the current mode */ SIU.WISR. WKUP.R = 0xA01B1000.CR. } /* Write keys to clear soft lock bit */ /* Clear watchdog enable (WEN) */ Qorivva Simple Cookbook.R = 0x00000002.B.while(ME.R = 0x00000000. by 4).RTCC.GS. FRZEN=CNTEN=1.B. RTC.R = 0x0000c520.MCTL.SR.R = 0xA000A50F. SWT.R = 0x0000d928. CODE CONTINUES HERE:*/ } void disableWatchdog(void) { SWT.R = 1. /* Enter STOP mode and inverted key */ while (ME. /* Enter STOP mode and key */ ME.GPDO[68].RTCC.R = 0x8000010A. 4 Freescale Semiconductor 125 .SR.GS. Rev. RTC. SWT.MCTL. enable reloading RTCVAL*/ CLKSEL=SIRC (div.

DMA Block Move Example Qorivva Simple Cookbook. These steps appear “messy” for every transfer. Exercise: Step through code. this TCD is assigned to the eQADC’s Command FIFO 0. Instead. • Poll when that request is done (check the CITER bit field). Because TCDs are in RAM. Hence the “minor loop” is simply one transfer. MPC5500 SRAM TCD0 TCD1 TCD2 TCD3 TCD4 • • • TCDn Source Array XBAR eDMA SRAM Transfer Control Descriptors (TCD’s) Destination Byte Other XBAR Masters Other XBAR Slaves Figure 25. Hence all fields used or enabled must be initialized. TCD0 will be used. Because a peripheral is not involved. remember that when using actual peripherals. This emulates a common use of DMA. observing DMA transferring the “Hello world” string to the destination byte. Only one byte of data will be transferred with each DMA service request. automatic DMA handshaking will not occur. On MPC551x devices. all fields will come up random. they are done automatically by hardware. Rev. which is only a byte in this example. Then modify the TCD so the destination is an array instead of a single byte location. which transfers one byte.14 14. The purpose of this example is to illustrate how to set up a DMA transfer. However. On MPC555x devices. TCDs are not hard-assigned to any channel.1 eDMA: Block Move Description Task: Initialize an eDMA channel’s Transfer Control Descriptor (TCD) to transfer a string of bytes (“Hello world”) from an array in SRAM to a single SRAM byte location. The “major loop” here consists of 12 minor loop iterations. the software handshaking given here must be implemented for each transfer: • Start DMA service request (set a START bit). where a string of data or commands is transferred automatically under DMA control to an input register of a peripheral. software never has to do these steps. 4 126 Freescale Semiconductor .

TCD0[DSIZE] = 0 TCD0[DOFF] = 0 TCD0[DLAST_SGA] = 0 TCD0[DMOD] = 0 TCD0[NBYTES] = 1 TCD0[BITER] = 12 TCD0[CITER] = 12 TCD0[D_REQ] = 1 TCD0[INT_HALF] = 0 TCD0[INT_MAJ] = 0 TCD0[CITERE_LINK] = 0 TCD0[BITERE_LINK] = 0 TCD0[MAJORE_LINK] = 0 TCD0[E_SG] = 0 TCD0[. but is not used. After completion. SSIZE = 0 (1 byte) SOFF = 1 SLAST = –12 SMOD = 0 DADDR = dest.14. addr. disable further D_REQ = 1 requests for transfer • Interrupts: interrupts are not enabled here INT_HALF = 0 INT_MAJOR = 0 • Linking: channel linking is not enabled here CITERE_LINK = 0 BITERE_LINK = 0 • Dynamic programming: dynamic channel linking MAJORE_LINK = 0 and scatter gather are not enabled E_SG = 0 • Bandwidth Control: no DMA stalls BWC = 0 • Status flags: initialize to 0 START = 0 DONE = 0 ACTIVE = 0 Init DMA Use fixed priorities for groups and channels (default) Arbitration Use defaults: Priorities (Gp = 0. Rev. Source Parameters: • Source address: address of SourceData • Source data transfer size: read 1 byte per transfer • Source address offset: increment source address by 1 after each transfer • Last source address adjustment: adjust source address by –12 at completion of major loop • Source address modulo: disabled Destination Parameters: • Destination address: address of SourceData • Destination data transfer size: write one byte per transfer • Destination address offset: do not increment destination address after each transfer • Last destination address adjustment: do not adjust destination address after completion of major loop • Destination address modulo: disabled Control Parameters • Inner “minor loop” byte transfer count: transfer 1 byte NBYTES = 1 per service request • Number of minor loop iterations in major loop: 12 BITER = 12 CITER = 12 • Disable request: at end of major loop. 4 Freescale Semiconductor 127 .2 Design Table 57. Ch = 0). DSIZE = 0 (1 byte) DOFF = 0 DLAST = 0 DMOD = 0 TCD0[SADDR] = &SourceData[] TCD0[SSIZE] = 0 TCD0[SOFF] = 1 TCD0[SLAST] = –12 TCD0[SMOD] = 0 TCD0[DADDR] = &Dest. Qorivva Simple Cookbook. no preemption Enable Chan. DMA: Block Move Step Relevant Bit Fields Pseudo Code SourceData = “Hello world “ SADDR = src.BWC] = 0 TCD0[START] = 0 TCD0[DONE] = 0 TCD0[ACTIVE] = 0 EDMA_CR = 0x0000 E400 EDMA_CPR0 = 0x00 SERQ = 0 SSB = 0 wait (START = 1 and ACTIVE = 0) SERQ = 0 EDMA_SERQR = 0 EDMA_SSBR = 0 while (TCD0[CITER] != 1) { wait for ((TCD0[START] = 1) & (TCD0[ACTIVE] = 0)) EDMA_SSBR = 0 } Data Init Init TCD0 Initialize data source string. addr. 0 Set enable request for channel 0 Initiate Set channel 0 START bit to initiate first minor loop DMA For each transfer (while not on last transfer)1: service by • Wait for last transfer to have started and minor loop software is finished (is no longer active) • Set start bit to initiate next minor loop transfer 1 The START bit is set on the last iteration here. the channel’s DONE bit will be set.

CPR[0].R = 0.TCD[0]. no dest addr change*/ EDMA.DLAST_SGA = 0.SOFF = 1.TCD[0]. All Rights Reserved */ Rev 1. channel priority = 2 */ EDMA. 4 128 Freescale Semiconductor . EDMA.CITER = 12.TCD[0].INT_MAJ = 0.R = 0x12. /* /* /* /* /* Transfer 1 byte per minor loop */ 12 minor loop iterations */ Initialize current iteraction count */ Disable channel when major loop is done*/ Interrupts are not used */ /* Linking is not used */ /* Dynamic program is not used */ /* Default bandwidth control.TCD[0].Mihalik.DMOD = 0.TCD[0].D_REQ = 1. EDMA.DOFF = 0.TCD[0].NBYTES = 1.MAJORE_LINK = 0.E_SG = 0.h" /* Use proper include file such as mpc5510.TCD[0].TCD[0].no stalls */ /* Initialize status flags */ } void main (void) { int i = 0.ACTIVE == 1)) {} EDMA.SLAST = -12. EDMA. /* Do not increment destination addr*/ EDMA.1 /* /* /* /* /* /* Code main.TCD[0].TCD[0]. /* Destination modulo feature not used */ EDMA. reset src addr*/ Source modulo feature not used */ EDMA. EDMA.START == 1) | (EDMA. Copyright Freescale.TCD[0]. EDMA.SSBR. EDMA.h */ const uint8_t uint8_t SourceData[] = {"Hello World\r"}. /* Enable EDMA channel 0 */ /* Set channel 0 START bit to initiate first minor loop transfer */ /* Initate DMA service using software */ while (EDMA.14. EDMA. initTCD0(). EDMA. /* Channel 0 priorites: group priority = 1.TCD[0].CR. must be done by debug scripts or BAM */ 2.START = 0. EDMA.0 Jul 10 2007 SM .SSIZE = 0.SSBR. EDMA. add 1 to src addr*/ After major loop.CITERE_LINK = 0.BITER = 12. /* Use fixed priority arbitration for DMA groups and channels */ EDMA.TCD[0]. } /* Loop forever */ Qorivva Simple Cookbook.TCD[0]. 2004. EDMA. Rev.R = 0.TCD[0]. MMU not initialized.TCD[0].SADDR = (vuint32_t) &SourceData. /* Write 2**0 = 1 byte per transfer */ EDMA. EDMA.DADDR = (vuint32_t) &Destination.TCD[0].TCD[0].R = 0. /* Source data string */ Destination = 0. 2004 S.TCD[0]. /* Destination byte */ void initTCD0(void) { EDMA.SERQR.ACTIVE = 0. EDMA.TCD[0].BITERE_LINK = 0. /* /* /* /* /* Load address of source data */ Read 2**0 = 1 byte per transfer */ After transfer. EDMA.SMOD = 0. EDMA.DSIZE = 0.TCD[0]. /* Load address of destination */ EDMA. EDMA.DMA-Block Move example */ Rev 0.TCD[0].INT_HALF = 0.TCD[0].1 Sept 30.3 14. /* After major loop. /* Dummy idle counter */ /* Initialize DMA Transfer Control Descriptor 0 */ EDMA.Changed from TCD18 to TCD0 to be MPC5510 compatible */ Notes: */ 1. must be done by debug scripts */ #include "mpc563m.TCD[0].h or mpc5554. /* Set channel 0 START bit again for next minor loop transfer */ } } while (1) { i++. EDMA. L2SRAM not initialized.BWC = 0.c (All except MPC56xxS) main.TCD[0].c .3.TCD[0].CITER != 1) { /* while not on last minor loop */ /* wait for START=0 and ACTIVE=0 */ while ((EDMA.R = 0x0000E400.DONE = 0.TCD[0]. EDMA.

TCD[0].CITER != 1) { /* while not on last minor loop */ /* wait for START=0 and ACTIVE=0 */ while ((EDMA.TCD[0]. EDMA. /* Destination byte */ void initTCD0(void) { EDMA.R = 1.TCD[0].TCD[0]. EDMA.TCD[0]. initTCD0().BWC = 0. no dest addr change*/ EDMA.DONE = 0.ACTIVE = 0.TCD[0].DMA Block Move */ Oct 23 2008 S.BITER = 12.2 /* /* /* /* main. /* Enable EDMA channel 0 */ /* Set channel 0 START bit to initiate first minor loop transfer */ } /* Initate DMA service using software */ while (EDMA. /* Do not increment destination addr */ EDMA.3.CITERE_LINK = 0.TCD[0].E_SG = 0.START == 1) | (EDMA. } /* Loop forever */ Qorivva Simple Cookbook.R = 0x0. EDMA.R = 0.INT_HALF = 0.TCD[0].SMOD = 0.DOFF = 0.D_REQ = 1.R = 0. EDMA. 4 Freescale Semiconductor 129 . EDMA. EDMA.TCD[0].TCD[0]. EDMA. add 1 to src addr*/ After major loop. /* Destination modulo feature not used */ EDMA. EDMA.DADDR = (vuint32_t) &Destination.TCD[0]./* Source data string */ uint8_t Destination = 0.TCD[0].CITER = 12. 2010 All rights reserved.TCD[0]. Rev.h or mpc5554.CR. /* Write 2**0 = 1 byte per transfer */ EDMA.TCD[0]. EDMA.SADDR = (vuint32_t) &SourceData.DSIZE = 0.SSIZE = 0.TCD[0].TCD[0]. /* Channel 0 priorites: group priority = 0. EDMA.CPR[0].SLAST = -12.R = 0.TCD[0].TCD[0].h */ const uint8_t SourceData[] = {"Hello World\r"}.TCD[0]. EDMA. /* Load address of destination */ EDMA.SSRT. EDMA. EDMA.INT_MAJ = 0. EDMA.c (MPC56xxS) main.START = 0. /* Use fixed priority arbitration for DMA groups and channels */ EDMA. EDMA.Mihalik -inital version */ Mar 15 2010 S Mihalik .TCD[0].TCD[0].SSRT. reset src addr*/ Source modulo feature not used */ EDMA.TCD[0].MAJORE_LINK = 0. EDMA.TCD[0].SOFF = 1.TCD[0].14. /* Set channel 0 START bit to initiate first minor loop transfer */ } while (1) { LoopForever: i++. /* /* /* /* /* Transfer 1 byte per minor loop */ 12 minor loop iterations */ Initialize current iteraction count */ Disable channel when major loop is done*/ Interrupts are not used */ /* Linking is not used */ /* Dynamic program is not used */ /* Default bandwidth control. channel priority = 0 */ EDMA.h" /* Use proper include file such as mpc5510.TCD[0]. /* Dummy idle counter */ /* Initialize DMA Transfer Control Descriptor 0 */ EDMA. /* /* /* /* /* Load address of source data */ Read 2**0 = 1 byte per transfer */ After transfer.updated for new eDMA version on MPC5606S */ Copyright Freescale Semiconductor.DLAST_SGA = 0.TCD[0].BITERE_LINK = 0.TCD[0].SERQ.DMOD = 0.c . EDMA.NBYTESu. Inc 2008. /* After major loop. */ #include "56xxS_0204. EDMA.R = 0x0000E400.no stalls */ /* Initialize status flags */ } void main (void) { volatile uint32_t i = 0.ACTIVE == 1)) {} EDMA.

Use a terminal emulation program for communication from the PC side with settings of 9600 baud. 144 QFP 98 97 176 QFP 122 121 208 BGA F14 F15 Function Name TXDA RXDA SIU PCR No. The program simply waits until flags are at the desired state before proceeding. 89 90 MPC555x Family Package Pin No. no parity. and no parity. Exercise: Connect a COM port of a PC to an MPC5500 evaluation board eSCI port.1 eSCI: Simple Transmit and Receive Description Task: Transmit the string of data “Hello World<CR>” to eSCI_A. the overflow flag would be checked after reading the received character. as we look for only one received character. 8 bits data. eSCI Simple Transmit and Receive Example Table 58. If overflow is a concern on reception. eight bits data. Rev. and no flow control. Overflow is not checked in this example. 4 130 Freescale Semiconductor . Interrupts and DMA are not used. 54 55 Package Pin No. Signals for eSCI Example MPC551x Family Pin Name SIU PCR No. Make sure to have the correct SCI jumper settings for Tx/Rx connection for the particular EVB used. MPC5500 ‘Hello World<CR>’ eSCI_A 8 MHz Crystal PLL Set to 64 MHz Data Register TxDA XCVR RxDA 64 MHz sysclk Received Characters Personal Computer COM Port Figure 26. The serial parameters are: 9600 baud. 496 BGA V24 U26 416 BGA U24 V24 324 BGA N20 P20 208 BGA J14 K14 EVB xPC 563M PJ1–14 PJ1–13 Signal TxDA RxDA PD6 PD7 Qorivva Simple Cookbook. Step through the program and verify proper transmission.15 15. then wait to receive a byte.

” The scope shot below shows the program running without a breakpoint. 4 Freescale Semiconductor 131 . the ASCII code for “H. Here the data bits. 16  SCI Baud Rate 16  9600 So after rounding it off to the nearest whole number.66. The oscilloscope shot below shows only one frame (character) because it was taken when stepping through code. are 0001 0010. It shows the bit time being met. Rev. which after putting MSB first is 0x48. LSB first. and the first two character are shown here. 417 (0x1A1) will be used for SBR in this example. followed by LSB through MSB bits. is: eSCI system clock 64 M SBR = --------------------------.2 Design For the desired 9600 SCI baud rate. the ideal calculation for SBR bitfield eSCIx_CR1[SBR]. assuming a 64 MHz sysclk to the eSCI module. There are contiguous transmissions of characters.. The time per bit at 9600 baud = 1 sec / 9600 bits.15. The scope shot also shows the transmission sequence of sending the start bit. which rounds off to 104 microseconds..= 416. Qorivva Simple Cookbook.= ------------.

Rev. PLL_ESYNCR2 = Wait for 0x0000 0006.Table 59. Also for PLL_ESYNCR2 = MPC563x: 0x0000 0005. } wait for ESCIA_SR[RDRF] = 1 ESCIA_SR = 0x2000 0000 RecData = ESCIA_DR Read and Echo Back Data wait for RDRF = 1 write RDRF = 1 wait for TDRE = 1 write TRDE = 1 wait for ESCIA_SR[TDRE] = 1 ESCIA_SR = 0x8000 0000 ESCIA_DR = RecData Qorivva Simple Cookbook. FMPLL_SYNSR PLL_ESYNCR1 = [LOCK] = 1. PLL_SYNSR [LOCK] = 1. FMPLL_SYNCR = Wait for 0x1600 0000. 0x1608 0000. eSCI Simple Design Steps Step Data Init Init sysclk Initialize data string to be transmitted on eSCI_A Initialize byte used to receive data from eSCI_A Set system clock = 64 MHz (See Section 10. “PLL: Initializing System Clock (MPC551x. MPC55xx)”) Note for 40 MHz Crystal used on MPC55xx — Replace FMPLL_SYNCR values: 0x1608 0000 with 0x4610 0000 0x1600 0000 with 0x4608 0000 Relevant Bit Fields Pseudo Code MPC551x MPC555x TransData = “Hello World!<CR>” RecData = 0 CRP_CLKSRC FMPLL_SYNCR = [XOSCEN] = 1. [CLKCFG]=7 MDIS = 0 (default) SBR = 417 (0x1A1) M = 0 (default) PE = 0 (default) TE = 1 RE = 1 PA = primary PA = primary SIU_PCR[54] = 0x0400 SIU_PCR[55] = 0x0400 SIU_PCR[89] = 0x0400 SIU_PCR[90] = 0x0400 ESCIA_CR2 = 0x2000 ESCIA_CR1 = 0x01A1 000C Init eSCI_A Turn on the eSCI module (in case it was off) Initialize eSCI control • Baud Rate value = 64 M / (16 9600) ~= 417 • Word length = 8 bits • Parity is not enabled • Enable transmitter • Enable receiver Configure pads: • TxDA • RxDA Transmit Data Loop for # characters: • Wait for Transmit Data Register Empty status flag • Clear status flag • Write one character Wait for Receive Data Register Full status flag Clear status flag Read byte Ensure Transmit Data Register Empty status flag Clear status flag Transmit back (echo) received byte wait for TDRE = 1 write TRDE = 1 Loop for # characters { wait for ESCIA_SR[TDRE] = 1 ESCIA_SR = 0x8000 0000 ESCIA_DR = next char. FMPLL_ SIU_SYSCLK ESYNCR1 [SYSCLKSEL] = 2. 0xF000 0020. 4 132 Freescale Semiconductor .

PCR[89]. /* SIU. ESCI_A. /* Use the following two lines SIU. while (ESCI_A.LTR.R = 0xF0000020. changed sysclk (50 MHz) & SBR.DR. /* Wait for FMPLL to LOCK */ FMPLL.ESYNCR1.SR.RDRF == 0) {} ESCI_A. */ /* Set CLKCFG=PLL.PCR[54].B. j< sizeof (TransData).c: Rev 0. no parity */ Transmit string of characters on eSCI A */ Receive and echo character on eSCI A */ Wait forever */ Qorivva Simple Cookbook.B.R = 0x00000005.SR.R = 0x01A1000C.SYNCR.SYSCLK.SYNSR.R = 0x400.B. 4 Freescale Semiconductor 133 . Rev. 8 bits.Modified for MPC551x. 2004 S.PCR[55]. */ /* Select PLL for sysclk */ /* MPC563x: Use the next line */ FMPLL. EMFD=0x20*/ /* while (FMPLL.SYNCR. */ cleared RDRF before reading data register */ Rev 1.CLKCFG = 0X7. must be done by debug scripts or BAM */ 2 SRAM not initialized. /* Clear TXRDY flag */ ESCI_B.SYSCLKSEL = 2. RecData = ESCI_A.Mihalik. /* Received byte from eSCI */ #include "mpc563m.*/ /* Wait for PLL to LOCK */ /* FMPLL. Tx & Rx enabled */ for MPC551x */ /* Configure pad for primary func: TxDA */ /* Configure pad for primary func: RxDA */ for MPC555x */ /* Configure pad for primary func: TxDA */ /* Configure pad for primary func: RxDA */ */ */ */ */ */ void TransmitData (void) { uint8_t j.ESYNCR2. j++) { /* Loop for character string */ while (ESCI_B.3 Jun 04 2008 SM .h or mpc5554.SR. no parity.h */ const void initSysclk (void) { /* MPC551x: Use the next 6 lines */ /* CRP. /* Use the following two lines /* SIU. initESCI_A().TDRE == 0) {} ESCI_A.B.SR. /* Dummy variable */ for (j=0. */ /* Enable external oscillator */ /* FMPLL. EPREDIV=0.B.h" /* Use proper include file such as mpc5510.SR.R = 0x400.SR.3 /* /* /* /* /* /* /* /* /* Code main.RDRF flags as required in MPC5554 RevA & on*/ Jul 19 2007 SM .R = 0x400.LOCK != 1) {}.initSysclk changed for MPC5633M support */ Notes: 1 MMU not initialized.DR.B. } void main(void) { initSysclk().LOCK != 1) {}.R = 0x400. 40MHz: 0x46100000 while (FMPLL.1 Simple eSCI program */ Sept 30.XOSCEN = 1.PCR[90].Changed sysclk to 64 MHz */ Rev 1.0 Rev 1.ESYNCR1. /* 8 MHz xtal: 0x16080000.R = 0x16000000.ESYNCR2. /* Transmit string & CR*/ RecData.B. ESCI_A.15. 8 bits. Copyright Freescale.R = 0x00004000.R = 0x80000000.R = 0x20000000.B.SYNSR. SIU. /* Change clk to PLL normal mode from crystal /* MPC555x including MPC563x: use the next 3 lines for either 8 or 40 MHz crystal FMPLL.CR1.2 Aug 08 2007 SM .R = 0x2000.TXRDY == 0) {} /* Wait for LIN transmit ready = 1 */ ESCI_B. } /* Module is enabled (default setting ) */ /* 9600 baud. */ /* Set ERFD to final value for 64 MHz sysclk /* SIU.D.R = 0x00000006. All Rights Reserved */ July 14 2005 SM-Cleared TDRE.D = RecData.CR2. ReceiveData(). */ } } void ReceiveData (void) { while (ESCI_A. /* 8 MHz xtal: 0x16000000.B.R = FrameSpecAndData[j] << 24. 2007. /* Write byte to LIN Trans Reg.B. 40MHz: 0x46080000 } void initESCI_A (void) { ESCI_A. while (1) {} } /* /* /* /* /* /* /* /* /* /* /* Wait for receive data reg full = 1 */ Clear RDRF flag */ Read byte of Data*/ Wait for transmit data reg empty = 1 */ Clear TDRE flag */ Echo back byte of Data read */ Set sysclk = 64 MHz running from PLL */ Enable Tx/Rx for 9600 baud.R = 0x16080000. TransmitData().1 Rev 1. */ /* Set ERFD to initial value of 6 */ /* FMPLL.CLKSRC. must be done by debug scripts or in a startup file*/ uint8_t uint8_t TransData[] = {"Hello World!\n\r"}.

8 bits data. NOTE The RxD receive pin must be able to monitor the TxD transmitted signal.16 16. For the most efficiency. MPC5500 LIN frame specification and data eSCI_B 8 MHz Crystal PLL Set to 64 MHz LIN Transmit Register LIN Receive Register 64 MHz sysclk TxDB LIN XCVR RxDB Scope or LIN tool Figure 27.1 eSCI: LIN Transmit Description Task: Transmit the data string “Hello” via LIN using eSCI_B. including 10417 baud. Alter frame ID and repeat. When sending bytes to the LIN Transmit Register. with software clearing the flag each time. “eSCI: Simple Transmit and Receive. 496 BGA Y27 Y24 416 BGA W25 W23 324 BGA R21 T19 208 BGA L13 EVB xPC 563M PJ1–16 Signal TxDB RxDB PD8 PD9 M13 PJ1–15 Qorivva Simple Cookbook. or (2) for debug purposes. Interrupts and DMA are not used. 56 57 Package Pin No. use software to poll the TXRDY flag for each byte write. Parameters from Section 15. 144 QFP 94 93 176 QFP 118 117 208 BGA G13 F16 Function Name TXDB RXDB SIU PCR No. the TxD and RxD can be shorted together without using the transceiver. eSCI LIN Example Table 60. 4 134 Freescale Semiconductor . 91 92 MPC555x Family Package Pin No. Hence either (1) the LIN transceiver must be connected as shown and the transceiver must be powered. The MPC5510 EVB and MPC563M EVB require changing the default configuration to implement one of these two options. DMA would be used. The next most efficient method would be to have the TXRDY interrupt the processor.” are used. Signals for eSCI LIN Example MPC551x Family Pin Name SIU PCR No. Rev. Exercise: Connect an oscilloscope or LIN tool and verify the transmit output. which automatically waits for TXRDY flag and clears it after a write. and no parity.

which includes the header (HDCHK = 1). ESCIx_LSR_[STO] The LIN state machine can automatically reset after an exception of a bit error.2 Design To transmit a LIN frame. The byte values used in the example are shown in the table below.x and J2602 the a checksum is used (CSUM = 1). first the frames data must be specified by writing the ID. but we will allow the reset to occur by disabling the feature (accomplished by clearing the LDBG bit in eSCIx_LCR).16. and the frame’s header starts to transfer. Normally one would enable error interrupts and/or check those status flags also. Although DMA is not used here. Per LIN 2. where no errors occur or are checked. ESCIx_SR[FE] • RxD input stuck after transmission starts: sets physical bus error flag. Qorivva Simple Cookbook. a slave does not respond in the specified timeout in ESCIx_LTR: sets slave timeout flag. Table 61. This specifies the LIN frame. or wakeup. 4 Freescale Semiconductor 135 . Next. Rev. ESCIx_LSR[PBERR] • For receive frames. this bit will be set anyway. Bytes Written to LIN Transmit Register (SCIB_LTR) Field Parity (1:0) = 0 (Parity not used) ID (5:0) = 0x35 Length (7:0) = 8 (for 8 bytes data) HDCHK = 1 (header is included in checksum) CSUM = 1 (checksum is appended to end of frame) CRC = 0 (2 CRC bytes not appended to end of frame) Data 0 = ‘H’ Data 1 = ‘e’ Data 2 = ‘l’ Data 3 = ‘l’ Data 4 = ‘o’ Data 5 = ‘ ’ Data 6 = ‘ ’ Data 7 = ‘ ’ TX = 1 (Transmit operation) Timeout (11:8) = 0 (Timeout is zero for transmit frame) Byte Value 0x35 0x08 0xD0 Notes Specifies LIN frame (which causes LIN frame’s header to start transmission) 0x48 0x65 0x6C 0x6C 0x6F 0x20 0x20 0x20 Data to transmit in LIN frame Bit or physical bus errors can stop DMA transmission (by setting the BSTP bit in eSCIx_CR2). A partial list of errors includes: • A physical bus error of a permanently low bit: sets framing error flag. length and control to the LIN Transmit Register. physical bus error. This example shows a “good” case. the data is written to the same LIN Transmit Register. For debug purposes. it is useful to disable this feature.

such as TJA1020. PLL_ESYNCR2 = Wait for 0x0000 0006. at least the internal pullup should be used. 0xF000 0020. In this case. Also for PLL_ESYNCR2 = MPC563x: 0x0000 0005.) Transmit Data Loop for each FrameSpecAndData character: • Wait for Transmit Data Ready status flag • Clear status flag • Write one character wait for TXRDY = 1 write TXRDY = 1 write byte to LTR Loop for # characters { wait for ESCIB_SR[TXRDY] = 1 ESCIB_SR = 0x0000 4000 ESCIB_LTR = next char. ‘l’. FMPLL_SYNCR = Wait for 0x1600 0000. } Qorivva Simple Cookbook. FMPLL_ SIU_SYSCLK ESYNCR1 [SYSCLKSEL] = 2. eSCI LIN Design Steps Step Relevant Bit Fields Pseudo Code MPC551x MPC555x Data Init LIN frame specification and 8 bytes data for transmit FrameSpecAndData = 0x35. Rev. 0x1608 0000. 0xD0. [CLKCFG] = 7 ESCB_CR2 = 0x6240 MDIS = 0 (default) BRK13 = 1 BSTP = 1 SBSTP = 1 FBR = 1 ESCIB_CR1 = 0x0180 000C SBR = 384 (0x180) M = 0 (default) PE = 0 (default) TE = 1 RE = 1 TIE = TCIE = RIE = 0 ESCIB_LCR = 0x0100 0000 LIN = 1 LDBG = 0 PA = primary PA = primary SIU_PCR[56] = 0x0400 SIU_PCR[57] = 0x0400 SIU_PCR[91] = 0x0400 SIU_PCR[92] = 0x0400 Init sysclk Set system clock = 64 MHz (See Section 10. ‘ ’ CRP_CLKSRC FMPLL_SYNCR = [XOSCEN] = 1. “PLL: Initializing System Clock (MPC551x. MPC55xx)”) Note for 40 MHz Crystal used on MPC55xx — Replace FMPLL_SYNCR values: 0x1608 0000 with 0x4610 0000 0x1600 0000 with 0x4608 0000 Init eSCI B Initialize desired Control Register 2 settings: for LIN • Turn on the eSCI module (in case it was off) • Set break character length to 13 bits • Stop DMA (not used here) on bit/physical bus error • SCI bit errors cause stop on bit instead of frame end • Detect bit errors on each bit (“fast”) instead of byte Initialize desired Control Register 1 settings: • Baud Rate value = 64 M / (16x10417) ~= 384 • Word length = 8 bits • Parity is not enabled • Enable transmitter • Enable receiver • Do not use normal eSCI interrupts Initialize desired LIN Control Register settings: • Switch eSCI to LIN mode • Do not enable exception to reset state machine Configure pad: • TxDB • RxDB (NOTE: Some EVB transceivers. FMPLL_SYNSR PLL_ESYNCR1 = [LOCK] = 1. ‘ ’. require a pullup. 0x08.1 Design Steps Table 62. PLL_SYNSR [LOCK] = 1.16. ‘H’. so the PCR value should be 0x0403 instead of 0x400. ‘ ’. 4 136 Freescale Semiconductor . ‘e’.2. ‘o’. ‘l’.

Entire LIN Transmit Frame Qorivva Simple Cookbook. but code was deliberately stepped through here to show the header generation after the first three writes to the LIN Transmit Register.2 Design Screenshots Below is an oscilloscope trace of TxDB output showing the frame’s header. Rev. Normally the data would continue after the header.2. 4 Freescale Semiconductor 137 .16. LIN Transmit Frame Header Figure 29. Figure 28.

0xD0. /* Change clk to PLL normal mode from crystal /* MPC555x including MPC563x: use the next 3 lines for either 8 or 40 MHz crystal FMPLL.ESYNCR1.PCR[57].CR2. Tx & Rx enabled */ ESCI_B.PCR[56].SYNSR.CR1. 2007.*/ /* Wait for PLL to LOCK */ /* FMPLL.R = 0x400. /* eSCI put in LIN mode */ /* Use the following two lines for MPC551x */ /* SIU.'e'.' '. */ /* Set CLKCFG=PLL.Mihalik. j++) { /* Loop for character string */ while (ESCI_A. /* Dummy variable */ for (j=0.LOCK != 1) {}. 8 bits. /* Clear TXRDY flag */ ESCI_A. /* 8 MHz xtal: 0x16000000.XOSCEN = 1.16. 8 bits.0x08.'l'. */ /* Set ERFD to final value for 64 MHz sysclk /* SIU. must be done by debug scripts or in a startup file*/ #include "mpc563m.ESYNCR1.SYSCLKSEL = 2. All Rights Reserved */ Notes: 1 MMU not initialized.R = 0x16000000.R = 0x6240.R = 0x01000000. TransmitData().R = 0x400.LOCK != 1) {}. Rev.R = 0x400.R = 0x00004000.417K */ Copyright Freescale. 40MHz: 0x46080000 } */ */ */ */ */ void initESCI_B (void) { ESCI_B. /* Wait for FMPLL to LOCK */ FMPLL.R = 0x0180000C. /* 8 MHz xtal: 0x16080000. 40MHz: 0x46100000 while (FMPLL.SYNSR. initESCI_B(). EPREDIV=0. void initSysclk (void) { /* MPC551x: Use the next 6 lines */ /* CRP. 2007 S.CLKSRC.'l'.R = 0x00000006. 4 138 Freescale Semiconductor .R = FrameSpecAndData[j].h" /* Use proper include file such as mpc5510.h */ const uint8_t FrameSpecAndData[]={0x35. while (1) {} } /* /* /* /* Set sysclk = 64MHz running from PLL */ Enable Tx for 10417 baud.B. stop on errors */ ESCI_B.initSysclk changed for MPC5633M support */ Rev 0.3 /* /* /* /* /* /* /* Code main.h or mpc5554.B. */ /* Configure pad for primary func: TxDB */ /* SIU.' '}.LCR. no parity */ Transmit string of characters on eSCI B */ Wait forever */ Qorivva Simple Cookbook.B.PCR[91]. EMFD=0x20*/ /* while (FMPLL.LTR.c: Simple eSCI LIN program */ Rev 0.SYNCR.*/ } } void main(void) { initSysclk().3 Aug 16 2008 SM .Initial version */ Rev 0.PCR[92].2 Jun 04 2008 SM .TXRDY == 0) {} /*Wait for LIN transmit ready = 1*/ ESCI_A. */ /* Enable external oscillator */ /* FMPLL.ESYNCR2.SR.1 Oct 10. /* Write 8 byte to LIN Trans Reg. */ /* Set ERFD to initial value of 6 */ /* FMPLL.B.R = 0x00000005.'H'.SYNCR.SYSCLK. no parity.SR. j< sizeof (FrameSpecAndData). /* Configure pad for primary func: RxDB */ } void TransmitData (void) { uint8_t j. */ /* Select PLL for sysclk */ /* MPC563x: Use the next line */ FMPLL. /* 10417 baud. 13 bit break.B.'o'.B.R = 0xF0000020.R = 0x16080000.changed baud rate to 10.ESYNCR2. /* Module is enabled. must be done by debug scripts or BAM */ 2 SRAM not initialized. */ /* Configure pad for primary func: RxDB */ /* Use the following two lines for MPC555x */ SIU.R = 0x400.CLKCFG = 0X7.' '. /* Configure pad for primary func: TxDB */ SIU.

LINFBRR BDRM. Message Buffer Interface RxD XCVR LIN Figure 30. Exercise: Connect an oscilloscope or LIN tool and verify the transmit output. LINFlex LIN Transmit Example Simplified Block Diagram Qorivva Simple Cookbook. Hence either (1) the LIN transceiver must be connected as shown and the transceiver powered. BDRL BIDR[ID] BIDR[DFL] BIDR[DIR] BIDR[CCS] Task: Transmit the data string “Hello” and three spaces using LIN. or (2) for debug purpuses. 4 Freescale Semiconductor 139 .17 17. MPC56xxB/P/S LINFlex — LIN example parameters Parameter General Master or Slave Master break length CKSUM done in HW CKSUM enabled Baud rate Frame Data ID Data field length Message direction CKSYM type Master 13-bit break Yes (no CRC is used) Yes 10417 Hz for 64 MHz clock String “Hello” and 3 spaces 0x35 8 bytes Transmit Enhanced (LIN 2.1 LINFlex: LIN Transmit Description Table 63. NOTE The RxD receive pin must be able to monitor the TxD transmitted signal. Rev.0) Setting Register[Bit field] LINCR1[MME] LINCR1[MBL] LINCR1[CCD] LINCR1[CFD] LINIBRR. Use parameters as in the table below. MPC56xxB/P/S Crystal OSC0 Clock Generation Module 64 MHz sysclk LINFlex TxD LIN Control LIN Status Baud rate Filter config. the TxD and RxD can be shorted together without using the transceiver.

Rev.Table 64. 4 140 Freescale Semiconductor . MPC56xxB/P/S Signals for LINFlex LIN TransmitScan Example Signal Port MPC56xxB Family SIU Pad Package Pin # Configuration & Selection 100 144 176 Registers QFP QFP BGA (values in hex) 100 144 B2 Port MPC56xxP Family SIU Pad Package Port Configuration Pin # & Selection 100 144 Registers QFP QFP (values in hex) 79 114 MPC56xxS Family SIU Pad Package Pin # Configuration & Selection 144 176 208 Registers QFP QFP BGA (values in hex) 112 140 R14 TxD B2 PCR18=0400 LIN0 TX B3 PCR19=0103 LIN0 no PSMI RX B2 PCR18=0400 TXD B3 PCR19=0503 RXD PSMI31 = 0 B2 PCR18=0400 TxD_ A B3 PCR19=0503 RxD_ A RxD 1 1 B3 80 116 111 139 R13 Qorivva Simple Cookbook.

the status bit could instead be enabled to generate an interrupt request (assuming the INTC is intialized beforehand). Rev.1 Design Mode Use Mode Transition is required for changing mode entry registers. Mode Configurations Summary for MPC56xxB/P/S LINFlex LIN Transmit Example (modes are enabled in ME_ME register) Settings Mode Config. then initiating a mode transition to the same DRUN mode. Peripherals also have configurations to gate clocks on and off. This would allow software to complete other intialization tasks instead of brute force polling of the status bit. Enabled Modes pheral Config. Peripheral Configurations for MPC56xxB/P/S LINFlex LIN Transmit Example (low power modes are not used in example) PeriPeri. ME_RUNPC_1 is selected. Config. Table 65.17. This example changes from DRUN mode to RUN0 mode. However. Register Clock Sources Mode Config. Table 66.2. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral LINFlex 0 LINFlex 1 SIUL (MPC56xxB/S only) PCTL Reg.2 17. therefore peripherals to be used require a non-zero value in their respective ME_PCTL register. then an error condition could be recorded in EEPROM or elsewhere. It is normal to use a timer when waiting for a status bit to change. Hence even enabling the crystal oscillator to be active in the current mode (for example default mode (DRUN)) requires enabling the crystal oscillator in DRUN mode configuration register (ME_DRUN_MC). This minimal example simply polls a status bit to wait for the targeted mode transition to complete. enabling low power. This example by default would have a watchdog timer expire if for some reason the mode transition never completed. One could also loop code on incrementing a software counter to some maximum value as a timeout. Mode PLL1 16 MHz XOSC0 PLL0 (MPC Data IRC 56xxP/S Flash only) On On Off On Off On Off Off I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 (default) RUN0 ME_RUN0_MC 0x001F 0074 16 MHz IRC PLL0 Normal Normal Nomral Normal On On Off Off Other modes are not used in example. The following table summarizes the peripheral configurations used here. Register Value sysclk Selection Memory Power Mode Code Flash Main Voltage Reg. 4 Freescale Semiconductor 141 . If a timeout was reached. # 48 29 68 Other peripheral configurations are not used in example Qorivva Simple Cookbook.

1: run in RUN0 mode only Assign peripheral configuration to peripherals: • LINFlex 0: select ME_RUN_PC0 • LINFlex 1: select ME_RUN_PC0 • SIUL: select ME_RUN_PC0 (56xxB/S) Initiate software mode transition to RUN0 mode • Mode and key • Mode and inverted key • Wait for mode transition complete status flag • Clear transition complete status flag NOTE: if transition does not complete. code flash in normal mode (default) • PLL0 is switched on • Crystal oscilator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk Peri.17.2. 4 142 Freescale Semiconductor .2 Steps and Pseudo Code Table 67. MPC56xxS Steps for LINFlex LIN Transmit Example Pseudo Code Step Relevant Bit Fields MPC56xxB MPC56xxP MPC56xxS RUN0. check status flags such as ME_GS[XOSC] • Verify desired target mode was entered ME_RUN_PC1 = 0x0000 0010 ME_PCTL48 = 0x01 ME_PCTL49 = 0x01 .ME_PCTL68 = 0x01 (56xxB/S only) ME_MCTL =0x4000 5AF0 ME_MCTL =0x4000 A50F wait for ME_IS[I_TC] = 1 ME_IS[I_MTC] = 1 verify ME_GS[S_CURRENT_MODE] = RUN0 Disable • Write keys to clear soft lock bit Watchdog • Clear watchdog enable bit init Peri Clk Gen WEN = 0 SWT_SR = 0x000 0C520 SWT_SR = 0x0000 D928 SWT_CR = 0x8000 010A CGM_ SC_DC0 = 0x80 CGM_ SC_DC0 = 0x80 Initialize peripheral clockgeneration (See appendix: MPC56xxB/P/S Peripheral Clocks) DE0=1 • LINFlex (56xxB/S): peripheral set 1 – sysclk/1 DIV0=0 Qorivva Simple Cookbook. Rev. MPC56xxP. See PLL example.) Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data. DRUN=1 ME_ME = 0x0000 001D CGM_FMPLL_CR (MPC56xxB) CGM_FMPLL[0]_CR (MPC56xxS) = 0x0240 0100 (8 MHz crystal) or 0x1240 0100 (40 MHz crystal) PDO=0 MVRON=1 DFLAON = 3 CFLAON = 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON = 1 SYSCLK=0x4 RUN0=1 RUN_CFG = 1 RUN_CFG = 1 RUN_CFG = 1 TARGET_MODE= RUN0 wait for I_TC = 1 I_TC=1 ME_RUN0_MC = 0x001F 0074 Init Modes and Clock Enable desired modes Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: • 8 MHz xtal: FMPLL[0]_CR=0x02400100 • 40 MHz xtal: FMPLL[0]_CR=0x12400100 (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value. Config. MPC5606B.

4 Freescale Semiconductor 143 . Note: LINFBRR[DIV_F] field is 4 bits. MPC5606B.Table 67.0) Request header transmission (using default error HTRQ=1 controls) 1 Per MPC5606S Microcontroller Reference Manual Rev 3 Table 22-1 for 10417 baud rate. Rev. Qorivva Simple Cookbook. so the value must be less than 16. MPC56xxS Steps for LINFlex LIN Transmit Example Pseudo Code Step Init Put LINFlex hardware in init mode LINFlex_0 Initialize module: (as LIN • Mode = LIN Master Master) • LIN master break length = 13 • CKSUM done in hardware • CKSUM field (for LIN frame) enabled • Module HW put in INIT mode Set baud rate = 10417 for 64 MHz sysclk1 Put LINFlex hardware in normal mode Init pads for FlexLIN_0 TxD & RxD INIT = 0 SLEEP = 0 Relevant Bit Fields MPC56xxB INIT = 1 MME = 1 MBL = 3 CCD = 0 CFD = 0 INIT = 1 LINIBRR = 384 LINFBRR = 0 LINCR1 = 0x0000 0310 SIU_PCR18 = SIU_PCR18 = SIU_PCR18 = 0x0400 0x0400 0x0400 SIU_PCR19 = SIU_PCR19= SIU_PCR19= 0x0103 0x0503 0x0503 PSMI31=0 BDRM = 0x4865 6C6C BDRL = 0x6F20 2020 BIDR = 0x0000 1E35 ID = 0x35 DFL = 7 DIR = 1 CCS = 0 LINCR2[HTRQ] = 1 MPC56xxP LINCR1[INIT] = 1 LINCR1 = 0x0000 0311 MPC56xxS Transmit LIN Frame Load buffer data with 8 bytes: “Hello” and 3 blank spaces (hex 48 65 6C 6C 6F 20 20 20) Init header in Buffer ID register: • ID = 0x35 • Data field length = 8 bytes • Message direction = transmit • Cksum tyipe = Enhanced (for LIN 2. MPC56xxP. Some documentation has a table incorrectly showing value of 16 for this field at 10417 baud.

BIDR. 4 144 Freescale Semiconductor .RUNPC[1] */ ME. enh. LINFLEX_0.modified initModesAndClock.LINCR1. /* Enable DRUN. updated header file */ #include "MPC5604B_0M27V_0101.R = 0x00001E35. Cfg.SC_DC[0]. } void main(void) { volatile uint32_t IdleCtr = 0. SIU.3. RUN0.INIT = 1.*/ /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME.PCTL[68].S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void initPeriClkGen(void) { CGM.R = 0x02400100.RUNPC[0] */ /* Mode Transition to enter RUN0 mode: */ ME.MCTL.LINCR2. initLINFlex_0().syclk=PLL */ ME.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME. /* MPC56xxB/S SIUL: select ME.R = 0x0400. initModesAndClks().h" /* Use proper header file*/ void initModesAndClks(void) { ME. disableWatchdog().MER.GS.R = 0x0000001D.R = 0x0000d928.B.B.R = 0x001F0074.RUNPC[1].PCTL[48]. /* RUN0 cfg: 16MHzIRCON.1 Code MPC560xB /* main.LINFBRR.FMPLL_CR.BDRL.R = 0x00000010. while (1) {IdleCtr++.initial version */ /* Mar 14 2010 SM .SR.DIV_M= 383. /* Clear watchdog enable (WEN) */ } void initLINFlex_0 (void) { LINFLEX_0.SR. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 1 of the next 2 lines depending on crystal frequency: */ CGM.3 17. 0 to FlexCAN C buf. /* Peri.HTRQ = 1. LINFLEX_0. SIU. LINFLEX_0.17.R = 0x0000c520. /* Write keys to clear soft lock bit */ SWT. /* MPC56xxB/P/S LINFlex 0: select ME. SAFE.R = 0x2020206F.R = 0x6C6C6548. /* Enter RUN0 Mode & Inverted Key */ while (ME.LINIBRR.PCR[19]. cksum*/ Request header transmission */ } void transmitLINframe (void) { LINFLEX_0.PLL0ON.CR. /* 8 MHz xtal: Set PLL0 to 64 MHz */ /*CGM.FMPLL_CR. LINFLEX_0.R = 0x4000A50F.B. 1 settings: only run in RUN0 mode */ ME.R = 0x01.} } /* Initialize mode entries */ /* Initialize peripheral clock generation for LINFlex */ /* Disable watchdog */ /* Initialize FLEXCAN 0 as master */ /* Transmit one frame from master */ /* Idle loop: increment counter */ Qorivva Simple Cookbook.R = 0x80. 1 */ /* Oct 30 2009 SM .R = 0x40005AF0. LINFLEX_0.B. LINFLEX_0. /* /* /* /* /* /* /* /* /* /* /* Put LINFlex hardware in init mode */ Configure module as LIN master & header */ Mantissa baud rate divider component */ Fraction baud rate divider comonent */ Configure module as LIN master & header */ MPC56xxB: Configure port B2 as LIN0TX */ MPC56xxB: Configure port B3 as LIN0RX */ Load buffer data most significant bytes */ Load buffer data least significant bytes */ Init header: ID=0x35. 8 B. /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */ } void disableWatchdog(void) { SWT. transmitLINframe().LINCR1.R= 0x00000310.B. Rev.LINCR1.R = 0x8000010A.MCTL. initPeriClkGen().GS.OSC0ON.R= 0x00000311.PCR[18].BDRM.R = 0x12400100. Tx. LINFLEX_0. /* Enter RUN0 Mode & Key */ ME. SWT.DIV_F = 16.R = 0x01.B.RUN[0].c: LINFlex program for MPC56xxB */ /* Description: Transmit one message from FlexCAN 0 buf.R = 0x0103.

RESET modes */ /* Initialize PLL before turning it on: */ /* Use 2 of the next 4 lines depending on crystal frequency: */ /*CGM.CR.R = 0x0000001D.OSC0ON. initPeriClkGen().CMU_0_CSR.LINFBRR.B.GS. Cfg.FMPLL[0].2 /* /* /* /* MPC560xP main. 1 */ Rev Oct 30 2009 SM .INIT = 1.SR. LINFLEX_0.PSMI[31]. /* MPC56xxB/P/S LINFlex 0: select ME.c: LINFlex program for MPC56xxP */ Description: Transmit one message from FlexCAN 0 buf.R = 0x000000000.R = 0x6C6C6548.LINCR1.R= 0x00000311.DIV_F = 16. /* RUN0 cfg: 16MHzIRCON. LINFLEX_0. /* Enter RUN0 Mode & Key */ ME.R = 0x00001E35.R = 0x02400100.MCTL. /* /* /* /* /* /* /* /* /* /* /* /* Put LINFlex hardware in init mode */ Configure module as LIN master & header */ Mantissa baud rate divider component */ Fraction baud rate divider comonent */ Configure module as LIN master & header */ MPC56xxP: Configure port B2 as LIN0TX */ MPC56xxP: Configure port B3 as LIN0RX */ MPC56xxP: LIN0 Pad select mux port B3 */ Load buffer data most significant bytes */ Load buffer data least significant bytes */ Init header: ID=0x35.R = 0x001F0074.PCTL[48]. LINFLEX_0. no PLL monitor */ /*CGM.3. initLINFlex_0().R = 0x01. initModesAndClks(). SAFE.B.R = 0x40005AF0.LINCR2. /* Monitor FXOSC > FIRC/1 (16MHz).B. cksum*/ Request header transmission */ } void transmitLINframe (void) { LINFLEX_0. disableWatchdog().h" /* Use proper include file */ void initModesAndClks(void) { ME. transmitLINframe().R = 0x0400. /* Clear watchdog enable (WEN) */ } void initLINFlex_0 (void) { LINFLEX_0.CMU_0_CSR. /* Peri.Modified initModesAndClks.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME. while (1) {IdleCtr++. 0 to FlexCAN C buf. 8 B.17. } void main(void) { volatile uint32_t IdleCtr = 0.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void initPeriClkGen(void) { } void disableWatchdog(void) { SWT.syclk=PLL */ ME.} } /* Initialize mode entries */ /* Initialize peripheral clock generation for LINFlex */ /* Disable watchdog */ /* Initialize FLEXCAN 0 as master */ /* Transmit one frame from master */ /* Idle loop: increment counter */ Qorivva Simple Cookbook. /* Enable DRUN.R= 0x00000310.LINCR1.*/ /* 8 MHz xtal: Set PLL0 to 64 MHz */ CGM. SWT. LINFLEX_0.LINCR1.R = 0x000000004.GS.R = 0x8000010A.LINIBRR.*//* Monitor FXOSC > FIRC/4 (4MHz). no PLL monitor*/ CGM. LINFLEX_0.PCR[19].R = 0x0503.DIV_M= 383.R = 0x12400100.R = 0x2020206F. Tx. LINFLEX_0. updated header */ #include "jdp_pictus_0106.BIDR. SIU.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME.R = 0x4000A50F. /* Write keys to clear soft lock bit */ SWT.BDRM. /* Enter RUN0 Mode & Inverted Key */ while (ME. LINFLEX_0.R = 0x0000d928.SR. SIU.BDRL. 1 settings: only run in RUN0 mode */ ME.RUNPC[1].PLL0ON. 4 Freescale Semiconductor 145 .HTRQ = 1.PCR[18].RUN[0].FMPLL[0]. RUN0.R = 0.R = 0x00000010.initial version */ Rev Mar 14 1020 SM .CR.R = 0x0000c520. Rev.B. enh. /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME.B. SIU.CR.MCTL.MER.B.

/* Enter RUN0 Mode & Inverted Key */ while (ME. disableWatchdog().SR. LINFLEX_0.CR.B. SWT.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME.R = 0x001F0074.BDRL. /* MPC56xxB/P/S LINFlex 0: select ME. /* 8 MHz xtal: Set PLL0 to 64 MHz */ ME.PCR[19].R = 0x40005AF0.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void initPeriClkGen(void) { CGM.PLL0ON. } /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */ void disableWatchdog(void) { SWT. initPeriClkGen().OSC0ON.MER.R = 0x2020206F.R = 0x4000A50F.MCTL.RUNPC[1] */ ME.CR.R = 0x8000010A.initial version */ Mar 15 2010 SM . 8 B. /* Write keys to clear soft lock bit */ SWT. Cfg.R = 0x00001E35.GS.LINCR1.LINCR2. /* Enable DRUN. while (1) {IdleCtr++.DIV_M= 383.FMPLL[0].3.R = 0x0000001D. LINFLEX_0.PCTL[48].DIV_F = 16.c: LINFlex program for MPC56xxS*/ Description: Transmit one message from FlexCAN 0 buf. RESET modes */ /* Initialize PLL before turning it on: */ CGM.LINIBRR. 1 */ Oct 30 2009 SM . RUN0.R= 0x00000311.B.R = 0x02400100.B.BDRM. updated header */ #include "56xxS_0204.INIT = 1.R = 0x80. SIU. 1 settings: only run in RUN0 mode */ ME.R = 0x01.B. /* MPC56xxB/S SIUL: select ME.RUNPC[1]. initModesAndClks().R = 0x01.h" /* Use proper header file */ void initModesAndClks(void) { ME.syclk=PLL */ ME.R = 0x6C6C6548.R = 0x0000d928. LINFLEX_0.MCTL.LINCR1. } void main(void) { volatile uint32_t IdleCtr = 0.LINCR1.3 /* /* /* /* MPC56xxS main.LINFBRR.SR.PCTL[68].HTRQ = 1.R = 0x0503. cksum*/ Request header transmission */ } Initialize mode entries */ Initialize peripheral clock generation for LINFlex */ Disable watchdog */ Initialize FLEXCAN 0 as master */ Transmit one frame from master */ Idle loop: increment counter */ Qorivva Simple Cookbook.R = 0x0000c520. 4 146 Freescale Semiconductor . SAFE.R= 0x00000310.modified initModesAndClks.PCR[18]. /* Enter RUN0 Mode & Key */ ME.R = 0x00000010.RUN[0]. LINFLEX_0. /* /* /* /* /* /* /* Put LINFlex hardware in init mode */ Configure module as LIN master & header */ Mantissa baud rate divider component */ Fraction baud rate divider comonent */ Configure module as LIN master & header */ MPC56xxS: Configure port B2 as LIN0TX */ MPC56xxS: Configure port B3 as LIN0RX */ } void transmitLINframe (void) { LINFLEX_0.} /* /* /* /* /* /* /* /* /* /* Load buffer data most significant bytes */ Load buffer data least significant bytes */ Init header: ID=0x35. /* Clear watchdog enable (WEN) */ } void initLINFlex_0 (void) { LINFLEX_0. initLINFlex_0().BIDR. transmitLINframe(). Tx.SC_DC[0].17. SIU. enh. LINFLEX_0. 0 to FlexCAN C buf.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME. Rev.GS.R = 0x0400.B. /* RUN0 cfg: 16MHzIRCON. LINFLEX_0.B. /* Peri. LINFLEX_0.

GPRE= 254. configured as a modulus counter. and slow down the oscillations using code changes below. Increase Channel 23 Modulus Counter value.1 eMIOS: Modulus Counter. Alternate exercise: Wire an eMIOS channel to an LED. 3. Example: EMIOS_0. Counter: divide by 1 & count 1000 clocks) eMIOS Channel 0 or 21 (OPWM or OPWMB: Rising edge at 250 Falling edge at 500) EMIOS[0] or EMIOS_0[21] sysclk = 64 MHz 1 MHz eMIOS internal clock (available to all eMIOS channels) eMIOS Channel 1 or 2 or 22 (OPWM or OPWMB: Rising edge at 500 Falling edge at 999) EMIOS[1] or EMIOS[2] or EMIOS_0[22] Time Base A (Counts 1000 1 µsec clocks. The original modulus counter and OPWM modes in early MPC555x devices were later replaced by modulus counter buffered and OPWM buffered modes in some MPC555x devices and in all MPC551x devices. connect an eMIOS output to the speaker (if available) and/or an LED or oscilloscope.R = 64000. eMIOS OPWM Example Qorivva Simple Cookbook.CBDR. 1. Observe pulses on LED. Example: EMIOS_0. MPC5500 / MPC5600 8 MHz Crystal Clocks and PLL eMIOS (eMIOS_0 on MPC56xxB/P/S) eMIOS Prescaler (Divide by 64) eMIOS Channel 23 (Mod.CH[21].CH[23]. Increase Channel 21 falling edge value. so channel 2 is used in the example code. Example: EMIOS_0. then alter code to change the frequency or duty cycle. MPC56xxB/S use eMIOS_0.R = 32000.MCR. The common counter bus is a separate eMIOS channel.CADR. Increase eMIOS Prescaler. 4 Freescale Semiconductor 147 . Rev. available to all eMIOS channels) Figure 31. OPWM Functions Description Task: Provide two Output Pulse Width Modulation (OPWM) signals that are synchronized to a common counter bus.18 18. Observe the outputs. Exercise: If using the MPC5500 Evaluation Board. Code is provided to manage both cases. The MPC563x lacks OPWMB mode on channel 1.B. 2.

MPC56xxB/S Signals for eMIOS OPWM Example Signal Port MPC56xxB Family MPC56xxS Family SIU Pad Package Pin # Port SIU Pad Package Pin # Configuration Configuration 100 144 176 144 176 208 & Selection & Selection QFP QFP BGA QFP QFP BGA Registers Registers (values in hex) (values in hex) 94 95 133 139 C6 B5 A[1] PCR1=0A00 136 166 135 165 B1 A1 EMIOS_0[21] E5 PCR69=0600 EMIOS_0[22] E6 PCR70=0600 A[0] PCR0=0A00 Qorivva Simple Cookbook. 32 33 Package Pin No. PJ8–2 EMIOS[0] EMIOS[1] EMIOS[2] PC0 PC1 not used in MPC551x code only used in MPC563x code Table 69. 144 QFP 122 121 176 QFP 146 145 208 BGA B11 C11 Function Name EMIOS[0] EMIOS[1] EMIOS[2] SIU PCR No. MPC55xx Signals for eMIOS OPWM Example MPC551x Family Signal Pin Name SIU PCR No.Table 68. MPC551x. 496 BGA AD17 AD21 416 BGA AF15 AE15 324 BGA AB10 AB11 208 BGA T4 T5 EVB xPC 563M PJ8–1 n. 179 180 181 MPC555x Family Package Pin No. Rev.a. 4 148 Freescale Semiconductor .

18. 4 Freescale Semiconductor 149 . which will be used as the global counter bus. Config. # 68 72 Other peripheral configurations are not used in example Qorivva Simple Cookbook. Enabled Modes pheral Config. each channel with different duty cycles. the signal polarity will be rising edge for the first match. Register Mode Config. up-counting 1000 eMIOS internal clocks (use value of 1000 – 1 = 999) • eMIOS Channels 0 and 1: OPWM mode based on Time Bus A. Table 71. Settings Clock Sources Mode Mode Config. PeriPeri. I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 16 MHz IRC (default) RUN0 ME_RUN0_MC 0x001F 007D PLL0 Normal Normal Normal Normal On On Off Off Other modes are not used in example Peripherals also have configurations to gate clocks on or off for different modes.2 Design Timing resources used will include: • sysclk: 64 MHz — assume 8 MHz crystal unless noted • eMIOS internal clock: Choose 1 MHz (requires prescaling sysclk by 64) • eMIOS Channel 23: initialize in modulus counter mode. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral SIUL (MPC56xxB/S) eMIOS 0 PCTL Reg. Register Value sysclk Selection PLL1 16MHz XOSC0 PLL0 (MPC IRC 56xxP/S only) On On Off On Off On Off Off Memory Power Mode Data Flash Code Flash Main Voltage Reg. Hence even enabling the crystal oscillator to be active in the default mode (DRUN) requires enabling the crystal oscillator in appropriate mode configuration register (ME_xxxx_MC) then initiating a mode transition. falling edge for the second match 18. This example transitions from the default mode after reset (DRUN) to RUN0 mode. Rev.2. The following table summarizes the peripheral configurations used in this example. Mode Configurations for MPC56xxB/S DSPI SPI to SPI Example Modes are enabled in ME_ME Register.1 Mode Use Summary (MPC56xxB/S only) Mode Transition is required for changing mode entry registers. Table 70. Peripheral Configurations for MPC56xxB/S DSPI SPI to SPI Example Low power modes are not used in example. enabling low power.

CFLAON= 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0=1 - ME_ RUN0_MC = 0x001F 0070 - ME_RUN_PC1 = 0000 0010 MC_PCTL68 = MC_PCTL72 = 0x01 ME_MCTL =0x4000 5AF0. then mode & inverted key TARGET_MODE = • Wait for transition to complete RUN0 S_TRANS • Verify current mode is RUN0 CURRENTMODE init Sysclk Initialize sysclk to 64 MHz. See PLL example.PLL div. Config. RUN0 = 1 init Enable desired modes Modes and Clock Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: (MPC • 8 MHz xtal: FMPLL[0]_CR=0x02400100 56xxPBS • 40 MHz xtal: FMPLL[0]_CR=0x12400100 only) (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value. by 1 • MPC56xxS: Enable Aux Clk 1. Rev. =0x4000 A50F wait ME_GS [S_TRANS] = 0 verify 4 = ME_GS [CURRENTMODE] MPC56xxB: CGM_SC_DC= 0x0000 8000 MPC56xxS: CGM_AC_DC2= 0x80 See PLL Initialization example Assign peripheral configuration to peripherals: • SIUL: select ME_RUN_PC1 (MPC56xxB/S) RUN_CFG = 1 • eMIOS 0: select ME_RUN_PC1 RUN_CFG = 1 Initiate software mode transition to RUN0 mode • Mode & key. then clearing WEN (MPC56xxBPS (56xxPBS) only) - Qorivva Simple Cookbook. running from PLL init Peri Clk Gen (MPC 56xxPBS only) Initialize peripheral clock generation (See appendix: MPC56xxB/P/S Peripheral Clocks) • MPC56xxB: Enable Peri.) Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data. code flash in normal mode (default) • PLL0 is switched on • Crystal oscillator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk MPC56xxB/S: • Peri.2 Design Steps Table 72.2.18. Set 2. eMIOS Modulus Counter and Output Pulse Width (OPWM) Example Pseudo Code Step Relevant Bit Field MPC551x MPC555x MPC56xxB/S ME_ME = 0x0000 001D 8 MHz Crystal: CGM_ FMPLL[0]_CR =0x02400100 DRUN=1. by 1 - See PLL Initialization example - disable Disable watchdog by writing keys to Status Watchdog Register.sysclk div. 1: run in RUN0 mode only PDO=0 MVRON=1 DFLAON. 4 150 Freescale Semiconductor .

up counter • Counter bus select = internal counter • Channel prescaler = 1 • Enable channel prescaler • Enable freezing count in debug mode init EMIOS Set Channel’s A match Data value = 250 ch 0 Set Channel’s B match Data value = 500 Relevant Bit Field MPC551x GPRE = 63(0x3F) ETB = 0 (default) GPREN = 1 GTBE = 1 FRZ = 1 A = 999 MPC555x MPC56xxB/S EMIOS_0_ MCR = 0x3400 3F00 EMIOS_ MCR = 0x3400 3F00 EMIOS_ CH[23]CADR = 999 EMIOS_0_ CH[23]CADR = 999 EMIOS_0_ CCR[23] = 0x8202 0650 EMIOS_ EMIOS_ MODE= 0x50(551x) CCR[23] = CCR[23] = MODE= 0x10(555x) 0x8202 0650 0x8202 0610 BSL = 3 UCPRE= 0 UCPREN = 1 FREN = 1 A = 250 EMIOS_ CH[0]CADR = 250 EMIOS_ CH[0]CBDR = 500 EMIOS_ CH[0]CCR = 0x0000 00A0 or (MPC563x): 0x0000 00E0 EMIOS_0_ CH[0]CADR = 250 EMIOS_0_ CH[0]CBDR = 500 EMIOS_0_ CH[0]CCR = 0x0000 00E0 B = 500 Set up Channel Control: • BSL = Bus selected is counter bus A • EDPOL = leading edge sets.Table 72. 4 Freescale Semiconductor 151 . 563x. up counter buf’d • Mode (555x) = mod. 56xxB/S) = mod. 56xxB/S) = Output PWMB • Mode (MPC555x) = Output PWM Configure pad for eMIOSchannel 0: • Pad assignment= EMIOS Ch 0 • Pad output buffer enabled init EMIOS Set Channel’s A match Data value = 500 ch 1 (MPC563x :channel 2 is used because channel 1 lacks OPWMB mode) Set Channel’s B match Data value = 999 EMIOS_ BSL=0 (default) CH[0]CCR = EDPOL=1 0x0000 Mode=0x60 (551x 00E0 or 563x) Mode=0x20 (555x) PA = 1 (MPC551x) SIU_PCR[32] SIU_PCR[179] = 0x0600 = 0x0E00 PA = 3 (MPC555x) OBE = 1 A = 500 EMIOS_ CH[1]CADR = 500 EMIOS_ CH[1]CBDR = 999 See table: MPC56xxB/P/S Signals EMIOS_0_ CH[1]CADR = 500 EMIOS_0_ CH[1]CBDR = 999 EMIOS_0_ CH[1]CCR = 0x0000 00E0 B = 999 Set up Channel Control: • BSL = Bus selected is counter bus A • EDPOL = leading edge sets. eMIOS Modulus Counter and Output Pulse Width (OPWM) Example (continued) Pseudo Code Step initEMIOS Config eMIOS for 1 MHz internal clock: • Set global prescaler = divide by 64 (63 + 1) • Do not use external time base • Enable global prescaler & internal clock • Enable global time base • Enable freezing counters during debug init EMIOS Set Channel’s A match data for 1000 counts ch 23 (Match value used for modulus counter) Channel 23: Enable channel as up counter • Mode (551x. 563x. trailing clears • Mode (551x. trailing clears • Mode (551x. Rev. 56xxB/S) = Output PWMB • Mode (MPC555x) = Output PWM Configure pad for eMIOS channel 1: • Pad assignment = EMIOS Ch 1 • Pad output buffer enabled EMIOS_ EMIOS_ BSL=0 (default) CH[1]CCR = CH[1]CCR = EDPOL=1 0x0000 0x0000 00A0 Mode=0x60 (551x 00E0 or (MPC563x): or 563x) 0x0000 00E0 Mode=0x20 (555x) PA = 1 (MPC551x) SIU_PCR[33] SIU_PCR[180] = 0x0600 = 0x0E00 PA = 3 (MPC555x) OBE = 1 See table: MPC56xxB/S Signals Qorivva Simple Cookbook.

2. Both channels schedule leading and trailing edges based on the counter of channel 23. Hence the OPWM frequency is 1 kHz.18.3 Design Screenshot The screenshot below shows the two OPWM channels as a result of this design. Qorivva Simple Cookbook. Rev. 4 152 Freescale Semiconductor . which counts to 1000 s.

*/ Notes: */ 1. MPC563x: Mod Ctr Bufd (MCB) int clk */ EMIOS.B.CH[0].B.CCR. SRAM not initialized.CCR. /* MPC555x: Initialize pad for eMIOS chan.LOCK != 1) {}. 50 MHz sysclk.B. /* Freeze channel counting when in debug mode */ EMIOS.CH[0].CH[23].XOSCEN = 1.GPREN = 1.B. Inc.PCR[179]. 40MHz: 0x46100000 while (FMPLL.M.MODE = 0x60.*/ /* MPC551x. MPC563x: Mode is OPWM Buffered */ EMIOS.CLKCFG = 0X7.eMIOS OPWM example */ Description: eMIOS example using Modulus Counter and OPWM modes */ Rev 1.R = 999.MODE = 0x10.*/ /* Wait for PLL to LOCK */ /* FMPLL.CH[0].EDPOL = 1.CH[0].B. /* Enable prescaler.R = 0x16000000.LOCK != 1) {}.2 June 26 1006 S.R = 0x00000006. MPC555x main.3 July 19 2007 SM. Mod Ctr data value*/ Rev 1.initSysclk changed for MPC5633M support */ Copyright Freescale Semiconductor. /* Leading edge when channel counter bus=250*/ EMIOS.c .updated comments & made i volatile uint32_t */ Rev 1. /* Set channel prescaler to divide by 1 */ EMIOS.1 April 13 2006 S.GTBE = 1. */ /* Change clk to PLL normal mode from crystal /* MPC555x including MPC563x: use the next 3 lines for either 8 or 40 MHz crystal FMPLL.MCR.FRZ = 1.Changed to use sysclk of 64 MHz */ Rev 1.R = 0x0600. uses default divide by 1 */ } void initEMIOSch0(void) { /* EMIOS CH 0: Output Pulse Width Modulation */ EMIOS.corrected GPRE to be div by 12 instead of 13*/ Rev 1.CCR.CH[23].ESYNCR1.MCR.GPRE= 63.B.CCR.B.0 Sept 9 2004 S. */ /* Enable external oscillator */ /* FMPLL.CH[23]. EMIOS.18.CH[0].CH[23].Mihalik */ Rev 1.UCPREN = 1. /* 8 MHz xtal: 0x16000000.R = 500.CH[0].BSL = 0x3.B. Ch 23 drives ctr bus A */ Enable eMIOS clock */ Enable global time base */ Enable stopping channels when in debug mode */ */ */ */ */ */ } void initEMIOSch23(void) { /* EMIOS CH 23: Modulus Up Counter */ EMIOS. MMU not initialized. /* MPC555x: Mode is OPWM */ /* Use one of the following 2 lines: */ /* SIU.CH[23]..MCR. EPREDIV=0.FREN = 1. /* Trailing edge when channel counter bus=500*/ EMIOS.5 Jun 04 2008 SM .CADR.B. /* Polarity-leading edge sets output/trailing clears*/ /* Use one of the following two lines for mode (Some MPC555x devices lack OPWMB)*/ /* EMIOS. .CCR. /* Use counter bus A (default) */ EMIOS.*//* MPC551x.B.B.ESYNCR2.SYNSR. /* 8 MHz xtal: 0x16080000.CCR.UCPRE=0. EMIOS. */ /* Set CLKCFG=PLL.MCR.CCR. */ /* Select PLL for sysclk */ /* MPC563x: Use the next line */ /* FMPLL. Rev.SYNSR. must be done by debug scripts or BAM */ 2.R = 0xF0000020. /* /* /* /* /* Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk*/ External time base is disabled.CH[23].BSL = 0x0.CCR.CBDR. 0 output */ SIU.R = 0x0E00.h" /* Use proper include file such as mpc5510.R = 250. EMIOS.CH[23].SYSCLKSEL = 2. EMIOS.1 /* /* /* /* /* /* /* /* /* /* /* /* Code MPC551x. 40MHz: 0x46080000 } void initEMIOS(void) { EMIOS. */ /* MPC551x: Initialize pad for eMIOS chan. 4 Freescale Semiconductor 153 .3 18.MODE = 0x50. 0 output */ } Qorivva Simple Cookbook.B.ESYNCR1.h */ void initSysclk (void) { /* MPC551x: Use the next 6 lines */ /* CRP. */ /* Set ERFD to final value for 64 MHz sysclk /* SIU.B. must be done by debug scripts or in a crt0 type file */ #include "mpc5554.*//* MPC555x: Modulus Counter (MC) */ EMIOS. /* Wait for FMPLL to LOCK */ FMPLL.ESYNCR2.CLKSRC.MCR.MODE = 0x20.PCR[32].B.CADR.3. /* Use internal counter */ EMIOS.B.B.B.M. /* Period will be 999+1 = 1000 clocks (1 msec) */ /* Use one of the following two lines for mode (Note some MPC555x devices lack MCB)*/ /*EMIOS. 2007 All rights reserved.R = 0x00000005.CCR.ETB = 0.SYSCLK.SYNCR. */ /* Set ERFD to initial value of 6 */ /* FMPLL.h or mpc5554. EMFD=0x20*/ /* while (FMPLL.4 Aug 10 2007 SM .CCR.B.Changes for MPC551x.R = 0x16080000.SYNCR.B.B.

*/ /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME.OSC0ON.R = 0x40005AF0. } /* Wait forever */ } 18.void initEMIOSch1(void) { /* EMIOS CH 1: Output Pulse Width Modulation */ EMIOS.R = 999. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 1 of the next 2 lines depending on crystal frequency: */ CGM.8 Mar 14 2010 SM .M.R = 0x0000001D. /* MPC555x: Initialize pad for eMIOS chan. .R = 0x4000A50F.B. 2004–2010 All rights reserved.RUNPC[1] */ ME. /* RUN0 cfg: 16MHzIRCON.R = 0x80.R = 0x01.3. RUN0.SC_DC[2]. /* MPC56xxB/S EMIOS 0: select ME. /* Use counter bus A (default) */ EMIOS.B.CH[1]. /* Set sysclk = 50MHz running from PLL */ initEMIOS(). /* Dummy idle counter */ initSysclk().CH[1].7 Jun 24 2008 SM . /* Enter RUN0 Mode & Inverted Key */ while (ME. /* 8 MHz xtal: Set PLL0 to 64 MHz */ /*CGM.CCR.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME.R = 0x0E00.Mihalik */ Rev 1. /* Initialize eMIOS to provide 1 MHz clock to channels */ initEMIOSch23(). /* Peri.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void initPeriClkGen(void) { CGM. 1 output */ SIU.FMPLL_CR.simplified code */ Rev 1.PCTL[68]. /* Initialize eMIOS channel 0 as OPWM. Mod Ctr data value*/ Rev 1.*/ /* MPC551x. using ch 23 as time base */ while (1) {i++.B. using ch 23 as time base */ initEMIOSch1().Changes for MPC551x.M.R = 0x0600.MCTL.PCTL[72]. 1 settings: only run in RUN0 mode */ ME. /* MPC56xxB/S SIUL: select ME. Inc.PCR[33].R = 0x01.B.BSL = 0x0.2 /* /* /* /* /* /* /* /* /* /* /* /* MPC56xxB/S (MPC56xxB shown with 8 MHz crystal) main. } void disableWatchdog(void) { Qorivva Simple Cookbook. /* Initialize eMIOS channel 1 as OPWM. */ /* Use proper include file */ /* Dummy idle counter */ vuint32_t i = 0.RUNPC[1].modified initModesAndClock.3 July 19 2007 SM.c .eMIOS OPWM example */ Description: eMIOS example using Modulus Counter and OPWM modes */ Rev 1.B. 1 output */ } void main (void) { volatile uint32_t i = 0.B. /* Initialize eMIOS channel 23 as modulus counter*/ initEMIOSch0().R = 500.Changed to use sysclk of 64 MHz */ Rev 1. 50 MHz sysclk. /* Enter RUN0 Mode & Key */ ME. /* Leading edge when channel counter bus=500*/ EMIOS.MER.CBDR. updated header file */ Copyright Freescale Semiconductor.PLL0ON.corrected GPRE to be div by 12 instead of 13*/ Rev 1.CH[1]. #include "MPC5604B_0M27V_0102.CCR.CADR.GS.R = 0x001F0074. /*Polarity-leading edge sets output/trailing clears*/ /* Use one of the following two lines for mode (Some MPC555x devices lack OPWMB) */ /* EMIOS.GS. 4 154 Freescale Semiconductor /* MPC56xxB: Enable peri set 3 sysclk divided by 1*/ .0 Sept 9 2004 S.CH[1].EDPOL = 1.RUN[0].CCR. Cfg.1 April 13 2006 S.syclk=PLL */ ME. */ /* MPC551x: Initialize pad for eMIOS chan.R = 0x00000010.CH[1]. /* Trailing edge when channel's counter bus=999*/ EMIOS.initSysclk changed for MPC5633M support */ Rev 1.MODE = 0x60.CH[1].MCTL.FMPLL_R = 0x12400100. SAFE..4 Aug 10 2007 SM .2 June 26 1006 S.updated comments & made i volatile uint32_t */ Rev 1. MPC563x: Mode is OPWM Buffered */ EMIOS.h" void initModesAndClock(void) { ME.R = 0x02400100. /* Enable DRUN.PCR[180]. /* MPC555x: Mode is OPWM */ /* Use one of the following 2 lines: */ /* SIU.CCR.6 May 22 2009 SM .modified for MPC56xxB/S */ Rev 1.5 Jun 04 2008 SM .MODE = 0x20. Rev.

}

SWT.SR.R = 0x0000c520; SWT.SR.R = 0x0000d928; SWT.CR.R = 0x8000010A;

/* Write keys to clear soft lock bit */ /* Clear watchdog enable (WEN) */

void initEMIOS_0(void) { EMIOS_0.MCR.B.GPRE= 63; /* Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk*/ EMIOS_0.MCR.B.GPREN = 1;/* Enable eMIOS clock */ EMIOS_0.MCR.B.GTBE = 1; /* Enable global time base */ EMIOS_0.MCR.B.FRZ = 1; /* Enable stopping channels when in debug mode */

}

void initEMIOS_0ch23(void) { /* EMIOS 0 CH 23: Modulus Up Counter */ EMIOS_0.CH[23].CADR.R = 999; /* Period will be 999+1 = 1000 clocks (1 msec)*/ EMIOS_0.CH[23].CCR.B.MODE = 0x50; /* Modulus Counter Buffered (MCB) */ EMIOS_0.CH[23].CCR.B.BSL = 0x3; /* Use internal counter */ EMIOS_0.CH[23].CCR.B.UCPRE=0; /* Set channel prescaler to divide by 1 */ EMIOS_0.CH[23].CCR.B.UCPEN = 1; /* Enable prescaler; uses default divide by 1*/ EMIOS_0.CH[23].CCR.B.FREN = 1; /* Freeze channel counting when in debug mode*/ } void initEMIOS_0ch21(void) { /* EMIOS 0 CH 21: Output Pulse Width Modulation*/ EMIOS_0.CH[21].CADR.R = 250; /* Leading edge when channel counter bus=250*/ EMIOS_0.CH[21].CBDR.R = 500; /* Trailing edge when channel counter bus=500*/ EMIOS_0.CH[21].CCR.B.BSL = 0x0; /* Use counter bus A (default) */ EMIOS_0.CH[21].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output */ EMIOS_0.CH[21].CCR.B.MODE = 0x60; /* Mode is OPWM Buffered */ SIU.PCR[69].R = 0x0600; /* MPC56xxS: Assign EMIOS_0 ch 21 to pad */ } void initEMIOS_0ch22(void) { /* EMIOS 0 CH 22: Output Pulse Width Modulation*/ EMIOS_0.CH[22].CADR.R = 500; /* Leading edge when channel counter bus=500*/ EMIOS_0.CH[22].CBDR.R = 999; /* Trailing edge when channel's counter bus=999*/ EMIOS_0.CH[22].CCR.B.BSL = 0x0; /* Use counter bus A (default) */ EMIOS_0.CH[22].CCR.B.EDPOL = 1; /* Polarity-leading edge sets output*/ EMIOS_0.CH[22].CCR.B.MODE = 0x60; /* Mode is OPWM Buffered */ SIU.PCR[70].R = 0x0600; /* MPC56xxS: Assign EMIOS_0 ch 22 to pad */ } void main (void) { volatile uint32_t i = 0; /* Dummy idle counter */ initModesAndClock(); /* Initialize mode entries and system clock */ initPeriClkGen(); /* Initialize peripheral clock generation for DSPIs */ disableWatchdog(); /* Disable watchdog */ initEMIOS_0(); /* Initialize eMIOS 0 to provide 1 MHz clock to channels */ initEMIOS_0ch23(); /* Initialize eMIOS 0 channel 23 as modulus counter*/ initEMIOS_0ch21(); /* Initialize eMIOS 0 channel 0 as OPWM, ch 23 as time base */ initEMIOS_0ch22(); /* Initialize eMIOS 0 channel 1 as OPWM, ch 23 as time base */ while (1) {i++; } /* Wait forever */

}

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 155

19
19.1

eMIOS: PEC, OPWFM Functions
Description

Task: Count the number of input pulses in a time window using an eMIOS channel in pulse edge counting (PEC) mode. Input pulses will be generated by an eMIOS channel in output pulse width and frequency modulation (OPWFM) mode. The time base used for the time window is based on eMIOS channel 23 in modulus counter, as in Section 18, “eMIOS: Modulus Counter, OPWM Functions.” Also per that example, the window open and close times used for the PEC channel are replicated by a separate channel in OPWM mode, for observation purposes. Exercise: Connect eMIOS channels 2 and 3 externally. Optionally, connect an oscilloscope to observe the pulses and their mirrored counting window, channel 2. Execute the code and verify four pulses were counted in the window. Then alter code to reduce the timing window 50% and verify the result.
MPC5500

eMIOS eMIOS Prescaler (Divide by 12) eMIOS Channel 23 (Mod. Counter: counts b1000) eMIOS Channel 0 (OPWM: Rising edge at 200 Falling edge at 600) EMIOS[0]

Crystal 8 MHz

FMPLL with 1.5x Multiplier

12 MHz sysclk

1 MHz eMIOS internal clock

eMIOS Channel 3 (PEC: 400 s window Window open at 200 Window close at 600) EMIOS[3]

eMIOS Channel 2 (OPWFM: 10 kHz, 100 s pulse period)

EMIOS[2]

Figure 32. eMIOS PEC and OPWFM Example Table 73. Signals for eMIOS PEC and OPWFM Example
MPC555x Family Function Name SIU PCR No. 179 181 182 Package Pin No. 496 BGA AD17 P21 R22 416 BGA AF15 AC16 AD15 324 BGA AB10 W12 AA11 208 BGA T4 N7 R6

Signal

EMIOS[0] EMIOS[2] EMIOS[3]

EMIOS[0] EMIOS[2] EMIOS[3]

Qorivva Simple Cookbook, Rev. 4 156 Freescale Semiconductor

19.2

Design

Timing resources used will include: • sysclk: 12 MHz: assume 8 MHz crystal and use default 1.5 multiplier • eMIOS internal clock: Choose 1 MHz (requires prescaling sysclk by 12) • eMIOS channel 2: Generate a 10 kHz signal using OPWFM mode • eMIOS channel 3: Count input pulses using PEC mode; use eMIOS channel 23 for timebase • eMIOS channel 23: Initialize in modulus counter mode, counting 1000 eMIOS internal clocks • eMIOS channel 0: OPWM mode based on Time Bus A — the output pulse will have the same timing parameters as the PEC window of eMIOS channel 3

19.2.1

Steps and Pseudo Code
Step Relevant Bit Field GPRE = 0xB ETB = 0 (default) GPREN = 1 FRZ = 0 Pseudo Code EMIOS_MCR = 0x0400 0B00

Table 74. eMIOS Pulse Edge Counting (PEC) and Output Pulse Width and Frequency Modulation (OPWFM)

initEMIOS

Config eMIOS for 1 MHz internal clock: • Set global prescaler (GPRE+1) = div. by 12 • Use channel 23 for Time Base A, not external • Enable global prescaler and internal clock • Disable freezing counters during debug Set period = 100 eMIOS clocks (1 s each) Set duty cycle = 20 eMIOS clocks (1 s each) Set up Channel Control: • Channel counter’s prescaler = 1 • Enable counter’s prescaler • Set polarity to be active high • Mode = OPWFM, next period update, flag at B Configure GPIO 181: • Pad assignment = EMIOS Ch • Pad output buffer enabled

init EMIOS ch 2 (10 kHz OPWFM)

EMIOS_CH[2]CBDR = 99 EMIOS_CH[2]CADR = 19 UCPRE = 0 UCPREN = 1 EDPOL = 1 MODE = 0x19 PA = 3 OBE = 1 A = 999 EMIOS_CH[23]CADR = 999 EMIOS_CH[23]CCR = 0x0200 0610 EMIOS_CH[2] CCR= 0x0200 0099

SIU_PCR[181] = 0x0E00

init EMIOS ch 23 Set modulus counter to match after 1000 clks (Modulus Counter) (Match value used for modulus counter) Set up Channel Control: • Mode = modulus up counter, using eMIOS internal clk • Counter bus select = internal • Set channel prescale to divide by • Enable channel prescaler

MODE = 0x10 BSL = 3 UCPRE = 0 UCPREN = 1

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 157

Table 74. eMIOS Pulse Edge Counting (PEC) and Output Pulse Width and Frequency Modulation (OPWFM)
Step init EMIOS ch 3 (PEC) Define end of pulse counting window = 650 Set up Channel Control: • Use counter bus A for defining window • Count single edge trigger for counting • Count falling edges • Use main clock for input filtering • Use two clock periods for input filter • MODE = PEC, continuous mode Define start of pulse counting window = 250 (note: writing to this register after mode is set) Configure GPIO 182 • Pad assignment = EMIOS Ch 3 • Enable input buffer init EMIOS ch 0 (OPWM) Set Channel’s A match data value = 250 Set Channel’s B match data value = 650 PA = 3 IBE = 1 A = 250 B = 650 EMIOS_CH[0]CADR = 250 EMIOS_CH[0]CBDR = 650 EMIOS_CH[0]CCR = 0x0000 00A0 BSL = 0 EDSEL = 0 EDPOL = 0 FCK = 1 IF = 1 MODE =0xA Relevant Bit Field Pseudo Code EMIOS_CH[3]CBDR = 650 EMIOS_CH[3]CCR = 0x000C 000A

EMIOS_CH[3]CADR = 250 SIU_PCR[182] = 0x0E00

Set up Channel Control: • BSL = Bus selected is counter bus A BSL = 0 (default) • EDPOL = leading edge sets; trailing clears EDPOL = 1 • Mode = Output PWM, use immediate update MODE = 0x20 Configure GPIO 179: • Pad assignment = EMIOS Ch 0 • Enable output buffer Start timers Read number of pulses Start eMIOS (and eTPU) timers counting PA = 3 OBE = 1 GTBE = 1

SIU_PCR[179] = 0x0E00

EMIOS_MCR[GTBE] = 1 wait for EMIOS_CH[3]CCR[FLAG] = 1 NoOfPulses = EMIOS_CH[3]CCNTR

Wait for channel flag to indicate end of window wait for FLAG = 1 Read number of pulses counted

Clear PEC flag

Write one to FLAG bit to clear it

FLAG = 1

EMIOS_CH[3]CCR[FLAG] = 1

Qorivva Simple Cookbook, Rev. 4 158 Freescale Semiconductor

Rev.2.19.2 Design Screenshots Qorivva Simple Cookbook. 4 Freescale Semiconductor 159 .

10kHz*/ EMIOS.CCR.CH[3].h" void initEMIOS(void) { EMIOS.CH[3].CH[3].B.CH[0].CCR.MODE = 0x10.CH[2].CH[2].BSL = 0x0. /* Mode is Modulus Counter. 19 from 100.R = 650.CH[2].MCR. /* Channel counter's prescaler is loaded & enabled*/ EMIOS.IF = 1.B.CADR. time base is disabled. /* /* /* /* /* /* /* /* /* /* /* /* EMIOS CH 3: Pulse Edge Counting.B.UCPRE=0.PA = 3.3 Code /* main.PCR[182].Initial version */ /* Rev 1.R = 250. } SIU.CH[23].CH[23]. single shot */ Count pulses during 400 usec window */ Count window closes when counter bus=650*/ Use counter bus A which is eMIOS Ch 23 */ Edge Select.OBE = 1. */ /* Ch 23 as mod ctr of 1MHz in & counts to 1000. /* SIU.CH[0]. /* Set channel prescaler to divide by 1 */ EMIOS.FCK = 1.Single edge trigger (count) */ Input filter will use main clock */ Input filger uses 2 clock periods */ Mode is PEC.B. 20 */ /* and OPWM period to 999 from 1000 */ /* Copyright Freescale Semiconductor.B.CH[2].CH[3].R = 250.19.B.UCPREN = 1. /* Duty cycle = 1 usec x (19+1) = 20 usec (20%) */ EMIOS. 2006 All rights reserved. /* Initialize pad AC16 for output */ void initEMIOSch23(void) { /* EMIOS CH 23: Modulus Up Counter: */ /* input = 1MHz eMIOS clock.CCR.CH[23].ETB = EMIOS.PCR[179].CBDR.B. uses default divide by 1 */ } void initEMIOSch3(void) { EMIOS.CCR.GPRE= EMIOS.B. EMIOS. /* EMIOS. /* EMIOS.CBDR. /* Channel counter uses divide by (0+1) prescaler */ EMIOS. S.CH[0]. /* /* /* /* eMIOS clk= sysclk/(GPRE+1)= 12 MHz/12= 1MHz */ Ext.GPREN EMIOS.CH[2].CH[3].PCR[181]. must be done by debug scripts or BAM */ /* 2. /* Counter period= (999+1) clks x 10 usec/clk= 1 msec*/ EMIOS. /* Qorivva Simple Cookbook.CH[3]. */ /* Notes: */ /* 1.B.PCR[182].MCR. internal clock */ EMIOS.R = 650. Ch 3 as PEC */ /* Rev 1. EMIOS. Inc. /* Mode= 0PWFM. /* Initialize pad for eMIOS channel.CADR.CADR.B. Mihalik .CH[0].c .PA = 3.B. /* SIU. = 1. /* Use internal counter */ EMIOS.CCR. 0.EDPOL = 1. Ch2 OPWFM at 10kHz.B.0 Apr 20 2006.B.PA = 3.B.CCR.B.B.MODE= 0x19.CCR. Rev. EMIOS.CH[3]. MMU not initialized. flag on B match*/ SIU.MCR.B.PCR[179]. SRAM not initialized.Corrected OPWFM B.UCPREN = 1.B.MODE = 0xA.OBE = 1.MCR. A values to 99.B.CCR.B.FRZ = 0xB.EDSEL = 0. /* Enable prescaler.B. EMIOS. 0.EDPOL = 1.BSL = 0x3.PCR[181].CCR. EMIOS.CCR. Ch 23 drives ctr bus A */ Enable eMIOS clock */ Disable freezing channel counters in debug mode */ } void initEMIOSch2(void) { } /* EMIOS CH 2: Output Pulse Width & Freq Modulation*/ /* Provide 10kHz output (100usec period) */ /* Input clock is eMIOS clk of 1MHz (1 usec period)*/ EMIOS.CCR. /* EMIOS.IBE = 1.CCR.R = 99.CCR. */ SIU.R = 999. next period update.B.CBDR.CADR. must be done by debug scripts or in a crt0 type file */ #include "mpc5554. continuous */ Count window opens when counter bus=250*/ NOTE: write to CADR after MODE is set */ Initialize pad for eMIOS channel */ Initialize pad for input */ EMIOS CH 0: Output Pulse Width Modulation */ Mirror ch 3 PEC window for observation */ Leading edge occurs when counter bus = 250 */ Trailing edge occurs when counter bus = 650 */ Use counter bus A which is eMIOS Ch 23 */ Polarity-leading edge sets output */ Mode is OPWM */ Initialize pad for eMIOS channel */ Initialize pad for output */ void initEMIOSch0(void) { } /* /* EMIOS. SIU.UCPRE = 0.CCR.1 Jul 16 2007 SM . counts to 1000 */ EMIOS. /* Polarity is active high */ EMIOS.CH[23].B.CCR.R = 19.eMIOS example focusing on PEC and OPWFM*/ /* Description: Configures 1MHz eMIOS clock.MODE = 0x20. /* Period = 1 usec x (99+1) = 100 usec.CH[2].CCR.B. EMIOS. /* EMIOS.B. 4 160 Freescale Semiconductor .CH[0].B.BSL = 0x0.CH[23].

/* Start timers/counters by enabling global time base */ while (EMIOS.FLAG == 0) {} /* Wait for flag at end of window */ NoOfPulses = EMIOS.GTBE = 1. initEMIOS().R.MCR. } /* Wait forever */ } Qorivva Simple Cookbook. initEMIOSch2(). vuint32_t NoOfPulses = 0.void main (void) { uint32_t i = 0. using ch 23 as time base */ eMIOS channel 0 as OPWM to mirror ch 3 PEC window */ Init.CCNTR. Init.CSR. EMIOS. /* /* /* /* /* /* Dummy idle counter */ /* Number of pulses counted in PEC function of eMIOS */ eMIOS to provide 1 MHz clock to eMIOS channels */ eMIOS channel 2 for 10kHz OPWFM */ eMIOS channel 23 as 1K modulus counter*/ eMIOS channel 3 for PEC.B. /* Read number of pulses counted */ EMIOS. initEMIOSch23(). Init. initEMIOSch3(). initEMIOSch0(). Init.CH[3]. Rev.B.FLAG = 1. /* Clear flag */ while (1) {i++.CH[3].CSR.B. 4 Freescale Semiconductor 161 . Init.CH[3].

or oscilloscope. Step through code and observe PWM frequency change. and eTPU application program interface for the PWM function. then update to 2 kHz with 60% duty cycle. Then assign and use the PWM function on eTPU A channel 5.20 20. LED. 496 BGA H9 M3 416 BGA L4 M3 324 BGA K4 K3 208 BGA M4 P2 EVB XPC 563M PJ9–6 PJ9–3 Signal eTPUA5 eTPUA2 ETPUA5 ETPUA2 Qorivva Simple Cookbook. see application note AN2864. eTPU Set 1 PWM Function Example Table 75.1 eTPU: Set 1 PWM Function Description Task: Using the existing Set 1 eTPU functions from the Freescale web site. This example uses the Freescale-provided eTPU utilities. MPC5500 eTPUA TCR1 with prescaler of sysclk/2 divided by 32 eTPU A Channel 5 PWM: initial values: Period: 1000 Hz Duty Cycle: 25% ETPUA5 Crystal 8 MHz FMPLL with 16x multiplier 64 MHz sysclk eTPU A Channel 2 ETPUA2 TCR1 counts at 1 MHz (available to all eTPUA channels and optionally to other eTPUs and eMIOS channels) Figure 33. build an image that loads them to eTPU RAM. Rev. General C Functions for the eTPU. Exercise: If using the MPC555x evaluation board. Signals for eTPU Set 1 PWM Example MPC555x Family Function Name SIU PCR No. 4 162 Freescale Semiconductor . connect eTPU A channel 5 to the speaker. 119 116 Package Pin No. initially at 1 kHz with 25% duty cycle. For further information. Then alter code to configure eTPU A channel 2 for PWM at a frequency of your choice. eTPU code image.

Rev. and use code from Section 10. MPC55xx).2 Design Timing resources used will include: • sysclk = 64MHz: assume 8 MHz crystal. 4 Freescale Semiconductor 163 .2. MPC55xx)”) init eTPU Configure eTPU A for: • MISC not used • eTPUA Input filter clock divided by 8 • eTPUA Channel input filter uses 3 samples • eTPUA TCR1 = sysclk/2 prescaled by 32 • eTPUA TCR2 = sysclk/8 prescaled by 8 • eTPUB configurations as desired Channel = eTPUA[5] Priority = middle Frequency = 1000 Hz Duty cycle = 25% Timebase = TCR1 Timebase frequency = 1 MHz etpu_config_t fs_etpu_init init eTPUA[5] PWM • • • • • • Configure Pad – fs_etpu_pwm_init Configure Pad for eTPUA[5] output Pad Assignment = eAPUA[5] Output Buffer is enabled Open Drain is not enabled Start all eTPU timers and eMIOS timers • • • • Channel = eTPUA[5] Frequency = 2000 Hz Duty cycle = 60% Timebase = 1 MHz SIU_PCR[119] = 0x0E00 PA = 3 OBE = 1 ODE = 0 – – fs_timer_start fs_etpu_pwm_update Start timers Update eTPU[5] Qorivva Simple Cookbook. Note for 40 MHz Crystal used on MPC555x — Replace FMPLL_SYNCR values: 0x1608 0000 with 0x4610 0000 0x1600 0000 with 0x4608 0000 FMPLL_SYNCR = 0x1600 0000 Also for MPC563x: FMPLL_ESYNCR1[CLKCFG] = 7 init FMPLL Set sysclk = 64 (See Section 10. • eTPU TCR1 clock: Count at 1 MHz rate.20. Initialization: eTPU Using Set 1 Function Example Step Relevant Bit Field or Structure Pseudo Code / Function FMPLL_SYNCR = 0x1608 0000 Wait for FMPLL_SYNSR [LOCK] = 1. “PLL: Initializing System Clock (MPC551x. “PLL: Initializing System Clock (MPC551x. 20.1 Steps and Pseudo Code Table 76.” to generate.

h MPC5500 Headers mpc5554.c and main. Table 77.com/etpu.c etpu_util.h. 4 164 Freescale Semiconductor .” Note that the eTPU C compiler is not needed to make this example because the output files are available on the Freescale website at www. except for main. Rev.c etpu_pwm.freescale.3.2. which are listed in Section 20.20. “Code.h Headers for MPC5500 device Qorivva Simple Cookbook. Description Link and Make Files link file make file Freescale eTPU Set 1 Library etpu_pwm.h etpu_struct.h eTPU Utilities etpu_util.h Files written for this example Link file and make file used for this example Host application program interface for pwm function Header file for pwm function Parameters automatically generated by eTPU compiler for pwm function Code image and globals generated by eTPU compiler for all of set 1 functions Host utilities to initialize eTPU. However.h mpc5554_vars. Files Used in Example Provider User Type “Application code” Filename main. etc.2 Files Used For Example Below is a summary of the files used for this project.h etpu_pwm_auto.c main. all the source files used to build the set 1 functions are available and may be useful for reference. copy code image into code RAM. All are available from the Freescale website.h typedefs.h etpu_set1.

4 Freescale Semiconductor 165 . Rev.3 Design Screenshot The screenshot below shows the output at the initial PWM setting of 1 kHz period and 25% duty cycle.20.2. Qorivva Simple Cookbook.

h" /* Use proper include file such as mpc5510.1 Code main. /* Configure pad for signal ETPU_A[5] output */ fs_timer_start ().h" /* eTPU PWM API */ /* User written include files */ #include "main. initSysclk(). 40MHz: 0x46080000 */ } main () { int32_t error_code. /* 8 MHz xtal: 0x16000000. /* Returned value from etpu API functions */ /* Initialize PLL to 64 MHz */ /* Initialize eTPU hardware */ fs_etpu_init ( my_etpu_config.c COPYRIGHT (c) FREESCALE 2006 * * DESCRIPTION: All Rights Reserved * * Sample eTPU program based on gpio_example function. /* Wait forever */ Qorivva Simple Cookbook. Loelinger.h" /* useful utility routines */ #include "etpu_set1.R = 0x0E00.c /***************************************************************************** * FILE NAME: main. /* Timebase (TCR1) freq = 1 MHz */ } while(1). SRAM not initialized. /* Initialize eTPU channel ETPU_A[5] */ error_code = fs_etpu_pwm_init (5.h" /* eTPU standard function set 1 */ #include "etpu_pwm.7 S.B.8 S.3 20. /* Channel ETPU_A[5] */ 2000. must be done by debug scripts or BAM */ /* 2.R = 0x16080000. 4 166 Freescale Semiconductor .SYNCR.h" /* MPC563m specific variables */ #include "etpu_util.ESYNCR1.h or mpc5554. /* Timebase (TCR1) freq is 1 MHz */ SIU. /* Duty cycle = 2500/100 = 25% */ FS_ETPU_PWM_ACTIVEHIGH.B. /* New frequency = 2kHz*/ 6000.20.CLKCFG = 0X7. * * Original author: J. Mihalik 12/May/08 Added options for 40 MHz crystal. Rev. 1000.LOCK != 1) {}. /* Wait for FMPLL to LOCK */ FMPLL.h */ #include "mpc563m_vars.3. S Mihalik * * 0. MMU not initialized. (uint32_t *) etpu_code. /* pointer to the first free parameter */ void initSysclk (void) { /* MPC563x: Use the next line */ FMPLL.SYNSR. 40MHz: 0x46100000 */ while (FMPLL. MPC563m * ****************************************************************************/ /* Notes: */ /* 1. /* Change clk to PLL normal mode from crystal */ /* MPC555x including MPC563x: use the next 3 lines for either 8 or 40 MHz crystal */ FMPLL. */ uint32_t *fs_free_param. 1000000). /* Channel ETPU_A[5] */ FS_ETPU_PRIORITY_MIDDLE.h" /* include application specific defines. /* Enable all timebases */ error_code = fs_etpu_pwm_update (5. G Emerson.SYNCR. modified by K Terry.R = 0x16000000. Mihalik 10/Aug/07 Modified for sysclk = 64 MHz * * 0.PCR[119]. sizeof (etpu_code). /* Frequency = 1000 Hz*/ 2500. must be done by debug scripts or in a crt0 type file */ /* Use one of the next two pairs of lines for header files */ #include "mpc563m. FS_ETPU_TCR1. sizeof (etpu_globals)). /* 8 MHz xtal: 0x16080000. /* New duty cycle = 6000/100= 60% */ 1000000). (uint32_t *) etpu_globals.

......v $ COPYRIGHT (c) FREESCALE 2004 * * DESCRIPTION: All Rights Reserved * * This file contains prototypes and definitions for the sample MPC5500 * * program using the the eTPU GPIO function.... still 1 MHz TCR1 */ #include "etpu_util...v $ * Revision 1.h based on gpio_example... /*MISC value from eTPU compiler link file*/ /*Configure eTPU engine A*/ FS_ETPU_FILTER_CLOCK_DIV8 + FS_ETPU_CHAN_FILTER_3SAMPLE + FS_ETPU_ENTRY_TABLE.2 main..... Mihalik : modified for 50 MHz sysclk...... 0.3 Updated for new build structure. Mihalik : modified for eTPU PWM example */ /* Rev 16/Jul/07 S.....2 K Terry 29/Apr/04 mod'd for GPIO function test * * 0..3.......... Rev. * *========================================================================* * ORIGINAL AUTHOR: Jeff Loeliger (r12110) * * $Log: gpio_example..h. * * 0...* * 0.....20..h /* main.... FS_ETPU_TCR2CTL_DIV8 + ( 7 << 16) + FS_ETPU_TCR1CTL_DIV2 + 3. 4 Freescale Semiconductor 167 .. /*Configure eTPU engine A timebases*/ /*TCR2 prescaler of 8 (7+1)*/ /*TCR1 prescaler of 32 (31+1) applied to sysclk/2*/ /*Configure eTPU engine B*/ FS_ETPU_FILTER_CLOCK_DIV4 + FS_ETPU_CHAN_FILTER_3SAMPLE + FS_ETPU_ENTRY_TABLE.. Qorivva Simple Cookbook. 1 MHz TCR1 */ /* Rev 10/Aug/07 S.. Mihalik : modified for eTPU PWM example */ /* Rev 15/Mar/06 S. 0 /*Configure eTPU engine B timebases*/ /*TCR2 prescaler of 8 (7+1)*/ /*TCR1 prescaler of 4 (3+1)*/ }.. Emerson 2/Nov/04 Added etpu_config_t definition * **************************************************************************/ /* Rev 15/Mar/06 S.....h below */ /************************************************************************* * FILE NAME: $RCSfile: gpio_example..1 2004/12/08 11:45:09 r47354 * Updates as per QOM API rel_2_1 * *...... /*MCR register*/ FS_ETPU_MISC... FS_ETPU_TCR2CTL_DIV8 + ( 7 << 16) + FS_ETPU_TCR1CTL_DIV2 + 31. Mihalik: modified for 64 MHz sysclk. * * 0..4 G.... Loeliger 05/Sep/03 Initial version..h" struct etpu_config_t my_etpu_config = { FS_ETPU_MISC_DISABLE.1 J....h.

144 QFP 4 176 QFP 4 208 BGA D1 Function Name AN[5] SIU PCR No. and use converter ADC0. – MPC555x Family Package Pin No. 496 BGA B9 416 BGA A8 324 BGA A9 208 BGA A7 EVB xPC 563M PJ7–6 Signal AN5 PA[5] Qorivva Simple Cookbook. interrupts. eQADC Single Software Scan Example Table 78. Accuracy. SW Trigger CFIFO0 Conversion Commands 40:1 MUX ADC0 (BN0) Configuration Commands AN0 • • • AN5 • • • AN39 • • • • • • ADC0_CR ADC0_TSCR ADC0_TBCR ADC0_GCCR ADC0_OCCR RFIFO0 RFIFO0 Pop Register Figure 34. Design. which is not faster than 16 MHz. The system clock will be the default of 16 MHz (MPC551x) or 12 MHz (MPC555x). and read the result.21 21. which must not exceed the 6 MHz for maximum resolution. to AN5 and read the converted result. 5 Package Pin No. 4 168 Freescale Semiconductor . MPC5500 eQADC CFIFO0 Push Register CFIFO0 Trigger Mode: Single Scan. will assume here the default system clock. see AN2989. Full accuracy may not be possible because calibration is not implemented here. Use CFIFO 0 in single-scan software-triggered mode. DMA. calibration.1 eQADC: Single Software Scan Description Task: Convert the analog signal on analog channel 5. such as from a variable resistor. Signals for eQADC Single Software Scan Example MPC551x Family Pin Name SIU PCR No. It does not incorporate queues. and Calibration of Analog to Digital Converters on the MPC5500 Family. Send results to RFIFO 0. The ADC_CLK. send conversion command. This minimal example shows how to send configuration commands for ADC0. For information. nor does it clear the last Command FIFO EOQ flag and Result FIFO drain flag. Exercise: Jumper a voltage. or time stamp. Rev.

(Note for the MPC5516 evaluation board: the variable resistor is hard-wired to AN0 that is on PA[0].21. 4 Freescale Semiconductor 169 . so you can simply jumper this to AN5. EOQF] = 1 Qorivva Simple Cookbook. Code here is for illustrative purposes. and run this program. Table 79. (Note: Flags are cleared by writing a 1. On MPC563x devices using the default system clock of 8 MHz. To achieve an ADC clock not exceeding 6 MHz. Relevant Bit Fields ADC0_EN=1 ADC0_CLK_PS = 1(div 4) EQADC_CFPR[0] = 0x8080_0101 Pseudo Code – EOQ = 1 BN = 0 R/W = 0 (write) ADC_REGISTER=0x8001 ADC_REG_ADDRESS=1 MODE0=1. Therefore existing flags at 1 are cleared. Rev. we round up to a value of prescaler of 4. the default system clock is 16 MHz.) On MPC555x devices using the default system clock of 12 MHz.2 Design For MPC551x devices. SSE0 = 1 wait for RFDF0 = 1 EQADC_CFCR[0] = 0x0410 wait EQADC_FISR[EOQ] = 1 EQADC_FISR[EOQ] = 1 EQADC_CRPR[0] = 0x8000_0500 EQADC_CFCR[0] = 0x0410 Wait EQADC_FISR[RFDF]=1 read EQADC_RFPR[0] EQADC_FISR [RFDF. an ADC prescaler of 4 provides an ADCCLK = 12 MHz / 4 = 3 MHz. Because we need an even integer value that keeps the ADCCLK under 6 MHz. but actually causes all flags in the FISR register to clear because the compiler will read the current value from the register. value for ADC0: • Enable ADC0 • Prescaler = 4 —>ADC0 Control Reg = 0x8001 Send one write configuration command to CFIFO0: • End of Queue (only sending one message here) • Select ADC0 (Buffer Number 0) • Configuration command is Write (not Read) • ADC Control Register value = 0x8001 • ADC Control Register address = 0x1 Trigger CFIFO0 using single scan SW mode (Send configuration command(s) to ADC0’s registers) Wait for End of Queue Flag for CFIFO0 Clear End of Queue Flag for CFIFO0 Send Conversion Command Send one conversion command to CFIFO0: • Convert Channel 5 • Use Result FIFO0 • Use ADC0 (BN0) • Format is unsigned • Set EOQ Trigger CFIFO0 using single scan SW mode (Sends conversion command(s) to ADC 0) Read Result Wait for RFIFO0 Drain Flag to set Read result from Result FIFO Pop Register 0 Clear flags for any subsequent use. SSE0=1 wait for EOQF0 = 1 EOQF = 1 CHANNEL_NUMBER = 5 MESSAGE_TAG = 0 BN = 0 FMT = 0 EOQ = 1 MODE0 = 1. This provides an ADCCLK = 16 MHz / 4 = 4 MHz. OR in the “1”. the prescaler will be 16 MHz sysclk / 6 MHz = 8/3 = 2. which is on PA[5].67. The proper way to clear a flag is to write to the entire register. eQADC Single Software Scan Step init ADC0 Determine Control Reg. an ADC prescaler of 4 provides an ADCCLK = 8 MHz / 4 = 2 MHz. and write back the new value.

/* Clear RFIFO 0's Drain Flag */ EQADC. conversion in loop */ Rev 1.FISR[0]. and send result to RFIFO 0*/ EQADC.h */ void initADC0(void) { EQADC.EOQF = 1.RFPR[0].B. 4 170 Freescale Semiconductor .21. /* ADC result */ ResultInMv = (uint32_t)((5000*Result)/0x3FFC). static uint32_t ResultInMv = 0. added result in millivolts.FISR[0]. /* ADC conversion result */ /* ADC conversion result in millivolts */ #include "mpc563m.Changed ADCCLK prescaler for faster MPC551x default */ sysclk.h or mpc5554. */ Rev 1.0 Sept 13. ReadResult().RFDF = 1. while (1) { SendConvCmd(). must be done by debug scripts or in a crt0 type file */ static uint32_t Result = 0.h" /* Use proper include file such as mpc5510. /* Conversion command: convert channel 5 */ /* with ADC0.R = 0x80000500. initADC0().B.R = 0x0410.R.CFPR[0].2 Jun 12 2008 SM.CFCR[0]. 2004 S. SRAM not initialized. } /* Send CFIFO 0 a ADC0 configuration command */ /* enable ADC0 & sets prescaler= divide by 2*/ EQADC.c: performs a simple ADC conversion of channel 5 using ADC0 */ Rev 1. All Rights Reserved */ Notes: */ 1.B. } } /* Dummy idle counter */ /* Enable ADC0 only on eQADC */ /* Send one conversion command */ /* Read result */ /* Wait forever */ Qorivva Simple Cookbook.RFDF != 1){} /* Wait for RFIFO 0's Drain Flag to set*/ Result = EQADC.EOQF = 1. Mihalik.B.CFCR[0]. /* ADC result in millivolts */ EQADC.3 /* /* /* /* /* /* /* /* /* Code main.EOQF !=1) {} /* Wait for End Of Queue flag */ EQADC.FISR[0]. /* Clear End Of Queue flag */ void SendConvCmd (void) { EQADC.R = 0x0410.B.R = 0x80801001. Rev. MMU not initialized. /* Clear CFIFO's End of Queue flag */ } int main(void) { int i = 0. used channel 5.FISR[0].Moved initADC0 out of while loop */ Copyright Freescale. /* Trigger CFIFO 0 using Single Scan SW mode */ } void ReadResult(void) { while (EQADC.1 Jul 18 2007 SM. 2007. set EOQ.FISR[0].CFPR[0]. i++. /* Trigger CFIFO 0 using Single Scan SW mode */ while (EQADC. must be done by debug scripts or BAM */ 2.

. etc. Use ANS7 on PC[7] pin for the Dashboard Cluster Demo’s AUX MOTOR pot. 4 Freescale Semiconductor 171 . 34. “Scan Mode description. * ANS0. etc. Scan Mode is used where “a sequential conversions of N channels specified in the NCMR registers is continuously performed. section 28. etc. and verify results.3. Add an injected channel using an external trigger of PIT or eMIOS.1 ADC: Software Trigger.” Qorivva Simple Cookbook. on MPC56xxB/S use NCMR1and CDR 32.”1 Exercise: Connect an analog channel to the pot on the EVB. ANS1. Add additional channels and connect to a known voltage. . Rev. ADC Continuous SW Scan Example Simplified Block Diagram Table 80. . etc. MPC56xxB/P/S Crystal OSC0 Clock Generation Module 64 MHz sysclk ADC_0 Normal Conversion Mask Register (NCMR0)* Ch 0* Ch 1* A/D Ch 2* .3.1. . 1. Rev 3.. etc. Figure 35. Channel Data Registers (CDRx)* CDR 0* CDR 1* CDR 2* . Continuous Scan Description Task: Convert a few standard ADC channel inputs by starting a normal conversion which is software triggered. . MPC56xxB/P/S Signals for Continous SW Scan Example Signal Port MPC56xxB Family SIU Pad Package Pin # Configuration & Selection 100 144 176 Registers QFP QFP BGA (values in hex) 39 38 40 53 52 54 R9 T9 P9 Port MPC56xxP Family SIU Pad Package Port Configuration Pin # & Selection 100 144 Registers QFP QFP (values in hex) 29 31 28 43 47 41 MPC56xxS Family SIU Pad Package Pin # Configuration & Selection 144 176 208 Registers QFP QFP BGA (values in hex) 72 71 70 88 87 86 T13 T12 R12 ANS0 ANS1 ANS2 B8 PCR24=2000 ANS0 B9 PCR25=2000 ANS1 B10 PCR26=2000 ANS2 B7 PCR23=2400 AN0 B8 PCR24=2400 AN1 C1 PCR33=2400 AN2 C0 PCR30=2000 ANS0 C1 PCR31=2000 ANS1 C2 PCR32=2000 ANS2 1. Instead of One Shot Mode.22 22. download program. 33. etc. ANS0 ANS1 ANS2 . ANS2. Jumper ATD’s VDD to 5 V. 2. MPC5606S Microcontroller Reference Manual. . and on MPC560xP use NCMR0 and CDR 0.

MA=1 ANS[10]. 4 172 Freescale Semiconductor .2V rail 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 ANS[0] ANS[0] 33 ANS[1] ANS[1] 34 ANS[2] ANS[2] 35 ANS[3] ANS[3] 36 ANS[4] ANS[4] 37 ANS[5] ANS[5] 38 ANS[6] ANS[6] 39 ANS[7] ANS[7] 40 ANS[8] ANS[8] 41 ANS[9] ANS[9] 42 ANS[10] ANS[10] 43 ANS[11] ANS[11] 44 ANS[12] ANS[12] 45 ANS[13] ANS[13] 46 ANS[14] ANS[14] 47 ANS[15] ANS[15] 48:59 ANS[26:17] The following channels use multiplex selector signals.22. MPC56xxB/P/S Mapping of ADC Channels to ADC Input Pins MPC56xxB ADC Channel Number Pin Function Name ANP[0] ANP[1] ANP[2] ANP[3] ANP[4] ANP[5] ANP[6] ANP[7] ANP[8] ANP[9] ANP[10] ANP[11] ANP[12] ANP[13] ANP[14] ANP[15] MPC56xxP ADC 0 ADC 1 Pin Function Name MPC56xxS Pin Pin Function Function Name Name AN[0] AN[0] AN[1] AN[1] AN[2] AN[2] AN[3] AN[3] AN[4] AN[4] AN[5] AN[5] AN[6] AN[6] AN[7] AN[7] AN[8] AN[8] AN[9] AN[9] AN[10] AN[10] AN[11] (shared) AN[12] (shared) AN[13] (shared) AN[14] (shared) Temp. MA=1 Qorivva Simple Cookbook.2. 1.1 Design Mapping of ADC Channels to Analog Input Pins Table 81.2 22. MA=0 ANS[10]. MA=0 65 ANX[0]. Rev. MA[0:2] 64 ANX[0].

MA=6 ANX[3]. MA=4 ANX[2]. MA=5 ANX[1]. MA=6 ANX[2]. This example changes from DRUN mode to RUN0 mode. MA=1 ANX[1]. MA=2 ANS[10]. Rev. MA=3 ANX[3]. MA=4 ANX[3]. the status bit could instead be enabled to generate an interrupt request (assuming the INTC is intialized beforehand). MA=6 ANX[1]. MA=4 ANX[0]. MA=2 ANX[2]. MPC56xxB/P/S Mapping of ADC Channels to ADC Input Pins 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 ANX[0]. If a timeout was reached. then initiating a mode transition to the same DRUN mode. It is normal to use a timer when waiting for a status bit to change. MA=3 ANX[1]. MA=7 ANX[3]. MA=5 ANX[2]. Hence even enabling the crystal oscillator to be active in the current mode (for example default mode (DRUN)) requires enabling the crystal oscillator in DRUN mode configuration register (ME_DRUN_MC). MA=7 22. MA=3 ANX[2]. MA=0 ANX[2]. MA=2 ANX[1]. MA=3 ANX[0]. However. MA=6 ANX[0]. MA=1 ANX[3]. then an error condition could be recorded in EEPROM or elsewhere. MA=5 ANS[10]. This example by default would have a watchdog timer expire if for some reason the mode transition never completes. MA=5 ANX[0]. MA=7 ANS[10]. MA=4 ANX[1]. MA=0 ANX[3]. Qorivva Simple Cookbook. MA=2 ANX[3]. MA=0 ANX[1].2 Mode Use Mode Transition is required for changing mode entry registers.2. MA=7 ANX[2]. 4 Freescale Semiconductor 173 . MA=7 ANX[1]. MA=2 ANX[0]. MA=4 ANS[10]. MA=3 ANS[10]. MA=5 ANX[3]. MA=6 ANS[10]. One could also loop code on incrementing a software counter to some maximum value as a timeout. MA=1 ANX[2].Table 81. This would allow software to complete other intialization tasks instead of brute force polling of the status bit. This minimal example simply polls a status bit to wait for the targeted mode transition to complete.

Peripherals also have configurations to gate clocks on and off. Mode Configurations Summary for MPC56xxB/P/S ADC Continuous SW Scan Example (modes are enabled in ME_ME Register) Settings Mode Config. 4 174 Freescale Semiconductor . Enabled Modes pheral Config. Register Value sysclk Selection Memory Power Mode PLL1 (MPC Data 56xxP/S Flash only) Off Off Code Flash Main Voltage Reg. ME_RUNPC_1 is selected. Rev. enabling low power. Mode 16MHz IRC On On XOSC0 PLL0 I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 (default) RUN0 ME_RUN0_MC 0x001F 0074 16 MHz IRC PLL0 Off On Off On Normal Normal Nomral Normal On On Off Off Other modes are not used in example. Qorivva Simple Cookbook. Register Clock Sources Mode Config. so peripherals to be used require a non-zero value in their respective ME_PCTL register. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral ADC 0 SIUL (MPC56xxB/S only) PCTL Reg. # 32 68 Other peripheral configurations are not used in example. Peripheral Configurations for MPC56xxB/P/S ADC Continous SW Scan Example (low power modes are not used in example) PeriPeri. Config.Table 82. Table 83. The following table summarizes the peripheral configurations used here.

) Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data.ME_PCTL68 = 0x01 (56xxB/S only) ME_MCTL =0x4000 5AF0 ME_MCTL =0x4000 A50F wait for ME_GS[S_MTRANS] = 0 Assign peripheral configuration to peripherals: • ADC 0: select ME_RUN_PC0 RUN_CFG = 1 • SIUL: select ME_RUN_PC0 (56xxB/S) RUN_CFG = 1 Initiate software mode transition to RUN0 mode • Mode and key TARGET_MODE= • Mode and inverted key RUN0 • Wait for mode transition to complete S_MTRANS NOTE: if transition does not complete. Rev. MPC56xxP. See PLL example. CFLAON = 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0=1 ME_RUN0_MC = 0x001F 0074 Init Modes and Clock Enable desired modes Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: • 8 MHz xtal: FMPLL[0]_CR=0x02400100 • 40 MHz xtal: FMPLL[0]_CR=0x12400100 (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value. check status flags such as ME_GS[XOSC] • Verify desired target mode was entered Disable • Write keys to clear soft lock bit Watchdog • Clear watchdog enable bit init Peri Clk Gen init Pads Initialize peripheral clockgeneration (See appendix: MPC56xxB/P/S Peripheral Clocks) • ADC (56xxB/S): peripehral set 3. Config. DRUN=1 ME_ME = 0x0000 001D CGM_FMPLL_CR (MPC56xxB) CGM_FMPLL[0]_CR (MPC56xxS) = 0x0240 0100 (8 MHz crystal) or 0x1240 0100 (40 MHz crystal) PDO=0 MVRON=1 DFLAON = 3. MPC5606B.3 Steps and Pseudo Code Table 84. 4 Freescale Semiconductor 175 .sysclk/1 Init pads for converting ANS0.2.22. ANS1. MPC56xxS Steps for ADC Continous SW Scan Example Pseudo Code Step Relevant Bit Fields MPC56xxB MPC56xxP MPC56xxS RUN0. code flash in normal mode (default) • PLL0 is switched on • Crystal oscilator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk Peri. 1: run in RUN0 mode only ME_RUN_PC1 = 0x0000 0010 ME_PCTL32 = 0x01 . ANS2 verify ME_GS[S_CURRENT_MODE] = RUN0 SWT_SR = 0x000 0C520 SWT_SR = 0x0000 D928 SWT_CR = 0x8000 010A CGM_ SC_DC2 = 0x80 CGM_ SC_DC2 = 0x80 WEN = 0 DE2=1 DIV2=0 SIU_PCR24 = SIU_PCR23 = SIU_PCR30 = SIU_PCR25= SIU_PCR24= SIU_PCR31= SIU_PCR26= SIU_PCR25= SIU_PCR33= 0x2000 0x2400 0x2000 Qorivva Simple Cookbook.

MPC56xxP. MPC56xxS Steps for ADC Continous SW Scan Example (continued) Pseudo Code Step init ADC0 Initialize ADC 0 module & start conversions: • Configure Analog Clock as sysclk/2 (PLL/2 = 32 MHz for this example) • Mode is Scan Mode (continuous) • Trigger: on chip not used • ADC in normal mode. MPC5606B.in reference manuals: MPC5604B/C Microcontroller Reference Manual Rev 2 Table 25-1. 4 176 Freescale Semiconductor . not power down mode Relevant Bit Fields MPC56xxB ADCLKSEL = 0 MODE = 1 TRIGEN =0 PWDN = 0 ADC_ NCMR1 = 0x0000 0007 ADC_CTR1 = 0x0000 8606 ADC0_ NCMR0 = 0x0000 0007 ADC0_CTR0 = 0x00008606 ADC0_ NCMR1 = 0x0000 0007 ADC0_CTR1 = 0x00008606 MPC56xxP MPC56xxS ADC_MCR = 0x2000 0000 (MPC56xxB) ADC0_MCR = 0x2000 0000 (MPC56xxS) Enable normal sampling of desired channels for MPC56xxP: ADC 0 (Input pins ANS0. Rev. AD_CLK” table row for 32 MHz fmax.Table 84. and MPC5606S Microcontroller Reference Manual Rev 3 Table 28-2. Qorivva Simple Cookbook. ADC_MCR [NSTART] = 1 (MPC56xxB) ADC0_MCR [NSTART] = 1 (MPC56xxS) Wait for first ADC_ ISR[EOC] =1 Wait for first ADC0_ ISR[EOC] =1 Wait for first ADC0_ ISR[EOC] =1 CDATA Result0 = Result0 = Result0 = ADC_CDR32[ ADC0_CDR0 ADC0_CDR32[ CDATA] [CDATA] CDATA] Result1 = Result1 = Result1 = ADC_CDR33[ ADC0_CDR1 ADC0_CDR33[ CDATA] [CDATA] CDATA] Result2 = Result2 = Result2 = ADC_CDR34[ ADC0_CDR2 ADC0_CDR34[ CDATA] [CDATA] CDATA] ResultInMv0 = int16_t (5000*Result0 / 0x3FF) ResultInMv1 = int16_t (5000*Result1 / 0x3FF) ResultInMv2 = int16_t (5000*Result2 / 0x3FF) Convert resutls to mv 1 Per “Max AD_CLK frequency and related configuration settings. ANS1. ANS2) CHAN0:2 = 1 MPC56xxS: CHAN32:34 =1 Initialize conversion timings for 32 MHz ADCLK1 Trigger ADC Loop: Start Normal Conversions: • Start normal conversion (immediately) Wait for completion of first chain (Note: VALID flag clears when read) Read results INPLATCH = 1 INPCMP = 3 INPSAMP = 6 NSTART = 1 wait for EOC = 1. MPC5604P Microcontroller Reference Manual Rev 2 Table 23-2.

R = 0x00000010. RUN0.CDATA.MCTL. } Qorivva Simple Cookbook. /* MPC56xxB/S SIU: select ME.R = 0x2000.CR. /* Dummy idle counter */ initModesAndClock().simplified initModesAndClock.B.R = 0x2000. /* Read ANS2 conversion result data */ ResultInMv[0] = (uint16_t) (5000*Result[0]/0x3FF). /* ADC conversion results */ uint16_t ResultInMv[3]. ANS1 using scan mode (continuous) */ Rev 1 Oct 26 2009 S Mihalik .ADC_ADC_scan example for MPC56xxS */ Description: Converts inputs ANS0. /* 8 MHz xtal: Set PLL0 to 64 MHz */ ME.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME.MCTL.B. Rev. /* MPC56xxB/P/S ADC 0: select ME. /* Read ANS1 conversion result data */ Result[2]= ADC_0. SIU.PCTL[32].R = 0x01.R = 0x0000001D.PCR[32].CDR[33].FMPLL[0].RUNPC[1].GS.22.R = 0x01.B.CDATA. /* Peri. 1 settings: only run in RUN0 mode */ ME.CDR[34].R = 0x00008606. SIU.R = 0x0000d928. 4 Freescale Semiconductor 177 . /* Converted result in mv */ ResultInMv[2] = (uint16_t) (5000*Result[2]/0x3FF). ADC_0. /* Enter RUN0 Mode & Key */ ME.B.R = 0x40005AF0.CDR[33].syclk=PLL0*/ ME.SR.MCR.R = 0x0000c520. /* ADC conversion results in mv */ void initModesAndClock(void) { ME. /* Write keys to clear soft lock bit */ SWT.NSTART=1. /* RUN0 cfg: 16MHzIRCON.R = 0x20000000.CDATA.3 /* /* /* /* /* Code (MPC56xxS shown) main.R = 0x8000010A.R = 0x4000A50F.VALID != 1) {}.PCR[31]. 2010. initPeriClkGen(). SWT.R = 0x001F0074. All rights reserved. ADC_0.R = 0x02400100.R = 0x2000.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void disableWatchdog(void) { SWT. RESET modes */ /* Initialize PLL before turning it on: */ CGM.GS.CTR[1].NCMR[1].PCR[30].RUNPC[1] */ ME.R = 0x80. /* Enable DRUN. Inc 2009.R = 0x00000007.RUN[0].1 Mar 15 2010 S Mihalik.PCTL[68]. /* Converted result in mv */ i++.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME.MER. /* Wait for last scan to complete */ Result[0]= ADC_0.B.OSC0ON. /* Converted result in mv */ ResultInMv[1] = (uint16_t) (5000*Result[1]/0x3FF).PLL0ON. /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */ } void main (void) { vuint32_t i = 0.SC_DC[2].c .B.B.CR. /* Enter RUN0 Mode & Inverted Key */ while (ME. /* Read ANS0 conversion result data */ Result[1]= ADC_0.SR.CDR[32].MCR. new header */ Copyright Freescale Semiconductor. /* Clear watchdog enable (WEN) */ } void initPeriClkGen(void) { CGM. Cfg. disableWatchdog(). SIU. ADC_0. SAFE.initial version */ Rev 1.h" /* Use proper header file */ uint16_t Result[3]. ADC_0. /* Initialize mode entries and system clock */ /* Disable watchdog */ /* Initialize peripheral clock generation for DSPIs */ /* MPC56xxS: Initialize PC[0] as ANS0 */ /* MPC56xxS: Initialize PC[1] as ANS1 */ /* MPC56xxS: Initialize PC[2] as ANS2 */ /* /* /* /* Initialize ADC0 for scan mode */ Select ANS0:2 inputs for conversion */ Conversion times for 32MHz ADClock */ Trigger normal conversions for ADC0 */ } while (1) { while (ADC_0. */ #include "56xxS_0200.

etc. MPC56xxB Crystal OSC0 64 MHz sysclk Clock Generation Module ADC ANS0 ANS1 ANS2 . eMIOS channel 3 is configured for OPWM. ADC CTU Example Simplified Block Diagram Qorivva Simple Cookbook. .1 ADC . Connect ANS1:2 to other known voltages.23 23. ADC inputs ANS1 and ANS2 are continuously scanned. Exercise: Make the connections shown below. . 23 (ModCtr) Chan.. In this example. use the Cross Triggering Unit (CTU) to trigger a conversion from an eMIOS channel event. 4 178 Freescale Semiconductor . Normal Conversion Mask Register (NCMR) Ch 32 Ch 33 A/D Ch 34 . etc. where the channel is configured as Single Action Input Capture (SAIC). 2 FLAG (with DMA=1) CTU Event Cfg Reg 2 (Selects ADC chan 32) EMIOS0[3] Figure 36. . Both channels use eMIOS channel 23 configured as modulus counter for their time base. Channel Data Registers CDR 32 CDR 33 CDR 34 . Verify the eMIOS channel 2 injects an ADC command which reads the pot value. To generate an input signal. 3 (OPWM) Chan. . Rev. Connect ANS0 to a potentiometer or a known voltage. Cross trigger ADC ch 32 eMIOS0 EMIOS0[2] Chan. . etc.CTU: eMIOS Trigger (MPC560xB) Description Task: While performing normal conversions on a few standard ADC channel inputs. EMIOS and the CTU are configured so an input signal on eMIOS channel 2 will cause an event that “cross triggers” a conversion for ANS0. 2 (SAIC) Chan. .

2) Signal Name (per Table 2-3) ANP 0:15 — ANS 0:15 ANS 16:27 — ANX 0. Rev. Table 86. ADC channel numbers and CTU trigger channel numbers (per MPC5607B Microcontroller Reference Manual.Table 85. MA 0:7 ADC Channel # (per Fig.2. MA 0:7 ANX 0. MPC56xxB Mapping of Analog Signals. 4 Freescale Semiconductor 179 . and CTU channel numbers. 23-1) ADC 0 0:15 — 32:47 48:59 — 64:71 72:79 80:87 88:95 ADC 1 0:15 — — — — — — — — 0:15 16:31 Not mapped — 32:39 40:47 48:55 56:63 CTU_EVTCFTRx[CHANNEL_VALUE] (per Table 30-6) Qorivva Simple Cookbook. Rev.2 23. MPC56xxB Signals for ADC CTU Example Signal Port MPC56xxB Family SIU Pad Configuration Package Pin # & Selection Registers 100 144 176 (values in hex) QFP QFP BGA PCR24=2000 PCR25=2000 PCR26=2000 PCR2=0503 PCR3=0600 39 38 40 5 68 53 52 54 9 90 R9 T9 P9 F2 K15 ANS0 ANS1 ANS2 eMIOS0[2] eMIOS0[3] B8 B9 B10 A2 A3 23.1 Design Channel Mappings The following table provides the numbering used for analog input signal names. MA 0:7 ANX 0. ADC channel numbers. MA 0:7 ANX 0.

One could also loop code on incrementing a software counter to some maximum value as a timeout. Peripheral Configurations for MPC56xxB ADC CTU Example (low power modes are not used in example) PeriPeri. If a timeout was reached.2 Mode Use Mode Transition is required for changing mode entry registers.23. so peripherals to be used require a non-zero value in their respective ME_PCTL register.2. Table 87. then an error condition could be recorded in EEPROM or elsewhere. Mode 16MHz IRC On On XOSC0 PLL0 I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 (default) RUN0 ME_RUN0_MC 0x001F 0074 16 MHz IRC PLL0 Off On Off On Normal Normal Nomral Normal On On Off Off Other modes are not used in example. ME_RUNPC_1 is selected. This would allow software to complete other intialization tasks instead of brute force polling of the status bit. Hence even enabling the crystal oscillator to be active in the current mode (for example default mode (DRUN)) requires enabling the crystal oscillator in DRUN mode configuration register (ME_DRUN_MC). # 32 57 68 72 Other peripheral configurations are not used in example. Enabled Modes pheral Config. Qorivva Simple Cookbook. Mode Configurations Summary for MPC56xxB ADC CTU Example (modes are enabled in ME_ME Register) Settings Mode Config. This example changes from DRUN mode to RUN0 mode. However. Register Clock Sources Mode Config. Rev. This minimal example simply polls a status bit to wait for the targeted mode transition to complete. enabling low power. the status bit could instead be enabled to generate an interrupt request (assuming the INTC is intialized beforehand). It is normal to use a timer when waiting for a status bit to change. then initiating a mode transition to the same DRUN mode. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral ADC 0 CTUL SIUL eMIOS PCTL Reg. Register Value sysclk Selection Memory Power Mode PLL1 (MPC Data 56xxP/S Flash only) Off Off Code Flash Main Voltage Reg. Peripherals also have configurations to gate clocks on and off. Table 88. Config. The following table summarizes the peripheral configurations used here. 4 180 Freescale Semiconductor . This example by default would have a watchdog timer expire if for some reason the mode transition never completes.

sysclk/1 DIV2=0 Init pads: • eMIOS0[2] as input • eMIOS0[3] as output • ANS0 • ANS1 • ANS2 Qorivva Simple Cookbook. eMIOS: peri. DRUN=1 Pseudo Code ME_ME = 0x0000 001D CGM_FMPLL_CR (MPC56xxB) = 0x0240 0100 (8 MHz crystal) PDO=0 MVRON=1 DFLAON = 3._MTRANS] = 0 verify ME_GS[S_CURRENT_MODE] = RUN0 SWT_SR = 0x000 0C520 SWT_SR = 0x0000 D928 SWT_CR = 0x8000 010A CGM_ SC_DC0 = 0x0000 8000 SIU_PCR2 = 0x0503 SIU_PCR3 = 0x0600 SIU_PCR24 = 0x2000 SIU_PCR25 = 0x2000 SIU_PCR26 = 0x2000 Disable • Write keys to clear soft lock bit Watchdog • Clear watchdog enable bit init Peri Clk Gen init Pads WEN = 0 Initialize peripheral clockgeneration (See appendix: MPC56xxB/P/S Peripheral Clocks) DE2=1 • ADC.23.3 Steps and Pseudo Code Table 89.ME_PCTL72 = 0x01 ME_MCTL =0x4000 5AF0 ME_MCTL =0x4000 A50F wait for ME_GS[S. CTU. CFLAON = 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0=1 RUN_CFG = 1 RUN_CFG = 1 RUN_CFG = 1 RUN_CFG = 1 TARGET_MODE= RUN0 S_MTRANS ME_RUN0_MC = 0x001F 0074 Init Modes and Clock Enable desired modes Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration. 1: run in RUN0 mode only Assign peripheral configuration to peripherals: • ADC 0: select ME_RUN_PC0 • CTUL: select ME_RUN_PC0 • SIUL: select ME_RUN_PC0 • eMIOS 0: select ME_RUN_PC0 Initiate software mode transition to RUN0 mode • Mode and key • Mode and inverted key • Wait for mode transition to complete NOTE: if transition does not complete.2. Rev. MPC5606B Steps for MPC56xxB ADC CTU Example Step Relevant Bit Fields RUN0. check status flags such as ME_GS[XOSC] • Verify desired target mode was entered ME_RUN_PC1 = 0x0000 0010 ME_PCTL32 = 0x01 ME_PCTL57 = 0x01 . code flash in normal mode (default) • PLL0 is switched on • Crystal oscilator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk Peri. using progessive clock switching: • 8 MHz Crystal: FMPLL[0]_CR=0x02400100 Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data. 4 Freescale Semiconductor 181 . Config. set 3.ME_PCTL68 = 0x01 .

Rev. AD_CLK” table row for 32 MHz fmax. MPC5606B Steps for MPC56xxB ADC CTU Example (continued) Step init ADC Initialize ADC module but do not start conversions: • Configure Analog Clock as sysclk/2 (PLL/2 = 32 MHz for this example) • Mode is Scan Mode (continuous) • Trigger: on chip not used • ADC in normal mode.in reference manual: MPC5604B/C Microcontroller Reference Manual Rev 2 Table 25-1. which will generate PWM output for eMIOS channel 2 input ADC_MCR [NSTART] = 1 NSTART = 1 GTPREN = 1 EMIOS_0_MCR[GPREN] = 1 Per “Max AD_CLK frequency and related configuration settings. OPWM example for details) Channel 2: intialize as SAIC • Bus selected is ch 23 • Edge Selected is a single edge • Edge Polarity is trigger on rising edge • Mode is SAIC • Flag enables IRQ or DMA request • DMA selected on flag (NOTE: CTU request generated instead of DMA request when CTU is enabled for that eMIOS channel) — — CTU_EVTCFGR[2] = 0x0000 8010 init eMIOS EMIOS_0_MCR = 0x3000 3F00 EMIOS_0_CHAN[23]CADDR = 999 EMIOS_0_CHAN[23]CCR = 0x8202 0650 EMIOS_0_CHAN[3]CADDR = 250 EMIOS_0_CHAN[3]CBDDR = 500 EMIOS_0_CHAN[3]CCR = 0x0000 00E0 EMIOS_0_CHAN[2]CCR = 0x0102 0082 — BSL = 0 EDSEL = 0 EDPOL = 1 MODE = 2 FEN = 1 DMA = 1 Normal trigger Cross trigger 1 Start Normal Conversions: • Start normal conversion (immediately) Start eMIOS module counting. not power down mode • Enable CTU • Do not start conversions yet Enable normal sampling of desired channels for ADC 0 (Input pins ANS1. Qorivva Simple Cookbook. OPWM example for details) Channel 23: initialize as modulus counter: Count 1000  1 usec clocks -> 1 kHz period (see Modulus Counter. ANS2) Initialize conversion timings for 32 MHz ADCLK1 Relevant Bit Fields ADCLKSEL = 0 MODE = 1 TRIGEN =0 PWDN = 0 CTUEN = 1 NSTART = 0 CHAN33:34 =1 INPLATCH = 1 INPCMP = 3 INPSAMP = 6 ADC_NCMR1 = 0x0000 0006 ADC_CTR1 = 0x0000 8606 Pseudo Code ADC_MCR = 0x2002 0000 init CTU Configure event on eMIOS ch. 4 182 Freescale Semiconductor . 2 to trigger ADC ch. OPWM example for details) Channel 3: initialize as OPWMB: Use Channel 23 as time base (see Modulus Counter. 0 • Enable trigger mask TM = 1 • Select input pint ANS0 (ADC ch 32=CTU ch 16) CHANNEL_VALUE = 16 (0x10) eMIOS module: configure for 1 MHz internal clock (see Modulus Counter.Table 89.

MCR. /* Ch 3: Match "B" is 500 */ EMIOS_0. Rev.R = 0x2000.R = 250.R = 0x0000c520.initial version */ Mar 14 2010 S Mihalik .CH[2].R = 999.GS.R = 0x0000d928.R= 0x01020082.PCTL[72].PLL0ON. /* Enter RUN0 Mode & Inverted Key */ while (ME. /* RUN0 cfg: 16MHzIRCON.MCTL. 1 settings: only run in RUN0 mode */ ME.CBDR.CR.CADR.PCR[2].simplified initModesAndClock.RUNPC[1] */ ME. /* Write keys to clear soft lock bit */ SWT. SWT. 2010.ADC CTU example for MPC56xxB */ Description: Convert inputs ANS1:2 using normal scan mode and */ use eMIOS channel in SAIC mode with the CTU to trigger ANS0 */ Nov 11 2009 S Mihalik .R = 0x80. /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */ } void initPads (void) { SIU.R= 0x000000E0.c .R = 0x2000.R = 0x001F0074.23.CH[3]. /* Read converstion result from ADC input ANS0 */ void initModesAndClock(void) { ME.R = 0x02400100.3 /* /* /* /* /* /* Code main.R = 0x8000010A.h" /* Use proper header file */ uint16_t Result.CH[23].S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void disableWatchdog(void) { SWT.syclk=PLL0 */ ME.R = 500. /* MPC56xxB: Initialize PB[9] as ANS1 */ SIU.PCTL[57].R = 0x40005AF0. /* Ch 3: Match "A" is 250 */ EMIOS_0. /* MPC56xxB: Initialize PB[10] as ANS2 */ } void initADC(void) { ADC. /* Select ANS1:2 inputs for normal conversion */ ADC. /* MPC56xxB CTUL: select ME. RUN0.R = 0x00008606. updated header file */ Copyright Freescale Semiconductor.CCR.R = 0x0600. 4 Freescale Semiconductor 183 . /* MPC56xxB: Initialize PB[8] as ANS0 */ SIU. /* Initialize eMIOS module for 1 MHz clock */ EMIOS_0.R = 0x2000. /* Ch 2: Mode is SAIC. /* MPC56xxB ADC 0: select ME.R=0x82020650. RESET modes */ /* Initialize PLL before turning it on: */ CGM.MCR.RUNPC[1] */ ME. time base = ch 23 */ } Qorivva Simple Cookbook.R = 0x01.CTR[1]. /* Initialize ADC */ ADC. /* Conversion times for 32MHz ADClock */ } void initCTU(void) { CTU. /* MPC56xxB: Initialize PA[3] as eMIOS[3] output */ SIU.GS.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME.PCTL[32].CH[3].FMPLL_CR.NCMR[1]. time base = ch 23 */ EMIOS_0.R = 0x30003F00.MER.B.R = 0x01. /* Ch 3: Mode is OPWMB.EVTCFGR[2].R = 0x0503. /* Clear watchdog enable (WEN) */ } void initPeriClkGen(void) { CGM.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME. Cfg. Inc 2009.R = 0x01. All rights reserved.R = 0x20020000.R = 0x00000010. /* Ch 32: set mode as modulus counter */ EMIOS_0.PCR[24].SR.R = 0x00000006.R = 0x0000001D.R = 0x01.PCTL[68]. /* Enter RUN0 Mode & Key */ ME.R = 0x4000A50F.RUN[0].B. /* 8 MHz xtal: Set PLL0 to 64 MHz */ ME. /* Ch 32: period will be 999+1 = 1K clks (1msec)*/ EMIOS_0.R = 0x00008010.CCR. /* Enable DRUN. /* Peri. /* MPC56xxB eMIOS 0: select ME. /* MPC56xxB SIU: select ME. */ #include "MPC5604B_0M27V_0102.RUNPC[1] */ ME. SAFE.MCTL.SC_DC[2].PCR[26].CCR.SR.PCR[25].CH[23].PCR[3].CADR. /* Config event on eMIOS Ch 2 to trig ANS[0] */ } void initEMIOS_0(void) { EMIOS_0.CH[3].RUNPC[1]. /* MPC56xxB: Initialize PA[2] as eMIOS[2] input */ SIU.OSC0ON.

ADC for normal conversions but don't start yet*/ initCTU(). /* Configure desired CTU event(s) */ initEMIOS_0(). 4 184 Freescale Semiconductor .CDR[33].B. /* Wait for cross trigger to complete */ Result = ADC.VALID != 1) {}. /* Dummy idle counter */ } initModesAndClock(). Rev.CDATA.MCR. /* Start eMIOS counters to generate cross trigger */ while (1) { while (ADC.void main (void) { vuint32_t i = 0. OPWM */ ADC.NSTART=1.CDR[32]. /* Initialize eMIOS channels as counter. } Qorivva Simple Cookbook. /* Read ANS0 conversion result data */ i++.MCR. /* Initialize mode entries and system clock */ disableWatchdog().B.B.B. SAIC. /* Init. /* Initialize peripheral clock generation for DSPIs */ initPads().GPREN= 1. /* Trigger normal conversions for ADC0 */ EMIOS_0. /* Initialize pads used in example */ initADC(). /* Disable watchdog */ initPeriClkGen().

4 Freescale Semiconductor 185 . Clearing EOQ re-enables transmission if commands are present. PCS0_C MPC5500/ MPC5600 Master DSPI (DSPI_C or DSPI_0) Push Register TxFIFO SOUT_C SIN_C Crystal 8 MHz Clocks and PLL CTAR0 Shift Register RFIFO Pop Register 64 MHz sysclk SCK_C SCK_D Slave DSPI (DSPI_D or DSPI_B or DSPI_1) Push Register TxFIFO SOUT_D SIN_D Shift Register RFIFO CTAR0 Pop Register SS_D Figure 37.) Change the data being sent and received. which immediately enables SPI operation. Debug tip: verify that SCK is at the desired baud rate by setting master DSPI MCR[CONT_SCK] with the debugger. Rev.1 DSPI: SPI to SPI Description Task: Transmit data from a DSPI configured as master to a DSPI configured as slave.24 24. Initialization and data is set up first before clearing the DSPI’s HALT bit. The data sent by the master is 0x1234. DSPI Single SPI Transfer Example (Signals shown use DSPI_C and DSPI_D) Qorivva Simple Cookbook. This example shows how to configure a Clock and Transfer Attributes Register (CTAR) and other necessary items. and the slave will return 0x5678. Setting the transmit command’s End Of Queue (EOQ) bit puts the DSPI in the stopped state at the end of that frame’s transmission. Exercise: (Note: external connections shown below are not required on MPC555x and MPC563x because of code that connects DSPIs internally in the SIU. then send a single command. Interrupts and DMA are not used.

Rev. Signals for Single SPI Transfer Example using DSPI_C and DSPI_B Signal Pin Name MPC551x Family SIU PCR # 21 60 22 61 24 62 23 63 Package Pin # 144 QFP 129 90 128 89 126 88 127 87 176 QFP 157 114 156 113 152 110 153 107 208 BGA D8 H14 A9 H15 C9 J14 B9 K14 Function Name SIU PCR # 110 105 109 102 108 104 107 103 MPC555x Family Package Pin # 496 BGA M26 R27 N27 T27 M27 N28 T28 P28 416 BGA R23 N25 P24 P25 N24 N23 P26 M26 324 BGA L19 J21 K20 K21 J20 J19 K22 H22 208 BGA J13 EVB xPC 563M PJ2–9 PCS0_C SS_B SCK_C SCK_B SIN_C SOUT_B SOUT_C SIN_B PB5 PD12 PB6 PD13 PB8 PD14 PB7 PD15 PCSC[0] PCSB[0] SCKC SCKB SINC SOUTB SOUTC SINB G16 PJ1–10 H14 J16 G14 G13 PJ2–8 PJ1–9 PJ2–7 PJ1–8 H15 PJ1–12 G15 PJ1–7 Qorivva Simple Cookbook.Table 90. 4 186 Freescale Semiconductor . Signals for Single SPI Transfer Example using DSPI_C and DSPI_D Signal Function Name MPC555x Family SIU PCR # 110 106 109 98 108 100 107 99 Package Pin # 496 BGA M26 R28 N27 N26 M27 U24 T28 N24 416 BGA R23 N26 P24 T25 N24 U23 P26 P23 324 BGA L19 J22 K20 M21 J20 N19 K22 K19 208 BGA J13 H16 H14 J15 G14 — H15 H13 PCS0_C SS_D SCK_C SCK_D SIN_C SOUT_D SOUT_C SIN_D PCSC[0] PCSD[0] SCKC SCKD SINC SOUTD SOUTC SIND Table 91.

4 Freescale Semiconductor 187 . MPC56xxB/P/S Signals for Single SPI Transfer Example using DSPI_0 and DSPI_1 Signal Port MPC56xxB Family MPC56xxP Family MPC56xxS Family SIU Pad Package Pin # Port SIU Pad Package Port SIU Pad Package Pin # Configuration Configuration Pin # Configuration & Selection & Selection & Selection 100 144 176 100 144 144 176 208 Registers Registers Registers QFP QFP BGA QFP QFP QFP QFP BGA (values in hex) (values in hex) (values in hex) 27 94 28 93 31 91 30 92 40 133 42 132 45 130 44 131 R6 C[4] PCR36=0604 C6 A[5] PCR5=0503 P6 C[5] PCR37=0604 D6 A[6] PCR6=0503 T7 C[7] PCR39=0103 A7 A[7] PCR7=0604 R7 C[6] PCR38=0604 B7 A[8] PCR8=0103 5 8 7 2 9 4 98 6 11 H[4] PCR103=0604 47 57 44 48 46 49 45 50 61 73 54 62 56 63 55 66 R5 N9 T6 P8 P7 N8 N7 R7 PCS0_0 A15 PCR15=0604 SS_1 SCK_0 SCK_1 SIN_0 E5 PCR69=0903 PSMI9=02 A14 PCR14=0604 E4 PCR68=0903 PSMI7=01 A12 PCR12=0103 14 C[13] PCR43=0D03 PSMI14=00 13 2 15 10 142 12 B[9] PCR25=0604 B[4] PCR20=0503 B[7] PCR23=0503 B[5] PCR21=0604 B[8] PCR24=0604 B[6] PCR22=0503 SOUT_1 C5 PCR37=0604 SOUT_0 A13 PCR13=0604 SIN_1 C4 PCR36=0103 PSMI8=00 Qorivva Simple Cookbook.Table 92. Rev.

To keep the example simple. etc. Both master and slave SPIs will use the same CTAR values. as well as the SPI command itself. 4.625 nanoseconds. 15. since there is just one device for SPI communication. the system clock period is about 15 nsec. The formula for after SCK delay in the MPC5554 is: tASC = (system clock period)  (PASC prescaler of 1.) With a system clock frequency of 64 MHz. In order to show an example of how to determine these items. the MSB will be sent first in this example to make it easier to decipher the logic analyzer trace shown in the end of this section. This example will use: PCSSCK (PCS to SCK delay prescaler) = 0 (for a prescaler value of 1) CSSCK (PCS to SCK delay scaler) = 7 (for a scaler value of 256) This gives a PCS to SCK delay of: tCSC = 15 ns  1  256 = 3.2 Design Determining the timing clock and transfer attributes. This example will use: PASC (After SCK delay prescaler) = 0 (for a prescaler value of 1) ASC (After SCK delay scaler) = 7 (for a prescaler value of 256) This gives an after SCK delay of: tASC = 15 ns  1  256 = 3.” The MC33394 minimum value is 105 ns. 8. The parameters below are based on the MC33394 data sheet.1 Clock and Transfer Attribute Register Parameters A 64 MHz sysclk is used in this example. 4 188 Freescale Semiconductor . Rev.3. are used (except where noted). 24. the MC33394. depends entirely on the connected device’s specification. 8. the system clock period is about 15 ns. Clock Polarity: The MC33394 uses SCK low in the inactive state. p. The formula for PCS to SCK delay in the MPC5554 is: tCSC = (system clock period)  (PCSSCK prescaler of 1. specifications from an actual device.” The MC33394 minimum value is 50 ns. The MC33394 calls this parameter “enable lag time. Slave SPIs must use CTAR0. 15 nanoseconds will be used in the timing parameter calculations that follow. PCS to SCK Delay (tCSC): The MC33394 calls this parameter the “enable lead time.84 s Qorivva Simple Cookbook. 4. which has a period of 15.5 or 7)  (ASC delay scaler of 2.3. Frame Size: The MC33394 uses 16 bits for SPI communication.2. rev 2.5 or 7)  (CSSCK delay scaler of 2. which is the rising edge since clock polarity is set to make SCK low when inactive.) With a system clock frequency of 64 MHz.24. 16 etc.5 11/2002. The master SPI only needs one CTAR. 21–22. LSB First: Although the MC33394 requires the least significant bit is sent first. pp.84 s After SCK Delay (tASC): This is the delay from the last edge of SCK to the negation of PCS. Clock Phase: The MC33394 captures data on the leading edge.

4. Faster baud rates require increasing the SRC field value in the respective pad configuration registers. but we will use close to 100 kHz here. this example will use: DBR = 0 (double baud rate feature not used) PBR = 2 (for a prescaler of 5) BR = 7 (for a scaler of 128) Hence the baud rate is SCK Baud Rate = (64 MHz / 5)  ((1+0) / 128) = 100 kHz (10 s SCK period) 24.Delay after Transfer (tDT): This is the length of time between the negation of PCS on the current frame and the assertion of PCS for the next frame. This example’s baud rate of 100 kHz is relatively slow for a SPI.2 SPI Command The SPI command will be written to the SPI’s push register. called “CS Negated Time. This example will use: PDT (Delay after Transfer prescaler) = 2 (for a prescaler value of 5) DT (Delay after Transfer scaler) = 2 (for a prescaler value of 8) This gives an after SCK delay of: tDT = 15 ns  5  8 = 600 ns Baud Rate (BR): The baud rate maximum for the MC33394 is 5 MHz.2. 8. 4 Freescale Semiconductor 189 . Transfer Data: The slave DSPI (DSPI_D or DSPI_B) will have data 0x1234 in its shift register to respond to a transfer from the master DSPI (DSPI_C). The formula for DSPI baud rate in the MPC5554 is: SCK Baud Rate = (fSYS / PBR prescaler)  ((1+DBR)/ (BR scaler)) With a system clock frequency of 64 MHz.2. so the EOQ bit will be set. The MC33394 has a minimum time. Rev.) With a system clock frequency of 64 MHz. The fields are listed below. Peripheral Chip Selects used: PCS0 will be connected from the master to the SS of the slave DSPI. 5 or 7)  (DT delay scaler of 2. tDT = (system clock period)  (PDT prescaler of 1. the system clock period is about 15 ns. Clock and Transfer Register: CTAR0 is required for the slave DSPI. which will then automatically fall through the FIFO. 3. SIU_PCR[SRC]. The master will use CTAR0 also. 16 etc. Continuous Peripheral Chip Select: Continuous PCS is not used and is inactive between transfers. 24. End of Queue: Only one transfer is used in this example. Qorivva Simple Cookbook. This example will only focus on a single transfer. again based on the MC33394 data sheet.” of 500 ns.3 Pad Slew Rate Control versus SPI Baud Rate Pads must be driven harder for faster signals. but the calculation is shown here in case of a different situation. The master will transmit 0x5678 for data.

Settings Clock Sources Mode Mode Config. Enabled Modes pheral Config. Register Mode Config.4 Mode Use Summary (MPC56xxB/P/S only) Mode Transition is required for changing mode entry registers. Hence even enabling the crystal oscillator to be active in the default mode (DRUN) requires enabling the crystal oscillator in appropriate mode configuration register (ME_xxxx_MC) then initiating a mode transition. This example transitions from the default mode after reset (DRUN) to RUN0 mode. Table 93. Config. Table 94.2. I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 16 MHz IRC (default) RUN0 ME_RUN0_MC 0x001F 007D PLL0 Normal Normal Normal Normal On On Off Off Other modes are not used in example Peripherals also have configurations to gate clocks on or off for different modes. 4 190 Freescale Semiconductor . PeriPeri.24. Peripheral Configurations for MPC56xxB/P/S DSPI SPI to SPI Example Low power modes are not used in example. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral DSPI 0 DSPI 1 SIUL (MPC56xxB/S) PCTL Reg. Register Value sysclk Selection PLL1 16MHz XOSC0 PLL0 (MPC IRC 56xxP/S only) On On Off On Off On Off Off Memory Power Mode Data Flash Code Flash Main Voltage Reg. Mode Configurations for MPC56xxB/P/S DSPI SPI to SPI Example Modes are enabled in ME_ME Register. # 4 5 68 Other peripheral configurations are not used in example Qorivva Simple Cookbook. Rev. enabling low power. The following table summarizes the peripheral configurations used in this example.

Rev.2. CFLAON= 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0=1 - ME_ RUN0_MC = 0x001F 0070 RUN_CFG = 1 ME_RUN_PC1 = 0000 0010 MC_PCTL4 = ME_PCTL5 = ME_PCTL68 = 0x01 ME_MCTL =0x4000 5AF0. =0x4000 A50F wait ME_GS [S_TRANS] = 0 verify 4 = ME_GS [CURRENTMODE] MPC555x: SIU_DISR = 0x0000 C0FC - TARGET_MODE = RUN0 S_TRANS MPC563x: SIU_ISEL2.24. 1 PDO=0 MVRON=1 DFLAON.MPC56xxB/S: Enable Peri Set 2. Config. then mode & inverted key • Wait for transition to complete • Verify current mode is RUN0 CURRENTMODE (Optional step . to peripherals: • DSPI 0: select ME_RUN_PC1 • DSPI 1: select ME_RUN_PC1 • SIUL: select ME_RUN_PC1 (MPC56xxB/S) Initiate software mode transition to RUN0 mode • Mode & key. 1: run in RUN0 mode only Assign peripheral config. code flash in normal mode (default) • PLL0 is switched on • Crystal oscillator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk MPC56xxB/S: • Peri.) Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data. See PLL example. running from PLL init Peri Clk Gen (MPC 56xxPBS) Initialize peripheral clock generation (See appendix: MPC56xxB/P/S Peripheral Clocks) . MPC563x only) • MPC555x: Connect master DSPI C to slave DSPI D internally • MPC563x: Connect master DSPI C to slave DSPI D internally init Sysclk Initialize sysclk to 64 MHz.allows not using external connections for MPC555x.5 Steps and Pseudo Code Pseudo Code MPC551x MPC555x MPC56xxB/P/S Table 95.R = 0x00A8A000 See PLL Initialization example MPC56xxB/S: CGM_SC_DC1= 0x80 Qorivva Simple Cookbook. Steps and Pseudo Code Table (shown using DSPI_C as Master. 4 Freescale Semiconductor 191 . Initialize data to be received on master SPI Initialize data to be received on slave SPI Relevant Bit Fields RecDataMaster = 0 RecDataSlave = 0 ME_ME = 0x0000 001D 8 MHz Crystal: CGM_ FMPLL[0]_CR =0x02400100 init Enable desired modes DRUN=1.sysclk div. DSPI_D as Slave) Step Data Init. Modes RUN0 = 1 and Clock Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: (MPC • 8 MHz xtal: FMPLL[0]_CR=0x02400100 56xxPBS • 40 MHz xtal: FMPLL[0]_CR=0x12400100 only) (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value.

MSTR = 1 CONT_SCKE = 0 DCONF = 0 FRZ = 0 MTFE = 0 PCSSE = 0 ROOE = 0 PCSIS0 = 1 DOZE. DSPI_D as Slave) (continued) Step Disable Watchdog init DSPI_C or DSPI_0 (master) Disable watchdog by writing keys to Status Register.84 us (>50 ns required) • Delay after transfer = 800 ns (>500 ns required) • Double Baud Rate feature not used • Baud Rate = 78.84 usec (>105 ns required) • After SCK delay = 3. module disable not used • Transmit FIFO not disabled • Receive FIFO not disabled • Transmit FIFO not cleared • Receive FIFO not cleared • Sample points not used • Halt state enabled (STOPPED) for initialization Configure CTAR0 for MC33394 • Frame Size = 16 bits • Clock polarity: low inactive state • Data is captured on leading edge • Most (not least) significant bit is first in frame • PCS to SCK delay = 3.125 kHz (<5 MHz required) Change DSPI from STOPPED to RUNNING Configure pads for Master (DSPI_C or DSPI_0): • SOUT_x output • SIN_x input • SCK_x output • PCSC0_x output Note: Faster baud rates would require increasing the pad’s slew rate control in SIU_PCR[SRC]. CSSCK=7 PASC = 0.Table 95. 4 192 Freescale Semiconductor . then clearing WEN (MPC56xxBPS only) Initialize DSPI as master • SPI is master • SCK will not be continuous • DSPI is configured for SPI only • Debug Freeze does not halt transfers • Modified transfer format is not used • Peripheral chip select strobe is not used • Ignore receive FIFO overflows • Peripheral Chip Select 0 inactive state = high • Doze. Steps and Pseudo Code Table (shown using DSPI_C as Master. BR = 7 HALT = 0 DSPIC_MCR = 0x8001 0000 SIU_PCR[23] = 0x0A00 SIU_PCR[24] = 0x0900 SIU_PCR[22] = 0x0A00 SIU_PCR[21] = 0x0A00 DSPI0_MCR = 0x8001 0000 DSPI0_CTAR0 = 0x780A 7727 Relevant Bit Fields Pseudo Code MPC551x MPC555x MPC56xxB/P/S See PLL Initialization example DSPI0_MCR = 0x8001 0001 DSPIC_MCR = 0x8001 0001 SIU_PCR[107] See table: = 0x0A00 MPC56xxB/P/S SIU_PCR[108] Signals = 0x0900 Connections Table SIU_PCR[109] for SIU_PCR = 0x0A00 Registers and SIU_PCR[110] Values = 0x0A00 Qorivva Simple Cookbook. Rev. ASC = 7 PDT = 2. MDIS = 0 DIS_TXF = 0 DIS_RXF = 0 CLR_TXF = 0 CLR_RXF = 0 SMPL_PT = 0 HALT = 1 DSPIC_CTAR0 = 0x780A 7727 FSIZE = 0xF CPOL = 0 CPHA = 0 LSBE = 0 PCSSCK = 0. DT = 2 DBR = 0 PBR = 2.

DSPI_1): • SCK_x input • SIN_x input • SOUT_x output • PCS0/SS_x input Note: Faster baud rates would require increasing the pad’s slew rate control in SIU_PCR[SRC]. Steps and Pseudo Code Table (shown using DSPI_C as Master. rest inactive • Transfer Data = 0x5678 TxDATA=0x1234 HALT = 0 DSPID_MCR = 0x0001 0001 DSPID_CTAR0 = 0x780A 7727 DSPID_MCR = 0x8001 0000 SIU_PCR[42] = 0x0B00 SIU_PCR[44] = 0x0B00 SIU_PCR[43] = 0x0D00 SIU_PCR[45] = 0x1100 SIU_PCR[98] = 0x0900 SIU_PCR[99] = 0x0900 SIU_PCR[100] = 0x0A00 SIU_PCR[106] = 0x0900 See table: MPC56xxB/P/S Signals for SIU_PCR & SIU_PSMI Registers and Values DSPID_PUSHR = 0x0000_1234 DSPI1_PUSHR = 0x0000_1234 CONT=0 CTAS=0 EOQ=1 CTCNT=0 PCS0=1. Rev. DSPI_D. other PCSx=0 TxDATA=0x5678 DSPIC_PUSHR = 0x0801_5678 DSPI0_PUSHR = 0x0801_5678 Qorivva Simple Cookbook. • Do not Clear SPI Transfer Count • PCS0=active. 4 Freescale Semiconductor 193 . Initialize response data from slave DSPI: Init • Data = 0x1234 DSPI_D or DSPI_1 Response Transmit DSPI_C or DSPI 0 data Transmit a single SPI command from DSPI: • Continuous PCS disabled • Clock and Transfer Register 0 used • End of Queue is set (only one command sent).Table 95. DSPI_D as Slave) (continued) Step Relevant Bit Fields Pseudo Code MPC551x MPC555x MPC56xxB/P/S DSPI1_MCR = 0x0001 0001 DSPI1_CTAR0 = 0x780A 7727 DSPI1_MCR = 0x8001 0000 init Enable as slave (other fields same as master MSTR=0 DSPI_D DSPI) or DSPI_1 Configure CTAR0 same as for master DSPI (Slave) Change DSPI from STOPPED to RUNNING Configure pads for Slave (DSPI_B.

Table 95. DSPI_D as Slave) (continued) Step Read data Wait for data to be received on slave SPI DSPI_D or DSPI_1 Read data on slave from master Clear flags by writing a “1” • Clear Receive FIFO Drain flag • Clear Transmit Complete flag Read data Wait for data to be received on master SPI DSPI_C or DSPI_0 Read data on master from slave Clear flags by writing a “1” • Clear Receive FIFO Drain flag • Clear Transmit Complete flag • Clear End Of Queue flag Relevant Bit Fields wait for RFDF=1 Pseudo Code MPC551x MPC555x MPC56xxB/P/S wait for DSPI1_SR[RDRF] =1 RecDataSlave = DSPI1_POPR DSPI1_SR = 0x8002 0000 wait for DSPI0_SR[RDRF] =1 RecDataMaster = DSSPI0_POPR DSPI0_SR = 0x9002 0000 wait for DSPID_SR[RDRF]=1 RecDataSlave = DSPID_POPR DSPID_SR = 0x8002 0000 wait for DSPIC_SR[RDRF]=1 RFDF = 1 TCF = 1 wait for RDRF = 1 RecDataMaster = DSSPIC_POPR RFDF = 1 TCF = 1 EOQ=1 DSPIC_SR = 0x9002 0000 24. Steps and Pseudo Code Table (shown using DSPI_C as Master. Rev.6 Design Screenshot The signals for this example are shown in the screenshot below for master DSPI_C and slave DSPI_D. The data is MSB first. Figure 38.2. DSPI Example Signals (Captured on MPC555x EVB) Qorivva Simple Cookbook. 4 194 Freescale Semiconductor . and the frame size is 16 bits wide.

1 July 20 2007 SM .R = 0x00000003.ESYNCR2.MCR.R = 0xF0020030.R = 0x0A00.initSysclk changed for MPC5633M support */ /* Rev 2.PCR[63].XOSCEN = 1.R.ESYNCR2. /* MPC551x: Config pad as DSPI_B SOUT output*/ SIU. /* Dummy idle counter */ uint16_t RecDataMaster = 0.SR.Switched slave DSPI to DSPI_B.POPR.3.R = 0x00001234. /* Configure DSPI_B as slave */ DSPI_B. /* Initialize DSPI_C as master SPI and init CTAR0 */ initDSPI_B(). /* MPC551x: Config pad as DSPI_B PCS0/SS input */ } void ReadDataDSPI_B(void) { while (DSPI_B. /* Clear TCF.Mihalik */ /* Rev 2.HALT = 0x0. /* MPC551x: Config pad as DSPI_C SOUT output */ SIU.SR.R = 0x780A7727.2 Aug 13 2007 SM . EPREDIV=0.B. /* Initialize DSPI_B as Slave SPI and init CTAR0 */ DSPI_B.POPR.SR.0 Jan 3 2007 S.B. EPREDIV=2.Changed PLL initial ERFD value. /* 8MHz xtal: ERFD to initial value of 7 */ FMPLL.B. /* Select PLL for sysclk */ } void initDSPI_C(void) { DSPI_C.R = 0x0600.SR. /* Data received on slave SPI */ void initSysclk(void) { /* Initialize PLL and sysclk to 64 MHz */ /* Use appropriate code for crystal*/ FMPLL.ESYNCR1.PCR[23].ESYNCR1. /* MPC551x: Config pad as DSPI_B SCK input */ SIU.PUSHR. Inc. /* Enable external oscillator */ while (FMPLL.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */ RecDataMaster = DSPI_C.CTAR[0]. changed sysclk (50 MHz) */ /* Rev 2.c: performs a single transfer from DSPI_C to DSPI_B on MPC551x */ /* Rev 1.PCR[24].PCR[21].SYSCLK. /* Configure CTAR0 */ DSPI_C.PCR[62]. /* Data recieved on master SPI */ uint16_t RecDataSlave = 0. /* Read data on master DSPI */ while (1) {i++. /* MPC551x: Config pad as DSPI_C SCK output */ SIU.R = 0x0A00.1 Code MPC551x (DSPI_C master.R = 0x00000005. Rev.Modified for sysclk of 64 MHz & lenghened CSSCK.0 Sept 14 2004 S. Mihalik . /* Transmit data from master to slave SPI with EOQ */ ReadDataDSPI_B().24.R = 0x80020000.B. */ /* 12MHz xtal: ERFD to initial value of 5 */ /*FMPLL. DSPI_B slave) /* main.5 Aug 18 2008 D McKenna-Kept DSPI_MCR[HALT] set during DSPI initialization*/ /* Rev 2.B. EOQ flags by writing 1 */ } int main(void) { initSysclk().SYNSR.R = 0x0500.R = 0x0900.R = 0x0A00. /* MPC551x: Config pad as DSPI_C PCS0 output */ } void initDSPI_B(void) { DSPI_B. RDRF flags by writing 1 to them */ } void ReadDataDSPI_C(void) { while (DSPI_C.h or mpc5554. /* 8MHz xtal: ERFD change for 64 MHz sysclk */ /*FMPLL. /* Configure CTAR0 */ DSPI_B. /* Read data received by master SPI */ DSPI_C.B. /* Set sysclk = 64MHz running from PLL */ initDSPI_C(). */ /* 12MHz xtal: CLKCFG=PLL. /* Clear TCF. } /* Wait forever */ } Qorivva Simple Cookbook.Modified for MPC551x.6 Aug 12 2009 SM .PCR[60]. /* Initialize slave DSPI_B's response to master */ DSPI_C. /* Read data received by slave SPI */ DSPI_B. /* MPC551x: Config pad as DSPI_B SIN input */ SIU.PUSHR. /* Exit HALT mode: go from STOPPED to RUNNING state*/ SIU.h */ vuint32_t i = 0.R = 0xF0000020.3 Jun 04 2008 SM .MCR.R = 0x0500. */ /* 12MHz xtal: ERFD change for 64 MHz sysclk */ SIU.SYSCLKSEL = 2.h" /* Use proper include file like mpc5510.3 24.R = 0x00000005.R = 0x00000007. removed 555x lines */ /* Rev 2.ESYNCR2.4 Aug 14 2008 SM . /* 8MHz xtal: CLKCFG=PLL. /* MPC551x: Config pad as DSPI_C SIN input */ SIU.B.R = 0x90020000.LOCK != 1) {}. RDRF.R = 0x00010001.R = 0x80010001. /* Configure DSPI_C as master */ DSPI_C.PCR[22]. /* Exit HALT mode: go from STOPPED to RUNNING state*/ SIU. 4 Freescale Semiconductor 195 .R.R = 0x0500.HALT = 0x0. /* Read data on slave DSPI */ ReadDataDSPI_C(). EMFD=0x30*/ CRP. ASC*/ /* Rev 2.Modified to use two SPIs */ /* Rev 2.MCR.PCR[61].CLKSRC.R = 0x780A7727. */ #include "mpc5510.MCR.CTAR[0].ESYNCR2. 2007 All rights reserved.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */ RecDataSlave = DSPI_B. added 12MHz crystal */ /* Copyright Freescale Semiconductor. EMFD=0x20 */ /*FMPLL. /* Wait for PLL to LOCK */ FMPLL.R = 0x08015678.

c: performs a single transfer from DSPI_C to DSPI_D on MPC555x*/ Rev 1. MPC563x */ Rev 2.PCR[99].0 Jan 3 2007 S.h" /* Use proper include file like mpc5510. DSPI_C. SIU.PCR[109].LOCK != 1) {}.SYNCR. ASC*/ Rev 2.R = 0x0900.2 Aug 13 2007 SM . DSPI_D. } int main(void) { SIU. /* Configure CTAR0 */ DSPI_D. SIU.HALT = 0x0. Rev.R = 0x08015678.R = 0x16000000.POPR. ReadDataDSPI_C(). initDSPI_C().R = 0x00001234.R = 0x0900.R = 0x0A00.MCR. /* Configure DSPI_D as slave */ DSPI_D.R = 0x0000C0FC.R = 0x0A00.PCR[108].R.1 July 20 2007 SM .DISR. SRAM not initialized.R = 0x0900.PCR[107].POPR.B.R = 0x80010001.4 Aug 15 2008 SM .3 Jun 04 2008 SM . /* Wait for FMPLL to LOCK */ FMPLL. Inc.PUSHR.Modified to use two SPIs */ Rev 2. changed sysclk (50 MHz) */ Rev 2. } /* Configure DSPI_C as master */ /* Configure CTAR0 */ Exit HALT mode: go from STOPPED to RUNNING state*/ /* MPC555x: Config pad as DSPI_C SOUT output */ /* MPC555x: Config pad as DSPI_C SIN input */ /* MPC555x: Config pad as DSPI_C SCK output */ /* MPC555x: Config pad as DSPI_C PCS0 output */ void initDSPI_D(void) { DSPI_D.B.SYNCR.MCR.R = 0x780A7727. */ Notes: */ 1.R = 0x780A7727.h or mpc5554.Modified for MPC551x. while (1) {i++.SYNSR.Mihalik */ Rev 2.removed lines for MPC551x. } } /* /* /* /* /* /* /* /* /* to RUNNING state*/ SCK input */ SIN input */ SOUT output*/ PCS0/SS input */ /* Wait for Receive FIFO Drain Flag = 1 */ /* Read data received by slave SPI */ /* Clear TCF.RFDF != 1){} RecDataMaster = DSPI_C. 2007 All rights reserved.R.R = 0x0A00.24. 40MHz: 0x46080000 */ } void initDSPI_C(void) { DSPI_C.h */ void initSysclk (void) { FMPLL. must be done by debug scripts or in a crt0 type file */ vuint32_t i = 0. 40MHz: 0x46100000 */ while (FMPLL. RDRF.PCR[110]. initDSPI_D(). DSPI_C. 4 196 Freescale Semiconductor .R = 0x0A00.R = 0x16080000.R = 0x90020000.R = 0x0900. } void ReadDataDSPI_C(void) { while (DSPI_C. SIU.PCR[100].SR.B.Modified for sysclk of 64 MHz & lenghened CSSCK.R = 0x80020000.SR. /* 8 MHz xtal: 0x16000000.5 Aug 18 2008 D McKenna.PCR[98].MCR.R = 0x00010001. /* Dummy idle counter */ /* Data recieved on master SPI */ /* Data received on slave SPI */ #include "mpc5554. uint16_t RecDataMaster = 0.CTAR[0].B.PCR[106]. initSysclk().SR.SR.HALT = 0x0. /* SIU.B. Mihalik . /* MPC555x: Config pad as DSPI_D } void ReadDataDSPI_D(void) { while (DSPI_D. /* Exit HALT mode: go from STOPPED SIU. DSPI_C. /* 8 MHz xtal: 0x16080000.3. ReadDataDSPI_D().Kept DSPI_MCR[HALT] set during initialization*/ Copyright Freescale Semiconductor.CTAR[0]. DSPI_D slave) main.initSysclk changed for MPC5633M support */ Rev 2. DSPI_C. uint16_t RecDataSlave = 0. RDRF flags by writing 1 to them */ /* Wait for Receive FIFO Drain Flag = 1 */ /* Read data received by master SPI */ /* Clear TCF. MMU not initialized.2 /* /* /* /* /* /* /* /* /* /* /* /* MPC555x (DSPI_C master.PUSHR. DSPI_D internally */ Set sysclk = 64MHz running from PLL */ Initialize DSPI_C as master SPI and init CTAR0 */ Initialize DSPI_D as Slave SPI and init CTAR0 */ Initialize slave DSPI_D's response to master */ Transmit data from master to slave SPI with EOQ */ Read data on slave DSPI */ Read data on master DSPI */ Wait forever */ Qorivva Simple Cookbook.0 Sept 14 2004 S. /* MPC555x: Config pad as DSPI_D SIU. /* MPC555x: Config pad as DSPI_D SIU. DSPI_D.MCR. must be done by debug scripts or BAM */ 2. EOQ flags by writing 1 */ MPC555x only: Connect DSPI_C. /* MPC555x: Config pad as DSPI_D SIU.RFDF != 1){} RecDataSlave = DSPI_D.

PCR[110]. /* MPC555x: Config pad as DSPI_C SIU. /* ReadDataDSPI_B().2 Aug 18 2008 D McKenna. /* Configure DSPI_B as slave */ DSPI_B.DISR.R = 0x00010001. /* Exit HALT mode: go from STOPPED SIU.CTAR[0].R = 0x80020000. /* 8 MHz xtal: 0x16080000. must be done by debug scripts or BAM */ /* 2. /* MPC555x: Config pad as DSPI_C SIU. /* DSPI_B. 2007 All rights reserved. DSPI_B slave) /* main.R = 0x0A00. /* 8 MHz xtal: 0x16000000.h" /* Use proper include file such as mpc5510. /* Wait for FMPLL to LOCK */ FMPLL.Ported from AN2865 example Rev 2.R = 0x780A7727.ESYNCR1. 40MHz: 0x46080000 */ } void initDSPI_C(void) { DSPI_C.POPR.R = 0x80010001.MCR.B. /* MPC555x: Config pad as DSPI_B } to RUNNING state*/ SOUT output */ SIN input */ SCK output */ PCS0 output */ to RUNNING state*/ SCK input */ SIN input */ SOUT output*/ PCS0/SS input */ void ReadDataDSPI_B(void) { while (DSPI_B. /* initSysclk(). /* initDSPI_B().R = 0x00001234.PCR[108]. */ /* SIU. /* MPC555x: Config pad as DSPI_C } void initDSPI_B(void) { DSPI_B.B.RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */ RecDataSlave = DSPI_B.3. DSPI_D*/ MPC563x only: Connect DSPI_C.R = 0x0500. /* while (1) {i++. /* Read data received by slave SPI */ DSPI_B.Modified SIU. SRAM not initialized.SYNCR.PCR[103].R = 0x16080000. /* Clear TCF. 4 Freescale Semiconductor 197 . EOQ flags by writing 1 */ } int main(void) { /* Optional: Use one of the next /* SIU.R = 0x08015678.1 Aug 15 2008 SM .R = 0x0500. */ /* Notes: */ /* 1.SR.R = 0x90020000. /* Configure CTAR0 */ DSPI_B.R = 0x0000C0FC.R = 0x780A7727.24.R = 0x0600. /* Configure CTAR0 */ DSPI_C.PCR[102].MCR. /* Configure DSPI_C as master */ DSPI_C.PCR[107]. Inc.SR.R = 0x0A00.DISR line for internal DSPI connections */ /* Rev 1.DISR. RDRF flags by writing 1 to them */ } void ReadDataDSPI_C(void) { while (DSPI_C.HALT = 0x0. RDRF. } /* } two lines for internal DSPI connections: */ MPC55xx except MPC563x: Connect DSPI_C. /* ReadDataDSPI_C().B.R = 0x0500.CLKCFG = 0X7.PCR[109]. /* Exit HALT mode: go from STOPPED SIU.POPR.B. vuint32_t RecDataMaster = 0.PCR[105].B. /* Clear TCF. vuint32_t RecDataSlave = 0. /* Read data received by master SPI */ DSPI_C.HALT = 0x0. DSPI B */ /* and used POPR[RXDATA] for RecDataMaster.PUSHR.SR.B.RXDATA.CTAR[0].3 MPC563x (DSPI_C master. /* MPC555x: Config pad as DSPI_B SIU.0 Jun 2 2008 SM .RFDF != 1){} /* Wait for Receive FIFO Drain Flag = 1 */ RecDataMaster = DSPI_C.R = 0x00A8A000.SYNCR.R = 0x0A00.R = 0x0900. /* initDSPI_C(). must be done by debug scripts or in a crt0 type file */ #include "mpc563m.Kept DSPI_MCR[HALT] set during initialization*/ /* Copyright Freescale Semiconductor.SYNSR. DSPI_B */ Set sysclk = 64MHz running from PLL */ Initialize DSPI_C as master SPI and init CTAR0 */ Initialize DSPI_B as Slave SPI and init CTAR0 */ Initialize slave DSPI_B's response to master */ Transmit data from master to slave SPI with EOQ */ Read data on slave DSPI */ Read data on master DSPI */ Wait forever */ Qorivva Simple Cookbook.MCR.B.R = 0x16000000.c: performs a single transfer from DSPI_C to DSPI_B */ /* Rev 1. /* MPC563x: Change clk to PLL normal from crystal*/ FMPLL.LOCK != 1) {}. /* MPC555x: Config pad as DSPI_B SIU. MMU not initialized. 40MHz: 0x46100000 */ while (FMPLL. /* MPC555x: Config pad as DSPI_B SIU. /* MPC555x: Config pad as DSPI_C SIU.B. /* DSPI_C. Rev.PCR[104].RXDATA.h or mpc5554.MCR.h */ vuint32_t i = 0. RecDataSlave */ /* Rev 1.SR.PUSHR. /* Dummy idle counter */ /* Data recieved on master SPI */ /* Data received on slave SPI */ void initSysclk (void) { /* MPC563x: Use the next line */ FMPLL.2 for DSPI C.

4 May 22 2009 SM . /* MPC56xxP: Config SIU.RUNPC[1] */ /*ME. /* MPC56xxP: Config SIU. 4 198 Freescale Semiconductor . DSPI_1 slave.Simplified code */ Rev 2.0 Jan 3 2007 S. /* MPC56xxP: Config SIU.R = 0x8000010A. /* Configure DSPI_0 DSPI_0.R = 0x02400100.Simplified code */ Rev 2. /* Clear watchdog enable (WEN) */ } void initDSPI_0(void) { DSPI_0. Mihalik . RESET modes */ /* Initialize XOSC.HALT = 0x0.R = 0x000000000.GS.PCR[7].*/ /* Monitor FXOSC > FIRC/4 (4MHz).FMPLL[0].PCTL[5]. changed sysclk (50 MHz) */ Rev 2. /* MPC56xxP: Config } as master */ */ from STOPPED to RUNNING state*/ pad as DSPI_0 SOUT output */ pad as DSPI_0 SIN input */ pad as DSPI_0 SCK output */ pad as DSPI_0 PCS0 output */ as slave */ */ from STOPPED to RUNNING state*/ pad as DSPI_1 SCK input */ pad as DSPI_1 SIN input */ pad as DSPI_1 SOUT output*/ pad as DSPI_1 PCS0/SS input */ Qorivva Simple Cookbook. /* MPC56xxB/P/S DSPI0: select ME.0 Sept 14 2004 S.Modified for sysclk of 64 MHz & lenghened CSSCK. /* Enter RUN0 Mode & Key */ ME.CR.R = 0x000000004.R = 0x780A7727. /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME.PLL0ON.R = 0x00000010. Rev. /* Monitor FXOSC > FIRC/1 (16MHz).MCTL.R = 0x0103.6 Mar 14 2010 SM . /* MPC56xxP: Config SIU.24. Inc.OSC0ON. /* MPC56xxP: Config SIU.PCTL[4]. /* MPC56xxP: Config SIU. PLL before turning them on: */ /* Use 2 of the next 4 lines depending on crystal frequency: */ /*CGM.CR.syclk=PLL */ ME.R = 0x4000A50F.B. 2007–2010.Mihalik */ Rev 2. 1 settings: only run in RUN0 mode */ ME. /* Enter RUN0 Mode & Inverted Key */ while (ME.MCTL. uint16_t RecDataMaster = 0.CMU_0_CSR.3.PCR[36].PCTL[68]. no PLL monitor*/ CGM. SWT. */ /* Use proper include file */ /* Dummy idle counter */ /* Data recieved on master SPI */ /* Data received on slave SPI */ #include "Pictus_Header_v1_09.R = 0x0000001D.Modified for MPC551x.*/ /* 8 MHz xtal: Set PLL0 to 64 MHz */ CGM.R = 0x01.h" vuint32_t i = 0. /* Enable DRUN. void initModesAndClks(void) { ME.Modified for MPC56xxB/P/S */ Rev 2.MCR.HALT = 0x0.SC_DC[1].R = 0x0604.PCR[37].S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void initPeriClkGen(void) { /* Use the following code as required for MPC56xxB or MPC56xxS:*/ /*CGM.R = 0x0604. Cfg. /* RUN0 cfg: 16MHzIRCON. /* Configure CTAR0 DSPI_0.R = 0x0604. SAFE. MPC56xxP shown) main.R = 0x12400100. RUN0.4 /* /* /* /* /* /* /* /* /* /* MPC56xxB/P/S (DSPI_0 master.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME. uint16_t RecDataSlave = 0. no PLL monitor*/ /*CGM.SR.1 July 20 2007 SM .PCR[38].PCR[8].RUN[0]. */ /* MPC56xxB/S SIUL: select ME. /* MPC56xxB/P/S DSPI1: select ME.Modified to use two SPIs */ Rev 2.R = 0x80010001.R = 0x780A7727.R = 0x0503.PCR[5]. /* Configure DSPI_1 DSPI_1.CMU_0_CSR. */ /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1*/ } void disableWatchdog(void) { SWT. /* Peri.MER.CTAR[0].RUNPC[1].R = 0x80.MCR. /* Configure CTAR0 DSPI_1.GS.R = 0x0000c520.R = 0x40005AF0.RUNPC[1] */ ME.MCR.5 Jun 25 2009 SM .B.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME.3 Mar 03 2009 SM .PCR[39].R = 0x01. /* Write keys to clear soft lock bit */ SWT.R = 0x0000d928.R = 0x0604. /* MPC56xxP: Config } void initDSPI_1(void) { DSPI_1.PCR[6].B. /* Exit HALT mode: go SIU. All rights reserved.R = 0x01.CTAR[0].B.R = 0x001F0074. ASC*/ Rev 2.2 Aug 13 2007 SM .c: performs a single transfer from DSPI_0 to DSPI_1 */ Rev 1.FMPLL[0].R = 0x0103. /* Exit HALT mode: go SIU.R = 0x00010001.modified initModesAndClock.CR. updated header file */ Copyright Freescale Semiconductor.R = 0x0503.MCR.SR.

while (1) {i++.POPR. Rev.R = 0x90020000. 4 Freescale Semiconductor 199 . } int main(void) { initModesAndClks().R = 0x08015678. ReadDataDSPI_0().RFDF != 1){} RecDataSlave = DSPI_1.R = 0x80020000. EOQ flags by writing 1 */ Initialize mode entries and system clock */ Initialize peripheral clock generation for DSPIs*/ Disable watchdog */ Initialize DSPI_0 as master SPI and init CTAR0 */ Initialize DSPI_1 as Slave SPI and init CTAR0 */ Initialize slave DSPI_1's response to master */ Transmit data from master to slave SPI with EOQ */ Read data on slave DSPI */ Read data on master DSPI */ Wait forever */ Qorivva Simple Cookbook.B. } void ReadDataDSPI_0(void) { while (DSPI_0.PUSHR. DSPI_0.void ReadDataDSPI_1(void) { while (DSPI_1.RFDF != 1){} RecDataMaster = DSPI_0.R. initDSPI_0(). RDRF flags by writing 1 to them */ /* Wait for Receive FIFO Drain Flag = 1 */ /* Read data received by master SPI */ /* Clear TCF.SR.POPR.SR. RDRF. ReadDataDSPI_1().B. } } /* /* /* /* /* /* /* /* /* /* /* Wait for Receive FIFO Drain Flag = 1 */ /* Read data received by slave SPI */ /* Clear TCF.SR.R. initPeriClkGen().PUSHR. initDSPI_1().SR.R = 0x00001234. disableWatchdog(). DSPI_0. DSPI_1. DSPI_1.

1 FlexCAN Transmit and Receive Description Task: Initialize two FlexCAN modules for 100 kHz bit time based on an 8 MHz crystal. Msg Buffer 63 Time Quanta Freq. (SCK) CAN0TX CANL CNRxA or XCVR osc. which could limit the CAN frequency. not the PLL. Exercise: On a Evaluation Board (EVB). The transmit outputs must be configured as open drain and use a pullup resistor. 4 200 Freescale Semiconductor . we want the second CAN module to respond to the first. Be sure to use appropriate CAN_SEL jumpers on the EVB. EVBs typically have the pullup resistor. externally connect FlexCAN modules. then modify to send a second message. This allows more buffers to be available for a node. Note this extra resistance on the transmit line may slow rise and fall times.7K CNTxA or FlexCAN_A or FlexCAN_0 CANH Msg Buffer 0 Msg Buffer 1 . It is common for two CAN modules to be connected to the same transceiver. Rev. MPC5500 EVB MPC5500 / MPC5600 Crystal 8 MHz +5V Clocks and PLL sysclk 4.. The modules will be connected externally in an open drain circuit. MUX CLK_SRC Divide by (PRESDIV+1) CAN0RX FlexCAN_C or FlexCAN 1 Msg Buffer 0 Msg Buffer 1 . Msg Buffer 63 Time Quanta Freq. However. Send a message from FlexCAN A (FlexCAN 0 on MPC56xxB/P/S). Verify proper operation.. (SCK) CNTxC or CAN1TX CNRxC or MUX CLK_SRC Divide by (PRESDIV+1) CAN1RX Qorivva Simple Cookbook.. The connections needed are shown below.25 25. In this case.. only one module is used for transmit and the other FlexCAN module’s transmit is not connected — otherwise the node might acknowledge itself. before the transceiver. The CAN reference will be based on the crystal. because there are not any other nodes connected in this example.

144 QFP 104 100 103 99 176 QFP 128 124 127 123 208 BGA D15 E D16 F13 Function Name SIU PCR No. 48 52 49 53 Package Pin No. MPC56xxB/P/S Signals for FlexCAN Transmit and Receive Example (MPC56xxP: Safety Port is used for CAN1) Signal Port MPC56xxB Family MPC56xxP Family MPC56xxS Family SIU Pad Package Pin # Port SIU Pad Package Port SIU Pad Package Pin # Pin # Configuration & Configuration Configuration Selection & Selection & Selection 100 144 176 100 144 144 176 208 Registers Registers Registers QFP QFP BGA QFP QFP QFP QFP BGA (values in hex) (values in hex) (values in hex) 23 22 24 77 31 28 32 N3 B0 PCR16=0624 76 99 77 109 143 110 B0 J7 B1 J6 PCR16=0624 PCR112=0A24 PCR17=0500 PSMI0=00 PCR111=0900 PSMI1=02 106 130 T15 60 A6 CAN0TX B0 PCR16=0624 CAN1TX C10 PCR42=0624 CAN0RX CAN1RX B1 PCR17=0100 C3 PCR35=0100 PSMI0=00 M3 A14 PCR14=0624 N1 B1 PCR17=0500 105 129 T14 59 B5 116 B11 A15 PCR15=0900 100 144 Qorivva Simple Cookbook. MPC551x. 83 87 84 88 MPC555x Family Package Pin No. MPC55xx Signals for FlexCAN Transmit and Receive Example MPC551x Family Pin Name SIU PCR No.Table 96. Rev. 496 BGA AF22 W24 AG22 Y26 416 BGA AD21 V23 AE22 W24 324 BGA Y17 P19 AA18 R20 208 BGA P12 K13 R12 L14 EVB xPC 563M PJ1–5 PJ1–6 PJ1–3 PJ1–4 Signal CNTxA CNTxC CNRxA CNRxC MPC56 PD0 PD4 PD1 PD5 CNTXA CNTXC CNRXA CNRXC Table 97. 4 Freescale Semiconductor 201 .

MPC56XX EVB main board: I/O power (J4) should be jumpered to 5 V as shown so transceiver pullup gets 5 V. at least one FlexCAN needs to be connected to the transceiver. which routes it to the transmitting FlexCAN’s Rx pin. connecting pins 1–3 and 2–4. J27. 2. Disconnect this jumper to allow Port B0 to drive it’s output properly. This allows (1) the CAN bus to sync by allowing the Rx to see an idle bus and (2) the receiving FlexCAN to transmit an acknowledge from its Tx pin. 3. MPC56XX EVB main board: needs CAN_SEL jumpers. CANH_SEL (J27) jumpers are connected as shown and CANL_SEL (J29) jumpers are not connected. 4 202 Freescale Semiconductor . Rev. through the transceiver.Connection Notes: 1. In addition to connecting both Rx pins together and both Tx pins together. Qorivva Simple Cookbook. MPC56XX main board with XPC560S: Trimmer jumper (J40) on main board connects Port B0 to an potentiometer hooked to 5V.

4. 4 Freescale Semiconductor 203 . MPC5534EVB’s CAN_EN jumpers are shown below. 5. MPC5510DEMO EVB needs CAN_EN jumpers (J9) connected by the CAN transceiver. 6. Rev. Transceiver’s need 5V on most EVBs. Connect pins 1-2 and 3-4 to connect Tx and Rx to the transceiver as shown below. MPC553x and MPC555x EVBs Tx and Rx pins need be connected to the CAN transceiver with jumpers. MPC56xxS EVB’s expansion card: make sure VDDE_B (J23)and VDDE_E (J25) are jumpered to 5V for the FlexCAN port pins used in this example. Qorivva Simple Cookbook.

Observing a Repeating CAN Frame When debugging CAN. 4 204 Freescale Semiconductor . This direct connection allows the Rx pin to listen to the Tx without a transceiver. This example code uses an open drain on transmit pins. a debugger window that constantly reads the TIMER or another message buffer may cause premature unlocking of a message buffer in your program. Qorivva Simple Cookbook. since there is no acknowledge from any receiving CAN module. These jumpers connect FlexCAN A Tx and Rx to transceiver. In addition. Rev. a simple test is only to connect Tx and Rx of one CAN together. making it easy to examine on an oscilloscope or other tool. 2. so that when a CAN frame starts to transmit then an error frame will not be generated. MPC5554EVB has jumpers located further to left. 2 installed on MPC5534EVB (default setting). hence that buffer is locked and cannot receive a message. or else disable the open drain in the transmitting CAN’s Pad Configuration Register (SIU_PCR). Conversely. the transmitting CAN module will keep repeating the transmitting of the frame. so if you are doing this test be sure either that an external pullup is connected on the board. Debug Tips: 1. Inadvertent Locking/Unlocking of Message Buffers Sometimes a message will not be received because a debugger window is reading the buffer’s Control and Status (CS).CAN_SEL jumpers 1. and not to the transceiver.

which is 12 time quanta units into the 16 time quanta period Hence.6M time quanta) = 10 s Qorivva Simple Cookbook.25. the bit rate will increase five times. For this example and within the above guidelines.6 MHz Prescaler Value (PRESDIV + 1) = fCANCLK / ftq = 8 MHz / 1.1 Design Timing Calculations These common guidelines are used in this example: • CAN bit rate period is typically subdivided into 12–20 time quanta units.6 MHz = 5 PRESDIV = 5 – 1 = 4 Table 98. • The Sync_Seg is 1 time quanta.2 25. PROPSEG = 6 Resync Jump Width (RJW + 1) = 4 Also for this example. Rev. PSEG1 = 3 Prop_Seg = 16 – Phase_Seg1 – Phase_Seg2 – SYNCSEG = 16 – 4 – 4 – 1 = 7. the following applies for an 8 MHz crystal.2. PSEG2 = 3 Phase_Seg1 = Phase_Seg2 = 4 time quanta. otherwise (RJW +1) = 4. • The value of Phase_Seg1 will be the same as Phase_Seg2. • The sample point is normally chosen around 75%–80% through the bit rate period. • Resync Jump Width (RJW+1) = Phase_Seg2 (if Phase_Seg2 < 4. (Note: If a 40 MHz crystal is used. these are the values selected for CAN modules: number of time quanta units per bit rate period = 16 Sample point = 75%. Phase_Seg2 = (100% – 75%)  16 time quanta = 25%  16 time quanta = 4 time quanta.) fCANCLK = 8 MHz (EVB oscillator) Desired bit rate = 100 kHz Hence. 4 Freescale Semiconductor 205 . Segments Within the Bit Time SYNCSEG Number of Time Quanta Register Bit Fields 1 – PROP_SEG 7 PROPSEG + 1 PHASE_SEG1 4 PSEG1 + 1 PHASE_SEG2 4 PSEG 2 + 1 1 bit time = (16 time quanta)  (1 sec / 1. • The remaining 20–25% will be the value for Phase_Seg2. ftq (time quanta frequency) = (16 time quanta/bit rate period)  (100 K bit rate periods/sec) = 1.

struct { vuint32_t:3. vuint16_t H[4]. struct { vuint32_t:4. Hence all buffers must all have their CODE field set inactive before negating the halt state. vuint32_t STD_ID:11. vuint32_t RTR:1. vuint32_t EXT_ID:18. struct canbuf_t { union { vuint32_t R. union { vuint8_t B[8]. vuint32_t SRR:1. vuint32_t W[2]. Remember that buffers are in FlexCAN RAM. which is from Freescale’s MPC5554 header files version 1. union { vuint32_t R. Qorivva Simple Cookbook. } BUF[64]. vuint32_t IDE:1. } DATA. } ID. } B.2. vuint32_t TIMESTAMP:16. vuint32_t CODE:4. } B. } CS.2 Message Buffers The message buffer structure is shown below. so they are random in value on power-up.25.2. /* /* /* /* Data Data Data Data buffer buffer buffer buffer in in in in Bytes (8 bits) */ Half-words (16 bits) */ words (32 bits) */ words (32 bits) */ . Rev. vuint32_t:1. 4 206 Freescale Semiconductor . vuint32_t LENGTH:4. vuint32_t R[2].

Table 100. The following table summarizes the peripheral configurations used in this example. Enabled Modes pheral Config. Config. Hence even enabling the crystal oscillator to be active in the default mode (DRUN) requires enabling the crystal oscillator in appropriate mode configuration register (ME_xxxx_MC) then initiating a mode transition. PeriPeri. Register Value sysclk Selection Memory Power Mode Code Flash Main Voltage Reg. enabling low power.25. Mode Configurations for MPC56xxB/P/S FlexCAN Transmit and Receive Example Modes are enabled in ME_ME Register. Table 99.3 Mode Use Summary (MPC56xxB/P/S only) Mode Transition is required for changing mode entry registers. This example transitions from the default mode after reset (DRUN) to RUN0 mode. Peripheral Configurations for MPC56xxB/P/ S FlexCAN Transmit and Receive Example Low power modes are not used in example. Rev. PLL1 16MHz XOSC0 PLL0 (MPC Data IRC 56xxP/S Flash only) On On Off On Off On Off Off I/O Power Down Ctrl DRUN ME_DRUN_MC 0x001F 0010 16 MHz IRC (default) RUN0 ME_RUN0_MC 0x001F 007D PLL0 Normal Normal Normal Normal On On Off Off Other modes are not used in example Peripherals also have configurations to gate clocks on or off for different modes.2. Register Mode Config. Settings Clock Sources Mode Mode Config. Register RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET PC1 ME_ RUNPC_ 1 0 0 0 1 0 0 0 0 Peripherals Selecting Configuration Peripheral FlexCAN0 (MPC56xxB/P/S) FlexCAN1 (MPC56xxB/S) SafetyPort (MPC56xxP use as FlexCAN) SIUL (MPC56xxB/S) PCTL Reg. # 16 17 26 68 Other peripheral configurations are not used in example Qorivva Simple Cookbook. 4 Freescale Semiconductor 207 .

4 Steps and Pseudo Code Table 101.MC_PCTL16 = ME_PCTL17 = ME_PCTL96 = ME_PCTL68 = 0x01 Assign peripheral configuration to peripherals: • FlexCAN 0: select ME_RUN_PC0 RUN_CFG = 1 • FlexCAN 1: select ME_RUN_PC0 RUN_CFG = 1 (56xxB/S) • Safety Port: select ME_RUN_PC0 (56xxP) RUN_CFG = 1 • SIUL: select ME_RUN_PC0 (56xxB/S) RUN_CFG = 1 Initiate software mode transition to RUN0 mode • Mode & key.sysclk div. 1 • MPC56xxP Safety Port: Aux Clk 2. Config.) Configure RUN0 Mode: • I/O Output power-down: no safe gating • Main Voltage regulator is on (default) • Data. RxLENGTH byte. 4 208 Freescale Semiconductor . =0x4000 A50F wait ME_GS [S_TRANS] = 0 verify 4 = ME_GS [CURRENTMODE] MPC56xxB/S: CGM_SC_DC1= 0x80 MPC56xxP: CGM_AC2_SC= 0x0400 0000 CGM_AC2_DC= 0x8000 0000 — Qorivva Simple Cookbook. See PLL example. Steps and Pseudo Code Table for FlexCAN Transmit and Receive Example Step Relevant Bit Fields Pseudo Code MPC551x MPC555x MPC56xxB/P/S Data Init Global variables for a CAN receive buffer RxCODE byte.1: run in DRUN mode only PDO=0 MVRON=1 DFLAON. RxID word. Rev. — — ME_ME = 0x0000 001D 8 MHz Crystal: CGM_ FMPLL[0]_CR =0x02400100 init Enable desired modes DRUN=1. code flash in normal mode (default) • PLL0 is switched on • Crystal oscillator is switched on • 16 MHz IRC is switched on (default) • Select PLL0 (system pll) as sysclk MPC56xxB/S: • Peri.25. 1 TARGET_MODE = RUN0 S_TRANS - ME_MCTL =0x4000 5AF0. Modes RUN0 = 1 and Clock Initialize PLL0 dividers to provide 64 MHz for input crystal before mode configuration: (MPC • 8 MHz xtal: FMPLL[0]_CR=0x02400100 56xxPBS • 40 MHz xtal: FMPLL[0]_CR=0x12400100 only) (MPC56xxP & 8 MHz xtal requires changing default CMU_CSR value. RxDATA 8 byte string.2. CFLAON= 3 PLL0ON=1 XOSC0ON=1 16MHz_IRCON=1 SYSCLK=0x4 RUN0=1 — ME_ RUN0_MC = 0x001F 0070 — — ME_RUN_PC1 = 0000 0010 . RxTIMESTAMP word. then mode & inverted key • Wait for transition to complete • Verify current mode is RUN0 CURRENTMODE init Peri Clk Gen 56xxB/S Initialize peripheral clock generation (See appendix: MPC56xxB/P/S Peripheral Clocks) • MPC56xxB/S CANs: Peri Set 2.PLL0 div.

buffers CANC_CR = 0x04DB 0006 CANC_ MB0:63[CODE] = 0 CANC_MB4[IDE] = 0 CANC_MB4[ID] = 555 <<18 CANC_MB4[CODE] = 4 CANC_RXGMASK = 0x1FFFFFFF CODE = b0000 IDE = 0 std. OBE= 1. open drain. 15 Initialize interrupt mask bits as needed Configure pad as CNTXC. FRZ= 1 MAXMB = 63 or 31 See other CAN Relevant Bit Fields Pseudo Code MPC551x — MPC555x MPC56xxB/P/S See PLL Initialization example CAN1_MCR = 0x5000 003F MPC56xxP only: 1F CAN1_CR = 0x04DB 0006 CAN1_ MB0:63[CODE] = 0 CAN1_MB4[IDE] = 0 CAN1_MB4[ID] = 555 <<18 CAN1_MB4[CODE]= 4 CAN1_RXGMASK = 0x1FFFFFFF – SIU_PCR[52 SIU_PCR[87] ] = 0x062C = 0x0E2C SIU_PCR[53 SIU_PCR[88] ] = 0x0500 = 0x0D03 CANC_MCR = 0x0000 003F See table: MPC56xxB/P/S Signals CAN1_MCR = 0x0000 003F or 1F CANC_MCR = 0x5000 003F (or Configure bit timing parameters.Table 101. bit rate. Steps and Pseudo Code Table for FlexCAN Transmit and Receive Example (continued) Step Disable Disable watchdog by writing keys to Status Watchdog Reg. FRZ= 0 MAXMB = 63 or 31 Qorivva Simple Cookbook. SRC=3 PA= 3. ODE=1. then clearing WEN (MPC56xxBPS only) init FlexCAN C Put FlexCAN module in freeze mode When in freeze mode. FlexCAN arbitration (same as FlexCAN C or FlexCAN 1 or Safety 1) Port) Inactivate 32 or 64 Message Buffers. 4 Freescale Semiconductor 209 . Initialize Message Buffer 4 for receive: • Extended ID is not used • Desired std. while enabling the maximum number of msg. max slew rate Configure pad as CNRXC Negate HALT state. IBE= 1 HALT=0. Rev. enable all 64 buffers (32 message buffers for MPC56xxP) HALT= 1. ID = 555 CODE = b0100 MI=0x1FFF FFFF (none used here) PA= 3. ID for incoming message is 555 (0x22B) • Set MB as RX EMPTY Initialize global acceptance mask: exact ID matches on all message buffers except 14.

only req’d in exd’d frames] Activate MB to transmit a data frame DATA = ‘Hello’ SRR = 1 CODE = b1100 Qorivva Simple Cookbook. FRZ=1 MAXMB = 63 (31 for MPC56xxP) PROPSEG = 6 PSEG1 = 3 PSEG2 = 3 RJW = 3 Pseudo Code MPC551x MPC555x MPC56xxB/P/S CAN0_MCR = 0x5000 003F MPC56xxP only: 0x5000 001F CAN0_CR = 0x04DB 0006 CANA_MCR = 0x5000 003F (or Configure bit timing parameters FlexCAN0) CANA_CR = 0x04DB 0006 Configure bit rate for 8 MHz OSC. OBE =1. max slew rate Configure pad as CNRXA Negate HALT state. and 16 time quanta PRESDIV = 4 Configure internal arbitration. Rev. 100 kHz bit CLK_SRC = 0 rate. Steps and Pseudo Code Table for FlexCAN Transmit and Receive Example (continued) Step init FlexCAN A Put FlexCAN module in freeze mode When in freeze mode. enable all 64 buffers (32 message buffers for MPC56xxP) Relevant Bit Fields HALT=1. SRC=3 PA = 1. open drain. IBE = 1 HALT=0. 4 210 Freescale Semiconductor . FRZ=0 MAXMB = 63 or 31 IDE = 0 std. others to default LBUF = 0 CANA_ MB0:63[CODE] = 0 CANA_ MB0[CODE] = 8 – – SIU_PCR[48] SIU_PCR[83] = 0x062C = 0x062C SIU_PCR[49] SIU_PCR[84] = 0x0500 = 0x0500 CANA_MCR = 0x0000 003F CANA_MB0[IDE] = 0 CANA_MB0[ID] = 555 <<18 CANA_MB0[RTR] = 0 CANA_MB0[LENGTH] =5 CANA_MB0[DATA] = ‘Hello’ CANA_MB0[SRR] = 1 CANA_MB0[CODE] = 0xC See table: MPC56xxB/P/S Signals CAN0_MCR = 0x0000 003F or 1F CAN0_MB0[IDE]= 0 CAN0_MB0[ID] = 555 <<18 CAN0_MB0[RTR] = 0 CAN0_MB0[LENGTH ]=5 CAN0_MB0[DATA] = ‘Hello’ CAN0_MB0[SRR] = 1 CAN0_MB0[CODE] = 0xC CAN0_ MB0:63[CODE]= 0 CAN0_ MB0[CODE] = 8 Inactivate all 64 message buffers (reduce to CODE = b0000 32 message buffers for MPC56xxP) CODE = b1000 Message Buffer 0: set as TX INACTIVE Initialize acceptance masks as needed Initialize interrupt mask bits as needed Configure pad as CNTXA. ODE=1.Table 101. not remote Tx request RTR = 0 Length of data is five bytes LENGTH = 5 Data is string “Hello” SRR = 1 for transmit. ID = 555 Frame is a data frame. not extended ID Standard ID = 555 (0x22B) (none used here) (none used here) PA = 1. while enabling the maximum number of message buffers Transmit Message (Assume CANA MB 0 is inactive) Use standard ID.

Steps and Pseudo Code Table for FlexCAN Transmit and Receive Example (continued) Step Receive Message Wait for CANC MB 4 flag to set Relevant Bit Fields wait for BUF04I = 1 Pseudo Code MPC551x MPC555x MPC56xxB/P/S wait for CAN1_ IFRL [BUF04I] = 1 RxCODE = CAN1_MB4[CODE] RxID = CAN1_MB4[ID] RxDATA[ ] = CAN1_MB4[DATA] RxTIMESTAMP = CAN1_MB4 [TIMESTAMP] Read CAN1_TIMER CAN1_ IFRL = 0x0000 0010 wait for wait for CANC_ CANC_ IFLAG1 IFRL [BUF04I] = 1 [BUF04I] = 1 RxCODE = CANC_MB4[CODE] RxID = CANC_MB4[ID] RxDATA[ ] = CANC_MB4[DATA] RxTIMESTAMP = CANC_MB4 [TIMESTAMP] Read CANC_TIMER CANC_ CANC_ IFLAG1 = IFRL = 0x0000 0010 0x0000 0010 Read CODE (activates internal buffer lock) Read ID Read DATA Read TIMESTAMP CODE will be b0010 Read TIMER to unlock buffer Clear CANC MB 4 flag by writing a 1 to it CODE = b0100 BUF04I = 1 Qorivva Simple Cookbook. Rev.Table 101. 4 Freescale Semiconductor 211 .

2. • Oscilloscope screenshot of the start of the transmit output line. changing at the 100 kHz bit time rate • CAN tool screenshot of the transmitted message as seen on the CAN bus Qorivva Simple Cookbook.5 Design Results The pictures below show results for this design based on an 8 MHz crystal. Rev.25. 4 212 Freescale Semiconductor .

modified for newer Freescale header files (r 16) */ Rev 0.R = 0x04DB0006. /* Inactivate all message buffers */ } CAN_C.CODE = 8. open drain */ SIU.MCR.ID.PCR[52]. /* Inactivate all message buffers */ } CAN_A. /* Put in Freeze Mode & enable all 64 msg buffers*/ CAN_C.R = 0x0500.3 25. Rev.1 Jan 16.Mihalik.BUF[4]. not bit.MCR.CS.R = 0x0500.STD_ID = 555.*/ /* MPC551x: Configure pad as CNTXC. /* Message Buffer 0 set to TX INACTIVE */ /* Use 1 pair of the next four lines of code for MPC551x or MPC555x */ /*SIU. /* MB 4 will look for ID = 555 */ CAN_C.3 Jun 15 2006 SM . /* MPC555x: Configure pad as CNRXA */ CAN_A.BUF[4]. must be done by debug scripts or BAM */ 2.PCR[49].PCR[83].MCR.B. open drain */ /*SIU. open drain */ /*SIU.PCR[84]. RxLENGTH. uint8_t RxDATA[8].BUF[4].B.h or mpc5554.Removed other redundant CAN_C.BUF[i]. /* MPC555x: Configure pad as CNTXC.25.0 Jul 10 2009 SM .*/ /* MPC551x: Configure pad as CNRXA */ SIU.CODE = 4.BUF[i].R = 0x0000003F.3.CR.c: FlexCAN program */ Description: Transmit one message from FlexCAN A buf. i<64.R = 0x5000003F. i<64.changed Flexcan A to C & enabled 64 msg buffers */ Rev 0.Changes for new MPC5510 header file symbols */ Rev 1.8 May 15 2008 SM .h */ uint32_t RxCODE.B.PCR[87].R = 0x1FFFFFFF. /* MPC555x: Configure pad as CNRXC */ CAN_C. /* Global acceptance mask */ /* Use 1 pair of the next four lines of code for MPC551x or MPC555x */ /*SIU. CAN_C. /* Configure for 8MHz OSC.PCR[53].R = 0x062C. MMU not initialized.h" /* Use proper include file such as mpc5510. All Rights Reserved */ Rev 0.CS.MCR init */ Rev 0.*/ /* MPC551x: Configure pad as CNRXC */ SIU.CS. /* Negate FlexCAN A halt state for 64 MB */ } void initCAN_C (void) { uint8_t i. SRAM not initialized. /* Put in Freeze Mode & enable all 64 msg buffers*/ CAN_A. */ increased Tx pads slew rate. void initCAN_A (void) { uint8_t i.B.R = 0x062C.CODE = 0. Made globals uninitialized */ 2.R = 0x062C. 4 Freescale Semiconductor 213 .Correced init of MBs . 0 to FlexCAN C buf.CS.6 Mar 08 2007 SM . /* MB 4 set to RX EMPTY */ CAN_C.1. instead of 63 */ Rev 0. uint32_t RxTIMESTAMP.RXGMASK.CS.PCR[48]. /* MB 4 will look for a standard ID */ CAN_C.4 Aug 11 2006 SM . dummy data types and */ init receiving CAN first to allow CAN bus sync time before receiving first msg*/ Notes: */ 1.R = 0x0500. MPC555x main. 100kHz bit time */ for (i=0.CODE = 0.PCR[88]. added idle loop code for smoother Nexus trace */ 4.*/ /* MPC551x: Configure pad as CNTXA.Changes for MPC5510 */ Rev 0. removed setting buffer's CODE*/ 3. uint32_t RxLENGTH. 2006 S.IDE = 0.7 Jul 20 2007 SM . /* Negate FlexCAN C halt state for 64 MB */ } Qorivva Simple Cookbook.CR. changed RxCODE.cleared 64 MBs. must be done by debug scripts or in a crt0 type file */ /* /* /* /* /* Received Received Received Received Received message message message message message buffer code */ ID */ number of data bytes */ data string*/ time */ #include "mpc563m. CAN_A.Cleared CAN Msg Buf flag by writing to reg. open drain */ SIU.BUF[0]. receiveMsg function: read CANx_TIMER.2 Jun 6 2006 SM . 100kHz bit time */ for (i=0.MCR. Copyright Freescale.R = 0x0E2C. 4 */ Rev 0. uint32_t RxID. i++) { CAN_A.1 /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* /* Code MPC551x. /* Configure for 8MHz OSC. /* MPC555x: Configure pad as CNTXA.Removed redundant CAN_A.R = 0x0D00.R = 0x0000003F. 2006.R = 0x5000003F.R = 0x04DB0006.B. i++) { CAN_C.MCR init */ Rev 0.5 Jan 31 2007 SM .B.

j++) { RxDATA[j] = CAN_C.CS.CS. /* Use standard ID length */ CAN_A. TransmitMsg().BUF[0]. } /* /* /* /* /* Initialize FLEXCAN C Initialize FlexCAN A Transmit one message Wait for the message Idle loop: increment & one of its buffers for receive*/ & one of its buffers for transmit*/ from a FlexCAN A buffer */ to be received at FlexCAN C */ counter */ } Qorivva Simple Cookbook.LENGTH = sizeof(TxData) -1 .TIMER. 4 214 Freescale Semiconductor .IFFRL. /* Data to be transmitted */ } CAN_A. /* Transmit ID is 555 */ CAN_A. LENGTH. ID. receiveMsg().B.void TransmitMsg (void) { uint8_ti.IDE = 0.LENGTH.B.CODE =0xC.BUF[0]. for (j=0.B.B. /* Activate msg.R = 0x00000010.ID.STD_ID = 555. j<RxLENGTH. /* Read CODE. RxLENGTH = CAN_C. TIMESTAMP*/ RxID = CAN_C.*/ /* MPC551x: Clear CAN C MB 4 flag */ CAN_C.IFLAG1.B.DATA. } /* Assumption: Message buffer CODE is INACTIVE */ const uint8_t TxData[] = {"Hello"}.IFLAG1.CS.BUF04I == 0) {}.BUF[0]. /* # bytes to transmit w/o null */ for (i=0.BUF[4]. i<sizeof(TxData). /* Data frame.CS.B.CODE. to transmit data frame */ void receiveMsg (void) { uint8_t j. uint32_t dummy.DATA. while (1) { IdleCtr++.BUF[4].CS.*//* MPC551x: Wait for CAN C MB 4 flag */ while (CAN_C.B. i++) { CAN_A.R. Rev. /* Tx frame (not req'd for standard frame)*/ CAN_A.B.B.BUF04I == 0) {}. /* Use 1 of the next 2 lines: /*while (CAN_C.IFRL. *//* MPC555x: Wait for CAN C MB 4 flag */ RxCODE = CAN_C.R = 0x00000010.B.CS.CS. /* Read TIMER to unlock message buffers */ /* Use 1 of the next 2 lines: */ /*CAN_C. /* MPC555x: Clear CAN C MB 4 flag */ } void main(void) { volatile uint32_t IdleCtr = 0.BUF[0].BUF[0].RTR = 0. DATA.B[i] = TxData[i]. initCAN_C().BUF[0]. buf.STD_ID. dummy = CAN_C. } RxTIMESTAMP = CAN_C.B.B[j].BUF[0]. /* Transmit string*/ CAN_A. initCAN_A().ID.CS.TIMESTAMP.BUF[4].BUF[4].B.BUF[4]. not remote Tx request frame */ CAN_A.SRR = 1.

FMPLL_CR.BUF[i].Changes for new header file symbols */ /* Rev 0.c: FlexCAN program */ /* Description: Transmit one message from FlexCAN 0 buf.B.Changes for MPC5510 */ /* Rev 0. increased Tx pads slew rate.B.STD_ID = 555.GS.0 Jul 10 2009 SM . Rev.OSC0ON. /* 8 MHz xtal: Set PLL0 to 64 MHz */ /*CGM. while (ME. /* MPC56xxB/S SIUL: select ME.MCR init */ /* Rev 0.R = 0x00000010. uint8_t RxDATA[8].Mihalik.SC_DC[1].R = 0x01.3 Jun 15 2006 SM .BUF[4].Corrected init of MBs. RxLENGTH.R = 0x02400100.2 MPC56xxB/S (MPC56xxB shown) /* main.SR. updated header file */ /* NOTE!! structure canbuf_t in jdp. void initModesAndClks(void) { ME.MER.7 Jul 20 2007 SM .R = 0x01. 2006. dummy data types*/ /* & init receiving CAN first to allow CAN bus sync time before receiving 1st msg*/ /* Rev 1. /* Put in Freeze Mode & enable all 64 msg bufs */ /* Configure for 8MHz OSC. for (i=0. /* MPC56xxB/S FlexCAN1: select ME.RUNPC[1] */ ME.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ ME. SWT. i++) { CAN_1. modified for newer Freescale header files (r 16) */ /* Rev 0.3.9 May 22 2009 SM .5 Jan 31 2007 SM .1. Made globals uninitialized */ /* 2. Cfg.BUF[4].4 Aug 11 2006 SM .R = 0x0000c520.PCTL[68].R = 0x12400100.MCR init */ /* Rev 0. CAN_1. CAN_1.CODE = 4. 2006 S.modified initModesAndClock. /* Write keys to clear soft lock bit */ SWT.1 Mar 14 2010 SM .Simplified.B. cleared CAN Msg Buf flag by writing to reg */ /* not bit. uint32_t RxLENGTH.RUNPC[1] */ ME.R = 0x80.PLL0ON. 1 */ /* Rev 0.h" /* Use proper include file */ uint32_t RxCODE. instead of 63 */ /* Rev 0.MCR. CAN_1.PCTL[16]. Copyright Freescale. } CAN_1.B.Removed redundant CAN_A.B.CS.R = 0x40005AF0.B. /* MPC56xxB/P/S FlexCAN0: select ME.6 Mar 08 2007 SM .PCTL[17]. All Rights Reserved */ /* Rev 0. RecieveMsg function: read CANx_TIMER.R = 0x0000001D.CODE = 0.S_MTRANS) {} } /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */ void initPeriClkGen(void) { CGM.R = 0x01.R = 0x001F0074.CR.8 May 15 2008 SM .MCTL. added idle loop code for smoother Nexus trace */ /* 4. 0 to FlexCAN C buf.IDE = 0.R = 0x04DB0006.syclk=PLL */ ME.changed Flexcan A to C & enabled 64 msg buffers */ /* Rev 0.RUNPC[1]. /* RUN0 cfg: 16MHzIRCON. i<64. ME. } void disableWatchdog(void) { SWT. uint32_t RxTIMESTAMP. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 1 of the next 2 lines depending on crystal frequency: */ CGM.Changes for MPC56xxB/P/S */ /* Rev 1.MCTL.CS. CAN_1. 4 Freescale Semiconductor 215 .ID. chg’d RxCODE.CS.Removed other redundant CAN_C. removed setting buffer's CODE*/ /* 3. 1 settings: only run in RUN0 mode */ ME.R = 0x4000A50F. /* Peri. uint32_t RxID.R = 0x5000003F.CR.h header file modified to allow byte addressing*/ #include "MPC5604B_0M27V_0102.25.1 Jan 16.FMPLL_CR. /* /* /* /* /* Received Received Recieved Received Received message message message message message buffer code */ ID */ number of data bytes */ data string*/ time */ /* Enable DRUN.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ /* Enter RUN0 Mode & Key */ /* Enter RUN0 Mode & Inverted Key */ /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME.SR. 100kHz bit time */ /* Inactivate all message buffers */ /* MB 4 will look for a standard ID */ /* MB 4 will look for ID = 555 */ /* MB 4 set to RX EMPTY */ Qorivva Simple Cookbook. RUN0.R = 0x0000d928. SAFE.cleared 64 MBs.2 Jun 6 2006 SM .*/ /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME. /* Clear watchdog enable (WEN) */ } void initCAN_1 (void) { uint8_t i.GS.R = 0x8000010A.BUF[4].RUN[0].

/* Use standard ID length */ CAN_0.BUF[4].CS.STD_ID. for (j=0.CODE = 8.BUF[0].B[j]. TIMESTAMP */ RxID = CAN_1.CODE = 0.CR. } /* Assumption: Message buffer CODE is INACTIVE */ const uint8_t TxData[] = {"Hello"}.ID. SIU. RxLENGTH = CAN_1. } CAN_0. SIU.ID. i++) { CAN_0.R = 0x00.PCR[35]. j++) { RxDATA[j] = CAN_1. initCAN_1().IFRL.R = 0x0000003F. /* Put in Freeze Mode & enable all 64 msg bufs */ /* Configure for 8MHz OSC. /* Data frame. /* Wait for CAN 1 MB 4 flag */ RxCODE = CAN_1.RXGMASK.B.CS.PCR[16]. i<sizeof(TxData). SIU.R = 0x0000003F. i++) { CAN_0.B. initModesAndClks().B.BUF[0].BUF[0].MCR.BUF[4].LENGTH. initPeriClkGen().MCR. TransmitMsg(). /* Transmit string*/ CAN_0.B.R = 0x0100.TIMER.LENGTH = sizeof(TxData) -1 .CS.IFRL.STD_ID = 555.BUF[0]. SIU.B.B. SIU. dummy = CAN_1.CS. buf. LENGTH. } RxTIMESTAMP = CAN_1.R = 0x5000003F.B.BUF04I == 0) {}. while (1) { IdleCtr++. /* Read TIMER to unlock message buffers */ CAN_1.R = 0x0624.CODE =0xC. /* Data to be transmitted */ } CAN_0. /* Clear CAN 1 MB 4 flag */ } void main(void) { volatile uint32_t IdleCtr = 0. not remote Tx request frame */ CAN_0. 4 216 Freescale Semiconductor .BUF[4]. ID. j<RxLENGTH.PSMI[0].CS.B. while (CAN_1. DATA. CAN_1. to transmit data frame */ void RecieveMsg (void) { uint8_t j.B.DATA. i<64.CS. disableWatchdog().BUF[4]. /* Read CODE.} CAN_1. /* Activate msg.B. open drain */ /* MPC56xxB: Configure port B1 as CAN0RX */ /* Negate FlexCAN 0 halt state for 64 MB */ } void TransmitMsg (void) { uint8_ti. initCAN_0().BUF[i]. CAN_0.R = 0x0100.PCR[17].R = 0x0624. } /* Initialize mode entries */ /* Initialize peripheral clock generation for DSPIs */ /* Disable watchdog */ /* Initialize FLEXCAN 1 & one of its buffers for receive*/ /* Initialize FlexCAN 0 & one of its buffers for transmit*/ /* Transmit one message from a FlexCAN 0 buffer */ /* Wait for the message to be recieved at FlexCAN 1 */ /* Idle loop: increment counter */ } Qorivva Simple Cookbook.BUF[0].R = 0x00000010. for (i=0.DATA. 100kHz bit time */ /* Inactivate all message buffers */ /* Message Buffer 0 set to TX INACTIVE */ /* MPC56xxB: Config port B0 as CAN0TX.R = 0x04DB0006.CODE. /* Transmit ID is 555 */ CAN_0.CS. RecieveMsg().R = 0x1FFFFFFF.SRR = 1.B.BUF[0]. /* # bytes to transmit w/o null */ for (i=0.B[i] = TxData[i]. /* Tx frame (not req'd for standard frame)*/ CAN_0.BUF[4].B.CS.TIMESTAMP.BUF[0]. Rev.RTR = 0.B.IDE = 0. /* Global acceptance mask */ /* MPC56xxB: Config port C10 as CAN1TX open drain */ /* MPC56xxB: Configure port C3 as CAN1RX */ /* MPC56xxB: Select PCR 35 for CAN1RX Input */ /* Negate FlexCAN 1 halt state for 64 MB */ void initCAN_0 (void) { uint8_t i.CS. CAN_0.CS.MCR.PCR[42]. CAN_0.BUF[0].R. uint32_t dummy.

CGM.Changes for MPC5510 */ /* Rev 0.9 May 22 2009 SM .Changes for MPC56xxB/P/S */ /* Rev 1.CMU_0_CSR. /* Enter RUN0 Mode & Inverted Key */ while (ME.5 Jan 31 2007 SM .Removed redundant CAN_A.cleared 64 MBs.SR.SR.B. uint8_t RxDATA[8].Removed other redundant CAN_C. /* Clear watchdog enable (WEN) */ } void initSAFEPORT (void) { uint8_t i.R = 0x18DB0006. /* Enter RUN0 Mode & Key */ ME.syclk=PLL */ ME. 0 */ /* Rev 0.MCTL. /* Peri.S_MTRANS) {} /* Wait for mode transition to complete */ /* Note: could wait here using timer and/or I_TC IRQ */ while(ME. SWT.CR. /* /* /* /* /* Received Received Recieved Received Received message message message message message buffer code */ ID */ number of data bytes */ data string*/ time */ /* Enable DRUN.Changes for new header file symbols */ /* Rev 0.Mihalik.RUNPC[1]. 2006 S. /* 40 MHz xtal: Set PLL0 to 64 MHz */ ME. 2006.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */ } void initPeriClkGen(void) { CGM.MCR init */ /* Rev 0.*/ /* 8 MHz xtal: Set PLL0 to 64 MHz */ CGM.GS.CR.25. 4 Freescale Semiconductor 217 .RUN[0].0 Jul 10 2009 SM .CODE = 0.MCR init */ /* Rev 0. RecieveMsg function: read CANx_TIMER. /* Put in Freeze Mode & enable all 32 msg bufs */ /* Use 1 of the next 2 lines depending on crystal frequency: */ /*SAFEPORT.R = 0x0000d928. no PLL monitor*/ /*CGM.R = 0x0000c520.1.R = 0x0000001D.R = 0x000000004. modified for newer Freescale header files (r 16) */ /* Rev 0.changed Flexcan A to C & enabled 64 msg buffers */ /* Rev 0.B.R = 0x001F0074.RUNPC[1] */ ME.R = 0x80000000.c: FlexCAN program */ /* Description: Transmit one message from FlexCAN 0 buf. /* MPC56xxB/P/S FlexCAN0: select ME.FMPLL[0]. /* Write keys to clear soft lock bit */ SWT. /* Configure for 40MHz OSC.AC2DC.8 May 15 2008 SM .R = 0x04DB0006. uint32_t RxID. updated header */ /* NOTE!! structure canbuf_t DATA in header file modified to allow byte addressing*/ #include "Pictus_Header_v1_09.B. void initModesAndClks(void) { ME. instead of 63 */ /* Rev 0.*/ /* Monitor FXOSC > FIRC/4 (4MHz). */ /* increased Tx pads slew rate. i<32.3 MPC56xxP /* main. uint32_t RxTIMESTAMP. Made globals uninitialized */ /* 2.4 Aug 11 2006 SM .1 Jan 16. /* Monitor FXOSC > FIRC/1 (16MHz).GS. /* MPC56xxP SafetyPort: select ME.R = 0x5000001F.R = 0x8000010A. */ /* Configure for 8MHz OSC. RESET modes */ /* Initialize PLL before turning it on: */ /* Use 2 of the next 4 lines depending on crystal frequency: */ /*CGM.R = 0x02400100.MER.R = 0x40005AF0.R = 0x01. changed RxCODE.h" /* Use proper include file */ uint32_t RxCODE. dummy data types and */ /* init receiving CAN first to allow CAN bus sync time before receiving first msg*/ /* Rev 1.R = 0x01. simplified.CS.RUNPC[1] */ /* Mode Transition to enter RUN0 mode: */ ME.3 Jun 15 2006 SM .CMU_0_CSR.2 Jun 6 2006 SM .R = 0x000000000.MCTL. */ /* Cleared CAN Msg Buf flag by writing to reg.Corrected init of MBs.PCTL[16].FMPLL[0].PCTL[26].R = 0x4000A50F. no PLL monitor*/ CGM.R = 0x04000000. All Rights Reserved */ /* Rev 0. Copyright Freescale.PLL0ON.AC2SC.R = 0x00000010. RxLENGTH. added idle loop code for smoother Nexus trace */ /* 4. SAFEPORT.BUF[i].3.7 Jul 20 2007 SM . RUN0.Changes made for MPC56xxP. Rev. /* Inactivate all message buffers */ Qorivva Simple Cookbook.MCR. 100kHz bit time */ SAFEPORT.Modified initModesAndClks. Cfg.OSC0ON. /* RUN0 cfg: 16MHzIRCON. } /* MPC56xxP Safety Port: Select PLL0 for aux clk 0 */ /* MPC56xxP Safety Port: Enable aux clk 0 div by 1 */ void disableWatchdog(void) { SWT.CR.0 Mar 14 1020 SM .R = 0x12400100. 1 settings: only run in RUN0 mode*/ ME. SAFE. not bit. removed setting buffer's CODE*/ /* 3. uint32_t RxLENGTH. 100kHz bit time */ for (i=0.6 Mar 08 2007 SM . i++) { SAFEPORT.CR.CR.

/* Read TIMER to unlock message buffers */ SAFEPORT.R = 0x5000001F.MCR. RecieveMsg(). 4 218 Freescale Semiconductor .CS.STD_ID. /* MPC56xxP: Configure port B1 as CAN0RX */ CAN_0. /* Read CODE. disableWatchdog().BUF[4].CS. /* MPC56xxP: Configure port A15 as CAN1RX */ SAFEPORT. initModesAndClks(). dummy = SAFEPORT. 100kHz bit time */ CAN_0.B.CODE =0xC.IFRL.BUF04I == 0) {}.LENGTH.IDE = 0.CS.B. /* # bytes to transmit w/o null */ for (i=0. not remote Tx request frame */ CAN_0.PCR[15]. /* Negate FlexCAN 0 halt state for 21 MB */ } void TransmitMsg (void) { uint8_ti.RXGMASK.BUF[0].R = 0x0624. /* Activate msg.SRR = 1. open drain */ SIU. /* Assumption: Message buffer CODE is INACTIVE */ const uint8_t TxData[] = {"Hello"}.STD_ID = 555.B[i] = TxData[i].BUF[4].B.BUF[0].B. /* Data to be transmitted */ } CAN_0. Rev. initSAFEPORT(). TransmitMsg().CS.BUF[4].PCR[16].CR. ID. while (SAFEPORT.R = 0x0500. open drain */ SIU.CS.CS. buf. /* Put in Freeze Mode & enable all 32 msg bufs */ /* Use 1 of the next 2 lines depending on crystal frequency: */ /*CAN_0. to transmit data frame */ } void RecieveMsg (void) { uint8_t j. /* Message Buffer 0 set to TX INACTIVE */ SIU.} } SAFEPORT.LENGTH = sizeof(TxData) -1 . /* Data frame.DATA.BUF[4].PCR[17].B.B. i<sizeof(TxData).BUF[0].TIMESTAMP.R = 0x0000001F. /* Global acceptance mask */ SIU.R = 0x00000010.BUF[0]. /* Clear SAFETY PORT MB 4 flag */ } void main(void) { volatile uint32_t IdleCtr = 0. } /* Initialize mode entries */ /* Initialize peripheral clock generation for DSPIs */ /* Disable watchdog */ /* Initialize SafetyPort & one of its buffers for receive*/ /* Initialize FlexCAN 0 & one of its buffers for transmit*/ /* Transmit one message from a FlexCAN 0 buffer */ /* Wait for the message to be recieved at FlexCAN 1 */ /* Idle loop: increment counter */ Qorivva Simple Cookbook.TIMER.BUF[4].R = 0x18DB0006. /* Wait for SAFETY PORT MB 4 flag */ RxCODE = SAFEPORT.BUF[0]. /* Transmit string*/ CAN_0.B.CODE = 0.B.R = 0x0624. /* Use standard ID length */ CAN_0.BUF[4].ID.RTR = 0.MCR.CODE = 8.CS.CS. /* Transmit ID is 555 */ CAN_0.B. 100kHz bit time */ for (i=0.B. /* Configure for 40MHz OSC. /* MB 4 will look for a standard ID */ SAFEPORT. i++) { CAN_0. initPeriClkGen().ID.BUF[0]. i++) { CAN_0.CR.R = 0x04DB0006. /* MPC56xxP: Config port A14 as CAN1TX.R = 0x0900. /* Inactivate all message buffers */ } CAN_0.B.B[j].BUF[0]. DATA. /* MPC56xxP: Config port B0 as CAN0TX.BUF[4]. CAN_0.CODE. uint32_t dummy. j++) { RxDATA[j] = SAFEPORT. RxLENGTH = SAFEPORT.CS. /* MB 4 will look for ID = 555 */ SAFEPORT. LENGTH.B.PCR[14].CS.B.MCR. while (1) { IdleCtr++.BUF[0]. j<RxLENGTH. initCAN_0(). /* Negate SAFETY PORT halt state for 32 MB */ void initCAN_0 (void) { uint8_t i.R = 0x0000001F. } RxTIMESTAMP = SAFEPORT.ID.DATA. TIMESTAMP */ RxID = SAFEPORT.CS.R = 0x1FFFFFFF.R.CS. i<32.B. for (j=0. /* Tx frame (not req'd for standard frame)*/ CAN_0.BUF[i]. */ /* Configure for 8MHz OSC.B. /* MB 4 set to RX EMPTY */ SAFEPORT.CODE = 4.IDE = 0.B.BUF[4].STD_ID = 555.IFRL.

Line buffer bus interface width is 32 or 64 bits. Parameters affecting transfers between the flash array and the line buffers. for example. are not optimal out of reset and for best performance should be configured for desired target a system clock frequency. “Optimizing Performance for the MPC5500 Family.1 Flash: Configuration Description Task: Configure the flash performance parameters for a 64 MHz system clock and increase performance for branch instructions by enabling branch target buffers and branch prediction. 32 or 64 bits SRAM other crossbar bus slaves Line Buffer Line Buffer . the core. Qorivva Simple Cookbook. Rev.” MPC5500 e200 Core Branch Target Buffers other crossbar bus masters Crossbar Flash Module Configuration Reg. see application note AN3519. such as in this example. but the actual buffer width is the width of the flash array: either 128 or 256 bits. such as read wait states. it is good practice not to execute code in the same memory that is having its characteristics modified. Line buffers allow overlapping fast access between the crossbar and a flash module line buffer with a slower access between a line buffer and the flash array.. Hence code to modify the flash performance parameters of the module’s configuration register will be executed from SRAM.. When modifying characteristics for a memory. 4 Freescale Semiconductor 219 .26 26. other line buffers 128 or 256 bits Flash Array Figure 39. Hence one line buffer fill from the array will provide multiple bus interface transfers to. For a more complete checklist of performance items. Key elements of the flash module include the flash array and its line buffers. Flash Configuration Example Exercise: Change configuration parameters and attempt to determine performance differences.

This overlapping operation allows the flash module to provide sequential address accesses without any delay. so prefetching will not be a benefit. Rev. 26.2.26. APC (Address Pipelining Control): Address pipelining drives a subsequent access address and control signals while waiting for the current access to complete. Recommendation: Set BFEN = 1 to enable the use of line buffers.2. WWSC (Write Wait State Control): Defines the number of wait states to be added to the flash array access time for writes. another line buffer can be prefetching the next sequential address from the flash array at the same time.2. Therefore as a general rule.3 Line Buffer Prefetch Controls When one line buffer is being accessed from the crossbar.1 Line Buffer Enable BFEN or BFE (FBIU Line Read Buffers Enable): Enables or disables line read buffer hits.2 Line Buffer Wait State and Hold Cycles Wait states and hold cycles are defined to be between the flash line buffers and flash array. APC defines the number of hold cycles between flash array access requests. such as instructions. prefetching should be enabled when accesses are expected to be sequential. IPFEN or IPFE (Instruction Prefetch Enable): Enables line buffers to prefetch instructions. 4 220 Freescale Semiconductor . 26. not between flash and core or crossbar. 26. RWSC (Read Wait State Control): Defines the number of wait states to be added to the flash array access time for reads.2 Design Flash configuration consists of optimizing the flash bus interface for the following areas: • Enabling line buffers • Number of wait states and pipeline hold cycles for a given frequency • Line buffer prefetch controls • Line buffer configurations (MPC551x and MPC56xxB/P/S only) • Read-While-Write control (MPC56xxB/P/S only) NOTE: Be sure to verify flash configuration parameters with the latest data sheet for each device. Prefetching does not provide any benefit if accesses are not sequential beyond a flash line. Qorivva Simple Cookbook. Recommendation: Use the parameter values in the reference manuals for the desired system clock frequency to get fastest performance. Generally data access has addresses more random than sequential.

prefetching the next sequential address usually benefits only instruction fetching. instruction prefetching should be enabled for any access. This is based on the rationale that. large graphic objects. Recommendation: Most of the time.2. Most of the time DMA is simply moving a byte. Few prefetch benefits occur from other masters.Recommendation: Since most instruction accesses are sequential. such as table data. or with fixed partitions. Qorivva Simple Cookbook. or a pool for both instruction and data fetches. (However.5 Line Buffer Configuration (MPC551x and MPC56xxB/P/S) Some devices have two interfaces (ports) to the flash module. such as data fetching. half word. 4 Freescale Semiconductor 221 . or FEC.) Recommend only prefetching for master 0 (core). the line buffer control value is loaded initially from the shadow block by BAM code. or word for MPC5500 and MPC5600 devices. The following table summarizes values for given devices from the respective device documentation. On the MPC551x.2. 26. and DMA. Recommendation: Generally the optimal configuration s would be to have a fixed partition of mostly instructions fetch line buffers. Each port has its own set of line buffers. Many data accesses may be sequential. For MPC56xxB/P. RWWC (Read-While-Write Control): Defines the flash controller response to flash reads while the array is busy with a program (write) erase operation. Recommendation: Prefetch the next sequential line on a hit or a miss. filter coefficients. Settings may be optimized differently in these cases. this may not be true for bus masters such as a display controller. external bus master. hence there are two configuration registers to initialize. only enable prefetching for core instructions. Rev. 26. and for MPC5606S. DPFEN or DPFE (Data Prefetch Enable): Enables line buffers to prefetch data. FlexRAY. For engine control.6 Read-While-Write (RWW) Control (MPC56xxB/P/S) Low cost flash arrays such as on MPC56xxB/P/S do not support RWW as in MPC55xx devices. start with DPFEN = 1. most of the time.2. Likely Recommendation: Terminate RWW or generate bus stall with abort and abort interrupt enabled so the CPU knows it occurred. start with DPFEN = 0 and for MPC5606S with graphics in internal flash.4 Master Prefetch Enables / Disables MnPFE (Master n Pre Fetch Enable) and MnPFD (MPC56xxB/P/S — Disable): Enables (disables on MPC56xxB/P/S) line buffers to prefetch an entire line in the flash array to a line buffer for that master. 26. start with enabled for any read access. LBCFG or BCFG (Line Buffer Configuration): Specifies configuration of how many buffers are used for instruction fetches and data fetches. Line buffers for each port can be organized as a “pool” available for data and instructions. PFLIM (Prefetch Limit): Defines the maximum number of prefetches done on a buffer miss. Recommendation: Determining the setting is not as obvious as for instruction prefetch enable.

1 for data Enable port’s buffers B1_P1_BFE = 1 No instruction access on port 1 Enable prefetching assuming there is significant sequential data Prefetch on miss only (allows more bandwidth for core) All 4 line buffers available for any access Values are system clock frequency dependent - B0_P1_BFE = 1 B0_P1_IPFE = 0 B0_P1_DPFE = 1 Enable port’s buffer - B0_P1_PFLIM = 1 - Page Buffer Configuration Array Access Read Wait States (for 64 MHz) Write Wait States Adv. Data accesses are expected to generally be random. MPC56xxB/P/S Flash Configuration Example Values for 64 MHz System Clock General Recommendations Code Flash (MPC56xxB/P: Bank 0. not sequential Prefetch on hit or miss - Enable port’s buffer - B0_P0_DPFE = 0 - Prefetch Limit Page Buffer Configuration Port 1 Page Buffer Enable (Connected to Instruction Prefetch DCU. Rev. Qorivva Simple Cookbook.Table 102. Pipeline Ctl. 4 222 Freescale Semiconductor . connected to core only on MPC56xxS) Data Prefetch Enable B0_P0_BFE = 1 B0_P0_IPFE = 1 Data Flash (Bank 1) 1 Line Buffer Per Port Access Parameter Comments Parameter Symbol in register PFCR1 Result Value: 0x1084_0101 Comments Enable port’s buffers B1_P0_BFE = 1 Instructions are mostly sequential. DMA on Enable MPC56xxS) Data Prefetch Port 1 fields Enable ignored in MPC56xxB/P) Prefetch Limit B0_P0_PFLIM = 3 B0_P0_BCFG = 3 - Allocate 3 line buffers for instructions. so prefetching can improve performance. Assumes software must first check if any program or erase commands are in progress. Assumes software must first check if any program or erase commands are in progress. Read While Write Ctl. B0_P1_BCFG = 0 - BK0_RWSC = 2 BK0_WWSC = 2 BK0_APC = 2 BK0_RRWC = 0 BK1_RWSC = 2 BK1_WWSC = 2 BK1_APC = 2 Values are system clock frequency dependent Terminate RWW attempt with error response. Terminate RWW BK1_RRWC = 0 attempt with error response. MPC56xxS: Banks 0 & 2) 4 Line Buffers Per Port Parameter Symbol in register PFCR0 Result value: 0x1084_126F Port 0 Page Buffer Enable (Connected to Instruction Prefetch all masters on Enable MPC56xxB/P.

Table 103. MPC56xxB/P/S Crossbar Master Assignments.
Crossbar Physical Master ID 0 1 2 3 4 to 7 MPC56xxB e200z0h core instructions e200z0h core data MPC56xxP e200z0h core instructions e200z0h core data eDMA FlexRAY MPC56xxS e200z0h core instructions e200z0h core data eDMA DCU -

Table 104. MPC56xxB/P/S Access and Protection Example Settings (Result value for MPC56xxS in PFAPR = 0x03F2 005D)
MPC56xxB Value in Register PFAPR Result Value: MPC56xxP Value in Register PFAPR Result Value: MPC56xxS Value in Register PFAPR Result Value:

Parameter

Symbol

0x00FE 000D
Arbitration Mode Master n Prefetch Disable ARBM M0PFD M1PFD M2PFD

0x00FE 005D

0x03F2 005D

3 (start with round-robin and change after application testing as needed) 0 (since core instructions are mostly sequential, so prefetching should help) 1 (assuming CPU data is not normally accessed sequentially) 1 (assuming eDMA will not 0 assuming eDMA will have have significant consecutive significant consecutive data accesses) used for graphics 1 (assuming FlexRAY will not have significant consecutive accesses) 1 (R only for core instructions) 3 (R+W access allowed for core data) 1 (R only for eDMA) 1 (R only unless flashing over FlexRay) 1 (R only for DCU) 0 (assuming DCU will have significant consecutive data used for graphics)

M3PFD

-

Master n Access Protection

M0AP M1AP M2AP M3AP

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 223

x

Table 105. MPC551x, MPC55xx Flash Configuration Example Values (MPC551x port 0 configuration register also uses values LBCF=0, ARB=1 and PRI=0 here and MPC5634M configuration register also uses GCE = 0.)
Device & Reference for APC, RWSC, WWSC Max. Target Frequency Reset Default Up to 25 MHz Up to 50 MHz Up to 80 MHz MnPFE Resulting Core Configuration APC RWSC WWSC DPFEN IPFEN PFLIM BFEN (others Register and 0x0) Value 0 1 1 1 0 1 1 1 1 0 1 1 1 7 0 1 2 7 0 1 2 3 7 1 1 2 7 0 1 2 7 0 1 2 3 7 1 2 3 3 1 1 1 3 1 1 1 1 3 1 1 1 0 0 0 0 0 1 1 1 1 0 3 3 3 0 1 1 1 0 1 1 1 1 0 3 3 3 0 2 2 2 0 2 2 2 2 0 2 2 2 0 1 1 1 0 1 1 1 1 0 1 1 1 PFCRP0 = 0x0800 FF00 PFCRP0 = 0x0801 0815 PFCRP0 = 0x0801 2915 PFCRP0 = 0x0801 4A15 BUICR = 0x0000 FF00 BUICR = 0x0001 0855 BUICR = 0x0001 2955 BUICR = 0x0001 4A55 BUICR = 0x0001 6B55 BUICR = 0x0000 FF00 BUICR = 0x0001 29FD BUICR = 0x0001 2AFD BUICR = 0x0001 4BFD

MPC5510 - port 0 (Reference: MPC5510 Data Sheet, Rev. 3 & MPC5510 Ref Manual, Rev. 1)

MPC5533, MPC5534 Reset Default (Reference: MPC5534 Rev. 1 Addendum, Rev. 1 Up to 25 MHz (Note on up to 25 MHz row: This APC/RWSC/WWSC Up to 50 MHz combination requires setting the Flash MCR register bit Up to 75 MHz PRD=1.) Up to 80 MHz MPC5553, MPC5554, MPC5565, MPC5566, MPC5567 (Reference: published data sheets as of April 2009) Reset Default Up to 82 MHz Up to 102 MHz Up to 132 MHz (MPC555x) or up to 135 MHz (MPC556x) Up to 147 MHz (MPC5566 only) MPC5632M, MPC5634M, Reset Default MPC5634M (Reference: MPC5634M Ref. Up to 40 MHz Manual, Rev. 2) Up to 62 MHz Up to 82 MHz

1

3

4

1

3

3

2

1

BUICR = 0x0001 6CFD PFCR1 = 0x0000 FF00 PFCR1 = 0x0001 2955 PFCR1 = 0x0001 4A55 PFCR1 = 0x0001 6B55

0 1 1 1

7 1 2 3

7 1 2 3

3 1 1 1

0 1 1 1

0 1 1 1

0 2 2 2

0 1 1 1

Qorivva Simple Cookbook, Rev. 4 224 Freescale Semiconductor

Table 106. Flash Configuration Steps (Shown for MPC5554 for up to 82 MHz sysclk)
Step Data Init Determine desired configuration data. In this case, assume an MPC555x running up to 82 MHz. Relevant Bit Fields Pseudo Code FLASH_CONFIG_DATA = 0x0001 29FD FLASH_CONFIG_REG = FLASH_BIUCR uint32_t mem_write_code[] = { 0x90640000, 0x7C0006AC, 0x4E800020 } typedef void (*mem_write_code_ptr_t) (int, int) (*((mem_write_code_ptr_t) mem_write_code)) (FLASH_CONFIG_DATA, &FLASH_CONFIG_ADDR) HID0[PBRED]=0 BUCSR[BBFI]=1 BUCSR[BPEN]=1 spr HID0 = 0x0 (reset default) spr BUCSR = 0x0000 0201

Configure Flash

In RAM, create array structure of machine code to write 32 bits data in r3 to address in r4, ensure the instruction completes, then return. Instruction code is: — stw r3, 0 (r4) — mbar — blr Create a new typedef for function pointer that does not return anything (void) and passes two integers (in r4, then r5 per EABI). Call memory write code function: Cast memory_write_code as a function pointerq — then de-reference it, which converts it to a function which passes, in order: — Value to be written (goes into r3 per EABI) — — Memory address used for write (goes into r4 per EABI)

Enable Branch Acceleration and Branch Target Buffers

Enable branch acceleration for forward and backward branches (reset default = enabled) Invalidate branch target buffers and Enable branch target buffers

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 225

26.3
/* /* /* /* /* /*

Code (Shown for MPC5554 with 64 MHz sysclk)
flash configuration plus using branch target buffers */ Semiconductor, Inc 2008 All rights reserved. */ Dan and Steve Mihalik */ S. Mihalik - added mbar to mem_write_code */ S. Mihalik - updated Config. value */ S. Mihalik - corrected BUCSR value to 0x0201 */

main.c - Example of Copyright Freescale Rev 0.1 Jun 18 2008 Rev 0.2 Oct 30 2008 Rev 0.3 May 20 2009 Rev 0.4 Sep 11 2009

#include "mpc5554.h" /* Include appropriate header file like mpc5554.h */ #define FLASH_CONFIG_DATA 0x001029FD #define FLASH_CONFIG_REG FLASH.BIUCR.R /* MPC5554 config. value for up to 82 MHz */ /* Flash config. register address */

asm void enable_accel_BTB(void) { li r0, 0 /* Enable branch acceleration (HID[PBRED]=0) */ mtHID0 r0 li r0, 0x0201 /* Invalidate Branch Target Buffers and enable them */ mtBUCSR r0 } int main(void) { uint32_t i=0; /* Dummy idle counter */ uint32_t mem_write_code [] = { 0x90640000, /* stw r3,(0)r4 machine code; writes r3 contents to addr in r4 */ 0x7C0006AC, /* mbar machine code: ensure prior store completed */ 0x4E800020 /* blr machine code: branches to return address in link register */ }; typedef void (*mem_write_code_ptr_t)(uint32_t, uint32_t); /* create a new type def: a func pointer called mem_write_code_ptr_t */ /* which does not return a value (void) */ /* and will pass two 32 bit unsigned integer values */ /* (per EABI, the first parameter will be in r3, the second r4) */ (*((mem_write_code_ptr_t)mem_write_code)) /* cast mem_write_code as func ptr*/ /* * de-references func ptr, i.e. converts to func*/ (FLASH_CONFIG_DATA, /* which passes integer (in r3) */ (uint32_t)&FLASH_CONFIG_REG); /* and address to write integer (in r4) */ enable_accel_BTB(); } while(1) {i++;} /* Enable branch accel., branch target buffers */ /* Wait forever */

Qorivva Simple Cookbook, Rev. 4 226 Freescale Semiconductor

26.4

Code (Shown for MPC56xxS with 64 MHz sysclk)

/* main.c - Example of flash configuration plus using branch target buffers */ /* Copyright Freescale Semiconductor, Inc 2009 All rights reserved. */ /* Rev 0.1 May 22 2009 S. Mihalik - Initial version based on AN2865 example */ /* Rev 0.2 Sep 11 2009 S. Mihalik - corrected BUCSR value to 0x0201 */ /* Rev 0.3 Mar 11 2010 S. Mihalik - corrected FLASH_CONFIG_DATA to 0x1084126F */ #include "jdp.h" /* Include appropriate header file like mpc5554.h */ #define #define #define #define FLASH_CONFIG_DATA 0x1084126F /* MPC56xxS flash config value for 64 MHz */ FLASH_CONFIG_REG CFLASH.PFCR0.R /* Flash config. register address */ FLASH_ACCESS_PROT_DATA 0x03F2005D /* MPC56xxS flash access prot. value */ FLASH_ACCESS_PROT_REG CFLASH.FAPR.R /* Flash Access Prot. Reg. address */

asm void enable_accel_BTB(void) { li r0, 0 /* Enable branch acceleration (HID[PBRED]=0) */ mtHID0 r0 li r0, 0x0201 /* Invalidate Branch Target Buffers and enable them */ mtBUCSR r0 } int main(void) { uint32_t i=0; /* Dummy idle counter */ /* NOTE: Structures are default aligned on a boundary which is a multiple of */ /* the largest sized element, 4 bytes in this case. The first two */ /* instructions are 4 bytes, so the last instruction is duplicated to */ /* avoid the compiler adding padding of 2 bytes before the instruction. */ uint32_t mem_write_code_vle [] = { 0x54640000, /* e_stw r3,(0)r4 machine code: writes r3 contents to addr in r4 */ 0x7C0006AC, /* mbar machine code: ensure prior store completed */ 0x00040004 /* 2 se_blr's machine code: branches to return address in link reg.*/ }; typedef void (*mem_write_code_ptr_t)(uint32_t, uint32_t); /* create a new type def: a func pointer called mem_write_code_ptr_t */ /* which does not return a value (void) */ /* and will pass two 32 bit unsigned integer values */ /* (per EABI, the first parameter will be in r3, the second r4) */ (*((mem_write_code_ptr_t)mem_write_code_vle)) /* cast mem_write_code as func ptr*/ /* * de-references func ptr, i.e. converts to func*/ (FLASH_CONFIG_DATA, /* which passes integer (in r3) */ (uint32_t)&FLASH_CONFIG_REG); /* and address to write integer (in r4) */ (*((mem_write_code_ptr_t)mem_write_code_vle)) /* cast mem_write_code as func ptr*/ /* * de-references func ptr, i.e. converts to func*/ (FLASH_ACCESS_PROT_DATA, /* which passes integer (in r3) */ (uint32_t)&FLASH_ACCESS_PROT_REG); /* and address to write integer (in r4) */ enable_accel_BTB(); } while(1) {i++;} /* Enable branch accel., branch target buffers */ /* Wait forever */

Qorivva Simple Cookbook, Rev. 4 Freescale Semiconductor 227

and Handlers Interrupt Type Core Interrupts Memory Section in Examples ivor_branch_table (MPC551x. Table names used in examples are listed for reference. MPC555x Alignment N.Appendix A Interrupt Alignment Summary The table below shows the alignment requirements for interrupts. N. N.A.A.A. 4 228 Freescale Semiconductor . MPC56xxB/P/S only) ivor_handlers INTC SW mode Interrupts INTC HW mode Interrupts MPC551x. ISR’s. interrupt tables.A. Table 107. Rev. and interrupt handlers. Address Locations and Alignment for Interrupt Tables. MPC55xxB/P/S Address IVPR0:19 Alignment 4 KB (0x1000) Address N. 2 KB (0x800) IVPR0:15 + IVORx16:28 INTC_IACKR0:20 [VTBA] IVPR0:15 IVPR: 64 KB (0x1 0000) Handlers: 16 Bytes (0x10) 2 KB (0x800) Software Vector Mode: INTC_IACKR0:20 intc_sw_isr_vector_table [VTBA] Hardware Vector Mode: intc_hw_branch_table IVPR0:19 + 0x800 2 KB (0x800) above a 4 KB boundary 64 KB (0x1 0000) Qorivva Simple Cookbook.

section “ivor_branch_table” is only used for interrupts on MPC551x. NOTE: These examples assume 32 KB of internal SRAM. table starts at: 0x4000 0800 (MPC551x) 0x4000 0000 (MPC555x) For INTC SW vector mode. This memory map is intended as a general example for a single-core processor for both MPC551x and MPC555x devices. only have 24 KB internal SRAM. table starts at 0x4000 3000. 4 Freescale Semiconductor 229 . etc. the Decrementer example does not use the section “intc_hw_branch_table. etc.Appendix B Single Core Build Files This section describes the build files used in this application note’s examples that use only a single core. so the program can run on the MPC5500 family member with the least amount of memory. so adjustments are needed for link files in that case. Therefore some memory section names are defined that do not exist for some builds. and does not exist for MPC555x applications. Some devices. Memory Segment Names 0x4000 0000 interrupts_ram (12 KB) Memory Section Names MPC551x core interrupts ivor_branch_table intc_hw_branch_table ivor_handlers intc_sw_isr_vector_table (code. Memory Map for Executing from Internal SRAM (IVPR Value is Passed as 0x4000 0000) Qorivva Simple Cookbook. B. If using this mode. 0x4000 3000 internal_ram (19 KB) 0x4000 7CFF 0x4000 7FFF stack_ram (1 KB) (stack) Figure 40.) (data. there is no special boot code — the debugger scripts must initialize internal RAM and MMU. as well as setting the instruction pointer to the beginning of code. If using this mode.) For INTC HW vector mode. For example.1 Memory Map for Executing from Internal RAM To execute from SRAM.” Similarly. Only 32 KB RAM is assumed. the memory map in Figure 40 is used. Rev. From this build. such as MPC5604S.

text) *(.text : { *(. _heap_end = ADDR(internal_ram)+SIZEOF(internal_ram).ctors) *(.ivor_branch_table : {} /* For MPC5516 core interrupts */ . 4 230 Freescale Semiconductor . /* These are not currently being used _heap_addr = ADDR(. _stack_end = ADDR(stack_ram).data (DATA) .lcf .sbss (BSS) . /* L2 SRAM Location (used for L2 SRAM initialization) */ L2SRAM_LOCATION = 0x40000000. Qorivva Simple Cookbook. len = 0x3000 internal_ram: org = 0x40003000.sdata (DATA) .intc_hw_branch_table ALIGN (2048) : {} /* For INTC in HW Vector Mode */ .intc_sw_isr_vector_table : {} /* For INTC in SW Vector Mode */ .B.init) *(.bss)+SIZEOF(.+15).eini) . = (.bss (BSS) } > internal_ram : : : : {} {} {} {} } /* Freescale CodeWarrior compiler address designations */ _stack_addr = ADDR(stack_ram)+SIZEOF(stack_ram). Rev.dtors) *(.rodata) *(.ivor_handlers : {} /* Handlers for core interrupts */ } > interrupts_ram GROUP : { .fini) *(. */ __IVPR_VALUE = ADDR(interrupts_ram). } .Simple minimal MPC5500 link file using 32 KB SRAM */ /* Aug 30 2007 initial version */ /* May 09 208 SM: Put stack in it's own 1KB (0x400) memory segment */ MEMORY { interrupts_ram: org = 0x40000000.1 CodeWarrior Link File for Execution from Internal RAM /* 5500_ram.bss).sdata2 : {} extab : {} extabindex : {} } > internal_ram GROUP : { . len = 0x4C00 stack_ram: org = 0x40007C00. len = 0x0400 } SECTIONS { GROUP : { .1.

len = 0x0400 } SECTIONS { GROUP : { .Simple minimal MPC5500 link file for 32 KB SRAM */ Jul 05 2007 S.Stack */ /************************************************************************/ interrupts_ram:org = 0x40000000. assumption: debug scripts will init SRAM.sbss (BSS) : {} . start vector */ MEMORY { /************************************************************************/ /* Address Length Use */ /************************************************************************/ /* 0x4000_0000 .0x4000_2FFF 12 KB RAM . len = 0x3000 internal_ram:org = 0x40003000. Put stack in separate memory segment Notes: 1.2 /* /* /* /* Diab Link File for Execution from Internal RAM 5500_ram.rodata) *(.1.dtors) *(.Interrupt area */ /* 0x4000_3000 .M.+15) & ~15.bss (BSS) : {} } > internal_ram } __IVPR_VALUE = ADDR(interrupts_ram).Code and data */ /* 0x4000_7C00 .sdata (DATA) LOAD(ADDR(.ivor_branch_table : {} /* For MPC5516 core interrupts */ .text) *(.sdata2)+SIZEOF(. Initial version.intc_sw_isr_vector_table ALIGN (2048): {} /* For INTC SW Vector Mode */ . 4 Freescale Semiconductor 231 .init) *(.sdata2)) : {} . len = 0x4C00 stack_ram: org = 0x40007C00.data)) : {} . */ May 09 2008 S.lin . MMU.0x4000_7FFF 1 KB RAM .fini) *(.M.B. /* Pass address to be loaded to spr IVPR */ Qorivva Simple Cookbook.0x4000_7BFF 15 KB RAM .text (TEXT) : { *(. Rev. = (.eini) . } .intc_hw_branch_table ALIGN (2048): {} /* For INTC in HW Vector Mode */ .sdata2)+SIZEOF(.sdata2)+SIZEOF(.sdata2 (TEXT) : {} } > internal_ram GROUP : { .ivor_handlers : {} /* Handlers for core interrupts */ } > interrupts_ram GROUP : { .ctors) *(.data (DATA) LOAD(ADDR(.

bss).sdata2)+SIZEOF(. Qorivva Simple Cookbook.bss)+SIZEOF(. __BSS_END = ADDR(. __BSS_START = ADDR(.sbss).sdata).sdata)+SIZEOF(. __SP_END = ADDR(stack_ram). __DATA_ROM = ADDR(.sdata2). __HEAP_END = ADDR(internal_ram)+SIZEOF(internal_ram). Rev. __DATA_RAM = ADDR(.data). __DATA_END = ADDR(.bss)+SIZEOF(. __HEAP_START= ADDR(.__SP_INIT = ADDR(stack_ram)+SIZEOF(stack_ram). 4 232 Freescale Semiconductor .bss).

sbss0 CLEAR ABS .ld .sdata2 .sbss . : : : : : : : : > > > > > > > > .512 KB flash.sdabase ALIGN(8) . . MMU. .heap ALIGN(16) PAD(heap_reserve) Qorivva Simple Cookbook. */ /* Notes: 1.ivor_branch_table : > interrupts_ram . . .text . 32 KB SRAM */ /* May 09 2008 S.PPC.sdata0 ABS . . Initial version. LENGTH = 12K ORIGIN = . . assumption: debug scripts will init SRAM. . LENGTH = 19K ORIGIN = .secinfo .init . Rev.syscall ..intc_hw_branch_table ALIGN(2048) : > . . .PPC. /* For GHS hostio support */ /* For GHS startup code */ . .data .sdata . .fixtype : : : : : : : : > > > > > > > > /* For MPC5516 core interrupts */ /* For INTC in HW Vector Mode */ /* For core interrupt handlers */ : : : ORIGIN = 0x40000000.L.M.rodata . LENGTH = 1K internal_ram .3 Green Hills Link File for Execution from Internal RAM /* 5500_ram.EMB.Example minimal MPC5500 link file.B.bss . .fixaddr . . 4 Freescale Semiconductor 233 . G.ivor_handlers : > .1. start vector */ MEMORY { /*******************************************************************/ /* Address Length Use */ /*******************************************************************/ /* 4000_0000-4000_2fff 12 KB RAM Interrupt area */ /* 4000_3000-4000_7BFF 19 KB RAM Code and data except stack */ /* 4000_7C00-4000_7FFF 1 KB RAM Stack */ /*******************************************************************/ interrupts_ram internal_ram stack_ram } CONSTANTS { stack_reserve = 1K heap_reserve = 1K } SECTIONS { // RAM SECTIONS . .EMB. . . .

__ghs_romstart = 0. // They are used by the MULTI debugger. = ADDR(. __ghs_ramend = MEMENDADDR(stack_ram). __ghs_rombootcodeend = 0. // They are used by the GHS startup code (_start and __ghs_ind_crt0).stack). // __ghs_rambootcodestart = MEMADDR(interrupts_ram). // // These special symbols mark the bounds of RAM and ROM images of boot code. } Qorivva Simple Cookbook. // __ghs_ramstart = MEMADDR(interrupts_ram). __ghs_rombootcodestart = 0.stack ALIGN(16) PAD(stack_reserve) : > stack_ram /* SP init value addr stack_ram + pad */ __STACK_SIZE __SP_END __IVPR_VALUE = stack_reserve. /* Pass address to be loaded to IVPR */ // // These special symbols mark the bounds of RAM and ROM memory. Rev. __ghs_romend = 0. __ghs_rambootcodeend = ADDR(.fixtype).. = MEMADDR(interrupts_ram). 4 234 Freescale Semiconductor .

the BAM code inside the device will initialize the MMU. When executing from flash. NOTE: These examples assume 32 KB of internal SRAM. If using this mode. we must add some “boot” code. etc. Some devices. section “ivor_branch_table” is only used for interrupts on MPC551x. etc. After reset. Therefore some memory section names are defined that do not exist for some builds. For example. and code to initialize SRAM. including a Reset Configuration Half Word (RCHW). Rev. table starts at: 0x4000 0800 (MPC551x) 0x4000 0000 (MPC555x) For INTC SW vector mode.B. start vector MPC551x core interrupts For INTC HW vector mode. Memory Segment Names 0x0000 0000 0x0001 0000 boot_flash (64 KB) interrupts_flash (64 KB) Memory Section Names boot ivor_branch_table intc_hw_branch_table ivor_handlers intc_sw_isr_vector_table (code. the Decrementer example does not use the section “intc_hw_branch_table. such as MPC5604S. Only 512 KB flash is assumed. table starts at 0x0002 0000.) contains RCHW. so the program can run on the MPC5500 family member with the least amount of memory. Memory Map for Executing from Internal Flash (IVPR Value is Passed as 0x0001 0000) Qorivva Simple Cookbook. If using this mode.” Similarly.) stack_ram (1 KB) (stack) Figure 41. only have 24 KB internal SRAM. a starting vector. and does not exist for MPC555x applications.2 Memory Map for Executing from Internal Flash To execute from flash. 4 Freescale Semiconductor 235 . so adjustments are needed for link files in that case. 0x0002 0000 internal_flash (384 KB) 0x0007 FFFF 0x4000 0000 internal_ram (31 KB) 0x4000 7FFF (data. This is put in the “boot” memory section. This memory map is intended as a general example for a single-core processor for both MPC551x and MPC555x devices. the memory map in Figure 41 is used.

intc_hw_branch_table (TEXT) LOAD (_e_ivor_branch_table) ALIGN (0x800) : {} . } .text : { *(.B. DF initial version */ /* May 09 208 SM: Put stack in it's own 1KB (0x400) memory segment */ MEMORY { boot_flash: interrupts_flash: internal_flash: internal_ram: stack_ram: } org org org org org = = = = = 0x00000000.rodata) *(.fini) *(. len len len len len = = = = = 0x00010000 0x00010000 0x00060000 0x00007C00 0x0400 /* This will ensure the rchw and reset vector are not stripped by the linker */ FORCEACTIVE { "bam_rchw" "bam_resetvector"} SECTIONS { .Simple minimal MPC5500 link file using 32 KB SRAM */ /* Sept 20 2007 SM.text) *(.init) *(.ivor_handlers (TEXT) LOAD (_e_intc_hw_branch_table) : {} /* Each MPC555x handler require 16B alignmt */ } > interrupts_flash GROUP : { . 4 236 Freescale Semiconductor .intc_sw_isr_vector_table ALIGN (2048) : {} /* For INTC in SW Vector Mode */ .sdata2 : {} extab : {} extabindex : {} } > internal_flash Qorivva Simple Cookbook.lcf . 0x40007C00.dtors) *(.2.ivor_branch_table (TEXT) LOAD (ADDR(interrupts_flash)) : {} . = (. 0x00010000. 0x40000000.boot LOAD (0x00000000) : {} > boot_flash /* LOAD (0x0) prevents relocation by ROM copy during startup */ GROUP : { /* Note: _e_ prefix enables load after END of that specified section */ . Rev.+15).eini) .ctors) *(. 0x00020000.1 CodeWarrior Link File for Execution from Internal Flash /* 5500_flash.

data (DATA) : . */ __IVPR_VALUE = ADDR(interrupts_flash). Qorivva Simple Cookbook.sdata0 : {} . _stack_end = ADDR(stack_ram).PPC.sbss0 : {} } > internal_ram } {} {} {} {} /* Freescale CodeWarrior compiler address designations */ _stack_addr = ADDR(stack_ram)+SIZEOF(stack_ram). /* L2 SRAM Location (used for L2 SRAM initialization) */ L2SRAM_LOCATION = 0x40000000.GROUP : { . /* These are not currently being used _heap_addr = ADDR(.sbss (BSS) : .PPC.EMB.bss)+SIZEOF(. 4 Freescale Semiconductor 237 .EMB.bss (BSS) : . _heap_end = ADDR(internal_ram)+SIZEOF(internal_ram).bss).sdata (DATA) : . Rev.

dtors) *(.Available for code. etc */ /* 4000_0000-4000_7BFF 31 KB Internal RAM except stack */ /* 4000_7C00-4000_7FFF 1 KB Internal RAM .RCHW & start vector */ /* 0001_0000-0001_FFFF 64 KB Flash. = (.2.data)) : {} .boot : {} > boot_flash GROUP : { .sbss (BSS) : {} . len = 0x60000 internal_ram: org = 0x40000000.sdata (DATA) LOAD(ADDR(. } . 4 238 Freescale Semiconductor .sdata2)) : {} .sdata2)+SIZEOF(.lin . len = 0x10000 internal_flash: org = 0x00020000.bss (BSS) : {} } > internal_ram Qorivva Simple Cookbook.B.+15) & ~15.stack */ /*******************************************************************/ boot_flash: org = 0x00000000.ivor_branch_table : {} /* For MPC5516 core interrupts */ . 32 KB SRAM */ /* Jul 05 2007 S.ivor_handlers : {} /* For core interrupt handlers */ } > interrupts_flash GROUP : { . len = 0x7C00 stack_ram: org = 0x40007C00.sdata2 (TEXT) : {} } > internal_flash : {} /* For INTC SW Vector Mode */ GROUP : { .fini) *(.text) *(.M.intc_hw_branch_table ALIGN (2048): {} /* For INTC in HW Vector Mode */ .M.Simple minimal MPC5500 link file for 512 KB flash.data (DATA) LOAD(ADDR(. len = 0x0400 } SECTIONS { .init) *(. len = 0x10000 interrupts_flash: org = 0x00010000.eini) .2 Diab Link File for Internal Flash Execution /* 5500_flash.rodata) *(. Put stack in separate memory segment MEMORY { /*******************************************************************/ /* Address Length Use */ /*******************************************************************/ /* 0000_0000-0000_FFFF 64 KB Flash. Initial version.sdata2)+SIZEOF(. Rev.intc_sw_isr_vector_table ALIGN (2048) .text (TEXT) : { *(.ctors) *(.sdata2)+SIZEOF(. */ /* May 09 2008 S.Interrupt area */ /* 0002_0000-0007_FFFF 384 KB Flash.

__BSS_END = ADDR(.bss). __BSS_START = ADDR(. Rev. __DATA_ROM = ADDR(. __DATA_RAM = ADDR(.sdata).bss)+SIZEOF(.sdata)+SIZEOF(. 4 Freescale Semiconductor 239 .bss)+SIZEOF(. __HEAP_START= ADDR(. __HEAP_END = ADDR(internal_ram)+SIZEOF(internal_ram). __DATA_END = ADDR(.} __IVPR_VALUE = ADDR(interrupts_flash).data). __SP_END = ADDR(stack_ram).sbss).sdata2)+SIZEOF(. Qorivva Simple Cookbook.bss). /* Pass address to to load to IVPR */ __SP_INIT = ADDR(stack_ram)+SIZEOF(stack_ram).sdata2).

Rev.ivor_handlers : > . .3 Green Hills Link File for Execution from Internal Flash /* 5500_flash.Example minimal MPC5500 link file. compressed initialized data */ > . etc */ /* 4000_0000-4000_7BFF 31 KB Internal RAM except stack */ /* 4000_7C00-4000_7FFF 1 KB Internal RAM .sdata) : /* CROM(.EMB.CROM.ld .CROM.PPC.B. .L.syscall .512 KB flash.text .EMB. LENGTH = 1K } CONSTANTS { stack_reserve = 1K heap_reserve = 1K } SECTIONS { // FLASH SECTIONS . LENGTH = 384K internal_ram : ORIGIN = 0x40000000..intc_hw_branch_table ALIGN(2048) : > . G.sdata2 . : /* CROM(. Initial version.sdata .RCHW & start vector */ /* 0001_0000-0001_FFFF 64 KB Flash.fixaddr .Stack */ /*******************************************************************/ boot_flash : ORIGIN = 0x00000000.boot : > boot_flash /* For MPC5516 core interrupts */ /* For INTC in HW Vector Mode */ /* For core interrupt handlers */ . . */ MEMORY { /*******************************************************************/ /* Address Length Use */ /*******************************************************************/ /* 0000_0000-0000_FFFF 64 KB Flash. compressed initialized data */ > .ivor_branch_table : > interrupts_flash . .fixtype . . . compressed initialized data */ Qorivva Simple Cookbook. LENGTH = 31K stack_ram : ORIGIN = .rodata . 32 KB SRAM */ /* May 09 2008 S.data : : : : : : : > > > > > > > . .PPC.data) : /* : > internal_flash /* For GHS hostio support */ /* For GHS startup code */ CROM(.sdata0 . . LENGTH = 64K interrupts_flash : ORIGIN = .secinfo .init .CROM. LENGTH = 64K internal_flash : ORIGIN = . . .Interrupt area */ /* 0002_0000-0007_FFFF 384 KB Flash. 4 240 Freescale Semiconductor .sdata0) > .Available for code.M. .2.

bss .sbss0 CLEAR ABS . // __ghs_rambootcodestart = 0. // __ghs_ramstart = MEMADDR(internal_ram). .sdata . = ADDR(.heap ALIGN(16) PAD(heap_reserve) : : : : : : : : > > > > > > > > internal_ram . /* Pass address to load to IVPR */ // // These special symbols mark the bounds of RAM and ROM memory. __ghs_romend = MEMENDADDR(internal_flash).PPC. .sdata0 ABS . __ghs_ramend = MEMENDADDR(stack_ram). .boot).sbss . __ghs_rombootcodestart = ADDR(. // They are used by the MULTI debugger.PPC. __ghs_rambootcodeend = 0. __ghs_romstart = MEMADDR(boot_flash). . 4 Freescale Semiconductor 241 . // // These special symbols mark the bounds of RAM and ROM images of boot code. __ghs_rombootcodeend = ENDADDR(.sdabase ALIGN(8) . // They are used by the GHS startup code (_start and __ghs_ind_crt0).stack). Rev.EMB.fixtype).EMB. . .stack ALIGN(16) PAD(stack_reserve) : > stack_ram /* SP init = addr stack_ram + pad */ __STACK_SIZE __SP_END __IVPR_VALUE = stack_reserve. } Qorivva Simple Cookbook. . = MEMADDR(interrupts_flash).// RAM SECTIONS .data .

s. MPC563x devices have a second watchdog that can be enabled in the RCHW. watchdog(s) are disabled by the RCHW for flash targets. init_l2RAM: lis r11.boot section that contains: — the Reset Configuration Half Word (RCHW) — the vector to the first line of code. 4 242 Freescale Semiconductor . 32 GPRs x 4 B = 128 init_l2ram_loop # loop for 64 KB of RAM Qorivva Simple Cookbook.boot . The code below is from the MPC5553/MPC5554 Reference Manual to initialize 64 KB SRAM. 512 # loop counter for 64 bits x 512 = 64 KB RAM r12 init_l2ram_loop: stmw addi bdnz r0.LONG . It is inserted in the startup file.” and included in the build. 128 # increment the ram pointer.boot code that is added to the startup file of these flash examples. often called the “crt0” file.section . For these examples. RAM executable example programs perform these functions by executing a debugger script file. Code to initialize all of internal RAM. Add a . This must be done before using RAM. 1.3 Additions to Startup File for Flash Executable The startup file. 0(r11) # write all 32 GPRs to RAM r11. Rev. to avoid ECC errors. r11. BOOTID = 0x5A _start Sample code to initialize RAM is listed in the MPC55xx reference manuals. typically labelled “_start” 2. has two modifications below for a flash executable. typically when the debugger starts up.B. . The file is then renamed.LONG 0x005A0000 # RCHW: WTE = SWT = PS = VLE = 0. such as “crt0new. 64-bit word aligned li mtctr r12. 0x4000 # base address of RAM. Below is example .

elf: makefile $(OBJS-FLASH) $(LD) $(LOPTS-FLASH) $(OBJS-FLASH) -o $(EXECUTABLE-FLASH).c. Rev.o LOPTS-FLASH = -tPPC5554ES:cross -@E+err.modified to provide both RAM and FLASH output files OBJS-RAM= main.log -g -O -c -Xdebug-dwarf2-extensions-off / -I .o Qorivva Simple Cookbook.o handlers.S.5.map $(DUMP) -tv $(EXECUTABLE-RAM).elf $(DUMP) -Rv -o $(EXECUTABLE-FLASH).elf / -Wm 5500_flash.s19 $(EXECUTABLE-FLASH). 4 Freescale Semiconductor 243 .B. & P.s19: $(EXECUTABLE-FLASH).s19: $(EXECUTABLE-RAM).elf -Wm 5500_ram.s.lin / > $(EXECUTABLE-RAM).lin > $(EXECUTABLE-FLASH).o handlers.elf clean: del *. 2006 .elf >>$(EXECUTABLE-FLASH)..o crt0new.1 # Rev 1 .log -g LOPTS-RAM = -tPPC5554ES:cross -@E+err.Jan.log -Ws -m6 -lc EXECUTABLE-RAM = DEC-ram EXECUTABLE-FLASH = DEC-flash .updated for DWARF 2.o # For MPC551x only OBJS-FLASH= main. # Rev 2 .o : $(CC) $(COPTS) -o $*.elf: makefile $(OBJS-RAM) $(LD) $(LOPTS-RAM) $(OBJS-RAM) -o $(EXECUTABLE-RAM).\MPC5500 AOPTS = -tPPC5554ES:cross -@E+err.o # For MPC555x only #OBJS-FLASH= main.s19 $(EXECUTABLE-RAM).map # Generate s record file $(EXECUTABLE-FLASH).o ivor_branch_table.elf $(EXECUTABLE-FLASH).o # For MPC551x only #OBJS-RAM= main.3.SUFFIXES: .elf $(EXECUTABLE-FLASH).M.o ivor_branch_table.elf >>$(EXECUTABLE-RAM).map $(DUMP) -tv $(EXECUTABLE-FLASH).o $< .map # Generate s record file $(EXECUTABLE-RAM).o # For MPC555x only CC = dcc AS = das LD = dcc DUMP = ddump COPTS = -tPPC5554ES:cross -@E+err.o : $(AS) $(AOPTS) $< default: $(EXECUTABLE-RAM).s19 $(EXECUTABLE-FLASH).elf $(EXECUTABLE-RAM).March. 2003 .log -Ws -m6 -lc -l:crt0.c .4 “Makefile” for Building Flash & RAM Executable Programs # makefile : Sample makefile for MPC5500 to work with Diab v5.0 output # Rev 3 .o handlers.o crt0new.s .elf $(DUMP) -Rv -o $(EXECUTABLE-RAM).s19 $(EXECUTABLE-RAM).based on example from S.Feb. 2007 .o handlers.

” The linker files must indicate code sections to be VLE.text : {} . Language Settings — C/C++ PreProcessor: Set the preprocessor macro: “#define VLE_IS_ON 1”. In the project’s settings.ivor_branch_table_p0 (VLECODE) LOAD (0x00001000) : {} .intc_sw_isr_vector_table_p0 ALIGN (2048) : {} . the following must be done. 4 244 Freescale Semiconductor .rdata) *(.c when setting up the RCHW.5 VLE Implementation .init_vle (VLECODE) : { *(.init) *(.text_vle) } .intc_hw_branch_table_p0 LOAD (0x00001800): {} .B. This gets used in MPC55xx_init. Rev. Example: SECTIONS { . 3. the PEMicro debugger would have the Argument: LOADTORAM -RESETFILE “mpc5516vle.rodata) } . check the item “Generate VLE Instructions. Code Generation — EPPC Processor: In the “e500/Zen Options” box.text_vle (VLECODE) ALIGN(0x1000): { *(.__bam_bootarea LOAD (0x00000000): {} > resetvector GROUP : { .rodata (CONST) : { *(. If converting an existing project to use VLE.init : {} . Qorivva Simple Cookbook. which start with “e_” or “se_”.ctors : {} . the debugger may need to know code is VLE.__exception_handlers_p0 (VLECODE) LOAD (0x00001100) : {} } > exception_handlers_p0 GROUP : { .dtors : {} extab : {} extabindex : {} } > internal_flash Any assembly function must either be encapsulated in a C function or use VLE mnemonics. Target — Build Extras: If “Use External Debugger” is checked.text) *(. change the following: 1.CodeWarrior Project CodeWarrior’s project wizard allows selection of the project to be VLE.init_vle) } . For example.mac” 2.

39 41 44 45 . unclocked in others. Peripheral Control Registers ME_PCTL # 4-5 6 7 10 16 17 18 19 .21 23 24 26 32 33 35 38 .Appendix C MPC56xxB/P/S Peripheral Clocks Clocks to peripherals are sometimes not connected after reset. there will be a bus error when attempting to access any of its registers.49 50 . This allows peripherals to be clocked in some modes. Table 108. Rev. ME_LP_PCx registers and each peripheral’s ME_PCTLx register. Software must initialize in two ways: C. DCU MPC56xxB MPC56xxP MPC56xxS Y Y — — Y Y Y Y — — — Y — — — — Y — Y Y — Y Y — — — Y Y Y — Y — — — — Y Y Y Y Y Y Y — — Y — — — — — — — Y — — Y Y Y — — Y — — Y — — — — Y Y Y — Y — Y Y Y Y Qorivva Simple Cookbook.51 56 57 60 61 62 63 Peripheral DSPI 0:1 DSPI 2 DSPI 3 QuadSPI FlexCAN 0 FlexCAN 1 FlexCAN 2 FlexCAN 3:5 DMA Mux FlexRAY Safety Port ADC 0 ADC 1 CTU 0 eTimer 0:1 FlexPWM 0 I2C DMA 0 I2C DMA 1:3 LIN FLEX 0:1 LIN FLEX 2:3 Gauge Driver CTUL CAN Sampler LCD Sound Gen. If a peripheral does not have a clock.1 Peripheral Clock Gating on a Mode Basis Clocks are gated to peripherals based on ME_RUN_PCx.47 48 . The table below lists the ME_PCTLx registers and the peripherals they control. 4 Freescale Semiconductor 245 .

etc. Table 109. LCD CMU Monitor CGM_AC1_SC FlexCAN CGM_SC_DC1 CGM_AC1_DC0 CAN Sampler DSPI CGM_AC2_SC ADC CGM_AC2_DC0 CGM_AC3_SC DCU CGM_AC3_DC0 eMIOS_0 eMIOS_1 QuadSPI CGM_SC_DC2 2 FlexCAN DSPI eMIOS ADC CTU CGM_SC_DC1 3 CGM_SC_DC2 Safety Port — — — — FlexRay CGM_AC0_SC CGM_AC1_SC CGM_AC1_DC0 CGM_AC2_SC CGM_AC2_DC0 CGM_AC3_SC Qorivva Simple Cookbook. 4 246 Freescale Semiconductor . Sometimes you must specify the clock source such as PLL. The following table lists the sets and the registers that must be configured to use any peripheral in that set. Rev. Peripheral Control Registers ME_PCTL # 68 69 72 . This clock generation is done on a “peripheral set” basis where all peripherals in a group run at the same frequency. some peripherals also require generating a clock to them.2 Clock Generation on a Peripheral or Peripheral Set Basis In addition to the peripheral clock gating. Clocks to those peripherals may be disabled after reset and must be enabled with a clock divider value.Table 108.73 91 92 104 Peripheral SIUL WKPU eMIOS 0:1 RTC/API PIT/RTI CMU MPC56xxB MPC56xxP MPC56xxS Y Y Y Y Y Y — — — — Y — Y Y Y Y Y Y C. external oscillator. Peripheral Set Clock Generation Registers MPC56xxB Peripheral Set Registers to Enable and Generate Clock CGM_SC_DC0 MPC56xxP (after cut 1) Registers to Enable and Generate Clock MPC56xxS (after cut 1) Registers to Enable and Generate Clock Peripherals LINFlex I2C Peripherals Peripherals 1 Motor Control CGM_AC0_SC LINFlex CGM_SC_DC0 CGM_AC0_DC0 I2C Motor Control Stall Detect Sound Gen.

Qorivva Simple Cookbook. 4 Freescale Semiconductor 247 . Rev.

Freescale sells products pursuant to standard terms and conditions of sale. All other product or service names are the property of their respective owners. Freescale makes no warranty. nor does Freescale assume any liability arising out of the application or use of any product or circuit. Off.com Web Support: freescale.org word marks and the Power and Power. mobileGT. and Xtrinsic are trademarks of Freescale Semiconductor.reg. and specifically disclaims any and all liability. Document Number: AN2865 Rev.. representation. ColdFire. The Power Architecture and Power. QUICC Engine. C-Ware. Flexis. Airfast. PowerQUICC. Reg. SMARTMOS. ColdFire+. which can be found at the following address: http://www. SafeAssure. or guarantee regarding the suitability of its products for any particular purpose. Energy Efficient Solutions logo. Ready Play. Kinetis. U.org logos and related marks are trademarks and service marks licensed by Power. All operating parameters. MXC. Processor Expert.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products.htm Freescale. © 2005–2010 Freescale Semiconductor. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. CodeTest. and VortiQa are trademarks of Freescale Semiconductor. Inc. Inc. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications. CoreNet. & Tm. C-5. Qorivva.net/v2/webservices/Freescale/Docs/TermsandConditions. and actual performance may vary over time. Inc. Pat. including “typicals. Vybrid. the Freescale logo. Freescale does not convey any license under its patent rights nor the rights of others. MagniV. TurboLink.” must be validated for each customer application by customer’s technical experts. Platform in a Package. BeeKit. Freescale reserves the right to make changes without further notice to any products herein. AltiVec. BeeStack. QorIQ Qonverge.org. 4 04/2010 .How to Reach Us: Home Page: freescale. Symphony. StarCore. QorIQ.S. including without limitation consequential or incidental damages. CodeWarrior.

Sign up to vote on this title
UsefulNot useful