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Designing A SEPIC Converter

Designing A SEPIC Converter

National Semiconductor Application Note 1484 Wei Gu June 2007

In a SEPIC (Single Ended Primary Inductance Converter) design, the output voltage can be higher or lower than the input voltage. The SEPIC converter shown in Figure 1 uses two inductors, L1 and L2. The two inductors can be wound on the same core since the same voltages are applied to them

throughout the switching cycle. Using a coupled inductor takes up less space on the PCB and tends to be lower cost than two separate inductors. The capacitor Cs isolates the input from the output and provides protection against a shorted load. Figures 2 and 3 show the SEPIC converter current flow and switching waveforms.


FIGURE 1. SEPIC Topology


FIGURE 2. SEPIC Converter Current Flow Top: During Q1 On-Time, Bottom: During Q1 Off-Time


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national. The peak current in the inductor. to ensure the inductor does not saturate. The ripple current flowing in equal value inductors L1 and L2 is given by: If L1 and L2 are wound on the same core. and the maximum drain to source voltage. www. The maximum duty cycle is: Inductor Selection A good rule for determining the inductance is to allow the peak-to-peak ripple current to be approximately 40% of the maximum input current at the minimum input voltage. Logic level or sublogic-level threshold MOSFETs should be used based on the gate drive voltage. the on-resistance RDS (ON). The inductor value is calculated by: Power MOSFET Selection The inductor value is calculated by: The parameters governing the selection of the MOSFET are the minimum threshold voltage Vth(min). gate-drain charge QGD. VDS(max). the value of inductance in the equation above is replaced by 2L due to mutual inductance. SEPIC Converter Switching Waveforms (VQ1: Q1 Drain to Source Voltage) Duty Cycle Consideration For a SEPIC converter operating in a continuous conduction mode (CCM).AN-1484 20194803 FIGURE 3. is given by: VD is the forward voltage drop of the diode 2 . the duty cycle is given by: fsw is the switching frequency and Dmax is the duty cycle at the minimum Vin.

Output Ripple Voltage The ESR.AN-1484 The peak switch voltage is equal to Vin + Vout. SEPIC Coupling Capacitor Selection The selection of SEPIC capacitor. having high RMS current ratings relative to size. Ensure that the conduction losses plus the switching losses do not exceed the package ratings or exceed the overall thermal budget. Hence. or multi-layer ceramic capacitors are recommended at the output. Similar to the boost converter. Thus the selected output capacitor must be capable of handling the maximum RMS current. the average diode current is equal to the output current. the peak voltage is typically close to the input voltage. ESL. and polymer tantalum. the inductor is charging and the output current is supplied by the output capacitor. good quality cawww. when the power switch Q1 is turned on. the diode peak current is the same as the switch peak current IQ1(peak). tantalum. the SEPIC has an inductor at the input. a 10 µF or higher value. ESR and capacitance requirements. The minimum peak reverse voltage the diode must withstand is: 20194816 FIGURE 4. The RMS current in the output capacitor is: (2) PQ1. The peak switch current is given by: trolytic capacitors work well for through-hole applications where the size is not limited and they can accommodate the required RMS current rating. polymer electrolytic. Elec3 (5) The input capacitor should be capable of handling the RMS current. Hence. Tantalum and ceramic capacitors are the best choice for SMT. depends on the RMS current. IG is the gate drive current. As a result. which is given by: Input Capacitor Selection Similar to a boost converter. Output Capacitor Selection The MOSFET power dissipation PQ1 is approximately: In a SEPIC converter. the output capacitor sees large ripple currents. and the bulk capacitance of the output capacitor directly control the output ripple. The voltage rating of the SEPIC capacitor must be greater than the maximum input voltage. the total power dissipation for MOSFETs includes conduction loss (as shown in the first term of the above equation) and switching loss as shown in the second term. (3) (4) The output cap must meet the RMS current. As shown in Figure 4. This property makes the SEPIC much better suited to lower power applications where the RMS current through the capacitor is relatively small (relative to capacitor technology). Although the input capacitor is not so critical in a SEPIC application. Output Diode Selection The output diode must be selected to handle the peak current and the reverse voltage. In a SEPIC. The peak-to-peak ripple voltage on Cs (assuming no ESR): (1) The RMS current through the switch is given by: A capacitor that meets the RMS current requirement would mostly produce small ripple voltage on Cs. Schottky diodes are recommended in order to minimize the efficiency loss. The power dissipation of the diode is equal to the output current multiplied by the forward voltage drop of the diode. In surface mount applications. Hence. The inductor ensures that the input capacitor sees fairly low ripple . Cs. The RDS(ON) value should be selected at maximum operating junction temperature and is typically given in the MOSFET datasheet. we assume half of the ripple is caused by the ESR and the other half is caused by the amount of capacitance. The RMS current in the input capacitor is given by: The SEPIC capacitor must be rated for a large RMS current relative to the output power. the input current waveform is continuous and triangular.national.

5A Switching frequency fsw: 330kHz LM3478 controller is used in this example. Si4442DY (RDS(ON) = 8mΩ and QGD = 10nC) is selected in this design.0V-5.AN-1484 pacitor would prevent impedance interactions with the input supply.5V.national. The gate drive current IG of the LM3478 is 0. Schematic Step 1: Duty cycle calculation We assume that the VD is 0. The estimated power loss is: (9) The closest standard value of an off-the-shelf inductor is 4. The peak input inductor current is: www.3V Output current (IOUT): 2.7V LM3478 controller is used in this example.7 µ 4 . SEPIC Converter Design Example Input voltage (VIN): 3. Output voltage (VOUT): 3. Schematic is shown in Figure 5. 20194820 FIGURE 5. (10) The peak current for L2 is: (6) (11) Step 3: Power MOSFET selection The MOSFET peak current is: (7) Step 2: Inductor selection The input inductor L1 ripple current is: (12) and the RMS current is: (8) and the inductance for L1 and L2 is: (13) The rated drain voltage for the MOSFET must be higher than VIN+VOUT. Schematic is shown in Figure 5.3A.

For cost-sensitive applications. Rc is chosen to set the desired crossover frequency. Step 8: Feedback resistors. Gcs is the current sense gain (roughly 1/Rsn) 100A/V.26V. an electrolytic capacitor and a ceramic capacitor can be used together. Step 5: SEPIC coupling capacitor selection The RMS current of the Cs is: For the LM3478. Step 7: Input capacitor selection The RMS current of the input capacitor is: Parts . There is also a right-halfplane zero (fRHPZ). which has one zero at 1/(2πRc*Cc1). current sensing resistor calculation and frequency set resistor R1 is the top resistor and R2 is the bottom resistor of the voltage divider. where RL is the load resistant.national. the threshold voltage to trigger the current protection circuit is 120mV. and another pole at 1/(2πRc*Cc2).26V. then: (14) Step 4: Output diode selection The rated reverse voltage of the diode must be higher than VIN+VOUT and the average diode current is equal to the output current at full load. 5 www. Thus the sensing resistor value is: and the ripple voltage is Rf is approximately 50 kΩ for 330 kHz operation. Subtracting the compensation slope voltage drop from 120mV.AN-1484 If R1 = 20 kΩ. Noise sensitive applications can include a second stage filter. VOUT is the output voltage. The ESR zero of the output capacitor is 1/(2πESR*Cout). Step 9: Compensation Design In the control to output transfer function of a peak current mode controlled SEPIC converter. Where.3V output voltage. we get approximately 75mV. the ESR of the output capacitor is: and the capacitance is: The crossover frequency is set at one sixth of the fRHPZ or fR. The feedback reference voltage is 1. whichever is lower: Two pieces of 100 µF (6mΩ ESR) ceramic caps are used. the load pole can be estimated as 1/(2πRL*Cout). and Gma is the error amplifier transconductance (800 µmho). given by: A 10 µF ceramic cap is selected. Cout is the output capacitor and ESR is the Equivalent Series Resistance of the output capacitor. Step 6: Output capacitor selection The RMS current of the output capacitor is: We can also see a “glitch” in the magnitude plot at the resonant frequency of the network formed by the SEPIC capacitor Cs and the inductor L2: Assuming the peak-to-peak ripple is 2% of the 3. one pole at the origin. Cc2 and Rc form a compensation network. VREF is the reference voltage of 1.

com 6 . www.national.AN-1484 Cc1 is chosen to set the compensator zero to ¼ of the crossover frequency The pole at 1/(2πRc*Cc2) is to cancel the ESR zero 1/ (2πESR*Cout).

AN-1484 Notes 7 .

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