Syllabus

DIGITAL ELECTRONICS
EEC-302
UNIT-I
Digital System and Binary Numbers
Signed binary numbers, binary codes, cyclic codes, error detecting and correcting codes, hamming codes.
Floating Point Representation
Gate-level minimization: The map method up to five variable, dont care conditions, POS simplification, NAND
and NOR implementation, Quine Mc-Clusky method (Tabular method).
UNIT-II
Combinational Logic
Combinational circuits, analysis procedure, design procedure, binary adder-subtractor, decimal adder, binary
multiplier, magnitude comparator, decoders, encoders, multiplexers.
UNIT-III
Synchronous Sequential Logic
Sequential circuits, storage elements; latches, flip flops, analysis of clocked sequential circuits, state reduction
and assignments, design procedure.
Registers and Counters
Shift registers, ripple counter, synchronous counter, other counters
UNIT-IV
Memory and Programmable Logic
RAM, ROM, PLA, PAL.
Design at the Register Transfer Level
ASMs, design example, design with multiplexers.
UNIT-V
Asynchronous Sequential Logic
Analysis procedure, circuit with latches, design procedure, reduction of state and flow table, race free state
assignment, hazards.

DIGITAL ELECTRONICS
Nandani Prakashan Pvt. Ltd.
7/22 1st Floor, Ansari Road, Daryaganj, Delhi-110002.
E-mail: nandaniprakashan@gmail.com
Ph. 011-43522135, 011-47078713

Prabhakar Sharma
B.Tech, M.Tech (CDAC-Mohali)
Assistant Professor
ITS Engineering College, Gr. Noida

Shilpa Sharma
B.Tech, M.Tech.
(Banasthali University
Jaipur)

EEC-302
DIGITAL ELECTRONICS
Prabhakar Sharma
Shilpa Sharma
Published by:
NANDANI PRAKASHAN PVT. LTD.
7/22, 1st Floor, Ansari Road, Daryaganj, New Delhi-110002
E-mail: nandaniprakashan@gmail.com
Phone : 011-43522135, 011-47078713

 Publisher
First Edition : 2013
All rights reserved, No part of this publication may be reproduced, translated or
transmitted (except for review or criticism), without the written permission of the
publishers.
ISBN: 978-93-81126-56-1
Printed at:
Durga Offset Printers, Haryana.

Dedicated in the Lotus feet of

My Parents
Er. B. N. Sharma
Mrs. Sumitra Sharma
&
My Loving Sons
Master Love and Master Bhumik

Preface
This book has been written primarily to serve as a textbook in accordance with the syllabus of
Digital Electronics course offered by MTU Noida and GBTU Lucknow. It is intended to provide a
student with clear understanding of the fundamentals of Digital Electronics with an emphasis on solving
large number of numerical problems that generally ask in their examinations.
The book has been organised accordance to the syllabus of MTU and GBTU. The complete syllabus
is divided into five units. The first unit introduce digital system, binary numbers and gate level
minimization technique.
The second unit cover the combinational logic circuits like adder, subtractor, comparator, multiplier,
decoder, encoder, mux, demux and designing. The third unit deal with the synchronous sequential logic
circuits and its designing. It cover all types of flip-flops, analysis of clocked sequential circuits, state
reduction and assignment. The second part of this unit deals with registers and counters.
The fourth unit outlines the construction of various primary memories and programmable logic
devices like PAL and PLA. The second part of this unit introduces design at the register transfer level
like ASMs. The fifth unit deals with asynchronous sequential circuits with races and hazards.
This book is a gradual development of our lecture notes on Digital Electronics used for last six plus
years. Our experience tells us that a text book, which is meant for learning a student, who trying to
understand subject for the first time, must clarify all the basic features of the subject in a most lucid and
systematic manner. This book is written with the same central idea, so that students can be benefitted
from this book with a greater sense of ease.
Illustrative large number of examples and solved problems with the previous year university questions
are interspersed throughout the book at their natural locations. These have been selected so that apart
from illustrating the concepts involved, all types of questions have covered which was asked in last
years university exams. For the basics, some short question and answer are given at the end of book
which cover all fundamentals and frequent ask queries.
In spite of our best care, it is just possible that some errors, printing mistakes etc. might have
occurred. We shall be thankful if the same are bought to our notice. Suggestions for further improvement
of the book will be thankfully acknowledged by the authors at prabhakar.sh@gmail.com.
Prabhakar Sharma
Shilpa Sharma

Acknowledgements
I am obliged to my parents Er. B.N. Sharma and Mrs. Sumitra Sharma for everything that I have. How
can I acknowlege my teachers and mentors who made me what I am today, still my great regards will
forever in their lotus feet.
I wish to express my profound thanks to all those who helped in making this book a reality. I thank
to Prof. Vikas Maheswari, Prof. Prabhat Sharma, Prof. Kapil Kumawat, Prof. Ravi Singh, Prof. Sumit
Tripathi and Prof. Pooja Japra for extending their cooperation while writing this book.
I would like to my sincere thanks to the entire management of ITS engineering college, Dr. R.P.
Chadhna (Chairman) and Mr. B.K. Arora (Secretary) specially. I forward my regards to Dr. N.T. Rao
(Director), Dr. L.N. Paliwal (D.G.), Prof. R.K. Yadav (HOD-EC), Prof. Vijay Shukla (HOD-CS),
Prof. Subhajit Ghosh (HOD-IT), Prof. Chadna (HOD-EEE), Dr. Jai Prakash (VC, GLA University),
Dr. Parul Garg (Professor, NSIT New Delhi), Dr. R. Kumar (DG, VGI), Dr. Himanshu Vijay (AEC,
Agra) Prof. Sanjay Singhal (AEC, Agra) and to all my colleagues for their support throughout the
work.
I am greatly thankful to Mrs. Shimsa Verma, Mr. Rahul Verma and all other staff members of
Nandani Prakashan Pvt. Ltd. for making this book a great reality.
Thanks to you my students, enjoy learning Digital Logic Design.
Prabhakar Sharma

We are Thankful to
Dr. T.N. Sharma GLA University, Mathura
Prof. V.K.Deolia GLA University, Mathura
Prof. A.K. Singh ITS Engg. College, Gr. Noida
Dr. Sanjay Agrawal IGNOU, New Delhi
Dr. Himanshu Vijay AEC, Agra
Prof. Brajesh Kaushal FET, Agra
Prof. S.K. Dubey Accurate, Gr. Nodia
Prof. S.K. Jaiswal IEM, Mathura
Prof. Ayub Khan AEC, Agra
Prof. Sanjay Singh HCST, Agra
Prof. Manish Sharma AEC, Agra
Prof. Prakash Chandra AEC, Agra
Prof. M.K. Agrawal GLA University, Mathura
Prof. Vikas Chawla MPGIT, Kanpur
Prof. S.K. Dwivedi HITM, Agra
Prof. Manish Gupta HITM, Agra
Prof. Abhay Chaturvedi GLA University, Mathura
Er. Nagesh Sharma JPM Group, Gurgaon
Er. Devendra Gautam Vodafone, Karnal
Er. Lokendra Sharma N.Railway
Er. J.P. Sharma N.Railway
Mr. Ashish Sharma Govt. Contractor
Dr. Ravi Kumar Fair Wealth Security Ltd.
Prof. Ravindra Sharma BSACET, Mathura
Mr. R.B. Sharma Store Incharge, AEC, Agra
Prof. Kapil Kumawat SBCET, Jaipur
Prof. Anand Kumar Galgotias, Gr. Noida
Prof. Ashish Gupta ITS, Gr. Noida
Mr. Vijay Pratap Yadav ITS, Gr. Noida
Prof. Manish Saraswat ABES, Ghaziabad
Prof. Arun Sharma SIT, Mathura
Prof. Rishi Sikka Sanjay Institute, Mathura
Prof. Chandra Shankar Porwal JSS Academy, Noida
Prof. Abhay Goel VIET, Gr. Noida
Prof. Anubhav Kumar VIET, Gr. Noida
Prof. Awanish Kaushik VIET, Gr. Noida

Mr. Harish Saraswat VIT, Gr. Noida

Prof. Praveer Saxena Accurate, Gr. Noida
Prof. Shweta Varshney KIET, Ghaziabad
Prof. Alok Kumar GLA University, Mathura
Prof. Santosh Sahu HITM, Agra
Prof. Vijay Dixit BSACET, Mathura
Adv. R.P. Gupta Advocate, Ghaziabad
Prof. R.K. Pachauri Sarswati Institute, Ghaziabad
Prof. A.N. Mishra Bhagwati Institute, Ghaziabad
Prof. Rahul Saraswat HITM, Agra
Prof. R.S. Tomar AEC, Agra
Prof. Anamika Sharma ABSS, Meerut
Prof. Prashant Kr. Pradhan ITS, Gr. Noida
Prof. Anubhav Singhal MIET, Meerut
Prof Sunil Kumar IET, Sitapur
Prof. Anubhav Yadav ITS, Gr. Noida
And all others who taught us, suggested us and helped us directly or indirectly.

Prabhakar Sharma
Shilpa Sharma
xii Acknowledgments

Contents
1. NUMBER SYSTEM AND GATE LEVEL MINIMIZATION 1110
1.1 Introduction of Analog and Digital Signals ............................................................................3
1.1.1 Analog and Digital Systems ................................................................................................ 3
1.1.2 Representation of Digital Signals ........................................................................................ 3
1.1.3 Advantages of Digital System ............................................................................................. 4
1.2 Number Systems .......................................................................................................... .............4
1.2.1 Decimal Number System ...................................................................................................... 5
1.2.2 Binary Number System .................................................................................................. ...... 5
1.2.3 Octal Number System ................................................................................................... ........ 5
1.2.4 Hexadecimal Number System .............................................................................................. 5
1.3 Interconversion of Numbers .....................................................................................................6
1.3.1 Conversion from any Base to Decimal Number (Multiplication Method) ......................... 6
1.3.2 Conversion from Decimal Number to any Base Number
(Repeated Division and Multiplication Method) .......................................................................... 7
1.3.3 Conversion from Octal Number to Binary Number ............................................................. 9
1.3.4 Conversion from Binary Number to Octal Number ............................................................. 9
1.3.5 Conversion from Hexadecimal Number to Binary Number .............................................. 10
1.3.6 Conversion from Binary Number to Hexadecimal Number .............................................. 10
1.3.7 Conversion from Octal Number to Hexadecimal Number ................................................. 10
1.3.8 Conversion from Hexadecimal Number to Octal Number ................................................. 11
1.4 Signed Binary Number .................................................................................................... .... .11
1.4.1 Sign Magnitude Representation ........................................................................................ 11
1.4.2 1s Complement Representation ....................................................................................... 12
1.4.3 2s Complement Representation ....................................................................................... 12
1.5 Complement Representation ............................................................................................... ... 13
1.5.1 Radix Complement ...................................................................................................... ... ... 13
1.5.2 Diminished Radix Complement ..................................................................................... ... 13
1.6 Arithmetic Operations Using Complements ......................................................................... 14
1.6.1 Arithmetic Operation using rs/radix Complement (2s/8s/10s/16s) ........................... . 14
1.6.2 Arithmetic Operation using (r 1)s/Diminished Radix Complement (1s/9s/7s/15s) . 16
1.6.3 Arithmetic Operation of Two Same Sign Operands using rs and (r 1)s
Complement Method ......................................................................................................... 18
1.7 Binary Codes ....................................................................................................................... 20
1.7.1 Binary Coded Decimal (BCD) Code ............................................................................... 21
1.7.2 Other 4-bit Weighted BCD Codes .................................................................................... 25
1.7.3 Biquinary Code.................................................................................................................. 26
1.7.4 Non-Weighted Codes ........................................................................................................ 26
1.7.5 Cyclic Codes ..................................................................................................................... 28
1.8 Error Detecting and Correcting Codes ................................................................................. 28
1.8.1 Error Detection Code ........................................................................................................ 29
1.8.2 Error Correction Code ....................................................................................................... 32

1.8.3 Detection and Correction of Error ................................................................................... . 33

1.8.4 Single-error Correction, Double-error Detection ............................................................... 35
1.9 Floating Point Representation ............................................................................................ . 36
1.9.1 IEEE Standards of Floating Point Representation ........................................................... . 37
1.10 Minimization of Boolean Expression ...................................................................................39
1.10.1 Algebraic Simplifications ................................................................................................. 39
1.10.2 Boolean Algebra ............................................................................................................... 40
1.10.3 Logic Gates ....................................................................................................................... 43
1.11 Karnaugh-map Simplification ..............................................................................................47
1.11.1 Representation of K-map .................................................................................................. 47
1.11.2 Representation of SOP and POS form on K-map ............................................................. 49
1.11.3 Grouping of Adjacent Cells .............................................................................................. 50
1.12 Simplification of SOP Form Using K-map ......................................................................... 52
1.13 Simplification of POS Using K-map ....................................................................................53
1.13.1 Conversion of SOP form into POS form and Vice-versa into K-map ............................ . 54
1.14 Dont Care Conditions ..................................................................................................... .. .56
1.15 NAND and NOR Implementation ....................................................................................... 57
1.15.1 Two Level NAND and NOR Implementation ................................................................. 58
1.15.2 Multilevel NAND and NOR Implementation .................................................................. 61
1.16 Quine-Mcclusky (Tabular) Method .....................................................................................63
1.16.1 Minimisation of Boolean Expression by Decimal Representation Method ..................... 63
1.16.2 Minimisation of Boolean Expression by Binary Representation Method ........................ 66
1.17 University Questions ........................................................................................................... 67
1.18 Solved Questions ................................................................................................................. 69
1.19 Check Yourself ................................................................................................................... 109
2. COMBINATIONAL LOGIC 111189
2.1 Introduction ............................................................................................................ .............. 112
2.1.1 Design Procedure ............................................................................................................ . 112
2.1.2 Steps Used to Design a Combinational Logic Circuit .................................................... 112
2.1.3 Examples of Combinational Logic Circuits ............................................................... ..... 113
2.2 Binary Adder ....................................................................................................................... 115
2.2.1 Classification of Binary Adders ....................................................................................... 116
2.3 N-Bit Parallel Adder ............................................................................................................ 120
2.3.1 Drawback in Parallel Adder ............................................................................................. 120
2.4 Carry Look-Ahead Adder (CLA) ........................................................................................120
2.5 BCD Adder ......................................................................................................................... 123
2.5.1 Algorithm for BCD Addition and Verification ............................................................... 123
2.6 Binary Subtractor ............................................................................................................... 125
2.6.1 Types of Binary Subtractors ........................................................................................... 125
2.7 Binary Parallel Subtractor .................................................................................................. 128
2.7.1 Subtraction using 1s Complement ..................................................................................128
2.7.2 Subtraction using 2s Complement ..................................................................................129
2.7.3 By using I.C. .................................................................................................................. . 130
2.8 Binary 4-bit Parallel Adder-Subtractor .............................................................................. 130
2.9 Code Conversion ................................................................................................................ 131
2.9.1 Binary to Gray Code Converter ....................................................................................... 131
2.9.2 BCD to Excess-3 Code Converter ................................................................................... 131
2.10 Binary Multiplier ...............................................................................................................133
2.11 Magnitude Comparator ..................................................................................................... 135
2.11.1 1-bit Comparator ............................................................................................................ 135
2.11.2 2-bit Comparator ............................................................................................................ 136
2.11.3 4-bit Comparator ............................................................................................................ 138
2.12 Decoders ............................................................................................................................139
2.12.1 Decoder with dont Care Condition .............................................................................. 140
2.12.2 Decoders Expansion ...................................................................................................... 141

2.12.3 Application ...................................................................................................................... 142

2.12.4 Decoder with Complement Form .................................................................................... 144
2.13 Encoders ............................................................................................................................. 144
2.13.1 Octal to Binary Encoder .................................................................................................. 144
2.13.2 Priority Encoder ..................................................................................................... .......... 145
2.14 Multiplexers (Data Selector) ............................................................................................... 146
2.14.1 Applications of Multiplexers ........................................................................................... 148
2.14.2 Necessity of Multiplexers ............................................................................................... . 148
2.14.3 Advantage of Multiplexers ............................................................................................ .. 148
xvi Contents
2.14.4 Multiplexer Tree (Multiplexer Expansion) ..................................................................... 149
2.14.5 Boolean Function Implementation of Multiplexer ......................................................... 150
2.15 Demultiplexers .................................................................................................................. 154
2.15.1 Demultiplexer Tree ........................................................................................................ 155
2.15.2 Demultiplexer Applications ......................................................................................... . 157
2.16 University Questions ........................................................................................................ 157
2.16 Solved Examples .............................................................................................................. 159
2.18 Check Yourself .............................................................................................................. ... 188
3. SYNCHRONOUS SEQUENTIAL LOGIC 190317
3.1 Sequential Circuits ...................................................................................................................... 192
3.2 Comparison of Combinational and Sequential Circuits ............................................................. 192
3.3 Comparison Between Synchronous and Asynchronous Sequential Circuits ............................. 193
3.4 Storage Elements ........................................................................................................ ................. 193
3.5 Latches ........................................................................................................................................ 193
3.5.1 SR Latch using NOR Gates ..................................................................................................... 193
3.5.2 SR Latch using NAND Gates .................................................................................................. 195
3.6 Flip-flop ........................................................................................................................ .............. 196
3.6.1 Characteristics of Flip-Flop ..................................................................................................... 196
3.6.2 Clock Signal ............................................................................................................................ 196
3.6.3 Types of Flip-Flop ................................................................................................................... 197
3.7 Clocked S-R Flip-Flop ............................................................................................................... 197
3.7.1 Clocked SR Flip-flop Using NOR Gates ................................................................................ 198
3.8 J-K Flip-Flop ............................................................................................................................... 199
3.9 Limitation of J-K Flip-flop (Race Around Condition) ................................................................ 201
3.10 Master-slave J-K Flip-flop ........................................................................................................ 201
3.11 T-Flip-flop .................................................................................................................................202
3.12 D flip-flop ................................................................................................................................. 203
3.13 Characteristics Equations ..........................................................................................................203
3.14 Excitation tables for Flip-flops ................................................................................................. 205
3.15 Flip-flop Conversion ................................................................................................................ 206
3.15.1 S-R Flip-flop to J-K Flip-flop .............................................................................................. 207
3.15.2 S-R Flip-flop to T Flip-flop .................................................................................................. 209
3.15.3 S-R Flip-flop to D Flip-flop ................................................................................................. 210
3.15.4 T Flip-flop to D Flip-flop ..................................................................................................... 211
3.15.5 T Flip-flop to S-R Flip-flop .................................................................................................. 212
3.15.6 D Flip-flop to S-R Flip-flop ................................................................................................. 214
3.15.7 J-K Flip-flop to D Flip-flop .................................................................................................. 215
3.16 Analysis of Clocked Sequential Circuits ................................................................................. 216
3.16.1 State Table .................................................................................................................. ......... 216
3.16.2 State Diagram ........................................................................................................ ........... ...218
3.17 State Reduction and state Assignment ................................................................................... 219
3.17.1 State Reduction ................................................................................................................... 219
3.17.2 State Assignment ..................................................................................................... ........... 220
3.18 Design Procedure ................................................................................................................... 221
3.18.1 Design Using Unused States ...............................................................................................224

3.19 Registers ...................................................................................................................................... 227

3.20 Data Formats ........................................................................................................... .................... 227
3.21 Shift Register and its Classification ............................................................................................ 228
3.21.1 Serial In Serial Out (Shift Left Mode) ..................................................................................... 228
3.21.2 Serial In Serial Out (Shift Right Mode) .................................................................................. 230
3.21.3 Serial in Parallel Out (SIPO) .................................................................................................. 231
3.21.4 Parallel in Serial out (PISO) ........................................................................................ .......... 232
3.21.5 Parallel In Parallel Out (PIPO) ............................................................................................... 233
3.22 Bidirectional Shift Register ....................................................................................................... 233
3.23 Universal Shift Register ............................................................................................................234
3.24 Application of Shift Registers .................................................................................................. 235
3.24.1 Time Delay ........................................................................................................................... 235
3.24.2 Serial to Parallel Converter .................................................................................................. 236
3.24.3 Parallel to Serial Converter .................................................................................................. 236
3.24.4 Arithmetic Operation ................................................................................................. ........... 236
3.25 Counters ................................................................................................................................... 237
3.26 Classification of Counters ........................................................................................................ 237
3.27 Modulus of Counter ................................................................................................................. 238
3.28 Asynchronous or Ripple Counter (2 Bit up Counter) .............................................................. 238
3.28.1 3-Bit Asynchronous Counter or Mod-8 Counter .................................................................. 239
3.28.2 4-Bit Asynchronous Counter or MOD-16 Counter .............................................................. 241
3.29 Asynchronous Down Counter ................................................................................................. 242
3.29.1 Method-1 ......................................................................................................................... 242
3.29.2 Method-3 ......................................................................................................................... 2 43
3.30 UP/DOWN Ripple Counter ............................................................................................... 244
3.31 Modulus-Counter (MOD-m Counter) or Divide-By-N Ripple Counter ............................ 244
3.31.1 Design of Modulo-5 Ripple Counter ............................................................................... 245
3.31.2 Mod-10 Ripple Counter/Decade Counter/BCD Counter ................................................ 247
3.31.3 NAND Gate Inputs for MOD-m Counter ....................................................................... 249
3.32 Synchronous Counters ................................................................................................... ..... 249
3.32.1 2-Bit Synchronous Counter ............................................................................................. 250
3.32.2 3-Bit Synchronous Counter ............................................................................................. 252
3.32.3 4-Bit Synchronous Counter (UP) ..................................................................................... 253
3.33 Modulus-m Synchronous Counter ...................................................................................... 254
3.33.1 Mod-5 Synchronous Counter .......................................................................................... 255
3.33.2 MOD-10/Decade/BCD Synchronous Counter ................................................................ 256
3.34 UP/DOWN Synchronous Counter ..................................................................................... 259
3.35 Lock Out Condition ........................................................................................................... 261
3.35.1 Lock Free .................................................................................................. ....................... 261
3.36 Other Counters ......................................................................................................... .......... 264
3.36.1 Ring Counter ................................................................................................................... 264
3.36.2 Johnson Counter ...................................................................................................... ........ 265
3.37 Counter Applications .......................................................................................................... 268
3.38 Comparison of Asynchronous and Synchronous Counters ................................................ 268
3.39 Performance Comparison of Counters and Registers ......................................................... 268
3.40 University Questions ........................................................................................................... 269
3.41 Solved Questions ................................................................................................................. 271
3.42 Check Yourself .................................................................................................................... 316
4. MEMORY, PROGRAMMABLE LOGIC AND DESIGN AT RTL (ASM) 318396
4.1 Introduction of Memory and Programmable Logic ..................................................................... 319
4.2 Terminology in Memory ............................................................................................................. 319
4.3 Block Diagram of a Memory Device ........................................................................................ ... 320
4.4 Classification of Memories .......................................................................................................... 321
4.4.1 Classification Based on Principle of Operation .............................................................. ..322
4.4.2 Classification Based on Physical Characteristics ..................................................................... 323

4.4.3 Classification Based on Mode of Access ....................................................................... 324

4.4.4 Classification Based on Fabrication Technology ........................................................... 324
4.5 Random Access Memory (RAM) ...................................................................................... 324
4.5.1 Internal Organization of RAM ......................................................................................... 324
4.5.2 Write Operation ....................................................................................................... ......... 324
4.5.3 Read Operation ................................................................................................................ 326
4.5.4 Types of RAM .......................................................................................................... ........ 326
4.6 Static Ram (SRAM) ............................................................................................................ 326
4.6.1 TTL RAM Cell .......................................................................................................... ....... 327
4.6.2 MOS Static RAM ............................................................................................................. 328
4.7 Dyamic RAM (DRAM) ....................................................................................................... 328
4.7.1 Advantages and Disadvantages of DRAM ...................................................................... 329
4.7.2 Dynamic MOS RAM Cell ................................................................................................ 3 29
4.8 Comparison Between SRAM and DRAM .......................................................................... 330
4.9 NVRAM (Non-Volatile RAM) ........................................................................................... 330
4.10 Basic Construction of a Binary Cell .................................................................................. 331
4.11 Logic Construction of a 4 4 RAM ................................................................................. 332
4.12 Coincident Decoding ........................................................................................................ 332
4.13 Memory Expansion.............................................................................................................333
4.14 ROM (Read Only Memory) .............................................................................................. 336
4.14.1 Internal Construction of ROM ......................................................................................... 336
4.14.2 Programming the ROM ................................................................................................... 337
4.14.3 Illustrate MOS ROM Cell ............................................................................................... 338
4.14.4 Combinational Logic Circuit Implementation Using ROM ........................................... 338
4.14.5 Types of ROMs ........................................................................................................ ........ 341
4.15 Flash Memory .......................................................................................................................345
4.16 Programmable Logic Devices (PLD) .................................................................................. 345
4.16.1 PROM (Programmable Read Only Memory) ................................................................... 346
4.16.2 Programmable Logic Array (PLA) ................................................................................... 349
4.16.3 Programmable Array Logic (PAL) ................................................................................... 353
4.17 Comparision Between PROM, PLA and PAL ..................................................................... 356
4.18 Advantages of PLDs ............................................................................................................. 356
4.19 Design at the Register Transfer Level (RTL) ............................................................................... 356
4.19.1 Basic Operation of Register ...................................................................................................... 357
4.19.2 Register Transfer Operation with Conditional Statement ................................................... ..... 357
4.20 Algorithmic State Machine (ASM) .............................................................................................. 358
4.20.1 Basic Elements of Chart ....................................................................................................... .. 358
4.20.2 ASM Block .......................................................................................................................... .... 359
4.20.3 ASM chart for Sequential Circuit Design .......................................................................... .... 365
4.21 Design with Multiplexers ............................................................................................... ...... ....... 369
4.22 University Questions ............................................................................................................ ....... 375
4.23 Solved Questions ....................................................................................................... ........... ....... 376
4.24 Check Yourself ...................................................................................................................... ...... 395
5. ASYNCHRONOUS SEQUENTIAL LOGIC AND HAZARDS 397457
5.1 Introduction ...................................................................................................................... 398
5.1.1 Comparison Between Synchronous and Asynchronous-Sequential Circuits ................. 399
5.1.2 Application of Asynchronous Sequential Circuits .......................................................... 399
5.1.3 Advantages and Disadvantages of Asynchronous Sequential Circuits .......................... 399
5.2 Modes of Asynchronous Sequential Systems .................................................................... 400
5.3 General Design Procedure for Asynchronous Sequential Circuits ................................... 401
5.4 Analysis Procedure of Asynchronous Sequential Circuits ............................................... 401
5.4.1 Transition Table ............................................................................................................... 401
5.4.2 Flow Table ....................................................................................................................... 404
5.5 Race Conditions ................................................................................................................... 406
5.5.1 Types of Races ........................................................................................................ ......... 406

5.5.2 How to Avoid Races .................................................................................................... .... 407

5.6 Stability Consideration ....................................................................................................... 408
5.7 Circuit With Latches .................................................................................................... ....... 409
5.7.1 SR Latch Using NOR Gates ............................................................................................. 409
5.7.2 SR Latch Using NAND Gates ......................................................................................... 411
5.7.3 Analysis of Asynchronous Sequential Circuits with Latches ......................................... 412
5.7.4 Latch Excitation Table .................................................................................................... 413
5.7.5 Debounce Circuit ............................................................................................................. 416
5.8 Design Procedure ........................................................................................................ .........416
5.8.1 Design Example ............................................................................................................... 417
5.9 Reduction of States and Flow Tables ................................................................................. 422
5.9.1 Implication Table ............................................................................................................. 422
5.9.2 Merging of the Primitive Flow Table .............................................................................. 424
5.10 Race-Free State Assignment ............................................................................................. 428
5.11 Hazards ................................................................................................................ ............... 431
5.11.1 Hazards in Combinational Circuits ................................................................................. 432
5.11.2 Types of Hazards ............................................................................................................ 432
5.11.3 Hazard Detection ............................................................................................................. 433
5.11.4 Hazard Elimination .......................................................................................................... 434
5.11.5 Conditions for Static Hazard ........................................................................................... 434
5.12 Hazards in Sequential Circuits ........................................................................................... 434
5.12.1 Implementation with SR Latch ........................................................................................ 435
5.13 Essential Hazards ...................................................................................................... .......... 436
5.14 University Questions ........................................................................................................... 441
5.15 Solved Questions .................................................................................................................443
5.16 Check Yourself ................................................................................................................... 456
APPENDICES
UNIVERSITY EXAMINATION PAPERS

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