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Freescale Semiconductor, Inc.

DOCUMENT NUMBER 9S12DJ64DGV1/D

MC9S12DJ64 Device User Guide V01.19 Covers also
Freescale Semiconductor, Inc...

MC9S12D64, MC9S12A64, MC9S12D32, MC9S12A32

Original Release Date: 19 Nov. 2001 Revised: 2 September 2004

Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

1 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc.

Revision History

Version Revision Effective Number Date Date
V01.00 16 NOV 2001 18 FEB 2002 19 NOV 2001 18 FEB 2002

Author

Description of Changes
Initial version based on MC9SDP256-2.09 Version. In table 7 I/O Characteristics" of the electrical characteristics replaced tPULSE with tpign and tpval in lines "Port ... Interrupt Input Pulse filtered" and "Port ... Interrupt Input Pulse passed" respectively. Table "Oscillator Characteristics": removed "Oscillator start-up time from POR or STOP" row Table "5V I/O Characteristics": Updated Partial Drive IOH = +–2mA and Full Drive IOH = –10mA Table "ATD Operating Characteristics": Distinguish IREFfor 1 and 2 ATD blocks on Table "ATD Electrical Characteristics": Update CINS to 22 pF Table "Operating Conditions": Changed VDD and VDDPLL to 2.35 V (min) Removed Document number except from Cover Sheet Updated Table "Document References" Table "5V I/O Characteristics" : Corrected Input Capacitance to 6pF Section: "Device Pinout" (112-pin and 80-pin): added in diagrams RXCAN0 to PJ6 and TXCAN0 to PJ7 Table "PLL Characteristics": Updated parameters K1 and f1 Figure "Basic PLL functional diagram": Inserted XFC pin in diagram Enhanced section "XFC Component Selection" Added to Sections ATD, ECT and PWM: freeze mode = active BDM mode Added 1L86D to Table "Assigned Part ID numbers" Corrected MEMSIZ1 value in Table "Memory size registers" Subsection "Device Memory Map: Removed Flash mapping from $0000 to $3FFF. Table "Signal Properties": Added column "Internal Pull Resistor". Preface Table "Document References": Changed to full naming for each block. Table "Interrupt Vector Locations", Column "Local Enable": Corrected several register and bit names. Figure "Recommended PCB Layout for 80QFP: Corrected VREGEN pin position Thermal values for junction to board and package BGND pin pull-up Part Order Information Global Register Table Chip Configuration Summary Modified mode of Operations chapter Section "Printed Circuit Board Layout Proposals": added Pierce Oscillator examples for 112LQFP and 80QFP

V01.01

Freescale Semiconductor, Inc...

V01.02

6 MAR 2002

6 MAR 2002

V01.03

4 June 2002

4 June 2002

V01.04

4 July 2002

4 July 2002

V01.05

30 July 2002

30 July 2002

For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. MC9S12DJ64 Device User Guide — V01.19

Version Revision Effective Number Date Date
V01.06 20 Aug. 2002 20 Aug. 2002

Author

Description of Changes
NVM electricals updated Subsection "Detailed Register Map: Address corrections Preface, Table "Document references": added OSC User Guide New section "Oscillator (OSC) Block Description" Electrical Characteristics: -> Section "General": removed preliminary disclaimer ->Table "Supply Current Characteristics": changed max Run IDD from 65mA to 50mA changes max Wait IDD from 40mA to 30mA changed max Stop IDD from 50uA to 100uA Section HCS12 Core Block Description: mentioned alternate clock of BDM to be equivalent to oscillator clock Table "5V I/O Characteristics": Corrected Input Leakage Current to +/- 1 uA Section "Part ID assignment": Located on start of next page for better readability Added MC9S12A64 derivative to cover sheet and "Derivative Differences" Table Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz Renamed "Preface" section to "Derivative Differences and Document references". Added details for derivatives missing CAN0 and/or BDLC Table "ESD and Latch-up Test Conditions": changed pulse numbers from 3 to 1 Table "ESD and Latch-Up Protection Characteristics": changed parameter classification from C to T Table "5V I/O Characteristics": removed foot note from "Input Leakage Current" Table " Supply Current Characteristics": updated Stop and Pseudo Stop currents Subsection "Detailed Register Map": Corrected several entries Subsection "Unsecuring the Microcontroller": Added more details Table "Operating Conditions": improved footnote 1 wording, applied footnote 1 to PLL Supply Voltage. Tables "SPI Master/Slave Mode Timing Characteristics: Corrected Operating Frequency Appendix ’NVM, Flash and EEPROM’: Replaced ’burst programming’ by ’row programming Table "Operating Conditions": corrected minimum bus frequency to 0.25MHz Section "Feature List": ECT features changed to "Four pulse accumulators ..." Replaced references to HCS12 Core Guide by the individual HCS12 Block guides Table "Signal Properties" corrected pull resistor reset state for PE7 and PE4-PE2. Table "Absolute Maximum Ratings" corrected footnote on clamp of TEST pin. Added cycle definition to "CPU 12 Block Description". Added register reset values to MMC and MEBI block descriptions. Diagram "Clock Connections": Connect Bus Clock to HCS12 Core

V01.07

20 Sept. 2002

20 Sept. 2002

Freescale Semiconductor, Inc...

V01.08

25 Sept. 2002

25 Sept. 2002

V01.09

10 Oct. 2002

10 Oct. 2002

V01.10

8 Nov. 2002

8 Nov. 2002

V01.11

24 Jan. 2003

24 Jan. 2003

V01.12

31 Mar. 2003

31 Mar. 2003

V01.13

20 May 2003

20 May 2003

V01.14

10 June 2003

10 June 2003

3 For More Information On This Product, Go to: www.freescale.com

75*VDDPLL item 14 VIL.19 22 July 2003 24 Feb.15 V01.Freescale MC9S12DJ64 Device User Guide — V01. 2004 22 July 2003 24 Feb. Inc. Version Revision Effective Number Date Date V01.com .. 4 For More Information On This Product. Added MC9S12D32 and MC9S12A32 Appendix.freescale.3*VDDPLL to 0..EXTAL min value from 0. Inc.7*VDDPLL to 0.18 V01.EXTAL max value from 0.17 V01. 2004 21 May 2004 13 July 2004 2 Sept.16 V01. Table "Oscillator Characteristics": changed item 13 VIH. 2004 21 May 2004 13 July 2004 2 Sept.19 Semiconductor. 2004 Author Description of Changes Mentioned "S12 LRAE" bootloader in Flash section Section Document References: corrected S12 CPU document reference Added 3L86D maskset with corresponding Part ID Table Oscillator Characteristics: Added more details for EXTAL pin Added 4L86D maskset with corresponding Part ID Table "MC9S12DJ64 Memory Map out of Reset": corrected $1000 $3fff memory in single chip modes to "unimplemented".25*VDDPLL Freescale Semiconductor. Go to: www.

. . . . . .2 Signal Properties Summary .53 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2. . . . . .3. . .2 RESET — External Reset Pin . . . . . . . . . . . . . . .25 Detailed Register Map . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . and Mode Pin . .1 EXTAL. . . . . . . . . . . . . .19 PE1 / IRQ — Port E Input Pin 1 . . .59 2. . . . . . . . . . . . . . . . . . . . . XTAL — Oscillator Pins . . . . . . . .59 2. .57 2. . . .14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . .3. . . . . . . . . . . . Inc. . . . . . . . . . .3. . . . . . . . . . . . . . .59 2. . . . . . . . . .3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . .51 2.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . .56 2. . . . . . . . . . . . . . .8 PAD[14:08] / AN[14:08] — Port AD Input Pins ATD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2. . . . . . . . . . . . .19 Features . . . . . .. . . .19 Modes of Operation .59 5 For More Information On This Product. . . . . . . . . . . . . . . . . .3. . . . . .3 1. .6 BKGD / TAGHI / MODC — Background Debug. . . . . . . . . . . . .2 1. . . . . . . . . . . . . . . . . . . . . . . . . . .59 2. . . . . . . . . . . . . . . . . .56 2. . . . . . Go to: www. . . .17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . .5. . . . . . . . . . . . . .10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . . . . . .3. .57 2. .3. . . . . . . . . . . . .3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . .6 Overview. . . . . . . .3. . . . . .11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . .49 Freescale Semiconductor. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2. . .16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . .3. . . .18 PE2 / R/W — Port E I/O Pin 2 . . . .4 1. . . . . . . . . . .1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . Section 2 Signal Description 2. . . . . . . .4 VREGEN — Voltage Regulator Enable Pin .3. . .9 PAD07 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . .21 Block Diagram . .30 Part ID Assignments. . .3. .57 2. . .3. . . . . . . . .7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Device Pinout . . . . . . . . . . . . . . . . . . . . .57 2. . . . . . . .3. . . . . . . . . . . . .56 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2. . . . . Inc. . . . . . . . . . . . . . .3. .56 2. . . . .56 2. . . . . . . . . .3. . . . . . . . . . . . . . . . . . . .3. .1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. .Freescale Semiconductor. . . . . . . . . . . . MC9S12DJ64 Device User Guide — V01. . . . . . . . . . .3 TEST — Test Pin . . . . . . . . . . . . . . . . . . .5 XFC — PLL Loop Filter Pin . . . . . . . .19 Table of Contents Section 1 Introduction 1. . . . .59 2.57 2. . . . . . . .3. . . . . . . .22 Device Memory Map. . . . . . . . . . .3. . . . . . . . . . . . . . . . . . Tag High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .freescale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .com . . . . . . . . . . . . . . . .

. . .3. . . . .61 PM3 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . .62 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . .60 PH2 / KWH2 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . .3.63 PS2 / RXD1 — Port S I/O Pin 2 . . .30 2. . . . . . . .23 2. . . . . . . . . . . . 6 For More Information On This Product. . . . . . . . . . . . . . . . . . .63 PP1 / KWP1 / PWM1 — Port P I/O Pin 1. . . . . . . Inc. . . . .61 PM7 — Port M I/O Pin 7. . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . .38 2. . .60 PJ7 / KWJ7 / SCL / TXCAN0 — PORT J I/O Pin 7 . . . .32 2. . . .3. . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . .55 2. . . . . . . .3. . . . . . . . . . . . . .3. . . .3. . . . . . . .25 2. . . . . . . . . . . . . . . . .63 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . .37 2. . . . . .3. . .29 2. . . . . . . . . . . . . . . . . . . . .3. . .53 2. . . . . . . . . . . . . . . .63 PS6 / SCK0 — Port S I/O Pin 6 . . . . . .61 PM4 / RXCAN0 / MOSI0 — Port M I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2. .60 PH0 / KWH0 — Port H I/O Pin 0 . . .3. . . . . . . . . . . . . . . . . . . . . . . .43 2. . .. . . .44 2. . .51 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2. . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . .49 2. . . . . . .36 2. . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . .3.60 PJ6 / KWJ6 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . .freescale.3. . .62 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2. . . . . .3. . . .28 2. . . . . .62 PP3 / KWP3 / PWM3 — Port P I/O Pin 3. . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2. .64 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . .64 Freescale Semiconductor. . . .61 PM5 / TXCAN0 / SCK0 — Port M I/O Pin 5 . . . . . . .3. . . . . . . .41 2. . . . . . . . . . . . .60 PH1 / KWH1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . .3. . . . . . . . . .59 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . .3.63 PP0 / KWP0 / PWM0 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . .39 2. . . . . . . . . . .45 2. . .19 2.60 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . .3. . . . . . . . . . . . . . . . . .61 PK7 / ECS / ROMCTL — Port K I/O Pin 7 . . . . .33 2. . .46 2. . . . . .63 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . .21 2. . . . . . . . . . . .27 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PP2 / KWP2 / PWM2 — Port P I/O Pin 2. . . . . .50 2. .62 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . .42 2. . . . . .. . . . . . . . . . .3. . . . . . . . .52 2. . . . . . . . . . . . . Go to: www. . . . . . . . . . .3. . . . . . .3. . . .60 PH3 / KWH3 — Port H I/O Pin 3 . . . . .60 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . .3. . . . . . . . . . .22 2. . . . . . . .61 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . .com . . . . .62 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . .34 2. . PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . .62 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . .3.3.3. . . .24 2. . . . . . . . . . . . . . . . . . . . . . . .Freescale MC9S12DJ64 Device User Guide — V01. . . .31 2. .61 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . .26 2. . . . . . . . . . . . . . . . .63 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . . . . . .62 PM2 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . . . . . . . . . .3. . . . . .63 PS7 / SS0 — Port S I/O Pin 7 . . . . . .48 2. . . . . . .3.61 PM6 — Port M I/O Pin 6. . . . . . . .62 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . .56 Semiconductor. . . . .

. . . .4. . . . . . . . . . . . . . . . . . . . . . .3. . . . .2 Memory . . . . . . . . . . . . . . . . .64 2. . . . . . .3 4. . . . . . . . . . . Section 3 System Clock Description 3. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .69 Security. . . . . . . . . . . . . . .65 2. . . . . . . . . . . . . . . . . . . . . . . Go to: www. . . .3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Wait . . . . . . . . . . VSSA — Power Supply Pins for ATD0/ATD1 and VREG . . .64 2. . . . . . . . . . .69 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Freescale Semiconductor. . . . . . . .2. . . . .4. . . .75 Section 6 HCS12 Core Block Description 7 For More Information On This Product. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . . . . . . .1 Overview. .73 5. . . . . . . . . . . . . . . . . . .71 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2. . . . . . . . .3. . . . . . . . . . . . . . . .3 4. . . . . . . .4. . . . . . VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 65 2. . . . . . . . . . . . . . . . . . . . . . . . . . . VRL — ATD Reference Voltage Input Pins .73 5. . . . . . . . . . . . . . . . . . .1 Vector Table. . . . . . . . . . . . .1 4. . . . . . . .1 Overview. . . . .2 4. . . . . . . . . . . . . . . . . . . . . . . . . . VSS2 — Internal Logic Power Supply Pins . . . . . VSSPLL — Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Operation of the Secured Microcontroller . . . . . . . . .19 2.4 4. .4. . . . . . . . .2 4. . . . . . . . . . . . . . . . . . . . . .4. . . . .65 2.71 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . .4 VDDA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Power Supply Pins . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 4. . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . . . . . . .73 5. . . . . . . . . . . . . . . VDD2. . . . . . . . . . . . . . .1 VDDX. . . . . . . .3. . . . . . . . .74 5. . . . . . . . . . . . . . . . .freescale. . . . .com . . . . . .4. . . . . . . . . .3. . . . . . . . . . .65 2.67 Section 4 Modes of Operation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 VDDPLL. . . . . . . . . . . . . . . . . .70 Unsecuring the Microcontroller .3. . . . . . . . .4. . . . .3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . .74 5. . . . . . . . . . . . . . . . Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS1.3. . .4 Overview. . . . .71 Run. . . . . . . . .57 PS0 / RXD0 — Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2. . . . . . .7 VREGEN — On Chip Voltage Regulator Enable . . . . . . . . . . . . .3 4. . . . . . . . . .2 VDDR. . . . . . . . . . . . . . . .2 4. . . . . . . . . . . . . . Inc. . . . . . .2 Vectors . .72 Section 5 Resets and Interrupts 5. . . . . .3 VDD1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2. . . . . . . . . . . . . . . . . . . . . . . .70 Securing the Microcontroller . . . . . . . . . . . . . . . . .1 4. . .4. . .58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . .71 Pseudo Stop. . . . . .5 VRH. MC9S12DJ64 Device User Guide — V01. . . . .Freescale Semiconductor.

.1 6. . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Device-specific information . .1 Device-specific information. . . . . . . . . . . . .1 6.3 6. . . . . . . . . . . . . . . . . . . . .77 HCS12 Module Mapping Control (MMC) Block Description . . . .77 HCS12 Interrupt (INT) Block Description . . . Inc. . . . . . . . .77 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . .5. . . . . . . . . . . . . . . . . . . . . . . . . .78 HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . .5 6. .78 Freescale Semiconductor. . .2 6. . . . . . . . . . . . .freescale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . .. . . . . . . . . . .com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .78 Device-specific information . . . . . .4 6.1. . . . . . . . . .6 Semiconductor. . . . . . . . . . . . . . . . . . . . . . . . . .77 Device-specific information . . . . .78 HCS12 Breakpoint (BKP) Block Description . . . . CPU12 Block Description .78 Section 9 Enhanced Capture Timer (ECT) Block Description Section 10 Analog to Digital Converter (ATD) Block Description Section 11 Inter-IC Bus (IIC) Block Description Section 12 Serial Communications Interface (SCI) Block Description Section 13 Serial Peripheral Interface (SPI) Block Description Section 14 J1850 (BDLC) Block Description Section 15 Pulse Width Modulator (PWM) Block Description Section 16 Flash EEPROM 64K Block Description Section 17 EEPROM 1K Block Description Section 18 RAM Block Description Section 19 MSCAN Block Description 8 For More Information On This Product. . . . . . . . . . . . . . .77 Device-specific information . . . . .78 Section 8 Oscillator (OSC) Block Description 8. . . . . . . . . . . . . . . . . .1 6. . . . . . . . . . .Freescale MC9S12DJ64 Device User Guide — V01. . . . .1 6. Section 7 Clock and Reset Generator (CRG) Block Description 7. . . . . . . . .3. . . . . . . . . . . Go to: www. . . . . .1 6. . . . . . . . . .1 Device-specific information. . . . . . . . . .

. . . . . . . . . .115 A. . . . .1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . .90 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..5 Absolute Maximum Ratings . . . . . .2 Oscillator . . . . . . .108 A. . . . . . . . . . . . .93 A. . . . . . .94 A. . . . . . . . . . . . . . .1 Master Mode . . .7. . . . . . . . . . . . . . . . . . . Flash and EEPROM .6 ESD Protection and Latch-up Immunity .87 A. . . . . . . . . . . . . . . . . . .87 A. . . . . . . . . . . .91 A. . . . . . . . . . .1 NVM timing. .3 Pins . . . . . . . . . . . .9 I/O Characteristics . . .88 A. . . . . . . . . . .19 Section 20 Port Integration Module (PIM) Block Description Section 21 Voltage Regulator (VREG) Block Description Section 22 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics A. . . . . . . .119 A. . . . . . . . . . . . . . . . . . . . . . . . . .105 A. . . . MC9S12DJ64 Device User Guide — V01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . .113 A. . . . . . . . . .1 General Muxed Bus Timing . .5. . . . . . . . . . . . .115 A. . . . . . . . . . .119 Freescale Semiconductor. . . . . . . . .2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . .107 A. .99 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. .8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 ATD Characteristics . .2 Power Supply . . . . . . . . . . . . . . . . . . . .97 A. . . . . . . . . .10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . .107 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . .2. .97 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A. . . . . . . .97 A. . . . . . . .2. . . . . . . . . . . . . . . .88 A. . . . . . . . . .7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Current Injection. . . . . . . . . . . . . . . . . . . . . .2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . .3 ATD accuracy. .freescale. . . . . . . . . . . . . . . . . . . . .7 Operating Conditions . . . . . . . . . .7. . . . . . . . . .87 A. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . Go to: www. . . . .1 Parameter Classification . . . . . . . . . . . . . . . . . . . . .1. . . . .3. . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . .1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 NVM. . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . .5. . . . .109 A. . Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3. . . . . . .2 NVM Reliability. . . . .6 MSCAN. .103 A. . . .101 A. . . . . . . . . . . . . . . . . . . . Inc.8. . . . . . . .com . . . . . . . . . . . . . . . . . . . .8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Voltage Regulator. . . . . . . . . . .1 Startup . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . .Freescale Semiconductor. .90 A. .5 Reset. . . . . . . . . . . . . . . . . . . . . .5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . .117 A. . . . . . . . . . . . . . . . . . . .101 A. . . . . . 9 For More Information On This Product.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . .123 112-pin LQFP package. . . . . .19 Appendix B Package Information B. . . . . . . . . . . . . . . . . . . . . 10 For More Information On This Product. . . . .1 B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inc. . . . . . . . .125 Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01. . . . . . . . . . Inc. . . . . . . . . . . .3 Semiconductor. . . .. . . . . .124 80-pin QFP package. .com . . . . . . . .. . . . . . . . . . . .freescale. . . . General. . . . . . . . . . . . . . . .2 B. . . . . . . Go to: www. . . . .

. . . . . . . 109 Jitter Definitions . . . . . . . . . . .Freescale Semiconductor.27 MC9S12D32 Memory Map out of Reset . . . . . . . . . . . . . . . 987) . . . . Go to: www. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Recommended PCB Layout for 80QFP Pierce Oscillator . . . . . . . . . . 117 General External Bus Timing. . . . . . 111 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SPI Master Timing (CPHA = 0) . . . . . .com . . . . . . . . . . . .freescale. .83 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . .15 MC9S12DJ64 Block Diagram . . . . . . . . . . . . . . . . . . 841B) . . . . . . . . . . . . . . . . . . . . . . . . . . .58 External Clock Connections (PE7=0) . . . . . . . . . . . . .23 MC9S12DJ64 Memory Map out of Reset . . . . . . . . . Inc. . . . . . . . . .52 Pin Assignments in 80-pin QFP for MC9S12DJ64 and MC9S12D32 . . . . . . . .58 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . 125 Freescale Semiconductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 For More Information On This Product. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .56 Colpitts Oscillator Connections (PE7=1) . . . MC9S12DJ64 Device User Guide — V01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 PLL Loop Filter Connections .67 Recommended PCB Layout 112LQFP Colpitts Oscillator. . 120 112-pin LQFP mechanical dimensions (case no. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Pin Assignments in 112-pin LQFP for MC9S12DJ64 . . . . . . 124 80-pin QFP Mechanical Dimensions (case no. . . . . . . . . . . . . . . . . . . . . . .82 Recommended PCB Layout for 80QFP Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . 116 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . 100 Basic PLL functional diagram . . . . . . . . . . . .19 List of Figures Figure 0-1 Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 3-1 Figure 22-1 Figure 22-2 Figure 22-3 Figure 22-4 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure B-1 Figure B-2 Order Partnumber Example. . . .58 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19 Semiconductor. Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01. Inc.. 12 For More Information On This Product.com . Go to: www.freescale. Inc..

...........$0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ......$010F Flash Control Register (fts64k) . .. ..................... ...42 $0120 ... ..... .... .. ............ .... ...... .............. ............. ..... .......... .. ..... ....$011B EEPROM Control Register (eets1k) ..... .. ....32 $0028 ..42 $011C .... ... ................39 $00D0 .... ....... .... ..............$001D MMC map 3 of 4 (HCS12 Module Mapping Control.. .... ..46 Freescale Semiconductor........17 Table 1-1 Device Memory Map for MC9S12DJ64 . ..... ...30 $0010 .......$00D7 SCI1 (Asynchronous Serial Interface) ..... .....................$001F INT map 2 of 2 (HCS12 Interrupt) ...$002F BKP (HCS12 Breakpoint) ........ ........ ... .. .. .....$0016 INT map 1 of 2 (HCS12 Interrupt) .... ......32 $0034 . ................ ... .. ...19 List of Tables Table 0-1 Derivative Differences ........................................32 $0030 ........... .......... .......... .... . ... ...33 $0040 ......40 $00E8 . ..........$00CF SCI0 (Asynchronous Serial Interface) .... .................32 $0032 .31 $001E ...... .37 $00C8 ..... Table 1-5) ........... ...$013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) .......... 13 For More Information On This Product..... . . ...... ............ ......................... ......freescale......36 $00A0 .......$00FF Reserved .... ... ........ ...$0019 Reserved ... ......... .... ......... ........ . ...$000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) . .......... .... . ... ............. ............ ... .... .. .. .......... ................. ................ .$00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) .....31 $001C ..................... . ... ........ Go to: www..... Inc............. .Freescale Semiconductor.................................... .... ........$007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) ............................... ........... ......... ........41 $00F0 ................... ...... .....25 Table 1-2 Device Memory Map for MC9S12D32 ....30 $0015 ...... ... ................ .. ................... ......... . ..32 $0020 . ... ...$003F CRG (Clock and Reset Generator) .... ...... .......$00DF SPI0 (Serial Peripheral Interface) .. ..... .........41 $0100 .....$009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ..com .. ....................... ........... ...31 $001F ............. ... ................... ........39 $00D8 .. ..$001B Device ID Register (Table 1-4) .......... .......... ..... .. ..................................$001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) ........$011F Reserved for RAM Control Register ............... ...$017F CAN0 (Motorola Scalable CAN . ............. ....... ...... ...... ........ .$023F Reserved . .44 Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout ......31 $001A .................$0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ....28 $0000 .. .... ................31 $0017 ........ . . ............ ........... ............ ....$00E7 IIC (Inter IC Bus) .... ....................... .......... .... ............... ....... Inc. ..15 Table 0-2 Document References .... MC9S12DJ64 Device User Guide — V01................. ................................ .................... ...... ..... . .......... .......40 $00E0 .. ..43 $0140 ..... .$0027 Reserved ...................... .. ...................... ....... ..$00EF BDLC (Bytelevel Data Link Controller J1850) .....MSCAN) ........... .........41 $0110 .....45 $0180 .. .... .... .. .... .. ... ........ ........... .......... ........ .$0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) ........................... .... ...33 $0080 ... ... ....... ...

. .69 Table 4-3 Voltage Regulator VREGEN .. .. . .. . . . . .. . . . . . . . . . . . . .. . . . . . . . .. . . . . . .. . . .com .. . .99 Table A-11 NVM Timing Characteristics .. . .. . .64 Table 4-1 Mode Selection . . . . . . . . . . . . .. . . . .. .49 Table 1-5 Memory size registers . .. . . . . . . . . . . . . . . . .108 Table A-16 PLL Characteristics . . . .. . . . . . . . . . . . . . . . . . . . . .. . .. . . ... .. .. . . . . . . . . 14 For More Information On This Product. . . . .116 Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ...freescale. . . . .. . . . . . . . . .. . . . .. . . . . . . . .. .... . . . . . . . .105 Table A-14 Startup Characteristics. . . . . ... . . . . . . . . . . . . .. .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . .54 Table 2-2 MC9S12DJ64 Power and Ground Connection Summary . . . . ..48 Table 1-4 Assigned Part ID Numbers . . . . . . . . . . .. . . . .. . . . . . . .. . . .. . . .46 $0280 . . . . . . . . . . . . . . .. . . . . .. . . .118 Table A-20 Expanded Bus Timing Characteristics . . .. .. . .. . . .. . . . .69 Table 4-2 Clock Selection Based on PE7 . .. . . . . . .90 Table A-4 Operating Conditions . . . .. . . . .. . . . . . . . . . . .. . . . . . .$03FF Reserved . . . . . . .. . . . . . . . . .. .113 Table A-18 SPI Master Mode Timing Characteristics. . .. . . . . .. . . .. . . . . . . . .73 Table 22-1 Suggested External Component Values . . . . . . . .. . . . . . .. . .98 Table A-10 ATD Conversion Performance .. . . . . . .. . . ..94 Table A-7 Supply Current Characteristics . . . . ..90 Table A-3 ESD and Latch-Up Protection Characteristics . . . . . . ... . . . . . .. . . . . . . . .. . . ... . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . ..Freescale MC9S12DJ64 Device User Guide — V01.. . . . .. . . . . .. . . . . . .. . . . . . . . . Inc. . . . . . . . . . . . . . . .. . . . . . ... .. . . . . . . . . . . . . . . . . . . . . . . .. .. . . .$027F PIM (Port Integration Module) . . . .. .. .. . . . . .. . . . . . . . . . . . .. .70 Table 5-1 Interrupt Vector Locations . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . ... . . . . . . . . . . . .. Inc. . . . . . . . . . . . . .. . . . . . .112 Table A-17 MSCAN Wake-up Pulse Characteristics.. . . .. .. . . .. . . . . . . . . . . .. ... . . . .97 Table A-9 ATD Electrical Characteristics . . . .. . . . . . . . . . . . . . . . .. . . . . . .... . . ... . . . . .. . . . . . . . . .. . . Go to: www. . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . ... . . . . . .. . . .. . . . . . . . .. . .. . . . .. .. . .107 Table A-15 Oscillator Characteristics . . . . . . .. . . . . . . . . . . . . . . . .. . .. . .. . . . . . . . . . .. . . .91 Table A-5 Thermal Package Characteristics . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . . .. . .. . . . .. . . . . . . . . . . .. . ... . . . . . . . . . .. ...19 Semiconductor. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Table A-6 5V I/O Characteristics .. .. .. . . . . . . . . . . . . .. . . . . .. . . .. . . ... . . . . . . .. . . . . . .. . . . . . . .89 Table A-2 ESD and Latch-up Test Conditions .. . . . . . .. . . . . .. . .. . . . . . . . . . . . .. .95 Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . .. . .. . . . . . . . .81 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . .. . . . .102 Table A-12 NVM Reliability Characteristics.. .. . . . . .121 Freescale Semiconductor. .. . . . . . . . . . . . .. . . . . $0240 . . . . . .. .103 Table A-13 Voltage Regulator Recommended Load Capacitances . . . .. .49 Table 2-1 Signal Properties . . . .

V. C PV. Fill the BDLC interrupt vector ($FFC2.$00EF). Inc. Inc. $FFC3) according to your coding policies for unused interrupts. V.$017F). Do not write or read BDLC registers (after reset: address range $00E8 . • Registers – – • Do not write or read CAN0 registers (after reset: address range $0140 . MC9S12DJ64 Device User Guide — V01. 80QFP L86D C PV. V. if using a derivative without BDLC (see Table 0-1).Freescale Semiconductor. FU An errata exists contact Sales office MC9S12D32 1 0 80QFP L86D M. Mask Set Temp Options Package Codes Note MC9S12 DJ64 C FU Package Option Temperature Option Device Title Controller Family Temperature Options C = -40˚C to 85˚C V = -40˚C to 105˚C M = -40˚C to 125˚C Package Options FU = 80QFP PV = 112LQFP Figure 0-1 Order Partnumber Example The following items should be considered when using a derivative. Interrupts – – 15 For More Information On This Product.19 Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. Go to: www. if using a derivative without BDLC (see Table 0-1). Table 0-1 Derivative Differences Generic device CAN0 J1850/BDLC Packages MC9S12DJ64 1 1 112LQFP.$FFB7) according to your coding policies for unused interrupts. FU An errata exists contact Sales office MC9S12A64 0 0 112LQFP. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. if using a derivative without CAN0 (see Table 0-1). 80QFP L86D M. C PV. if using a derivative without CAN0 (see Table 0-1).com . 80QFP L86D M. FU An errata exists contact Sales office MC9S12D64 1 0 112LQFP... Fill the four CAN0 interrupt vectors ($FFB0 . C FU An errata exists contact Sales office MC9S12A32 0 0 80QFP L86D C FU An errata exists contact Sales office Freescale Semiconductor.freescale.

Inc. The CAN0 pin functionality (TXCAN0. PM1 and PM0. PM4. Bit 7 = PUKE = 1 in the register PUCR at Base+$000C. if using a derivative without CAN0 (see Table 0-1). if using a derivative without BDLC (see Table 0-1). Therefore care must be taken not to disable the pull enables on PJ[1:0] by clearing the bits PERJ1 and PERJ0 at Base+$026C. Therefor care must be taken not to clear this bit. PM5. Do not modify the ATD1 registers! Pins not available in 80 pin QFP package – Freescale Semiconductor. RXB) is not available on port PM1 and PM0. The BDLC pin functionality (TXB.19 • Ports – – – • Semiconductor. Inc. special implementation details of the module are given in the block description sections of this document. – – – – – – Document References The Device User Guide provides information about the MC9S12DJ64 device made up of standard HCS12 blocks and the HCS12 processor core. Port K Port K pull-up resistors are enabled out of reset.. if using a derivative without CAN0 (see Table 0-1). In a effort to reduce redundancy all module specific information is located only in the respective Block Guide. Port S[7:4] PS7:4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs.Freescale MC9S12DJ64 Device User Guide — V01. PJ6. Port H In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register (DDRH at Base+$0262) to $FF. i. Do not write MODRR1 and MODRR0 Bit of Module Routing Register (PIM_9DJ64 Block User Guide). RXCAN0) is not available on port PJ7. A complete set of device manuals also includes all the individual Block Guides of the implemented modules. Port M[7:6] PM7:6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs..e. 16 For More Information On This Product.com . PM3. Port J[1:0] Port J pull-up resistors are enabled out of reset on all four pins (7:6 and 1:0). Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input. See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide. PAD[15:8] (ATD1 channels) Out of reset the ATD1 is disabled preventing current flows in the pins. This document is part of the customer documentation. If applicable. PM2. Go to: www.freescale. or enabling the pull resistors by writing a $FF to the pull enable register (PERH at Base+$0264).

. Asynchronous Serial Interface (SCI) Block User Guide Serial Peripheral Interface (SPI) Block User Guide Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block User Guide 64K Byte Flash (FTS64K) Block User Guide 1K Byte EEPROM (EETS1K) Block User Guide Byte Level Data Link Controller -J1850 (BDLC) Block User Guide Motorola Scalable CAN (MSCAN) Block User Guide Voltage Regulator (VREG) Block User Guide Port Integration Module (PIM_9DJ64) Block User Guide 17 For More Information On This Product. Inc.19 Table 0-2 Document References User Guide HCS12 CPU Reference Manual HCS12 Module Mapping Control (MMC) Block Guide HCS12 Multiplexed External Bus Interface (MEBI) Block Guide HCS12 Interrupt (INT) Block Guide HCS12 Background Debug (BDM) Block Guide HCS12 Breakpoint (BKP) Block Guide Clock and Reset Generator (CRG) Block User Guide Oscillator (OSC) Block User Guide Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block User Guide Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block User Guide Inter IC Bus (IIC) Block User Guide Versi on V02 V04 V03 V01 V04 V01 V04 V02 V01 V02 V02 V02 V02 V01 V01 V01 V01 V02 V01 V01 Document Order Number S12CPUV2/D S12MMCV4/D S12MEBIV3/D S12INTV1/D S12BDMV4/D S12BKPV1/D S12CRGV4/D S12OSCV2/D S12ECT16B8CV1/D S12ATD10B8CV2/D S12IICV2/D S12SCIV2/D S12SPIV2/D S12PWM8B8CV1/D S12FTS64KV1/D S12EETS1KV1/D S12BDLCV1/D S12MSCANV2/D S12VREGV1/D S12PIM9DJ64V1/D Freescale Semiconductor. Inc.Freescale Semiconductor.. MC9S12DJ64 Device User Guide — V01. Go to: www.freescale.com .

.com .19 Semiconductor. Inc. Inc. Go to: www. Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01.freescale. 18 For More Information On This Product..

0 A. Upward compatible with M68HC11 instruction set ii. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. 29 discrete digital I/O channels (Port A.freescale. However. real time interrupt. MC9S12DJ64 Device User Guide — V01. Inc. Enhanced indexed addressing – – – – – • • MEBI (Multiplexed External Bus Interface) MMC (Module Mapping Control) INT (Interrupt control) BKP (Breakpoints) BDM (Background Debug Mode) CRG (low current Colpitts or Pierce oscillator. a digital Byte Data Link Controller (BDLC). Interrupt stacking and programmer’s model identical to M68HC11 iii. a CAN 2. PLL. 10-bit analog-to-digital converters (ADC).1 Overview The MC9S12DJ64 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU). 4K bytes of RAM. The MC9S12DJ64 has full 16-bit data paths throughout. an 8-channel pulse-width modulator (PWM).2 Features • HCS12 Core – 16-bit HCS12 CPU i. Freescale Semiconductor. COP watchdog. 64K bytes of Flash EEPROM. 1. reset. one serial peripheral interfaces (SPI). clock monitor) 8-bit and 4-bit ports with interrupt functionality – – Digital filtering Programmable rising or falling edge trigger 64K Flash EEPROM 1K byte EEPROM • Memory – – 19 For More Information On This Product. two asynchronous serial communications interfaces (SCI). 1K bytes of EEPROM. Port K and Port E).. Inc.19 Section 1 Introduction 1. an 8-channel IC/OC enhanced capture timer. clocks.com . 20 discrete digital I/O lines with interrupt and wakeup capability. Go to: www. and an Inter-IC Bus. Instruction queue iv.Freescale Semiconductor. Port B. the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. B software compatible modules (MSCAN12).. two 8-channel.

Freescale MC9S12DJ64 Device User Guide — V01. Tx. Inc.0 A. Go to: www. B software compatible module Freescale Semiconductor. Inc. 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx. Two 8-channel Analog-to-Digital Converters External conversion trigger capability Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit.19 – • – – • – – – – – 4K byte RAM 10-bit resolution Semiconductor. • Enhanced Capture Timer – – – • 8 PWM channels – – – – – – – • Serial interfaces – – • Byte Data Link Controller (BDLC) – • Inter-IC Bus (IIC) – – – • 112-Pin LQFP or 80 QFP package 20 For More Information On This Product.freescale.com .. error and wake-up Low-pass filter wake-up function Loop-back for self test operation 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Four 8-bit or two 16-bit pulse accumulators Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Two asynchronous Serial Communications Interfaces (SCI) Synchronous Serial Peripheral Interface (SPI) SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications Compatible with I2C Bus standard Multi-master operation Software programmable for one of 256 different serial clock frequencies 1M bit per second.. CAN 2.

MC9S12DJ64 Device User Guide — V01.com . Inc.3 Modes of Operation User modes Freescale Semiconductor.19 – – – – – – I/O lines with 5V input and drive capability 5V A/D converter inputs Operation at 50MHz equivalent to 25MHz Bus Speed Development support Single-wire background debug™ mode (BDM) On-chip hardware breakpoints 1. Go to: www.freescale.. Inc..Freescale Semiconductor. • Normal and Emulation Operating Modes – – – – – Normal Single-Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Single-Chip Mode with active Background Debug Mode Special Test Mode (Motorola use only) Special Peripheral Mode (Motorola use only) • Special Operating Modes – – – Low power modes • • • Stop Mode Pseudo Stop Mode Wait Mode 21 For More Information On This Product.

Inc.19 Semiconductor..4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DJ64 device. Freescale Semiconductor.. 1. Go to: www. 22 For More Information On This Product. Inc.Freescale MC9S12DJ64 Device User Guide — V01.com .freescale.

5V VDDPLL VSSPLL A/D Converter 5V & Voltage Regulator Reference VDDA VSSA PWM Voltage Regulator 5V & I/O VDDR VSSR PTP DDRH PH2 PTH PH3 PH4 PH5 PH6 PH7 Signals shown in Bold are not available on the 80 Pin Package DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 PTM 23 For More Information On This Product.19 Figure 1-1 MC9S12DJ64 Block Diagram 64K Byte Flash EEPROM 4K Byte RAM 1K Byte EEPROM VDDR VSSR VREGEN VDD1. Inc...Freescale Semiconductor.com .2 VSS1.5V VDD1.2 I/O Driver 5V VDDX VSSX PTJ Multiplexed Narrow Bus KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DDRP DDRJ PLL 2. Go to: www.2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ATD0 VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 ATD1 VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 Voltage Regulator AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD AD0 Single-wire Background Debug Module Clock and Reset Generation Module CPU12 DDRK PPAGE PLL Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01. Inc. Periodic Interrupt COP Watchdog Clock Monitor Breakpoints PTK AD1 ECS XIRQ IRQ System R/W Integration LSTRB ECLK MODA MODB NOACC/XCLKS DDRE PTE Enhanced Capture Timer DDRT DDRS SCI0 PTS SCI1 Multiplexed Address/Data Bus SPI0 DDRA PTA DATA15 ADDR15 PA7 DATA14 ADDR14 PA6 DATA13 ADDR13 PA5 DATA12 ADDR12 PA4 DATA11 ADDR11 PA3 DATA10 ADDR10 PA2 DATA9 ADDR9 PA1 DATA8 ADDR8 PA0 MISO MOSI SCK SS PTT DDRB PTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Module to Port Routing BDLC (J1850) DDRM RXB TXB RXCAN CAN0 TXCAN Multiplexed Wide Bus IIC SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 Internal Logic 2.2 VSS1.freescale.

com . Freescale Semiconductor. Inc.freescale. Go to: www. 24 For More Information On This Product. Inc.19 Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01...

freescale.$0019 Module HCS12 Multiplexed External Bus Interface HCS12 Module Mapping Control HCS12 Interrupt Reserved Size (Bytes) 16 5 2 3 2 2 1 1 8 8 2 2 12 64 32 40 8 8 8 8 8 16 16 12 4 32 64 192 64 384 2048 4096 16384 16384 $001A . Table 1-1 Device Memory Map for MC9S12DJ64 Address $0000 . Inc.$009F HCS12 Multiplexed External Bus Interface HCS12 Interrupt Reserved HCS12 Breakpoint Module HCS12 Module Mapping Control HCS12 Multiplexed External Bus Interface Clock and Reset Generator (PLL. $001C .$001D HCS12 Module Mapping Control $001E $001F $0020 .$00FF $0100.$7FFF Reserved Flash Control Register EEPROM Control Register Analog to Digital Converter 10-bit 8 channels (ATD1) Motorola Scalable Can (CAN0) Reserved Port Integration Module (PIM) Reserved EEPROM array 1k Array mapped twice in the address space RAM array Fixed Flash EEPROM array incl. and the 1K $0400 . RTI.$BFFF Flash EEPROM Page Window 25 For More Information On This Product.$00E7 Inter IC Bus $00E8 .. Inc.$03FF) are hidden by the register space.$03FF $0000 .$017F $0180 .Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01.$0033 $0034 .$027F $0280 .$011B $0120 .$007F $0080 .com .5K.$00EF Byte Data Link Controller (BDLC) $00F0 .$00D7 Serial Communications Interface 0 (SCI1) $00D8 .19 1.$010F $0110 . The 1K EEPROM is mapped twice in a 2K address space.$002F $0030 . 0.$023F $0240 .$013F $0140 .$00DF Serial Peripheral Interface (SPI0) $00E0 .$011F Reserved $8000 .$0031 $0032 .$00CF Serial Communications Interface 0 (SCI0) $00D0 .$0FFF $4000 .$00C7 Pulse Width Modulator 8-bit 8 channels (PWM) $00C8 .5 Device Memory Map Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DJ64 after reset. Note that after reset the bottom 1k of the EEPROM ($0000 . 2K or 4K Protected Sector at start $011C . 1K.$0014 $0015 .$0016 $0017 . COP) Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0) $00A0 .$003F $0040 .$0027 $0028 .$000F $0010 . Go to: www.$001B Device ID register (PARTID) Freescale Semiconductor.$07FF $0000 ..$07FF is hidden by the RAM.

Freescale MC9S12DJ64 Device User Guide — V01. Inc.. Table 1-1 Device Memory Map for MC9S12DJ64 Address Module Size (Bytes) 16384 Fixed Flash EEPROM array $C000 . Inc..5K.19 Semiconductor. 1K.$FFFF incl.com .freescale. Go to: www.$FFFF Freescale Semiconductor. 0. 26 For More Information On This Product. 2K or 4K Protected Sector at end and 256 bytes of Vector Space at $FF80 .

$4000 $4000 16K Fixed Flash Page $3E = 62 (This is dependant on the state of the ROMHM bit) $7FFF $8000 $8000 EXTERN $BFFF 16K Page Window 4 x 16K Flash EEPROM pages $C000 $C000 16K Fixed Flash Page $3F = 63 $FFFF $FF00 $FF00 VECTORS $FFFF EXPANDED NORMAL SINGLE CHIP SPECIAL SINGLE CHIP VECTORS VECTORS $FFFF BDM (if active) 27 For More Information On This Product..Freescale Semiconductor. Go to: www. Inc.. MC9S12DJ64 Device User Guide — V01. Inc.freescale. 1K mapped two times in the 2K address space) $07FF $1000 $0000 4K Bytes RAM (Mappable to any 4K Boundary) Unimplemented Unimplemented $0FFF Freescale Semiconductor.com .19 Figure 1-2 MC9S12DJ64 Memory Map out of Reset $0000 $0400 $03FF $0000 REGISTERS (Mappable to any 2K Boundary within the first 32K) $0800 $0000 1K Bytes EEPROM (Mappable to any 2K Boundary.

$023F $0240 ..$003F $0040 .$009F $00A0 .$00D7 Serial Communications Interface 0 (SCI1) $00D8 ..$00C7 Pulse Width Modulator 8-bit 8 channels (PWM) $00C8 .$0019 Module HCS12 Multiplexed External Bus Interface HCS12 Module Mapping Control HCS12 Interrupt Reserved Size (Bytes) 16 5 2 3 2 2 1 1 8 8 2 2 12 64 32 40 8 8 8 8 8 16 16 12 4 32 64 192 64 384 2048 4096 16384 32768 $001A .$FFFF 32K Fixed Flash EEPROM array 28 For More Information On This Product.$001B Device ID register (PARTID) $001C .$03FF $0000 .$07FF $0000 .$7FFF Reserved Flash Control Register EEPROM Control Register Analog to Digital Converter 10-bit 8 channels (ATD1) Motorola Scalable Can (CAN0) Reserved Port Integration Module (PIM) Reserved EEPROM array 1k Array mapped twice in the address space RAM array.$011B $0120 .$00DF Serial Peripheral Interface (SPI0) $00E0 .$010F $0110 .Freescale MC9S12DJ64 Device User Guide — V01.$017F $0180 . COP) Enhanced Capture Timer 16-bit 8 channels Analog to Digital Converter 10-bit 8 channels (ATD0) Freescale Semiconductor.$000F $0010 .$0033 $0034 .$0027 HCS12 Multiplexed External Bus Interface HCS12 Interrupt Reserved HCS12 Breakpoint Module HCS12 Module Mapping Control HCS12 Multiplexed External Bus Interface Clock and Reset Generator (PLL.com . Inc.$0031 $0032 . Table 1-2 Device Memory Map for MC9S12D32 Address $0000 .$BFFF when ROMHM=0) $011C .$027F $0280 .$00E7 Inter IC Bus $00E8 .freescale.$00CF Serial Communications Interface 0 (SCI0) $00D0 .$00EF Byte Data Link Controller (BDLC) $00F0 .19 Semiconductor.$011F Reserved $8000 .$0016 $0017 . Inc. lower half ($0000-$07FF not usable) 16k Fixed Flash EEPROM array (same as array from $8000 .$0014 $0015 .$002F $0030 . $0028 .$001D HCS12 Module Mapping Control $001E $001F $0020 .$0FFF $4000 .$013F $0140 .$00FF $0100. Go to: www.$007F $0080 . RTI.

. $4000 $4000 16K Fixed Flash Block 1 (This is dependant on the state of the ROMHM bit) $7FFF $8000 $8000 EXTERN $BFFF 16K Fixed Flash Block 1 (paging not usable) $C000 $C000 16K Fixed Flash Block 2 $FFFF $FF00 $FF00 VECTORS $FFFF EXPANDED NORMAL SINGLE CHIP SPECIAL SINGLE CHIP VECTORS VECTORS $FFFF BDM (if active) 29 For More Information On This Product.com . 1K mapped two times in the 2K address space) $07FF $1000 $0000 4K Bytes RAM lower half ($0000-$07FF) not usable (Mappable to any 4K Boundary) Unimplemented Unimplemented $0FFF Freescale Semiconductor. Go to: www.freescale. MC9S12DJ64 Device User Guide — V01.19 Figure 1-3 MC9S12D32 Memory Map out of Reset $0000 $0400 not usable $0800 not usable not usable $03FF $0000 $0000 REGISTERS (Mappable to any 2K Boundary within the first 32K) 1K Bytes EEPROM (Mappable to any 2K Boundary. Inc..Freescale Semiconductor. Inc.

$0014 Address $0010 $0011 Name INITRM INITRG MMC map 1 of 4 (HCS12 Module Mapping Control) Bit 7 Read: RAM15 Write: Read: 0 Write: Bit 6 RAM14 REG14 Bit 5 RAM13 REG13 Bit 4 RAM12 REG12 Bit 3 RAM11 REG11 Bit 2 0 0 Bit 1 0 0 Bit 0 RAMHAL 0 30 For More Information On This Product.Freescale MC9S12DJ64 Device User Guide — V01.1 Detailed Register Map $0000 .5..freescale. $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 .. Inc.19 Semiconductor.$000F Address $0000 $0001 $0002 $0003 Name PORTA PORTB DDRA DDRB Reserved Reserved Reserved Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 6 6 0 0 0 0 6 6 0 MODB 0 0 0 0 Bit 5 5 5 5 5 0 0 0 0 5 5 PIPOE MODA 0 0 0 0 Bit 4 4 4 4 4 0 0 0 0 4 4 NECLK 0 PUPEE RDPE 0 0 Bit 3 3 3 3 3 0 0 0 0 3 3 LSTRE IVIS 0 0 0 0 Bit 2 2 2 2 2 0 0 0 0 2 Bit 2 RDWE 0 0 0 0 0 Bit 1 1 1 1 1 0 0 0 0 Bit 1 0 0 EMK PUPBE RDPB 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 0 0 0 Bit 0 0 0 EME PUPAE RDPA ESTR 0 Freescale Semiconductor.com . 1. Go to: www. Inc.

Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01.$001B Address $001A $001B Name PARTIDH PARTIDL Read: Write: Read: Write: Device ID Register (Table 1-4) Bit 7 ID15 ID7 Bit 6 ID14 ID6 Bit 5 ID13 ID5 Bit 4 ID12 ID4 Bit 3 ID11 ID3 Bit 2 ID10 ID2 Bit 1 ID9 ID1 Bit 0 ID8 ID0 $001C .$001E Address $001E Name INTCR Read: Write: MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 IRQE Bit 6 IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 31 For More Information On This Product. $0016 $0017 .19 $0010 .freescale.com .. Inc. Table 1-5) Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0 $001E . Inc.$0014 Address $0012 $0013 $0014 Name INITEE MISC Reserved Read: Write: Read: Write: Read: Write: MMC map 1 of 4 (HCS12 Module Mapping Control) Bit 7 EE15 0 0 Bit 6 EE14 0 0 Bit 5 EE13 0 0 Bit 4 EE12 0 0 Bit 3 EE11 Bit 2 0 Bit 1 0 Bit 0 EEON EXSTR1 EXSTR0 ROMHM ROMON 0 0 0 0 $0015 .$001D Address $001C $001D Name MEMSIZ0 MEMSIZ1 MMC map 3 of 4 (HCS12 Module Mapping Control.$0019 Address $0017 $0019 Name Reserved Read: Write: Reserved Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 $001A .$0016 Address $0015 Name ITCR ITEST Read: Write: Read: Write: INT map 1 of 2 (HCS12 Interrupt) Bit 7 0 INTE Bit 6 0 INTC Bit 5 0 INTA Bit 4 WRINT INT8 Bit 3 ADR3 INT6 Bit 2 ADR2 INT4 Bit 1 ADR1 INT2 Bit 0 ADR0 INT0 Freescale Semiconductor.. Go to: www.

$002F BKP (HCS12 Breakpoint) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Freescale Semiconductor. Inc..$0033 Address $0032 $0033 Name PORTK DDRK Read: Write: Read: Write: MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 Bit 7 Bit 7 Bit 6 6 6 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 Bit 2 2 2 Bit 1 1 1 Bit 0 Bit 0 Bit 0 32 For More Information On This Product.$001F Address $001F Name HPRIO Read: Write: Semiconductor.19 $001F .$0031 Address $0030 $0031 Name PPAGE Reserved Read: Write: Read: Write: MMC map 4 of 4 (HCS12 Module Mapping Control) Bit 7 0 0 Bit 6 0 0 Bit 5 PIX5 0 Bit 4 PIX4 0 Bit 3 PIX3 0 Bit 2 PIX2 0 Bit 1 PIX1 0 Bit 0 PIX0 0 $0032 . Go to: www.. Address $0028 $0029 $002A $002B $002C $002D $002E $002F Name BKPCT0 BKPCT1 BKP0X BKP0H BKP0L BKP1X BKP1H BKP1L $0030 .$0027 Address $0020 $0027 Name Reserved Read: Write: Reserved Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 $0028 .Freescale MC9S12DJ64 Device User Guide — V01.com . Inc.freescale. INT map 2 of 2 (HCS12 Interrupt) Bit 7 PSEL7 Bit 6 PSEL6 Bit 5 PSEL5 Bit 4 PSEL4 Bit 3 PSEL3 Bit 2 PSEL2 Bit 1 PSEL1 Bit 0 0 $0020 .

freescale. MC9S12DJ64 Device User Guide — V01.$003F Address $0034 $0035 $0036 $0037 $0038 $0039 Name SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP CRG (Clock and Reset Generator) Bit 7 Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: RTIF Write: Read: RTIE Write: Read: PLLSEL Write: Read: CME Write: Read: 0 Write: Read: WCOP Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 7 Bit 6 0 0 0 PORF 0 PSTP PLLON RTR6 RSBCK 0 0 0 6 Bit 5 SYN5 0 0 0 0 Bit 4 SYN4 0 0 LOCKIF LOCKIE Bit 3 SYN3 Bit 2 SYN2 Bit 1 SYN1 Bit 0 SYN0 REFDV3 REFDV2 REFDV1 REFDV0 0 LOCK 0 PLLWAI 0 RTR3 0 0 0 0 3 0 TRACK 0 CWAI PRE RTR2 CR2 0 0 0 2 0 SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1 0 SCM 0 COPWAI SCME RTR0 CR0 0 0 0 Bit 0 SYSWAI ROAWAI AUTO RTR5 0 0 0 0 5 ACQ RTR4 0 0 0 0 4 Freescale Semiconductor.com .Freescale Semiconductor. Inc. $003A $003B $003C $003D $003E $003F $0040 . Go to: www. Inc.$007F Address $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 Name TIOS CFORC OC7M OC7D TCNT (hi) TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 ECT (Enhanced Capture Timer 16 Bit 8 Channels) Bit 7 Read: IOS7 Write: Read: 0 Write: FOC7 Read: OC7M7 Write: Read: OC7D7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: TEN Write: Read: TOV7 Write: Read: OM7 Write: Read: OM3 Write: Bit 6 IOS6 0 FOC6 OC7M6 OC7D6 14 6 TSWAI TOV6 OL7 OL3 Bit 5 IOS5 0 FOC5 OC7M5 OC7D5 13 5 TSFRZ TOV5 OM6 OM2 Bit 4 IOS4 0 FOC4 OC7M4 OC7D4 12 4 TFFCA TOV4 OL6 OL2 Bit 3 IOS3 0 FOC3 OC7M3 OC7D3 11 3 0 TOV3 OM5 OM1 Bit 2 IOS2 0 FOC2 OC7M2 OC7D2 10 2 0 TOV2 OL5 OL1 Bit 1 IOS1 0 FOC1 OC7M1 OC7D1 9 1 0 TOV1 OM4 OM0 Bit 0 IOS0 0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 0 TOV0 OL4 OL0 33 For More Information On This Product...19 $0034 .

$007F Address $004A $004B $004C $004D $004E $004F Name TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo) TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACN3 (hi) Semiconductor. ECT (Enhanced Capture Timer 16 Bit 8 Channels) Bit 7 Read: EDG7B Write: Read: EDG3B Write: Read: C7I Write: Read: TOI Write: Read: C7F Write: Read: TOF Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Bit 6 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 PAEN 0 6 Bit 5 EDG6B EDG2B C5I 0 C5F 0 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 PAMOD 0 5 Bit 4 EDG6A EDG2A C4I 0 C4F 0 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 PEDGE 0 4 Bit 3 EDG5B EDG1B C3I TCRE C3F 0 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 CLK1 0 3 Bit 2 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 CLK0 0 2 Bit 1 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 PAOVI PAOVF 1 Bit 0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01. Inc. Go to: www.. $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058 $0059 $005A $005B $005C $005D $005E $005F $0060 $0061 $0062 34 For More Information On This Product. Inc..com .freescale.19 $0040 .

19 $0040 .. $0069 $006A $006B $006C $006D $006E $006F $0070 $0071 $0072 $0073 $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B 0 0 0 0 0 TCBYP 0 PBEN 0 6 6 6 6 14 6 14 6 14 6 0 0 5 5 5 5 13 5 13 5 13 5 0 0 4 4 4 4 12 4 12 4 12 4 0 0 3 3 3 3 11 3 11 3 11 3 0 0 2 2 2 2 10 2 10 2 10 2 PBOVI PBOVF 1 1 1 1 9 1 9 1 9 1 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 35 For More Information On This Product.com .$007F Address $0063 $0064 $0065 $0066 $0067 $0068 Name PACN2 (lo) PACN1 (hi) PACN0 (lo) MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST Test Only Reserved Reserved PBCTL PBFLG PA3H PA2H PA1H PA0H MCCNT (hi) MCCNT (lo) TC0H (hi) TC0H (lo) TC1H (hi) TC1H (lo) ECT (Enhanced Capture Timer 16 Bit 8 Channels) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: MCZI Write: Read: MCZF Write: Read: 0 Write: Read: 0 Write: Read: NOVW7 Write: Read: SH37 Write: Read: Write: Read: 0 Write: Read: Write: Read: Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Bit 6 6 6 6 MODMC 0 0 0 NOVW6 SH26 Bit 5 5 5 5 RDMCL 0 0 0 NOVW5 SH15 Bit 4 4 4 4 0 ICLAT 0 0 0 NOVW4 SH04 Bit 3 3 3 3 0 FLMC POLF3 PA3EN 0 NOVW3 TFMOD Bit 2 2 2 2 MCEN POLF2 PA2EN 0 NOVW2 PACMX Bit 1 1 1 1 MCPR1 POLF1 PA1EN DLY1 NOVW1 BUFEN Bit 0 Bit 0 Bit 0 Bit 0 MCPR0 POLF0 PA0EN DLY0 NOVW0 LATQ Freescale Semiconductor.. Inc. Go to: www. MC9S12DJ64 Device User Guide — V01. Inc.Freescale Semiconductor.freescale.

Go to: www.19 $0040 . ECT (Enhanced Capture Timer 16 Bit 8 Channels) Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 6 14 6 14 6 Bit 5 13 5 13 5 Bit 4 12 4 12 4 Bit 3 11 3 11 3 Bit 2 10 2 10 2 Bit 1 9 1 9 1 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 $0080 .freescale. Inc.$007F Address $007C $007D $007E $007F Name TC2H (hi) TC2H (lo) TC3H (hi) TC3H (lo) Read: Write: Read: Write: Read: Write: Read: Write: Semiconductor.com .$009F Address Name ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 Reserved ATD0TEST0 ATD0TEST1 Reserved ATD0STAT1 Reserved ATD0DIEN Reserved PORTAD0 ATD0DR0H ATD0DR0L ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: Bit 7 Write: Read: 0 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 CCF6 0 6 0 6 14 Bit6 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 CCF5 0 5 0 5 13 0 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 CCF2 0 2 0 2 10 0 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 CCF1 0 1 0 1 9 0 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC 0 CCF0 0 Bit 0 0 BIT 0 Bit8 0 Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01. $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 0 CCF4 0 4 0 4 12 0 S1C PRS3 0 0 0 0 0 0 CCF3 0 3 0 3 11 0 36 For More Information On This Product. Inc...

$009F Address $0092 $0093 $0094 $0095 $0096 $0097 Name ATD0DR1H ATD0DR1L ATD0DR2H ATD0DR2L ATD0DR3H ATD0DR3L ATD0DR4H ATD0DR4L ATD0DR5H ATD0DR5L ATD0DR6H ATD0DR6L ATD0DR7H ATD0DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 13 0 13 0 13 0 13 0 13 0 13 0 13 0 Bit 4 12 0 12 0 12 0 12 0 12 0 12 0 12 0 Bit 3 11 0 11 0 11 0 11 0 11 0 11 0 11 0 Bit 2 10 0 10 0 10 0 10 0 10 0 10 0 10 0 Bit 1 9 0 9 0 9 0 9 0 9 0 9 0 9 0 Bit 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Freescale Semiconductor. $0098 $0099 $009A $009B $009C $009D $009E $009F $00A0 ..Freescale Semiconductor.$00C7 Address $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC Test Only PWMSCLA PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: PWME7 Write: Read: PPOL7 Write: Read: PCLK7 Write: Read: 0 Write: Read: CAE7 Write: Read: CON67 Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Bit 6 PWME6 PPOL6 PCLK6 PCKB2 CAE6 CON45 0 0 6 Bit 5 PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0 5 Bit 4 PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0 4 Bit 3 PWME3 PPOL3 PCLK3 0 CAE3 PSWAI 0 0 3 Bit 2 PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0 2 Bit 1 PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0 1 Bit 0 PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0 Bit 0 37 For More Information On This Product.19 $0080 . MC9S12DJ64 Device User Guide — V01. Inc. Go to: www..com .freescale. Inc.

.freescale.19 $00A0 .Freescale MC9S12DJ64 Device User Guide — V01. PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 6 6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Bit 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Freescale Semiconductor. Inc.$00C7 Address $00A9 $00AA $00AB $00AC $00AD $00AE Name Read: PWMSCLB Write: PWMSCNTA Read: Test Only Write: PWMSCNTB Read: Test Only Write: Read: PWMCNT0 Write: Read: PWMCNT1 Write: Read: PWMCNT2 Write: Read: PWMCNT3 Write: Read: PWMCNT4 Write: Read: PWMCNT5 Write: Read: PWMCNT6 Write: Read: PWMCNT7 Write: Read: PWMPER0 Write: Read: PWMPER1 Write: Read: PWMPER2 Write: Read: PWMPER3 Write: Read: PWMPER4 Write: Read: PWMPER5 Write: Read: PWMPER6 Write: Read: PWMPER7 Write: Read: PWMDTY0 Write: Read: PWMDTY1 Write: Read: PWMDTY2 Write: Read: PWMDTY3 Write: Read: PWMDTY4 Write: Read: PWMDTY5 Write: Semiconductor. $00AF $00B0 $00B1 $00B2 $00B3 $00B4 $00B5 $00B6 $00B7 $00B8 $00B9 $00BA $00BB $00BC $00BD $00BE $00BF $00C0 $00C1 38 For More Information On This Product. Go to: www..com . Inc.

.$00CF Address $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF Name SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL SCI0 (Asynchronous Serial Interface) Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 4 SBR12 SBR4 M ILIE IDLE 0 0 R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 2 SBR10 SBR2 ILT RE NF BRK13 0 R2 T2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR 0 R1 T1 Bit 0 SBR8 SBR0 PT SBK PF RAF 0 R0 T0 $00D0 . Inc.$00D7 Address $00D0 $00D1 $00D2 $00D3 $00D4 Name SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1 SCI1 (Asynchronous Serial Interface) Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Bit 5 0 SBR5 RSRC RIE RDRF Bit 4 SBR12 SBR4 M ILIE IDLE Bit 3 SBR11 SBR3 WAKE TE OR Bit 2 SBR10 SBR2 ILT RE NF Bit 1 SBR9 SBR1 PE RWU FE Bit 0 SBR8 SBR0 PT SBK PF 39 For More Information On This Product.Freescale Semiconductor.$00C7 Address $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 Name PWMDTY6 PWMDTY7 PWMSDN Reserved Reserved Reserved PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 6 6 PWMIE 0 0 0 Bit 5 5 5 Bit 4 4 4 Bit 3 3 3 0 0 0 0 Bit 2 2 2 PWM7IN 0 0 0 Bit 1 1 1 Bit 0 Bit 0 Bit 0 PWMRSTRT PWMLVL PWM7INL PWM7ENA 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01. Inc.com .19 $00A0 . Go to: www..freescale. $00C8 .

com .Freescale MC9S12DJ64 Device User Guide — V01.$00DF Address $00D8 Name SPI0CR1 SPI0CR2 SPI0BR SPI0SR Reserved SPI0DR Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: SPI0 (Serial Peripheral Interface) Bit 7 SPIE 0 0 SPIF 0 Bit7 0 0 Bit 6 SPE 0 SPPR2 0 0 6 0 0 Bit 5 SPTIE 0 SPPR1 SPTEF 0 5 0 0 Bit 4 MSTR Bit 3 CPOL Bit 2 CPHA 0 SPR2 0 0 2 0 0 Bit 1 SSOE SPISWAI SPR1 0 0 1 0 0 Bit 0 LSBFE SPC0 SPR0 0 0 Bit0 0 0 Freescale Semiconductor.$00E7 Address $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 Name IBAD IBFD IBCR IBSR IBDR Reserved Reserved Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: IIC (Inter IC Bus) Bit 7 ADR7 IBC7 IBEN TCF D7 0 0 0 Bit 6 ADR6 IBC6 IBIE IAAS D6 0 0 0 Bit 5 ADR5 IBC5 MS/SL IBB D5 0 0 0 Bit 4 ADR4 IBC4 TX/RX IBAL D4 0 0 0 Bit 3 ADR3 IBC3 TXAK 0 D3 0 0 0 Bit 2 ADR2 IBC2 0 RSTA SRW D2 0 0 0 Bit 1 ADR1 IBC1 0 IBIF D1 0 0 0 Bit 0 0 IBC0 IBSWAI RXAK D0 0 0 0 40 For More Information On This Product.freescale... Go to: www. $00D9 $00DA $00DB $00DC $00DD $00DE $00DF MODFEN BIDIROE SPPR0 MODF 0 4 0 0 0 0 0 3 0 0 $00E0 . Inc. Inc.$00D7 Address $00D5 $00D6 $00D7 Name SCI1SR2 SCI1DRH SCI1DRL Read: Write: Read: Write: Read: Write: Semiconductor. SCI1 (Asynchronous Serial Interface) Bit 7 0 R8 R7 T7 Bit 6 0 T8 R6 T6 Bit 5 0 0 R5 T5 Bit 4 0 0 R4 T4 Bit 3 0 0 R3 T3 Bit 2 BRK13 0 R2 T2 Bit 1 TXDIR 0 R1 T1 Bit 0 RAF 0 R0 T0 $00D8 .19 $00D0 .

19 $00E8 . Inc.$00EF Address $00E8 $00E9 $00EA $00EB $00EC $00ED Name DLCBCR1 DLCBSVR DLCBCR2 DLCBDR DLCBARD DLCBRSR DLCSCR DLCBSTAT BDLC (Bytelevel Data Link Controller J1850) Bit 7 Read: IMSG Write: Read: 0 Write: Read: SMRST Write: Read: D7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 CLKS 0 DLOOP D6 RXPOL 0 0 0 Bit 5 0 I3 RX4XE D5 0 R5 0 0 Bit 4 0 I2 NBFS D4 0 R4 BDLCE 0 Bit 3 0 I1 TEOD D3 BO3 R3 0 0 Bit 2 0 I0 TSIFR D2 BO2 R2 0 0 Bit 1 IE 0 TMIFR1 D1 BO1 R1 0 0 Bit 0 WCM 0 TMIFR0 D0 BO0 R0 0 IDLE Freescale Semiconductor..$00FF Address $00F0 $00FF Name Reserved Read: Write: Reserved Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 $0100 .Freescale Semiconductor. Go to: www. Inc. MC9S12DJ64 Device User Guide — V01.$010F Address $0100 $0101 $0102 $0103 $0104 $0105 $0106 $0107 $0108 $0109 Name FCLKDIV FSEC Reserved FCNFG FPROT FSTAT FCMD Reserved FADDRHI FADDRLO Flash Control Register (fts64k) Bit 7 Bit 6 Read: FDIVLD PRDIV8 Write: Read: KEYEN NV6 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: FPOPEN NV6 Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: Bit 14 Bit 14 Write: Read: Bit 7 6 Write: Bit 5 FDIV5 NV5 0 KEYACC FPHDIS PVIOL CMDB5 0 13 5 Bit 4 FDIV4 NV4 0 0 FPHS1 ACCERR 0 0 12 4 Bit 3 FDIV3 NV3 0 0 FPHS0 0 0 0 11 3 Bit 2 FDIV2 NV2 0 0 FPLDIS BLANK CMDB2 0 10 2 Bit 1 FDIV1 SEC1 0 0 FPLS1 0 0 0 9 1 Bit 0 FDIV0 SEC0 0 0 FPLS0 0 CMDB0 0 Bit 8 Bit 0 41 For More Information On This Product.. $00EE $00EF $00F0 .com .freescale.

Flash Control Register (fts64k) Bit 7 Bit 15 Bit 7 0 Bit 6 14 6 0 Bit 5 13 5 0 Bit 4 12 4 0 Bit 3 11 3 0 Bit 2 10 2 0 Bit 1 9 1 0 Bit 0 Bit 8 Bit 0 0 $0110 .. Inc.$011B Address $0110 Name ECLKDIV Reserved Reserved ECNFG EPROT ESTAT ECMD Reserved for Factory Test EADDRHI EADDRLO EDATAHI EDATALO EEPROM Control Register (eets1k) Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: NV6 EPOPEN Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Bit 7 6 Write: Read: Bit 15 14 Write: Read: Bit 7 6 Write: Bit 5 EDIV5 0 0 0 NV5 PVIOL CMDB5 0 0 Bit 4 EDIV4 0 0 0 NV4 ACCERR 0 0 0 Bit 3 EDIV3 0 0 0 EPDIS 0 0 0 0 Bit 2 EDIV2 0 0 0 EP2 BLANK CMDB2 0 0 Bit 1 EDIV1 0 0 0 EP1 0 0 0 0 Bit 0 EDIV0 0 0 0 EP0 0 CMDB0 0 Bit 8 Bit 0 Bit 8 Bit 0 Freescale Semiconductor..$011F Address $011C $011F Name Reserved Read: Write: Reserved for RAM Control Register Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 42 For More Information On This Product.$010F Address $010A $010B $010C $010F Name FDATAHI FDATALO Reserved Read: Write: Read: Write: Read: Write: Semiconductor. Go to: www.Freescale MC9S12DJ64 Device User Guide — V01. $0111 $0112 $0113 $0114 $0115 $0116 $0117 $0118 $0119 $011A $011B 5 13 5 4 12 4 3 11 3 2 10 2 1 9 1 $011C . Inc.freescale.com .19 $0100 .

. MC9S12DJ64 Device User Guide — V01. Go to: www. Inc.$013F Address $0120 $0121 $0122 $0123 $0124 $0125 Name ATD1CTL0 ATD1CTL1 ATD1CTL2 ATD1CTL3 ATD1CTL4 ATD1CTL5 ATD1STAT0 Reserved ATD1TEST0 ATD1TEST1 Reserved ATD1STAT1 Reserved ATD1DIEN Reserved PORTAD1 ATD1DR0H ATD1DR0L ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DR3L ATD1DR4H ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: Bit 7 Write: Read: 0 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Read: Bit7 Write: Read: Bit15 Write: Bit 6 0 0 AFFC S8C SMP1 DSGN 0 0 0 0 0 CCF6 0 6 0 6 14 Bit6 14 Bit6 14 Bit6 14 Bit6 14 Bit 5 0 0 AWAI S4C SMP0 SCAN ETORF 0 0 0 0 CCF5 0 5 0 5 13 0 13 0 13 0 13 0 13 Bit 4 0 0 Bit 3 0 0 Bit 2 0 0 ETRIG FIFO PRS2 CC CC2 0 0 0 0 CCF2 0 2 0 2 10 0 10 0 10 0 10 0 10 Bit 1 0 0 ASCIE FRZ1 PRS1 CB CC1 0 0 0 0 CCF1 0 1 0 1 9 0 9 0 9 0 9 0 9 Bit 0 0 0 ASCIF FRZ0 PRS0 CA CC0 0 0 SC 0 CCF0 0 Bit 0 0 BIT 0 Bit8 0 Bit8 0 Bit8 0 Bit8 0 Bit8 ETRIGLE ETRIGP S2C PRS4 MULT FIFOR 0 0 0 0 CCF4 0 4 0 4 12 0 12 0 12 0 12 0 12 S1C PRS3 0 0 0 0 0 0 CCF3 0 3 0 3 11 0 11 0 11 0 11 0 11 Freescale Semiconductor.Freescale Semiconductor.19 $0120 . Inc. $0126 $0127 $0128 $0129 $012A $012B $012C $012D $012E $012F $0130 $0131 $0132 $0133 $0134 $0135 $0136 $0137 $0138 43 For More Information On This Product.freescale.com ..

ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit 6 Bit6 14 Bit6 14 Bit6 14 Bit6 Bit 5 0 13 0 13 0 13 0 Bit 4 0 12 0 12 0 12 0 Bit 3 0 11 0 11 0 11 0 Bit 2 0 10 0 10 0 10 0 Bit 1 0 9 0 9 0 9 0 Bit 0 0 Bit8 0 Bit8 0 Bit8 0 Freescale Semiconductor.19 $0120 .MSCAN) Bit 2 WUPE WUPM BRP2 Bit 1 SLPRQ SLPAK BRP1 Bit 0 INITRQ INITAK BRP0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Read: RXACT SYNCH CAN0CTL0 RXFRM CSWAI TIME Write: Read: 0 CAN0CTL1 CANE CLKSRC LOOPB LISTEN Write: Read: CAN0BTR0 SJW1 SJW0 BRP5 BRP4 BRP3 Write: Read: CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 Write: Read: RSTAT1 RSTAT0 TSTAT1 CAN0RFLG WUPIF CSCIF Write: Read: CAN0RIER WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 Write: Read: 0 0 0 0 0 CAN0TFLG Write: Read: 0 0 0 0 0 CAN0TIER Write: Read: 0 0 0 0 0 CAN0TARQ Write: Read: 0 0 0 0 0 CAN0TAAK Write: Read: 0 0 0 0 0 CAN0TBSEL Write: Read: 0 0 0 CAN0IDAC IDAM1 IDAM0 Write: Read: 0 0 0 0 0 Reserved Write: Read: 0 0 0 0 0 Reserved Write: Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 CAN0RXERR Write: TSEG12 TSEG11 TSEG10 TSTAT0 TSTATE0 TXE2 TXEIE2 OVRIF OVRIE TXE1 TXEIE1 RXF RXFIE TXE0 TXEIE0 ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 TX2 IDHIT2 0 0 ABTAK1 TX1 IDHIT1 0 0 ABTAK0 TX0 IDHIT0 0 0 RXERR2 RXERR1 RXERR0 44 For More Information On This Product.com .. Inc. $013F $0140 .$017F Address $0140 $0141 $0142 $0143 $0144 $0145 $0146 $0147 $0148 $0149 $014A $014B $014C $014D $014E Name CAN0 (Motorola Scalable CAN . Inc.$013F Address $0139 $013A $013B $013C $013D $013E Name ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01. Go to: www.freescale..

Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address $0160 Name Extended ID Standard ID CAN0RIDR0 Extended ID Standard ID CAN0RIDR1 Extended ID Standard ID CAN0RIDR2 Extended ID Standard ID CAN0RIDR3 CAN0RDSR0 CAN0RDSR7 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CAN0RDLR Write: Read: Reserved Write: Read: CAN0RTSRH Write: Read: CAN0RTSRL Write: Extended ID Read: CAN0TIDR0 Write: Standard ID Read: Write: Extended ID Read: CAN0TIDR1 Write: Standard ID Read: Write: Bit 7 ID28 ID10 ID20 ID2 ID14 Bit 6 ID27 ID9 ID19 ID1 ID13 Bit 5 ID26 ID8 ID18 ID0 ID12 Bit 4 ID25 ID7 SRR=1 RTR ID11 Bit 3 ID24 ID6 IDE=1 IDE=0 ID10 Bit 2 ID23 ID5 ID17 Bit 1 ID22 ID4 ID16 Bit 0 ID21 ID3 ID15 $0161 ID9 ID8 ID7 $0162 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR $0163 $0164$016B $016C $016D $016E $016F DB7 DB6 DB5 DB4 DB3 DLC3 DB2 DLC2 DB1 DLC1 DB0 DLC0 TSR15 TSR7 ID28 ID10 ID20 ID2 TSR14 TSR6 ID27 ID9 ID19 ID1 TSR13 TSR5 ID26 ID8 ID18 ID0 TSR12 TSR4 ID25 ID7 SRR=1 RTR TSR11 TSR3 ID24 ID6 IDE=1 IDE=0 TSR10 TSR2 ID23 ID5 ID17 TSR9 TSR1 ID22 ID4 ID16 TSR8 TSR0 ID21 ID3 ID15 $0170 $0171 45 For More Information On This Product. Inc. Go to: www..Freescale Semiconductor. Inc..com .freescale.MSCAN) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Write: Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Read: FOREGROUND RECEIVE BUFFER see Table 1-3 Write: Read: FOREGROUND TRANSMIT BUFFER see Table 1-3 Write: Freescale Semiconductor.19 $0140 .$017F Address $014F $0150 $0153 $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F Name CAN0TXERR CAN0IDAR0 CAN0IDAR3 CAN0IDMR0 CAN0IDMR3 CAN0IDAR4 CAN0IDAR7 CAN0IDMR4 CAN0IDMR7 CAN0RXFG CAN0TXFG CAN0 (Motorola Scalable CAN . MC9S12DJ64 Device User Guide — V01.

Inc.Freescale MC9S12DJ64 Device User Guide — V01.. Go to: www.freescale.$023F Address $0180 $023F Name Reserved Read: Write: Reserved Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 $0240 ..$027F Address $0240 $0241 $0242 $0243 $0244 $0245 $0246 $0247 $0248 $0249 Name PTT PTIT DDRT RDRT PERT PPST Reserved Reserved PTS PTIS PIM (Port Integration Module) Bit 7 Read: PTT7 Write: Read: PTIT7 Write: Read: DDRT7 Write: Read: RDRT7 Write: Read: PERT7 Write: Read: PPST7 Write: Read: 0 Write: Read: 0 Write: Read: PTS7 Write: Read: PTIS7 Write: Bit 6 PTT6 PTIT6 DDRT7 RDRT6 PERT6 PPST6 0 0 PTS6 PTIS6 Bit 5 PTT5 PTIT5 DDRT5 RDRT5 PERT5 PPST5 0 0 PTS5 PTIS5 Bit 4 PTT4 PTIT4 DDRT4 RDRT4 PERT4 PPST4 0 0 PTS4 PTIS4 Bit 3 PTT3 PTIT3 DDRT3 RDRT3 PERT3 PPST3 0 0 PTS3 PTIS3 Bit 2 PTT2 PTIT2 DDRT2 RDRT2 PERT2 PPST2 0 0 PTS2 PTIS2 Bit 1 PTT1 PTIT1 DDRT1 RDRT1 PERT1 PPST1 0 0 PTS1 PTIS1 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0 0 PTS0 PTIS0 46 For More Information On This Product.19 Semiconductor. Inc.com . $017D $017E $017F PRIO7 TSR15 TSR7 PRIO6 TSR14 TSR6 PRIO5 TSR13 TSR5 PRIO4 TSR12 TSR4 PRIO3 TSR11 TSR3 $0180 . Table 1-3 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address $0172 Name Extended ID CAN0TIDR2 Standard ID Extended ID CAN0TIDR3 Standard ID CAN0TDSR0 CAN0TDSR7 CAN0TDLR CAN0TTBPR CAN0TTSRH CAN0TTSRL Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: ID14 Bit 6 ID13 Bit 5 ID12 Bit 4 ID11 Bit 3 ID10 Bit 2 ID9 Bit 1 ID8 Bit 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR $0173 $0174$017B $017C DB7 DB6 DB5 DB4 DB3 DLC3 DB2 DLC2 PRIO2 TSR10 TSR2 DB1 DLC1 PRIO1 TSR9 TSR1 DB0 DLC0 PRIO0 TSR8 TSR0 Freescale Semiconductor.

. $0250 $0251 $0252 $0253 $0254 $0255 $0256 $0257 $0258 $0259 $025A $025B $025C $025D $025E $025F $0260 $0261 $0262 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 PTP7 PTIP7 DDRP7 RDRP7 PERP7 PPSP7 PIEP7 PIFP7 PTH7 PTIH7 DDRH7 0 PTP6 PTIP6 DDRP7 RDRP6 PERP6 PPSP6 PIEP6 PIFP6 PTH6 PTIH6 DDRH7 0 PTP5 PTIP5 DDRP5 RDRP5 PERP5 PPSP5 PIEP5 PIFP5 PTH5 PTIH5 DDRH5 MODRR4 PTP4 PTIP4 DDRP4 RDRP4 PERP4 PPSP4 PIEP4 PIFP4 PTH4 PTIH4 DDRH4 0 PTP3 PTIP3 DDRP3 RDRP3 PERP3 PPSP3 PIEP3 PIFP3 PTH3 PTIH3 DDRH3 0 PTP2 PTIP2 DDRP2 RDRP2 PERP2 PPSP2 PIEP2 PIFP2 PTH2 PTIH2 DDRH2 MODRR1 MODRR0 PTP1 PTIP1 DDRP1 RDRP1 PERP1 PPSP1 PIEP1 PIFP1 PTH1 PTIH1 DDRH1 PTP0 PTIP0 DDRP0 RDRP0 PERP0 PPSS0 PIEP0 PIFP0 PTH0 PTIH0 DDRH0 47 For More Information On This Product. Inc.com .Freescale Semiconductor.$027F Address $024A $024B $024C $024D $024E $024F Name DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM MODRR PTP PTIP DDRP RDRP PERP PPSP PIEP PIFP PTH PTIH DDRH Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: PIM (Port Integration Module) Bit 7 DDRS7 RDRS7 PERS7 PPSS7 WOMS7 0 PTM7 PTIM7 DDRM7 RDRM7 PERM7 PPSM7 Bit 6 DDRS7 RDRS6 PERS6 PPSS6 WOMS6 0 PTM6 PTIM6 DDRM7 RDRM6 PERM6 PPSM6 Bit 5 DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0 PTM5 PTIM5 DDRM5 RDRM5 PERM5 PPSM5 Bit 4 DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0 PTM4 PTIM4 DDRM4 RDRM4 PERM4 PPSM4 Bit 3 DDRS3 RDRS3 PERS3 PPSS3 WOMS3 0 PTM3 PTIM3 DDRM3 RDRM3 PERM3 PPSM3 Bit 2 DDRS2 RDRS2 PERS2 PPSS2 WOMS2 0 PTM2 PTIM2 DDRM2 RDRM2 PERM2 PPSM2 Bit 1 DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 PTM1 PTIM1 DDRM1 RDRM1 PERM1 PPSM1 Bit 0 DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0 Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01. Go to: www.. Inc.19 $0240 .freescale.

com . Inc.. $0269 $026A $026B $026C $026D $026E $026F $0270 $027F $0280 .Freescale MC9S12DJ64 Device User Guide — V01..$03FF Address $0280 $03FF Name Reserved Read: Write: Reserved Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 48 For More Information On This Product.19 $0240 . PIM (Port Integration Module) Bit 7 Read: RDRH7 Write: Read: PERH7 Write: Read: PPSH7 Write: Read: PIEH7 Write: Read: PIFH7 Write: Read: PTJ7 Write: Read: PTIJ7 Write: Read: DDRJ7 Write: Read: RDRJ7 Write: Read: PERJ7 Write: Read: PPSJ7 Write: Read: PIEJ7 Write: Read: PIFJ7 Write: Read: 0 Write: Bit 6 RDRH6 PERH6 PPSH6 PIEH6 PIFH6 PTJ6 PTIJ6 DDRJ7 RDRJ6 PERJ6 PPSJ6 PIEJ6 PIFJ6 0 Bit 5 RDRH5 PERH5 PPSH5 PIEH5 PIFH5 0 0 0 0 0 0 0 0 0 Bit 4 RDRH4 PERH4 PPSH4 PIEH4 PIFH4 0 0 0 0 0 0 0 0 0 Bit 3 RDRH3 PERH3 PPSH3 PIEH3 PIFH3 0 0 0 0 0 0 0 0 0 Bit 2 RDRH2 PERH2 PPSH2 PIEH2 PIFH2 0 0 0 0 0 0 0 0 0 Bit 1 RDRH1 PERH1 PPSH1 PIEH1 PIFH1 PTJ1 PTIJ1 DDRJ1 RDRJ1 PERJ1 PPSJ1 PIEJ1 PIFJ1 0 Bit 0 RDRH0 PERH0 PPSH0 PIEH0 PIFH0 PTJ0 PTIJ0 DDRJ0 RDRJ0 PERJ0 PPSJ0 PIEJ0 PIFJ0 0 Freescale Semiconductor.freescale.$027F Address $0263 $0264 $0265 $0266 $0267 $0268 Name RDRH PERH PPSH PIEH PIFH PTJ PTIJ DDRJ RDRJ PERJ PPSJ PIEJ PIFJ Reserved Semiconductor. Inc. Go to: www.

The read-only value is a unique part ID for each revision of the chip. Table 1-4 shows the assigned part ID number. Table 1-5 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details.19 1.com .freescale. The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision number including FAB transfers Bit 3-0: Minor .non full .. Go to: www. MC9S12DJ64 Device User Guide — V01.Freescale Semiconductor. Inc. Table 1-4 Assigned Part ID Numbers Device MC9S12DJ64 MC9S12DJ64 MC9S12DJ64 MC9S12DJ64 MC9S12DJ64 Mask Set Number 0L86D 1L86D 2L86D 3L86D 4L86D Part ID1 $0200 $0201 $02012 $0203 $0204 Freescale Semiconductor.6 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). 1L86D is identical to 2L86D except improved ESD performance on 2L86D The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset).mask set revision 2. NOTES: 1. Inc.. Table 1-5 Memory size registers Register name MEMSIZ0 MEMSIZ1 Value $11 $80 49 For More Information On This Product.

Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01.freescale. Inc...19 Semiconductor. 50 For More Information On This Product. Go to: www. Inc.com .

as described in the Signal Descriptions.19 Section 2 Signal Description This section describes signals that connect off-chip. a table of signal properties. Go to: www. 51 For More Information On This Product. Inc. It includes a pinout diagram. and detailed discussion of signals.. 2.Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01. Freescale Semiconductor. It is built from the signal description sections of the Block Guides of the individual IP blocks on the device..1 Device Pinout The MC9S12DJ64 is available in a 112-pin low profile quad flat pack (LQFP) and in a 80-pin quad flat pack (QFP).com . Inc.freescale. Figure 2-1 and Figure 2-2 show the pin assignments. Most pins perform two or more functions. The MC9S12D32 is only available in a 80-pin quad flat pack (QFP).

. Go to: www.19 Semiconductor..com ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST KWH3/PH3 KWH2/PH2 KWH1/PH1 KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP6/KWP6/PWM6 PP7/KWP7/PWM7 PK7/ECS/ROMCTL VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN0/MISO0 PM3/TXCAN0/SS0 PM4/RXCAN0/MOSI PM5/TXCAN0/SCK0 PJ6/KWJ6/SDA/RXCAN0 PJ7/KWJ7/SCL/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6 PM7 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 MC9S12DJ64 112LQFP VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 Signals shown in Bold are not available on the 80 Pin Package . Inc.freescale. Figure 2-1 Pin Assignments in 112-pin LQFP for MC9S12DJ64 52 For More Information On This Product.Freescale MC9S12DJ64 Device User Guide — V01. Freescale Semiconductor. Inc.

ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 53 For More Information On This Product.Freescale Semiconductor. Inc.19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PP4/KWP4/PWM4 PP5/KWP5/PWM5 PP7/KWP7/PWM7 VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN0/MISO0 PM3/TXCAN0/SS0 PM4/RXCAN0/MOSI0 PM5/TXCAN0/SCK0 PJ6/KWJ6/SDA/RXCAN0 PJ7/KWJ7/SCL/TXCAN0 VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL PWM3/KWP3/PP3 PWM2/KWP2/PP2 PWM1/KWP1/PP1 PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Freescale Semiconductor.freescale. Go to: www.com ... MC9S12DJ64 80 QFP VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 Figure 2-2 Pin Assignments in 80-pin QFP for MC9S12DJ64 and MC9S12D32 2. Inc.2 Signal Properties Summary Table 2-1 summarizes the pin functionality. Signals shown in bold are not available in the 80 pin package. MC9S12DJ64 Device User Guide — V01.

Bus Clock Output Port E I/O. Interrupt Port H I/O. Non Maskable Interrupt Port H I/O. Interrupt PERH/ PPSH Disabled Port H I/O. Interrupt Port H I/O. Byte Strobe. Tag Low Port E I/O. R/W in expanded modes Port E Input.. Interrupt Port H I/O. Access.freescale. Interrupt Port H I/O. Pipe Status.. Mode Input low: Port E I/O. Analog Input AN7 of ATD0. External Trigger Input of ATD0 Port AD Inputs.19 Semiconductor. Inc. Go to: www. PAD15 PAD[14:08] PAD07 PAD[06:00] PA[7:0] PB[7:0] VDDA None None Port AD Inputs. Table 2-1 Signal Properties Pin Name Function1 EXTAL XTAL RESET TEST VREGEN XFC BKGD Pin Name Function2 — — — — — — TAGHI AN15 AN[14:08] AN07 AN[06:00] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] NOACC IPIPE1 IPIPE0 ECLK LSTRB R/W IRQ XIRQ KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 Pin Name Pin Name Powered Function3 Function4 by — — — — — — MODC ETRIG1 — ETRIG0 — — — — — — — — — — — — — — — — PUCR/ PUPAE PUCR/ PUPBE PUCR/ PUPEE Internal Pull Resistor CTRL Reset State Description VDDPLL VDDR N. Tag High. Maskable Interrupt Port E Input. Analog Inputs AN[6:0] of ATD0 Port A I/O. Multiplexed Address/Data Mode dependant1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 XCLKS MODB MODA — TAGLO — — — — — — — — — — — — — — — — — — — — — — — — — — — VDDR Port E I/O. Clock Select While RESET pin is Port E I/O. Interrupt Port H I/O. Interrupt Port H I/O. Analog Inputs AN[6:0] of ATD1 Port AD Input. External Trigger Input of ATD1 Freescale Semiconductor.com . Pipe Status.Freescale MC9S12DJ64 Device User Guide — V01. Mode Input Down Mode dependant1 Up Port E I/O. VDDX VDDPLL VDDR Always Up Up None None Oscillator Pins External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Background Debug. Interrupt PUCR/ PUPEE 54 For More Information On This Product. Inc. Multiplexed Address/Data Disabled Port B I/O.A. Analog Input AN7 of ATD1. Mode Input Port AD Input.

MC9S12DJ64 Device User Guide — V01. MISO of SPI0 Port M I/O. Interrupt. TX of CAN0. Interrupt. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide 55 For More Information On This Product. Interrupt. PWM Channel 4 Port P I/O. PWM Channel 3 Port P I/O. Interrupt.Freescale Semiconductor. RX of CAN0. TX of CAN0 PJ7 PJ6 PJ[1:0] PK7 PK[5:0] PM7 PM6 PM5 KWJ7 KWJ6 KWJ[1:0] ECS XADDR[19:14] — — TXCAN0 RXCAN0 TXCAN0 RXCAN0 TXCAN0 RXCAN0 KWP7 KWP6 KWP5 KWP4 KWP3 KWP2 KWP1 KWP0 SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0 IOC[7:0] SCL SDA — ROMCTL — — — SCK MOSI SS0 MISO0 TXB RXB PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 — — — — — — — — — TXCAN0 RXCAN0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — PERT/ PPST PERS/ PPSS Up VDDX PERP/ PPSP PERM/ PPSM PUCR/ PUPKE Up VDDX PERJ/ PPSJ Up Port J I/O. PM4 PM3 PM2 PM1 PM0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PT[7:0] Port M I/O. SCL of IIC. TXD of SCI0 Port S I/O. TX of CAN0. ROM On Enable Port K I/O. Go to: www. Channel 7 of PWM Port P I/O. MOSI of SPI0 Port M I/O. Inc.com .. RX of CAN0 Port J I/O.freescale. PWM Channel 0 Port S I/O. RX of CAN0. Interrupt. Interrupt. Emulation Chip Select. Inc. RX of CAN0. Interrupt. SS of SPI0 Port M I/O. MISO of SPI0 Port S I/O. SDA of IIC. Timer channels NOTES: 1. PWM Channel 6 Port P I/O. PWM Channel 5 Port P I/O. Interrupts Port K I/O. PWM Channel 1 Port P I/O. SCK of SPI0 Port S I/O. RXD of SCI0 Disabled Port T I/O.19 Pin Name Function1 Pin Name Function2 Pin Name Pin Name Powered Function3 Function4 by Internal Pull Resistor CTRL Reset State Description Port J I/O. Interrupt. PWM Channel 2 Port P I/O. Extended Addresses Port M I/O Port M I/O Port M I/O.. SCK of SPI0 Port M I/O. RX of BDLC Disabled Port P I/O. SS of SPI0 Port S I/O. TX of CAN0. TXD of SCI1 Port S I/O. RXD of SCI1 Port S I/O. Interrupt. RX of BDLC Freescale Semiconductor. MOSI of SPI0 Port S I/O. Interrupt.

an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the 56 For More Information On This Product.3..6 BKGD / TAGHI / MODC — Background Debug. Go to: www. On reset all the device clocks are derived from the EXTAL input frequency. Inc. XFC R0 MCU CS VDDPLL VDDPLL CP Figure 2-3 PLL Loop Filter Connections 2. XTAL is the crystal output.2 RESET — External Reset Pin An active low bidirectional control signal. This input only pin is reserved for test. Any current leakage on this pin must be avoided.3.1 EXTAL.com . 2. NOTE: The TEST pin must be tied to VSS in all applications. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements.freescale. In MCU expanded modes of operation when instruction tagging is on.3 TEST — Test Pin Freescale Semiconductor. 2. 2.3. and an output when an internal MCU function causes a reset. 2. and Mode Pin The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. it acts as an input to initialize the MCU to a known start-up state.Freescale MC9S12DJ64 Device User Guide — V01. XTAL — Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins..5 XFC — PLL Loop Filter Pin PLL loop filter. Inc. 2.3.3.3.19 Semiconductor. Tag High.4 VREGEN — Voltage Regulator Enable Pin This input only pin enables or disables the on-chip voltage regulator.3 Detailed Signal Descriptions 2.

During MCU expanded modes of operation. Go to: www.3. It is used as a MCU operating mode select pin during reset. 2.PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD0. It can act as an external trigger input for the ATD0.9 PAD07 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 PAD07 is a general purpose input pin and analog input AN0 of the analog to digital converter ATD0. 2.3.PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD1. when enabled. This signal will assert when the CPU is not using the bus. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. It can act as an external trigger input for the ATD1.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins PB7-PB0 are general purpose input or output pins. 57 For More Information On This Product. 2.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 PE7 is a general purpose input or output pin. is used to indicate that the current bus cycle is an unused or “free” cycle. 2. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL.19 instruction queue.3. This pin has a permanently enabled pull-up device.7 PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. In MCU expanded modes of operation. these pins are used for the multiplexed external address and data bus. Inc. the NOACC signal. if the pin is left floating. The state of this pin is latched to the MODC bit at the rising edge of RESET.3.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 PAD06 . Inc. the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.Freescale Semiconductor.3.freescale.3.. 2. these pins are used for the multiplexed external address and data bus.8 PAD[14:08] / AN[14:08] — Port AD Input Pins ATD1 PAD14 . Since this pin is an input with a pull-up device during reset. In MCU expanded modes of operation. 2. MC9S12DJ64 Device User Guide — V01.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins PA7-PA0 are general purpose input or output pins.com . 2. The state of this pin is latched at the rising edge of RESET. Freescale Semiconductor.. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used.

Figure 2-4 Colpitts Oscillator Connections (PE7=1) EXTAL C3 MCU RS * RB Crystal or ceramic resonator C4 XTAL VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals.freescale.19 Semiconductor.com . Inc.. Inc. Go to: www. Refer to manufacturer’s data.Freescale MC9S12DJ64 Device User Guide — V01. C1 Crystal or ceramic resonator Freescale Semiconductor. EXTAL CDC * MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC.. Figure 2-5 Pierce Oscillator Connections (PE7=0) EXTAL MCU CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) XTAL not connected Figure 2-6 External Clock Connections (PE7=0) 58 For More Information On This Product.

This pin is an input with a pull-down device which is only active when RESET is low.21 PH7 / KWH7 — Port H I/O Pin 7 PH7 is a general purpose input or output pin.16 PE4 / ECLK — Port E I/O Pin 4 PE4 is a general purpose input or output pin. Inc. It is used as a MCU operating mode select pin during reset. This pin is an input with a pull-down device which is only active when RESET is low. Inc. This will wake up the MCU from STOP or WAIT mode.3. 2. 2.com . It indicates the direction of data on the external bus. In MCU expanded modes of operations. 2.freescale.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. This pin is shared with the instruction queue tracking signal IPIPE0. TAGLO is used to tag the low half of the instruction word being read into the instruction queue.3. Freescale Semiconductor. 2. Go to: www. It is used as a MCU operating mode select pin during reset. MC9S12DJ64 Device User Guide — V01.. this pin drives the read/write output signal for the external bus. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 PE5 is a general purpose input or output pin. The state of this pin is latched to the MODB bit at the rising edge of RESET.Freescale Semiconductor. 2. ECLK can be used as a timing reference. It can be configured to drive the internal bus clock ECLK.. The state of this pin is latched to the MODA bit at the rising edge of RESET.3. LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on. In MCU expanded modes of operation.19 2.3. This will wake up the MCU from STOP or WAIT mode. 59 For More Information On This Product.3.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 PE3 is a general purpose input or output pin.20 PE0 / XIRQ — Port E Input Pin 0 PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This pin is shared with the instruction queue tracking signal IPIPE1.3.18 PE2 / R/W — Port E I/O Pin 2 PE2 is a general purpose input or output pin. 2.19 PE1 / IRQ — Port E Input Pin 1 PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. 2.

25 PH3 / KWH3 — Port H I/O Pin 3 PH3 is a general purpose input or output pin.3. It can be configured as the serial clock pin SCL of the IIC module. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.freescale. Inc. 2.24 PH4 / KWH4 — Port H I/O Pin 2 Freescale Semiconductor. 2. Inc. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.3. 2.Freescale MC9S12DJ64 Device User Guide — V01. PH4 is a general purpose input or output pin.28 PH0 / KWH0 — Port H I/O Pin 0 PH0 is a general purpose input or output pin..com .3. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).22 PH6 / KWH6 — Port H I/O Pin 6 PH6 is a general purpose input or output pin. 60 For More Information On This Product.3.26 PH2 / KWH2 — Port H I/O Pin 2 PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.3.27 PH1 / KWH1 — Port H I/O Pin 1 PH1 is a general purpose input or output pin.3. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode..3. 2.23 PH5 / KWH5 — Port H I/O Pin 5 PH5 is a general purpose input or output pin.3. 2. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.19 Semiconductor. 2.29 PJ7 / KWJ7 / SCL / TXCAN0 — PORT J I/O Pin 7 PJ7 is a general purpose input or output pin. Go to: www. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.

3.35 PM6 — Port M I/O Pin 6 PM6 is a general purpose input or output pin.2 Chip Configuration Summary.3. PK7 is a general purpose input or output pin..freescale. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.33 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] PK5-PK0 are general purpose input or output pins.3. Inc..34 PM7 — Port M I/O Pin 7 PM7 is a general purpose input or output pin.3. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). During MCU expanded modes of operation. It can be configured as the serial data pin SDA of the IIC module.Freescale Semiconductor. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.37 PM4 / RXCAN0 / MOSI0 — Port M I/O Pin 4 PM4 is a general purpose input or output pin. this pin is used as the emulation chip select output (ECS). 2. these pins provide the expanded address XADDR[19:14] for the external bus.31 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] PJ1 and PJ0 are general purpose input or output pins. 2. Inc. During MCU expanded modes of operation. Go to: www. MC9S12DJ64 Device User Guide — V01. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). the state of this pin is latched to the ROMON bit. this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL).19 2. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). 61 For More Information On This Product.com . 2.3. For a complete list of modes refer to 4. 2.3. 2.32 PK7 / ECS / ROMCTL — Port K I/O Pin 7 Freescale Semiconductor.36 PM5 / TXCAN0 / SCK0 — Port M I/O Pin 5 PM5 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).30 PJ6 / KWJ6 / SDA / RXCAN0 — PORT J I/O Pin 6 PJ6 is a general purpose input or output pin. 2.3. 2.3. It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0). In MCU expanded modes of operation. At the rising edge of RESET.

It can be configured as Pulse Width Modulator (PWM) channel 5 output.39 PM2 / RXCAN0 / MISO0 — Port M I/O Pin 2 PM2 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).42 PP7 / KWP7 / PWM7 — Port P I/O Pin 7 PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. Inc. 2. Go to: www.44 PP5 / KWP5 / PWM5 — Port P I/O Pin 5 PP5 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). 2. Freescale Semiconductor. It can be configured as Pulse Width Modulator (PWM) channel 6 output. 2.43 PP6 / KWP6 / PWM6 — Port P I/O Pin 6 PP6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0).41 PM0 / RXCAN0 / RXB — Port M I/O Pin 0 PM0 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). 2.3.Freescale MC9S12DJ64 Device User Guide — V01. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.. 2. 2.40 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 PM1 is a general purpose input or output pin..38 PM3 / TXCAN0 / SS0 — Port M I/O Pin 3 PM3 is a general purpose input or output pin.3.3. Inc.3. It can be configured as Pulse Width Modulator (PWM) channel 7 output. It can be configured as the receive pin RXB of the BDLC. It can be configured as the transmit pin TXB of the BDLC.45 PP4 / KWP4 / PWM4 — Port P I/O Pin 4 PP4 is a general purpose input or output pin.3. 2.19 Semiconductor. It can be configured as Pulse Width Modulator (PWM) channel 4 output.com . It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0).3. 62 For More Information On This Product. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0). 2.freescale.3.3.

Go to: www. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0). 2. PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.3.54 PS3 / TXD1 — Port S I/O Pin 3 PS3 is a general purpose input or output pin.3. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output.com .3.46 PP3 / KWP3 / PWM3 — Port P I/O Pin 3 PP3 is a general purpose input or output pin. 2.3. 2. MC9S12DJ64 Device User Guide — V01. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.51 PS6 / SCK0 — Port S I/O Pin 6 PS6 is a general purpose input or output pin. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0).freescale.48 PP1 / KWP1 / PWM1 — Port P I/O Pin 1 Freescale Semiconductor.Freescale Semiconductor.3. 2.3. Inc.. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.3.19 2.53 PS4 / MISO0 — Port S I/O Pin 4 PS4 is a general purpose input or output pin.3. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).. It can be configured as Pulse Width Modulator (PWM) channel 3 output.47 PP2 / KWP2 / PWM2 — Port P I/O Pin 2 PP2 is a general purpose input or output pin. 63 For More Information On This Product. It can be configured as Pulse Width Modulator (PWM) channel 1 output.3. 2. Inc. 2. 2.52 PS5 / MOSI0 — Port S I/O Pin 5 PS5 is a general purpose input or output pin.49 PP0 / KWP0 / PWM0 — Port P I/O Pin 0 PP0 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1).50 PS7 / SS0 — Port S I/O Pin 7 PS6 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0).

supply to pin drivers. 2. 2.0V Description Internal power and ground generated by internal regulator External power and ground.Freescale MC9S12DJ64 Device User Guide — V01. Go to: www. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0).56 PS1 / TXD0 — Port S I/O Pin 1 PS1 is a general purpose input or output pin. Inc.19 Semiconductor.4 Power Supply Pins MC9S12DJ64 power and ground pins are described below. PS0 is a general purpose input or output pin. 2 VDDR VSSR VDDX VSSX VDDA VSSA VRL VRH Pin Number 112-pin QFP 13.3. Inc. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator.0V 0V 5.3. 2 VSS1. 2.57 PS0 / RXD0 — Port S I/O Pin 0 Freescale Semiconductor. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).5V 0V 5. 64 For More Information On This Product.com .58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] PT7-PT0 are general purpose input or output pins.3. 2.. NOTE: All VSS pins must be connected together in the application. allows the supply voltage to the A/D to be bypassed independently. External power and ground. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0).freescale. supply to pin drivers and internal voltage regulator.55 PS2 / RXD1 — Port S I/O Pin 2 PS2 is a general purpose input or output pin.0V 0V 0V 5.3. 65 14. 66 41 40 107 106 83 86 85 84 Nominal Voltage 2. 2.. Reference voltages for the analog-to-digital converter.0V 0V 5. Table 2-2 MC9S12DJ64 Power and Ground Connection Summary Mnemonic VDD1. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1).

T and S. It also provides the reference for the internal voltage regulator. Bypass requirements depend on how heavily the MCU pins are loaded. VDDX and VSSX are the supplies for Ports J. 65 For More Information On This Product. VSS2 — Internal Logic Power Supply Pins Power is supplied to the MCU through VDD and VSS. There is no static load on those pins allowed. short-duration current demands on the power supply. Internal power and ground generated by internal regulator. Inc.4 VDDA.4. NOTE: No load allowed except for bypass capacitors.0V Description Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently.. use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. 2. short-duration current demands on the power supply. This allows the supply voltage to ATD0/ATD1 and the reference voltage to be bypassed independently. 2. Internal Voltage Regulator enable/disable 2. Inc. use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.5V 0V 5. VSSA are the power supply and ground input pins for the voltage regulator and the two analog to digital converters. VDD2. Because fast signal transitions place high. Because fast signal transitions place high.2 VDDR. VDDR and VSSR are the supplies for Ports A.4. VSS1. MC9S12DJ64 Device User Guide — V01. External power and ground for I/O drivers.3 VDD1. B.Freescale Semiconductor.5V supply is derived from the internal voltage regulator. if VREGEN is tied to ground.4. The internal voltage regulator is turned off. K. M. 2. Because fast signal transitions place high. This 2. VSSA — Power Supply Pins for ATD0/ATD1 and VREG VDDA. VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Go to: www. use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible..com . P.19 Mnemonic VDDPLL VSSPLL VREGEN Pin Number 112-pin QFP 43 45 97 Nominal Voltage 2. VSSX — Power & Ground Pins for I/O Drivers Freescale Semiconductor.freescale.1 VDDX. E and H. short-duration current demands on the power supply. Bypass requirements depend on how heavily the MCU pins are loaded.4.

This 2.6 VDDPLL.4.4..5V voltage is generated by the internal voltage regulator. Enables the internal 5V to 2. If this pin is tied low. This allows the supply voltage to the Oscillator and PLL to be bypassed independently..com . 2. 2. VRL — ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter.freescale.2 and VDDPLL must be supplied externally. VDD1.7 VREGEN — On Chip Voltage Regulator Enable Freescale Semiconductor. Inc.5 VRH.5V voltage regulator.Freescale MC9S12DJ64 Device User Guide — V01. 66 For More Information On This Product. Go to: www. NOTE: No load allowed except for bypass capacitors. 2.4.19 Semiconductor. Inc. VSSPLL — Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop.

Go to: www. Flash RAM EEPROM EXTAL ECT ATD0. Inc.Freescale Semiconductor..19 Section 3 System Clock Description 3. 1 OSC CRG Bus Clock Oscillator Clock XTAL PWM SCI0.1 Overview The Clock and Reset Generator provides the internal clock signals for the HCS12 Core and all peripheral modules.com .. SCI1 SPI0 CAN0 IIC BDLC PIM Figure 3-1 Clock Connections 67 For More Information On This Product.freescale. Inc. Consult the CRG Block User Guide and OSC Block User Guide for details on clock generation. Figure 3-1 shows the clock connections from the CRG to all modules. HCS12 CORE BDM CPU MMC BKP Core Clock MEBI INT Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01.

. Go to: www. Inc. Freescale Semiconductor.19 Semiconductor.freescale. 68 For More Information On This Product. Inc.com .Freescale MC9S12DJ64 Device User Guide — V01..

com . BDM allowed and ACTIVE.2 Chip Configuration Summary Freescale Semiconductor. BDM allowed Emulation Expanded Wide. The operating mode out of reset is determined by the states of the MODC. and MODA pins are latched into these bits on the rising edge of the reset signal. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. MODB.. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. Inc. BDM allowed Normal Single Chip. Emulation Expanded Narrow. MC9S12DJ64 Device User Guide — V01. ROMON = 1 mean the Flash is visible in the memory map. The states of the MODC. Each mode has an associated default memory map and external bus configuration. Inc. BDM allowed Normal Expanded Narrow. MODB. BDM allowed Peripheral. BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide.19 Section 4 Modes of Operation 4.. BDM is allowed in all other modes but a serial command is required to make BDM active. Three low power modes exist for the device.1 Overview Eight possible modes determine the operating configuration of the MC9S12DJ64 and MC9S12D32. The MODC. MODB. BDM allowed Special Test (Expanded Wide).Freescale Semiconductor. BDM allowed 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide. Go to: www. and MODA pins during reset (Table 4-1). and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. 4. Table 4-1 Mode Selection BKGD = MODC 0 PE6 = MODB 0 PE5 = MODA 0 PK7 = ROMCTL X 0 1 X 0 1 X 0 1 X 0 1 ROMON Bit 1 1 0 0 1 0 1 0 1 1 0 1 Mode Description Special Single Chip.freescale. Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS 1 Description Colpitts Oscillator selected 69 For More Information On This Product.

1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM (if desired). Inc. The user must be reminded that part of the security must lie with the user’s code.3. The security byte resides in a portion of the Flash array. VDD1.5V 4.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS 0 Description Pierce Oscillator/external clock selected Table 4-3 Voltage Regulator VREGEN VREGEN 1 0 Description Internal Voltage Regulator enabled Internal Voltage Regulator disabled.freescale.2 and VDDPLL must be supplied externally with 2. Check the Flash Block User Guide for more details on the security configuration.3. This feature allows: • • • • Protection of the contents of FLASH. Protection of the contents of EEPROM..com . At the same time the user may also wish to put a back door in the user’s program.2. This code would defeat the purpose of security.3 Security Freescale Semiconductor. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM. 70 For More Information On This Product.3. Go to: www. The BDM operation will be blocked. Operation from external memory with internal FLASH and EEPROM disabled. Inc.Freescale MC9S12DJ64 Device User Guide — V01.2 Operation of the Secured Microcontroller 4..19 Semiconductor. the part can be secured by programming the security bits located in the FLASH module. The device will make available a security feature preventing the unauthorized read and write of the memory contents. 4. Operation in single-chip mode. 4. An extreme example would be user’s code that dumps the contents of the internal program.

3 Wait This mode is entered by executing the CPU WAI instruction. Go to: www. This is generally done through the BDM. Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state. This mode consumes more current than the full STOP mode. Wake up from this mode can be done via reset or external interrupts. An important source of information about the clock system is the Clock and Reset Generator User Guide (CRG). the part can be reset into special single chip mode. MC9S12DJ64 Device User Guide — V01.com .. 4. 71 For More Information On This Product. This can be done through an external program in expanded mode or via a sequence of BDM commands. Inc.19 4. the user can erase and program the FLASH security bits to the unsecured state. and Wait Mode.2.4 Low Power Modes The microcontroller features three main low power modes. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. 4. but the wake up time from this mode is significantly shorter. Unsecuring is also possible via the Backdoor Key Access. 4. the internal FLASH and EEPROM must be erased.Freescale Semiconductor.3 Unsecuring the Microcontroller In order to unsecure the microcontroller. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active.. Once the user has erased the FLASH and EEPROM. All peripherals stay active. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes. The internal CPU signals (address and data bus) will be fully static.3. Inc. Refer to Flash Block Guide for details.2 Pseudo Stop This mode is entered by executing the CPU STOP instruction. BDM operations will be blocked. Freescale Semiconductor.4. In this mode the CPU will not execute instructions. For further power consumption the peripherals can individually turn off their local clocks.freescale.4. the part will be secured again.4. Other peripherals are turned off.1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode.3. Consult the respective Block User Guide for information on the module behavior in Stop. but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Pseudo Stop. 4.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. 4.

Inc. unused peripheral modules should not be enabled in order to save power.4. 72 For More Information On This Product. Inc..com . Go to: www.19 4.Freescale MC9S12DJ64 Device User Guide — V01.freescale.4 Run Semiconductor. Freescale Semiconductor. Although this is not a low power mode..

Inc. ILIE) ATDCTL2 (ASCIE) ATDCTL2 (ASCIE) PIEJ (PIEJ7. $FFD7 $FFD4. Table 5-1 Interrupt Vector Locations Vector Address $FFFE. Freescale Semiconductor. ILIE) SCICR2 (TIE. RIE. $FFEB $FFE8. PIEJ1. SCME) COP rate select None None None IRQCR (IRQEN) CRGINT (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSRC2 (TOI) PACTL (PAOVI) PACTL (PAI) SPICR1 (SPIE. $FFDD $FFDA. $FFE3 $FFE0. $FFFD $FFFA. $FFF3 $FFF0.com .Freescale Semiconductor. $FFDB $FFD8. TCIE. $FFD3 $FFD0. $FFFF $FFFC. $FFE1 $FFDE.19 Section 5 Resets and Interrupts 5. $FFED $FFEA. $FFD1 $FFCE. $FFE9 $FFE6. TCIE. PIEJ6. $FFDF $FFDC. MC9S12DJ64 Device User Guide — V01. PIEJ0) PIEH (PIEH7-0) HPRIO Value to Elevate – – – – – – $F2 $F0 $EE $EC $EA $E8 $E6 $E4 $E2 $E0 $DE $DC $DA $D8 $D6 $D4 $D2 $D0 $CE $CC 73 For More Information On This Product. $FFF9 $FFF6. $FFF1 $FFEE. $FFE5 $FFE2.2.1 Overview Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. 5.. $FFEF $FFEC. $FFFB $FFF8.2 Vectors 5. $FFCF $FFCC. $FFE7 $FFE4. $FFD5 $FFD2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority. SPTIE) SCICR2 (TIE.freescale. RIE.. $FFCD Interrupt Source Reset Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ IRQ Real Time Interrupt Enhanced Capture Timer channel 0 Enhanced Capture Timer channel 1 Enhanced Capture Timer channel 2 Enhanced Capture Timer channel 3 Enhanced Capture Timer channel 4 Enhanced Capture Timer channel 5 Enhanced Capture Timer channel 6 Enhanced Capture Timer channel 7 Enhanced Capture Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI0 SCI0 SCI1 ATD0 ATD1 Port J Port H CCR Mask None None None None None X-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Local Enable None PLLCTL (CME. $FFF7 $FFF4. $FFF5 $FFF2. Go to: www. Inc. $FFD9 $FFD6.

$FFB3 $FFB0. Refer to the PIM Block User Guide for reset configurations of all peripheral module ports. $FFBF $FFBC.freescale. $FF97 $FF94.19 $FFCA. $FF8D $FF80 to $FF8B Port P Reserved Semiconductor. $FFB5 $FFB2. $FFA1 $FF9E. OVRIE) CANRIER (RXFIE) CANTIER (TXEIE2-TXEIE0) $CA $C8 $C6 $C4 $C2 $C0 $BE $BC $BA $B8 $B6 $B4 $B2 $B0 $AE $AC $AA $A8 $A6 $A4 $A2 $A0 $9E $9C $9A $98 $96 $94 $92 $90 $8E $8C Modulus Down Counter underflow Pulse Accumulator B Overflow CRG PLL lock CRG Self Clock Mode BDLC IIC Bus Reserved EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit Freescale Semiconductor. $FFA3 $FFA0. CBEIE) CANRIER (WUPIE) CANRIER (CSCIE. $FFA7 $FFA4. $FFC1 $FFBE. $FF9B $FF98. $FF9F $FF9C. Inc.Freescale MC9S12DJ64 Device User Guide — V01. $FFA9 $FFA6. PWM Emergency Shutdown 5. $FFAB $FFA8.3 Effects of Reset When a reset occurs. $FFC9 $FFC6. CBEIE) FCNFG (CCIE. $FFB1 $FFAE. Inc. 74 For More Information On This Product.. $FFA5 $FFA2. Go to: www. $FF93 $FF90. $FF95 $FF92. $FFBB $FFB8. Refer to the respective module Block User Guides for register reset states.3. 5. $FF91 $FF8E. $FFC5 $FFC2. $FFAD $FFAA. MCU registers and control bits are changed to known start-up states.. $FFCB $FFC8. $FFC7 $FFC4. $FFAF $FFAC. E and K out of reset.1 I/O pins Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A. I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Reserved PIEP (PIEP7-0) PWMSDN (PWMIE) Reserved MCCTL (MCZI) PBCTL (PBOVI) CRGINT (LOCKIE) CRGINT (SCMIE) DLCBCR1 (IE) IBCR (IBIE) Reserved ECNFG (CCIE. $FFB7 $FFB4. $FFC3 $FFC0.com . $FFB9 $FFB6. B. $FF8F $FF8C. $FF99 $FF96. $FFBD $FFBA. $FF9D $FF9A.

Go to: www. Refer to Table 2-1 for affected pins.Freescale Semiconductor. Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01.com . 5.3.2 Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.19 NOTE: For devices assembled in 80-pin QFP packages all non-bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs. Inc. Inc.freescale. 75 For More Information On This Product...

19 Semiconductor. 76 For More Information On This Product. Inc.freescale.com . Inc... Go to: www.Freescale MC9S12DJ64 Device User Guide — V01. Freescale Semiconductor.

6..1.3.1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU.1 Device-specific information • INITEE – – • Reset state: $01 Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special modes". Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module.. 6. Inc. Go to: www.1 Device-specific information When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock periods.19 Section 6 HCS12 Core Block Description 6. Inc. 6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module. So 1 cycle is equivalent to 1 Bus Clock period.freescale.Freescale Semiconductor. 6.2 HCS12 Module Mapping Control (MMC) Block Description Freescale Semiconductor. Reset state: $00 Register is "Write anytime in all modes" Reset state: $11 Reset state: $80 PPAGE – – • • MEMSIZ0 – – MEMSIZ1 6.1 Device-specific information • PUCR – Reset state: $90 77 For More Information On This Product.com . MC9S12DJ64 Device User Guide — V01.2.

6. 6.1 Device-specific information The Low Voltage Reset feature of the CRG is not available on this device. Freescale Semiconductor. Inc.6 HCS12 Breakpoint (BKP) Block Description Consult the BKP Block Guide for information on the HCS12 Breakpoint module. Section 9 Enhanced Capture Timer (ECT) Block Description Consult the ECT_16B8C Block User Guide for information about the Enhanced Capture Timer module. When the ECT_16B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.Freescale MC9S12DJ64 Device User Guide — V01.3.19 Semiconductor.5 HCS12 Background Debug (BDM) Block Description Consult the BDM Block Guide for information on the HCS12 Background Debug module. 78 For More Information On This Product. 6.. Section 7 Clock and Reset Generator (CRG) Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module. 7.com . Go to: www.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7).freescale. Section 8 Oscillator (OSC) Block Description Consult the OSC Block User Guide for information about the Oscillator module. 6. 8..5.1 Device-specific information When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock.1 Device-specific information The XCLKS input signal is active low (see 2. Inc.4 HCS12 Interrupt (INT) Block Description Consult the INT Block Guide for information on the HCS12 Interrupt module.

Inc.freescale. Section 11 Inter-IC Bus (IIC) Block Description Consult the IIC Block User Guide for information about the Inter-IC Bus module. Section 12 Serial Communications Interface (SCI) Block Description There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DJ64 device. Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter module. Section 16 Flash EEPROM 64K Block Description 79 For More Information On This Product. Go to: www. Section 14 J1850 (BDLC) Block Description Consult the BDLC Block User Guide for information about the J1850 module. Freescale Semiconductor.. Section 15 Pulse Width Modulator (PWM) Block Description Consult the PWM_8B8C Block User Guide for information about the Pulse Width Modulator module.Freescale Semiconductor. When the ATD_10B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode.com . When the PWM_8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode. Inc.. Consult the SCI Block User Guide for information about each Serial Communications Interface module. MC9S12DJ64 Device User Guide — V01. Section 13 Serial Peripheral Interface (SPI) Block Description Consult the SPI Block User Guide for information about each Serial Peripheral Interface module.19 Section 10 Analog to Digital Converter (ATD) Block Description There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DJ64.

Section 17 EEPROM 1K Block Description Consult the EETS1K Block User Guide for information about the EEPROM module.. Section 22 Printed Circuit Board Layout Proposals 80 For More Information On This Product.freescale. Go to: www. Consult the FTS64K Block User Guide for information about the flash module. Exact details of the changeover (ie blank to programmed) for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB. For more details of the S12 LRAE and its implementation.. it must simply be erased prior to flash programming. Section 19 MSCAN Block Description Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. Section 20 Port Integration Module (PIM) Block Description Consult the PIM_9DJ64 Block User Guide for information about the Port Integration Module. if not required.Freescale MC9S12DJ64 Device User Guide — V01. Inc. Section 18 RAM Block Description This module supports single-cycle misaligned word accesses.19 Semiconductor. Section 21 Voltage Regulator (VREG) Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator.com . please see the S12 LREA Application Note (AN2546/D). It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE programmed in the Flash . Inc. Use of the LRAE program is at the discretion of the end user and. Please contact Motorola SPS Sales if you have any additional questions. The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. Freescale Semiconductor.

Freescale Semiconductor.C6).. Keep traces of VSSPLL. Inc. C8... Use low ohmic low inductance connections between VSS1. 220nF 100nF >=100nF 100nF >=100nF Freescale Semiconductor. Inc.19 Table 22-1 Suggested External Component Values Component C1 C2 C3 C4 C5 C6 C7 C8 Purpose VDD1 filter cap VDD2 filter cap VDDA filter cap VDDR filter cap VDDPLL filter cap VDDX filter cap OSC load cap OSC load cap PLL loop filter cap Type ceramic X7R ceramic X7R ceramic X7R X7R/tantalum ceramic X7R X7R/tantalum Value 100 . C10 and Q1 and the connection area to the MCU. Central point of the ground star should be the VSSR pin. C9 / CS C10 / CP C11 / CDC R1 R2 / RB R3 / RS Q1 See PLL specification chapter PLL loop filter cap DC cutoff cap PLL loop filter res PLL loop filter res Pierce mode only PLL loop filter res Quartz Colpitts mode only. if recommended by quartz manufacturer See PLL specification chapter The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. C8. MC9S12DJ64 Device User Guide — V01. C11 and Q1 as small as possible. Go to: www. EXTAL and XTAL as short as possible and occupied board area for C7.com . 220nF 100 . VSSPLL must be directly connected to VSSR.freescale. Do not place other signals or supplies underneath area occupied by C7. Central power input should be fed in at the VDDA/VSSA pins. VSS2 and VSSR. The following rules must be observed: • • • • • • • Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins(C1 . 81 For More Information On This Product..

. Go to: www.19 Semiconductor. Inc.Freescale MC9S12DJ64 Device User Guide — V01. Inc.freescale.com . Figure 22-1 Recommended PCB Layout 112LQFP Colpitts Oscillator VDDX VREGEN C6 VSSX VSSA C3 VDDA Freescale Semiconductor. VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR C4 VDDR C5 C9 R1 C10 C8 Q1 VSSPLL VDDPLL C7 C11 82 For More Information On This Product..

Go to: www.Freescale Semiconductor.freescale. Inc.19 Figure 22-2 Recommended PCB Layout for 80QFP Colpitts Oscillator VDDX C6 VREGEN VSSX VSSA C3 VDDA VDD1 Freescale Semiconductor.com C9 VSSPLL VDDPLL 83 . VSS2 C1 C2 VSS1 VDD2 VSSR C4 C5 VDDR C11 C8 C7 Q1 C10 R1 For More Information On This Product. MC9S12DJ64 Device User Guide — V01. Inc...

Inc. Inc.19 Semiconductor. Figure 22-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VREGEN VDDX C6 VSSX VSSA C3 VDDA Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01.freescale.. Go to: www.com . VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR R3 C5 R2 Q1 C9 C10 C8 C7 VSSPLL C4 VDDR VDDPLL R1 84 For More Information On This Product..

Inc.com C9 VSSPLL VDDPLL 85 . Go to: www.19 Figure 22-4 Recommended PCB Layout for 80QFP Pierce Oscillator VDDX C6 VREGEN VSSX VSSA C3 VDDA Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01..freescale..Freescale Semiconductor. Inc. VDD1 VSS2 C1 C2 VSS1 VDD2 VSSPLL VSSR C4 C5 VDDR R2 Q1 C8 C7 R3 C10 R1 For More Information On This Product.

Freescale MC9S12DJ64 Device User Guide — V01.19

Semiconductor, Inc.

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Freescale Semiconductor, Inc. MC9S12DJ64 Device User Guide — V01.19

Appendix A Electrical Characteristics
A.1 General
This introduction is intended to give an overview on several common topics like power supply, current injection etc.

A.1.1 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate.

Freescale Semiconductor, Inc...

NOTE:
P:

This classification is shown in the column labeled “C” in the parameter tables where appropriate.

Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.

A.1.2 Power Supply
The MC9S12DJ64 and MC9S12D32 utilize several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal.

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Freescale MC9S12DJ64 Device User Guide — V01.19

Semiconductor, Inc.

VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection.

NOTE:

In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2.

A.1.3 Pins

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There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator.

A.1.4 Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.

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Freescale Semiconductor, Inc. MC9S12DJ64 Device User Guide — V01.19 A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings1

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Num
1 2 3 4 5 6 7 8 9 10 11 12 13

Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 2 PLL Supply Voltage 2 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 Instantaneous Maximum Current Single pin limit for TEST 5 Storage Temperature Range

Symbol
VDD5 VDD VDDPLL ∆VDDX ∆VSSX VIN VRH, VRL VILV VTEST ID I

Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 – 65

Max
6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25 +25 0 155

Unit
V V V V V V V V V mA mA mA °C

DL

IDT T
stg

NOTES: 1. Beyond absolute maximum ratings device might be damaged. 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSR, but not clamped high. This pin must be tied low in applications.

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5 Unit Ohm pF Freescale Semiconductor.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits.Freescale MC9S12DJ64 Device User Guide — V01. Table A-2 ESD and Latch-up Test Conditions Model Series Resistance Description Symbol R1 C R1 C - Value 1500 100 1 1 0 200 3 3 -2. During the device qualification ESD stresses were performed for the Human Body Model (HBM). Go to: www.19 Semiconductor. Inc. Inc. 90 For More Information On This Product.1.1.. the Machine Model (MM) and the Charge Device Model.5 7. Unless otherwise noted those conditions apply to all the following data. Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit Ohm pF V V Table A-3 ESD and Latch-Up Protection Characteristics Num C 1 2 3 4 Rating Symbol VHBM VMM VCDM ILAT Min 2000 200 500 +100 -100 +200 -200 Max - Unit V V V mA T Human Body Model (HBM) T Machine Model (MM) T Charge Device Model (CDM) Latch-up Current at TA = 125°C T positive negative Latch-up Current at TA = 27°C T positive negative 5 ILAT - mA A.com . A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. A.. unless specified otherwise in the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature.7 Operating Conditions This chapter describes the operating conditions of the device.freescale.

com . 3.8 Power Dissipation and Thermal Characteristics.Freescale Semiconductor. Please refer to Section A.5 0 0 - Max 5. For power dissipation calculations refer to Section A. Table A-4 Operating Conditions Rating I/O.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. MC9S12DJ64 Device User Guide — V01. Go to: www.75 2. V. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation.5 0.g. Inc. The given operating range applies when this regulator is disabled and the device is powered from an external source. M) with regards to the ambient temperature TA and the junction temperature TJ.freescale..25 2.1 0. The user must assure that the maximum operating junction temperature is not exceeded. 2.35 2. A. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply.35 -0.1.. Some blocks e.1 -0.1 16 25 Unit V V V V V MHz MHz Freescale Semiconductor. The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D • Θ JA ) T J = Junction Temperature.5 2.1.1. Oscillator Bus Frequency MC9S12DJ64C Operating Junction Temperature Range Operating Ambient Temperature Range 3 MC9S12DJ64V Operating Junction Temperature Range Operating Ambient Temperature Range 3 MC9S12DJ64M Operating Junction Temperature Range Operating Ambient Temperature Range 3 T T J -40 -40 27 100 85 °C °C A T J -40 -40 27 120 105 °C °C TA TJ TA -40 -40 27 140 125 °C °C NOTES: 1. [°C ] 91 For More Information On This Product. Inc.252 Typ 5 2.5 2. Regulator and Analog Supply Voltage Digital Logic Supply Voltage 1 PLL Supply Voltage 1 Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Symbol VDD5 VDD VDDPLL ∆VDDX ∆VSSX fosc fbus Min 4.19 NOTE: Please refer to the temperature rating of the device (C.1 0.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ.75 0.

Internal Voltage Regulator disabled P INT = I DD ⋅ V DD + I DDPLL ⋅ V DDPLL + I DDA ⋅ V DDA 2 P IO = R DSON ⋅ I IO i i ∑ PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. Internal voltage regulator enabled P INT = I DDR ⋅ V DDR + I DDA ⋅ V DDA IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR.freescale.for outputs driven high I OH 2.. Inc. Go to: www. [W] Two cases with internal voltage regulator enabled and disabled must be considered: Freescale Semiconductor.com .. For RDSON is valid: V OL R DSON = ----------.. Inc. [°C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation.. 1. 2 P IO = R DSON ⋅ I IO i i respectively ∑ PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. [°C ] P D = Total Chip Power Dissipation. 92 For More Information On This Product.Freescale MC9S12DJ64 Device User Guide — V01. which additionally contains the current flowing into the external loads with output high. [W] Semiconductor.for outputs driven low I OL V DD5 – V OH R DSON = ----------------------------------. Θ JA = Package Thermal Resistance.19 T A = Ambient Temperature.

e. single sided PCB T Thermal Resistance QFP 80.1. Go to: www. double sided PCB with 2 internal planes3 C/W C/W o T Junction to Board LQFP112 T Junction to Case LQFP112 T Junction to Package Top LQFP112 T Thermal Resistance QFP 80. Inc. All parameters are not always applicable. PC Board according to EIA/JEDEC Standard 51-7 A.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. not all pins feature pull up/down resistances.com .. double sided PCB with 2 internal planes oC/W o o o C/W C/W C/W Freescale Semiconductor. The values for thermal resistance are achieved by package simulations 2. Inc.g..19 Table A-5 Thermal Package Characteristics1 Num C 1 2 3 4 5 6 Rating Symbol θJA θJA θJB θJC ΨJT θJA θJA θJB θJC ΨJT Min – – – – – – – – – – Typ – – – – – – – – – – Max 54 41 31 11 2 51 41 27 14 3 Unit o T Thermal Resistance LQFP112. PC Board according to EIA/JEDEC Standard 51-3 3. 7 8 9 10 oC/W oC/W oC/W oC/W T Junction to Board QFP80 T Junction to Case QFP80 T Junction to Package Top QFP80 NOTES: 1. single sided PCB2 T Thermal Resistance LQFP112.Freescale Semiconductor.freescale. 93 For More Information On This Product. MC9S12DJ64 Device User Guide — V01.

8 V 7 IPUL IPUH IPDH IPDL Cin IICS IICP tpign tpval - - –130 µA µA µA µA pF mA µs µs 8 Internal Pull Up Device Current. IL 10 6 2. P Interrupt Input Pulse passed2 -2. Refer to Section A. C tested at V Max. A.3 0.5 25 3 D Input Capacitance Injection current1 T Single Pin limit Total Device Limit. P tested at V Min. P tested at V Max. for more details 2. 94 For More Information On This Product. J. J... IL Iin –1 - 1 Freescale Semiconductor. Table A-6 5V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 P Input High Voltage P Input Low Voltage C Input Hysteresis Rating Symbol V IH IL Min 0. Inc. Sum of all injected currents P Port H. Go to: www.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements.65*VDD5 VSS5 .5 -25 - 13 14 10 NOTES: 1.4 Current Injection. Inc.0.Freescale MC9S12DJ64 Device User Guide — V01. IH - - 130 10 11 12 Internal Pull Down Device Current.1.com .8 - - V 6 V OL - - 0.3 Typ 250 Max VDD5 + 0. Parameter only applies in STOP or Pseudo STOP mode.19 Semiconductor.freescale. P Interrupt Input Pulse filtered2 P Port H.1. 5 V OH VDD5 – 0.35*VDD5 Unit V V mV µA V V HYS 4 Input Leakage Current (pins in high impedance input P mode) V =V or VSS5 in DD5 Output High Voltage (pins in output mode) P Partial Drive IOH = –2mA Full Drive IOH = –10mA Output Low Voltage (pins in output mode) P Partial Drive IOL = +2mA Full Drive IOL = +10mA Internal Pull Up Device Current. IH -10 - - 9 Internal Pull Down Device Current. C tested at V Min.

Go to: www.. Inc.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address. 2 -40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C Pseudo Stop Current (RTI and COP enabled) 1. data and control signals as well as on the duty cycle of those signals. Internal regulator enabled Wait Supply current All modules enabled. MC9S12DJ64 Device User Guide — V01. A. PLL on only RTI enabled 1 Pseudo Stop Current (RTI and COP disabled) 1. Conditions are shown in Table A-4 unless otherwise noted Num C 1 P Rating Run supply currents Single Chip.. internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Unless otherwise noted the currents are measured in single chip mode. Production testing is performed using a square wave signal at the EXTAL input.1.19 A.1.1 Measurement Conditions All measurements are without output loads.freescale.Freescale Semiconductor. Table A-7 Supply Current Characteristics Freescale Semiconductor. Inc.10.10. A very good estimate is to take the single chip currents and add the currents due to the external loads. 2 -40°C 27°C 70°C 85°C 105°C 125°C 140°C Stop Current 2 -40°C 27°C 70°C 85°C "C" Temp Option 100°C 105°C "V" Temp Option 120°C 125°C "M" Temp Option 140°C Symbol IDD5 IDDW Min Typ Max 50 30 5 Unit mA 2 P P C P C C P C P C P C C C C C C C C P C C P C P C P mA 3 IDDPS 370 400 450 550 600 650 800 850 1200 570 600 650 750 850 1200 1500 12 25 100 130 160 200 350 400 600 500 µA 1600 2100 5000 4 IDDPS µA 100 µA 5 IDDS 1200 1700 5000 95 For More Information On This Product.com . No generally applicable numbers can be given.

Inc.. At those low power dissipation levels TJ = TA can be assumed Freescale Semiconductor. 96 For More Information On This Product. NOTES: 1.19 Semiconductor.. Inc. PLL off 2. Go to: www.freescale.Freescale MC9S12DJ64 Device User Guide — V01.com .

2. The following constraints exist to obtain full-scale.freescale.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. Time at 2.com . source capacitance and current injection ..0 28 14 26 13 20 0. Time at 2.2.50V 2. MC9S12DJ64 Device User Guide — V01.0MHz ATD Clock fATDCLK 5 D NCONV8 TCONV8 tREC IREF IREF 6 7 8 D Recovery Time (VDDA=5. Table A-8 ATD Operating Characteristics Freescale Semiconductor. full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA.00 5.2 Factors influencing accuracy Three factors .750 0.19 A.25 2. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. A. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.375 Clock Cycles2 NCONV10 Conv.2.have an influence on the accuracy of the ATD. Go to: www. A.1 Source Resistance: Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input.0MHz ATD Clock fATDCLK TCONV10 ATD 8-Bit Conversion Period Clock Cycles2 Conv.0 Volts) P Reference Supply current 2 ATD blocks on P Reference Supply current 1 ATD block on NOTES: 1.5 14 7 12 6 Typ Max VDDA/2 VDDA Unit V V V MHz Cycles µs Cycles µs µs mA mA C Differential Reference Voltage1 D ATD Clock Frequency ATD 10-Bit Conversion Period D 5..source resistance.50 0.2. Full accuracy is not guaranteed when differential voltage is less than 4. The maximum source resistance RS 97 For More Information On This Product. Conditions are shown in Table A-4 unless otherwise noted Num C Reference Potential 1 2 3 4 D Rating Low High Symbol VRL VRH VRH-VRL fATDCLK Min VSSA VDDA/2 4.Freescale Semiconductor. Inc.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. Inc.

3 Current Injection There are two cases to consider. with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. A. Inc.5mV) at the maximum leakage current. Inc. Freescale Semiconductor.5 10-4 10-2 98 For More Information On This Product.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This additional current impacts the accuracy of the conversion depending on the source resistance..19 Semiconductor. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ. larger values of source resistance is allowed. A.Freescale MC9S12DJ64 Device User Guide — V01. Current is injected into pins in the neighborhood of the channel being converted.2.2.com . specifies results in an error of less than 1/2 LSB (2. If device or operating conditions are less than worst case or leakage-induced error is acceptable. then the external filter capacitor. This can cause a voltage drop due to charge sharing with the external and the pin capacitance..2. For a maximum sampling error of the input voltage ≤ 1LSB. 2.CINN).5 2.2. Go to: www. 1. A portion of this current is picked up by the channel (coupling ratio K). The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. A current is injected into the channel being converted. Table A-9 ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 Rating Symbol RS CINN CINS INA Kp Kn Min - Typ - Max 1 10 22 Unit KΩ pF mA A/A A/A C Max input Source Resistance Total Input Capacitance T Non Sampling Sampling C Disruptive Analog Input Current C Coupling Ratio positive current injection C Coupling Ratio negative current injection -2.freescale. Cf ≥ 1024 * (CINS.

input capacitance and source resistance. 4 5 6 7 8 0. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH .5 Counts Counts Counts NOTES: 1.– n 1LSB 99 For More Information On This Product. For the following definitions see also Figure A-1.0MHz Num C 1 2 3 P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error1 P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error1 Rating Symbol LSB DNL INL AE LSB DNL INL AE Min Typ 5 Max Unit mV –1 –2.0 1.VRL = 5.5 ±0.5 ±1. These values include the quantization error which is inherently 1/2 count for any A/D converter.5 3 Counts Counts Counts mV Freescale Semiconductor..– 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = ∑ i=1 Vn – V0 DNL ( i ) = ------------------. MC9S12DJ64 Device User Guide — V01. Vi – Vi – 1 DNL ( i ) = ----------------------.5 ±2.2.5 –1.5 1.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection.com . Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.5 -3 ±1.0 -1. Inc.12V. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.0 20 –0. Go to: www.19 A. Inc.Freescale Semiconductor.0 1 2.freescale..

. 100 For More Information On This Product.freescale. $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $FE 10-Bit Resolution $3F4 $3F3 $FD 9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 45 Ideal Transfer Curve 2 10-Bit Transfer Curve 1 8-Bit Transfer Curve 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-1 ATD Accuracy Definitions NOTE: Figure A-1 shows only definitions. for specification values refer to Table A-10. Inc. Inc. DNL LSB Vi-1 $3FF $3FE $3FD $3FC 10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary $FF Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01. Go to: www..com 8-Bit Resolution .19 Semiconductor.

3. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. A. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively.3.+ 25 ⋅ ---------f NVMOP f bus A.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator.1. Inc.com ..3. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations.1. Inc.1.freescale.Freescale Semiconductor. The frequency of this clock must be set within the limits specified as fNVMOP. The time to program a consecutive word can be calculated as: 1 1 t bwpgm = 4 ⋅ --------------------. MC9S12DJ64 Device User Guide — V01. A.3. Go to: www. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.19 A.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.. Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. Freescale Semiconductor.3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes: 101 For More Information On This Product.+ 9 ⋅ ---------f NVMOP f bus The time to program a whole row is: t brpgm = t swpgm + 31 ⋅ t bwpgm Row programming is more than 2 times faster than single word programming. 1 1 t swpgm = 9 ⋅ --------------------.2 Row Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled.3 NVM. A.

Inc.com .1.5 Blank Check Freescale Semiconductor. 1 t era ≈ 4000 ⋅ --------------------f NVMOP The setup time can be ignored for this operation. A. Burst Programming operations are not applicable to EEPROM 5.4 2 678. Restrictions for oscillator in crystal mode apply! 2.3. It takes one bus cycle per word to verify plus a setup of the command.A. if first word in the array is not blank 7.5 1 150 46 2 20.4 2 20 5 100 5 11 6 11 6 Typ Max 50 1 Unit MHz MHz D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word 4 D Flash Burst Programming Time for 32 Words 4 P Sector Erase Time P Mass Erase Time D Blank Check Time Flash per block D Blank Check Time EEPROM per block 200 74. Refer to formulae in Sections A.1.. Minimum time.5 3 26.1.7 3 133 3 32778 7 20587 kHz µs µs µs ms ms tcyc tcyc NOTES: 1.1.3. The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. 6.3. Go to: www.1 .19 Semiconductor. Inc. 3. Maximum time to complete check on an erased block 102 For More Information On This Product. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus.3.Freescale MC9S12DJ64 Device User Guide — V01. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP.5 3 31 3 1035. 4. t check ≈ location ⋅ t cyc + 10 ⋅ t cyc Table A-11 NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 7 8 9 10 Rating Symbol fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck Min 0.freescale.4 Mass Erase Erasing a NVM block takes: 1 t mass ≈ 20000 ⋅ --------------------f NVMOP The setup time can be ignored for this operation..4 for guidance. A. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus.

com . Go to: www.freescale. MC9S12DJ64 Device User Guide — V01. Inc.. constant process monitors and burn-in to screen early life failures.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification. Table A-12 NVM Reliability Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Data Retention at an average junction temperature of TJavg = 70°C Symbol tNVMRET nFLPE nEEPE nEEPE Min 15 10.19 A.000 Cycles 103 For More Information On This Product. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed.. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. 1 2 3 C C Flash number of Program/Erase cycles C EEPROM number of Program/Erase cycles (–40°C ≤ TJ ≤ 0°C) EEPROM number of Program/Erase cycles (0°C < TJ ≤ 140°C) 4 C 100.000 Typ Max Unit Years Cycles Cycles Freescale Semiconductor. Inc.Freescale Semiconductor.000 10.3.

Go to: www. Freescale Semiconductor. 104 For More Information On This Product.19 Semiconductor.. Inc.Freescale MC9S12DJ64 Device User Guide — V01. Inc..com .freescale.

Freescale Semiconductor, Inc. MC9S12DJ64 Device User Guide — V01.19

A.4 Voltage Regulator
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances
Rating
Load Capacitance on VDD1, 2 Load Capacitance on VDDPLL

Symbol
CLVDD CLVDDfcPLL

Min

Typ
220 220

Max

Unit
nF nF

Freescale Semiconductor, Inc...

105 For More Information On This Product, Go to: www.freescale.com

Freescale MC9S12DJ64 Device User Guide — V01.19

Semiconductor, Inc.

Freescale Semiconductor, Inc...
106 For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc. MC9S12DJ64 Device User Guide — V01.19

A.5 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).

A.5.1 Startup
Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.

Table A-14 Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted

Freescale Semiconductor, Inc...

Num C
1 2 3 4 5 6 T POR release level T POR assert level

Rating

Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS

Min

Typ

Max
2.07

Unit
V V tosc

0.97 2 192 20 14 196

D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time

nosc ns tcyc

A.5.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.5.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. A.5.1.4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system.

107 For More Information On This Product, Go to: www.freescale.com

The device also features a clock monitor.EXTAL VIH. STOP or oscillator fail. Table A-15 Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Freescale Semiconductor.EXTAL VIL.1. Inc.EXTAL Min 0.0.EXTAL VHYS. The controller can be woken up by internal or external interrupts.5 200 50 ms s KHz MHz ns ns 1 1 7 1.5.5 100 1003 2. The quality check also determines the minimum oscillator start-up time tUPOSC.1 0. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected.19 Semiconductor. XTAL pins) C DC Operating Bias in Colpitts Configuration on EXTAL Pin 82 0.5 9. Pierce oscillator/external clock mode allows the input of a square wave..com .2 Oscillator The device features an internal Colpitts and Pierce oscillator.25*VDDPLL VDDPLL ..5 9.45 50 0. Num C 1a 1b 2 3 4 5 6 7 8 9 10 11 12 13 Rating Symbol fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS VIH.3 0. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA.freescale.EXTAL VIL. Inc. A. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on.Freescale MC9S12DJ64 Device User Guide — V01. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Go to: www.3 250 ns ns pF V V V V V mV P EXTAL Pin Input High Voltage4 T EXTAL Pin Input High Voltage4 14 P EXTAL Pin Input Low Voltage4 T EXTAL Pin Input Low Voltage4 15 C EXTAL Pin Input Hysteresis4 108 For More Information On This Product.75*VDDPLL VDDPLL+ 0. After twrs the CPU starts fetching the interrupt vector.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes.5 100 Typ Max 16 40 Unit MHz MHz µA C Crystal oscillator range (Colpitts) C Crystal oscillator range (Pierce) 1 P Startup Current C Oscillator start-up time (Colpitts) D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency 4 D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input Capacitance (EXTAL. A.5 0.5.

.48MHz/V 109 For More Information On This Product. f1 and ich from Table A-16. these frequencies are used for fOSC = 4MHz and a 25MHz bus clock.freescale. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. Maximum value is for extreme cases using high Q. fosc = 4MHz. E. Freescale Semiconductor. Depending on the crystal a damping series resistor might be necessary 2. C = 22pF. 3.19 NOTES: 1.5.5.Freescale Semiconductor. Only valid if Pierce oscillator/external clock mode is selected A.. Inc.. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode.com .3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 – f vco ) ---------------------K 1 ⋅ 1V ( 60 – 50 ) ----------------------– 100 KV = K1 ⋅ e = – 100 ⋅ e = -90. Cp VDDPLL Cs fosc fref 1 refdv+1 ∆ fcmp R Phase KΦ Detector Loop Divider 1 synr+1 XFC Pin VCO KV fvco 1 2 Figure A-2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1.3. Inc. Go to: www. MC9S12DJ64 Device User Guide — V01.g. low frequency crystals 4.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. A.

2 Jitter Information The basic functionality of the PLL is shown in Figure A-2.9 ensures a good transient response. ζ = 0.freescale.516 2⋅ζ C s = --------------------.( ζ = 0.= 2 ⋅ ( synr + 1 ) f ref = 50 With the above values the resistance can be calculated.= 2*π*50*10kHz/(316.9 ) = 5. Go to: www. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-3. Inc. the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.7nF π ⋅ fC ⋅ R fC ⋅ R The capacitance Cp should be chosen in the range of: 2 C s ⁄ 20 ≤ C p ≤ C s ⁄ 10 Cp = 470pF A.----. With each transition of the clock fcmp. temperature and other factors cause slight variations in the control loop resulting in a clock jitter. Noise.5.9kΩ=~10kΩ KΦ The capacitance Cs can now be calculated as: 0..19nF =~ 4.→ f C < ------------..The adjustment is done continuously with no abrupt changes in the clock output frequency.7Hz/Ω)=9. Inc. typical values are 50.com . K Φ = – i ch ⋅ K V ich is the current in tracking mode. 110 For More Information On This Product.19 The phase detector relationship is given by: Semiconductor. = 316.7Hz/Ω The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10.≈ -------------. The example is shown for a loop bandwidth fC=10kHz: 2 ⋅ π ⋅ n ⋅ fC R = ---------------------------.( ζ = 0. And finally the frequency relationship is defined as f VCO n = -----------.9 ) 4 ⋅ 10 10 2 π ⋅ ζ + 1 + ζ  fC < 25kHz   Freescale Semiconductor. 2 ⋅ ζ ⋅ f ref f ref 1 f C < -----------------------------------------.3..Freescale MC9S12DJ64 Device User Guide — V01.. voltage.

Inc. Go to: www.. Inc.+ j 2 N J(N) 1 5 10 20 N Figure A-4 Maximum bus clock jitter approximation 111 For More Information On This Product. N ⋅ t nom N ⋅ t nom   For N < 100. Figure A-3 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period.freescale. 1 – -------------------.com . and decreases towards zero for larger number of clock periods (N).. the following equation is a good fit for the maximum jitter: j1 J ( N ) = ------..19 0 1 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Freescale Semiconductor.Freescale Semiconductor. Defining the jitter as: t min ( N )  t max ( N )  J ( N ) = max  1 – -------------------. MC9S12DJ64 Device User Guide — V01.

.3 0.5 2. Rs = 10KΩ. SYNR = #$018.7nF. fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03.freescale. Cs = 4.Freescale MC9S12DJ64 Device User Guide — V01.5 50 4 1. fOSC = 4MHz.5 0. Go to: www.5 3.19 Semiconductor. Inc.2 -100 60 38.com .5 8 Unit MHz MHz %1 %1 %1 %1 ms ms ms MHz/V MHz µA µA P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode Freescale Semiconductor. Inc..13 % % NOTES: 1.5 1.1 0. 5 6 7 8 9 10 11 12 13 14 15 C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay 2 D PLLON Tracking mode stabilization delay 2 D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 12 C Jitter fit parameter 22 0. % deviation from target frequency 2. This is very important to notice with respect to timers.5 6 Typ Max 5. Table A-16 PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 Rating Symbol fSCM fVCO |∆trk| |∆Lock| |∆unl| |∆unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2 Min 1 8 3 0 0. serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. 112 For More Information On This Product. Cp = 470pF.

Freescale Semiconductor.. Inc.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol tWUP tWUP Min Typ Max 2 Unit µs µs P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass 5 Freescale Semiconductor. MC9S12DJ64 Device User Guide — V01. 113 For More Information On This Product..com .19 A.freescale. Go to: www. Inc.

19 Semiconductor. Go to: www.com . Inc.Freescale MC9S12DJ64 Device User Guide — V01.. Freescale Semiconductor.freescale. 114 For More Information On This Product. Inc..

SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) 1. Timing values are shown in Table A-18..Freescale Semiconductor.com . Inc. Go to: www. MSB. Inc... . 1 9 MSB OUT2 BIT 6 . .. 1 LSB OUT LSB IN 10 Figure A-5 SPI Master Timing (CPHA = 0) 115 For More Information On This Product. . 1 4 4 11 3 12 Freescale Semiconductor.freescale. 2. For LSBF = 1.7. bit order is LSB.19 A. . If configured as output.1 Master Mode Figure A-5 and Figure A-6 illustrate the master mode timing. LSBF = 0. bit 6.. 6 MSB IN2 BIT 6 .7 SPI A. . bit 1. MC9S12DJ64 Device User Guide — V01.

. 12 11 3 4 11 12 6 MSB IN2 BIT 6 . 1 10 LSB IN Freescale Semiconductor. Inc. . LSBF = 0. 116 For More Information On This Product. If configured as output 2.19 SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA 1.. Inc. 8 in the column labeled “Num” are missing. Semiconductor.. CLOAD = 200pF on all outputs Num C 1 1 2 3 4 5 6 9 10 11 12 P Operating Frequency Rating Symbol fop tsck tlead tlag twsck tsu thi tv tho tr tf Min DC 4 1/2 1/2 tbus − 30 25 0 Typ Max 1/2 2048 — Unit fbus tbus tsck tsck P SCK Period tsck = 1.freescale. . . . For LSBF = 1. The numbers 7. Go to: www. bit 1. bit 6. MASTER MSB OUT2 BIT 6 . bit order is LSB.Freescale MC9S12DJ64 Device User Guide — V01.com .. 1 MASTER LSB OUT PORT DATA Figure A-6 SPI Master Timing (CPHA =1) Table A-18 SPI Master Mode Timing Characteristics1 Conditions are shown in Table A-4 unless otherwise noted.. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A-19. MSB../fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs 1024 tbus ns ns ns 25 0 25 25 ns ns ns ns NOTES: 1.

. 1 LSB IN BIT 6 . . .. Timing values are shown in Table A-19. Inc. 1 4 4 11 12 8 10 10 12 11 3 Freescale Semiconductor. . .freescale. . . SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 7 9 MSB OUT 6 MSB IN BIT 6 .Freescale Semiconductor. 1 LSB IN 4 11 12 12 11 3 10 BIT 6 .com .19 A. Inc. . Go to: www.7. MC9S12DJ64 Device User Guide — V01. .2 Slave Mode Figure A-7 and Figure A-8 illustrate the slave mode timing. 1 SLAVE LSB OUT 8 Figure A-8 SPI Slave Timing (CPHA =1) 117 For More Information On This Product. MISO (OUTPUT) SLAVE 5 SLAVE LSB OUT MOSI (INPUT) Figure A-7 SPI Slave Timing (CPHA = 0) SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 7 MOSI (INPUT) SLAVE 5 MSB IN MSB OUT 6 BIT 6 .

6 7 8 9 10 11 12 1 1 25 0 25 25 tcyc tcyc ns ns ns ns 118 For More Information On This Product.Freescale MC9S12DJ64 Device User Guide — V01. Go to: www..com . Table A-19 SPI Slave Mode Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted. Inc.19 Semiconductor.. CLOAD = 200pF on all outputs Num C 1 1 2 3 4 5 P Operating Frequency Rating Symbol fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf Min DC 4 1 1 tcyc − 30 25 25 Typ Max 1/6 2048 Unit fbus tbus tcyc tcyc ns ns ns P SCK Period tsck = 1. Inc./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs Freescale Semiconductor.freescale.

All major bus signals are included in the diagram.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values shown on table Table A-20.. While both a data write and data read cycle are shown. Inc. The timing parameters shown assume a balanced load across all outputs. Go to: www.19 A.com .8. Inc. 119 For More Information On This Product.Freescale Semiconductor.1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions.freescale. Freescale Semiconductor. A. MC9S12DJ64 Device User Guide — V01.. only one or the other would occur on a particular bus cycle.

freescale. Go to: www..19 Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01.5 34 35 36 Figure A-9 General External Bus Timing 120 For More Information On This Product. Inc.. Inc. 17 Non-Multiplexed Addresses PK5:0 20 ECS PK7 18 19 21 22 23 24 R/W PE2 25 26 27 LSTRB PE3 28 29 30 NOACC PE7 31 32 33 IPIPO0 IPIPO1. 1. PB data addr 8 16 4 10 data 11 14 data 13 Freescale Semiconductor.com . 2 3 ECLK PE4 5 9 Addr/Data (read) PA. PB data 6 15 addr 7 12 Addr/Data (write) PA. PE6.

E low D Pulse width. CLOAD = 50pF Num C 1 2 3 4 5 6 7 Rating Symbol fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV Min 0 40 19 19 Typ Max 25. 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 121 For More Information On This Product.. E high1 D Address delay time D Address valid time to E rise (PWEL–tAD) D Muxed address hold time D Address hold to data valid D Data hold to address D Read data setup time D Read data hold time D Write data delay time D Write data hold time D Write data setup time1 (PWEH–tDDW) D Address access time1 (tcyc–tAD–tDSR) D E high access time1 (PWEH–tDSR) D Non-multiplexed address delay time D Non-muxed address valid to E rise (PWEL–tNAD) D Non-multiplexed address hold time D Chip select delay time D Chip select access time1 (tcyc–tCSD–tDSR) D Chip select hold time D Chip select negated time D Read/write delay time D Read/write valid time to E rise (PWEL–tRWD) D Read/write hold time D Low strobe delay time D Low strobe valid time to E rise (PWEL–tLSD) D Low strobe hold time D NOACC strobe delay time D NOACC valid time to E rise (PWEL–tNOD) 8 11 2 7 2 13 0 7 2 12 19 6 6 15 2 16 11 2 8 7 14 2 7 14 2 7 14 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Freescale Semiconductor. Go to: www. Inc.0 Unit MHz ns ns ns P Frequency of operation (E-clock) P Cycle time D Pulse width. MC9S12DJ64 Device User Guide — V01.Freescale Semiconductor..freescale. Inc.com .19 Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted.

. Inc.19 Semiconductor. 122 For More Information On This Product.1. CLOAD = 50pF Num C 32 33 34 35 36 D NOACC hold time D IPIPO[1:0] delay time Rating Symbol tNOH tP0D tP0V tP1D tP1V Min 2 2 11 2 11 Typ Max Unit ns 7 ns ns D IPIPO[1:0] valid time to E rise (PWEL–tP0D) D IPIPO[1:0] delay time1 (PWEH-tP1V) D IPIPO[1:0] valid time to E fall 25 ns ns NOTES: 1.freescale.com . Go to: www. Affected by clock stretch: add N x tcyc where N=0. Inc. depending on the number of clock stretches.. Freescale Semiconductor.Freescale MC9S12DJ64 Device User Guide — V01.2 or 3. Table A-20 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted.

Inc.Freescale Semiconductor..1 General This section provides the physical dimensions of the MC9S12DJ64 and MC9S12D32 packages. MC9S12DJ64 Device User Guide — V01.com .19 Appendix B Package Information B.. 123 For More Information On This Product.freescale. Freescale Semiconductor. Inc. Go to: www.

650 BSC 0.000 BSC 10.350 1.750 0.200 22.100 0. MILLIMETERS MIN MAX 20.000 BSC 20. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.200 0.20 T L-M N J1 J1 C L 4X P VIEW Y 108X G X X=L.450 0.600 0.370 0.050 θ2 VIEW AB 0. 5.25 PER SIDE.090 0. M OR N VIEW Y B L M B1 V1 V J AA Freescale Semiconductor. DATUM T.Freescale MC9S12DJ64 Device User Guide — V01.450 0. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 2. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE.090 0. ALLOWABLE PROTRUSION IS 0.10 T 112X SEATING PLANE θ3 T θ R R2 0. DATUM T.46.5M.270 0. 4. 6. Inc.com . DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. B.13 M BASE METAL 29 56 T L-M N N A1 S1 A S SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE NOTES: 1.330 0.050 0.170 0.160 8 ° 0° 7 ° 3 ° 13 ° 11 ° 11 ° 13 ° C2 C 0. DIMENSIONING AND TOLERANCING PER ASME Y14.25 GAGE PLANE R R1 C1 (Y) (Z) VIEW AB (K) E θ1 DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA θ θ1 θ2 θ3 Figure B-1 112-pin LQFP mechanical dimensions (case no.000 BSC 11. Go to: www.000 REF 0. DIMENSIONS IN MILLIMETERS.270 0. 28 57 F D 0.000 BSC 22.325 BSC 0. Inc.500 REF 0.2 112-pin LQFP package 4X PIN 1 IDENT 1 112 0.19 Semiconductor..000 BSC 10.250 REF 1.150 1. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 3. M AND N TO BE DETERMINED AT SEATING PLANE.freescale.20 T L-M N 4X 28 TIPS 85 84 0. DATUMS L.100 0. 987) 124 For More Information On This Product.000 BSC 0..000 BSC --1. 1994.000 BSC 11.

35 REF 5° 10 ° 0.33 0. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.22 0.325 BSC 0° 7° 0.-B-.25 PER SIDE.15 2. DATUM PLANE -H. 2.20 -A-. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.22 0.95 17.10 13. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-.IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.freescale.20 0.10 2.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.05 A-B J S N 0. 6.23 0.00 2.com .13 0.13 0. 4. 1982.10 M U T DATUM PLANE -H- R K W X DETAIL C Q NOTES: 1.13 --0° --16.TO BE DETERMINED AT DATUM PLANE -H-.20 M F A H A-B S S D S 0. DIMENSIONING AND TOLERANCING PER ANSI Y14.35 0.95 17.45 0.38 2. ALLOWABLE PROTRUSION IS 0.19 B. -B.05 D M M C A-B -A- -B- S S D 0.25 0. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.90 14.AND -D.30 16. Go to: www. CONTROLLING DIMENSION: MILLIMETER.95 12.6 REF Figure B-2 80-pin QFP Mechanical Dimensions (case no. Inc. DATUMS -A-.-DDETAIL A Freescale Semiconductor.45 0. MC9S12DJ64 Device User Guide — V01.. 841B) 125 For More Information On This Product.13 0.. 5.Freescale Semiconductor.40 0.3 80-pin QFP package L 60 61 41 40 S S B B P D L H A-B B V 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.65 0.17 0. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-.65 BSC --0.45 0.90 14.45 1. Inc. DETAIL A 80 1 20 21 -D0. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13. 7.5M.20 E C -CSEATING PLANE M C A-B D S M DETAIL C -HH G DATUM PLANE D 0. 3. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.

126 For More Information On This Product. Inc.Freescale MC9S12DJ64 Device User Guide — V01.freescale.com . Freescale Semiconductor. Go to: www.. Inc..19 Semiconductor.

com . MC9S12DJ64 Device User Guide — V01. Inc. Go to: www.. 127 For More Information On This Product.freescale..Freescale Semiconductor.19 User Guide End Sheet Freescale Semiconductor. Inc.

Freescale MC9S12DJ64 Device User Guide — V01.freescale.. Inc.com . FINAL PAGE OF 128 PAGES 128 For More Information On This Product. Inc. Freescale Semiconductor..19 Semiconductor. Go to: www.