You are on page 1of 5

Design and implementation of low power digital FIR filter based on low power multipliers and adders on xilinx

FPGA
Rashidi, Bahram Rashidi, Bahman Pourormazd, Majid University of Tabriz This paper appears in: Electronics Computer Technology (ICECT), 2011 3rd International Conference on Issue Date: 8-10 April 2011 Volume: 2 On page(s): 18 - 22 Location: Kanyakumari, India Print ISBN: 978-1-4244-8678-6 Digital Object Identifier: 10.1109/ICECTECH.2011.5941647 Date of Current Version: 07 July 2011

ABSTRACT This paper presents the methods to reduce dynamic power consumption of a digital Finite Imppulse Respanse (FIR) filter these mrthods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear pheas architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitching is also reduced. The minimum power achieved is 110mw in fir filter based on shift/add multiplier in 100MHZ to 8taps and 8bits inputs and 8bits coefficions. The proposed FIR filters were synthesized implemented using Xilinx ISE Virtex IV FPGA and power is analized using Xilinx XPower analyzer.

Low power noise detection circuit utilizing switching activity measurement method
Razak, Z. Erdogan, A. Arslan, T. Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK This paper appears in: Design and Architectures for Signal and Image Processing (DASIP), 2010 Conference on Issue Date: 26-28 Oct. 2010 On page(s): 258 - 264 Location: Edinburgh E-ISBN: 978-1-4244-8733-2 Print ISBN: 978-1-4244-8734-9 INSPEC Accession Number: 11822199 Digital Object Identifier: 10.1109/DASIP.2010.5706273 Date of Current Version: 31 January 2011

ABSTRACT Noise often limits the performance of transmitted signals and degrades signals quality. Moreover, stochastic nature of noise makes it difficult to predict, and hence, is hard to detect. In hardware implementation, the reduction of noise can only be optimized in the baseband where complex and intensive computation is executed using digital signal processors (DSPs). Although analog pre-filtering is applied at receiver front-end to reduce interferences, fractions of noise still exist due to non-ideality of the device. We present a method to detect noise in signal using switching activity measurement (SWAM) of analog-to-digital converter (ADC) output. Simulation results show that switching activity of digital outputs varies with different signal-to-noise ratio (SNR) values where high SNR value leads to low switching activity. A noise detection unit (NDU) is implemented and is synthesized using AMS 0.35 m/3.3V CMOS standard library. The result shows minimum overhead where NDU occupies only 774 equivalent 2-input NAND gates and consumes only 978 W of power. With advantage of small complexity and power usage, NDU is attractive to be used in ADC-based systems and noise prone devices in order to detect noise and leads to further signal improvement.

A design of IIR based digital hearing aids using genetic algorithm


Srisangngam, Pichet Chivapreecha, Sorawat Dejhan, Kobchai Faculty of Science and Technology Phranakhon Si Ayuttaya Rajabhat University, Thailand 13000 This paper appears in: Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2011 8th International Conference on Issue Date: 17-19 May 2011 On page(s): 967 - 970 Location: Khon Kaen, Thailand Print ISBN: 978-1-4577-0425-3 Digital Object Identifier: 10.1109/ECTICON.2011.5948003 Date of Current Version: 12 July 2011

ABSTRACT This paper presents a design of digital filter for digital hearing aids application. The structure of filter is consist a combination in parallel form of IIR (Infinite Impulse Response) a low-pass, a band-pass and a high-pass filter. This study shows an advantage of IIR filter can gives a good result in the low complexity digital hearing aids which leads to low hardware resources requirement and low power consumption for VLSI design. The filter coefficients of there IIR filter will obtained from the optimization procedure by genetic algorithm (GA.) The error between desired magnitude response and actual magnitude response will be minimized by GA. In order to achieve a capable of the best compensation for each hearing loss pattern. Finally, the design example and simulation results will show the accuracy of hearing loss compensation and optimal coefficients.

Power Scalable Digital Baseband Architecture for IEEE 802.15.4


Dwivedi, S. Amrutur, B. Bhat, N. ECE Dept., Indian Inst. of Sci., Bangalore, India This paper appears in: VLSI Design (VLSI Design), 2011 24th International Conference on Issue Date: 2-7 Jan. 2011 On page(s): 30 - 35 Location: Chennai ISSN: 1063-9667 Print ISBN: 978-1-61284-327-8 INSPEC Accession Number: 11836861 Digital Object Identifier: 10.1109/VLSID.2011.64 Date of Current Version: 22 February 2011

ABSTRACT We propose a power scalable digital base band for a low-IF receiver for IEEE 802.15.42006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle worst case conditions. We propose tuning of these knobs based on measurements of Signal and the interference levels. We show that in a 0.13u CMOS technology, for an adaptive digital base band section of the receiver designed to meet the 802.15.4 standard specification, power saving can be up to nearly 85% (0.49mW against 3.3mW) in favorable interference and signal conditions.