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Exam TEMA2.

TIMER (A) Name___________________________________

MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question. 1) What advantage does a J-K flip-flop have over an R-S flip-flop? A) It has only one output. B) It has fewer gates. C) It has no invalid states. D) It does not require a clock input. 2) If both inputs of an S-R flip-flop are low, what will happen when the clock goes high? A) The output will reset. B) An invalid state will exist. C) No change will occur in the output. D) The output will toggle. 3) An astable multivibrator is a circuit which ________. A) has two stable states B) is free-running C) produces a continuous output signal D) Both B and C are correct. 4) A 555 timer is connected for astable operation as shown below, along with the output waveform. It is determined that the duty cycle should be 0.5. What steps need to be taken to correct the duty cycle, while maintaining the same output frequency? 1)




A) Increase Vcc and decrease RL. C) Decrease R 1 and increase R2 .

B) Decrease R 1 and R 2. D) Increase the value of C. 5)

5) Which symbol is used to identify edge-triggered flip-flops? A) A bubble on the Clock input. B) A triangle on the Clock input. C) An inverted "L" on the output. D) The letter E on the Enable input. 6) A retriggerable one-shot has a pulse width of 10mS; 3mS after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ ms. A) 3 B) 10 C) 7 D) 13



Nothing is wrong with the circuit. the flip-flop is probably bad. B) When both R and S are high at the same time. except during the active clock input 8) Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown here. but independent of the clock C) having full control over the FF. Determine if the circuit is functioning properly. but not to the inputs B) being tied to the inputs. and the clock cycles. D) The outputs should have toggled on the leading edge of the second clock pulse. regardless of the input or clock states D) having little or no control over the FF. B) A bad connection probably exists between ff-3 and ff-4. 7) 8) A) The input to flip-flop 3 (D2) is probably wrong. the clock signal is inverted. A) being tied to the clock. A) not change B) be invalid C) remain unchanged D) toggle 10) Given the waveforms for this R-S flip-flop. C) The Q output should be high at the beginning of the second clock pulse.7) Asynchronous inputs are best described as ________. what is wrong with the circuit? 9) 10) A) The outputs should change on the trailing edge of the clock. 2 . the IC is bad. check the source of D2. causing ff-3 not to reset. the output is unpredictable. the output will ________. D) Q2 is incorrect. C) The circuit is functioning properly. what might be wrong. The IC is defective. and if not. 9) When both inputs of a J-K pulse-triggered FF are high.