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LIST OF EXPERIMENTS

1.Modeling of Sequential Digital system using VHDL. 2.Modeling of Sequential Digital system using Verilog. 3.Design and Implementation of ALU using FPGA. 4.Simulation of NMOS and CMOS circuits using SPICE. 5.Modeling of MOSFET using C. 6.Implementation of FFT, Digital Filters in DSP Processor. 7.Implementation of DSP algorithms using software package. 8.Implementation of MAC Unit using FPGA

EX.NO:1.a DATE: DESIGN OF HALF ADDERUSING VHDL AIM: To design a Half adder using VHDL. SOFTWARE REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b. Step 3: Declare output ports s, c. Step 4:Begin the process using behavioral architecture. Step 5:Assign s= a b. Step 6: Assign c=a.b. Step 7: End the process. THEORY: The half adder operation needs two binary inputs, augends and add end bits and two binary outputs are sum and carry. SUM Carry = = a a.b b

In multi-digit addition, we have to add two bytes along with the carry of the previous digit addition. Effectively such addition requires addition of three bits. This is not possible with the half adder

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ha is Port ( a,b: in STD_LOGIC; s,c: out STD_LOGIC); end ha; architecture Behavioral of ha is begins<=a XOR b; c<=a AND b; end Behavioral; RESULT: Thus the Half adder was designed using VHDL.

RTL SCHEMATIC:

OUTPUT:

EX.NO:1.b DATE: DESIGN OF FULL ADDER USING VHDL AIM: To design a full adder using VHDL. SOFTWARES REQUIRED: Xilinx. Modelsim.

ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b, Cin Step 3: Declare the output ports s, cy. Step 4: Begin the process using behavioral architecture. Step5:Assign s=a b cin Assign cy= (a.b) + (b.cin) + (cin.a). Step 6: End the process.

THEORY: Full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the inputvariables denoted by A and B, represent the two significant bits to be added.The third input Cin represents the carry from the previous lower significant position. Sum= A .B .Cin + A .B. Cin+ A. B .Cin + A.B.Cin Cin=Cin (A B)

Cout=A.B+A.Cin+B.Cin

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full is Port ( a,b,cin : in STD_LOGIC; S,cy : out STD_LOGIC); end full; architecture Behavioral of full is begin s<=a xor b xor cin; cy<=(a and b)or(b and cin)or(cin and a); end Behavioral; RESULT: Thus the full adder was designed using VHDL

RTL SCHEMATIC:

OUTPUT:

EX NO:1.c DATE : DESIGN OF D-FLIP FLOP USING VHDL AIM: To design a D-Flip flop using VHDL. SOFTWARES REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1:Start the program. Step 2: Declare input ports d, reset, clk. Step 3: Declare output port q. Step 4: Assign always positive edge clock. Step 5: Begin the process. Step 6: If clk=1 then q=d. Step 7: End the process. THEORY: In D-Flip Flop, the basic SR-Flip Flop is used with complemented inputs. The D-Filp Flop is similar to D-Latch except clock pulse is used instead of enable input. The D-Flip Flop can be realized and asQn+1 function follows D inputs at the positive edges of the clock pulse. The characteristics equation for the D-Filp Flop is Qn+1=D

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d,clk : in STD_LOGIC; q : out STD_LOGIC); end dff; architecture Behavioral of dff is begin process(clk) begin if clk='1' then q <= d; end if; end process; end Behavioral;

RESULT: Thus the D-flip flop was designed using VHDL

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EX.NO:2.a DATE: DESIGN OF ENCODER USING VHDL AIM: To design an encoder using VHDL. SOFTWARES REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b, c, d, e, f, g, and h. Step 3: Declare the output ports x, y, and z. Step 4: Begin the process using behavioral architecture. Step 5: Assign x=e or f or g or h; y=c or d or g or h; z=b or d or f or h; Step 6: End the process. THEORY: In priority encoder, if two or more inputs are equal to 1 at the sametime, the input having the highest priority will take precedence. The output zindicates one or more of the inputs are equal to 1.If all inputs are zero, z=0and the other two outputs ofthe circuits are not used.

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity en is Port ( a,b,c,d,e,f,g,h: in STD_LOGIC; x,y,z: out STD_LOGIC); end en; architecture Behavioral of en is begin x=e or f or g or h; y=c or d or g or h; z=b or d or f or h; end Behavioral;

RESULT: Thus the encoder was designed using VHDL

RTL SCHEMATIC:

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EX.NO:2.b DATE: DESIGN OF MULTIPLEXER USING VHDL AIM: To design a multiplexeradder using VHDL. SOFTWARES REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b, c,d. Step 3: Declare the output ports y. Step 4: Begin the process using behavioral architecture. Step 5: Assign y=a when s=00 else y=b when s=01 else y=c when s=10 else y=d when s=11. Step 6: End the process. THEORY: A multiplexer is a device having many inputs and one output. Byapplying control signals, any one of the inputs can be stored to the output. Itis also known as Data selector. It can be an analog device or digital device. Multiplexing may be done in time or frequency domain

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( a,b,c,d: in STD_LOGIC; s: in STD_LOGIC_VECTOR(0 TO 1); y : o ut S T D _L OG IC ) ; end mux; architecture Behavioral of mux is begin y<=a when s=00 else b when s=01 else c when s=10 else d when s=11; end Behavioral;

RESULT: Thus the multiplexer was designed using VHDL.

RTL SCHEMATIC:

OUTPUT:

EX.NO:3.a DATE: DESIGN OF HALF ADDER USING VERILOG AIM: To design a Half adder using VERILOG module. SOFTWARE REQUIRED Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b. Step 3: Declare output ports s, c. Step 4:Begin the process. Step 5: Assign s = a b. Step 6: Assign c=a.b. Step 7: End the process. THEORY: The half adder operation needs two binary inputs, augends andaddend bits and two binary outputs are sum and carry. Sum = a Carry= ab. b .

In multi-digit addition, we have to add two bytes along with thecarry of the previous digit addition. Effectively such addition requiresaddition of three bits. This is not possible with the half adder

PROGRAM: module ha(a, b, sum, carry); input a; input b; output sum; output carry; XOR (sum, a, b); AND (carry, a, b); end module;

RESULT: Thus the Half adder was designed using VERILOG module

RTL SCHEMATIC:

OUTPUT:

EX.NO:3.b DATE: DESIGN OF FULL ADDER USING VERILOG AIM: To design a full adder using VHDL. SOFTWARES REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports a, b, cin Step 3: Declare the output ports s, cy. Step 4: Declare the input-output ports x, y, z. Step 5: Compute s = a b Cin .Assign cy= (a.b) + (b.cin) + (cin.a). Step 6: End the process. THEORY: Full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the input variables denoted by A and B, represent the two significant bits to be added. The third input Cin represents the carry from the previous lower significant position SUM=A . B . Cin + A . B . Cin + A . B . Cin + A . B . Cin Cin=Cin (A B) Cout=A.B+A.Cin+B.Cin

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full is Port ( a,b,cin : in STD_LOGIC; s,c : out STD_LOGIC); end full; architecture Behavioral of full is begin s<=a xor b xor cin; c<=(a and b)or(b and cin)or(cin and a); end Behavioral; RESULT: Thus the full adder was designed VERLOG

RTL SCHEMATIC:

OUTPUT:

EX NO:3.c DATE : DESIGN OF D-FLIP FLOP USING VERILOG AIM: To design a D-Flip flop using VERILOG module. SOFTWARES REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1:Start the program. Step 2: Declare input ports d, reset, clk. Step 3: Declare output port q. Step 4: Assign always positive edge clock. Step 5: Begin the process. Step 6: Assign q-bar is not equal to q. Step 7: End the process. THEORY: In D-Flip Flop, the basic SR-Flip Flop is used with complemented inputs. The D-Filp Flop is similar to D-Latch except clock pulse is used instead of enable input. The D-Flip Flop can be realized and asQn+1 function follows D inputs at the positive edges of the clock pulse. The characteristics equation for the D-Filp Flop is Qn+1=D

PROGRAM: module df(d,clk,q,qbar); input d; input clk; output q; output qbar; reg q; assign qbar=~q; always@(posedge clk) end module;

RESULT: Thus the D-flip flop was designed using VERILOG module

RTL SCHEMATIC:

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EX.NO:3.d DATE: DESIGN OF T-FLIPFLOP USING VERILOG AIM: To design a T-flip flop using VERILOG module. SOFTWARE REQUIRED Xilinx. Modelsim. ALGORITHM: Step 1: Start the program. Step 2: Declare the input ports t, clk. Step 3: Declare output port q and q-bar. Step 4: Declare register q and assign q-bar is equal to not q. Step 5: Assign always positive edge clk. Step 6: Begin the process. Step 7: If clk is positive then q=~t. Step 8: End the process. THEORY: T or Trigger flip flop has only a single data input, a clock input and two outputs Q and Q-Bar. When T-input is in the 0 state prior to the clock pulse Q will not change with clocking. When clock=0 then Q=T i.e. no changes occurs. When clock=1 then Q=not (T). Thus the state is completed

PROGRAM: module tf(t,clk,q,qbar); input t; input clk; output q; output qbar; reg q; assign qbar=~q; always@(posedge clk) q<=~t end module. RESULT: Thus the T-flip flop was designed using VERILOG module

RTL SCHEMATIC:

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EX NO:4 DATE: WRITING TEST BENCHES USING VERILOG AIM: To write a test bench using VERILOG module. SOFTWARE REQUIRED: Xilinx. Modelsim. ALGORITHM: S te p 1: S ta r t t he pr o g r a m Step2: Declare the input ports i 0, i 1 , i 2 , i 3 , s 1, s 0. Step3: Declare output ports out. Step4: Begin the process. S te p 5: A s s i g n wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1);not (s0n,s0); and (y0,i0,s1n,s0); and (y1,i1,s1n,s0); and (y2,i2,s1,s0n); and (y3,i3,s1,s0); or(out,y0,y1,y2,y3); Step6: End the process.

THEORY: A Test bench isa virtual environment used to verify the correctness and soundness of a system for the gate level of RTL description is simulated to assure

and convert the following functionality of the test bench has three main purposes. 1.To generate stimulus for simulation. 2.To apply this stimulus to the module under test and collect response. 3.To compare output response with expected values.

PROGRAM: module mux4-to-1(out, i0,i1,i2,i3,s1,s0); output out; input i0,i1,i2,i3; input s1,s0; wire s1n,s0n; wire y0,y1,y2,y3; not (s1n,s1); not (s0n,s0); and (y0,i0,s1n,s0); and (y1,i1,s1n,s0); and (y2,i2,s1,s0n); and (y3,i3,s1,s0); or(out,y0,y1,y2,y3); end module. module stimulus; reg IN0,IN1,IN2,IN3; reg s1,s0;wire OUTPUT; mux 4-to-1 my mux(OUTPUT,IN0,IN1,IN2,IN3,s1,s0); initial begin IN0=1;IN1=0;IN2=1;IN3=0;

#100 display (IN0=%b,IN1=%b,IN2=%b,IN3=%b/n,IN0,IN1,IN2,IN3); s1=0;s0=0;

#100 $ display (s1=%b,s0=%b,OUTPUT=%b/n,s1,s0,OUTPUT); s1=0;s0=1; #100 $ display (s1=%b,s0=%b,OUTPUT=%b/n,s1,s0,OUTPUT); s1=1;s0=0 #100 $ display (s1=%b,s0=%b,OUTPUT=%b/n,s1,s0,OUTPUT); s1=1;s0=1; #100 $ display (s1=%b,s0=%b,OUTPUT=%b/n,s1,s0,OUTPUT); End end module RESULT: Thus the test bench for multiplexer using verilog was verified.

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EX NO:5 DATE: DESIGN AND IMPLEMENTATION OF ALU USING FPGA AIM To implement ALU using FPGA. SOFTWARE REQUIRED: Xilinx. Modelsim. ALGORITHM: Step 1:Start the program. Step 2:Declare the input variables. Step 3:When x1=1 arithmetic operation. Step 4:When x1=0 logicaloperation. Step 5:Example:When x1=1,s1=1,s2=1 and s3=1 it gives invalidOutput using conditional operator. Step 6:Example:When x1=0,s1=1,s2=1 and s3=0 it gives 2sCompliment Output using conditional operator.Similarly for Everyother input values. Step 7:Stop t he program PROGRAM: module a1(a,b,s1,s2,s3,x1,out); input[3:0]a,b; input s1,s2,s3,x1; output out; wire [7:0] out; wire [7:0] arith,log; wire [4:0] sum,diff; wire [7:0] prod,,squ;

wire [3:0] comp1,comp2; wire [3:0] and1,or1; wire [3:0] sr1,sl1,not1,invalid; assign sum=a+b; assign diff=a-b; assign prod=a*b; assign squ=a^b; assign comp 1=~a; assign comp 2=~a+8b00000001; assign invalid=8b00000000; assign and 1=a&b; assign sr 1=a<<2; assign or 1=a | b; assign not 1=~a; assign sl 1=a>>2; assign out=x1?arith:log ;assignarith =s1?(s2?(s3? invalid:comp 2):(s3? comp1:squ)): (s2?(s3? invalid:prod)(s3? diff:sum)); assign log=s1?(s2? invalid:invalid):(s3? invalid:sl1)):(s2? invalid:sl1)): (s2?(s3? sr1:not)(s3? or1:and 1)); end module RESULT: Thus the ALU was designed and implemented using FPGA and itsoutput was verified

RTL SCHEMATIC:

TRUTH TABLE:

EX.NO:6 DATE:

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING FPGA AIM: To implement a combinational circuits using FPGA. SOFTWARES REQUIRED: Xilinx. Modelsim. TOOLS REQUIRED: FPGA kit. ALGORITHM: HALF ADDER : Step 1: Start the program. Step 2: Declare the input ports a, b. Step 3: Declare output ports s, c. Step 4:Begin the process using behavioral architecture. Step 5:Assign s= a b. Step 6: Assign c=a.b. Step 7: End the process.

FULL ADDER :

Step 1: Start the program. Step 2: Declare the input ports a, b, Cin Step 3: Declare the output ports s, cy. Step 4: Begin the process using behavioral architecture. Step5:Assign s=a b cin Assign cy= (a.b) + (b.cin) + (Cin.a). Step 6: End the process. THEORY: HALF ADDER :

The half adder operation needs two binary inputs, augends and add end bits and two binary outputs are sum and carry. SUM Carry = = a a.b b

In multi-digit addition, we have to add two bytes along with the carry of the previous digit addition. Effectively such addition requires addition of three bits. This is not possible with the half adder

FULL ADDER: Full adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three inputs and two outputs. Two of the inputvariables denoted by A and B, represent the two significant bits to be added.The third input Cin represents the carry from the previous lower significant position.

Sum= A .B .Cin + A .B. Cin+ A. B .Cin + A.B.Cin Cin=Cin (A B)

Cout=A.B+A.Cin+B.Cin PROGRAM: HALF ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ha is Port ( a,b: in STD_LOGIC; s,c: out STD_LOGIC); end ha; architecture Behavioral of ha is begin s<=a XOR b; c<=a AND b; end Behavioral; FULL ADDER: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full is Port ( a,b,cin : in STD_LOGIC; s,cy : out STD_LOGIC); end full;

architecture Behavioral of full is begin s<=a xor b xor cin; cy<=(a and b)or(b and cin)or(cin and a); end Behavioral; RESULT: Thus the combinational circuit was designed and implementedusing FPGA and its truth table was verified.

RTL SCHEMATIC: HALF ADDER:

FULL ADDER:

TRUTH TABLE: HALF ADDER:

FULL ADDER:

EX.NO:7 DATE:

MODELING OF MOSFET USINGC AIM: To design MOSFET using C language COMPILER USED: C language ALGORITHM: Step1: Start the program. Step2: Enter your choice using switch statement. Step3: If the choice is 1, Get the values of Vgs, Vds and find out region in which nMOS work and find Ids using formula Ids=/2(Vgs-Vt)2(saturation) Ids=/2*2(Vgs-Vt) Vds-Vds2](linear) Ids=0 (cut off region). Step4: Print the value of Ids and the region which it operates. Step5: If the choice is 2, Get the value of Vgs, Vds and find out the region in which nMOS work and find Ids using formula Ids= /2(Vgs-Vt)2(saturation) Ids=/2*2(Vgs-Vt)Vds-Vds2] (linear) Ids=0 (cutoff region). Step6: Print the value of Ids and the region in which itoperates. Step7: Stop the program THEORY: MOSFET is the common term for the Insulator Gate Field EffectTransistor (IGFET). There are two basic forms of MOSFET (i)Enhancement MOSFET (ii)Depletion MOSFET.

By applying a transverse electric field across an insulator, deposited on the semi conducting material can be controlled. In depletion MOSFET, the controlling electric field reduces the number of majority carriers available for conduction, whereas in the enhancement MOSFET, application of electric field causes an increase in majority carrier density in the conducting region of the transistor PROGRAM: #include<stdio.h> #include<math.h> void main() { float e0=8.85E-14,eins=4.0,un=650,up=240,tox=225.00E10,Vtn=0.622490, Vtp=0.632025,W=0.125,L=0.375; float K,Ids,Vgs,Vds,b;int x; printf("\n Enter your choice:1-nmos,2-pmos"); scanf("%d",&x); switch(x) { case 1: printf("\n Enter Vgs,Vds\n"); scanf("%f%f",&Vgs,&Vds);K=((eins*e0*un)/tox); b=K*(W/L); if(Vds>=(Vgs-Vtn)&&Vgs>Vtn){Ids=b*((Vgs-Vtn)*(Vgs-Vtn)); printf("\nsaturation region\nVgs=%f\nVds=%f\nIds=%f",Vgs,Vds,Ids); } else if(Vds<=(Vgs-Vtn)&&Vgs>=Vtn) { Ids=(b/2)*((2*(Vgs-Vtn)*Vds)-(Vds*Vds)); printf("\nLinear region\nVgs=%f\nVds=%f\nIds=%f",Vgs,Vds,Ids); } else If(Vgs<Vtn){Ids=0; printf("\ncutoffregion\nVgs=%f\nVds=%f\nIds=%f",Vgs,Vds,Ids);} break; case 2: printf("Enter Vgs and Vds\n");

scanf("%f%f",&Vgs,&Vds);K=((eins*e0*up)/tox); b=K*(W/L);if(Vds>=(VtpVgs)&&(Vgs<Vtp)){Ids=b*((Vgs-Vtp)*(Vgs-Vtp)); printf("\n Saturationregion\nVgs=%f\nVds=%f\nIds=%f\n",Vgs,Vds,Ids); } else if(Vds<=(Vtp-Vgs)&&Vgs<Vtp){Ids=(b/2)*((2*(Vgs-Vtp)*Vds)(Vds*Vds)); printf("\nLinear region\nVgs=%f\nVds=%f\nIds=%f\n",Vgs,Vds,Ids); } else if(Vgs>Vtp){Ids=0; printf("\nCutoff region\nVgs=%f\nVds=%f\nIds=%f\n",Vgs,Vds,Ids);} break; default: printf("\ninvalid choice"); } } RESULT: Thus MOSFET was modelled using c successfully

OUTPUT: Enter your choice:1-nmos,2-pmos 1 Enter Vgs,Vds 10 2 Linear region Vgs=10.000000 Vds=2.000000 Ids=0.057116

Enter your choice:1-nmos,2-pmos 2 Enter Vgs and Vds 2 3 Cutoff region Vgs=2.000000 Vds=3.000000 Ids=0.000000 Enter your choice:1-nmos,2-pmos 1 Enter Vgs, Vds 0.2 3 cutoff region Vgs=0.200000 Vds=3.000000 Ids=0.000000 Enter your choice:1-nmos,2-pmos 3 invalid choice

EX NO:8 DATE :

DESIGN OF FFT USING MATLAB AIM: Toimplementthe FFT for digital filter using Matlab. SOFTWARE REQUIRED: Matlab. ALGORITHM: Step 1:Start the program. Step 2: Get the input sequence of DFT. Step 3: Enter the number of points in the DFT. Step 4: If the length (Xn) is less than n then go to step 6. Step 5: Find the FFT sequence. Step 6: Display N must be greater than or equal to 1. Step 7: End the program.

THEORY: The fast fourier transform is a highly efficient finite series procedure for computing discrete Fourier transform of a finite series andrequires less no of computations than that of DFT the FFT is based on thedecomposition and breaking the transform and combining them to get thetotal transform. This algorithm makes use of the symmetric and periodicity properties of twiddle factor to reduce the DFT computation time. The FFTalgorithm provides speed, increase factors when compared with DFT

X(k)= PROGRAM:

k=0,1,2,.,N-1

clc; clear; close all; fs=1000; f=100; t=0:1/fs:1; sine=sin(2*pi*f*t); X=fft(sine); b=abs(X); subplot(2,1,1); stem(b); title(MAGNITUDE RESPONSE); ylabel(amplitud-); xlabel(n--); c=(180/pi)*angle(X); subplot(2,1,2); stem(c); title(PHASE RESPONSE); ylable(amplitude); xlable(n-);

RESULT: Thus the program for FFT was done and output was verified using MATLAB

OUTPUT:

EX NO:9 DATE : DESIGN OF DIGITAL FILTER USING MATLAB : AIM: Toimplementthe FFT for digital filter using Matlab. SOFTWARE REQUIRED: Matlab. ALGORITHM: FIR: Step 1:Open a new MATLAB file. Step 2: Clear command window, clear screen and close all plots. Step 3: Generate a sine wave with f1 and f2,f1 in pass band andf2 in stop band. Step 4: Generate a filter coefficient for a given filter specifications using fir1 and assign a=1 Step 5: Apply filter coefficient and input to the filter in build function in MATLAB Step 6: Find the fft of input and output of the filter and plot the absolute values of the fft coefficients Step 7:End the program. IIR: Step 1:Open a new MATLAB file. Step 2: Clear command window, clear screen and close all Plots. Step 3:Specify the sampling frequency. Step 4:Find the angular frequency for stop band and pass band frequency. Step 5:Using buttord inbuilt function find the order of the filter And the frequency Wn.

Step 6:Using butter inbuilt function generate the polynomials For IIR filter. Step7:Generate a input for IIR filter. Step 8:Using the filter function filter the input. Step 9:Plot the magnitude spectrum of the input and output. THEORY: FIR: The FIR filters are always stable.The FIR filter with exactly linear phase can easily be designed.They can be realized in both recursive and no recursive structures. FIR filters are free of the the limit cycle oscillations, when implemented on a finite-word length digital system. Excellent design methods are available for various kinds of FIR filter. But the implementation of narrow transition band. FIR filter are very closely as it required considerable more arithmetic operations and hardware components such as multipliers, adders and delay elements. Memory requirements and execution time are very high. The transfer function of a filter is given by H(z))= IIR: IIR filter are of recursive type, where by the present output samples depends on the present input, past input samples and output samples. The impulse function h(n) for a realization filter is h(n)=0 for n<=0 and for stability, it must satisfy the condition = | |

PROGRAM: FIR: clc; clear; close all; N=31; w=0.25; fs=8000; f1=5500; f2=500; t=0:1/fs:1;x=sin(2*pi*f1*t)+sin(2*pi*f2*t); b=fir1(N-1,w,'high'); a=1; wn=hamming(31); b=b*wn; OU=filter(b,a,x); y=abs(fft(x)); subplot(2,1,1); stem(y); title('input spectrum'); d=abs(fft(OU)); subplot(2,1,2); stem(d); title('filtered output');

IIR: clear all; alphap=4; alphas=30; fp=400; fs=800; f=2000;omp=2*fp/f;

oms=2*fs/f; [n,wn]=buttord(omp,oms,alphap,alphas) [b,a]=butter(n,wn); w=0:0.01:pi; [h,om]=freqz(b,a,w,'whole'); m=abs(h); an=angle(h); subplot(2,1,1); plot(om/pi,20*log(m)); grid;ylabel('gain in db'); xlabel('normalised frequency'); subplot(2,1,2); plot(om/pi,an); grid; ylabel('phase in radians'); xlabel('normalised frequency');

RESULT: Thus the program for FIR and IIR was done and output was verifiedusing the MATLAB software

OUTPUT: FIR:

IIR:

EX.NO:10 DATE: IMPLEMENTATION OF MAC UNIT USING FPGA AIM: To implement MAC unit using FPGA. SOFTWARE REQUIRED: Xilinx TOOLS REQUIRED: FPGA kit ALGORITHM: Step 1: Start the program. Step 2: Declare the input variables. Step 3: When x1=1 arithmetic operation. Step 4: When x1=0 logical operation. Step 5: Example:When x1=1,s1=1,s2=1 and s3=1 it gives invalid Output using conditional operator. Step 6: Example:When x1=0,s1=1,s2=1 and s3=0 it gives 2sCompliment Output using conditional operator.Similarly for Everyother input values. Step 7: Stop the program. THEORY: In the majority of digital signal processing (DSP) applications the critical operations usually involve many multiplications and/or accumulations. For realtime signal processing, a high speed and high throughput Multiplier Accumulator (MAC) is always a key to achieve a high performance digital signal processing system. In the last few years, the main consideration of MAC design is to enhance its speed. This is because; speed and throughput rate is always the concern of

digital signal processing system. But for the epoch of personal communication, low power design also becomes another main design consideration. This is because; battery energy available for these portable products limits the power consumption of the system. Therefore, the main motivation of this work is to investigate various VLSI Design and Implementation of Low Power MAC Unit with Block Enabling Technique PROGRAM: module MAC(clk,rst,a,b,z);i nput clk,rst; input[2:0] a,b; output z; wire[5:0] w; multiplier U1(.a(a),.b(b),.p(w)); pipo U2(.RIN(w),.clk(clk),.rst(rst),.ROUT(z)); end module module multiplier(a,b,p); input[2:0] a,b; output[5:0] p; wire[7:0] u; wire[1:0] su; wire[8:0] i; and(p[0],a[0],b[0]); and(u[0],a[1],b[0]); and(u[1],a[2],b[0]); and(u[2],a[0],b[1]); and(u[3],a[1],b[1]); and(u[4],a[2],b[1]); and(u[5],a[0],b[2]); and(u[6],a[1],b[2]); and(u[7],a[2],b[2]); hadd h1(.l(u[0]),.m(u[2]),.sum(p[1]),.cry(i[0])); hadd h2(.l(i[0]),.m(u[1]),.sum(su[0]),.cry(i[1])); hadd h3(.l(u[3]),.m(u[5]),.sum(su[1]),.cry(i[2])); hadd h4(.l(su[0]),.m(su[1]),.sum(p[2]),.cry(i[6])); hadd h5(.l(i[1]),.m(i[2]),.sum(i[5]),.cry(i[6]));

or(i[7],i[5],i[4]); fadd f3(.d(i[7]),.e(u[4]),.cin(u[6]),.s(p[3]),.cout(i[8])); fadd f4(.d(i[8]),.e(i[6]),.cin(u[7]),.s(p[4]),.cout(p[5])); endmodule module pipo(RIN,clk,rst,ROUT); input[5:0] RIN; input clk,rst; output[5:0] ROUT; r eg [ 5 :0 ] R O U T ; always @(posedge clk or negedge rst) begin if(!rst) begin ROUT<=6'b000000; End else begin ROUT<=RIN; End End End module module fadd(s,cout,d,e,cin); input d,e,cin; output s,cout; assign s=(d^e^cin); assign cout=((d&e)|(e&cin)|(d&cin)); endmodule module hadd(sum,cry,l,m); input l,m; output sum,cry; wire sum,cry; assign sum=(l^m); assign cry=(l&m); endmodule

RESULT: Thus the MAC unit was implemented using FPGA RTL SCHEMATIC: