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Caspian Journal of Applied Sciences Research, 1(11), pp.

92-100, 2012
Available online at http://www.cjasr.com
ISSN: 2251-9114, 2012 CJASR
92

Design of a Statcom-Based Harmonic-Free Static VAR Compensator for Load
Balancing Purposes

Abdulkareem Mokif Obais
*
, Jagadeesh Pasupuleti

Department of Electrical Power Engineering, College of Engineering, Universiti Tenaga Nasional,
Selangor, Malaysia
*Corresponding Author: karimobais@yahoo.com

In this paper, a bipolar (capacitive and inductive) static VAR compensator is built on the basis of statcom
fundamentals. The designed compensator exchanges wide range of pure reactive power with the ac supply
without significance of real power contribution. No harmonic generation is associating the compensation process,
thus no filtering is required. The compensator is built of two single-phase statcoms connected in parallel. One of
them represents a static linear synchronous condenser at the ac supply fundamental frequency, while the other
represents a harmonic-free linearly and continuously controlled reactor. Each statcom is built of a half-bridge
voltage source inverter shunted by two dc capacitors and exchanges pure reactive power with the ac supply
through a series reactor. The reactive power of each statcom is controlled linearly by the modulation index of its
voltage source inverter. A demonstration system for this compensator is designed and tested on PSpice.

Key words: Controlled reactor, Load balancing, Power quality, Statcom, Static VAR compensator

1. INTRODUCTION

Load balancing requires continuous control of
static VAR compensators in capacitive and
inductive modes of operation (Chen, Lee and Chen
1999; Lee and Wu 2000; Valderrama, Mattavelli
and Stankovic 2001; Xu et al. 2010). Synchronous
condensers can be employed as continuously
controlled reactive power compensators in
balanced systems, but static VAR compensators
are superior to them due their fast responses, low
operating losses, and the possibility of being
employed in applications requiring unbalanced
reactive power control (Bimal 2006; Teleke et al.
2008). Conventional static VAR compensators
constructed of fixed or switched capacitors and
thyristor controlled reactors can be employed as
bipolar (capacitive and inductive) reactive power
compensators for load balancing purposes (Best
and Zelaya-De La Parra1996; Gyugyi 1988; Lee
and Wu 2000; Morbn, Ziogas and Joos 1993).
Such kinds of compensators release disturbing
harmonics and employ natural commutated
medium speed switching devices (IEEE PES
Harmonic Working Group 2001). Static
compensators (statcoms) require forced
commutation fast switching devices and have fast
responses compared to conventional static VAR
compensators. A statcom is either a voltage source
converter loaded by a dc capacitor and exchange
reactive power with the ac supply through a small
reactor, or a current source converter loaded by a
dc reactor (Bimal 2006; Tavakoli Bina and Hamill
2005).
Statcoms under the above definitions release
wide spectrums of harmonics and exchange
unnecessary real power with ac supplies (IEEE
PES Harmonic Working Group 2001).
Consequently, the above compensators usually
require harmonics filtering circuitries installed
together with them. Harmonics can also be
minimized by employing multilevel statcoms
which results in more complicated systems
(Hadjeri, Ghezal and Zidi 2008). Harmonics
minimization Techniques cause more no load
operating losses.
In this study, a linearly and continuously
controlled bipolar (capacitive and inductive) static
VAR compensator built on the basis of single-
phase statcom concept will be presented. The new
configuration will be capable to exchange pure
reactive power with the ac supply at its
fundamental frequency without real power
contribution or harmonics association. The
compensator that will be devised requires no
harmonics filtering and dissipates negligible no
load operating losses.

2. THE PROPOSED SINGLE-PHASE
STATCOM

The proposed single-phase statcom is shown in
Fig. 1a. It is simply a single-phase half-bridge
voltage source inverter loaded by two dc capacitors
C
1
and C
2
and fed by the series reactor L. The
Obais and Pasupuleti
Design of a Statcom-Based Harmonic-Free Static VAR Compensator for Load Balancing Purposes
93
resistor r represents the self resistance of the series
reactor. The statcom configuration in Fig. 1a can
be modified by dividing the series reactor L into
two identical reactors and equipping the new
configuration with a series bandpass filter as
shown Fig. 1b. The filter is tuned at the carrier
frequency f
C
which represents the frequency of the
triangular signal employed in the generation of the
sinusoidal pulse width (SPWM) signals required
for triggering the single-phase half-bridge voltage
source inverter. This helps to smooth the envelope
of the statcom current. The ac supply (vs) is a
sinusoidal voltage having amplitude of V
m
and
angular frequency of . The bandpass filter is
designed such that it draws negligible current from
the ac supply.


Fig. 1: The proposed statcom configurations: (a) simple and (b) modified.

In Fig. 1a, the capacitor C
1
will charge to +V
m

through the series reactor and the diode D
1
,
whereas C
2
will charge to V
m
. The insulated gate
bipolar transistors (IGBTs) S
1
and S
2
are triggered
by V
S1
and V
S2
respectively as shown in Fig. 2a.
These signals are produced by comparing the
modulating signal (v
mod
) with the triangular signal
(v
C
). v
mod
is a sinusoidal voltage proportional to v
S

and in phase with it. If a parameter m is defined as
the normalised amplitudes ratio of v
mod
to v
C,
, then

t m v e sin
mod
= (1)

Here m represents the inverter modulation index. If
the triangular signal frequency f
C
is very much
greater than the modulating signal frequency f
which is equal to /2, then at any t, S
1
will
conduct for a period of time of t
1
, while S
2
will
conduct for a period of time of t
2
as shown in Fig.
2b. The following can be deduced from this figure
C
T t t = +
2 1
(2)
( ) t m
T
t m
T T
t
T
t
C
C C
C
e
e
sin 1
2

sin
4
2
2

' 2
2
1 2
=
|
.
|

\
|
=
=
(3)
( ) t m
T
t T t
C
C
e sin 1
2
2 1
+ = = (4)
A
N
1 2
0
1
C
2
C
L
r
S
V
1
S
2
S
1
D
2
D
(a)
A
1 2
0
1 2
1
2
B
a
n
d
p
a
s
s

f
i
l
t
e
r

t
u
n
e
d

a
t

f
c
1
C
2
C
2 / L
F
C
2 / L 2 / r 2 / r
F
L
F
r
S
V
1
S
2
S
1
D
2
D
N
(b)
Caspian Journal of Applied Sciences Research, 1(11), pp. 92-100, 2012
94

Fig. 2: The statcom sinusoidal pulse width modulation (SPWM). (a) Switching devices triggering signals and (b) their
conduction periods

If the term (msint) is positive, then t
1
is
greater than t
2
and vice versa. The instantaneous
voltage (v
i
) generated by the inverter at any t, is
shown in Fig. 3. The average of v
i
at any t is
designated by V
i
and is calculated as follows


( )
( ) sin
1

1 1
2 1
0 0 0
2 1
t mV t V t V
T
dt V dt V
T
dt v
T
V
m m m
C
t
m
t
m
C
T
i
C
i
C
e = =
|
|
.
|

\
|
+ = =
} } }
(5)

Fig. 3: The instantaneous voltage (vi) generated by the inverter at certain t.

The envelope scanned by V
i
from 0 to 2,
represents the inverter voltage fundamental (v
1
)

which is synchronized with the ac supply
instantaneous voltage v
S
and running at the supply
fundamental frequency f. The difference between v
i

and v
1
is the source of all current harmonics, thus
the circuit of Fig. 1a can be modelled as shown in
Fig. 4a. The capacitance C
T
represents C
1
//C
2
.The
current source i
H
includes all the possible harmonic
current components starting from the odd multiples
of the ac supply fundamental f and ending with the
multiples of the carrier frequency f
C
. The current
source i
1
is a pure capacitive current at the ac
supply fundamental f and is given by

( ) 2 / sin
1
t e e + = t C mV i
T m
(6)

The statcom approached in this paper is
designed such that

2
2
1
r L
C
T
>>
|
|
.
|

\
|
e
e
(7)
Time
C
v mod
v
1 S
V
2 S
V
Time
0s 10ms 20ms
V(U9:-) V(U9:+)
-1.0V
0V
1.0V
Time
0s 10ms 20ms
V(R1:2)
0V
2.5V
5.0V
Time
0s 10ms 20ms
V(U10C:A)
0V
2.5V
5.0V
(a)
0
-1
+1
t' 0
t m e sin
C
v
mod
v
1
t
2
t
1 S
V
2 S
V
4
C
T
2
C
T
4
3
C
T
C
T
1
' t
1
' t
1
' t
(b)
t
2
t
1
t
m
V +
m
V
C
T
Obais and Pasupuleti
Design of a Statcom-Based Harmonic-Free Static VAR Compensator for Load Balancing Purposes
95
L C
T
2
5 . 0 e s (8)

The constraint defined by (7) guaranties pure
reactive current at the ac fundamental, while the
constraint defined by (8) makes L suppress all
components of i
H
starting from third harmonic.
Consequently, the statcom modeling of Fig.4a can
be simplified as shown in Fig. 4b.

Fig. 4: The proposed single-phase statcom modeling: (a) exact and (b) simplified

The statcom impedance (Z
S
) is given by

e e Z =
T S
C L Z / 1 (9)

Where, is the impedance angle. If it is +90
0
,
then the statcom current i
S
will be pure inductive,
whereas for =-90
0
, i
S
will be pure capacitive. The
current i
S
can be given by

( ) ( )
T
m
T
m m
S
S
S
C
L
t V m
C
L
t mV t V
Z
v v
i
e
e
e

e
e
e e
1
sin 1

1
sin sin
1


=
Z

=

=
(10)

The statcom current can be linearly varied from
zero to its maximum value by varying the
modulation index m from unity to zero.

3. THE PROPOSED BIPOLAR STATIC VAR
COMPENSATOR

Two statcoms of Fig. 1a are connected in parallel
as shown in Fig. 5, to build a single-phase static
VAR compensator controllable linearly and
continuously in capacitive and inductive modes of
operation. The left statcom formed by L
1
, S
1
, S
2
,
C
1
, and C
2
is designed such that it can draw pure
capacitive current from v
S
, while the right statcom
is designed to draw pure inductive current. Each of
the reactors L
1
and L
2
must be divided into two
identical reactors as in Fig. 1b. Both statcoms must
comply with the constraints specified by (7) and
(8) and must be capable of handling the same
maximum reactive currents. Consequently, it can
be written

( ) ( )
4 3 2 1 2 1
/ 1 / 1 C C L
V
L C C
V
m m
+
=
+ e e e e
(11)

S S
N
1 2
A
0
S
v
L
r
H
i
1
i
T
C
S
i
(a)
1 2
0
S
v
L
1
v
T
C
S
i
(b)
Caspian Journal of Applied Sciences Research, 1(11), pp. 92-100, 2012
96

Fig. 5: The proposed single-phase statcom-based static VAR compensator

If the reactive current demand is capacitive,
then the switching devices S
1
and S
2
will be
activated, whereas S
3
and S
4
will be off. Therefore
the left statcom will draw pure capacitive current
(i
SC
) proportional to the reactive current demand.
In case of inductive reactive current demand, the
left statcom will be relaxed and the right statcom
will satisfy the demand by drawing pure inductive
current (i
SI
).

4. COMPENSATOR CIRCUIT DESIGN

A single-phase power system of 220V (RMS
value) and 50Hz was chosen as the ac supply v
S
of
the proposed compensator. The amplitude V
m
of
the system voltage is 311V. The compensator is
designed such it can handle maximum peak
reactive current of 200A for capacitive and
inductive modes of operation. The reactors L
1
and
L
2
were chosen to have resistance to inductance
ratio of 0.01(/mH). Choosing
2
L
1
(C
1
+C
2
) =0.51
and applying (11), the following basic design
parameters were obtained: C
1
=C
2
=500F,
L
1
=5.2mH, C
3
=C
4
=1000F, and L
2
=10mH. A
complete system was designed on the computer
program PSpice using aiding literatures (Bimal
2006; Miller 1982; Skvarenina 2002) and
datasheets of electronic parts employed in
electronic circuitries. The circuit diagram of the
designed compensator is shown in Fig. 6. Each of
the reactors L
1
and L
2
of Fig. 5 are divided into two
identical reactors in Fig. 6. A triangular waveform
of amplitude of 2V and f
C
of 2.5 KHz was chosen
as the carrier of the SPWM circuit. The
compensator was equipped with two bandpass
filters having the parameters L
F
=723.7H,
r
F
=0.02, and C
F
=5F. The controlling voltage of
this system is the voltage V
d
which is proportional
to the reactive current demand. The range of V
d
is -
4V to +4V. Its negative sign means that the
reactive current demand is inductive, while
positive sign means capacitive current demand.
The polarity of this voltage (V
P
) will be invested in
the triggering circuit to determine which statcom
should be activated, whereas its absolute value (V
a
)
will determine the output voltage v
mod
of the linear
gain-controlled amplifier which was designed by
investing the most linear portion of the
characteristics of a fast junction field effect
transistor. The amplitude of v
mod
can be controlled
linearly from zero to 2V by varying V
a
from 0 to
4V. Consequently, the modulation index m of the
activated statcom can be varied linearly from unity
to zero as the absolute of V
d
varies from 0 to 4V.

5. RESULTS AND DISCUSSION

The compensator was tested on PSpice for zero
reactive current demand. Fig. 7a shows the results
of that test which corresponded to V
d
=0 and m=1.
Many tests were preceded during reactive current
demand variations from 0 to compensator
maximum rating (200A peak value) in capacitive
and inductive modes of operation. In Fig. 7b, the
measured values of the compensator current are
plotted against reactive current demand in
capacitive and inductive modes of operation. This
figure obviously reflects the linearity of the
proposed compensator. Note that the minus sign of
current in Fig. 7b means inductive, while positive
sign means capacitive.

0
1 2 1 2
1
L
1
r
2
L
2
r
1
C
3
C
2
C
4
C
1
s
4
s
3
s
2
s
S
v
S
i
SC
i
SI
i
Obais and Pasupuleti
Design of a Statcom-Based Harmonic-Free Static VAR Compensator for Load Balancing Purposes
97

0
L3
5mH
1 2
R52
0.05
0
VS1 +5V
U15A
CLC428/CL
OUT
1
V
+
8
V
-
4
+
3
-
2
G2
G1
k1
k2
0
3
1
Capacitive statcom
3
1
Power circuit of statcom-based capacitive and inductive static VAR compensator
VL
VL
FREQ = 50Hz
VAMPL = 311V
VOFF = 0
Inductive statcom
U13A
74ACT04
1 2
D1
U13B
74ACT04
3 4
C3
1000uF
C4
1000uF
G3
U13C
74ACT04
5 6
k4
G4
k3
3
1
3
1
L1
2.6mH
1 2
R50
0.026
Sinusoidal pulse width modulation circuit
Vc
D2
S3 driving circuit S4 driving circuit
VS4 VS3
U10
A4N26
Q7
Q2N2222A
Q9
Q2N2222A
R31
22k
R32
560
R48
10k
R39
150
L2
2.6mH
1 2
R43
1
Q11
Q2N3906
R51
0.026
V5
15V
0
G3
k3
R30
33
U11
A4N26
Q8
Q2N2222A
Q10
Q2N2222A
R33
22k
R34
560
R49
10k
R40
150
R44
1
Q12
Q2N3906
V6
15V
U14A
74ACT08
1
2
3
G4
k4
0
R36
33
+5V
-5V
0
R18
5k
U14C
74ACT08
10
9
8
U3
max998/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
R2
5k
R21
40.5k
G1
VS2 +5V
R54
0.02
U16A
CLC428/CL
OUT
1
V
+
8
V
-
4
+
3
-
2
C5
5uF
L5
723.7uH
1
2
U14B
74ACT08
4
5
6
0
Vd
1V
U6A
DG303A
IN1
5
OUT1
4
VC
6
V
D
D
1
6
V
S
S
1
0
GND
7
IN2
2
OUT2
3
+5V
0
V3
5V
0
-5V
V4
5V
U14D
74ACT08
13
12
11
S1
CM400HA-24H
0
R45
270
-5V
R37
70k
R46
5k
0
0
Va
+5V
U7
max989/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
0
R6
1k
R1
10k
Vp
0
U1
max989/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
-5V
+5V
-5V
+5V
R16
5k
R7
5k
0
S2
CM400HA-24H
S1 driving circuit S2 driving circuit
VS2 VS1
U4
A4N26
Q1
Q2N2222A
Q3
Q2N2222A
R9
22k
R4
560
R22
10k
S3
CM400HA-24H
R14
82
R19
1
Q5
Q2N3906
V1
15V
k1
0
R8
33
U5
A4N26
Q2
Q2N2222A
Q4
Q2N2222A
R5
22k
R12
560
R23
10k
+5V VS3
R15
82
U15B
CLC428/CL
OUT
7
V
+
8
V
-
4
+
5
-
6
R20
1
Q6
Q2N3906
V2
15V
VS4
R24
560k
+5V
-5V
G2
k2
U16B
CLC428/CL
OUT
7
V
+
8
V
-
4
+
5
-
6
R25
1k
0
0
R27
4k
R11
33
Vmod
R28
2.8k
0
0
R41
5k
+5V
J1
J2N3458
-5V
R29
30k
R42
680k
-5V
U8
max998/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
S4
CM400HA-24H
R35
560k
R26
560k
0
-5V
+5V
R47
1k
R38
1k
U9
max998/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
R55
0.02
D3
C6
5uF
L6
723.7uH
1
2
+5V
VS1
TD = 0
TF = 0.1999m
PW = 0.0001m
PER = 0.4m
V1 = -2
TR = 0.2m
V2 = 2
0
Compensator triggering circuit
-5V
D4
Linear gain-controlled amplifier
Vmod
Absolute voltage determination circuit
C1
500uF
C2
500uF
Triangular waveform (2.5KHz)
U12
max998/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
0
R13
100
R3
12k
0
R10
65k
R17
1k
VL +5V
-5V
0
U2
max998/mxm
+
3
-
2
V
+
7
V
-
4
OUT
6
0
L4
5mH
1 2
R53
0.05
S
i
S
v

Fig. 6: PSpice design of statcom-based bipolar (capacitive and inductive) static VAR compensator

Caspian Journal of Applied Sciences Research, 1(11), pp. 92-100, 2012
98

(a)



(b)
Fig. 7: Compensator response to: (a) zero reactive current demand and (b) reactive current demand variations of -200A
to +200A (peak values).

The compensator instantaneous voltage v
S
and
current i
S
in capacitive and inductive modes of
operation are shown in Fig. 8a and Fig. 8b
respectively. It is obvious that absolute values of
the voltage V
d
in Fig. 6, control the modulation
index m which determines the absolute value of the
compensator current, while the polarity of V
d

determines the compensator current phase angle
which is +90
0
for positive sign and -90
0
for
negative sign.

6. CONCLUSION

In this paper, a bipolar (capacitive and inductive)
static VAR compensator is designed on the basis of
statcom concept. The current of this compensator
is pure reactive and its waveform is pure sinusoid
running at the ac supply fundamental frequency
without any sort of harmonics association and real
power contribution. The configuration and the
control strategy adopted in this paper, present
satisfactory replacements of technologies requiring
the building of multilevel converters and high
power harmonic filters. The proposed compensator
can be represented by a bipolar linear susceptance
that offers the possibility of delta connection which
can be employed in load balancing techniques.
Overall, the proposed compensator can be
considered as a parallel combination of static
synchronous condenser and reactor having
equivalent reactive ratings and offering the
possibility of wide zone of linear and continuous
control.
Time
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
1 m , 0 = =
d
V
Obais and Pasupuleti
Design of a Statcom-Based Harmonic-Free Static VAR Compensator for Load Balancing Purposes
99


Fig. 8: The compensator voltage and current waveforms in: (a) capacitive mode and (b) inductive mode of operation.

REFERENCES

Best R, Zelaya-De La Parra H (1996). Transient
Response of a Static Var Shunt
Compensator. IEEE Transaction on Power
Electronics, 11: 489-494.
Bimal K.B (2006). Power Electronics and Motor
Drives. Elsevier Inc, USA.
Chen J-H, Lee W-J, Chen, M-S (1999). Using a
Static Var Compensator to Balance a
Distribution System. IEEE Transaction on
Industry Applications, 35: 298-304.
Gyugyi L (1988). Power Electronics in Electric
Utilities: Static Var Compensators.
Proceeding of the IEEE, 76: 483-494.
Hadjeri S, Ghezal F, Zidi S.A (2008). Simulation
of a Three-Level-48 Pulses STATCOM.
ACTA Electrotehnica, 49: 189-193.
Time
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
75 . 0 m , 1 = + = V V
d
5 . 0 m , 2 = + = V V
d
S
v
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
Time
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
25 . 0 m , 3 = + = V V
d
Time
Time
0 m , 4 = + = V V
d
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
(a)
S
i
S
v
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
75 . 0 m , 1 = = V V
d
Time
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
5 . 0 m , 2 = = V V
d
Time
S
i
S
v
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
25 . 0 m , 3 = = V V
d
Time
S
v
S
i
(A) Current
(V) Voltage
Time
300ms 320ms 340ms 360ms
-I(VL) V(VL)
-200
0
200
0 m , 4 = = V V
d
Time
(b)
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