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IN - SystemVerilog Functional Coverage 11/12/12

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EXPLICIT BIN CREATION

Index Introduction Cover Group Explicit bin creation is recommended method. Not all values are interesting or Sample relevant in a cover point, so when the user knows the exact values he is going to Cover Points Coverpoint Expression cover, he can use explicit bins. You can also name the bins. Generic Coverage Groups Coverage Bins Explicit Bin Creation program main; Transition Bins bit [0:2] y; Wildcard Bins bit [0:2] values[$]= '{3,5,6}; Ignore Bins Illegal Bins covergroup cg; Cross Coverage cover_point_y : coverpoint y { Coverage Options bins a = {0,1}; Coverage Methods bins b = {2,3}; System Tasks bins c = {4,5}; Cover Property bins d = {6,7}; } endgroup cg cg_inst = new(); initial foreach(values[i]) begin y = values[i]; cg_inst.sample(); end endprogram
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Verilog
Verification Verilog Switch TB Basic Constructs

In the above example, bins are created explicitly. The bins are named a,b,c and d.

OpenVera

Coverage report: ------------------VARIABLE : cover_point_y Switch TB Expected : 4 RVM Switch TB Covered : 3 RVM Ethernet sample Percent: 75.00
Constructs

Specman E Interview Questions

Uncovered bins -------------------a Covered bins -------------------b c d

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program main. bin a is array of 8 bins and each bin associates to one number between 0 to 7. must follow the bin name.sample(). bit [0:2] values[$]= '{3. bit [0:3] y. Coverage report: -------------------VARIABLE : cover_point_y Expected : 8 Covered : 3 Percent: 37. a number can be specified inside the square brackets. end endprogram In the above example. cover_point_y : coverpoint y { bins a[4] = {[0:7]}. covergroup cg.5. cg_inst. program main. } endgroup cg cg_inst = new(). bit [0:2] y. .50 Uncovered bins ------------------a_0 a_1 a_2 a_4 a_7 Covered bins ------------------a_3 a_5 a_6 To create a fixed number of bins for a set of values. bit [0:2] values[$]= '{3. covergroup cg.Array Of Bins To create a separate bin for each value (an array of bins) the square brackets.6}.6}. initial foreach(values[i]) begin y = values[i]. cover_point_y : coverpoint y { bins a[] = {[0:7]}.5. [].

we have shown the number bins to be fixed to size 4. variable y is 4 bit width vector. end endprogram In the above example. we have giving the interested range as 0 to 7. } endgroup cg cg_inst = new(). initial foreach(values[i]) begin y = values[i].TESTBENCH. In this example.IN .WWW.00 Uncovered bins ------------------a[0:1] Covered bins -----------------a[2:3] a[4:5] a[6:7] Default Bin The default specification defines a bin that is associated with none value bins. So the coverage report is calculated over the range 0 to 7 only.SystemVerilog Functional Coverage 11/12/12 } endgroup cg cg_inst = new(). The default bin catches the values of the coverage point within any of t he defined bins. covergroup cg. testbench.6}.html 3/4 . the coverage calculation point shall not take into account the coverage captured by the default of the defined that do not lie for a coverage bin. program main.5. But in the cover point bins. bit [0:2] values[$]= '{3.in/CO_08_EXPLICIT_BIN_CREATION. Coverage report: -------------------VARIABLE : cover_point_y Expected : 4 Covered : 3 Percent: 75. bins d = default. initial foreach(values[i]) begin y = values[i]. However. bit [0:3] y. cg_inst. Total possible values for this vector are 16.sample(). cover_point_y : coverpoint y { bins a[2] = {[0:4]}.

we have specified only 2 bins to cover values from 0 to 4.IN . Rest of values are covered in default bin <93>d<94> which is not using in calculating the coverage percentage.TESTBENCH.in ::Disclaim e r testbench.SystemVerilog Functional Coverage 11/12/12 cg_inst.sample().00 Uncovered bins -----------------a[0:1] Covered bins ---------------a[2:4] Default bin ----------------d << PREVIOUS PAGE TOP NEXT PAGE >> copyr ight © 2007-2017 :: all r ights r eser ved www.html 4/4 .te stbe nch. end endprogram In the above example.WWW. Coverage report: -------------------VARIABLE : cover_point_y Expected : 2 Covered : 1 Percent: 50.in/CO_08_EXPLICIT_BIN_CREATION.

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