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Lendi Institute of Engineering and Technology, Vizianagaram 1

Department of Electronics and Communications Engineering
Experiment No:1
LINEAR WAVE SHAPING
AIM : a) To study the response of RC Low pass circuit and to determine
rise time for a square wave input for different time constants.
i) RC>>T ii) RC = T iii) RC<<T
b) To study the response of RC High pass circuit and to determine
percentage tilt for a square input for different time constants.
i) RC>>T ii) RC = T iii) RC<<T.
Components Required :
1. Resistors - 10kΩ, 100 kΩ, 1MΩ
2. Capacitor - 0.01µF
Apparatus Required :
1. Bread Board.
2. CRO
3. Function Generator.
4. Connecting Wires.
THEORY:
LINEAR WAVE SHAPING
The process of where by the form of a non-sinusoidal signal is altered by
transmission through a linear network is called “LINEAR WAVE SHAPING”.
a) RC Low Pass Circuit :
Figure 1: RC Low Pass Circuit.
The circuit passes low frequencies readily but attenuates high frequencies because the
reactance of the capacitor decreases with increasing frequency. At very high frequencies the
capacitor acts as a virtual short circuit and the output falls to zero. This circuit also works as
integrating circuit. A circuit in which the output voltage is proportional to the integral of the
input voltage is known as integrating circuit. The condition for integrating circuit is RC value
must be much greater than the time period of the input wave (RC>>T)
______________________________________________________________________________
V
0
R
C V
i
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Lendi Institute of Engineering and Technology, Vizianagaram 2
Department of Electronics and Communications Engineering
Let V
i
= alternating input voltage.
i = resulting current
Applying Kirchoff’s Voltage Law to RC low pass circuit (fig.1).

+ ·
T
o
i
dt i
C
iR V .
1
Multiplying throughout by C, we get

+ ·
T
o
i
dt i iRC CV .
As RC >> T, the term

T
o
dt i. may be neglected
∴ iRC CV
i
·
Integrating with respect to T on both sides, we get
∫ ∫
·
T T
i
dt i RC dt CV
0 0
. .
∫ ∫
·
T t
i
dt V
RC
dt i
C
0 0
.
1
.
1

·
T
dt i
C
V
0
0
.
1


·
t
i
dt V
RC
V
0
0
.
1
The output voltage is proportional to the integral of the input voltage.
EXPECTED GRAPH:
______________________________________________________________________________
V
i
t
t
t
RC<T
RC>>T
(0.9)V
0
(0.1)V
0
V
0
t
r
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Lendi Institute of Engineering and Technology, Vizianagaram 3
Department of Electronics and Communications Engineering
b) RC High Pass Circuit.
Figure: 2. RC High Pass Circuit.
The higher frequency components in the input signal appears at the output with less
attenuation than the lower frequency components because the reactance of the capacitor
decreases with increase in frequency. This circuit works as a differential circuit. A circuit in
which the output voltage is proportional to the derivative of the input voltage is known as
differential circuit. The condition for differential circuit is RC value must be much smaller then
the time period of the input wave (RC<<T).
Applying Kirchoff’s Voltage Law to RC high pass circuit (fig.2)

+ ·
T
o
i
iR dt i
C
V .
1
.
Divide throughout by R

+ ·
T
o
i
i dt i
RC R
V
.
1
.
As RC << T, the above equation is modified as

·
T
o
i
dt i
RC R
V
.
1
Differentiating above equation with respect to T.
i
RC
V
dt
d
R
i
.
1 1
·
iR V
dt
d
RC
i
·
iR V ·
0
Therefore
i
V
dt
d
RC V ·
0
.
i
V
dt
d
V ∝
0
______________________________________________________________________________
C
R
V
0
V
i
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Lendi Institute of Engineering and Technology, Vizianagaram 4
Department of Electronics and Communications Engineering
EXPECTED GRAPHS:
DESIGN:
1. Choose T = 1msec.
2. Select C = 0.01 µF.
3. For RC = T; select R.
4. For RC >> T; select R.
5. For RC << T; select R.
6. If RC << T, the High pass circuit works as a differentiator.
7. If RC >> T, the Low pass circuit works as an integrator.
PROCEDURE:
1. Connect the circuit as shown in the figure1 &2.
2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a square wave signal of frequency 1KHz at the input. (T = 1 msec.)
4. Observe the output waveform of the circuit for different time constants.
5. Calculate the rise time for low pass filter and tilt for high pass filter and compare
with the theoretical values.
6. For low pass filter select rise time (t
r
) = 2.2 RC (theoretical). The rise time is
defined as the time taken by the output voltage to rise from 0.1 to 0.9 of its final
value.
7. % tilt = ( T/2RC ) × 100 ( theoretical)
% tilt = [ ( V
1
– V
1
′ ) / ( V / 2 ) ] × 100 ( practical)
______________________________________________________________________________
V
i
t
t
t
RC=T
RC<<T
V
1
V
1
′ V
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Lendi Institute of Engineering and Technology, Vizianagaram 5
Department of Electronics and Communications Engineering
RESULT:
1. Rise time for lowpass filter when RC <<T
Theoretical = Practical =
2. % tilt for highpass filter when RC = T.
Theoretical = Practical =
Response of RC Low pass circuit is observed and rise time calculated.
Response of RC High pass circuit is observed and percentage tilt is
calculated.
______________________________________________________________________________
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Lendi Institute of Engineering and Technology, Vizianagaram 6
Department of Electronics and Communications Engineering
Experiment No:2
NON LINEAR WAVE SHAPING - CLIPPERS
AIM : To study the clipping circuits for the following reference voltages and
to verify the responses.
Components Required:
1. Resistors - 1KΩ
2. IN4007 Diode – 2No.
Apparatus Required :
1. Bread board.
2. Function generator
3. CRO
4. Power supply 0-30V
5. Connecting wires.
THEORY:
The non-linear semiconductor diode in combination with resistor can function as clipper
circuit. Energy storage circuit components are not required in the basic process of clipping.
These circuits will select part of an arbitrary waveform which lies above or below some
particular reference voltage level and that selected part of the waveform is used for transmission.
So they are referred as voltage limiters, current limiters, amplitude selectors or slicers.
There are three different types of clipping circuits.
1) Positive Clipping circuit.
2) Negative Clipping.
3) Positive and Negative Clipping ( slicer ).
In positive clipping circuit positive cycle of Sinusoidal signal is clipped and negative
portion of sinusoidal signal is obtained in the output of reference voltage is added, instead of
complete positive cycle that portion of the positive cycle which is above the reference voltage
value is clipped.
In negative clipping circuit instead of positive portion of sinusoidal signal, negative
portion is clipped.
In slicer both positive and negative portions of the sinusoidal signal are clipped.
I. Positive Clipping
Figure:1
______________________________________________________________________________
IN 4007
1 K
V
i
V
0
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Lendi Institute of Engineering and Technology, Vizianagaram 7
Department of Electronics and Communications Engineering
Figure: 2(a). Input waveform Figure: 2(b)Output waveform.
V
i
is a input sinusoidal signal as shown in the figure 2(a) . For positive portion of the
sinusoidal the diode IN4007 gets forward biased. The output voltages in the voltage across the
diode under forward biased which is cut-in-voltage of the diode. Therefore the positive portion
above the cut-in-voltage is clipped or not observed in the output (V
0
) as shown in figure 2(b).
II. Positive Clipping with Positive Reference Voltage
Figure:3.
Figure:4(a). Input waveform Figure:4(b). Output waveform.
The input sinusoidal signal (V
i
) in figure 4(a) can make the diode to conduct when its
instantaneous value is greater than V
R
. Up to that voltage (V
R
) the diode is open circuited and the
output voltage is same as the input voltage. After that voltage (V
R
) the output voltage is V
R
plus
the cut-in-voltage (V
γ
) of the diode as shown in figure 4(b).
______________________________________________________________________________
IN 4007
1 K
V
R
V
i
V
0
V
i
t
V
γ
V
0
t
V
i
t
V
R
+ V
γ
V
0
t
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Lendi Institute of Engineering and Technology, Vizianagaram 8
Department of Electronics and Communications Engineering
III. Positive Clipping with Negative Reference Voltage
Figure: 5.
Figure:6(a). Input waveform Figure:6(b) Output waveform.
In this circuit the diode conducts the output voltage is same as input voltage. The diode
conducts at a voltage less by V
R
from cut-in-voltage called as V
γ
. For voltage less than V
γ
, the
diode is open circuited and output is same as input voltage.
IV Negative Clipping Circuit
Figure:7.
______________________________________________________________________________
V
γ
-V
R
IN 4007
1 K
V
R
V
i
V
0
IN 4007
1 K
V
i
V
0
V
i
t
V
0
t
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Lendi Institute of Engineering and Technology, Vizianagaram 9
Department of Electronics and Communications Engineering
Figure:8 (a). Input waveform Figure:8 (b). Output waveform.
For this portion of the input sinusoidal signal (Vi
)
, the diode gets reverse biased and it is
open. Then the output voltage is same as input voltage. For the negative portion of the signal the
diode gets forward biased and the output voltage is the cut-in-voltage (-V
γ
) of the diode. Then
the input sinusoidal variation is not seen in the output. Therefore the negative portion of the input
sinusoidal signal (Vi
)
is clipped in the output signal ( V
0
).
V. Negative Clipping with Negative Reference Voltage
Figure:9
Figure:10(a). Input waveform. Figure:10(b) Output waveform.
In this circuit, the diode gets forward biased for the input sinusoidal voltage is less than
(–V
R
). For input voltage greater than (–V
R
), the diode is non-conducting and it is open. Then the
output voltage is same as input voltage.
______________________________________________________________________________
IN 4007
1 K
V
R
V
i
V
0
V
i
t
-V
γ
V
0
t
V
i
t
-V
R
-V
γ
V
0
t
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Lendi Institute of Engineering and Technology, Vizianagaram 10
V
i V
0
Department of Electronics and Communications Engineering
VI. Negative Clipping with Positive Reference Voltage
Figure:11.
Figure:12(a) Input waveform Figure:12(b) Output waveform.
For input sinusoidal signal voltage less than V
R
, the diode is shorted and the output
voltage is fixed ar V
R
. For input sinusoidal voltage greater than V
R
the diode is reverse biased and
open circuited. Then the output voltage is same as input voltage.
VII. Slicer
Figure:13.
______________________________________________________________________________
IN 4007
1 K
V
R
IN 4007
1 K
V
R1
IN 4007
V
R2
V
i
t
V
R
-V
γ
V
0
t
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Lendi Institute of Engineering and Technology, Vizianagaram 11
Department of Electronics and Communications Engineering
Figure:14(a). Input waveform Figure14(b). Output waveform.
DESIGN:
1. For positive clipping at ‘V’ volts reference select V
R
= V.
2. For negative clipping at ‘V’ volts reference select V
R
= V.
3. For clipping at two independent levels at V
1
&V
2
reference voltages select
V
R1
= V
1
, V
R2
= V
2
and V
R2
> V
R1
.
PROCEDURE:
1. Connect the circuit as shown in the figure 1.
2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a sine wave signal of frequency 1KHz at the input and observe the output
waveforms of the circuits.
4. Repeat the procedure for figure 3, 5, 7, 9, 11 and 13.
RESULT:
Vγ =
Clipping circuits for different reference voltages are studied.
QUESTIONS:
1. What is a clipper? Describe (i) Positive clipper (ii) Biased clipper (iii) Combination
clipper.
2. Discuss the differences between shunt and series clipper.
______________________________________________________________________________
V
i
t
V
γ
+V
R
V
γ
-V
R
V
0
t
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Lendi Institute of Engineering and Technology, Vizianagaram 12
Department of Electronics and Communications Engineering
Experiment No:3
NON LINEAR WAVE SHAPING – CLAMPERS
AIM : To get positive and negative clamping for sinusoidal and Square wave
inputs.
Components Required:
1. Resistors - 1kΩ
2. IN4007 Diode
3. Capacitor -10µF
Apparatus Required:
1. Bread board
2. Function generator
3. CRO
4. Power supply 0-30V
5. Connecting Wires.
THEORY:
Clamping Circuit
“A clamping circuit is one that takes an input waveform and provides an output that is
a faithful replica of its shape but has one edge tightly clamped to the zero voltage reference
point”.
There are various types of Clamping circuits, which are mentioned below:
1. Positive Clamping Circuit.
2. Negative Clamping Circuit.
3. Positive Clamping with positive reference voltage.
4. Negative Clamping with positive reference voltage.
5. Positive Clamping with negative reference voltage.
6. Negative Clamping with negative reference voltage.
______________________________________________________________________________
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Lendi Institute of Engineering and Technology, Vizianagaram 13
Department of Electronics and Communications Engineering
Negative Clamping Circuit
Figure:1
The input signal is a sinusoidal which begins at t=0. The capacitor C is charged at t = 0.
The waveform across the diode at various instant is studied.
During the first quarter cycle the input signal rises from zero to the maximum value V
m
.
The diode being ideal, no forward voltage may appear across it. During this first quarter cycle
the capacitor voltage V
A
= V
i
. The voltage across C rises sinusoidally, the capacitor is charged
through the series combination of the signal source and the diode. Throughout this first quarter
cycle the output V
0
has remained zero. At the end of this quarter cycle there exists across the
capacitor a voltage V
A
= V
m
.
After the first quarter cycle, the peak has been passed and the input signal begins to fall,
the voltage V
A
across the capacitor is no longer able to follow the input voltage. For in order to
do so, it would be required that the capacitor discharge, and because of the diode, such a
discharge is not possible. The capacitor remains charged to the voltage V
A
= V
m
, and, after the
first quarter cycle the output is V
0
= V
i
– V
m
. During succeeding cycles the positive excursion of
the signal just barely reaches zero. The diode need never again conduct, and the positive
extremity of the signal has been clamped to zero. The average value of the signal is –V
m
.
Positive Clamping Circuit:
Figure:2
It is also called as negative peak clamper, because this circuit clamps at the negative
peaks of a signal.
______________________________________________________________________________
V
i
V
0
V
A
C
D
+ -
+
-
V
i
V
0
V
m
C
D
+ -
+
-
+
-
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Lendi Institute of Engineering and Technology, Vizianagaram 14
m i
V V V + ·
0
Department of Electronics and Communications Engineering
Let the input signal be V
i
= V
m
sinωt. When V
i
goes negative, diode gets forward biased and
conducts. The capacitor charges to voltage V
m
, with polarity as shown. Under steady state
condition, the positive clamping circuit is given as,
) (
0 m i
V V V − − ·
Eq.1
During the negative half cycle of V
i
, the diode conducts and C charges to –V
m
volts, i.e.,
the negative peak value. The capacitor cannot discharge since the diode cannot conduct in the
reverse direction. Thus the capacitor acts as a battery of –V
m
volts and the output voltage is given
by equation.1 above. It is seen for figure 2, that the negative peaks of the input signal are
clamped to zero level. Peak-to-peak amplitude of output voltage 2V
m
, which is the same as that
of the input signal.
Negative Clamping with Positive Reference Voltage
Figure:2
Since V
R
is in series with the output of negative clamping circuit, now the average value of the
output becomes (-V
m
+ V
R
).
Similarly, the average of
i) Negative clamping with negative reference voltage is (-V
m
+ V
R
).
ii) Positive clamping is +V
m
.
iii) Positive clamping with positive reference voltage is V
m
+ V
R
.
iv) Positive clamping with negative reference voltage is V
m
- V
R
.
______________________________________________________________________________
V
i
V
0
C
D
V
R
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Lendi Institute of Engineering and Technology, Vizianagaram 15
Department of Electronics and Communications Engineering
Clamping Circuit Theorem:
It states that for any input waveform the ratio of the areas under the output voltage curve
in forward direction to that in the reverse direction is equal to the ratio (R
f
/ R).
R
R
A
A
f
r
f
· .
Where A
f
= area of the output wave in forward direction.
A
r
= area of the output wave in reverse direction.
Rf and R are forward and reverse resistances of the diode.
I. Negative Clamping
Figure:3
Figure:4 (a).Input waveform Figure:4 (b) Output waveform.
______________________________________________________________________________
IN 4007
1 K
V
i
V
0
10µF
C
D
R
V
i
t
V
m
-V
m
V
0
t
-2V
m
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Lendi Institute of Engineering and Technology, Vizianagaram 16
Department of Electronics and Communications Engineering
II. Negative Clamping with Positive Reference Voltage.
Figure:5
Figure:6 (a).Input waveform Figure:6 (b) Output waveform.
III. Negative Clamping with Negative Reference Voltage.
Figure:7
______________________________________________________________________________
IN 4007
1 K
V
i
V
0
10µF
C
D
R
V
R
t
V
i
V
R
t
V
0
IN 4007
1 K
V
i
V
0
10µF
C
D
R
V
R
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Lendi Institute of Engineering and Technology, Vizianagaram 17
Department of Electronics and Communications Engineering
Figure:8 (a).Input waveform Figure:8 (b) Output waveform.
IV. Positive Clamping.
figure:9
Figure:10 (a).Input waveform Figure:10 (b) Output waveform.
V. Positive Clamping with Negative Reference Voltage.
Figure: 11
______________________________________________________________________________
IN 4007
1 K
V
i
V
0
10µF
C
D
R
IN 4007
1 K
V
i
V
0
10µF
C
D
R
V
R
t
t
V
0
V
i
-V
R
V
0
t
V
i
t
2V
m
V
m
-V
m
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Lendi Institute of Engineering and Technology, Vizianagaram 18
Department of Electronics and Communications Engineering
Figure:12 (a).Input waveform Figure:12 (b) Output waveform.
VI. Positive Clamping with Positive reference Voltage.
Figure: 13
Figure:14 (a).Input waveform Figure:14 (b) Output waveform.
PROCEDURE:
1. Connect the circuit as shown in the figure 3.
2. Connect the function generator at the input terminals and CRO at the output
terminals of the circuit.
3. Apply a sine wave and square wave signal of frequency 1kHz at the input and
observe the output waveforms of the circuits in CRO.
4. Repeat the above procedure for the different circuit diagram as shown inf figure 5, 7,
9, 11 and 13.
IN 4007
1 K
V
i
V
0
10µF
C
D
R
V
R
t
V
i
V
R
t
V
0
t
V
i
t
V
0
-V
R
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Lendi Institute of Engineering and Technology, Vizianagaram 19
Department of Electronics and Communications Engineering
RESULT: The clamping voltages for positive and negative clamping circuits are noted.
QUESTIONS:
1. Explain the operation of a clamping circuit for a square wave input.
2. Differentiate the clippers with clampers.
3. Give the applications of clampers.
______________________________________________________________________________
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Lendi Institute of Engineering and Technology, Vizianagaram 20
Department of Electronics and Communications Engineering
Experiment No:4
STUDY OF LOGIC GATES
AIM : To study the various logic gates by using discrete components.
Component Required :
1. Resistors - 1kΩ -1, 10 kΩ -2
2. IN4007 Diode – 2 no
3. Transistor 2N2369
Apparatus Required:
1. Power supply 0-30V
2. Bread board
3. Connecting wires
THEORY:
TRUTH TABLE
A B Y
0
0 0
0 1 0
1 0 0
1 1 1
AND GATE:
The AND gate as a high output when all the inputs are high the figure 1 shows
one way to build the AND gate by using diodes.
Case 1: When both A and B are low then the diodes are in the saturation region then the supply
from V
CC
will flow to the diodes then the output is low.
Case 2: When A is low and B is high then diode D
1
will be in the saturation region and D
2
will
be in the Cut-off region, then the supply from V
CC
will flow through diode D
1
then the
output will be low.
Case 3: When A is high, B is low the diode D
1
will be in the Cut-off region and diode D
2
will be
in saturation region then the supply from V
CC
will flow through the diode D
2
, therefore
the output will be low.
Case 4: When both the A and B are high then the two diodes will be in Cut-off region therefore
the supply from V
CC
will flow through V
out
then V
out
is high.
______________________________________________________________________________
A
B
Y=A.B
SYMBOL
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Lendi Institute of Engineering and Technology, Vizianagaram 21
Department of Electronics and Communications Engineering
OR GATE:
TRUTH TABLE
A B Y
0
0 0
0 1 1
1 0 1
1 1 1
An OR gate has two or more inputs but only one output signal. It is called OR gate
because the output voltage is high if any or all the inputs are high.
The figure 2 shows one way to build OR gate (two inputs) by using diodes.
Case 1: When A and B are low then the two diodes D
1
and D
2
are in Cut-off region. Then the
V
out
is low.
Case 2: When A is low and B is high then the diode D
1
is in Cut-off region and diode D
2
is in
saturation region, then the V
out
is high.
Case 3: When A is high and B is low then the diode D
2
is in saturation region and diode D
1
is in
Cut-off region, then the V
out
is high.
Case 4: When both A and B are high the diodes D
1
and D
2
are in saturation region then the
output V
out
is high.
NOR GATE:
TRUTH TABLE
Symbol
NOR gate is referred to a NOT OR gate because the output is B A Y + · . Read this as Y
= NOT A OR B or Y = compliment of the A OR B. the circuit is in an OR gate followed by a
NO gate OR inverter. The only to get high output is to have both inputs low.
______________________________________________________________________________
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
B
Y = A + B
SYMBOL
A
B
Y = A + B
B A Y + ·
A
B
B A Y + ·
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Lendi Institute of Engineering and Technology, Vizianagaram 22
A
B
Y = A.B
B A Y . ·
A
B
B A Y . ·
Department of Electronics and Communications Engineering
NAND GATE:
TRUTH TABLE
Symbol
NAND gate is referred to as NOT AND GATE because the output is B A Y . · read this as Y =
NOT A AND B or Y = Compliment of A AND B. By this gate the output is low when all the
inputs are high.
NOT GATE:
TRUTH TABLE
A
Y
0 1
1 0
The Inverter or NOT gate is with only one input and only one output. It is called inverter
because the output is always opposite to the input.
The figure5 shows the one way to build inverter circuit by using transistor (CE mode)
when the Vin is low then the transistor will be in the Cut-off region. Then the supply from VCC
will flow to Vout. Then the Vout is high. When Vin is high then the transistor is in the saturation
region then the supply from VCC will flow through the transistor to the ground, then the Vout is
low.
______________________________________________________________________________
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A
Y=
A
Symbol
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Lendi Institute of Engineering and Technology, Vizianagaram 23
Department of Electronics and Communications Engineering
CIRCUIT DIAGRAM :
Figure 1 Figure 2
Figure 3
Figure 4
______________________________________________________________________________
D
1
IN4007
D
2
IN4007
10K
Y A
B
+5
AND GATE
D
1
IN4007
D
2
IN4007
10K
Y A
B
+5
OR GATE
D
1
IN4007
D
2
IN4007
10K
Y
A
B
+5
NOR GATE
1K
10K
2N2369
D
1
IN4007
D
2
IN4007
10K
Y
A
B
V
CC
+5V
NAND GATE
1K
10K
2N2369
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Lendi Institute of Engineering and Technology, Vizianagaram 24
Department of Electronics and Communications Engineering
Figure 5
PROCEDURE:
1. Connect the circuit as shown in figure 1
2. Verify the truth tables of various gates for different conditions of inputs.
3. Repeat the steps 1&2 for figures 2, 3, 4 & 5.
TRUTH TABLES
AND GATE OR GATE NAND GATE NOR GATE NOT GATE
A B Y A B Y A B Y A B Y A Y
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
Where 5V is represented by logic 1.
RESULT: Different logic gates are studied and their truth tables are
verified .
QUESTIONS:
1. Realize AND, OR, NOT gates using NAND & NOR gates
2. Why NAND & NOR gates are called universal gates.
______________________________________________________________________________
+5
1K
Y
2N2369 A
NOT GATE
10K
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Lendi Institute of Engineering and Technology, Vizianagaram 25
Department of Electronics and Communications Engineering
Ex p e r i m e n t N o : 5
A ST A B L E M U L T I V I B RA T OR
AIM : a) To design and test performance of an Astable Multivibrator to
generate clock pulse for a given frequency.
COMPONENTS REQUIRED:
1. Resistors
2. Capacitors 0.1 µf - 2
3. Transistors 2N2369 – 2
APPARATUS :
1. CRO
2. Power supply 0-30V
3. Bread board
4. Connecting wires
THEORY:
An Astable multivibrator has two quasi-stable states, and it keeps on switching between
these two states, by itself, No external triggering signal is needed. The astable multivibrator
cannot remain indefinitely in any of these two states. The two amplifiers of an astable
multivibrator are regeneratively cross-coupled by capacitor.
Principle:
A collector-coupled astable multivibrator using n-p-n transistor in figure 1. The working
of an astable multivibrator can be studied with respect to the figure1.
Figure:1
Let it be assumed that the multivibrator is already in action and is oscillating i.e.,
switching between the two states. Let it be further assumed that at the instant considered, Q
2
is
ON and Q
1
is OFF.
______________________________________________________________________________
RC
1 RC
2
R
2 R
1
C
2 C
1
2N2369 2N2369
V
CC
12V
Q
1 Q
2
A B
C D
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Lendi Institute of Engineering and Technology, Vizianagaram 26
Department of Electronics and Communications Engineering
i) Since Q
2
is ON, capacitor C
2
charges through resistor R
C1
. The voltage across C
2
is V
CC
.
ii) Capacitor C
1
discharges through resistor R
1
, the voltage across C
1
when it is about to start
discharging is V
CC
.(Capacitor C
1
gets charged to V
CC
when Q
1
is ON).
As capacitor C
1
discharges more and more, the potential of point A becomes more and
more positive (or less and less negative), and eventually V
A
becomes equal to V
γ
, the cut in
voltage of Q
1
. For V
A
> V
γ
, transistor Q
1
starts conducting. When Q
1
is ON Q
2
becomes OFF.
Similar operations repeat when Q
1
becomes ON and Q
2
becomes OFF.
Thus with Q
1
ON and Q
2
OFF, capacitor C
1
charges through resistor R
C2
and capacitor
C
2
discharges through resistor R
2
. As capacitor C
2
discharges more and more , it is seen that the
potential of point B becomes less and less negative (or more and more positive), and eventually
V
B
becomes equal to V
γ
, the cut in voltage of Q
2
. when V
B
> V
γ
, transistor Q
2
starts conducting.
When Q
2
becomes On, Q
1
becomes OFF.
It is thus seen that the circuit keeps on switching continuously between the two quasi-
stable states and once in operation, no external triggering is needed. Square wave voltage are
generated at the collector terminals of Q
1
and Q
2
i.e., at points C and D.
DESIGN:
I
C
max = 5 mA ; V
CC
= 12 V; V
CE (SAT)
= 0.2V
R
C
= (V
CC
- V
CE(SAT)
) / I
C MAX
Let C = 0.1 µf and R= 10KΩ
T = 0.69 (R
1
C
1
+R
2
C
2
) = 0.69(2RC) ( R
1
=R
2
; C
1
=C
2
)
=T
ON
+T
OFF
PROCEDURE:
1. Connect the circuit as shown in figure 1.
2. Observe the waveforms at V
BE1
, V
BE2
, V
CE1
, V
CE2
and find frequency.
3. Vary C from 0.01 to 0.001µF and measure the frequency at each step.
4. Keep the DC- AC control of the Oscilloscope in DC mode.
______________________________________________________________________________
Q
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Lendi Institute of Engineering and Technology, Vizianagaram 27
Department of Electronics and Communications Engineering
EXPECTED WAVEFORMS:
Q1 OFF, Q2 ON Q1 OFF, Q2 ON
Q1 ON, Q2 OFF Q1 ON, Q2 OFF
Figure 2
RESULT:
T
ON
= T
OFF
= T(T
ON
+ T
OFF
) =
Astable multivibrator is designed and its performance is tested.
QUESTIONS:
1. What is a switching circuit?
2. Justify that the Astable Multivibrator is a two stage RC coupled Amplifier using
negative feedback. How does it generate square wave.
3. What is the difference between a switching transistor and an ordinary transistor?
4. What is the effect of slew rate on the working of an Op-amp Multivibrator?
______________________________________________________________________________
VC
1
t
VC
2
t
VB
1
t
VB
2
t
V
CE (SAT)
V
CE (SAT)
V
CC
V
γ
V
γ
V
CC
I.R
C
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Lendi Institute of Engineering and Technology, Vizianagaram 28
Department of Electronics and Communications Engineering
Ex p e r i m e n t N o : 6
M ON OST A B L E M U L T I V I B RA T OR
AIM : a) To design and test performance of a monostable multivibrator to generate clock
pulse for a given frequency. And obtain the waveforms.
Components Required:
1. Resistors
2. Capacitors.
3. Transistors 2N2369 – 2
Apparatus Required:
1. CRO
2. Power supply 0-30V
3. Bread board
4. Connecting wires
CIRCUIT DIAGRAM:
Figure 1
THEORY :
‘A monostable multivibrator has only one stable state, the other state being quasi-
stable. Normally the multivibrator is in the stable state, and when an external triggering pulse is
applied, it switches from the stable to the quasi-stable state. It remains in the quasi-stable state
fro a short duration, but automatically reverts i.e. switches back to its original stable state,
without any triggering pulse’.
______________________________________________________________________________
RC
1 RC
2
R=10K
R
1
C=0.1µF
2N2369 2N2369
V
CC
12V
-V
BB
-1.5V
R
2
Q
1 Q
2
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Lendi Institute of Engineering and Technology, Vizianagaram 29
Department of Electronics and Communications Engineering
Principle of operation
A collector-coupled Monostable multivibrator of the two transistors Q
1
and Q
2
, Q
1
is
normally OFF and Q
2
is Normally ON. Resistor R
1
and R
2
are connected to the normally OFF
transistor, and the capacitor C is connected to the normally ON transistor.
It is seen from the circuit of the monostable multivibrator that, under normal conditions,
the supply voltage V
CC
provides enough base drive to the transistor Q
2
through resistor R, with
the result that Q
2
goes into saturation. With Q
2
ON, Q
1
goes OFF, as already studied in the
context of binary operation.
With Q
2
ON and Q
1
OFF, the capacitor finds a charging path. The voltage across the
capacitor is V
CC
with polarity. It is obvious that in the stable state of the multivibrator, Q
2
is ON
and Q
1
is OFF.
If the negative triggering pulse is applied to the collector of Q
1
, it is transmitted to the
base of Q
2
through the capacitor, and hence makes the base of Q
2
negative. Immediately Q
2
goes
OFF and Q
1
becomes ON. However, this is only a quasi-stable state as is obvious form the
following observation.
With Q
1
ON and Q
2
OFF, the capacitor C finds a discharging path. As the capacitor
discharges, it is seen that the potential at the base of the transistor Q
2
becomes less and less
negative, and after a time, we have V
B
= V
γ
, the cut-in-voltage of Q
2
.
As soon as V
B
crosses the level of V
γ
, Q
2
starts conducting and gets saturated.
When Q
2
becomes ON, Q
1
becomes OFF. Thus the original stable state of the multivibrator is
restored.
[ In quasi-stable state: Q
1
is ON and Q
2
is OFF]
The interval during which the quasi-stable state of the multivibrator persists i.e., Q
2
remains OFF is dependent upon the rate at which the capacitor C discharges. This duration of the
quasi-stable state is termed as delay time or pulse width or gate time. It is denoted as T. The
wave forms of the voltage at base of the transistor Q
2
and C (Collector of Q
1
)
D E S I G N :
V
CE
= 5.56v, V
CC
= 6v, V
CE(sat)
= 0.3v, V
BE(sat)
, = 0.7v, I
C
= 6mA,V
F
= -0.3v
Rc = (V
CC
–V
CE(sat)
)/I
C
.
C
C sat BE
C
CC
CE
R R
R V
R R
R V
V
+
+
+
·
1
) (
1
1
Find the values of R
1
and R
2
PROCEDURE:
1. Connect the circuit as shown in figure.
2. With the help of a triggering circuit and using the condition T (trig) >
T(Quasi) a pulse waveform is generated.
3. The output of the triggering circuit is connected to the base of the off
transistor.
4. The Off transistor goes into ON state.
5. Observe the waveforms at V
BE1
, V
BE2
, V
CE1
, V
CE2
6. Keep the DC- AC control of the Oscilloscope in DC mode.
______________________________________________________________________________
2 1
2 ) (
2 1
1
R R
R V
R R
R V
V
sat CE
BB
F
+
+
+

·
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Lendi Institute of Engineering and Technology, Vizianagaram 30
Department of Electronics and Communications Engineering
EXPECTED WAVEFORMS:
Q2 OFF, Q1 ON Q1 OFF, Q2 ON
Q2 ON, Q1 OFF
Figure 2
RESULT:
T
ON
=
T
OFF
=
Total T (T
ON
+ T
OFF
) =
Monostable multivibrator is designed and studied.
QUESTIONS:
1. Explain the operation of collector coupled Monostable Multivibrator?
2. Derive the expression for the gate width of a transistor Monostable Multivibrator?
3. Give the application of a Monostable Multivibrator.
______________________________________________________________________________
VC
2
t
VB
2
t
VC
1
t
VB
1
t
V
CE (SAT)
V
CE (SAT)
V
CC
V
γ
V
γ
V
CC
I.R
C
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Lendi Institute of Engineering and Technology, Vizianagaram 31
Department of Electronics and Communications Engineering
Experiment No:7
B I ST A B L E M U L T I V I B RA T OR
AIM: To design a fixed bias Bistable Multivibrator and to measure the stable state
voltages before and after triggering.
COMPONENTS REQUIRED:
1. Resistors
2. Capacitors.
3. Transistors 2N2369 – 2
APPARATUS:
1. Bread board
2. Power supply 0-30V
3. CRO
4. Connecting wires
THEORY:
A bistable multivibrator has two stable output states. It can remain indefinitely in any
one of the two stable states, and it can be induced to make an abrupt transition to the other stable
state by means of suitable external excitation. It would remain indefinitely in this stable state,
until it is again induced to switch into the original stable state by external triggering.
Bistable multivibrators are also termed as ‘Binary’s or Flip-flops’. A binary is sometimes
referred to as ‘Eccles-Jordan Circuit’.
Principle of Operation of bistable multivibrator.
Consider the circuit as shown in the figure.1. The transistor Q
1
and Q
2
are n-p-n
transistors. They are coupled to each other as shown in figure 1. It is evident that the output of
each transistor is coupled to the input of the other transistor. Since the transistors are identical,
______________________________________________________________________________
RC
1 RC
2
R
1
Q
2
+V
CC
Q
1
R
2 R
2
R
1
-V
BB
A B
C D
I
1
I
2
Figure 1
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Lendi Institute of Engineering and Technology, Vizianagaram 32
Department of Electronics and Communications Engineering
there quiescent currents would be the same, unless the loop gain is greater than unity. When I
1
increases slightly, the voltage drop across the collector resistance R
C1
increases. Since V
CC
is
fixed, the voltage of point C decreases. This has the effect of decreasing the base current of Q
2
.
This, in turn, decreases the collector current of Q
2
viz. I
2
decreases, the voltage drop I
2
R
C2
decreases. Hence the voltage of point D increases.
Due to increase of V
D
, the base current of Q
1
increases. This increases the collector
current of Q
1
viz I
1
. Thus I
1
further increases. I
1
R
C1
drop further increases, V
C
further decreases,
the base current of Q
2
further decreases, with the result that I
2
further decreases. Thus it can
easily seen that if the collector current I
1
increases even marginally, I
2
would go on progressively
decreasing and as a result, I
1
would progressively increase. Eventually I
2
would become
practically zero, cutting off the transistor Q
2
, at the same time transistor Q
1
would conduct
heavily with the result that it would be driven into saturation. Thus Q
2
becomes OFF and Q
1
becomes ON. It can similarly be shown that if I
2
increases even marginally similar sequence of
operation would result and ultimately Q
2
would be ON and Q
1
OFF. Thus when Q
1
is ON, Q
2
is
OFF and when Q
1
is OFF Q
2
is ON.
CIRCUIT DIAGRAM:
Figure: 2
PROCEDURE:
1. Connect the circuit as shown in figure 2.
2. Observe the waveforms at V
BE1
, V
BE2
, V
CE1
, V
CE2
3. Observe which transistor is in ON state and which transistor is in OFF state.
4. Apply –ve triggering at the base of the ON transistor and observe the voltages V
C1
,
V
C2
, V
B1
, and V
B2.
5. Apply + ve triggering at the base of the OFF transistor and observe the
Voltages V
C1
, V
C2
, V
B1
, V
B2.
______________________________________________________________________________
RC
1
2.2K
RC
2
2.2K
R
1
15K
2N2369
2N2369
V
CC
12V
-V
BB
= -1.5V
R
1
15K
R
2
1
0
0
K

R
2
1
0
0
K

Q
1 Q
2
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Lendi Institute of Engineering and Technology, Vizianagaram 33
Department of Electronics and Communications Engineering
EXPECTED WAVEFORMS:
RESULT:
QUESTIONS:
1. What is Multivibrator? Explain the principle on which it works? Why is it called a
binary?
2. Explain the role of commutating capacitors in a Bistable Multivibrator?
3. Give the Application of a Binary.
______________________________________________________________________________
V
BE1
V
BE2
V
CE1
V
CE2
Stable state Voltages
t
V
o
l
t
a
g
e
V
C1
V
C2
Before Triggering
t
V
o
l
t
a
g
e
V
C1
V
C2
After Triggering
0
0
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Lendi Institute of Engineering and Technology, Vizianagaram 34
Department of Electronics and Communications Engineering
Experiment No: 8
SCH M I T T T RI GGER
AIM: To design and analyze Schmitt trigger and to observe the waveforms.
COMPONENTS REQUIRED:
1. Resistors
2. Transistors 2N2369 – 2
3.
APPARATUS:
1. Bread board
2. Power supply 0-30V
3. Signal generator
4. CRO
5. Connecting Wires.
C I R C U I T D I A G R A M :
Figure:1
______________________________________________________________________________
-
+
R
B
RC
1
R
1
2N2369
RC
2
R
2
R
E
Signal
Generator
V
CC
= 12V
2N2369
Q
1
Q
2
V
0
V
i
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Lendi Institute of Engineering and Technology, Vizianagaram 35
Department of Electronics and Communications Engineering
THEORY:
The most important application of Schmitt Trigger circuit are amplitude comparator and
squaring circuit are amplitude comparator and squaring circuit. The circuit is used to obtain a
square waveform from any arbitrary input waveform. The loop gain is to be less than unity.
If Q
2
is conducting there will be voltage drop across R
Z
which will elevate the emitter of
Q
1
. Consequently if V is small enough in voltage, Q
1
will be cut-off with Q
1
conducting, the
circuit amplifies and since the gain is positive, the output to rise, V
2
continues to fall and Z
2
continues to rise. Therefore a value of V will be reached where Q
2
is turned OFF. At the point the
output no longer responds to the input.
Here the input signal is arbitrary except that it has large enough excursion to carry input
beyond the limits of hysteresis range, V
H
= (V
1
– V
2
).
The output is a square wave whose amplitude is independent of the amplitude of the input
waveform.
D E S I G N :
I
C2
= 5mA
(Rc
2
+ R
E
) = V
CC
/ I
C2
U.T.P = V
E2
= 5V
V
E2
= (R
E
×V
CC
) / (Rc
2
+R
E
)
I
2
= 0.1×I
C2
L.T.P = V
E1
= 3V
R
2
= E
R2i
/ I
2
= V
E1
/ I
2
= L.T.P / I
2
Rc
1
= {(R
E
×V
CC
) / V
E1
} –R
E
I
B2
= I
C2
/ hfe(min)
(V
CC
- V
E2
) / (R
1
+R
L1
))) = (V
E2
/R
2
)+I
B2
R
B
= (h
fe
×R
E
) / 10
Find R
1
, R
2
, R
E
, Rc
1
and Rc
2
from the above equations
PROCEDURE:
1. Connect the circuit as shown in figure 1 with designed values.
2. Apply V
CC
of 12V and an input frequency of 1KHz with an amplitude more than the
designed UTP.
3. Now note down the output wave forms
4. Observe that the output comes to ON state when input exceeds UTP and it comes to OFF
state when input comes below LTP
5. Observe the waveforms at V
C1
, V
C2
, V
B2
and V
E
and plot graphs.
6. Keep the DC- AC control of the Oscilloscope in DC mode.
______________________________________________________________________________
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Lendi Institute of Engineering and Technology, Vizianagaram 36
Department of Electronics and Communications Engineering
MODEL GRAPHS:
RESULT: Schmitt Trigger circuit is designed and studied.
QUESTIONS:
1. Explain how a Schmitt trigger acts as a comparator?
2. Derive its expressions for UTP & LTP.
__________________________________________________________________
VC
2
VC
1
VB
2
Input sin wave
V
MAX
>UTP
UTP
LTP
Schmitt Trigger
output
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Lendi Institute of Engineering and Technology, Vizianagaram 37
-
+
R
a
=1K
R
L
+Va
+V
b
+V
c
V
2
Ia
I
b
Ic
I
F
V
1
I
B2
≅0
I
B1
≅0
R
OM
= (R
a
|| R
b
|| R
c
|| R
F
)
+Vcc
-V
EE
741

,
`

.
|
+ + − ·
c
c
F
b
b
F
a
a
F
V
R
R
V
R
R
V
R
R
V
0
R
b
=1K
Rc=1K
R
f
=1K
3
2 7
4
6
R
1
R
F
V
2
-
+
R
L
R
R
R
+V
a
+V
b
+V
c
V
1
V
cc
V
EE

,
`

.
| + +

,
`

.
|
+ ·
3 1
1
0
c b a F
V V V
R
R
V
741
Department of Electronics and Communications Engineering
Experiment No:9
ADDER, SUBTRACTOR & COMPARATOR
AIM: To verify the operation of the Adder, Subtractor and comparator using 741 op amp.
APPARATUS:
1. Operational Amplifier µA 741 IC –1No.
2. Resistors 1KΩ - 5, 220Ω
3. Power supply( 0-30V)
4. Multi meter
5. Bread board
6. CRO (20MHz/30MHz)
CIRCUIT DIAGRAM:
1. ADDER:
Fig 1a) Inverting Configuration
Fig 1b)Non Inverting Configuration
______________________________________________________________________________
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Lendi Institute of Engineering and Technology, Vizianagaram 38
Department of Electronics and Communications Engineering
2. SUBTRACTOR:
Fig 2: Subtractor
3.BASIC COMPARATOR:
Fig.3(a) Inverting comparator
MODEL GRAPH:
Fig.3(b) if V
ref
is positive Fig.3(c) if V
ref
is negative
______________________________________________________________________________
+Vc
-
+
-V
EE
R
R
R
R
R
L
+V
+V
b
V
0
= V
b
-
74
+
-
+15V
-15V
LM74
1
2
3
7
4
6
R
L
10KΩ
R1KΩ
R1KΩ
V
REF V
IN
t
V
in
V
p
- V
p
- V
ref
0V
0V
t
+V
SAT
-V
SAT
Vin >VREF Vin >VREF
Vin <VREF
V
0
V
in
V
p
- V
p
0V
-V
REF
0V
t
t
+V
SAT
-V
SAT
Vin <VREF
Vin <VREF
Vin >VREF
V
0
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Lendi Institute of Engineering and Technology, Vizianagaram 39
Department of Electronics and Communications Engineering
THEORY:
1.Summing amplifiers
(A)Inverting configuration
Fig(1a) shows the inverting configuration with three inputs V
a
, V
b
, and V
c
.Using input
resistors R
a
, R
b
, and R
c
. The circuit can be used as either a summing amplifier, scaling amplifier,
or averaging amplifier. The circuit’s function can be verified by examining the expression for the
output voltage Vo, which is obtained from Kirchhoff’s current equation written at node V2.
Referring to fig(1), Ia + Ib + Ic = I
B
+ I
F
Since R
i
and A of the op-amp are ideally infinity, I
B
= 0A and V1 = V2≅ 0V.
Therefore,
F
o
c
c
b
b
a
a
R
V
R
V
R
V
R
V
− · + +

,
`

.
|
+ + − ·
c
F
b
b
F
a
a
F
o
R
R
V
R
R
V
R
R
V ---- 1
Summing amplifier:
If in the circuit of Fig(1a), R
a
= R
b
= R
c =
R, for example, then equation (1) can be rewritten as
| )
c b a
F
o
V V V
R
R
V + + − ·
This means that the output voltage is equal to the negative sum of all the inputs times the gain
of the circuit R
F
/R: Hence the circuit is called a summing amplifier.
(B)Non inverting Configuration:
If input voltages sources and resistors are connected to the non inverting terminal as
shown in fig (1b), the circuit can be used either as a summing or averaging amplifier through
selection of appropriate values of resistors, that is, R1 and R
F
.
Using the superposition theorem, the voltage V1 at the non inverting terminal is
c b a
V
R
R
R
V
R
R
R
V
R
R
R
V
2
2
2
2
2
2
1
+
+
+
+
+
·
3 3 3 3
1
c b a c b a
V V V V V V
V
+ +
· + + · ---- 2
Hence the output voltage is Vo =
1
1
1 V
R
R
F

,
`

.
|
+
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=
3
1
1
Vc V V
R
R
b a F
+ +

,
`

.
|
+
Summing amplifier:
A close examination of equation (2) revels that if the gain (1+R
F
/R
1
) is equal to the
number of inputs, the output voltage becomes equal to the sum of all input voltages. That is, if
(1+R
F
/R
1
) = 3. (From equation (1)),
V
o
= V
a
+ V
b
+V
c
Hence the circuit is called a non inverting summing amplifier.
2. Subtractor:
A basic differential amplifier can be used as a subtractor as shown in figure 2. In this
figure, input signals can be scaled to the desired values by selecting appropriate values for the
external resistors; when this is done, the circuit is referred to as scaling amplifier. However, in
figure 3 all external resistors are equal in value, so the gain of the amplifier is equal to 1. From
the figure, the output voltage of the differential amplifier with a gain of 1 is
| )
R
V V R
V
b a

− ·
0
That is,
a b
V V V − ·
0
Thus the output voltage V
0
is equal to the voltage applied to the non inverting terminal (V
b
)
minus the voltage applied to the inverting terminal(V
a
);hence the circuit is called a subtractor.
3.Basic comparator:
Figure (3) shows an op-amp used as a comparator. A fixed reference voltage V
ref
of 1V is applied to the (-) input, and the other time-varying signal voltage V
in
is applied to the (+)
input. Because of this arrangement, the circuit is called the noninverting comparator.
When V
in
is less than V
ref
, the output voltage V
0
is at –V
sat
(≅-V
EE
) because the voltage at
the (-) input is higher than that at the (+) input. On the other hand, when V
in
is greater than V
ref
,
the (+) input becomes positive with respect to the (-) input, and V
0
goes to +V
sat
(≅+Vcc). Thus
V
0
changes from one saturation level to another whenever V
in
≅ V
ref
, as shown in figure 3(b).
In short, the comparator is a type of analog-to-digital converter. At any given time the V
0
waveform shows whether V
in
is greater or less than V
ref
. The comparator is sometimes also
called a voltage-level detector because, for a desired value of V
ref
, the voltage level of the input
V
in
can be detected .
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The resistance R in series with V
in
is used to limit the current through D
1
and D
2
.
To reduce offset problems, a resistance R
OM
≅R is connected between (-) input and V
ref
.
If the reference voltage V
ref
is negative with respect to ground, with sinusoidal signal
applied to the (+) input, the output waveforms will be as shown in Figure3(c).
When V
in
>V
ref
, V
0
is at +Vsat; on the other hand, when V
in
<V
ref
, V
0
is at –V
sat.
Obviously, the amplitude of V
in
must be large enough to pass through V
ref
if the switching action
is to take place.
Figure (3) shows an inverting comparator in which the reference voltage V
ref
is applied to
the (+) input and Vin is applied to the (-) input. In this circuit, V
ref
is obtained by using a 10KΩ
potentiometer that forms a voltage divider with the dc supply voltage +Vcc and –V
EE
and the
wiper connected to the (+) input.
As the wiper is moved toward –V
EE,
V
ref
becomes more negative, while if it is moved
towards +Vcc, V
ref
becomes more positive. Thus a V
ref
of a desired amplitude and polarity can be
obtained by simply adjusting the 10KΩ potentiometer. With the sinusoidal input waveform, the
output V
0
has the waveform shown in Figure 3(a) or 3(b), depending on whether V
ref
is negative,
respectively.
PROCEDURE:
Part 1: ADDER:
1. Connect the circuit as shown in figure(1).
2. Apply different DC input voltages at V
a
, V
b
, and V
c
and
measure the output voltage V
o
using a multi meter
It should be V
o
= V
a
+ V
b
+ V
c
Part 2: SUBTRACTOR:
1. Connect the circuit as shown in figure(2).
2. Apply different DC input voltages at V
a
, andV
b
and
measure the output voltage V
o
using a multi meter .
It should be V
o
= V
b
– V
a
.
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Part 3: COMPARATOR:
1. Connect the circuit as shown in figure(3a).
2. Apply a reference voltage of (say 1V), to inverting terminal of op-amp.
3. Apply a sinusoidal wave with a peak voltage more than V
ref
to OP-AMPs
Non-inverting terminal.
4. Observe the output at pin number 6, which will be a square wave with peak to peak
voltage of (V
sat
to –V
sat
).
5. Observe that when V
ref
is less than V
in
, then the output goes to +V
sat
,
when V
ref
is greater than Vin then output goes to –V
sat
.
6. Now set another reference voltage and repeat the steps 4 and 5.
7. Draw the observed waveforms on graph sheet and obtain the practical reference voltage.
Result:
Hence the operation of Adder, Subtractor, and comparator (using 741 op amp) is verified.
Conclusions:
It is observed that the out put Values are very much nearer to the given inputs. So we can
conclude that Adder, Subtractor, and comparator are functioning properly.
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Experiment No:10
I NT EGRA T OR A N D D I FFEREN T I A T OR U SI N G 7 4 1 OP- A M P
A I M : To observe the output of an active integrator and differentiator using 741op-amp for a
given input signal and to plot their frequency response by varying the input signal
frequency from 100Hz to 10(or 20) KHz.
[Note: Here the input signal is a Square wave or a Sine wave with a
specific Amplitude(1V
P-P
) and a particular frequency(Say 1KHz)]
APPARATUS:
1. Operational Amplifier µA 741 IC –2No.
2. Resistors 1KΩ - 5, 220Ω
3. Power supply( 0-30V)
4. Multi meter
5. Bread board
6. CRO (20MHz/30MHz)
7. Capacitors
CIRCUIT DIAGRAM:
Fig 1: Integrator
v
2
i
1
I
B
i
F
1V
0V 0.5 1 1.5
-1V
v
1
0V
-0.5V
______________________________________________________________________________
V
o
Vi
t(msec)
t(msec)
-
+
+
+
LM
741
Signal
Generator
CRO
+15V
-15V
Rom=R1
2
3
6
R1
Rf
Cf
RL
7
4
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Fig 2: Differentiator
v
2
i
c
i
F 1V
i
B2
0V
-1V
v
1
2V
0V
i
B1 CRO
2V
Fig 3: OP AMP
PIN DIAGRAM:
OFFSET NULL 1 8 NC
INV i/p 2 7 V
+
NON INV i/p 3 6 o/p
V
-
4 5 OFFSET NULL
Fig 4 Frequency Response:
-
+
+
LM
741
Signal
Generator
+15V
-15V
Rom=R1
2
3
6
R1
RF
CF
RL
DIFFERENTIATOR
7
4
(4a) Integrator frequency response
Voltage gain in dB
dB
R
R
F
1
A
F
f
a f
b
0
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Gain dB
0
f
f
a
f
b
4b) Differentiator frequency response
THEORY:
A)INTEGRATOR:
A circuit in which “the output voltage waveform is the integral of the input voltage
waveform” is the integrator or the integration amplifier.
Such a circuit is obtained by using a basic inverting amplifier configuration, if the feed
back resistor R
F
is replaced by a capacitor C
F
.
Analysis of Integrator Circuit:
The expression for the output voltage v
0
can be obtained by writing Kirchhoff’s current
equation at node v
2
:
i
1
= I
B
+ i
F
Since I
B
is negligibly small,
i
1
≅ i
F
Recall that the relationship between current through and voltage across the capacitor is
i
C
= C
dt
dv
c
Therefore, | )
0 1
1
2 1
v v
dt
d
C
R
v v
F

,
`

.
|
·

However, v
1
= v
2
≅ 0 because A is very large. Therefore,
| )
0
1
v
dt
d
C
R
v
F
in
− ·
The output voltage can be obtained by integrating both sides with respect to time:
| )dt v
dt
d
C dt
R
v
t t
F
in
0
0 0 1
− ·
∫ ∫
= C
F
(-v
0
) +
0
0
· t
v
Therefore, v
0
=

+
t
in
F
C dt v
C R
0 1
1
------- 1
Where C is integration constant and is proportional to the value of the output voltage v
0
at time
t=0 seconds.
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Equation 1 indicates that the output voltage is directly proportional to the negative integral of the
input voltage and inversely proportional to the time constant R
1
C
F
.
If the input to the integrator is a sine wave, the output will be a cosine wave, or if the
input is a square wave, the output will be a triangular wave.
In the circuit shown in figure the stability and the low frequency roll-off problems can be
corrected by the addition of a resistor R
2
(R
F
). The term stability refers to a constant gain as
frequency of an input signal is varied over a certain range. Low frequency roll-off refers to the
rate of decrease in gain at lower frequencies. The input signal will be integrated properly if the
time period T of the signal is larger than or equal to R
F
C
F
.
• The frequency at which gain is 0 dB is given by f
b
=
f
C R
1
2
1
π
• The gain limiting frequency is given by f
a
=
f f
C R π 2
1
• The Values of f
a
and in turn R
1
C
f
and R
f
C
f
Values should be selected such that f
a
<f
b
.
• Ex: If f
a
=0.1f
b
, then R
f
=10R
1
.
• The input signal will be integrated properly, if the Time period of the signal T R
f
C
f
.
Applications:
The integrator is most commonly used in analog computers and analog to digital
converters and signal wave shaping circuits.
B)DIFFERENTIATOR:
The circuit shown in figure performs the mathematical operation of differentiation that is
the output waveform is the derivative of the input waveforms.
The differentiator may be constructed from a basic inverting amplifier if an input resistor
R
1
is replaced by a capacitor C
1
.
Analysis of Differentiator Circuit:
The expression for the output voltage v
0
can be obtained by writing Kirchhoff’s current
equation at node v
2
as follows:
i
C
= I
B
+ i
F
Since I
B
≅ 0,
i
C
= i
F
| )
F
in
R
v v
v v
dt
d
C
0 2
2 1

· −
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But v
1
= v
2
≅ 0V, because A is very large. Therefore,
F
in
R
v
dt
dv
C
0
1
− · Or
dt
dv
C R v
in
F 1 0
− ·
Thus the output v
0
is equal to R
F
C
1
times the negative instantaneous rate of change of the input
voltage v
in
with time.
Since the differentiator performs the reverse of the integrators function, a cosine wave input will
produce a sine wave output, or triangular wave input will produce a Square wave output.
The stability and the high frequency noise problems can be corrected by the addition of two
components R
1
and C
F
.
• The frequency at which gain is 0 dB is given by f
a
=
1
2
1
C R
f
π
• The gain limiting frequency is given by f
b
=
1 1
2
1
C R π
where R
1
C
1
=R
f
C
f
• The input signal will be differentiated properly, if the Time period of the signal
T R
f
C
1
.
• From the frequency f to f
b
,the gain increases at 20dB/decade.However,after f
b
the gain
decreases at 20 dB/decade.
Applications:
The differentiator is most commonly used in wave shaping circuits to detect high
frequency components in an input signal and also as a rate-of-change detector in FM modulator.
DESIGN :
Part 1:Design of Integrator
Design an Integrator to Integrate an input signal, that varies in
frequency from 1KHz to 10KHz.
[Note:Select T R
f
C
f
, where R
f
C
f
=
a
f π 2
1
(T= input signal time period)]
1. Select f
a
= 1 KHz. Assume a value of C
f
< 1 µf. (Let C
f
= 0.1 µf)
( f
a
is the gain limiting frequency)
2.Calculate the value of R
f
using the formula R
f
=
f a
C f π 2
1
3. let f
b
=10f
a
( f
b
is the frequency at which gain is 0 dB)
4.Calculate R
1
using the formula R
1
=
f b
C f π 2
1
.
6.Choose R
om
= R
1
.
6. Take load resistor R
L
= 10KΩ
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Part 2: Design of Differentiator
Design a Differentiator to Differentiate an input signal, that varies in
frequency from 1KHz to 20KHz.
1. Select f
a
= 1 KHz. Assume a value of C
1
< 1 µf. (Let C
1
= 0.1 µf)
( f
a
is the frequency at which gain is 0 dB)
2.Calculate the value of R
f
using the formula R
f
=
1
2
1
C f
a
π
(Result: R
f
=1.59K)
3. let f
b
= 20f
a
, f
b
is the gain limiting frequency
Calculate R
1
using the formula R
1
=
1
2
1
C f
b
π
.
(Result: R
1
=79.5)
4. From R
1
C
1
= R
f
C
f
calculate C
f
(Result: C
1
=0.005µf)
5.Choose R
om
= R
f
.
6. Take load resistor R
L
= 10KΩ
PROCEDURE:
Part 1
1. By using the component values as per the above specified design,Connect the circuit
as shown in the figure.
2. Apply the 1V
P-P
, 1KHz Sinewave or Squarewave as input
3. Observe the output on CRO.
4. Draw the input and output Signals on the Graph paper.
Part 2
5. Vary the input signal (Preferably Sine wave) frequency from 100 Hz to10(or 20)KHz
and notedown the amplitude of the output signal (V
0
).
6. Claculate Gain
i
o
V
V
at each value of the input signal frequency.
Also Calculate dB Value of Gain 20log
i
o
V
V
.
7. Plot the graph between frequency (on X-Axis) and
dB Value of Gain 20log
i
o
V
V
(on Y-Axis)
8. Identify the Practical Values of f
a
and f
b
from the Graphs.
(Note: The Practical Values of f
a
and f
b
observed from the Graphs must equal to the
Theoritical values)
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Re su l t : Hence the output of an active integrator and differentiator using op-amp 741 for a given
input signal is observed and plotted their frequency response by varying the input signal
frequency from 100Hz to 10(or 20) KHz.
Conclusions: The Practical Values of f
a
and f
b
observed from the Graphs are equal to the
Theoritical values. From this we can conclude that the Integrator and
Differentiator using 741 OP-AMP are satisfying their function properly.
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Frequency
0.707A
F
Experiment No.11
ACTIVE FILTER APPLICATIONS – LPF, HPF (FIRST ORDER)
AIM: To Plot the frequency response of first order low pass and high pass filters using
741 OP-AMP and to find Higher and Lower Cut-off frequencies.
APPARATUS:
1. Signal generator(0-1MHz)
2. Oscilloscope(20/30MHz)
3. Bread board
4. Power supply(0-30V)
5. Resistors 15KΩ (1 No.), 10KΩ(3 No.s)
6. Capacitors 0.01µF -1No.
7. Op-amp 741 IC – 1No.
CIRCUIT DIAGRAM:
1. Low Pass Filter
(a)
Department of Electronics and Communications Engineering
V
0
-
+
R
1
R
F
+Vcc
-V
EE
R
L
R
Vin
C
741
+15
-15v
10KΩ
10KΩ
10KΩ
V
2
20K pot at
15.9KΩ 0.01µF
+
Voltage gain
Passband Stopband
-20dB/decade
A
F
f
H
(b)
Fig.1 First-order low-pass Butterworth filters. (a) Circuit. (b) Frequency
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2. High Pass Filter
THEORY:
FILTER ANALYSIS:
1.LPF:
Figure1 shows a first-order low-pass Butterworth filter that uses an RC network for filtering.
Note that the op-amp is used in the non inverting configuration;
Hence it does not load down the RC network. Resistors R
1
and R
F
determine the gain of the
filter.
According to the voltage-divider rule, the voltage at the non inverting terminal
(across capacitor C) is
in
v
jXc R
jXc
v


·
1
Equation (1)
Where
j=√(-1) and -jX
c
=
fC j π 2
1
Simplifying Equation (1), we get
fRC j
v
v
in
π 2 1
1
+
·
And the output voltage
Department of Electronics and Communications Engineering
Vin
Fig.2 First-order high-pass Butterworth filters. (a) Circuit. (b) Frequency
response
-
1
R
1
R
F
+Vcc
-V
EE
R
L
R
C
741
+15
-15v
10KΩ
10KΩ
10KΩ
V
2
20K pot at
15.9KΩ
0.01µF
V
0
Voltage gain
Frequency
A
F
0.707A
F
stopband
dd
Pass band
-20dB/decade
f
L
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1
1
0
) 1 ( v
R
R
v
F
+ ·
That is,
fRC j
v
R
R
v
in F
π 2 1
) 1 (
1
0
+
+ ·
) / ( 1
0
H
F
in
f f j
A
v
v
+
· - Equation (2)
Where
in
v
v
0
= gain of the filter as a function of frequency
) 1 (
1
R
R
A
F
F
+ · = pass band gain of the filter
f = frequency of the input signal
RC
f
H
π 2
1
· = high cutoff frequency of the filter
The gain magnitude and phase angle equations of the low-pass filter can be obtained by
converting Equation-(2) into its equivalent polar form, as follows:
| )
2
) / ( 1
0
H
F
f f
A
Vin
V
+ √
· - Equation-(3)
Φ = -tan
-1

,
`

.
|
H
f
f
Where Φ is the phase angle in degrees.
The operation of the low-pass filter can be verified from the gain magnitude equation (3):
1. At very low frequencies, that is, f<f
H,
Vin
V0
≅ A
F
2. At f=f
H
Vin
V0
=
F
F
A
A
707 . 0
2
·

3. At f>f
H
,
Vin
V0
< A
F
Thus the low-pass filter has a constant gain A
F
from 0 Hz to the high cutoff frequency f
H
.
At f
H
the gain is 0.707 A
F,
and after f
H
it decreases at a constant rate with an increase in
frequency see Fig1b. That is, when the frequency is increased to tenfold (one decade), the
voltage gain is divided by 10.
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In other words, the gain decreases 20db (=20 log 10) each time the frequency is increased by 10.
Hence the rate at which the gain rolls off after f
H
is 20 db/decode or 6 db/octave, where octave
signifies a twofold increase in frequency.
The frequency f= f
H
is called the higher cutoff frequency because the gain of the filter at this
frequency is down by 3 db (=20 log 0.707) from 0 Hz. Other equivalent terms for cutoff
frequency are -3db frequency, break frequency, or corner frequency.
HPF:
High-pass filters are often formed simply by interchanging frequency-determining
resistors and capacitors in low-pass filters. That is, a first-order high-pass filter is formed from a
first-order low-pass type by interchanging components R and C. Similarly, a second-order high-
pass filter is obtained from a second-order low-pass filter if R and C are interchanged, and so on.
Figure2 shows a first-order high-pass Butterworth filter with a low cutoff frequency of f
L
. This is
the frequency at which the magnitude of the gain is 0.707 times its pass band value. Obviously,
all frequencies higher than f
L
are pass band frequencies, with the highest frequency determined
by the closed-loop bandwidth of the op-amp.
Note that the high-pass filter of figure2(a) and the low-pass filter of figure(1a) are the
same circuits, except that the frequency-determining components (R and C) are interchanged.
For the first-order high-pass filter of Figure, the output voltage is
in
F
V
fRC j
fRC j
R
R
V
π
π
2 1
2
) 1 (
1
0
+
+ ·
or
| )
| )
]
]
]
]

+
·
L
L
F
f f j
f f j
A
Vin
V
/ 1
/
0
Where ) 1 (
1
R
R
A
F
F
+ · = pass band gain of the filter
f= frequency of the input signal (Hz)
f
L
=
RC π 2
1
= low cutoff frequency (Hz)
Hence the magnitude of the voltage gain is
| )
| ) | )
2
0
/ 1
/
L
L F
f f
f f A
Vin
V
+ √
·
_____________________________________________________________________________
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Since high-pass filters are formed from low-pass filters simply by interchanging R’s and C’s, the
design procedure of the low-pass filter is also applicable to the high-pass filters
FILTER DESIGN:
A)LPF Design:
Design a LPF having Cutoff frequency of 1KHz with a Passband gain of 2.
A low-pass filter can be designed by implementing the following steps:
1. Choose a value of high cutoff frequency f
H
(let us take 1KHz)
2. Select a value of C less than or equal to 1µf. ( let us take C=0.01µf .)
3. Calculate the value of R using the formula
C f
R
H
π 2
1
· (It will become 15.9 K)
4. Finally, select values of R
1
and R
F
dependent on the desired pass band gain A
F
using
) 1 (
1
R
R
A
F
F
+ · [Since A
F
=2,then R
1
= R
F
. Let R
1
= R
F
=10K]
5.Let R
L
=10K.
A)HPF Design:
Design a HPF having Cutoff frequency of 1KHz with a Passband gain of 2.
A High-pass filter can be designed by implementing the following steps:
1. Choose a value of low cutoff frequency f
L
(let us take 1KHz)
2. Select a value of C less than or equal to 1µf. ( let us take C=0.01µf .)
3. Calculate the value of R using the formula
C f
R
L
π 2
1
· (It will become 15.9 K)
4. Finally, select values of R
1
and R
F
dependent on the desired pass band gain A
F
using
) 1 (
1
R
R
A
F
F
+ · [Since A
F
=2,then R
1
= R
F
. Let R
1
= R
F
=10K]
5.Let R
L
=10K.
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Note:
It is better to take a Capacitor of a standard(fixed)value,not a Variable Capacitor.
If we take Variable Capacitor Value, some times, the Filter may give bad Response(output).
So in the above Design Procedure,we have Chosen a fixed value for the Capacitor,
not a Variable Capacitor,and then Calculated the value of Resistor for a desired frequency.
PROCEDURE:
LOW PASS FILTER& HIGH PASS FILTER FREQUENCY RESPONSE
1.Connect the circuit as shown in figure
2.Take a signal generator and observe its output (sinusoidal signal) on CRO.
Adjust the Amplitude of the sinusoidal signal(V
i
) as 1V
p-p
.Keep its frequency as 100Hz.
2.Connect the signal generator to the input of the LPF.
Using CRO observe the input and output waveforms simultaneously.
3 Vary the frequency of input signal from 100Hz to 100KHz
4. Measure the output voltage Amplitude(V
o
) for every input frequency using oscilloscope.
5.Claculatethe Gain of the Filter
i
o
V
V
. Also Calculate its dB Value.
5. Draw the graph between frequency (Hz) on X-Axis and the Gain on Y –axis
on semi -log sheet.
6.Calculate the cut off frequency from the graph.This is the Practical value of Cut off frequency.
[from the graph find the value of Cut off frequency,at which the Gain is
0.707 times that of Pass band gain(A
F
)].
7.Compare the Practical values with Theoritical values.
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OBSERVATIONS:
Input Signal Amplitude(V
in
) = 1V
p-p
Frequency
(Hz)
Output
voltage(V
o
)
Gain = V
o
/V
in
Gain(in dB) =
20log (V
o
/V
in
)
100Hz
200Hz
400Hz
600Hz
800Hz
900Hz
950Hz
980Hz
1KHz
1.1KHz
1.2KHz
1.4KHz
2KHz
.
.
.
.
100KHz
Result:
Hence the frequency response of first order low pass and high pass filters using
741 OP-AMP were plotted,and Claculated the Higher and Lower Cut-off frequencies,
From Graphs.
Conclusions:
The Practical values are same as the theoritical values in both the cases(ie.,LPF&HPF)
In the First case,for the frequencies below 1KHz the Filter’s Gain is Constant and after 1KHz
there is a decrease in the Gain. So it is Called as LowPass Filter.
In the Second case,for the frequencies above 1KHz the Filter’s Gain is Constant and below
1KHz there is a decrease in the Gain. So it is Called as High Pass Filter.
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Experiment-12
FUNCTION GENERATOR USING 741 OP-AMP
AIM: To generate triangular waveform using 741 Op-Amp function generator.
APPARATUS: Op-amp 741-2No,
Capacitor – 0.1µf – 1No,
Zener diode – 5Z1 – 2No,
Resistors –10K-2, 150K-1, 15K-1, 1M-1, 8.2KΩ-1
CIRCUIT DIAGRAM:
OUTPUT WAVEFORMS
Department of Electronics and Communications Engineering
3
7
2
6
741
741
+15V
-15V
+15V
-15V
4
6
7
2
7
3
R1=10K
C= 0.05µF
Ri= 14K
R2=28K
V
A
V
B
4
t(ms)
+Vsat
15
V
UT 5
0
-5
- 10
- 15
-Vsat
V
LT
1 2 3
V
B
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Pin out diagram of LM 741 IC
OFFSET NULL 1 8 NC
INV I/P 2 7 V
+
NON INV I/P 3 6 O/P
V
-
4 5 OFFSET NULL
THEORY:
A basic bipolar triangle wave generator circuit is presented in fig 1 . The triangle wave
V
A
, is available at the output of the 741 integrator circuit . The square wave signal V
B
, is
available at the output of the 741 comparator . Assume that V
B
is high at +Vsat. This forces a
constant current (Vsat/R
i
) through C (left to right) to drive V
A
negative from V
UT
to V
LT
. When
V
A
reaches V
LT
, Pin 3 of the comparator goes negative and V
B
snaps to –Vsat. And t =1msec.
When V
B
is at -V
sat
, it forces a constant current( right to left) through C to drive V
A
positive from V
LT
toward V
UT
( the time interval 1 to 2 msec) . When V
A
reaches V
UT
at t=
2msec , pin 3 of the comparator goes positive and V
B
snaps to +Vsat. This initiates the next cycle
of oscillation .
Frequency of Operation
The peak values of the triangular wave are established by the ratio of resistor R
2
to R and
the saturation voltages .
They are given by
2
1
R
R V
V
sat
UT

·
2
1
R
R V
V
sat
LT
·
If the saturation voltages are reasonable equal , the frequency of oscillation (f) is given by
C R R
R
f
i 1
2
4
·
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PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Observe the output waveforms on CRO and note down necessary readings and
waveforms.
3. Calculate the time period and amplitude of the waveform theoretically.
4. Compare the theoretical values with the experimental results.
RESULT:
Hence triangular waveform is generated using 741 Op-Amp function generator .
CONCLUSIONS:
It can be concluded that the 741 integrator has produced a triangle wave (V
A
) and the 741
comparator has produced a square wave( V
B
)with amplitude levels –Vsat to +Vsat.The output
of the 741 comparator was given to the integrators input . That means integration of square wave
gives the triangle wave.
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Experiment No:13
MONOSTABLE MULTIVIBRATOR USING 555 IC
AIM: To observe the output waveform of Monostable multivibrator using 555 IC.
APPARATUS:
Bread Board
CRO(20/30MHz)
Connecting wires
COMPONENTS:
555 IC, Resistors and Capacitors as per the Design
CIRCUIT DIAGRAM:
MONOSTABLE MULTIVIBRATOR
Pin diagram
GND 1 8 V
CC
Trigger 2 7 Discharge
Output 3 6 Threshold
Reset 4 5 Control Voltage
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L
M

5
5
5
7
6
4
1
555
3
2
7
6
4
1
5
LM 555
0.01µf
R
C
8
CRO
V
CC
=5V
Trigger i/p
V
i
V
o
T
ON
time
time
(1.1 RC)
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THEORY:
THE 555 AS AN MONOSTABLE MULTIVIBRATOR:
A Monostable multivibrator is also called as a one-shot multivibrator is a pulse-
generating circuit in which the duration of the pulse is determined by the RC network connected
externally to the 555 timer. In a stable state the output of the circuit is zero or at logic-low level.
When an external trigger pulse is applied, the output is forced to go high (≅Vcc). The
time the output remains high is determined by the external RC network connected to the timer.
At the end of the timing interval, the output automatically reverts back to its logic low stable
state. The output stays low until the trigger pulse is again applied. Then the cycle repeats. The
monostable multivibrator has only the stable state.
The applications for the monostable multi vibrator are frequency divider and pulse
stretcher
DESIGN:
Dersign a MMV using 555IC to produce an Output Pulse width of 10msec.
1.Let R=10K
2.Claculate the value of C using the formula
R
T
C
p
1 . 1
·
PROCEDURE:
1.Connect the circuit as shown in the figure, by using the component as per design.
2. Apply the Trigger pulse at Pin no 2. Observe the output waveform at pin no 3.
3.Calculate the time during which the output remains high(t
p
or t
on
or T
p
)
4.Compare it with the theoritical value.
RESULT:
The output of Monostable multivibrator using 555IC is observed. It is also observed that
practical value of the time during which the output remains high is same as theoritical value.
CONCLUSIONS:
It can be concluded that,if the MMV is once triggered,its output will remain in the high state
until the set time elapses.The output will not change its state even if an input trigger is applied
again during this time interval T
p
.
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Experiment:14
ASTABLE MULTIVIBRATOR USING 555 IC
AIM: To observe the output waveform of Astable multivibrator using 555 IC.
APPARATUS:
Bread Board
CRO(20/30MHz)
Connecting wires
COMPONENTS:
555 IC, Resistors and Capacitors as per the Design
CIRCUIT DIAGRAM:
A ST A B L E M U L T I V I B RA T OR
3
R
B
3
Pin diagram
GND 1 8 V
CC
Trigger 2 7 Discharge
Output 3 6 Threshold
Reset 4 5 Control Voltage
Department of Electronics and Communications Engineering
L
M

5
5
5
0.69(R
A
+R
B
)C
0.69R
B
C
T
C
T
D
5
7
6
8
2
1
5
555
R
A
R
B
0.01µf
CRO
V
CC
=5V
4
C
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THEORY:
An Astable multivibrator, often called as free-running multivibrator, is a rectangular-wave-
generating circuit. This circuit does not require an external trigger to change the stable of the
output, hence the name free-running. However the time during which the output is either high or
low is determined by two resistors and a capacitor. Which are externally connected to the 555
timer.
The applications for astable multivibrator are (1) Square-wave oscillator (2) Free-running ramp
generator.
DESIGN:
Design an Astable Multivibrator using 555IC to produce an output pulse with a
positive pulse width(T
c
)=0.421msec and a a negative pulse width (T
d
)=0.269msec.
Let T
c
= 0.69 (R
A
+R
B
) C ---1, where T
c
is the time during which the output is high.
Let T
d
= 0.69 R
B
C------------2, where T
d
is the time during which the output is low
Calculate T = T
c
+T
d
1.Select C = 0.1 µF.
2.calculate R
B
using Equation 2
3.using the results in steps1,2,calculate R
A
using Equation 1
PROCEDURE:
1.Connect the circuit as shown in the figure.
2.Select the component values as per design.
3. Observe the output waveform at pin no 3.
4.Calculate the time during which the output is high and output is low.
Compare it with theoritical values.
5.Calculate the % duty cycle using the formula (Tc / T)*100. Compare it with theoritical
value.
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RESULT:
The output of Astable Multivibrator using 555IC is observed.
It is also observed that practical value of the time during which the output remains high and
output is low is same as theoritical value.
CONCLUSIONS:
It can be concluded that by changing the values of the Components (i.e., R
A
, R
B
and C),the
Pulse widths will be changed.
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V cc
R1
100kohm
R2
100kohm
Vcc/2
555
Output
0.01micro farad
Input
Vi
6
2
8 4
3
5
1
Department of Electronics and Communications Engineering
Experiment:15
SCHMITT TRIGGER
AIM: To observe the output of the Schmitt trigger using 741 & 555 IC’S
APPARATUS:1. Oscilloscope(20/30MHZ)
2. Power supply(0-30V)
3. Signal generator(0-1MHz)
4. Bread Board
5. Resistors 1KΩ-2No.s,560Ω,10KΩ
6. Resistors 100,50KΩ
7. Op-amp 741IC – 1No.
CIRCUIT DIAGRAM:
Fig(1a) Schmitt Trigger using 741 OP-Amp
Fig(1b) Schmitt Trigger using 555IC
-
+
+
ROM ≅ R
1
||R
2
+V
C
-V
EE
+15V
-
R
L
10KΩ
R
2
=50KΩ
V
lt
V
in
V
0
2
3 4
7
6
R
1
=100

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Department of Electronics and Communications Engineering
MODEL WAVEFORMS:
V
lt
V
0
Fig(1C)Input and output wave forms
Fig(1d)V
o
versus V
in
Plot of the Hysterisis Voltage
t
V
in
V
p
- V
p
- V
ut
0V
0V
t
+V
SAT
-V
SAT
+Vsat
+V
It
+V
ut
-Vsat
Vo
Vin
Hysteresis voltage
(V
ut
-V
it
)
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Department of Electronics and Communications Engineering
THEORY:
A)SCHMITT TRIGGER USING 741IC:
Figure (1a) shows an inverting comparator with positive feedback. This circuit
converts an irregular –shaped waveform to a square wave or pulse. The circuit is known as the
Schmitt trigger or squaring circuit.
The input voltage V
in
triggers (changes the state of) the output V
0
every time it exceeds certain
voltage levels called the upper threshold voltage V
ut
and lower threshold voltage V
lt
, as shown in
Figure (1c).
In Figure (1a), these threshold voltages are obtained by using the voltage divider R
1
-
R
2
, where the voltage across R
1
is fed back to the (+) input. The voltage across R
1
is a variable
reference threshold voltage that depends on the value and polarity of the output voltage V
0
.
When V
0
= +V
sat
, the voltage across R
1
is called the upper threshold voltage, V
ut
. The input
voltage Vin must be slightly more positive than V
ut
in order to cause the output Vo to switch
from +V
sat
to –V
sat
. As long as V
in
< V
ut
, V
o
is at +V
sat
. Using the voltage-divider rule,
| )
sat ut
V
R R
R
V +
+
·
2 1
1
1a
On the other hand, when V
0
= -V
sat
, the voltage across R
1
is referred to as the lower
threshold voltage, V
lt
. V
in
must be slightly more negative than V
lt
in order to cause V
0
to switch
from –V
sat
to +V
sat
. In other words, for V
in
values greater than V
lt
, V
0
is at –V
sat
. V
lt
is given by
the following equation:
| )
sat lt
V
R R
R
V −
+
·
2 1
1
1b
Thus, if the threshold voltage V
ut
and V
lt
are made larger than the input noise voltages,
the positive feedback will eliminate the false output transitions. Also, the positive feedback,
because of its regenerative action, will make V
0
switch faster between +V
sat
and –V
sat
. In Figure
(a), resistance R
OM
≅ R
1
¹¹R
2
is used to minimize the offset problems.
Figure (1c) shows that the output of the Schmitt trigger is a square wave when the input is a sine
wave. A noninverting comparator is used as a Schmitt trigger. When the input is a triangular
wave, the output of the Schmitt trigger is a square wave, where as if the input is a sawtooth
wave, the output is a pulse waveform.
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Department of Electronics and Communications Engineering
The comparator with positive feedback is said to exhibit hysteresis, a dead-band condition. That
is, when the input of the comparator exceeds V
ut
, its output switches from +V
sat
to –V
sat
and
reverts back to its original state, +V
sat,
when the input goes below V
lt.
(See Figure 1d)
The Hysteresis voltage is equal to the difference between V
ut
and V
lt
.
Therefore,
V
hy
= V
ut
-V
lt
.
| ) | }
sat sat
V V
R R
R
− − +
+
·
2 1
1
---------- 2
ANALYSIS OF THE CIRCUIT 1A:
For 741,the maximum output voltage swing is ±14V.That is +V
sat
=14V and -V
sat
= -14V.
From equation 1a&1b,
| ) mV V
ut
5 . 27 14
5100
100
· + ·
| ) mV V
lt
5 . 27 14
5100
100
− · − ·
The Hysterisis Voltage=55mV.
B) SCHMITT TRIGGER USING 555:
The use of 555 timer as a Schmitt Trigger is shown in Figure(1b). Here the two internal
comparators are tied together and externally biased at
2
CC
V
through R
1
and R
2
. Since the upper
comparator will trip at
3
2
V
CC
and lower comparator at
3
1
V
CC
, the bias provided by R1 and R2 is
centered within these two thresholds. Thus, a sine wave of sufficient amplitude
(>
2 3
2
6
CC
CC
CC
V
V
V
− · ) to exceed the reference levels causes the internal flip-flop to alternately
set and reset, providing a square wave output as shown
in Fig1c. It may be noted that unlike conventional multi vibrator, no frequency division is taking
place
and the frequency of square wave remains the same as that of input signal.
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Department of Electronics and Communications Engineering
PROCEDURE:
1. Connect the circuit as shown in figure.
2. Apply a sinusoidal wave with peak voltage greater than the designed voltage (U
t
).
3. Observe the waveform on CRO.
4. Note that, when input sinusoidal voltage is more than V(U
t
), the output changes
from –V
sat
to +V
sat.
.
When V
in
is less than V(L
t
) the output changes from +V
sat
to –V
sat
.
5.Observe the output waveform on CRO.
6.Put the CRO in XY Mode[Input signal on Channel1& output signal on Channel2].
Then we can observe the Hysterisis Voltage Curve on the CRO.
From this Note down V
UT
and V
LT
.These are the extreme points of the curve on X-axis.
(Extreme Left and Extreme right)
7.Draw the waveforms on graph sheets.
6. Obtain the V(U
t
) and V(L
t
) from graph and compare them with the following
theoretical values.
V(U
t
) =
| )
]
]
]

+
2 1
1
R R
R
*(+V
sat
)
V(L
t
) =
| )
]
]
]

+
2 1
1
R R
R
*(-V
sat
)
7. Note down the Hysterisis voltage V
hy
= V
ut
– V
Lt
.
RESULT: Hence the output of Schmitt trigger using 741 & 555 IC’s is observed.
CONCLUSIONS:
From the Hysterisis voltage curve, it can be observed that, the top and bottom extremes are
+V
sat
and –V
sat
.
So we can conclude that the Hysterisis voltage curve is existing, in between +V
sat
and –V
sat
on Y-
axis.
On X-axis Hysterisis voltage curve is existing in between V
ut
and V
Lt
.
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NC
Current limit
Current Sense
INV-Terminal
NON INV-Terminal
Voltage REF
Gnd
NC
NC
Freq. Compensation
V
+
V
CC
V
out
V
Z
Department of Electronics and Communications Engineering
Experiment No:16
VOLTAGE REGULATOR USING LM 723 IC
AIM: To plot the regulation characteristics of the given IC LM 723
APPARATUS: Resistors 7.5 KΩ - 2, 3.9KΩ - 1, Capacitor 100 µF – 1, IC LM 723 –1, DRB,
Voltmeter 0-30V, Ammeter 0-100mA.
PIN DIAGRAM & FUNCTIONAL BLOCK DIAGRAM:
Fig.1(a) Pin diagram of LM723
L
M

7
2
3
Ref
Amp
Vz
+
V
ref
(-7V)
-
V
+
V
-
Constant
current
source
D
Section-1
Err
Amp
NI
INV
V
+
V
-
V
C V
0
Q
1
Q
2
CL
CS
Freq. Comp.
Section-2
Fig1 b: Functional Block diagram of 723 IC
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CIRCUIT DIAGRAM:
Part-1 : Input Voltage versus Output Voltage
Fig (2-a) Circuit diagram for Input Voltage versus Output Voltage
Part-2 Load Resistance R
L
versus Output Voltage (Vo)
Fig (2-b) Circuit diagram for Load Resistance R
L
versus Output Voltage
Fig(2-c) R
L
versus % Regulation curve
12
11
6
5
10
2
3
4
7
13
100µF
A
V
L
M

7
2
3
R
L
3.9K 7.5K
7.5K
0-30V
Line Voltage
(From DC power supply)
R
12
11
6
5
10
2
3
4
7
13
100µF
L
M

7
2
3
R
L
3.9K 7.5K
.5K
0-30V
V
%R
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Lendi Institute of Engineering and Technology, Vizianagaram 72
Department of Electronics and Communications Engineering
THEORY:
With the advent of Micro-electronics, it is possible to incorporate the complete circuit on
a monolithic silicon chip. This gives low cost, high reliability, reduction in size and excellent
performance.
Examples of Monolithic regulators are 78xx/79xx series(Three terminal regulators) and 723
general purpose regulators.
The three terminal regulators have the limitations
(1) No short circuit protection. (2) Output voltage (positive or negative) is fixed.
These limitations have been over come in the 723 general purpose regulators, which can
be adjusted over a wide range of both positive and negative regulated voltage. This IC is
inherently low current device, but can be boosted to provide 5amps or more current by
connecting external components.
The limitations of 723 are that it has no in built thermal protection. It also has no short circuit
current limits. 723 regulator IC is available in a 14-pin, dual-in-line package.
Fig.1-b shows the functional block diagram of a 723 regulator IC. It has two separate sections.
The zener diode, a constant current source and reference amplifier produce a fixed voltage of
about 7 volts at the terminal V
ref
. The constant current source forces the zener to operate at a
fixed point so that the zener outputs a fixed voltage.
The other section of the IC consists of an error amplifier, a series pass transistor Q1 and a current
limit transistor limit transistor Q2. The error amplifier compares a sample of the output voltage
applied at the 1NV input terminal to the reference voltage V
ref
applied at the NI input terminal.
The error signal controls the conduction of Q1. These two sections are not internally connected
but the various points are brought out on the IC package. 723 Regulated IC is available in 14 Pin
Dual – in – line package or 10 pin metal can.
The important features of 723 Regulated IC are as follows:
1) Input voltage 40V max
2) Output voltage adjustable from 2V to 37V
3) 150mA output current without external pass transistor
4) Output currents in excess of 10A possible by adding external transistors
5) It Can be used as either a linear or a switching regulator.
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Lendi Institute of Engineering and Technology, Vizianagaram 73
Department of Electronics and Communications Engineering
The electrical characteristics of 723 Regulated IC can be seen from Appendix.
The 723 IC can be used as Low Voltage (2V to 7V) and High Voltage (>7V) Regulators
Current Limit Protection:
The 723 IC is provided with a current limit facility. Current limiting refers to the ability of a
regulator to prevent the load current from increasing above a present value. The characteristic
curve of a current limited regulator is shown in the following fig.
Characteristic curve of a current limited regulator
The output voltage remains constant for load current below I
limit
. As current approaches the
limit the output voltages drops . The current limit I
limit
is set by connecting an external resistor
R
sc
between the terminals CL and CS . The CL terminal is also connected to the output terminal
V
o
and CS terminal is connected to the load resistance .
I
limit
= 0.5V/R
sc
Current fold back:
In current limiting technique, the load current is maintained at a present value and when
overload condition occurs , the output voltage V
o
drops to zero . However , if the load is short
circuited , maximum current does flow through the regulator. To Protect the regulator one must
devise a method which will limit the short circuit current and yet allow higher currents to the
load . Current fold back is the method used for this. The following figure shows the current fold
back characteristic curve
I
sc
Current fold back characteristic curve
______________________________________________________________________________
V
0
I
Load
V
Load
I
limit
V
0
I
Load
V
Load
I
knee
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Lendi Institute of Engineering and Technology, Vizianagaram 74
Department of Electronics and Communications Engineering
OBSERVATIONS:
Table:
1. Variation of V
out
withV
in
2. Variation of % Regulation with R
L
V
NL
=
PROCEDURE:
Part 1: Input Voltage versus Output Voltage
1. Connect the circuit as shown in the fig2-a.
2. Connect the supply between 12 & 7 terminals
3. Connect the voltmeter to 10 & ground terminals
4. Increase the input voltage and note down the corresponding output voltage
5. Initially the output voltage is increasing with an increase in input Voltage
At some value of input Voltage , the output voltage becomes constant
Note down all these readings from the multimeter.
6. Draw the Graph between the line voltage(V
in
) Versus output voltage( V
out
)
Line voltage
(V
in
)
Output
voltage
(V
out
)
R
L
) I
L
(mA) Output
voltage
(V
out
)
% Regulation
FL
FL NL
V
V V −
1.0
2.0
3.0
4.0
.
.
.
12.0
13.0
14.0
15.0
16.0
17.0
2111
1111
911
711
511
411
311
211
111
100
90
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Lendi Institute of Engineering and Technology, Vizianagaram 75
Department of Electronics and Communications Engineering
Part 2: Load Resistance R
L
versus Output Voltage (Vo)
1. Connect the circuit as shown in the fig 2-b.
2. Keep the voltage constant at which part 1 is obtained.
3. Keep the load resistance (DRB) in the maximum position
( keep all the Knobs of DRB in maximum position)
4. Decrease the load resistance (R
Load
) and note down the output current (I
Load
)and output
voltage.
5. Decrease the load resistance till the output current reaches maximum rated current and
note down the corresponding values of the output voltage.
6. Draw the Graph between the load resistance(R
Load
) and % regulation
RESULT:
Hence the output voltage of 723 regulator is observed for different input voltages . and the
characteristics of the IC LM 723 are plotted.
CONCLUSIONS :
It is concluded that the % regulation is decreased with an increase in the load resistance(R
Load
)
______________________________________________________________________________
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Lendi Institute of Engineering and Technology, Vizianagaram 76
Department of Electronics and Communications Engineering
Experiment No: 17
4 BIT DAC USING OP AMP
AIM: To observe the output of a Digital to analog converter using
(1)Binary weighted resistors (2) R and 2R resistors.
APPARATUS: Op-amp 741 – 1, Resistors(R) 10 KΩ - 4, 20KΩ(2R)- 4,
47KΩ - 1, 100Ω - 1, 22KΩ, Potentiometer – 1 No, Multimeter
CIRCUIT DIAGRAM:
+
-
Vo
R= 10k
b
0
+5V
+15V
-15V
2
3
7
4
6
LM741
R R
2R
2R 2R 2R
2R
b
1
b
2
b
3
R
F
= 22k
R
L
= 10k
+
-
+15V
-15V
V
O
R = 10k
R/4
R/2
R/8
b0
b1
b2
b3
+5V
LM741
2
3
7
4
6
RF= 1K
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Lendi Institute of Engineering and Technology, Vizianagaram 77
Department of Electronics and Communications Engineering
THEORY:
A Digital-to-Analog Converter is used when a Binary output from a digital system must be
converted to some equivalent Analog voltage or Current.The Binary output from a digital system
is difficult to interpret.However a DAC makes the interpretation easier.The function of DAC is
exactly opposite to that of ADC.
Advantages:1)It is simpler in construction when compared to ADC 2)It can be used to form the
ADC.
Types of D/A Converters:
There are two types of DACs available
1. D/A converter with Binary –weighted Resistors
2. D/A converter with R and 2R resistors.
i.e.,A D/A converter in its simplest form uses an op-amp and either binary weighted resistors or
R and 2R resistors.
1) D/A converter with Binary –weighted Resistors
Basic DAC Techniques: The schematic of a DAC is shown in Fig1. The input is an n-bit binary
word D and is combined with a reference voltage V
R
to give an analog output signal. The output
of a DAC can be either a voltage or current. Theory o/p voltage
V
0
= K V
FS
(b
1
2
-1
+b
2
2
-2
+…..+b
n
2
-n
) Eq-1
Where V
0
= output voltage
V
FS
= full scale output voltage
K = scaling factor usually adjusted to unity
b
1
b
2
…..b
n
= n-bit binary fractional word with the decimal point located at the left
b
1
= most significant bit (MSB) with a weight of V
FS
/2
b
n
= least significant bit (LSB) with a weight of V
FS
/2
n
DAC
+
V
0
+
_
V
R
(MSB)
(LSB)
b
1
b
n-1
Schematic of a DAC
Binary
Word B
I
0
b
n
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Lendi Institute of Engineering and Technology, Vizianagaram 78
Department of Electronics and Communications Engineering
D/A converter with binary weighted resistors
The above figure2 shows D/A converter using op-amp and binary weighted resistors
.Although in this figure the op-amp is connected in the inverting mode it can also be connected
in the non inverting mode, Since the number of binary inputs is four,the converter is called 4 bit
(binary digit) converter .
Because there are 16( 2
4
) combinations of binary inputs for b0 through b3 an analog output
should have 16 possible corresponding values .In Fig2, four switches(b0to b3) are used to
stimulate the binary inputs ;in practice , a 4 bit binary counter such as 7493 may be used instead .
When switch b0 is closed (connected to +5V),the voltage across R is 5V because V
2
=V
1
=0V. Therefore R is 5V/10kΩ= 0.5mA .However , the input bias current I
B
is negligible; hence
the current through feedback resistor R
F
is also 0.5 mA ,which ,in turn produces an output
voltage of
–(1kΩ)(0.5mA) = -0.5V.Note that the op-amp is working as a current –to- voltage converter .
Now suppose that switch b1 is closed and b0 is opened .This action connects R/2 to the
positive supply of +5V, causing twice as much current (1mA) to flow through R
F
which in turn
doubles the output voltage .Thus the output voltage Vo is -1V When b1 switch is closed .
Similarly ,if both switches b0 and b1 are closed ,the current through R
F
will be 1.5 mA ,
which will be converted to an output voltage of –(1kΩ)(1.5mA)= -1.5V.
Thus, depending on whether switches b0 to b3 are open or closed , the binary weighted
currents will be set up in input resistors .The sum of these currents is equal to the current through
R
F
, which in turn is converted to a proportional output voltage .
When all the switches are closed ,obviously the output will be maximum .The output
voltage equation is given by
Vo = - R
F
,
`

.
|
+ + +
8 /
3
4 /
2
2 /
1 0
R
b
R
b
R
b
R
b
Where each of the inputs b
3
,b
2
,b
1
and b
0
may either be high (+5V) or low (0V).
Fig b shows analog outputs versus possible combinations of inputs .The output is a negative
going staircase waveform will 15 steps of -0.5V each in practice , however the steps may not all
be the same size because of the variations of the logic high voltage level .Notice that the size if
the steps depends on the value of R
F
Therefore a desired step can be obtained by selecting a
proper value of R
F
provided that the maximum output voltage doesnot exceed the saturation
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Lendi Institute of Engineering and Technology, Vizianagaram 79
Department of Electronics and Communications Engineering
levels of an op-amp .For accurate operation of the D/A converter precision metal film resistors
are recommended
Draw backs: The problem with D/A converter is that it requires binary weighted resistors which
may not readily available ,especially if the number of inputs more than four .An alternative is to
use R and 2R resistors for the D/A converter since it requires only two sets of precision
resistance values
D/A converter with R and 2R
Fig( a ) shows D/A converter with R and 2R resistors . As before, the binary inputs are simulated
by switches b0 through b3 and the output is proportional to the binary inputs .Binary inputs can
be in
either the high (+5v) or low (0v) state .Assume that the most significant bit (MSB) switch b3 is
connected to +5V and other switches are connected to ground , as in Fig (a ). Thevenizing the
circuit to the left of switch b3 .Thevenin’s equivalent resistance R
TH
is
R
TH
= [{[(2R 2R +R) 2R]+R} 2R]+R
= 2R= 20KΩ
The resultant circuit is shown in fig(B) .In this fig the (-) input is at virtual ground (V
2
≅0V) ;
therefore , the current through R
TH
(= 2R) is zero However , the current through 2R connected
to +5V is
Ω K
V
20
5
= 0.25mA .The same current flows through R
F
and in turn produces the output
voltage V
o
= -(20kΩ) (0.25mA) = - 5V
Using the same analysis, the output voltage corresponding to all possible combinations of binary
inputs can be calculated .The maximum or full –scale output of -9.375 V is obtained when all
the inputs are high .The output voltage equation can be written as
V
o
= - R
F
,
`

.
|
+ + +
R
b
R
b
R
b
R
b
16
0
8
1
4
2
2
3
Where each of the inputs b3, b2, b1 and b0 may be either high(+5V) or low (0V)
The great advantage of the D/A Converter is that it requires only two sets of precision
resistance values; nevertheless, it requires more resistors and is also more difficult to analyze
than the binary –weighted resistor type .As the number of binary inputs is increased beyond four,
both D/A converter circuit get complex and their accuracy degenerates. Therefore, in critical
applications an integrated circuit specially designed as D/A converter should be used.
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Lendi Institute of Engineering and Technology, Vizianagaram 80
Department of Electronics and Communications Engineering
OBSERVATIONS
S.No Digital Inputs Analog Output
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
PROCEDURE:
1. Connect the circuit as shown in the diagram.
2. Connect the output of ladder to the input of op-amp 741 ,
3. Observe the output of op-amp 741 with DMM.
4. For each value of input variation measure the output voltage with DMM and tabulate
the values.
5. Now remove DMM and observe the output on CRO.
6. Check whether the output of amplifier is a staircase waveform.
RESULT: Operation of digital to analog converter is verified.
_____________________________________________________________________________
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