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ECE 5202: Integrated Circuit Microfabrication
Prof. Carlos H. Mastrangelo

TR 12:25-1:45
WEB 1450


Fall 2012
Lecture 20

Gated Diode MOS Capacitor
MOS Field Effect Transistors
Lecture Outline
Gated-Diode MOS structure
Effect of substrate bias
Capacitance vs Gate voltage relations
Fixed charges and flatband changes
MOS Capacitor formulas

MOS Field Effect Transistors
Transistor Types nMOS and pMOS
CMOS
Threshold voltage and formation of channel
I
d
-V
ds
characteristics
Linear regime
Saturation
Channel length modulation
Parameter Extractions
MOS Transistor formulas

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Gated Diode MOS Structure


Gated diode MOS structure



Three terminal device
n-MOS Gated Diode
n+
Metal gate
oxide
P-type Silicon
GS
V
SB
V
gate terminal
source terminal
body terminal
Normally source is at body potential or at reverse bias V
SB
> 0
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The Source Voltage Modulates Depletion Region
n+
Metal gate
oxide
P-type Silicon
GS
V
SB
V
gate terminal
source terminal
body terminal
V
SB
must be dropped across x
d
shifts threshold voltage
( )
d SB
x V
Same Depletion Regime Equations
2
2
A
Si d
Si
qN
V x
c
=
Voltage drop across standard box profile
Of width x
d
and doping concentration N
A
Si A d
Q qN x =
Charge on depletion region
Si A d
oxide
ox ox
Q qN x
V
C C
= =
Voltage drop across oxide depends on the
depletion charge
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Now we can write the whole thing as a
function of x
d
1 1 1
( )
ox d
G ox Si Si ox Si
t x
C C C V c c
= + = +
2
2
A d A d
GB FB
ox Si
qN x qN x
V V
C c
= + +
Expect capacitance to drop with x
d
Expect gate voltage to increase with increased x
d
1
( )
G
ox d
ox Si
C
t x
c c
=
+
S
V
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Band Diagram at Onset of Inversion
( )
S B
q V V
( )
S B
V V
Same MOS Capacitance Curve but now
shifted by V
SB
ox
C
ox si
ox
ox si
C C
C
C C
= <
+
GB FB SB
V V V = +
Accumulation
GB FB SB
V V V < +
GB FB SB
V V V > +
Depletion
Note that the extra reverse bias on the diffusion is added to the gate to
body voltage
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Generally we measure gate-to-source
capacitance V
GS
ox
C
ox si
ox
ox si
C C
C
C C
= <
+
GS FB
V V =
Accumulation
GS FB
V V <
GS FB
V V >
Depletion
Same equation as before !
Inversion Regime Equations
(at Threshold)
2
max max
( ) ( ) | 2 |
2
A
Si d i SB
Si
qN
V x V o
c
= = +
Voltage drop across standard
box profile is increased
max
2 (| 2 | )
Si A d si A i SB
Q qN x q N V c o = = +
Maximum charge on
depletion region
2 (| 2 | )
si A i SB
Si
oxide
ox ox
q N V
Q
V
C C
c o +
= =
Voltage drop across oxide
depends on the depletion
charge at treshold
ln( )
A
i
i
N kT
q n
o =
max
2 (| 2 | )
si i SB
d
A
V
x
qN
c o +
=
Maximum depletion
region width
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Shifted Threshold Voltage Equations
Minimum capacitance
is independent of V
GS
but dependent on V
SB

GS T FB oxide Si SB
V V V V V V = = + + ln( )
A
i
i
N kT
q n
o =
Threshold voltage
(respect to source)
2 (| 2 | )
| 2 |
si A i SB
T FB i
ox
q N V
V V
C
c o
o
+
= + +
min
max
1 1
2(| 2 | )
( )
( )
G
ox d
ox i SB
ox Si
ox si A
C
t x
t V
q N
o
c c
c c
= =
+
+
+
Gated diode n-MOS Capacitance Curve
ox
C
GS FB
V V =
Accumulation
GS FB
V V <
GS FB
V V >
Depletion
Note that the threshold depends on V
SB
GS T
V V >
Inversion
( )
GS T SB
V V V =
threshold
voltage
increases
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Shifted Threshold Voltage Equations
Threshold voltage
(respect to source)
for zero V
SB
0
2 | 2 |
| 2 |
si A i
T FB i
ox
q N
V V
C
c o
o = + +
0
( | 2 | | 2 |)
T T i SB i
V V V o o = + +
2
si A
ox
q N
C
c
=
Gamma is the body factor
Determines threshold shift
Units are in V
1/2

Threshold voltage (respect to source) for any V
SB
pMOS
C-V characteristic of n-type Semiconductor
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p-MOS Gated Diode
p+
Metal gate
oxide
N-type Silicon
GS
V
SB
V
gate terminal
source terminal
body terminal
Normally source is at body potential or at reverse bias V
BS
> 0
Gated diode p-MOS Capacitance Curve
Note that the threshold depends on V
BS
ox
C
GS FB
V V =
Accumulation
GS FB
V V >
GS FB
V V <
Depletion
GS T
V V <
Inversion
( )
GS T BS
V V V =
threshold
voltage
decreases
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p-MOS Threshold equations
Threshold voltage
(respect to source)
for zero V
BS
0
2 | 2 |
| 2 |
si D i
T FB i
ox
q N
V V
C
c o
o =
0
( | 2 | | 2 |)
T T i BS i
V V V o o = +
2
si D
ox
q N
C
c
=
Gamma is the body factor
Determines threshold shift
Units are in V
1/2

Threshold voltage (respect to source) for any V
BS
ln( )
D
i
i
N kT
q n
o =
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Q
F
for Si-SiO2 interface is usually positive negative V
TH
shift
A good interface has N
ss
=Q
F
/q of 10
10
-10
11
cm
-2
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Threshold Tailoring with Ion Implantation
I I
i i A D
Q qN qN qN = = =
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The delta function approximation of the implanted profile
Summary of n-MOS Threshold Voltage Formulas
0
0
2 | 2 |
| 2 |
P
N P
si A i
ss I
T FB i
ox ox ox
q N
qN qN
V V
C C C
c o
o = + +
0
( | 2 | | 2 |)
N N P P
T T P i SB i
V V V o o = + +
2
si A
P
ox
q N
C
c
=
Threshold voltage (respect to source) for any V
SB
>0
N
FB
V
ln( )
P
A
i
i
N kT
q n
o =
0
FB MS
V = u
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Summary of p-MOS Threshold Voltage Formulas
0
0
2 | 2 |
| 2 |
N
P N
si D i
ss I
T FB i
ox ox ox
q N
qN qN
V V
C C C
c o
o =
0
( | 2 | | 2 |)
P P N
T T N iN BS i
V V V o o = +
2
si D
N
ox
q N
C
c
=
Threshold voltage (respect to source) for any V
BS
> 0
N
FB
V
ln( )
N
D
i
i
N kT
q n
o =
0
FB MS
V = u
Summary: Parameters Affecting V
TH
S
V
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MOS Field Effect Transistors
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n-MOS Transistor (n-channel)
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n-MOSFET I-V Analysis
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n-MOSFET I-V (ideal) Characteristics
Mobility of Inversion Charges
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n-MOS Tx Model Equations
( ( ) )
2
DS
DS GS T SB DS
V W
I k V V V V
L
| |
=
|
\ .
( )
SAT
DS DS GS T
V V V V < =
Linear or Triode regime (looks like nonlinear resistor between source and drain)
Saturation regime (looks like imperfect current source between source and drain)
2
( ( )) (1 )
2
DS GS T SB DS
k W
I V V V V
L

| |
= +
|
\ .
( )
SAT
DS DS GS T
V V V V > =
N ox
k C u = =
0
( ) ( | 2 | | 2 |)
T SB T i SB i
V V V V o o = + +
Channel length
modulation factor
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Parameter Extraction from I-V
Saturation Method
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Linear Regime Method (better)
Body Coefficient Extraction (saturation)
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Mobility and k parameters
n-MOSFET Transconductance
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Channel Modulation
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