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Inductorless oscillator design for personal communications devices A 1.

2 pm CMOS process case study

Tadeusz Kwasniewski*,Maamoun Abou-Seido*, Aurelie Bowhet**, Fabien GauSSOrgues**,Jacques Zimmerman**

*Department of Electronics, Carleton University, Ottawa,Ontario, K1S 5B6 Canada *+LPCS,INPC, 23, rue des Martyrs, BP257,38016 Grenoble, CEDEX 1, France


Three different 1.2 pm CMOS ring oscillator type VCO architectures have been presented. The VCO's are intended for the use as building blocks of digital radio fiequency synthesizer. It is demonstrated that linear control and improved phase-noise performance can be obtained by employing circuit design techniques and time domain based circuit optimization. The measurements results indicate that the maximum oscillating frequency range from 460 MHz to 900 MHz, power dissipation (at 5 Volts) from 6.5 to 11.5 mW and phase-noise at a 100 kHz carrier offset in a range of -83 to -95 dBc.



Modulus Control

vices for those components operating at the highest frequency i.e. the prescaler and VCO. Not only the technologies used preclude the use of a standard CMOS process but in the case of VCO an extemal LC tank is used resulting in an increased system component count. Recent research results [ 11, [2], [3] indicate the feasibility of a fully integrated CMOS, giga-hertz range frequency synthesizer. It is generally recognized that the phase-noise of a ring oscillator is inversely proportional to the voltage transition slope and the node capacitance value [41,[51. The resulting design guidelines call for large node charging o currents a condition equivalent t increased power consumption. In this presentation we attempt to answer the question of whether it is possible to improve the oscillator performance by equalizing and maximizing the slopes of the VCO node voltages. A differential structure has also been designed to confirm theoretidsimulation predictions of an improved phase noise performance. Although not an issue for an integrated VCO the problem of driving an extemal load has been addressed by designing a highspeed output driver. Circuit design In his often cited paper on noise in relaxation escalators Abidi [4] relates the oscillator jitter to the node rms , voltage noise V and the slope S of the node voltage transition.

Loop Filter


Figure 1 Typical building blocks for a modem RF PLL frequency S

The emerging markets for digital radio and highspeed data transmission result in an increased demand for
low-power consumption. low-phase noise components for CMOS frequency synthesizer where frequency in conrolled by applying a digital control K (see Fig. 1). Today's state of the art solutions employ either bipolar or GaAs de-

where a is a circuit dependent, and i denotes the i* transition (two transitions per node). In our previous paperf21 the sole optimization criteria used was the maximum operating frequency. This resulted in a circuit which node voltage did not exhibit equal voltage swing or equal slopes.
0-7803-2584-2/95 $3.00 01995 IEEE


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Fig. 2 show the circuit and the corresponding time domain waveforms. It is worth noting that according to Eq.1 a single

inverters. The differential structure reduces the effect of power supply noise. This improvement is however achieved at theprice of a decreased maximum oscillating frequency due to an increased node capacitance. The node capacitance increases as the result of the added cross-coupling transistors. Fig. 3b shows the time domain waveforms while Fig. 3c the VCO transfer characteristic.

Control Voltage

a) schematic

a) schematic

T m I=]

b) node voltages

b) node voltages
GYwd vpec4 M

c) transfer charactenshcs

VCOl[2] ring oscillator structure

offending transition could significantly deteriorate the entire circuit noise performance.Considering the fact that only parasitic capacitances are used and realizing that bringing the output signal out results in added capacitive loading of one of the oscillatorsnodes, we devised a timedomain optimization for simultaneous voltage excursion ( m u value desired) and slope ( m a value desired). Such an optimization resulted in a nearly rail-to-rail equal
slopes circuit operation.Fig. 3a shows the corresponding

Conad Vohage M

c) transfer characteristics
FIGURE 3. VC02 optimized oscillator structure

schematic diagram while Fig. 3b the time domain simulation of the same circuit. This VCO circuit (VC02) has also, as compared to VCOI, a wide range linear frequency control. It is worth noting that the optimization included not only the transistors in the main inverter chain but also transistors used in the linear frequency control circuitry The third structure considered is the differential structure, the two inverter rings are cross-connected by

As expected the power consumption of all three of the VCOs is linear function of the oscillating frequency. As an example Fig. 5 shows the power dissipation of vc02
Obtaining a strong output signal (at an I.C. pin) for a circuit operating in the frequency range form 500 to loo0 MHz in 1 . 2 CMOS process is a challenge on its own. ~ A custom designed multi-staged buffer was used to drive the output of each VCO. The drivers optimization simula-


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tions included the model of the bonding wire inductance and pin capacitance.




680 685 6D0 695 M m homr I M W l &

FIGURES Power ~ o n s u m ~ t i o n V C O ~ . of
Circuit Implementation The circuits were implemented in a 1.2pm doublepoly, double-metal,N-well CMOS technology. In this secT i tion, layout related design considerations associated with VCO sensitivity to power supply fluctuations, and noise of adjacent on chip circuitry are presented. Separate power supply pads for the VCO circuit reduced its sensitivity to the supply voltage noise. Such configuration also aided in the VCO's power consumption measurement. On-chip decoupling capacitors between vdd and gnd lines were added to filter the power supply high frequency noise. tTo " S isolate the VCO circuit from substrate noise of adjaVoltage I fully cent circuitry, additional substrate contacts were placed i.0 within the N and P wells. Double guard rings of n+ and pt connected to a stable vdd and gnd rails were placed around each well of the VCO cell as shown in Fig.(4). I

- . ,.




a) schematic

I contact

b) node voltages


substrate noise of adjacent circuitry

0 metal 1

FIGURE 6 Guard rings around the W O cell, to reduce .

Experimental Results

c) transfer characteristics VC03 aosscoupled rings oscillator structure

COnmrl Vobge [q

The experimantal oscillators were evaluated in a test bed built to minimize the power supply noise and W frequency pick-up. The output signal was probed by a highimpedance, high-frequency probe to minimize current load on the CMOS output drivers. The output amplitude o due t the special high-frequency output driver design used had the rms value of 0.4 t 0 7 V l s o . ot.

The VCO's phase noise was measured using the H P 3048A phase-noise measurement system, using the phase detector measurement technique (also called quadrature



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technique), a phase locked loop was applied to keep the VCO signal and the reference in %degree phase relationship. Table 1 summarizes the performance parameters of the PLL components in this design.

9 0MHz. The phase noise measured at lOOkHz Carrier 0 offset equals -83, -89 and -95dBc. These results combined with the power dissipation of approximately lOmW
clearly indicate that by using submicron CMOS technology good quality @reviously achievable only by LC t n ak bipolar circuits) oscillators can be built which reach a frequency range of two gigahertz.

FIGURE 9. The layout of the VCOs chip

I ,U<
1111Iu 111

L(O clinc,,iiii


i r i ~ i


m a m

V C 0 2 measured residual FWSSB phase noise

,.I? :/, , *

I .

o ~ ~ , - . . - . .:-* ..................~ .................................... ,,,, E..



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The authors wish to thank Canadian Microelectronics Corporation for fabrication support. Also, assistance from Rhone-Alps region (France) and INPG as well as technical assistance and access to measurements facility of Telecommunication Research Institute of Ontario is gratefully acknowledged. This work was supported by the (Canadian) Strategic Microelectronics Consortium and Strategic Technologies Program of Industry Canada within the Ultra-Low-Power Building Blocks for Portable Radio
Applications Project.


VC03 measured residual FM/SSB phase noise

L t l ) [dBc/Hzl



Max. Operating Frequency (MHz) Phase Noise at loOKHz offset Power (mW) at Fmax Table 1 Summary of measurement results, * excluding the output buffer circuit.

Jonathan Min, Ahmadrexa Rofougaram, Henry Samneli and Ased A. Abidi, An all-CMOS architecture for a low-power frequency-hopped 900 MHz spread spectrum transceiver, IEEE Custom ICs Conf. Proceeding, 1994. Manop Thamsirianunt and Tadeus A. Kwasniewski, A 1.2 CMOS implementation a low-power 900MHz mobile radio frequency synthesizer, IEEE Custom ICs Conf. Proceeding, 1994.
R. Rogenmoser, Q. Huang, E Piazza,1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 pm CMOS prescalers, IEEE Custom ICs Conf. Proceeding,

Three ring oscillator sfructures were implemented in

1 . 2 CMOS technology and evaluated for their maxi~

mum operaling frequency and phase noise performance. The structures included a previously reported [2] simple ring oscillator configuration and two new ones designed for improved phase noise performance. Maximum operathe ing frequency of the t r e oscillators varies from 460 to

Asad A. Abidi and R.G. Meyer, Noise in relaxation oscillators, IEEE Jour. Solid-state Ccts., Vol.SC-18, No.6, pp. 794-802, April, 1983. Todd C. Weigandt, Beomsup Kim, Paul R. Gray, Analysis of timing jitter in CMOS ring oscillators, ISCAS 1994.


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