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PLD, SPLD, GAL, CPLD, FPGA Design

4-tap FIR flter vhdl error-HELP!!!!

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Thread: 4-tap FIR flter vhdl error-HELP!!!!
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08-04-10, 18:41

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vampiro
Newbie level 3 Join Date: Posts: Helped: Feb 2010 4 0/0

4-tap FIR flter vhdl error-HELP!!!!
Hi, I wrote a VHDL code for a 4 tap fir filter. I am not getting errors when I compile using altium designer. but when I put in Xilinx ISE 9.2i I'm getting an error saying " Line 34. Choices for an array aggregate (Attribute name) must be locally static unless there is only one choice. (LRM 7.3.2.2) which I don't understand. Can someone please help!! I need to solve this ASAP this is the whole code... Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity FIR_Test is GENERIC (n:INTEGER:=4; m: INTEGER :=4); Port (x:in SIGNED(m-1 downto 0); clk,rst:in std_logic; y:out SIGNED(2*m-1 downto 0)); end FIR_Test; ARCHITECTURE RT1 of FIR_Test is TYPE registers IS ARRAY (n-2 DOWNTO 0) OF SIGNED(m1 DOWNTO 0); TYPE coefficients IS ARRAY (n-1 DOWNTO 0) OF SIGNED (m-1 DOWNTO 0); SIGNAL reg : registers; CONSTANT coef: coefficients :=("0001" , "0010" , "0011" , "0100"); BEGIN PROCESS(clk,rst) VARIABLE acc, prod: SIGNED(2*M-1 DOWNTO 0) := (OTHERS=> '0'); VARIABLE sign : STD_LOGIC; BEGIN IF (rst='1') THEN FOR i IN n-2 DOWNTO 0 LOOP

END LOOP. FOR i IN 1 TO n-1 LOOP sign := acc(2*m-1). END IF. Devas Reply With Quote . END IF. OTHERS => NOT sign). END LOOP. y<= acc. reg<= x & reg(n-2 DOWNTO 1). ELSIF (clk'EVENT AND clk = '1') THEN acc := coef(0)*x. prod := coef(i) * reg(n-1-i). 08:58 #2 devas Full Member level 2 Join Date: Posts: Helped: Jun 2009 129 40 / 40 Re: 4-tap FIR flter vhdl error-HELP!!!! Hi. END LOOP. As you use 'LEFT to assign a value to acc. IF (sign=prod(prod'left)) AND (acc(acc'left) /= sign)THEN acc := (acc'LEFT => sign. Reply With Quote 09-04-10.FOR i IN n-2 DOWNTO 0 LOOP FOR j IN m-1 DOWNTO 0 LOOP reg(i)(j) <= '0'. END rt1. acc := acc + prod. The width of the variable 'acc' depends on the generic M. the bit number of this assignment depends on the generic M and can be different for several instantiations of this fir_test and is therefor not "locally" static. END PROCESS.

----------------------------------------------------------------------------------------------------------------LIBRARY work. x: IN UFIXED (2-1 DOWNTO -6).all. ----------------------------------------------------------------------------------------------------------------entity Fir_Circular_Fixo is -. Brazil 2 0/0 . 19:39 #3 MarcosMedeiros Newbie level 2 4-tap FIR flter vhdl error-HELP!!!! VAMPIRO. Join Date: Location: Posts: Helped: Jun 2010 Fortaleza.NumCoef: INTEGER := 8.STD_LOGIC_1164. Do you know how? Here I used my fixed-point version: ----------------------------------------------------------------------------------------------------------------LIBRARY ieee. USE work. USE ieee.dec: INTEGER := 6 -.Número de bits da parte decimal do número -. it's no more generic. because I declared the generics m and n inside the architecture. and I replaced the integer values of m and n inside some parts of the process. USE ieee. USE work. -.Número de bits das entradas e dos coeficientes() -.math_utility_pkg. Reset: IN STD_LOGIC.Número de coeficientes -.all.07-06-10. I'm looking for a solution for make this code generic again. What did you do to run that filter? I had this same problem on ISE 10.fixed_pkg. y: OUT UFIXED (2*2-1 DOWNTO -(2*6)) ).std_logic_arith.ALL. PORT( ClockFIR.GENERIC( m: INTEGER := 2. that is generic.).1 to run on a STARTAN 3-E The code. -.ALL.

TYPE Coeficientes IS ARRAY (8-1 DOWNTO 0) OF UFIXED (2-1 DOWNTO -6). END IF.Incrementa o estado e desloca o vetor de retardo. SIGNAL Vetor_Retardo: Registradores. END LOOP. SIGNAL m: INTEGER := 2. Vetor_Retardo <= x & Vetor_Retardo(8-2 DOWNTO 1). OTHERS => NOT sinal). "01000000". "11100000". END PROCESS.Número de bits da parte decimal do número CONSTANT Coef : Coeficientes := ("00000000". . -. prod: UFIXED(2*2-1 DOWNTO -(2*6)). accum := resize(accum + prod.end Fir_Circular_Fixo. "01000000".Número de coeficientes SIGNAL dec: INTEGER := 6. END LOOP. ELSIF (ClockFIR'EVENT AND ClockFIR = '1') THEN accum := coef(0) * x. -. END IF.Número de bits das entradas e dos coeficientes SIGNAL NumCoef: INTEGER := 8.Verificação de overflow IF (sinal = prod(prod'LEFT)) AND (accum(accum'LEFT) /= sinal) THEN accum := (accum'LEFT => sinal. -. y <= accum. BEGIN -. -.Reset: Zera a linha de retardo do filtro FIR IF (Reset = '1') THEN FOR i IN 8-2 DOWNTO 0 LOOP FOR j IN (2+6)-1 DOWNTO 0 LOOP Vetor_Retardo (i)(j) <= '0'. y'high. Reset) VARIABLE accum. VARIABLE sinal : STD_LOGIC.:= (OTHERS => '0'). -.Impulso "11000000". END LOOP. prod := coef(ii) * Vetor_Retardo(NumCoef-1-ii). FOR ii IN 1 TO 8-1 LOOP sinal := accum(2*m-1). ----------------------------------------------------------------------------------------------------------------BEGIN PROCESS (ClockFIR. "10000000". -. "00000000").. "10000000". y'low). architecture Behavioral of Fir_Circular_Fixo is TYPE Registradores IS ARRAY (8-2 DOWNTO 0) OF UFIXED ((2+6-1) DOWNTO 0).

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