DSP56800E and DSP56800EX

Reference Manual
Digital Signal Controller Cores

DSP56800ERM Rev. 3 09/2011

freescale.com

Contents
About This Book
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxviii Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx

Chapter 1 Introduction
1.1 1.2 1.3 1.4 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example DSP56800EX Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-3 1-4 1-5

Chapter 2 Core Architecture Overview
2.1 Extending DSP56800E Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 Extending DSP56800 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.3 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 Dual Harvard Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 System Architecture and Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5.1 Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5.2 Address Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.5.3 Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.5.4 Data Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5.5 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5.6 Program Controller and Hardware Looping Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.5.7 Bit-Manipulation Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.5.8 Enhanced On-Chip Emulation (Enhanced OnCE) Unit . . . . . . . . . . . . . . . . . . . . . 2-11 2.6 Blocks Outside the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.6.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.6.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.6.3 Bootstrap Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.6.4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

Chapter 3 Data Types and Addressing Modes
3.1 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

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3.2 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.1 Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.1.1 Signed Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.1.2 Unsigned Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.1.3 Signed Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.1.4 Unsigned Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.2 Understanding Fractional and Integer Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 Memory Access Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1 Move Instruction Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.1.1 Ordering Source and Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.1.2 Memory Space Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.1.3 Specifying Data Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.2 Instructions That Access Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.2.1 Signed and Unsigned Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.2.2 Moving Words from Memory to a Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.2.3 Accessing Peripheral Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.3 Instructions That Access Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.4 Instructions with an Operand in Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.5 Parallel Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.3.5.1 Single Parallel Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.5.2 Dual Parallel Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.4 Data Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4.1 Data Alignment in Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4.2 Data Alignment in Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.3 Data Alignment in 24-Bit AGU and Control Registers . . . . . . . . . . . . . . . . . . . . . 3-14 3.4.4 Data Alignment in 16-Bit AGU and Control Registers . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.5 Data Alignment in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.4.5.1 Byte and Word Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.5.2 Byte Variable Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.4.5.3 Word Variable Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.4.5.4 Long-Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5 Memory Access and Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.1 Word and Byte Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.5.2 Accessing Word Values Using Word Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.3 Accessing Long-Word Values Using Word Pointers . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.5.4 Accessing Byte Values Using Word Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.5.5 Accessing Byte Values Using Byte Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.6 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.6.1 Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.6.2 Register-Direct Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.6.3 Address-Register-Indirect Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.6.3.1 No Update: (Rn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.6.3.2 Post-Increment: (Rn)+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3.6.3.3 Post-Decrement: (Rn)– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3.6.3.4 Post-Update by Offset N: (Rn)+N, (R3)+N3 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 3.6.3.5 Index by Offset N: (Rn+N). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.6.3.6 Index by 3-Bit Displacement: (RRR+x), (SP–x) . . . . . . . . . . . . . . . . . . . . . . . 3-34

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3.6.3.7 3.6.3.8 3.6.3.9 3.6.4 3.6.4.1 3.6.4.2 3.6.4.3 3.6.4.4 3.6.4.5 3.6.4.6 3.6.5 3.6.5.1 3.6.5.2 3.6.5.3 3.6.5.4 3.6.6 3.6.7

Index by 6-Bit Displacement: (SP–xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index by 16-Bit Displacement: (Rn+xxxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . Index by 24-Bit Displacement: (Rn+xxxxxx) . . . . . . . . . . . . . . . . . . . . . . . . . Immediate Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-Bit Immediate Data: #x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-Bit Immediate Data: #xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-Bit Immediate Data: #xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-Bit Immediate Data: #xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit Immediate Data: #xxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Bit Immediate Data: #xxxxxxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Short Address: aa. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Short Address: <<pp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-Bit Absolute Address: xxxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-Bit Absolute Address: xxxxxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implicit Address Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit-Reverse Address Mode (DSP56800EX Core only) . . . . . . . . . . . . . . . . . . . . .

3-35 3-36 3-37 3-38 3-38 3-38 3-38 3-39 3-39 3-41 3-41 3-42 3-43 3-44 3-45 3-45 3-45

Chapter 4 Instruction Set Introduction
4.1 Instruction Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 Multiplication Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.3 Shifting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.1.4 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.1.5 AGU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.1.6 Bit-Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.1.7 Looping Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.1.8 Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.1.9 Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2 Instruction Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.1 The ANDC, EORC, ORC, and NOTC Aliases. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.2 Instruction Operand Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.2.1 Duplicate Operand Remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.2.2 Addressing Mode Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3 Delayed Flow Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.1 Using Delayed Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.3.2 Delayed Instruction Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.3.3 Delayed Instructions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.1 Using the Instruction Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.2 Register Field Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.4.3 Immediate Value Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.4.4 Instruction Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.4.5 Parallel Move Summary Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 4.5 Register-to-Register Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-51

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Chapter 5 Data Arithmetic Logic Unit
5.1 Data ALU Overview and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 Data Registers (X0, Y1, Y0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.2 Accumulator Registers (A, B, C, D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.3 Multiply-Accumulator (MAC) and Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.1.4 Single-Bit Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.1.5 Arithmetic and Logical Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.1.6 Data Limiter and MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2 Accessing the Accumulator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.2.1 Accessing an Entire Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.2.1.1 Writing an Accumulator with a Small Operand . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.2.1.2 Using the Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.2.2 Accessing Portions of an Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.2.3 Reading and Writing Integer Data to an Accumulator . . . . . . . . . . . . . . . . . . . . . . 5-12 5.2.4 Reading 16-Bit Results of DSC Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.2.5 Converting a 36-Bit Accumulator to a 16-Bit Value . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.6 Saving and Restoring Accumulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.7 Bit-Manipulation Operations on Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3 Fractional and Integer Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3.1 DSP56800E Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.2 Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.3 Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.3.3.1 Fractional Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.3.3.2 Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.3.3.3 Operand Re-Ordering for Multiplication Instructions . . . . . . . . . . . . . . . . . . . 5-20 5.3.4 Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.3.4.1 General-Purpose Four-Quadrant Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.3.4.2 Positive Dividend and Divisor with Remainder . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.3.4.3 Signed Dividend and Divisor with No Remainder . . . . . . . . . . . . . . . . . . . . . . 5-23 5.3.4.4 Division Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.3.5 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.3.6 Shifting Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.3.6.1 Shifting 16-Bit Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.3.6.2 Shifting 32-Bit Long Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.3.6.3 Shifting Accumulators by 16 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.3.6.4 Shifting with Accumulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4 Unsigned Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.1 Condition Codes for Unsigned Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.2 Unsigned Single-Precision Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.5 Extended- and Multi-Precision Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.5.1 Extended-Precision Addition and Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.5.2 Multi-Precision Fractional Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.5.3 Multi-Precision Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.5.3.1 Signed 32-Bit × Signed 32-Bit with 32-Bit Result . . . . . . . . . . . . . . . . . . . . . . 5-33 5.5.3.2 Unsigned 32-Bit × Unsigned 32-Bit with 32-Bit Result. . . . . . . . . . . . . . . . . . 5-34 5.5.3.3 Signed 32-Bit × Signed 32-Bit with 64-Bit Result . . . . . . . . . . . . . . . . . . . . . . 5-34
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5.5.3.4 Other Applications of Multi-Precision Integer Multiplication . . . . . . . . . . . . . 5.6 Normalizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Normalized Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Normalizing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Condition Code Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Condition Code Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Condition Codes and Data Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Saturation and Data Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 Instructions Not Affected by the MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . 5.9 Rounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.1 Convergent Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.2 Two’s-Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9.3 Rounding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-35 5-36 5-36 5-37 5-38 5-38 5-38 5-39 5-39 5-41 5-42 5-43 5-44 5-46 5-46

Chapter 6 Address Generation Unit
6.1 AGU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1.1 Primary Address Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.1.2 Secondary Address Adder Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.3 Single-Bit Shifting Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2 AGU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.1 Address Registers (R0–R5, N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.2 Stack Pointer Register (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2.3 Offset Register (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.4 Secondary Read Offset Register (N3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.5 Modifier Register (M01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.6 Shadow Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3 Using Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.4 Byte and Word Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5 Word Pointer Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.5.1 Accessing Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.2 Accessing Long Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.3 Accessing Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.4 Accessing Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6 Byte Pointer Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6.1 Byte Pointers vs. Word Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.6.2 Byte Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.7 AGU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.8 Linear and Modulo Address Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.8.1 Linear Address Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.8.2 Understanding Modulo Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 6.8.3 Configuring Modulo Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.8.3.1 Configuring for Byte and Word Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.8.3.2 Configuring for Long Word Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.8.4 Base Pointer and Offset Values in Modulo Instructions. . . . . . . . . . . . . . . . . . . . . 6-26
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6.8.4.1 6.8.4.2 6.8.4.3 6.8.4.3.1 6.8.4.3.2 6.8.4.4 6.8.5 6.8.5.1 6.8.5.2 6.8.5.3 6.8.6 6.8.7 6.8.8 6.8.9 6.8.9.1 6.8.9.2 6.8.9.3

Operand Placement Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example of Incorrect Modulo Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Case - ADDA Instructions in Modulo Arithmetic . . . . . . . . . . . . . . . . Case 1. Adding a Positive Immediate Offset to a Pointer . . . . . . . . . . . . . Case 2. Adding a Negative Immediate Offset to a Pointer . . . . . . . . . . . . . Restrictions on the Offset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Memory Access Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulo Addressing for Word Memory Accesses . . . . . . . . . . . . . . . . . . . . . . Modulo Addressing for Byte and Long Memory Accesses . . . . . . . . . . . . . . . Modulo Addressing for AGU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . Simple Circular Buffer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up a Modulo Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wrapping to a Different Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Side Effects of Modulo Arithmetic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . When a Pointer Lies Outside a Modulo Buffer . . . . . . . . . . . . . . . . . . . . . . . . Restrictions on the Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Locations Not Accessible Using Modulo Arithmetic . . . . . . . . . . . .

6-26 6-27 6-28 6-28 6-28 6-28 6-29 6-29 6-29 6-30 6-30 6-32 6-33 6-34 6-34 6-34 6-34

Chapter 7 Bit-Manipulation Unit
7.1 Bit-Manipulation Unit Overview and Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.1 8-Bit Mask Shift Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.2 16-Bit Masking Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.3 16-Bit Testing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.4 16-Bit Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2 Bit-Manipulation Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1 Testing Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.2 Conditional Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.3 Modifying Selected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3 ANDC, EORC, ORC, and NOTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4 Other Bit-Manipulation Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.1 Bit-Manipulation Operations on Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.2 Bit-Manipulation Operations on Byte Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.2.1 Absolute Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.5.2.2 Word Pointers with Byte Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.5.3 Using Complex Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.5.4 Synthetic Conditional Branch and Jump Operations . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.5.4.1 JRSET and JRCLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.5.4.2 BR1SET and BR1CLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.5.4.3 JR1SET and JR1CLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

Chapter 8 Program Controller
8.1 8.1.1 Program Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 Instruction Latch and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

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8.1.2 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.1.3 Looping Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.1.4 Hardware Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.1.5 Interrupt Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.1.6 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2 Program Controller Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.1 Operating Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.1.1 Operating Mode (MA and MB)—Bits 0–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1.2 External X Memory (EX)—Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1.3 Saturation (SA)—Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1.4 Rounding (R)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1.5 Stop Delay (SD)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1.6 X or P Memory (XP)—Bit 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.2.1.7 Condition Code Mode (CM)—Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.1.8 Nested Looping (NL)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.2 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.2.1 Carry (C)—Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.2.2.2 Overflow (V)—Bit 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.2.2.3 Zero (Z)—Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.2.2.4 Negative (N)—Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.2.2.5 Unnormalized (U)—Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.2.2.6 Extension in Use (E)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2.7 Limit (L)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2.8 Size (SZ)—Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2.9 Interrupt Mask (I0–I1)—Bits 8–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2.10 Program Counter Extension (P0–P4)—Bits 10–14 . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.2.11 Loop Flag (LF)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.3 Loop Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.4 Loop Count Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.5 Loop Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.6 Loop Address Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.7 Hardware Stack Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.8 Fast Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.9 Fast Interrupt Return Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.3 Software Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.3.1 Pushing and Popping Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 8.3.2 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.3.3 Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.3.4 Parameter Passing and Local Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.4 Hardware Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.5 Hardware Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.5.1 Repeat (REP) Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.5.2 DO Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8.5.3 Specifying a Loop Count of Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.5.4 Terminating a DO Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.5.4.1 Allowing Current Block to Finish and Then Exiting . . . . . . . . . . . . . . . . . . . . 8-20 8.5.4.2 Immediate Exit from a Hardware Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21

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8.5.5 Specifying a Large Immediate Loop Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.6 Nested Hardware Looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.6.1 Nesting a REP Loop Within a DO Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.6.2 Nesting a DO Loop Within a DO Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.6.3 Nesting a DO Loop Within a Software Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Executing Programs from Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Entering Data-Memory Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Exiting Data-Memory Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.3 Interrupts in Data-Memory Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.4 Restrictions on Data-Memory Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-21 8-22 8-22 8-22 8-23 8-23 8-25 8-26 8-28 8-28

Chapter 9 Processing States
9.1 Normal Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 Reset Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 Exception Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.3.1 Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3.2 Interrupt and Exception Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3.2.1 Normal Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.3.2.2 Fast Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.3.3 Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3.1 External Hardware Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3.2 Hardware Interrupt Sources Within the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.3.2.1 Illegal Instruction Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.3.2.2 Hardware Stack Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.3.2.3 Misaligned Data Access Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.3.2.4 Debugging (Enhanced OnCE) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.3.3 Software Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.3.3.1 SWI Instruction—Level 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.3.3.2 SWI #x Instructions—Levels 0–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.3.3.3 SWILP Instruction—Lowest Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.3.4 Non-Interruptible Instruction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.4 Wait Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.4.1 Wait Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.2 Disabling Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.5 Stop Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.5.1 Stop Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.5.2 Disabling Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.6 Debug Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13

Chapter 10 Instruction Pipeline
10.1 Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Normal Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 General Pipeline Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Data ALU Execution Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10-3 10-3 10-4

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10.3 Pipeline During Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.1 Standard Interrupt Processing Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.2 The RTID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.3 Nested Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.3.4 SWI and Illegal Instructions During Interrupt Processing . . . . . . . . . . . . . . . . . . 10-11 10.3.5 Fast Interrupt Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.3.6 Interrupting a Fast Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.3.7 FIRQ Followed by Another Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.3.8 Interrupt Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.3.8.1 Interrupt Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.3.8.2 Re-Enabling Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.3.8.3 Cases That Increase Interrupt Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.3.8.4 Delay When Enabling Interrupts via CCPL . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.4 Pipeline Dependencies and Interlocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.4.1 Data ALU Pipeline Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.4.2 AGU Pipeline Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.4.3 Instructions with Inherent Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.4.3.1 Dependencies with Hardware Looping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31

Chapter 11 JTAG and Enhanced On-Chip Emulation (Enhanced OnCE)
11.1 Enhanced OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 Enhanced OnCE Module Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Enhanced OnCE System Level View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.3 Accessing the Enhanced OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.3.1 External Interaction via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.3.2 Core Access to the Enhanced OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3.3 Other Supported Interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4 Enhanced OnCE and the Processing States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.1 Using the Debug Processing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.2 Debugging and the Other Processing States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.4.3 Enhanced OnCE Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4.3.1 Command, Status, and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4.3.2 Breakpoint Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.4.3.2.1 Trigger Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.4.3.2.2 16-bit Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.4.3.2.3 Combining Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4.3.3 Step Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4.3.4 Change-of-Flow Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4.3.5 Realtime Data Transfer Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.4.4 Effectively Using the Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.4.1 Using the Step Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.4.1.1 Usage upon Exiting the Debug Processing State . . . . . . . . . . . . . . . . . . . 11-13 11.4.4.1.2 Step Counter Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.4.4.1.3 Other Step Counter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.4.4.2 Using the Breakpoint Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.4.4.2.1 Listing the Breakpoint Unit Triggers Available . . . . . . . . . . . . . . . . . . . . 11-16
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11.4.4.2.2 Breakpoint Unit Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4.2.3 Combining the Breakpoint Unit with the Step Counter . . . . . . . . . . . . . . 11.4.4.2.4 Breakpoint Unit — Step Counter Actions . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4.3 Capture Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4.3.1 16-Bit Capture Counter (Non-Cascaded) . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4.3.2 Actions for 16-Bit Capture Counter (Non-Cascaded) . . . . . . . . . . . . . . . 11.4.4.3.3 Using the Capture Counter with the Step Counter . . . . . . . . . . . . . . . . . . 11.4.4.3.4 16-bit Capture Counter — Step Counter Actions . . . . . . . . . . . . . . . . . . . 11.4.4.3.5 40-Bit Capture Counter (Cascaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.4.3.6 Actions for 40-Bit Capture Counter (Cascaded). . . . . . . . . . . . . . . . . . . . 11.4.4.4 Programmable Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.5 Example Breakpoint Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.1 JTAG Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2 JTAG Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2.1 JTAG Terminal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2.2 Core JTAG Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2.3 Core JTAG Port Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.2.4 Core TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5.3 JTAG Port Restriction — STOP Processing State . . . . . . . . . . . . . . . . . . . . . . . .

11-18 11-19 11-19 11-20 11-20 11-22 11-23 11-23 11-24 11-24 11-24 11-26 11-27 11-27 11-27 11-28 11-29 11-29 11-30 11-32

Appendix A Instruction Set Details
A.1 A.2 A.3 A.3.1 A.4 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.5.5 A.5.6 A.5.7 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 32 x 32 to 32/64 Multiply and MAC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . A-314 32 x 32 to 32/64 Multiplication and MAC Instruction Details. . . . . . . . . . . . . . . A-316 Test Bitfield and Set/Clear (BFSC) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-327 Instruction Opcode Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-329 Register Operand Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-330 MOVE Instruction Register Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-336 Encodings for Instructions that Support the Entire Register Set . . . . . . . . . . . . . A-338 Parallel Move Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-343 Addressing Mode Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-345 Conditional Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-345 Immediate and Absolute Address Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-346

Appendix B Condition Code Calculation
B.1 Factors Affecting Condition Code Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1.1 Operand Size and Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1.2 MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.1.3 Condition Code Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 B.2 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 B.2.1 Size Bit (SZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 B.2.2 Limit Bit (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5

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B.2.3 Extension in Use Bit (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 B.2.4 Unnormalized Bit (U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 B.2.5 Negative Bit (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 B.2.6 Zero Bit (Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 B.2.7 Overflow Bit (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 B.2.8 Carry Bit (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7 B.3 Condition Code Summary by Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 B.3.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 B.3.2 Condition Code Calculation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8 B.3.3 Special Calculation Rules for Certain Instructions. . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.1 ASL and ASL.W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.2 ASLL.W and ASLL.L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.3 ASRAC and LSRAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.4 BFCHG, BFCLR, BFSET, BFTSTH, and BRSET . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.5 BFTSTL and BRCLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.6 BFSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14 B.3.3.7 IMPY.W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15 B.3.3.8 NORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15

Appendix C Glossary

Freescale Semiconductor

Table of Contents

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 1-5 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 Figure 3-25 DSP56800EX/DSP56800E Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 Immediate Addressing: 7-Bit Immediate Data to Address Register. . . . . . 3-37 Immediate Addressing: 5-Bit Immediate Data to Accumulator . 3-32 Address Register Indirect: Indexed by Offset N. . . . . . . . . . . . . . . . . . . . 2-5 DSC Chip Architecture with External Bus . . . . . . . . . . . . . . . 3-12 Dual Parallel Read . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Accessing a Byte with a Word Pointer . . 2-6 Core Block Diagram . . . . . . . . . . . 3-22 Address Register Indirect: No Update . . . . . . . . . . . . . . . . 3-35 Address Register Indirect: Indexed by 16-Bit Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 List of Figures xv Freescale Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Single Parallel Move. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 Address Register Indirect: Post-Update by Offset N . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Structure of Byte and Word Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Accessing a Word with a Word Pointer . . . . . . . . . . . . . . . . . . . . . . 1-4 Analog Signal Processing . . . . . 2-7 Core Programming Model . . . . . . . . . Y0) . . . . . 3-21 Accessing a Byte with a Byte Pointer. . . . 3-12 Data Alignment in Accumulators . . . . . . . . . . . . . . 3-29 Address Register Indirect: Post-Increment . . . . . . . . . . . . . . 1-7 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 Address Register Indirect: Indexed by 6-Bit Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Example of Chip Based on DSP56800EX Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Data Alignment in 24-bit AGU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Accessing a Long Word Using the SP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 Address Register Indirect: Indexed by 24-Bit Displacement . . . . . . . . . . . . 2-3 Dual Harvard Memory Architecture. . . . . . . . . 3-15 Data Alignment in 16-Bit AGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Supported Data Types in Data Registers (X0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Accessing a Long Word Using an Address Register . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Correct Storage of 32-Bit Value in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y1. . . . . . . . . . . . . . . . . . . . . . . 1-5 Digital Signal Processing . . . . . . . . . . . . . . . . 1-6 Mapping DSC Algorithms into Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 Address Register Indirect: Indexed by 3-Bit Displacement . . . . . . . 3-30 Address Register Indirect: Post-Decrement . . . . . . . . . . . . . . . . .

. . . . . . 5-16 Fractional Word Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .and 32-Bit Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Arithmetic Shifts on 32-Bit Long Words . . . . . . . . . . . . . . . . 3-39 Immediate Addressing: 16-Bit Immediate Data to AGU Register . . 5-36 Normalizing a Large Positive Value. . . 5-10 Reading the Accumulator Extension Registers (FF2) . . . . . . . . . . . . . . . . . . . . . . . 5-40 Convergent Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Absolute Addressing: 6-Bit Absolute Short Address . . . . . . . . . . . . . . . . . . . . . . 5-3 The 32-Bit Y Register—Composed of Y1 Concatenated with Y0. . . . . . . . . . . . . . . . . . . . . . . . . . . .W) . . 5-19 Integer Multiplication with Word-Sized Result (IMPY. . . . . 5-20 16. . . . . . . . . . . .Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 3-31 Figure 3-32 Figure 3-33 Figure 4-1 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 5-16 Figure 5-17 Figure 5-18 Figure 5-19 Figure 5-20 Figure 5-21 Figure 5-22 Figure 5-23 Figure 5-24 Figure 5-25 Figure 5-26 Figure 5-27 Figure 5-28 Figure 5-29 Figure 6-1 Immediate Addressing: 7-Bit Immediate Data to Data ALU Register . . . . . . . 5-33 32-Bit × 32-Bit –> 32-Bit Unsigned Integer Multiplication. . . . . . . . . . . . . . . . . . . . . 5-34 32-Bit × 32-Bit –> 64-Bit Signed Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 Immediate Addressing: 16-Bit Immediate Data to Data ALU Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Absolute Addressing: 24-Bit Absolute Address . . 3-45 Moving Data in the Register Files . . . . . 5-4 Different Components of an Accumulator (Using “FF” Notation) . . . . . . . . . . . . . . . . . 5-45 Two’s-Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Data ALU Block Diagram . . . . . . . . . . . . . . . 3-43 Absolute Addressing: 16-Bit Absolute Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 Double-Precision-Times-Double-Precision Signed Multiplication . 4-51 Data ALU Programming Model . . . . . . 5-20 Integer Multiplication with Long-Word-Sized Result (IMPY. . . . . 6-2 xvi DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Single-Precision-Times-Double-Precision Signed Multiplication . . . . . . . . . . . . 5-8 Writing the Accumulator by Portions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Writing the Accumulator as a Whole . . . 3-40 Immediate Addressing: 32-Bit Immediate Data . . . . 5-17 Adding a Word Fractional to a Long-Word Fractional . . . . . . . . . 5-25 Arithmetic Shifts on 16-Bit Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46 Address Generation Unit Block Diagram (DSP56800E Core). . . . . . . . . . . . . . . . . 5-35 Normalizing a Small Negative Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 32-Bit × 32-Bit –> 32-Bit Signed Integer Multiplication . . . . . . . . . . . . . . . . . . . . . . . 3-42 Absolute Addressing: 6-Bit I/O Short Address . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Comparison of Integer and Fractional Multiplication . . . . . . . . . . . . 5-18 Fractional Multiplication (MPY) . . . . . . . . . . . 5-11 Integer Word Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 Example of Saturation Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Writing the Accumulator Extension Registers (FF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .L). . . . . . . 5-16 Adding a Word Integer to a Long-Word Integer . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Trigger 2 Logic . . . . . . . . . . . . . . . . . . . . . 10-15 Interrupting After Completing the Fastest Fast Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . .B Instruction . . . . . . . . . . . . . . . . . . . . . . . 10-22 Interrupt Latency Calculation—Non-Interruptible Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Execution of the RTID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 Interrupting a Fast Interrupt Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 37-Location Circular Buffer . .Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 6-10 Figure 7-1 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 9-1 Figure 9-2 Figure 9-3 Figure 10-1 Figure 10-2 Figure 10-3 Figure 10-4 Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 10-9 Figure 10-10 Figure 10-11 Figure 10-12 Figure 10-13 Figure 11-1 Figure 11-2 Figure 11-3 Figure 11-4 Figure 11-5 Figure 11-6 Figure 11-7 Figure 11-8 Dual Parallel Read Instruction . . . . . . . . . . 10-10 Interrupting an Interrupt Handler (Nested Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 DSP56800E On-Chip System with Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Simple Five-Location Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Bit-Manipulation Unit Block Diagram . 9-7 DSP56800E Eight-Stage Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Example Stack Frame . . . 6-2 Address Generation Unit Programming Model . 11-10 Realtime Data Transfer Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D Instruction . . . . . . . . 11-3 JTAG/Enhanced OnCE Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Step Counter — Started upon Exiting Debug State with Breakpoint Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Step Counter — Started upon Exiting Debug State . . . . . . . . 10-19 Second Interrupt Case with 4 Cycles Executed in FRTID Delay Slots . . . . . . . . . . . . . . . . 11-13 Freescale Semiconductor List of Figures xvii . 6-31 Linear Addressing with a Modulo Modifier . . . . . 9-6 Control Flow in Fast Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . 6-4 Word vs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Fast Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . 10-24 Delay When Updating the CCPL . . . . . . . . . . . . . . . 6-12 Executing the MOVEU. . . 10-23 Interrupt Latency and the REP Instruction . . . . . . . . . . . . . . . 11-9 Trigger 1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Effects of the JSR Instruction on the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Program Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 10-17 Interruption by Level 3 Interrupt During FRTID Execution . . . . . . . . . . . . . . . . 9-5 Control Flow in Normal Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BP X:(R1+7). . . . . . . . . . . . . . . . . . . 11-5 Breakpoint Unit Block Diagram . . Byte Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 Interrupt Latency Calculation . . . . . . . . 8-17 Example Data-Memory Execution Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Executing the MOVE. . . . . . . . . .L X:(R3+2). . . . . . . . . . . . . . . . . 8-2 Program Controller Programming Model. . . . . . . . . 10-1 Standard Interrupt Processing . 6-17 Circular Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . 11-30 TAP Controller State Diagram . . . . . . . . . . . . . . . . . .B1. . . . . . . . . 11-15 Triggering the Step Counter with the Breakpoint Unit. . . . . . . . . . . . . . . . . 11-31 Example Instruction Encoding . . . . . . . . . 11-23 Capture Counter — 40-bit Configuration (Cascaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A X:(R1)+. . 11-19 Capture Counter — 16-bit Configuration (Non-Cascaded) . . . .Y1 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 Triggering the Step Counter with the Capture Counter . . . . . . . 11-29 Core JTAG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 Programmable Trace Buffer . . B-2 Internal AGU Alignment and Extension . .Figure 11-9 Figure 11-10 Figure 11-11 Figure 11-12 Figure 11-13 Figure 11-14 Figure 11-15 Figure 11-16 Figure 11-17 Figure A-1 Figure A-2 Figure B-1 Figure B-2 Breakpoint Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 JTAG Port Programming Model . . . . . . . A-329 Encoding for the MPY Y1. . . . . . . . . . . . . . . . . B-2 xviii DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . A-329 Internal Data ALU Alignment and Extension . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Looping Instructions . 3-26 Assembler Operator Syntax for Immediate Data Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Absolute Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Address Generation Unit (AGU) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Typical 16-Bit-Word Register Loads . . . 4-6 Logical Instructions . . . . . . . . . . . . . . . . . . . .List of Tables Table 2-1 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table 4-14 Table 4-15 Table 4-16 Table 4-17 Table 4-18 Table 4-19 Example for Chip I/O and On-Chip Peripheral Memory Map . . . . . . 3-26 Assembler Operator Syntax for Branch and Jump Addresses . . . . . . . . . . . . . . . . . . 4-9 Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Immediate Addressing Modes . . . . . . . . . . . . . . . . . . . . 4-8 Bitfield Instructions . . 3-3 Interpretation of 16-Bit Data Values . . . . . . . . . . . . . . . . . . . . . 4-9 Additional DSP56800EX Bitfield Instruction . . . . . . . . . . . . . . . . . . . . . . 3-23 Register-Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Aliases for Logical Instructions with Immediate Data . . . . . 2-4 Core Registers. . . . . . . . . . . . . . . . . . . . . . . . 4-11 Miscellaneous Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Arithmetic Instructions . . . . . . . . . . . . . . . . 4-7 AGU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Sample Instruction Summary Table . 4-13 Delayed Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . 4-2 Additional 32-Bit DSP56800EX Multiplication Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Notation for AGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 List of Tables xix Freescale Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Register Fields for General-Purpose Writes and Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Interpretation of 36-Bit Data Values . . . . . . . . . . . . . . . . . 3-24 Address-Register-Indirect Addressing Modes . . . . . . . . 4-12 Instructions with Alternate Syntax . . . 4-3 Shifting Instructions . . . . . . . . . . . . . . . . . . . . . 3-10 Useful Built-In Assembler Functions . . . . . . . . . 4-10 Program Control and Change-of-Flow Instructions . . . . . . . . . . 3-9 Suffixes for Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Memory Space Symbols . . . . . . . . . . . . 3-27 Multiplication Instructions . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Addressing Mode Arithmetic—Byte Pointers to Data Memory . . . . . . . . . . . . 6-6 Hardware Implementation of Addressing Mode Arithmetic— Word Pointers to Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 Memory-to-Memory Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Addressing Mode Arithmetic—Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Move Byte Instructions—Byte Pointers . . . . 4-43 Branch-on-Bit-Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Data Limiter Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Data ALU Multiply Instructions. . . . . . . . . . . . . . . . . . . . . . . 4-26 Immediate Move Instructions . . . . . . . . . . . . . . . . 4-41 Miscellaneous Data ALU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 AGU Address Arithmetic Instructions . . . . . . 4-29 Data ALU Extended-Precision Multiplication Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 Data ALU Logical Instructions. . . 6-23 Programming the M01 Register—Long-Word Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Conditional Register Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Data Types and Range of Values . . . . . . . . . . . . . 4-41 AGU Arithmetic and Shifting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Move Long Word Instructions . . . . . . . . . . . . . . . 4-20 Immediate Value Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 Move Word Instructions—Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 Change-of-Flow Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 Capabilities of the Address Pointer Registers. . . 6-25 Base Pointer and Offset/Update for DSP56800E Instructions . . . . . . . . . 4-46 Looping Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 Bit-Manipulation Instructions. . . . 4-23 Move Word Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Data ALU Shifting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 xx DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 Rounding Results for Different Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 Control Instructions . . . . . . . . . . . . . 4-48 Single Parallel Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Register-to-Register Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Move Byte Instructions—Word Pointers . . . . . . . . . . . . . . . . . . . . . .Table 4-20 Table 4-21 Table 4-22 Table 4-23 Table 4-24 Table 4-25 Table 4-26 Table 4-27 Table 4-28 Table 4-29 Table 4-30 Table 4-31 Table 4-32 Table 4-33 Table 4-34 Table 4-35 Table 4-36 Table 4-37 Table 4-38 Table 4-39 Table 4-40 Table 4-41 Table 4-42 Table 4-43 Table 4-44 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 6-1 Table 6-2 Table 6-3 Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Additional Register Sets for Move Instructions . . . . . . . . 4-49 Dual Parallel Read Instructions . . . . . . 4-50 Accessing the Accumulator Registers . . . . . . . . . . . . . . . . . . . . 5-39 MAC Unit Outputs with Saturation Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Programming the M01 Register—Byte and Word Accesses . . . . . . . . . . . . 4-30 Data ALU Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 AGU Write Dependency Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 OMR Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Breakpoint Unit Trigger — for 16-bit Capture Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Instruction Field Symbols . . 11-25 JTAG Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 FISR Bit Descriptions . . . . . . . . . . . A-6 Data ALU Register Operand Encodings. . . . . . . . . . . . 11-17 Breakpoint Unit Trigger — 16-bit Counter Available for Triggering . . . . . . . 11-23 Starting and Stopping Trace Buffer Capture . . . . . . 11-18 Possible Breakpoint Unit Actions. 10-29 AGU Pipeline With No Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Additional Register Fields for Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 Processing States. . . . . . A-332 Freescale Semiconductor List of Tables xxi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 SR Bit Descriptions . . . . 11-19 Starting and Stopping the Capture Counter — Non-Cascaded. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Interrupt Priority Level Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 Breakpoint Unit — Step Counter Operation. . . . . . . 9-3 Current Core Interrupt Priority Levels . . . . . . . 11-25 Possible Actions on Trace Buffer Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 Possible Capture Counter Actions — Non-Cascaded. . . . . 8-8 Interrupt Mask Bits Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Table 7-1 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 9-1 Table 9-2 Table 10-1 Table 10-2 Table 10-3 Table 10-4 Table 10-5 Table 10-6 Table 10-7 Table 11-1 Table 11-2 Table 11-3 Table 11-4 Table 11-5 Table 11-6 Table 11-7 Table 11-8 Table 11-9 Table 11-10 Table 11-11 Table 11-12 Table 11-13 Table 11-14 Table 11-15 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Operations Synthesized Using DSP56800E Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Opcode Encoding Fields . . . . . . . . . . . . . . . . . . . . . . 10-4 Execution of Data ALU Instructions in the Pipeline . . . . . . . . . . . . . . . . . . 9-3 Mapping Fundamental Operations to Pipeline Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 Data ALU Operand Dependency Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Step Counter Operation . . . . . . . . . . . . . . . . . 8-13 Hardware Stack Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 Notation used in Breakpoint Unit Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 First Part of Breakpoint Unit Trigger(s)— 16-bit Counter Available for Triggering . . . . . . . . . . . . . . . A-2 Address Generation Unit (AGU) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 Register Fields for General-Purpose Writes and Reads . . . . . 11-20 First Part of Breakpoint Unit Trigger— 16-bit Counter in Capture Mode . . . . . . . . . 11-22 Possible Capture Counter Actions — Non-Cascaded. . . . . . . A-330 Three-Operand Data ALU Instruction Register Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 Data ALU Pipeline with No Dependencies . . . . . . . . . . . . . . . . . . . . . . . A-3 Data ALU Registers . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . B-8 Condition Code Summary . . . . . . . . . . A-336 Encodings for Instructions with Different Load and Store Register Sets. . . . . . B-9 xxii DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . . . . . . . . . . . . . . . . . . . . .Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Table A-19 Table B-1 Table B-2 Table B-3 Register Op Codes for DALU Instructions with Parallel Moves . . . . . . . . . . . A-339 Bit-Manipulation Register Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-347 Condition Code Bit Descriptions . . . . . . . A-340 Size-Dependent Register Encodings for MOVE Instructions . . . . . . . . . . . . . . . . . . . . . . A-345 Condition Encoding for Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-346 Offset Values for iii Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-344 Addressing Mode Encodings . . . A-336 Register Encodings for MOVE Instructions . . . . . . . . . . . . . . B-4 Condition Code Summary Table Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-345 Condition Encoding for the Tcc Instruction . . A-342 Single Parallel Move Register Encoding . . . . . . . . . . . . . . . . A-344 Dual Parallel Read Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Reading an Integer Value from an Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Converting a 36-Bit Accumulator to a 16-Bit Value . . 3-14 Allocation of 2 Bytes Globally . . . . . . . 4-15 Valid Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Loading Accumulators with Different Data Types. . . . . . . . . . . . . . . . . . 5-12 Reading a Word from an Accumulator with Saturation . 3-11 Examples of Operands in Memory . . . . . . . . . . 3-17 Allocation of a Character String . . . . . . . . . . . . . . . . . . . 5-9 Reading the Contents of the C2 Register . . . . . 4-17 Invalid Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Examples of Single Parallel Moves . 3-28 Logical OR with a Data Memory Location . . . . . . . . . . . 5-13 Saving and Restoring an Accumulator—Long Accesses . . . . . . . . . . . . . 5-12 Reading a Long Value from an Accumulator with Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Unsigned Load of a Long Word to an Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Using the Register-Direct Addressing Mode . . . . . 4-50 X0 Register Used in Operation and Loaded in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unsigned Division with Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Code Fragment with Regular Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Loading an Accumulator with an Integer Word . . . . . . . Signed Division with Remainder . . . . . 5-4 Accumulator A Used in Operation and Stored in Parallel . . . . . . 5-12 Loading an Accumulator with a Long Integer . . . . . . . . . .List of Examples Example 3-1 Example 3-2 Example 3-3 Example 3-4 Example 3-5 Example 3-6 Example 3-7 Example 3-8 Example 3-9 Example 3-10 Example 4-1 Example 4-2 Example 4-3 Example 4-4 Example 4-5 Example 4-6 Example 5-1 Example 5-2 Example 5-3 Example 5-4 Example 5-5 Example 5-6 Example 5-7 Example 5-8 Example 5-9 Example 5-10 Example 5-11 Example 5-12 Example 5-13 Example 5-14 Example 5-15 Example 5-16 Demonstrating Source and Destination Operands . . . . . . . . . . . . 5-14 5-14 5-22 5-23 Freescale Semiconductor List of Examples xxiii . . . . . . . . . . . 3-28 Effects of Data Types on Address Displacements . . . . . . . . . . . . . . . . . . . . . . . Bit Manipulation on a DSP56800E Accumulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Code Fragment with Delayed Branch. . . . . . . . . . . . . . . . 3-13 Storing Accumulators with Different Data Types . . . . 5-13 Saving and Restoring an Accumulator—Word Accesses. 5-11 Writing a Value into the C2 Register . . . . . 3-28 Effects of Data Types on AGU Arithmetic . . . 3-9 Program Memory Accesses . . . . . . . . .

5-46 Example Code for Convergent Rounding. . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Adding “–2” to a Modulo Pointer. . . . . . . . . .Example 5-17 Example 5-18 Example 5-19 Example 5-20 Example 5-21 Example 5-22 Example 5-23 Example 5-24 Example 5-25 Example 5-26 Example 5-27 Example 5-28 Example 5-29 Example 5-30 Example 5-31 Example 5-32 Example 5-33 Example 6-1 Example 6-2 Example 6-3 Example 6-4 Example 6-5 Example 6-6 Example 6-7 Example 6-8 Example 6-9 Example 6-10 Example 6-11 Example 6-12 Example 7-1 Example 7-2 Example 7-3 Example 7-4 Example 7-5 Example 7-6 Example 7-7 Example 7-8 Signed DIvision Without Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Clearing Bits in an Operand . 6-28 Adding Positive Offset to a Modulo Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 Normalizing with a Shift Instruction . . . . . . . . . . . . . . . . .Offset Values Satisfying Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Using a Mask to Operate on Bits 7–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 Multiplying Signed 16-Bit Word with Signed 32-Bit Long . . . . . Bit-Manipulation Operations Using Complex Addressing Modes. . 5-29 64-Bit Subtraction. . . . 6-16 Invalid Use of the Modulo Addressing Mode . . . . . . . .BP and MOVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Accessing the Circular Buffer. . . . . . . . . . 5-34 Multiplying Two Signed Long Integers . . . . . . . . . . . . . . . . 6-11 Comparison of MOVE. . . . . . . . . . 6-28 Correct Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Branching on Bits in an Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Examples of Byte Masks in BRSET and BRCLR Instructions . . . . Logical Operations on Bytes Using Word Pointers . . .B Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 Normalizing with the NORM Instruction . Logical Operations on Bytes in Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Initializing the Circular Buffer . . . . . . . . . . . . . . . . . . 5-33 Multiplying Two Unsigned Long Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 Multiplying Two Signed Long Integers . . . . . . . . . . . . . . . . . . . 5-47 Accessing Bytes with the MOVE. . . . . . . . . . . . . . . . . . . . . . . . 5-40 Demonstrating the Data Limiter—Negative Saturation . . . . . . . 5-41 Demonstrating the MAC Output Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 Fractional Single-Precision Times Double-Precision—Both Signed . . . . . . . . . . 7-5 7-7 7-8 7-8 xxiv DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 6-31 Accessing the Circular Buffer with Post-Update by Three . . . . . . . . . . . . . 5-30 Multiplying Two Fractional Double-Precision Values. . . . . . . . . . . . . . . 7-3 Testing Bits in an Operand . . . . . . . . .B Instruction . . . . . . . . . . . . . . . . . . 5-42 Example Code for Two’s-Complement Rounding . . . . 6-11 Accessing Elements in a Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Multiplication of 2 Unsigned Words . . . . . . . 5-28 64-Bit Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 Demonstrating the Data Limiter—Positive Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Accessing Elements in an Array of Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 Addressing Mode Examples for Long Memory Accesses . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 Exiting Data-Memory Execution Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-Bit Target Address . . . . . . . . . . . . . . . 7-10 Pushing a Value on the Software Stack . . . . . . . . . . . . . . . . . . . . . . . . 10-29 MOVE Instructions That Introduce Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Immediate Exit from Hardware Loop. . . . . . . 8-25 Entering Data Memory Execution. . . . . . . . . . . . . . . . . . . . . . . . 8-23 Example of Nested Looping in Software . . . . . . . . . . . . . . . 8-19 DO Loop Special Case . . . . . . . . . . . . . . . . . . . . . . . 8-23 Entering Data Memory Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 Case Without AGU Pipeline Dependencies . . . . . . . 7-9 JR1SET and JR1CLR Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 Dependency with Load of LC and Start of Hardware Loop. . . . . . . . . . . . . . . . . 8-16 Repeat Loop Example. . . . . . . . . . . .Example 7-9 Example 7-10 Example 7-11 Example 8-1 Example 8-2 Example 8-3 Example 8-4 Example 8-5 Example 8-6 Example 8-7 Example 8-8 Example 8-9 Example 8-10 Example 8-11 Example 8-12 Example 8-13 Example 8-14 Example 8-15 Example 8-16 Example 9-1 Example 10-1 Example 10-2 Example 10-3 Example 10-4 Example 10-5 Example 10-6 Example 10-7 Example 10-8 Example 10-9 JRSET and JRCLR Operations. . . . . . . . . . . . . . . . . 21-Bit Target Address . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 Freescale Semiconductor List of Examples xxv . . 8-27 BRSET Non-Interruptible Sequence . . . . . . . . . . . . . . . . . . . . . 10-27 Pipeline Dependency with AGU Registers. . . . . . . . . . . . . . 9-11 Example Code to Demonstrate Pipeline Flow . . . . . . . . . . . 10-6 Data ALU Operand Dependencies . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Example of a REP Loop Nested Within a DO Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 Instructions with No Stalls . 8-26 Exiting Data-Memory Execution Mode. . . . . . . . . . . . . . . . . . . 19-Bit Target Address . . 8-21 Using the DOSLC Instruction. . . . . . . . . . . . . . 7-9 BR1SET and BR1CLR Operations. . . . . . . . . . 8-15 Subroutine Call with Passed Parameters . . 10-27 Case with No Data ALU Pipeline Dependencies . . . . . . . . . . . . . . . . . . 8-22 Example of Nested DO Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-Bit Target Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 DO Loop Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Demonstrating the Data ALU Execution Stages . . . . . . . 8-14 Pushing Multiple Values on the Software Stack . . . . . . . 8-14 Popping Values from the Software Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxvi DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

” This chapter presents the programming model. and presents the data types and addressing modes found on the core.” This chapter describes the data ALU architecture. It is intended to be used with the appropriate DSP56800E or DSP56800EX family member reference manual. It shows the registers and addressing modes available to each instruction as well as the number of execution cycles and program words required. Chapter 4. “Data Types and Addressing Modes.” The DSP56800E and DSP56800EX core architecture consists of the data arithmetic logic unit (ALU). This manual provides practical information to help the user accomplish the following: • • • • • Understand the operation and instruction set of the DSP56800E and DSP56800EX families Write code for DSC algorithms Write code for general control tasks Write code for communication routines Write code for data-manipulation algorithms Audience The information in this manual is intended to assist software engineers with developing application software for DSP56800E and DSP56800EX family devices. bit-manipulation unit. “Core Architecture Overview. The appropriate DSP56800E or DSP56800EX family member’s technical data sheet provides timing. Chapter 3. Freescale Semiconductor About This Book xxvii . peripheral definitions. Chapter 5. The contents of the chapters are as follows: Chapter 1. “Instruction Set Introduction. Organization Information in this manual is organized into chapters by topic. which describes the specific chip architecture. Chapter 2. “Introduction. and data types. and program controller. The chapter also provides an introduction to fractional and integer arithmetic on the core and discusses other topics such as unsigned and multi-precision arithmetic. introduces the MOVE instructions and their syntax. address generation unit (AGU). pinout. its programming model. This chapter describes each subsystem and the buses that interconnect the major components in the DSC core central processing module. and packaging descriptions.About This Book This manual describes the central processing unit of the DSP56800E and DSP56800EX in detail. “Data Arithmetic Logic Unit. and programming models.” This chapter presents register notation and summarizes the instruction set. It also provides the novice with a brief overview of digital signal processing.” This chapter introduces the DSP56800E and DSP56800EX core architecture and its application. methods for accessing the accumulators.

its use. Suggested Reading The following DSC-related books may aid an engineer who is new to the field of digital signal processing: Advanced Topics in Signal Processing. V. R. David J. F. wait. Schafer (Prentice-Hall: 1975) Digital Signal Processing: A System Design Approach.” This appendix presents a detailed description of condition code computation. and debug).” This chapter describes in detail the program controller architecture. Appendix C.W. Oppenheim and R. DeFatta. “Address Generation Unit. Manolakis (Macmillan: 1988) Multirate Digital Signal Processing. Chapter 9. Candy (McGraw-Hill: 1988) Theory and Application of Digital Signal Processing. E. its programming model. Davis (Prentice-Hall: 1988) Signal Processing Handbook. A.” This chapter introduces the different processing states of the core (normal. Hodgkiss (John Wiley and Sons: 1988) Discrete-Time Signal Processing. A.Chapter 6.” This chapter describes in detail the bit-manipulation unit’s architecture and capabilities.” This chapter describes the pipeline of the DSP56800E and DSP56800EX architecture. subroutines. and William S. Cadzow (Macmillan: 1987) Handbook of Digital Signal Processing. “Condition Code Calculation. Alan V. Rabiner and Bernard Gold (Prentice-Hall: 1975) xxviii DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . A. “Processing States. “JTAG and Enhanced On-Chip Emulation (Enhanced OnCE). electronics. reset. Oppenheim (Prentice-Hall: 1988) Applications of Digital Signal Processing. “Program Controller. Stearns and R. Oppenheim (Prentice-Hall: 1978) Digital Processing of Signals: Theory and Practice. “Bit-Manipulation Unit. V. its programming model. and communications terms. and hardware looping. Elliott (Academic Press: 1987) Introduction to Digital Signal Processing. Chen (Marcel Dekker: 1988) Signal Processing: The Modern Approach. Chapter 8. John G. Oppenheim and Ronald W. Schafer (Prentice-Hall: 1989) Foundations of Digital Signal Processing and Data Analysis.” This appendix presents a detailed description of each DSC core instruction. Maurice Bellanger (John Wiley and Sons: 1984) Digital Signal Processing. Crochiere and L. James V. Jae S. Appendix A. C. R. Chapter 7. S. Lim and Alan V. exception. Lucas. and its address modifiers. H. and its effect on the processor. Proakis and Dimitris G. J. Joseph G. “Instruction Pipeline. its addressing modes. Lawrence R. stop.” This chapter describes in detail the AGU architecture. D.” This chapter provides an overview of the JTAG test interface and the integrated emulation and debugging module (Enhanced OnCE™). Chapter 10. the hardware and software stacks. Chapter 11. “Glossary. “Instruction Set Details. Appendix B. Rabiner (Prentice-Hall: 1983) Signal Processing Algorithms.” The Glossary defines useful DSC.

Writing this bit has no effect. – 1: Will reset to a logic 1. they are not always contiguous. Memory addresses in the separate program and data memory spaces are differentiated by a one-letter prefix. Unless noted otherwise. – rw: Standard read/write bit. – —: The reset state depends on individual chip implementation. Possible values include: – 0: Will reset to a logic 0. Bits within a register are formatted AA[n:0] when more than one bit is involved in a description.X:PCC . Possible values include: – r: Read-only. For example. the SS0 pin is asserted low. Code examples are displayed in a monospaced font. SCK0 for SPI master . P:$0200 indicates a location in program memory. In graphic displays of registers. — TYPE: The bit’s type defines its behavior. The terms data memory and X memory are used interchangeably. Refer to the programming-model diagrams or to the programmer’s sheets to find the exact location of bits within a register. as follows: $FFFB is the X memory address for the interrupt priority register (IPR). When a bit is described as set. ~SS0 as PC3 for GPIO line 1 line 2 line 3 • • • Freescale Semiconductor About This Book xxix . its value is set to one. the bits are presented as if they are contiguous within a register.Conventions This document uses the following notational conventions: • • Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB). For example. Data memory addresses have an X: prefix. Configure: . MISO0. MOSI0. while program memory addresses have a P: prefix. • • • • A pin or signal that is asserted low (made active when pulled to ground) has a bar over its name. Hexadecimal values are preceded by a dollar sign ($). and the terms program memory and P memory are used interchangeably. the following definitions of notation apply: — Grey bit: An unimplemented bit that always reads as zero. — RESET: The reset value of the bit. its value is set to zero. When a bit is described as cleared. as follows: BFSET #$0007. M designates the value 220 and K designates the value 210. – w: Write-only. Only software (or a hardware reset) can change the bit’s value. Writing has no effect. – ?: The reset state is undefined. For purposes of description. However.

” xxx DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . and Abbreviations The following terms appear frequently in this manual: DSC JTAG Enhanced OnCE ALU AGU IP-BUS digital signal controller Joint Test Action Group Enhanced On-Chip Emulation arithmetic logic unit address generation unit Freescale standard on-chip peripheral interface bus A complete list of relevant terms and their definitions appears in Appendix C.Definitions. Acronyms. “Glossary.

powerful addressing modes. making it a logical upgrade for performance-hungry applications. low-power computing. and bit-manipulation unit allow traditional control tasks to be performed with ease. The DSC cores’ large register set. enables the efficient coding of DSC and digital filtering algorithms. and ease product development. 1.Chapter 1 Introduction The 32-bit DSP56800EX core represents the next step in the evolution of Freescale’s families of digital signal controllers (DSCs). without the complexity and limitations normally associated with DSCs. reducing latency bit-reverse addressing mode. with optional rounding and negation. flexible addressing modes. Compatibility—The DSP56800EX is source-code compatible with the Freescale DSP56800E family. combining DSC power and parallelism with MCU-like programming simplicity. DSP56800 and DSP56800E software can be run on the DSP56800EX by simply recompiling or reassembling it. including: • • • • 32-bit x 32-bit multiply and MAC operations all registers in the Address Generation Unit (AGU) have shadowed registers that effectively reduce the context save/restore time during exception processing. Assisting in the coding of general-purpose programs is support for a software stack. The architectural features that make these benefits possible include the following: • • High Performance—support for all digital signal processing applications. and byte. The veteran DSC programmer recognizes a powerful DSC instruction set in these DSC cores. Microcontroller programmers have access to a rich set of controller and general processing instructions. reduce application cost. A powerful multiply-accumulate (MAC) unit. word. and long-word data types. The DSP56800EX core has all DSP56800E core features and adds new enhancements. designed for both efficient digital signal processing and a variety of controller operations. Freescale Semiconductor Introduction 1-1 . Each core is a general-purpose central processing unit.1 Key Features The DSP56800EX and DSP56800E architecture provides a variety of features that enhance performance. The DSP56800EX core extends the capabilities of the DSP56800E core architecture. supporting Fast Fourier Transform (FFT) new bit manipulation instruction (BFSC) that integrates test-bitfield and a set/clear-bitfield operations into a single instruction Both the DSP56800EX and DSP56800E cores provide low-cost.

Powerful addressing modes and a range of data sizes are also provided. the following can be executed in a single instruction: — Fetching the next instruction — A 16-bit × 16-bit multiplication with 36-bit accumulation — Optional negation. programmers have full control over the processor’s operation. Instruction-set support for both fractional and integer data types provides the flexibility that is necessary for optimal algorithm implementation. Precision—The DSP56800EX and DSP56800E cores enable precise DSC calculations. The result is compact. fast 32-bit context saves and restores to and from the system stack. non-intrusive. Because of the high level of parallelism. Low Power Consumption—Implemented in CMOS. Developers can program in high-level languages such as C without being concerned about the pipeline. simplifying and speeding debugging tasks without having to halt the core. which can provide even more power savings.Introduction • Ease of Programming—The instruction mnemonics are designed to resemble the mnemonics of MCUs. Hardware Looping—Two types of zero-overhead hardware looping are provided. efficient code. Multi-Tasking Support—Implementing a real-time operating system or simple multi-tasking is much easier on the DSP56800EX and DSP56800E than on most DSCs. High Code Density—The base instruction word size for the DSC cores is only 16 bits. and peripheral operates independently and in parallel. atomic test-and-set operations. The instruction set emphasizes efficient control programming. and four prioritized software interrupts. simplifying the transition from programming traditional microprocessors. Rich Instruction Set—In addition to supporting instructions that support DSC algorithms. The architecture provides full support for a software stack. and speed-independent access to the internal state of the DSC core. rounding. In addition. and integer processing instructions. A flexible instruction set and programming model enable the efficient generation of compiled code. even as they benefit from the pipeline’s throughput of one instruction per cycle. By using Enhanced OnCE. the core architecture supports low-power modes. Real-Time Debugging—Freescale’s Enhanced On-Chip Emulation technology (Enhanced OnCE™) allows simple. which accounts for the largest portion of an application. including STOP and WAIT. Support for High-Level Languages—The C programming language is well suited to the DSC core architecture. Parallelism—Each on-chip execution unit. inexpensive. resulting in optimal code density. The power management implementation can shut off unused sections of logic. The majority of an application can be written in a high-level language without compromising DSC performance. enhancing performance and making loop-unrolling techniques unnecessary. the DSC cores inherently consume very little power. Intermediate values in the 36-bit accumulators can range over 216 dB. Enough precision for 96 dB of dynamic range is provided by 16-bit data paths. memory device. with multi-word instructions for more complex operations. the DSP56800EX and DSP56800E provide control. • • 1-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . and saturation of the result — Two 16-bit data moves — No-overhead hardware looping — Two address pointer updates • • • • • • • • Invisible Instruction Pipeline—The eight-stage instruction pipeline provides enhanced performance while remaining essentially invisible to the programmer. bit-manipulation.

1. The following diagram shows the core architecture. and advanced debugging and test features make the core an excellent solution for real-time. extensive parallelism. an Enhanced On-Chip Emulation module (Enhanced OnCE).2 Architectural Overview The DSP56800EX and DSP56800E cores each consist of a data arithmetic logic unit (ALU). an address generation unit (AGU). and associated buses. a program controller. embedded DSC and control tasks. on-chip program and data memories.Architectural Overview The DSP56800EX and DSP56800E’s efficient instruction set and bus structure. It is the perfect choice for wireless and wireline DSC applications. DSP56800EX/DSP56800E Core Block Diagram Freescale Semiconductor Introduction 1-3 . digital and industrial control. DSC Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) M01 N3 Looping Unit ALU1 ALU2 Instruction Decoder Interrupt Unit R0 R1 R2 R3 R4 R5 N SP XAB1 XAB2 PAB PDB CDBW CDBR XDB2 Program Memory Data Memory IP-BUS Interface BitManipulation Unit Y A2 B2 C2 D2 Enhanced OnCE™ A1 B1 C1 D1 Y1 Y0 X0 A0 B0 C0 D0 Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter External Bus Interface JTAG TAP MAC and ALU Figure 1-1. a bit-manipulation unit. or any other embedded-controller application that needs high-performance processing.

Bootstrap ROM for devices that execute code from RAM. Among the peripherals available on some devices that are based on the DSP56800EX and DSP56800E cores are the following: • • • • • • Phase-locked loop (PLL) module 16-bit timer module Computer operating properly (COP) and real-time timer module Synchronous serial interface (SSI) module Serial peripheral interface (SPI) module Programmable general-purpose I/O (GPIO) module 1. For chips with an external bus. Non-volatile memory (NVM) modules. Supported memories include: • • • • Program RAM and ROM modules. the core architecture supports an external address bus that is up to 24 bits wide and data bus widths of 8. 16. Data RAM and ROM modules. Example of Chip Based on DSP56800EX Core The DSC core architecture optionally supports chips with external bus interfaces.3 Example DSP56800EX Device Figure 1-2 shows an example device that is built around the DSP56800EX core. The Freescale IP-BUS architecture supports a variety of on-chip peripherals. IRQA RAM Flash IRQB DSP56800EX ADR 24 DATA 32 PLL External Bus Interface 32-Bit DSC Core COP & RealTime Timer Timers Serial JTAG GPIO AA0002 Figure 1-2. or 32 bits.Introduction Flexible memory support is one of the strengths of the DSC architecture. 1-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

Introduction to Digital Signal Processing 1. component aging. and transformation Figure 1-3 shows an example of analog signal processing. and component accuracy. The resulting circuit typically has low noise immunity. This application requires an analog-to-digital (A/D) converter and digital-to-analog (D/A) converter in addition to the DSC. Analog Signal Processing The equivalent circuit using a DSC is shown in Figure 1-4 on page 1-6. Since the ideal filter is impossible to design.= – ----.4 Introduction to Digital Signal Processing Digital signal processing (DSC) is the arithmetic processing of real-time signals that are sampled and digitized at regular intervals. and is difficult to modify. power-supply variation. Examples of DSC processing include the following: • • • • Filtering Convolution (mixing two signals) Correlation (comparing two signals) Rectification. the engineer must design the filter for acceptable response. amplification. The circuit in the illustration filters a signal from a sensor using an operational amplifier and then controls an actuator with the result. Freescale Semiconductor Introduction 1-5 . requires adjustments.--------------------------R i 1 + jωR f C f x(t) Frequency Characteristics Gain Ideal Filter Actual Filter Frequency fc f AA0003 Figure 1-3. considering variations in temperature. Analog Filter Rf x(t) Input from Sensor x(t) Ri + Cf y(t) y(t) Output to Actuator t Rf 1 y(t) --------.

Introduction Low-Pass Anti-Aliasing Filter Sampler And Analog-to-Digital Converter DSC Operation FIR Filter N–1 Digital-to-Analog Converter Reconstruction Low-Pass A/D x(t) x(n)  k=0 c(k) × (n – k) y(n) D/A y(t) Finite Impulse Response Analog In A Analog Out Gain Ideal Filter f fc Frequency A Gain Analog Filter f fc Frequency A Digital Filter Gain f Frequency fc AA0004 Figure 1-4. which eliminates out-of-band signals that can be aliased back into the pass band due to the sampling process. Moreover. the advantages of using the DSC include the following: • • • 1-6 Fewer components Stable. The DSC output is processed by a D/A converter and is low-pass filtered to remove the effects of digitizing. can easily be created using DSC. The signal is then sampled. adaptive filters. which are extremely difficult to implement using analog techniques. and sent to the DSC. The particular filter implemented by the DSC is strictly a matter of software. In summary. Digital Signal Processing Processing in this circuit begins with band limiting the input signal with an anti-alias filter. deterministic performance No filter adjustments DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . digitized with an A/D converter. The DSC can implement any filter that can be implemented using analog techniques.

many DSC benchmarks execute very efficiently for a single-multiplier architecture. are directed to a multiply operation. as needed. they are designed with a general-purpose DSC architecture to efficiently execute common DSC algorithms and controller code in minimal time. The two operands. Mapping DSC Algorithms into Hardware The multiply-accumulate (MAC) operation is the fundamental operation used in DSC. As Figure 1-5 shows.Introduction to Digital Signal Processing • • • • • • Wide range of applications Filters with sharper filtering characteristics High noise immunity Adaptive filters are easily implemented Self-test can be built in Better power-supply rejection The DSP56800EX and DSP56800E families do not consist of custom chips designed for a particular application. This process is built into the chip in that two separate data memory accesses are allowed to feed a single-cycle MAC. and two address updates in a single operation. the DSC can perform two memory moves. the key attributes of a DSC are as follows: • • • • Multiply-accumulate (MAC) operation Fetching up to two operands per instruction cycle for the MAC Flexibility in implementation through a powerful instruction set Input/output capability to move data in and out of the DSC FIR Filter N–1 A/D x(t)  x(n) k=0 c(k) × (n – k) y(n) D/A y(t) X Memory X Program Σ MAC AA0005 Figure 1-5. Figure 1-5 shows how the DSC architecture matches the shape of the MAC operation. The DSP56800EX and DSP56800E families of processors have a dual Harvard architecture that is optimized for MAC operations. The entire process must occur under program control to direct the correct operands to the multiplier and to save the accumulated result. Freescale Semiconductor Introduction 1-7 . and the result is summed. C() and X(). Since the memory and the MAC are independent. a multiply and an accumulate. As a result.

Introduction 1-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

2. More detailed information on the individual blocks within the core. appears in later chapters.1 Extending DSP56800E Architecture The DSP56800EX core architecture extends Freescale’s DSP56800E family architecture. supporting Fast Fourier Transform (FFT) new bit manipulation instruction (BFSC) that integrates test-bitfield and a set/clear-bitfield operations into a single instruction 2. It is source-code compatible with DSP56800 devices and adds the following new features: • • • • • • • • • • Byte and long data types. AGU. It is source-code compatible with DSP56800E devices and adds the following new features: • • • • 32-bit x 32-bit multiply and MAC operations with 32-bit and 64-bit results all registers in the Address Generation Unit (AGU) have shadowed registers that effectively reduce the context save/restore time during exception processing. It introduces the different blocks and data paths within the core and their functions. supplementing the DSP56800’s word data type 24-bit data memory address space 21-bit program memory address space Three additional 24-bit pointer registers (one of which can be used as an offset register) A secondary 16-bit offset register to further enhance the dual parallel data ALU instructions Two additional 36-bit accumulator registers Full-precision integer multiplication 32-bit logical and shifting operations Second read in dual read instruction can access off-chip memory Loop count (LC) register extended to 16 bits Freescale Semiconductor Core Architecture Overview 2-1 .2 Extending DSP56800 Architecture The DSP56800E and DSP56800EX core architecture extends Freescale’s DSP56800 family architecture. and program controller. reducing latency bit-reverse addressing mode.Chapter 2 Core Architecture Overview This chapter presents the core’s architecture and programming model as well as the overall system architecture for devices based on the DSP56800EX and DSP56800E cores. such as the data ALU.

Core Architecture Overview • • • • Full support for nested DO looping through additional loop address and count registers Loop address and hardware stack extended to 24 bits Three additional interrupt levels with a software interrupt for each level Enhanced On-Chip Emulation (Enhanced OnCE) with three debugging modes: — Non-intrusive real-time debugging — Minimally intrusive real-time debugging — Breakpoint and step mode (core is halted) 2. and their location in memory. their function. Registers for on-chip peripherals are mapped into a 64-location block of data memory.3 Core Programming Model The registers in the core that are considered part of the core programming model are shown in Figure 2-1. 2-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . An example for this block of memory is shown in Table 2-1 on page 2-4. Consult a specific device’s user’s manual for details on the peripherals that are implemented. the registers that are defined for them in this memory area.

SR) 15 0 OMR SR Modifier Registers 15 M01 0 0 Secondary Offset Register 15 0 N3 A1 B1 C1 D1 0 16 15 A0 B0 C0 D0 0 23 0 23 0 20 Figure 2-1. Core Programming Model Freescale Semiconductor Core Architecture Overview 2-3 .Core Programming Model Data Arithmetic Logic Unit (ALU) Data Registers 35 32 31 A B C D A2 B2 C2 D2 15 Y Y1 Y0 X0 Address Generation Unit (AGU) 23 Pointer Registers R0 R1 R2 R3 R4 R5 N SP Program Control Unit 20 Program Counter PC Loop Address LA LA2 Hardware Stack HWS0 HWS1 Fast Interrupt Return Address FIRA 15 0 Loop Counter LC LC2 0 Fast Interrupt Status Register 12 0 FISR 0 Operating Mode Register and Status Register (OMR.

(Available for Peripherals) (Available for Peripherals) (Available for Peripherals) (Available for Peripherals) NOTE: Peripherals can be located anywhere in data memory and are defined by the specific device’s user’s manual. . 2-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . X:$xxFFC3 X:$xxFFC2 X:$xxFFC1 X:$xxFFC0 (Reserved for DSC Core) (Reserved for DSC Core) (Reserved for DSC Core) (Reserved for DSC Core) (Reserved for Interrupt Priority) (Reserved for Interrupt Priority) (Reserved for Bus Control) (Reserved for Bus Control) (Reserved for DSC Core) (Reserved for DSC Core) (Reserved for DSC Core) (Reserved for DSC Core) (Available for Peripherals) (Available for Peripherals) (Available for Peripherals) (Available for Peripherals) .Core Architecture Overview Table 2-1. . Example for Chip I/O and On-Chip Peripheral Memory Map X:$xxFFFF X:$xxFFFE X:$xxFFFD X:$xxFFFC X:$xxFFFB X:$xxFFFA X:$xxFFF9 X:$xxFFF8 X:$xxFFF7 X:$xxFFF6 X:$xxFFF5 X:$xxFFF4 X:$xxFFF3 X:$xxFFF2 X:$xxFFF1 X:$xxFFF0 . . .

Usually the location of this memory block is chosen so that it does not overlap with RAM or ROM data memory. single-cycle move and bit-manipulation instructions. The data memory interface also supports two simultaneous read operations.Dual Harvard Memory Architecture 2. as shown in Figure 2-2. and bus control functions. A 64-word block of data memory allocated for memory-mapped IP-BUS peripheral registers can be located anywhere in data memory. The X:<<pp addressing mode (see Section 3.4 Dual Harvard Memory Architecture The DSC core has a dual Harvard architecture with separate program and data memory spaces. This architecture allows for simultaneous program and data memory accesses.6. 15 0 $FFFFFF 16M (32 Mbyte) 15 0 $1FFFFF 2M (4 Mbyte) Program Memory Space Data Memory Space $xxFFFF $xxFFC0 Optimized for IP-BUS Peripherals 64K (64K – 64) (Relocatable) Accessible with X:<<pp Addressing (Relocatable) $0 Interrupt Vectors 0 $0 0 Figure 2-2. The compiler has access only to the lower 16 Mbyte of data memory. as shown in Table 2-1 on page 2-4. Dual Harvard Memory Architecture The block of memory containing reset and interrupt vectors can be any size and can be located anywhere in program memory.2. Note that the top 12 locations in the peripheral register area ($xxFFF4 through $xxFFFF) are reserved for use by the core. “I/O Short Address: <<pp. Peripheral registers are memory mapped into a 64-location region in the data memory space. Freescale Semiconductor Core Architecture Overview 2-5 . interrupt priority functions. enabling single-word.” on page 3-43) provides efficient access to this memory range. enabling up to three simultaneous memory accesses.5.

and XDB2 uni-directional data buses to the corresponding bus interfaces on the peripheral devices.Core Architecture Overview 2.5 System Architecture and Peripheral Interface The DSC system architecture encompasses all the on-chip components. Regardless of the implementation. CDBW. Figure 2-3 shows the overall system architecture for a device with an external bus. including the core. The IP-BUS–interface standard connects the two data address buses and the CDBR. on-chip memory. The program memory buses are not connected to peripherals. DSC Chip Architecture with External Bus The complete architecture includes the following components: • • • • • • DSP56800EX or DSP56800E core On-chip program memory On-chip data memory On-chip peripherals Freescale IP-BUS peripheral interface External bus interface Some DSC devices might not implement an external bus interface. all peripherals communicate with the core via the IP-BUS interface. 2-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . and the buses that are necessary to connect them. Peripheral Peripheral Peripheral IP-BUS Program Memory PAB PDB XAB1 DSC Core CDBR CDBW XAB2 XDB2 Data Memory IP-BUS Interface External Address External Data External Bus Interface Figure 2-3. peripherals.

System Architecture and Peripheral Interface 2. and for the program controller to prefetch the next instruction. There is also an independent bit-manipulation unit. Freescale Semiconductor Core Architecture Overview 2-7 . The program controller. for the AGU to generate up to two addresses. significantly decreasing the execution time for each instruction.1 Core Block Diagram The DSC core is composed of several independent functional units. allowing them to operate independently and in parallel. See Figure 2-4. which increases throughput. Core Block Diagram Instruction execution is pipelined to take advantage of the parallel units. which enables efficient bit-manipulation operations. Each functional unit interfaces with the other units. and the memory-mapped peripherals over the core’s internal address and data buses. all within a single execution cycle. address generation unit (AGU). memory. it is possible for the data ALU to perform a multiplication operation. For example. and data arithmetic logic unit (ALU) contain their own register sets and control logic.5. DSC Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) M01 N3 Looping Unit ALU1 ALU2 Instruction Decoder Interrupt Unit R0 R1 R2 R3 R4 R5 N SP XAB1 XAB2 PAB PDB CDBW CDBR XDB2 Program Memory Data Memory IP-BUS Interface BitManipulation Unit Y A2 B2 C2 D2 Enhanced OnCE™ A1 B1 C1 D1 Y1 Y0 X0 A0 B0 C0 D0 Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter External Bus Interface JTAG TAP MAC and ALU Figure 2-4.

Instruction word fetches occur over the PDB. This bus structure supports up to three simultaneous 16-bit transfers. The program address bus is 21 bits wide and is used to address (16-bit) words in program memory. and the secondary data address bus (XAB2). All three buses address on-chip memory. the primary data address bus (XAB1). They can also address off-chip memory on devices that contain an external bus interface unit.5.5. word. Any one of the following can occur in a single clock cycle: • • • • • One instruction fetch One read from data memory One write to data memory Two reads from data memory One instruction fetch and one read from data memory 2-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 2. 2. All other data transfers to core blocks occur using the CDBR and CDBW buses. and long data types.2 Address Buses The core contains three address buses: the program memory address bus (PAB). Peripheral transfers occur through the IP-BUS interface. The XAB2 bus is limited to (16-bit) word accesses.Core Architecture Overview The major components of the core are the following: • • • • • • • Address buses Data buses Data arithmetic logic unit (ALU) Address generation unit (AGU) Program controller Bit-manipulation unit Enhanced OnCE debugging module The following sections describe these components. The XAB1 bus can address byte. The two 24-bit data address buses allow for two simultaneous read accesses to data (X) memory. When two simultaneous memory reads are performed.3 Data Buses Data transfers inside the chip occur over the following buses: • Two uni-directional 32-bit buses: — Core data bus for reads (CDBR) — Core data bus for writes (CDBW) • Two uni-directional 16-bit buses: — Secondary X data bus (XDB2) — Program data bus (PDB) • IP-BUS interface Data transfers between the data ALU and data memory use the CDBR and CDBW when a single memory read or write is performed. the transfers use the CDBR and XDB2 buses.

C.5. minimizing address-calculation overhead. and one for the secondary data address bus (XAB2). and Y1) Four 36-bit accumulator registers (A. Division and normalization operations are provided by iteration instructions. The AGU operates independently of the other core units.5.4 Data Arithmetic Logic Unit (ALU) The data arithmetic logic unit (ALU) performs all of the arithmetic. in immediate instruction data. or 36-bit results. and logical operations. The results of data ALU operations are stored either in one of the data ALU registers or directly in memory.System Architecture and Peripheral Interface • • One instruction fetch and one write to data memory One instruction fetch and two reads from data memory An instruction fetch will take place on every clock cycle. shifting. allowing up to two 24-bit addresses to be generated every instruction cycle: one for either the primary data address bus (XAB1) or the program address bus (PAB). subtraction. The AGU consists of the following registers and functional units: • Seven 24-bit address registers (R0–R5 and N) Freescale Semiconductor Core Architecture Overview 2-9 . 2. although it is possible for data memory accesses to be performed without an instruction fetch. B. It can access 221 (2M) words on the PAB. The instruction set also supports 8-bit results for some arithmetic operations.5. or in the data ALU registers. addition. or 36 bits in size and can be located in memory. The XAB1 bus can address byte. The AGU can directly address 224 (16M) words on the XAB1 and XAB2 buses. It contains two address ALUs. Arithmetic operations and shifts can have 16-.5 Address Generation Unit (AGU) The address generation unit (AGU) performs all of the calculations of effective addresses for data operands in memory. “Data Arithmetic Logic Unit. the data ALU can perform multiplication. logical. The PAB and XAB2 buses can only address words in memory.” contains a detailed description of the data ALU. Logical operations are performed on 16. and shifting operations on data operands. 32. Data ALU source operands can be 8. Chapter 5. Such accesses typically occur when a hardware loop is executed and the repeated instruction is only fetched on the first loop iteration. All operations are performed using two’s-complement fractional or integer arithmetic. and D) One multiply-accumulator (MAC) unit A single-bit accumulator shifter One arithmetic and logical multi-bit shifter One MAC output limiter One data limiter All in a single instruction cycle.or 32-bit operands and yield results of the same size. and long data operands. The data ALU contains the following components: • • • • • • • Three 16-bit data registers (X0. The address ALU can perform both linear and modulo address arithmetic. Signed and unsigned multi-precision arithmetic is also supported. 32-. 2. “Hardware Looping. See Section 8.” on page 8-18 for more information on hardware loops. 16. Y0. word. multiply-accumulation (with positive or negative accumulation).

The loop address register (LA) and loop count register (LC) work in conjunction with the hardware stack to support no-overhead hardware looping. See Chapter 6. such as in the data ALU. 2-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . All of these registers can provide an address for the XAB1 and PAB address buses. N3. interrupt processing. and hardware looping. The modifier register. Actual instruction execution takes place in the other core units. and M01) on the DSP56800EX core A 24-bit dedicated stack pointer register (SP) Two offset registers (N and N3) A 16-bit modifier register (M01) A 24-bit adder unit A 24-bit modulo arithmetic unit Each of the address registers. selects between linear and modulo address arithmetic. The hardware stack is an internal last-in-first-out (LIFO) buffer that consists of two 24-bit words and that stores the address of the first instruction of a hardware DO loop. is used only for offset or update values. The N offset register can be used either as a general-purpose address register or as an offset or update value for the addressing modes that support those values. and M01) on the DSP56800E core. can contain either data or an address. N3. N. hardware interlocking. R1. it can subsequently be altered under program control. R0–R5 and N. M01. 2. AGU.Core Architecture Overview • • • • • • Four shadow registers (for R0. or nine shadow registers (for all Rn. The initial operating mode is typically latched on reset from an external source. addresses on the XAB2 bus are provided by the R3 register. The program controller contains the following: • • • • • An instruction latch and decoder The hardware looping control unit Interrupt control logic A program counter (PC) Two special registers for fast interrupts: — Fast interrupt return address register (FIRA) — Fast interrupt status register (FISR) • Seven user-accessible status and control registers: — Two-level-deep hardware stack — Loop address register (LA) — Loop address register 2 (LA2) — Loop count register (LC) — Loop count register 2 (LC2) — Status register (SR) — Operating mode register (OMR) The operating mode register (OMR) is a programmable register that controls the operation of the core.6 Program Controller and Hardware Looping Unit The program controller is responsible for instruction fetching and decoding.5. or bit-manipulation unit. including the memory-map configuration.” for a complete discussion of the AGU. The second 16-bit offset register. “Address Generation Unit. N.

Refer to Chapter 11. clearing. Freescale Semiconductor Core Architecture Overview 2-11 . This process allows for one hardware DO loop to be nested inside another. setting. and long data transfers occur on the CDBR and CDBW buses.7 Bit-Manipulation Unit The bit-manipulation unit performs bitfield operations on data memory words. Typical blocks include those outlined in the following subsections. The bit-manipulation unit can also test bytes for branch-on-bitfield instructions. the value is popped from the hardware stack. and registers within the DSC core. The size of the table is determined by the number of peripherals on the device and by the requirements of the particular application. or inverting individual or multiple bits within a 16-bit word. 2.” 2.8 Enhanced On-Chip Emulation (Enhanced OnCE) Unit The Enhanced On-Chip Emulation (Enhanced OnCE) unit provides a non-intrusive debugging environment.Blocks Outside the Core When the execution of the DO instruction begins a new hardware loop. When a loop finishes normally or an ENDDO instruction is encountered. Addresses in data memory are selected on the XAB1 and XAB2 buses.” For more information on hardware looping.6. See Chapter 7. word. “Program Controller. 2.1 Program Memory Program memory (RAM and/or flash memory) can be provided on-chip with the DSC architecture.2 Data Memory On-chip data memory (RAM or flash memory) can be implemented on a DSC device. The PAB bus is used to select program memory addresses. It is capable of testing.” for an overview of the Enhanced OnCE unit’s capabilities.” for a detailed description of the bitfield unit. The program controller is described in more detail in Chapter 8.6 Blocks Outside the Core Devices based on the DSC core contain several additional memory and peripheral blocks. A second 16-bit read operation can be performed in parallel on the XDB2 bus. Information on interrupt processing is contained in Chapter 9. Writes of 16-bit data to program memory are supported over the CDBW bus. with a maximum of 221 (2M) addressable locations. “Hardware Looping.5.5. Byte. 2. “Processing States. see Section 8.5. The interrupt and reset vector table can be any size and located anywhere in program memory. instruction fetches are performed over the PDB. It can also be used to set breakpoints in program or data memory and step or trace instruction execution.” on page 8-18. It is capable of examining and changing core or peripheral registers and memory values. “Bit-Manipulation Unit. peripheral registers. These blocks provide the functionality that is necessary for a complete working system on a chip. the address of the first instruction in the loop is pushed onto the hardware stack.6. 2. “JTAG and Enhanced On-Chip Emulation (Enhanced OnCE). Program memory can be expanded off-chip.

and bus control configuration registers.6. allowing access to external data and program memory. single cycle instructions. The DSC architecture provides a bootstrapping mode. The instruction set optimizes access to the peripheral registers with a special peripheral addressing mode that makes access to a 64-location peripheral address space more efficient. see Section 3.4 External Bus Interface An external bus interface extends the data and address buses off the chip. CDBW. Like the peripheral addressing mode. or other peripherals. The top 12 locations of the peripheral register address space are reserved by the system architecture for the core.1. Data memory can be expanded off-chip. and CDBR. allowing for a wide variety of external devices. All three sets of buses (PAB and PDB. XAB1. or any number of other peripherals. A special addressing mode also exists for the first 64 locations in data memory. MPUs in master/slave system configurations. The operating mode register can then be reprogrammed to fetch instructions from RAM. I/O devices.Core Architecture Overview Peripheral registers are memory mapped into the data memory space. Refer to the specific device’s user’s manual for information on implementing the external bus interface. The bootstrap ROM is used to load the application into RAM on reset.” on page 3-42. with a maximum of 224 (16M) addressable locations. For more information on these and other addressing modes used to access data memory. other DSCs. “Absolute Short Address: aa. 2. Although the peripheral register address range is typically from $00FFC0 to $00FFFF.6. interrupt priority.3 Bootstrap Memory A program bootstrap ROM is typically provided for devices that execute programs from on-chip RAM instead of ROM.6.5. these locations can be accessed using single word. The external-bus-interface timing is programmable. individual DSC devices may locate it anywhere in the data memory address space. 2. and XAB2 and XDB2) can be extended to access external devices. See the specific device’s user’s manual for information on bootstrapping mode. which fetches instructions from ROM and configures the RAM as read-only. These devices can include slow memory devices. 2-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

1. Registers in the data ALU are used for operations within that block. as are instructions in which a memory access can occur in parallel with an arithmetic operation. “Data ALU Overview and Architecture. and control.” on page 8-1. More information on these registers can be found in Section 5. More information on these registers can be found in Section 8.Chapter 3 Data Types and Addressing Modes The core contains a large register set and a variety of data types. such as arithmetic operations. Registers in the address generation unit (AGU) are used as pointers and for operations within that block. Registers in the program control unit are used for instruction fetching. word. “AGU Architecture. hardware looping. The programming model is divided into three major blocks in the DSC core. status.1. interrupt handling.” on page 5-2. 3.1 Core Programming Model The registers in the DSC core programming model are shown in Figure 3-1 on page 3-2.1. A powerful set of addressing modes also improves execution speed and reduces code size. enabling the efficient implementation of digital signal processing and general-purpose control algorithms. such as computations of effective addresses. “Program Controller Architecture. Byte. and long memory accesses are supported. More information on these registers can be found in Section 6. Freescale Semiconductor Data Types and Addressing Modes 3-1 .” on page 6-1.

Data Types and Addressing Modes Data Arithmetic Logic Unit (ALU) Data Registers 35 32 31 A B C D A2 B2 C2 D2 15 Y Y1 Y0 X0 Address Generation Unit (AGU) 23 Pointer Registers R0 R1 R2 R3 R4 R5 N SP Program Control Unit 20 Program Counter PC Loop Address LA LA2 Hardware Stack HWS0 HWS1 Fast Interrupt Return Address FIRA 15 0 Loop Counter LC LC2 0 Fast Interrupt Status Register 12 0 FISR 0 Operating Mode Register and Status Register (OMR. SR) 15 0 OMR SR Modifier Registers 15 M01 0 0 Secondary Offset Register 15 0 N3 A1 B1 C1 D1 0 16 15 A0 B0 C0 D0 0 23 0 23 0 20 Figure 3-1. 3-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Core Programming Model Table 3-1 on page 3-3 contains summary descriptions of all the registers in the core.

containing concatenated registers: A1:A0. Accumulator most significant product (MSP) register—Bits 31 to 16 of an accumulator. Accumulator—Contains three concatenated registers: A2:A1:A0. Accumulator—Contains three concatenated registers: B2:B1:B0. Core Registers Unit Data ALU Name Y1 Y0 Y Size (Bits) 16 16 32 Description Data register (upper 16 bits of 32-bit Y register). X0 A2 A1 16 4 16 A0 16 A10 32 A B2 B1 36 4 16 B0 16 B10 32 B C2 C1 36 4 16 C0 16 Freescale Semiconductor Data Types and Addressing Modes 3-3 . Data register. One long register containing two concatenated 16-bit registers. This register is pushed to the stack when a fast interrupt is processed. containing concatenated registers: B1:B0.Core Programming Model Table 3-1. Accumulator long portion—Bits 31 to 0 of an accumulator. Y1:Y0. Accumulator least significant product (LSP) register—Bits 15 to 0 of an accumulator. Accumulator extension register—Bits 35 to 32 of an accumulator. Accumulator extension register—Bits 35 to 32 of an accumulator. Accumulator least significant product (LSP) register—Bits 15 to 0 of an accumulator. Data register (lower 16 bits of 32-bit Y register). Accumulator extension register—Bits 35 to 32 of an accumulator. Accumulator least significant product (LSP) register—Bits 15 to 0 of an accumulator. Accumulator most significant product (MSP) register—Bits 31 to 16 of an accumulator. Accumulator most significant product (MSP) register—Bits 31 to 16 of an accumulator. Accumulator long portion—Bits 31 to 0 of an accumulator.

Accumulator long portion—Bits 31 to 0 of an accumulator. this register is also shadowed for fast interrupt processing. On the DSP56800EX core. this register is also shadowed for fast interrupt processing. This register is also shadowed for fast interrupt processing. Accumulator—Contains three concatenated registers: D2:D1:D0. Accumulator extension register—Bits 35 to 32 of an accumulator. Accumulator—Contains three concatenated registers: C2:C1:C0. Address register—On the DSP56800EX core. this register is also shadowed for fast interrupt processing. Accumulator most significant product (MSP) register—Bits 31 to 16 of an accumulator. this register is also shadowed for fast interrupt processing. containing concatenated registers: C1:C0. Stack pointer. containing concatenated registers: D1:D0. Accumulator least significant product (LSP) register—Bits 15 to 0 of an accumulator. may also be used as a pointer or index—This register is also shadowed for fast interrupt processing. Second read offset register—Sign extended to 24 bits and used as an offset in updating the R3 pointer in dual read instructions. Address register—On the DSP56800EX core. Modifier register—Used for enabling modulo arithmetic on the R0 and R1 address registers. Address register—This register is also shadowed for fast interrupt processing. Address register—This register is also shadowed for fast interrupt processing.Data Types and Addressing Modes Table 3-1. Offset register. Address register—On the DSP56800EX core. this register is also shadowed for fast interrupt processing. C D2 D1 36 4 16 D0 16 D10 32 D AGU R0 R1 R2 36 24 24 24 R3 24 R4 24 R5 24 N 24 SP N3 24 16 M01 16 3-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Address register—On the DSP56800EX core. Core Registers (Continued) Unit Data ALU Name C10 Size (Bits) 32 Description Accumulator long portion—Bits 31 to 0 of an accumulator.

LA 24 LA2 HWS 24 24 FIRA 21 FISR 13 OMR SR 16 16 LC LC2 16 16 3. and the 5 MSBs of the program counter register. Operating mode register—Sets up modes for the core. For integer values. Loop address 2—Saves loop address for outer loop. Fast interrupt status register—Saves a copy of the condition code register.2 Data Types The DSC architecture supports byte (8-bit). and the hardware looping status upon entering a level 2 fast interrupt service routine. the stack alignment state. Fast interrupt return address—Saves a 21-bit copy of the return address upon entering a level 2 fast interrupt service routine. long-word. Loop counter 2—Saves loop count for outer loop. and operand alignment for different fractional and integer representations. the same instruction can operate on both types of data. It also supports word. Status register—Contains status. The interpretation of a data value (fractional or integer) is determined by the instruction that uses it. In some cases. the decimal is always located immediately to the right of the value’s least significant bit. control. Table 3-2 on page 3-7 shows the location of the decimal point (binary point). For fractional arithmetic. Loop counter—Contains loop count when hardware looping. Freescale Semiconductor Data Types and Addressing Modes 3-5 . and accumulator (36-bit) fractional data types. bit weightings. different instructions are used for processing fractional numbers and integer numbers. is performed with the MPY instruction for fractional values and with IMPY.Data Types Table 3-1. for example.L for integer values. with identical results. The following subsections describe the data types and their interpretation. Loop address—Contains address of the last instruction word in a hardware DO loop. Hardware stack—Provides access to the hardware stack as a two-location LIFO buffer. Multiplication. Fractional and integer representations differ in the location of the decimal (or binary) point. word (16-bit). In others. Core Registers (Continued) Unit Program Controller Name PC Size (Bits) 21 Description Program counter—Composed of a dedicated 16-bit register (bits 15-0 of the program counter) as well as 5 bits stored in the upper byte of the status register. the decimal (or binary) point is always located immediately to the right of the MSP’s most significant bit. and long-word (32-bit) integer data types.

whose internal representation is $8000 (word) or $80000000 (long word). and the most positive.0 – 2–31). the N-bit operand is represented using the N. and the most negative. 3.1. signed long word is –2. and longs. 16-bit.647 ($7FFF_FFFF). The most positive. words.295 ($FFFF_FFFF). the N bit operand is represented using the 1. regardless of size.0 – 2–[N–1] This data format is available for words and long words.3 Signed Fractional In this format.767 ($7FFF).967.294. unsigned integer is 65. Signed fractional numbers lie in the following range: –1. The most negative. words.1.648 ($8000_0000). 3-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .2. 3.[N–1] format (1 sign bit. In this format. Fractional data types allow for powerful numeric and digital-signal-processing algorithms to be implemented.0.Data Types and Addressing Modes 3. 3.1 Signed Integer This format is used for processing data as integers. This data format is available for bytes. they are familiar to microprocessor and microcontroller programmers.483.2. Signed integer numbers lie in the following range: –2[N–1] ≤ SI ≤ [2[N–1] – 1] This data format is available for bytes. For both word and long-word signed fractions.2.535 ($FFFF). and the most positive signed long word is 2. The most positive word is $7FFF (1.0 ≤ SF ≤ +1. N–1 fractional bits).0 – 2–15). the most negative number that can be represented is –1.2 Unsigned Integer Unsigned integer numbers are positive only.483.147.0 format (N integer bits). The smallest unsigned integer number is zero ($0000). and the most positive long word is $7FFF_FFFF (1. signed word that can be represented is –32. 32-bit.1 Data Formats The DSC core supports four types of two’s-complement data formats: • • • • Signed integer Unsigned integer Signed fractional Unsigned fractional Signed and unsigned integer data types are useful for general-purpose computing.2. unsigned integer is 4. and long words.768 ($8000).1. Unsigned integer numbers lie in the following range: 0 ≤ UI ≤ [2N – 1] The binary word is interpreted as having a binary point immediately to the right of the integer’s least significant bit. The most positive signed word is 32. and they have nearly twice the magnitude of a signed number of the same size.147.

Table 3-2 shows how a 16-bit value can be interpreted as either fractional or integer. 1100 0000 0000 0000. 1001 0000 0000 0000.99997 0.0 – 2–[N–1] The binary word is interpreted as having a binary point after the MSB.0 ≤ UF ≤ 2.110 0000 0000 0000 1.0 –0. 3.875 –1.010 0000 0000 0000 0.001 0000 0000 0000 1.2.100 0000 0000 0000 0. or {1.000 0000 0000 0000 Fraction Decimal 0. Decimal 32767 28672 16384 8192 4096 0 –16384 –8192 –4096 –28672 –32768 Binary 0.0 The relationship between the integer interpretation of a 16-bit value and the corresponding fractional interpretation is: Fractional Value = Integer Value / (215) There is a similar relationship between 32-bit integers and fractional values: Fractional Value = Integer Value / (231) Table 3-3 on page 3-8 shows how a 36-bit value can be interpreted as either an integer or fractional value. 1000 0000 0000 0000. unsigned number is $FFFF. 0001 0000 0000 0000.000 0000 0000 0000 1. 0100 0000 0000 0000.2. Interpretation of 16-Bit Data Values Hexadecimal Representation $7FFF $7000 $4000 $2000 $1000 $0000 $C000 $E000 $F000 $9000 $8000 Integer Binary 0111 1111 1111 1111.111 1111 1111 1111 0. 1111 0000 0000 0000. Unsigned fractional numbers lie in the following range: 0. depending on the location of the binary point.2 Understanding Fractional and Integer Data Data in a memory location or register can be interpreted as fractional or integer. 0111 0000 0000 0000. 16-bit.4 Unsigned Fractional Unsigned fractional numbers may be thought of as positive only.0 – 2–[N–1])} = 1. Freescale Semiconductor Data Types and Addressing Modes 3-7 . and they have nearly twice the magnitude of a signed number with the same number of bits. 0000 0000 0000 0000.25 –0.100 0000 0000 0000 1.25 0. Table 3-2.Data Types 3. This data format is available for words and longs.875 0.111 0000 0000 0000 0. depending on the location of the binary point.5 0. 0010 0000 0000 0000.5 –0.001 0000 0000 0000 0. depending on a program’s needs.125 –0.125 0.1.99997.111 0000 0000 0000 1. The smallest unsigned fractional number is zero ($0000). 1110 0000 0000 0000.0 + (1. The most positive.

and decreases the power consumption and processing power that are required to perform a given task. and long-word memory accesses. word. 3-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .0 $2 0000 0000 $0 8000 0000 $0 4000 0000 $0 2000 0000 $0 0000 0000 $F E000 0000 $F C000 0000 $F 8000 0000 $E 0000 0000 3. decreases program code size. Byte. are supported. on both signed and unsigned data.0 –4. 3.3 Memory Access Overview The core implements a powerful set of memory-access operations that eases the task of programming the CPU.0 –0.25 –0. Examples include the following types of instructions: • • • Move instructions that access data or program memory Arithmetic or bit-manipulation instructions where one operand is located in data memory Parallel move instructions that perform an operation and move data to or from memory simultaneously Each of these memory accesses can be performed both on different sizes of data and with a number of different addressing modes.0 1.5 0. Interpretation of 36-Bit Data Values Decimal Representation Hexadecimal Representation 36-Bit Integer in Entire Accumulator 8589934592 2147483648 1073741824 536870912 0 –536870912 –1073741824 –2147483648 –8589934592 16-Bit Integer in MSP of Accumulator (Overflows) (Overflows) 16384 8192 0 –8192 –16384 –32768 (Overflows) Fraction 4. multiple data sizes. The provided addressing modes make it easy to access memory quickly and efficiently.0 0. Memory is accessed in a variety of ways.25 0.5 –1. Understanding the syntax for each of these options is essential to understanding and taking advantage of this flexibility.3. and a variety of addressing modes.Data Types and Addressing Modes Table 3-3. improves efficiency.1 Move Instruction Syntax The core supports memory moves to and from both data and program memory.

specify all addresses with one of these prefixes. R3 is the destination operand 3. Instructions that do not have this requirement include jump and branch instructions. “Memory Access and Pointers. Demonstrating Source and Destination Operands MOVE.3. Table 3-4. Table 3-4 shows the address space prefixes and their use.L” suffix—indicates long memory accesses “.2 Memory Space Syntax Each instruction that accesses memory must specify the particular memory address space (data or program) that is being referenced. Freescale Semiconductor Data Types and Addressing Modes 3-9 . as shown in Example 3-1.1.W” suffix—indicates word memory accesses “.DST. For unsigned register loads from memory. 3.1 Signed and Unsigned Moves The core provides separate move instructions to ensure that the destination register is zero extended or sign extended.3.Memory Access Overview 3. Addresses in memory should be prefixed with either X: to indicate the data memory space or with P: to indicate the program memory space.1 Ordering Source and Destination The syntax and sequence for all move instructions on the core are as follows: SRC.3.5. with no spaces either before or after the comma.BP” suffix—indicates byte memory accesses The difference between the two byte accesses is explained in Section 3.3.” 3. X0 is the source operand .B” suffix—indicates byte memory accesses “. The source and destination are separated by a comma.R3 . using an arithmetic instruction that has a parameter in data memory. Unsigned moves are important only when a register is being written and are not required when a register is being read.3. Example 3-1.W X0.2.1.2 Instructions That Access Data Memory Instructions access data memory in one of three ways: using a MOVE instruction with a parameter that refers to data memory. or using a bitfield manipulation instruction. whose target addresses always access program memory.1. as appropriate. Memory Space Symbols Symbol P: X: Examples P:(R2)+ X:(R0) X:$C000 Description Program memory access Data memory access To avoid confusion. the letter “U” immediately follows the “MOVE” portion of the instruction. 3.3 Specifying Data Size The size of data accessed from memory is indicated by a suffix: • • • • “.

Table 3-6 shows how MOVE instructions are typically used to load registers with 16-bit data.B X:(R0).W U.X0 MOVEU. Use the MOVEU. Using this instruction ensures that the word value is zero extended to the full register width.BP X:(R0). and SR Description Signed words loaded to data ALU registers Unsigned words loaded to AGU pointer registers Unsigned words loaded to other control registers The MOVE.BP U. 3.BP MOVE.A MOVEU.W MOVEU. with zero extension MOVE. HWS.W instruction when loading word values into the AGU and program controller registers.L Examples Description Load register with 1 word from memory. with zero extension Load register with 1 long from memory. OMR. with zero extension Load register with 1 byte from memory. Suffixes for Move Instructions Suffix .BP X:(R0). Typical 16-Bit-Word Register Loads Instruction MOVE. This instruction loads the value into the register and sign extends it correctly.X0 MOVE.W Destination Data ALU registers AGU registers LA. Table 3-6.2.W MOVEU.2.B U. For loading data ALU registers.2 Moving Words from Memory to a Register Data ALU registers are typically used to hold signed or fractional data because these data types are the ones that are most often used in DSC algorithms. with sign extension Load register with 1 byte from memory.Data Types and Addressing Modes Table 3-5 summarizes the various move instructions. 3-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . with sign extension Load register with 1 byte from memory.W instruction is always used to store any register to a word location in memory.3.3 Accessing Peripheral Registers The rules for accessing peripheral registers are the same as the rules for data memory accesses because peripheral registers are memory mapped in the data memory space. note that no extension is performed when moving to 24-bit AGU registers Load register with 1 byte from memory.B .X0 MOVEU.W X:(R0).W instruction is most frequently used. with sign extension Load register with 1 word from memory.L X:(R0). When loading word values into any of these registers. with sign extension.X0 3.A .R5 MOVE. LC.B X:(R0). Table 3-5.3. be sure to use the correct type of MOVE instruction to fit the use of the value.W . the MOVE.W X:(R0). the AGU and program controller registers almost always manipulate unsigned values because addresses are always positive integer values. In contrast.

When loaded into a temporary register. Examples of Operands in Memory . Add word in memory to accumulator ADD.W X:$2000.Memory Access Overview 3. Parallel moves are restricted to arithmetic operations in the data ALU.A uses the same method for loading the value at byte address $4000 into a temporary register that the instruction MOVE.W P:(R0)+. the value must then be written back to data memory. Example 3-2 shows examples of valid program memory accesses.BP X:$4000 .X0 MOVEU. Read 16-bit unsigned word from program memory .3.A uses to load the value into A. “Data Alignment in Accumulators. Decrement long in instruction memory memory memory 3.W X:$2000 . for example. Example 3-3. For more information on this loading method. Accesses to program memory follow the same rules that are used for data memory accesses.L X:$2000 . This operand value must be moved into a temporary register in the data ALU or in the AGU before the instruction can use it. Add long in memory to accumulator . Program Memory Accesses MOVE. Write 16-bit word to memory 3.4 Instructions with an Operand in Data Memory In some arithmetic instructions. A parallel move is not permitted.WP:(R0)+.4.3 Instructions That Access Program Memory The size of data that is accessed from program memory is always 16 bits.5 Parallel Moves The core implements two additional types of memory moves: the single parallel move and the dual parallel read.B X:$4000. the instruction ADD. one operand is located in data memory.memory location with read-modify-write DEC.” Example 3-3 shows some instructions with an operand in data memory. Decrement byte in DEC.L X:$2000.memory location as source operand ADD.B X:$4000. For example.1.P:(R0)+ . Freescale Semiconductor Data Types and Addressing Modes 3-11 .W” suffix is used at all times.R3 MOVE. the value is aligned and extended in the same way that it would be if it were placed in a register with a MOVE instruction. with a JMP or BFSET instruction.3.BP X:$4000. Add byte in memory to accumulator ADD. If the instruction modifies the operand value.3. Decrement word in DEC. so the “. Example 3-2.A .A .A . see Section 3. Read 16-bit signed word from program memory . Both are considered “parallel move” instructions and are extremely powerful in DSC algorithms and numeric computation.W R2.

Data Types and Addressing Modes 3. The size of the access is 1 memory word. it is possible to add two numbers while writing a value from a data ALU register to memory. Dual Parallel Read 3-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X:(R1)+N . a dual parallel read can multiply two numbers while reading two values from data memory to two of the data ALU registers. Figure 3-2 illustrates a single parallel move that uses 1 program word and executes in 1 instruction cycle.A Y0. all in the same instruction. Register X0 is added to the A accumulator. For example. the R0 register is post-updated with the value R0+N. Single Parallel Move 3. When the memory move is completed. in 1 clock cycle.3.5. 4. The original contents of the X0 and Y0 registers are multiplied. the following events occur: 1. and the result is added to and stored in the A accumulator. in 1 instruction cycle. Example parallel move instruction Opcode and Operands Single Parallel Move (Uses XAB1 and CDBW) Figure 3-2. The contents of the data memory location pointed to by the R3 register are moved into the X0 register.X0 Opcode and Operands Primary Read (Uses XAB1 and CDBR) Secondary Read (Uses XAB2 and XDB2) Figure 3-3. Figure 3-3 illustrates a dual parallel read that also uses 1 program word and executes in 1 instruction cycle.1 Single Parallel Move The single parallel move allows an arithmetic operation and 1 memory word access to be completed with 1 instruction. 2. ADD X0. the R1 register is post-updated by the value of R1+N. and R3 is decremented.5. and the result is stored back in A. The contents of the data memory location pointed to by the R0 register are moved into the Y1 register.A X:(R0)+N. For example.3. The contents of the Y0 register is stored as a word in data memory at the address contained in the R1 register. the following events occur: 1. After completing the memory moves. In this example. 2. 3. The size of the access is 1 memory word. the dual parallel read performs an arithmetic operation and reads two word values from data memory. 3.2 Dual Parallel Read With a single instruction.Y0. In this example.Y1 X:(R3)-. MAC X0.

B do not change the LSP of a 32. When a signed move is performed. C. MOVE. or D) is the source operand.4.BX:(R0+3). Values can be loaded into an accumulator as either signed or unsigned. Saturation is allowed only on word data types (MOVE. Byte and word values are located in the FF1 portion of an accumulator. accumulator accumulator accumulator accumulator accumulator accumulator loaded loaded loaded loaded loaded loaded with with with with with with signed byte signed byte unsigned byte unsigned byte signed word signed long Moves from an accumulator register to memory use only the portions of the accumulator that are identified in Figure 3-4. MOVEU. In this case.B. the LSP is cleared.BP (Unsigned Byte Move) ZXT.A MOVEU.B.4 Data Alignment This section discusses how data is aligned in registers and memory.A MOVEU.A . Move instructions that place a value in an accumulator are shown in Example 3-4.W X:(R0).B and ZXT.1 Data Alignment in Accumulators Figure 3-4 shows the alignment of different-size data values when they are located in an accumulator. Loading Accumulators with Different Data Types MOVE. .A MOVE.or 36-bit register destination.B X:(R0+88).W) and occurs only when an entire accumulator (A. Example 3-4. 35 MOVE. See Example 3-5 on page 3-14.A MOVE. the FF0 portion is always cleared. Unsigned moves cause the value to be zero extended.Data Alignment 3. while 32-bit values occupy both the FF1 and FF0 portions. . 3.L (Force to Signed Long) NOTE: Instructions SXT. Figure 3-4.A MOVE. respectively. . B.BPX:(R0). the value is sign extended through bit 35 of the accumulator.BP (Signed Byte Move) SXT. Freescale Semiconductor Data Types and Addressing Modes 3-13 .B (Force to Signed Byte) 35 MOVEU. Data Alignment in Accumulators When a byte or word value is moved into an accumulator using one of the MOVE instructions.B (Force to Unsigned Byte) 35 MOVE.W (Signed Word Move) Zero Extension 32 31 Sign Extension 32 31 Sign Extension 16 15 Zero Fill 0 Sign Extension 24 23 16 15 Zero Fill 0 24 23 16 15 Zero Fill 0 0 35 MOVE. unless the source is a 16-bit register.L (Signed Long Move) SXT.BPX:(R0)+. using the MOVE or MOVEU mnemonics. .L X:(R0). .

N. 15 MOVE. the value is sign extended to 16 or 32 bits before it is written.B or MOVEU.3 Data Alignment in 24-Bit AGU and Control Registers The 24-bit registers in the AGU include the address pointer registers (R0–R5.X:(R0+3) MOVE.W) from memory (integer or fractional) fill the entire 16-bit register.B (Signed Byte Move) 8 7 Sign Extension 8 7 Zero Extension 0 15 MOVEU.W A1. . Supported Data Types in Data Registers (X0.BPA1. Signed moves cause the value to be sign extended. Y0) The Y register.W (Signed Word Move) 0 Figure 3-5. Unsigned moves are marked with “U” (MOVEU.W or MOVE. 3. and long word) are right aligned in the destination register. .B or MOVE.B A1. 3-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Signed moves of bytes from memory (MOVE.X:(R0) . 3.4. and SP). Y1. .2 Data Alignment in Data Registers The alignment of data within the 16-bit data registers is shown in Figure 3-5. All values (byte. When an unsigned move instruction is used to load one of these registers. Storing Accumulators with Different Data Types MOVE.4. It is always read or written with a long-word move instruction (MOVE.X:(R0) MOVE. the value is zero extended to the full register width. . The placement of data in AGU registers from memory appears in Figure 3-6 on page 3-15.L A10. loop address registers (LA and LA2). word.L).W A.BP) and place zero extension into the upper 8 bits of the data register. the combination of the Y0 and Y1 registers. and the hardware stack register (HWS).BP) are put in the lower 8 bits of the data register and are sign extended in the upper 8 bits. store store store store store accumulator accumulator accumulator accumulator accumulator byte byte word word long (no saturation) (no saturation) (no saturation) (saturation) (no saturation) When a MOVE.X:(R0) MOVE.X:(R0) MOVE.Data Types and Addressing Modes Example 3-5. can hold a full 32-bit value.B (Unsigned Byte Move) 0 15 MOVE. and it is never sign extended or zero extended because a 32-bit value completely fills it.L instruction is used to write an accumulator extension register to memory. Moves of words (MOVE.

3. Note that accessing the HWS register also pushes and pops values onto the hardware stack.L (Long Move) 0 Figure 3-6.B and ZXTA.B (Force to Unsigned Byte) Zero Extension 23 Zero Extension 0 16 15 MOVE.4. the lower 24 bits are written and the upper 8 bits are discarded. Freescale Semiconductor Data Types and Addressing Modes 3-15 . Reading this register with a MOVE.5 Data Alignment in Memory The DSC core architecture requires that variables in data memory be aligned to byte.Data Alignment 23 SXTA. the upper 16 bits are discarded.W) always access the low-order sixteen bits. Byte accesses are not supported with these registers. Using MOVE. or long-word address boundaries according to the type of data being accessed.L to store a register in memory stores the register value in the lower 24 bits and fills the upper 8 bits with zero. Sixteen-bit accesses (such as using MOVE.L (Long Move) 0 0 Figure 3-7. “Hardware Stack. LC.” on page 8-3 for details.B (Force to Signed Byte) 16 15 87 0 Sign Extension 23 Sign Extension 87 0 16 15 ZXTA.1. word. byte data types can be used with the AGU’s SXTA. Data Alignment in 24-bit AGU Registers When a MOVE.B instructions.4. Although there are no instructions that move bytes to or from the AGU registers. M01.L instruction.W (Unsigned Word Move) 15 MOVE.L instruction is used to write a value to an AGU pointer register. Data Alignment in 16-Bit AGU Registers 3.4. and LC2) is shown in Figure 3-7. When these registers are written to with a MOVE. and the upper 16 bits are filled with zero extension.W (Unsigned Word Move) 23 MOVE. Refer to Section 8.L instruction places the register contents on the lowest 16 bits.4 Data Alignment in 16-Bit AGU and Control Registers The alignment of data within the AGU’s 16-bit registers (N3. 15 MOVEU.W (Signed Word Move) Sign Extension 23 16 15 Zero Extension 16 15 0 MOVEU.

3-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the complete word. When word pointers are used.4. the core data memory map can be thought of as 224 contiguous 16-bit words.5.4. Word Pointer 23 16 15 8 7 1 0 Word Address Word pointers can access bytes. it will use up 16 bits and will be located in the least significant 8 bits. the instruction set supports two types of addresses: byte and word. The variables thus created are referenced by the word address labels X:BYTVAR1 and X:BYTVAR2. since the 24-bit address used for accessing bytes can only access the lower 223 words in data memory. or two words when a long-word access is performed.Data Types and Addressing Modes 3. the upper byte is selected. Structure of Byte and Word Addresses Bits 23–1 of a byte address select the word in the memory map that is to be accessed. the assembler will force the address of the variable to be even. Figure 3-8. Example 3-6 on page 3-17 shows the ds assembler directive being used to allocate 1 word of uninitialized data memory. if the LSB is one. Byte addresses are used only for accessing bytes. because there are only 23 word-select bits in a byte pointer. or long-word (32-bit) values in memory. the lower byte within the word is selected. the byte is located in the least significant 8 bits of the word. For each variable. the address selects for use one of the bytes of the word. words. If the LSB is zero. byte variables can only be located in the lower 223 locations in the data memory map. Note that. When a byte is allocated statically or globally using a label. Although byte variables can be located at any address. word (16-bit). Byte Pointer 23 16 15 8 7 1 0 Word Address Upper or Lower Byte Select Byte pointers can access bytes only. Byte pointers select both the word in the memory map to access and the desired byte within the word. the core assembler only allows byte labels on word (even) address boundaries. When a label is used to name a byte variable location. or long words. Figure 3-8 shows the two types of pointers. The LSB selects the byte within that word. Word addresses can be used to access byte (8-bit).1 Byte and Word Addresses In order to access the different sizes of data that are supported by the core.2 Byte Variable Alignment Byte variables can be allocated anywhere in the lower half of the 24-bit data memory space. 3.5. In general.

in which each address represents one 16-bit word value. ‘r’ in upper byte ‘l’ in lower byte.5. . An array of bytes can begin at any byte address.1 Word and Byte Pointers As described in Section 3. Allocate 2 bytes at word address = $100 . . “Accessing Long-Word Values Using Word Pointers. This organization accounts for why the pairs of characters are reversed in Example 3-7.4.Memory Access and Pointers Example 3-6.5.5. This section introduces the concept of word and byte pointers and shows how they are used to access byte. Example 3-7. as illustrated in Figure 3-10 on page 3-19. and long values in memory.3 Word Variable Alignment Word (16-bit) variables are naturally aligned correctly using word addressing—each address is treated as referring to a 16-bit data value (see Section 3.” for more information.2. Allocation of a Character String STRING1 org dcb dcb dcb dcb X:$200 ‘ym’ ‘w ’ ‘ro’ ‘dl’ . 3. DS directive allocates a second word at $102 Arrays of bytes and structures containing bytes correctly allocate a byte as 8 bits rather than 16 bits.5. 3. Byte pointers are used to access byte values in memory. and long-word memory accesses while maintaining compatibility with the DSP56800 architecture.4.4. .3. while word pointers are used to access byte. In general. word. The string uses 8 bytes of data memory (four 16-bit words). ‘d’ in upper byte Data is organized in the memory map with the least significant byte occupying the lowest address in memory—so-called little-endian byte ordering.” for information on word addressing). . a long word is accessed using the (lower) even word address.5. Long-word accesses using the stack pointer work somewhat differently. word.4 Long-Word Alignment The core architecture requires that long-word variables be allocated on even word addresses. word. In Example 3-7. Allocate 8 bytes at word address = $200 ‘m’ in lower byte. The core instruction set has been enhanced to access byte. ‘y’ in upper byte ‘ ’ in lower byte. a string containing the characters “my world” is allocated in data memory. 3. DS directive allocates 1 word at $100 . See Section 3.5. Freescale Semiconductor Data Types and Addressing Modes 3-17 .” the core architecture supports both byte and word addresses. Data accesses to program memory are always treated as word accesses and behave the same as word accesses to data memory. or long-word data types in memory. 3. where each character is stored in a byte. “Byte and Word Addresses. Allocation of 2 Bytes Globally BYTVAR1 BYTVAR2 org ds ds X:$100 1 1 .1. ‘w’ in upper byte ‘o’ in lower byte. “Accessing Word Values Using Word Pointers.5 Memory Access and Pointers The DSP56800 core was designed to operate as a word-addressable machine.

6. Offsets are always in bytes. More detailed examples of byte and word pointers appear in Section 6. using the ASLA instruction. They provide efficient accesses to structures. Offsets in the N register are expressed in words (for word instructions) or in longs (for long instructions).W”.” on page 6-8 and Section 6. SP) points to a word address in memory.BP — ADD. However.L” suffixes indicate that an address register represents a word pointer. and RTI. word. Byte pointers are used exclusively for accessing byte values in data memory.BP. RTS. They cannot access program memory.BP — CLR. SUB. Instructions use the “. and it is considered a word pointer when it is used by instructions expecting word pointers.5. or long data memory accesses. N.BP” suffix to indicate that an address register is to be used as a byte pointer. NEG. Word pointers. The SP register is always used as a stack pointer. word. DEC. Examples of byte and word pointers are shown in the following sections. 3-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . using the LSRA instruction (the LSB is lost). or long word. Characteristics of word pointers include the following: • • • They indicate that an address register (R0–R5. Immediate offsets are in bytes (for byte instructions) or in words (for word and long instructions). Several instructions use address registers as byte pointers. it is possible to place and access bytes on the stack with the (SP – offset) addressing modes.BP. The “.BP. The suffix “. TST. They indicate that an address register (R0–R5.BP. CMP. Similarly.Data Types and Addressing Modes There is no inherent difference between a byte address and a word address—they are both simply 24-bit quantities. a byte pointer can be converted to a word pointer by logically right shifting the value 1 bit.BP” is also used to indicate that an absolute address is a byte address. They are extremely efficient for accessing arrays of bytes in memory. can be used for accessing data of any size: byte.B”.BP — INC.BP. Individual instructions determine how an address is used: an address in an AGU register is considered a byte pointer when it is used by instructions that expect byte pointers. “Word Pointer Memory Accesses. They are fully compatible with the DSP56800 architecture. MOVEU. “. N) points to a byte address in data memory. The instruction itself determines if an address is used as a word or byte pointer.BP.BP NOTE: • • • • • • • • • Characteristics of byte pointers include the following: The SP register cannot be used as a byte pointer. however. so it must always be word aligned for the correct operation of instructions such as JSR.” on page 6-13. which only supports word accesses. They can be used for byte. including the following: — MOVE. They can only access the lower half of the 24-bit data memory space (the lowest 223 words). and “. A word pointer can be converted to a byte pointer by left shifting the value 1 bit. “Byte Pointer Memory Accesses. They are used for byte accesses only.

Figure 3-9 shows an example of a word access using a word pointer. Word memory accesses always use an address as a word pointer. This instruction uses the value in the R0 register. and is always aligned on an even word address except when SP is used. The example executes the MOVE. $1000.W or MOVEU. as shown in Figure 3-10. as the address in X memory to which the value in A1 ($ABCD) is written. X Memory Word Address 15 0 $001000 A B C D R0 $001000 Instruction: MOVE.X:(R0) instruction. The even address holds the lower word.W instructions or with any of the data ALU instructions that access an operand from data memory.W X:(R0).W X:$C200.W A1.L instruction or with any data ALU instruction that accesses a long-word operand from data memory. Correct Storage of 32-Bit Value in Memory Freescale Semiconductor Data Types and Addressing Modes 3-19 .W A1. such as ADD.Memory Access and Pointers 3.5.X:(R0) Access Size: Word Figure 3-9.A or DEC.L X:$1000. such as ADD. Long-word memory accesses always use a word address.2 Accessing Word Values Using Word Pointers Word values are accessed from program or data memory with the MOVE. Accessing a Word with a Word Pointer 3.A. and the odd address holds the upper word. Storage of $12345678 in Data Memory X Memory Word Address 15 0 1 $001000 5 2 6 3 7 4 8 Odd Address: Always holds upper word Even Address: Always holds lower word Figure 3-10.3 Accessing Long-Word Values Using Word Pointers Long-word values are accessed from data memory with the MOVE. Each long-word value occupies two memory word locations.5.

” on page 9-9 for more information. the effective address used to access the value is not always that even word address. For all registers and addressing modes other than the stack pointer (SP).2.L A10. $1001.3. the effective address is the odd address that contains the upper word of the 32-bit value. X Memory Word Address 15 0 1 $001000 5 2 6 3 7 4 8 Note: Even Effective Address R0 $001000 Instruction: MOVE. Accessing a Long Word Using the SP Register 3-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .3. An attempt to access a long word in any other way generates a misaligned data access exception. as a word address. $12345678.X:(R0) instruction. which uses the value in the SP register. The example executes the MOVE.X:(SP) instruction. Refer to Section 9.3.L A10. The 32-bit value contained in the A accumulator. Accessing a Long Word Using an Address Register Figure 3-12 shows a long-word access using the stack pointer. which uses the value in the R0 register. The example executes the MOVE. is written to this location and the following one.L A10. The 32-bit value contained in the A accumulator.Data Types and Addressing Modes Although a long-word value is always located on an even word address boundary.X:(R0) Access Size: Long Effective Address: Even Value Figure 3-11. X Memory Word Address 15 0 1 $001000 5 2 6 3 7 4 8 Note: Odd Effective Address SP $001001 Instruction: MOVE. is written to addresses $1000 and $1001. $1000.L A10. Figure 3-11 shows a long-word access using an AGU pointer register.X:(SP) Access Size: Long Effective Address: Odd Value Figure 3-12. $12345678. “Misaligned Data Access Interrupt. as a word address. In an addressing mode that uses the stack pointer. the lower even address is used when accessing a long word.

5. the address contained in R0. 3.4 Accessing Byte Values Using Word Pointers The MOVE. In this example. are then written to this location. The byte address is specified using the following: • • The contents of a register: MOVE. $1000. N. Figure 3-13 shows an example of a byte access using a word pointer.A Freescale Semiconductor Data Types and Addressing Modes 3-21 . X Memory Word Address 15 0 Byte address: $2003 Word Address: $1001 Byte Select: 1 (Upper) $001001 $001000 C D X X LSB of Offset Short Immediate Value “3” from the Instruction Word >>1 + R0 Instruction: MOVE. The least significant bit (LSB) of the immediate offset selects which byte at the word address is accessed. SP) as word pointers and use an offset value to select the upper or lower byte. Accessing a Byte with a Word Pointer 3.5.A.A The result of an AGU calculation: MOVE.B A1.B and MOVEU.BP and MOVEU. such as ADD. is added to an immediate offset after the offset has been arithmetically right shifted 1 bit to give the correct word address: (3>>1) + $1000 = $1001. each long value must still be aligned on an even word address boundary even though the effective address that is used to access the value is odd. if the stack pointer addressing mode is used.BP X:$2001. The lowest 8 bits of the A1 register.B Access Size: Byte Byte Selected: Upper $001000 A1.BP X:(R2). the LSB of the immediate offset (3) is set. These instructions use the address registers (R0–R5. so the upper byte of the memory word is accessed. $CD. The example executes the MOVE. The lower byte of the memory location $1001 is not modified. Instructions that use addresses as byte pointers include the MOVE.B instructions are useful for accessing structures or unions containing bytes as well as for accessing bytes in a stack frame.BP X:(R1+$A701).BP instructions as well as data ALU instructions that access byte operands from data memory using the “.5 Accessing Byte Values Using Byte Pointers Byte pointers are useful for accessing byte variables or arrays of bytes.BP” suffix.X:(R0+3) instruction. When a byte pointer is used.Memory Access and Pointers Note that.X:(R0+3) Figure 3-13. In this case. the value in the selected address register is a byte address.

$1000. $CD.BP X:$108001. is logically right shifted to give the correct word address. are useful for converting a word address or label into a byte address for instructions that expect to receive a byte address. described in Table 3-7. The LSB of the R0 register selects which byte at the word address is accessed. These functions. $2001.X0 An absolute address (upper byte): MOVE. The lowest 8 bits of the A1 register. In this example.X:(R0) Figure 3-14. Useful Built-In Assembler Functions Assembler Function @hb(value) Computation Performed (value<<1) + 1 Comments Function is used to generate a byte address from a word address or label for the upper byte of a word Function is used to generate a byte address from a word address or label for the lower byte of a word @lb(value) (value<<1) + 0 NOTE: The stack pointer register is always used as a word pointer.BP A1. The lower byte of memory location $1000 is not modified.X:(R0) instruction.X0 Two of the functions in the preceding list are built into the assembler.BP Access Size: Byte Byte Selected: Upper A1.BP X:@hb($F000). Accessing a Byte with a Byte Pointer 3-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the LSB determines that the upper byte is to be accessed at location $1000. The example executes the MOVE. The address contained in R0. Figure 3-14 shows a byte access using a byte pointer.Data Types and Addressing Modes • • • An absolute address (upper byte): MOVE. Table 3-7. are then written to this location. X Memory Word Address 15 0 Word Address: $1000 Byte Select: 1 (Upper) $001000 C D X X >>1 LSB R0 $002001 Byte address: $2001 Instruction: MOVE.BP X:@lb(VAR_LABEL).X0 An absolute address (lower byte): MOVE.

Table 3-11 on page 3-25 shows all immediate addressing modes. 3. and how the register is updated. how the address is calculated. Table 3-12 on page 3-26 shows all absolute addressing modes. N. In some addressing modes. which are optimized for high-performance signal processing as well as for efficient controller code. N. R3 Comments Eight AGU address registers Six AGU address registers (DSP56800 registers) Seven AGU address registers Four pointer registers available for addressing Table 3-9 on page 3-24 shows all accessible core registers (register direct).1 Addressing Mode Summary This section contains a series of tables that summarize the addressing modes in the core. N R0. SP R0–R3. R1.6. Notation for AGU Registers Register Field Rn Rk RRR Rj Registers R0–R5. All address calculations are performed in the address generation unit to minimize execution time. SP R0–R5. An effective address in an instruction specifies the addressing mode. R2. in a register.” on page 4-20. “Instruction Summary Tables.Addressing Modes 3.4.6 Addressing Modes Addressing modes specify where the operands for an instruction can be found (in an immediate value.4. Table 3-10 on page 3-25 shows data and program memory accesses (address register indirect). the effective address further specifies an address register that points to a location in memory. The core instruction set contains a full set of operand addressing modes. The notation used in these tables to reference AGU registers is summarized in Table 3-8. The addressing modes are grouped into categories: • • • • • Register direct—directly references the registers on the chip as operands Address register indirect—uses an address register as a pointer to reference a location in memory as an operand Immediate—operand is contained as a value within the instruction itself Absolute—uses the address contained within the instruction itself to reference a location in memory as an operand Bit reverse (reverse carry)—applies only to address register indirect indexed by N = (Rn)+N address calculations and to word-sized or longword-sized operands These addressing modes are referred to extensively in Section 4. Table 3-8. or in memory) and provide the exact addresses of the operands. Freescale Semiconductor Data Types and Addressing Modes 3-23 .

Y0. and Table 4-18 on page 4-19. Y1.L HHHHH fff F F1 FF FFF1 FFF EEE Rj Rn RRR SSSS Examples A. LC2 HWS FISR. FIRA 1. A0 B. D0 Y. A1. R3 R4.L HHHH HHHH. LA2. C2. B0 C. R5 SP N N3 M01 PC OMR. R1.L DD DDDDD HHH HHH. SR LA.Data Types and Addressing Modes Table 3-9. B2. D2. C1. R2. X0 R0. A2. LC. Table 4-16 on page 4-17. C0 D. Register-Direct Addressing Mode Addressing Mode Any register Notation in the Instruction Set Summary1 dd dddd. 3-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . D1.The register field notations found in the middle column are explained in more detail in Table 4-17 on page 4-18. B1.

Address-Register-Indirect Addressing Modes Addressing Mode Notation in the Instruction Set Summary Accessing Program Memory Post-increment Post-update by offset N P:(Rj)+ P:(Rj)+N Accessing Data Memory No update X:(Rn) X:(R5) X:(N) X:(SP) X:(R1)+ X:(SP)+ X:(R5)– X:(N)– X:(R1)+N X:(R3)+N3 X:(R4+N) X:(SP+N) X:(R1+7) X:(N+3) X:(SP–8) X:(SP+15) X:(SP–$1E) X:(R4–97) X:(N+1234) X:(SP+$03F7) X:(Rn+$408001) X:(SP–$10ABCD) X:(N+$C08000) P:(R0)+ P:(R3)+N Examples Post-increment X:(Rn)+ Post-decrement X:(Rn)– Post-update by offset N or N3. 6-.Addressing Modes Table 3-10. and 7-bit (unsigned and signed) Immediate data—16-bit (unsigned and signed) Long immediate data—24. available for word accesses only Indexed by offset N X:(Rn)+N X:(R3)+N3 X:(Rn+N) Indexed by 3-bit displacement X:(RRR+x) X:(SP–x) Indexed by 6-bit displacement—SP register only X:(SP–xx) Indexed by 16-bit displacement X:(Rn+xxxx) Indexed by 24-bit displacement X:(Rn+xxxxxx) Table 3-11.and 32-bit Notation in the Instruction Set Summary #xx #xxxx #xxxxxxxx Examples #14 #<3 #$369C #>1234 #$12345678 #>>$00001234 Freescale Semiconductor Data Types and Addressing Modes 3-25 . Immediate Addressing Modes Addressing Mode Immediate short data—5-.

Data Types and Addressing Modes Table 3-12. These operators can be used in an instruction to force a desired addressing mode. Table 3-13. as shown in Table 3-13. Assembler Operator Syntax for Immediate Data Sizes Desired Action Force short immediate data Force 9-bit immediate data Force 16-bit immediate data Force 24. jump and branch instructions as shown in Table 3-14. 3-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .or 32-bit immediate data Force absolute short address Force I/O short address Force 16-bit absolute address Force 24-bit absolute long address Force short offset Forcing Operator Syntax #<xx #>xxx #>xxxx #>xxxxxx X:<xx X:<<xx X:>xxxx X:>xxxxxx X:(Rn+<x) X:(SP-<x) X:(SP-<xx) X:(Rn+>xxxx) X:(Rn+>>xxxxxx) Example #<$07 #>$07 #>$07 #>$07 X:<$02 X:<<$FFE3 X:>$02 X:>$02 X:(SP-<$02) X:(R0+<3) X:(SP->$02) X:(SP->>$02) Force 16-bit offset Force 24-bit offset Other assembler forcing operators are available for hardware looping. Absolute Addressing Modes Addressing Mode Absolute short address—6 bit (direct addressing) I/O short address—6 bit (direct addressing) Absolute address—16-bit (extended addressing) Absolute long address—24-bit (long extended addressing) Notation in the Instruction Set Summary X:aa X:<<pp X:xxxx X:xxxxxx Examples X:$0002 X:<$02 X:<<$FFE3 X:$00F001 X:>$C002 X:$18FC04 X:>>$804001 Several of the examples in Table 3-11 on page 3-25 and Table 3-12 demonstrate the use of assembler forcing operators.

Addressing Modes Table 3-14. Assembler Operator Syntax for Branch and Jump Addresses Desired Action Force 7-bit relative branch offset Force 18-bit relative branch offset Force 21-bit relative branch offset Force 19-bit absolute loop address Force 21-bit absolute loop address Force 19-bit absolute jump address Force 21-bit absolute jump address Forcing Operator Syntax <xx >xxxxx >>xxxxxx >xxxxx >>xxxxxx >xxxxx >>xxxxxx Example <LABEL1 >LABEL2 >>LABEL3 >LABEL4 >>LABEL5 >LABEL4 >>LABEL5 Freescale Semiconductor Data Types and Addressing Modes 3-27 .

NOTE: There can be pipeline dependencies when a data ALU.” on page 6-18 for detailed information on how arithmetic is performed for different data types and addressing modes. Effects of Data Types on AGU Arithmetic MOVE.8. Example 3-9. is in the AGU. 3 long words) from the SP.X0 .3 Address-Register-Indirect Modes In the address-register-indirect addressing modes. Most address-register-indirect modes also allow the pointer register to be updated in some way. “Linear and Modulo Address Arithmetic.BPX:(R5)+. when the register is used as a word pointer accessing a 16-bit word. “AGU Arithmetic Instructions. R0. the R5 register is post-incremented by one for a byte or word access and by two for a long memory access.A MOVE. Word Access: R5 <= R5 + 1 . two operands are specified with the register-direct addressing mode. Example 3-10.W X:(SP–3).Data Types and Addressing Modes 3. AGU. or control registers. the operand is not the address register itself.” on page 6-20. Example 3-8.W X:(R5)+. Note that the arithmetic performed can differ depending on the data type. Byte Access: R5 <= R5 + 1 .A . Using the Register-Direct Addressing Mode MOVE. “Pipeline Dependencies and Interlocks. X0.4.7.L X:(SP–6).6.6.A MOVE.W R0. Effects of Data Types on Address Displacements MOVE.” on page 10-26 to understand dependencies when accessing these registers. The source operand. or control register is being accessed. is in the data ALU. In Example 3-8. The remainder of this section illustrates each address-register-indirect addressing mode. accesses the memory location indicated by the address register and then subtracts one from the register. This type of reference is classified as a register reference. the AGU unit then left shifts the value in hardware to generate a displacement of 6 (that is. for example.A . but consists of the contents of the memory location that is pointed to by the address register.L X:(R5)+. In Example 3-9. Modulo arithmetic is covered in detail in Section 6. The X:(Rn)addressing mode. Refer to Section 10. data ALU. Access 3rd word from SP . Long Access: R5 <= R5 + 2 In the MOVE.2 Register-Direct Modes The register-direct addressing modes specify that each of up to three operands is in either the AGU. Operands are registers 3. the assembler right shifts the offset of “6” when encoding the value. Access 3rd long from SP The type of arithmetic (linear or modulo) used for calculating the effective address in R0 or R1 is specified in the modifier register (M01) rather than encoded in the instruction. 3-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . and the destination operand.A MOVE.L instruction in Example 3-10. See Section 6. When executing the instruction.

The contents of the address register are unchanged. N. X:(SP) Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0 Figure 3-15. or SP.W A1. Figure 3-15 demonstrates this addressing mode.1 No Update: (Rn) The address of the operand is in the address register Rn. X:(N). Long Assembler Syntax: X:(Rn).Addressing Modes 3.6.3. Word.X:(R2) Before Execution A2 A 0 1 2 35 32 31 A1 3 4 5 6 16 15 X Memory 15 0 15 A0 7 8 0 A A2 0 1 2 35 32 31 After Execution A1 3 4 5 6 16 15 X Memory 0 A0 7 8 0 $001000 X X X X $001000 1 2 3 4 R2 23 $001000 0 R2 23 $001000 0 Available for: Byte (Byte Pointer [Word Pointer for SP]). Address Register Indirect: No Update Freescale Semiconductor Data Types and Addressing Modes 3-29 . No Update Example: MOVE.

W B0. P:(Rj)+ Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0 Figure 3-16. After the operand address is used. Address Register Indirect: Post-Increment 3-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Long Assembler Syntax: X:(Rn)+.3. it is incremented and stored in the same address register. N. Post-Increment Example: MOVE.6. the pointer is incremented by two.Data Types and Addressing Modes 3. Word. or SP.2 Post-Increment: (Rn)+ The address of the operand is in the address register Rn. X:(N)+. When a long 32-bit memory location is accessed. Figure 3-16 demonstrates this addressing mode. X:(SP)+.X:(R2)+ Before Execution B2 B A 6 5 35 32 31 B1 4 3 F E 16 15 X Memory 15 0 15 B0 D C 0 B B2 A 6 5 35 32 31 After Execution B1 4 3 F E 16 15 X Memory 0 B0 D C 0 $002501 $002500 X X X X X X X X $002501 $002500 X F X E X D X C R2 23 $002500 0 R2 23 $002501 0 Available for: Byte (Byte Pointer).

or SP. When a long 32-bit memory location is accessed. N.X:(R2)Before Execution B2 B 0 6 5 35 32 31 B1 4 3 F E 16 15 X Memory 15 0 15 B0 D C 0 B B2 0 6 5 35 32 31 After Execution B1 4 3 F E 16 15 X Memory 0 B0 D C 0 $004735 $004734 X X X X X X X X $004735 $004734 6 X 5 X 4 X 3 X R2 23 $004735 0 R2 23 $004734 0 Available for: Byte (Byte Pointer). Address Register Indirect: Post-Decrement Freescale Semiconductor Data Types and Addressing Modes 3-31 . After the operand address is used.W B. X:(N)–. the pointer is decremented by two. Post-Decrement Example: MOVE. Word.Addressing Modes 3.3. Long Assembler Syntax: X:(Rn)–. it is decremented and stored in the same address register. X:(SP)– Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0 Figure 3-17.6. Figure 3-17 demonstrates this addressing mode.3 Post-Decrement: (Rn)– The address of the operand is in the address register Rn.

4 Post-Update by Offset N: (Rn)+N. In the addressing update. Address Register Indirect: Post-Update by Offset N 3-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . X:(R3)+N3. the contents of the offset register are treated as a signed. N. (R3)+N3 The address of the operand is in the address register Rn. Figure 3-18 demonstrates this addressing mode. the contents of the offset register (N or N3) are added to the address register and stored in the same address register. NOTE: The upper 8 bits of the N register are ignored in this addressing mode. 16-bit. X:(SP)+N.Data Types and Addressing Modes 3. or SP.W Y1. Post-Update by Offset N Example: MOVE.6.3. The lower 16 bits of the offset register are sign extended to 24 bits and used in the addition to the address register. two’s-complement number (the offset register itself remains unchanged). The 24-bit result is then stored back to the address register. P:(Rj)+N Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0 Figure 3-18. After the operand address is used. X:(N)+N.X:(R2)+N Before Execution Y1 Y 5 31 5 5 5 A A 16 15 X Memory 15 $003204 X X X X 0 $003204 15 X X X X Y0 A A 0 Y 5 31 5 After Execution Y1 5 5 A A 16 15 X Memory 0 Y0 A A 0 $003200 X X X X $003200 5 5 5 5 R2 23 N 23 $003200 0 $F00004 0 Sign Extend from Bit 15 + R2 23 N 23 $003204 0 $F00004 0 Available for: Word Assembler Syntax: X:(Rn)+N.

Figure 3-19 demonstrates this addressing mode. the N register is left shifted 1 bit before the addition.X:(R2+N) Before Execution A2 A F E D A1 C B A 9 A0 8 7 0 A A2 F E D 35 32 31 After Execution A1 C B A 9 16 15 X Memory 0 X X X $007003 15 E D C B 0 A0 8 7 0 35 32 31 16 15 X Memory 15 $007003 X $007000 X X X X $007000 X X X X R2 23 N 23 $007000 0 $000003 0 + R2 23 N 23 $007000 0 $000003 0 Available for: Byte (Byte Pointer).W A1. X:(N+N). two’s-complement. N. Long Assembler Syntax: X:(Rn+N). The content of N is treated as a signed. Indexed by Offset N Example: MOVE. The contents of the address register and N register are unchanged by this addressing mode. Word. or SP and the contents of the address offset register N. When a long 32-bit memory location is accessed.3. 24-bit number.6.5 Index by Offset N: (Rn+N) The address of the operand is the sum of the contents of the address register Rn. Address Register Indirect: Indexed by Offset N Freescale Semiconductor Data Types and Addressing Modes 3-33 . X:(SP+N) Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 0 Figure 3-19.Addressing Modes 3.

The field is always zero extended to form a positive offset from 0 to 7 when R0. Word Assembler Syntax: X:(Rn+x). Indexed by 3-Bit Displacement Example: MOVE. R5. or the N register is used.W A1.6. This field is always one extended to form a negative offset from –1 to –8 when the SP register is used.X:(R4+3) Before Execution A2 A F E D 35 32 31 A1 C B A 9 16 15 X Memory 15 $007003 X X X X 0 $007003 15 E D C B A0 8 7 0 A A2 F E D 35 32 31 After Execution A1 C B A 9 16 15 X Memory 0 A0 8 7 0 $007000 X X X X $007000 X X X X R4 23 $007000 0 + R4 23 $007000 0 Zero Extend for (RRR+x) One Extend for (SP–x) 3-Bit Immediate Value from the Instruction Word Available for: Byte (Word Pointer). X:(N+x). R4. R3. Address Register Indirect: Indexed by 3-Bit Displacement 3-34 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . R2. R1.6 Index by 3-Bit Displacement: (RRR+x). X:(SP–x) Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 0 Figure 3-20. (SP–x) This addressing mode contains the 3-bit immediate displacement within the instruction word. Figure 3-20 demonstrates this addressing mode.3.Data Types and Addressing Modes 3.

7 Index by 6-Bit Displacement: (SP–xx) This addressing mode contains the 6-bit immediate displacement within the instruction word. Indexed by 6-Bit Displacement Example: MOVE.3. When a long 32-bit memory location is accessed. This field is always one extended to form a negative offset from –1 to –64. Address Register Indirect: Indexed by 6-Bit Displacement Freescale Semiconductor Data Types and Addressing Modes 3-35 . Figure 3-21 demonstrates this addressing mode. Long Assembler Syntax: X:(SP–xx) Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 0 Figure 3-21.W A1.6. the 6-bit displacement is left shifted 1 bit before the addition.X:(SP-32) Before Execution A2 A F E D 35 32 31 A1 C B A 9 16 15 X Memory 15 $007020 X X X X 0 $007020 15 X X X X A0 8 7 0 A A2 F E D 35 32 31 After Execution A1 C B A 9 16 15 X Memory 0 A0 8 7 0 $007000 X X X X $007000 E D C B SP 23 $007020 0 + SP 23 $007020 0 One Extend for (SP–xx) 6-Bit Immediate Value from the Instruction Word Available for: Word.Addressing Modes 3.

X:(SP+xxxx) Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 1 Figure 3-22. When byte values are accessed. Long Assembler Syntax: X:(Rn+xxxx).X:(R2+$10CF) Before Execution A2 A F E D 35 32 31 A1 C B A 9 16 15 X Memory 15 $0080CF X X X X 0 $0080CF 15 E D C B A0 8 7 0 A A2 F E D 35 32 31 After Execution A1 C B A 9 16 15 X Memory 0 A0 8 7 0 $007000 X X X X $007000 X X X X R2 23 $007000 0 + R2 23 $007000 0 Zero Extend for MOVE.BP One Extend for All Other Instructions 16-Bit Immediate Value from the Instruction Word Available for: Byte (Byte and Word Pointer). two’s-complement.6. Figure 3-22 demonstrates this addressing mode. This addressing mode is available for the move instructions. X:(N+xxxx). Word. the displacement is given in bytes. MOVEU. When a long 32-bit memory location is accessed.W A1. 16-bit value except when byte pointers (MOVE.BP) are used.BP. Indexed by 16-Bit Displacement Example: MOVE. in which case the second word is zero extended.8 Index by 16-Bit Displacement: (Rn+xxxx) This addressing mode contains the 16-bit immediate displacement in the second instruction word. the 16-bit displacement is left shifted 1 bit before the addition. This second word is treated as a signed.3.BP and MOVEU. Address Register Indirect: Indexed by 16-Bit Displacement 3-36 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Data Types and Addressing Modes 3.

Addressing Modes

3.6.3.9 Index by 24-Bit Displacement: (Rn+xxxxxx)
This addressing mode contains the 24-bit immediate displacement in 2 of the 3 instruction words. The 24-bit displacement is treated as a signed, two’s-complement value. This addressing mode is available for move instructions. When a long-word (32-bit) memory location is accessed, the 24-bit displacement is left shifted 1 bit before the addition. When a byte is accessed, the displacement value is given in bytes. Figure 3-23 demonstrates this addressing mode.
Indexed by 24-Bit Long Displacement Example: MOVE.W A1,X:(R2+$40100F)
Before Execution A2 A F E D 35 32 31 A1 C B A 9 16 15 X Memory 15 $40800F X X X X 0 $40800F 15 E D C B A0 8 7 0 A A2 F E D 35 32 31 After Execution A1 C B A 9 16 15 X Memory 0 A0 8 7 0

$007000

X

X

X

X

$007000

X

X

X

X

R2 23

$007000 0 +

R2 23

$007000 0

24-Bit Immediate Value from the Instruction Word

Available for: Byte (Byte and Word Pointer), Word, Long Assembler Syntax: X:(Rn+xxxxxx), X:(N+xxxxxx), X:(SP+xxxxxx) Additional Instruction Execution Cycles: 2 Additional Effective Address Program Words: 2

Figure 3-23. Address Register Indirect: Indexed by 24-Bit Displacement

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3.6.4 Immediate Address Modes
The immediate address modes do not use an address register to specify an effective address. These modes specify the value of the operand directly in a field of the instruction.

3.6.4.1 4-Bit Immediate Data: #x
The 4-bit immediate data operand is located in the instruction operation word. In the ADDA instruction, the 4-bit unsigned value is zero extended to form a 24-bit value. In data ALU shifting instructions, the 4-bit value is zero extended to form a data ALU operand.

3.6.4.2 5-Bit Immediate Data: #xx
The 5-bit immediate data operand is located in the instruction operation word. When the MOVE.L instruction is used to write an accumulator, the 5-bit value is sign extended to form a 36-bit value. In data ALU instructions, the 5-bit value is zero extended to form a data ALU operand. Figure 3-24 demonstrates this addressing mode.
5-Bit Immediate into Full 36-Bit Accumulator Example: MOVE.L #-4,B
Before Execution B2 B X X X 35 32 31 B1 X X X X 16 15 B0 X X 0 B B2 F F F 35 32 31 After Execution B1 F F F F 16 15 B0 F C 0

Available for: Long Assembler Syntax: #xx Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0

Figure 3-24. Immediate Addressing: 5-Bit Immediate Data to Accumulator

3.6.4.3 6-Bit Immediate Data: #xx
The 6-bit immediate data operand is located in the instruction operation word. The 6-bit unsigned value is zero extended to form a 16-bit loop count. It is used by the DO and REP instructions when the loop count is specified with an immediate value.

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3.6.4.4 7-Bit Immediate Data: #xx
The 7-bit immediate data operand is located in the instruction operation word. The 7-bit signed value is sign extended to the appropriate size of the register. It is used by the MOVE.W instruction. Figure 3-25 and Figure 3-26 demonstrate this addressing mode.
7-Bit Immediate Into 24-Bit Address Register Example: MOVE.W #-2,R0

Before Execution R0 23 R0 0 23

After Execution

XXXXXX

$FFFFFE 0

Available for: Word Assembler Syntax: #xx Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0

Figure 3-25. Immediate Addressing: 7-Bit Immediate Data to Address Register

7-Bit Immediate into 16-Bit Data Register Example: MOVE.W #$0006,X0

Before Execution X0 15 XXXX 0 X0 15

After Execution $0006 0

7-Bit Immediate into 36-Bit Accumulator Example: MOVE.W #-58,B
Before Execution B2 B X X X 35 32 31 B1 X X X X 16 15 B0 X X 0 B B2 F F F 35 32 31 After Execution B1 C 6 0 0 16 15 B0 0 0 0

Available for: Word Assembler Syntax: #xx Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0

Figure 3-26. Immediate Addressing: 7-Bit Immediate Data to Data ALU Register

See Section 5.2.3, “Reading and Writing Integer Data to an Accumulator,” on page 5-12 for more details on correctly loading the accumulator registers.

3.6.4.5 16-Bit Immediate Data: #xxxx
There are two instructions available for writing 16-bit immediate data to an AGU register. The MOVEU.W instruction loads an AGU register with an unsigned 16-bit value, and the MOVE.L instruction loads an AGU register with a signed 16-bit value. Figure 3-27 on page 3-40 demonstrates these two instructions.

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Immediate into 24-Bit Address Register Example: MOVE.L #$FF8001,R5
Before Execution R5 X 23 X X X X X 0 R5 After Execution F 23 F 8 0 0 1 0

16 15

16 15

Immediate into 24-Bit Address Register Example: MOVEU.W #$8001,R5
Before Execution R5 X 23 X X X X X 0 R5 After Execution 0 23 0 8 0 0 1 0

16 15

16 15

Available for: Word Assembler Syntax: #xxxx Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 1

Figure 3-27. Immediate Addressing: 16-Bit Immediate Data to AGU Register

Sixteen-bit immediate data can also be moved to the data ALU registers. When the MOVE.W instruction is used, the 16-bit value is loaded into the MSP of the accumulator, the value is sign extended into the extension register, and the LSP is cleared. If the MOVE.L instruction is used, the value is moved into the LSP of an accumulator and is sign extended through the upper 20 bits. These two cases are shown in Figure 3-28.
Positive Immediate into 36-Bit Accumulator Example: MOVE.W #$1234,B
Before Execution B2 B X X X B1 X X X X B0 X X 0 B B2 0 1 2 After Execution B1 3 4 0 0 B0 0 0 0

35 32 31

16 15

35 32 31

16 15

Negative Immediate into Full 36-Bit Accumulator Example: MOVE.L #$FFFFB000,B
Before Execution B2 B X X X B1 X X X X B0 X X 0 B B2 F F F After Execution B1 F F B 0 B0 0 0 0

35 32 31

16 15

35 32 31

16 15

Available for: Word, Long Assembler Syntax: #xxxx Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 1

Figure 3-28. Immediate Addressing: 16-Bit Immediate Data to Data ALU Register

Sixteen-bit immediate data is also used to specify the mask for the bit-manipulation instructions.

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3.6.4.6 32-Bit Immediate Data: #xxxxxxxx
Figure 3-29 demonstrates using 32-bit immediate data to load a register. The immediate data value is truncated to 24 bits when it is written to one of the 24-bit AGU registers. The value is sign extended when it is moved to a 36-bit accumulator.
Immediate into 24-Bit Address Register Example: MOVE.L #$12345678,R5
Before Execution R5 X 23 X X X X X 0 R5 3 23 After Execution 4 5 6 7 8 0

16 15

16 15

Negative Immediate into 36-Bit Accumulator Example: MOVE.L #$800CF001,B
Before Execution B2 B X X X B1 X X X X B0 X X 0 B B2 F 8 0 After Execution B1 0 C F 0 B0 0 1 0

35 32 31

16 15

35 32 31

16 15

Positive Immediate into Full 36-Bit Accumulator Example: MOVE.L #$A987,B
Before Execution B2 B X X X B1 X X X X B0 X X 0 B B2 0 0 0 After Execution B1 0 0 A 9 B0 8 7 0

35 32 31

16 15

35 32 31

16 15

Available for: Long Assembler Syntax: #xxxxxxxx Additional Instruction Execution Cycles: 2 Additional Effective Address Program Words: 2

Figure 3-29. Immediate Addressing: 32-Bit Immediate Data

3.6.5 Absolute Address Modes
The absolute address modes do not use an address register to specify an effective address. These modes specify the address of the operand directly in a field of the instruction. This category includes direct addressing, extended addressing, and immediate data.

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Data Types and Addressing Modes

3.6.5.1 Absolute Short Address: aa
For the absolute short addressing mode, the address of the operand occupies 6 bits in the instruction operation word and is zero extended to 24 bits. This scheme allows direct access to the first 64 locations in X memory. No registers are used to form the address of the operand. Figure 3-30 demonstrates this addressing mode. Note the use of the assembler forcing operator (<) in this example (see Table 3-13 on page 3-26).
Absolute Short Address Example: MOVE.W R2,X:<$0003

Before Execution R2 15 $ABCD 0 R2 15

After Execution $ABCD 0

X Memory 15 0 15

X Memory 0

$000003

X

X

X

X

$000003

A

B

C

D

$000000

$000000

Available for: Word Assembler Syntax: X:aa Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0

Figure 3-30. Absolute Addressing: 6-Bit Absolute Short Address

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3.6.5.2 I/O Short Address: <<pp
In this addressing mode, the instruction specifies only the 6 LSBs of the effective address. The upper 18 bits are hard-wired to a specific area of memory, which varies depending on the specific implementation of the chip. This scheme allows efficient access to a 64-location area in data memory, which may be dedicated to on-chip peripheral registers. Figure 3-31 demonstrates the I/O short addressing mode. Note the use of the assembler forcing operator (<<) in this example, indicating that the I/O short addressing mode is in use (see Table 3-13 on page 3-26).
I/O Short Address Example: MOVEU.W X:<<$FFFB,R3
Before Execution R3 15 XXXX 0 R3 15 After Execution $5678 0

X Memory 15 0 15

X Memory 0

$00FFFF

$00FFFF

$00FFFB

5

6

7

8

$00FFFB

5

6

7

8

Available for: Word Assembler Syntax: X:<<pp Additional Instruction Execution Cycles: 0 Additional Effective Address Program Words: 0

Figure 3-31. Absolute Addressing: 6-Bit I/O Short Address

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3.6.5.3 16-Bit Absolute Address: xxxx
The address of the operand is zero extended to 24 bits. No registers are used to form the address of the operand. When a long 32-bit memory location is accessed, the 16-bit absolute address is left shifted 1 bit before the access occurs. Figure 3-32 demonstrates the 16-bit absolute addressing mode.
Absolute Address Example: MOVE.W X:$8079,X0

Before Execution X0 15 XXXX 0 X0 15

After Execution $1234 0

X Memory 15 0 15

X Memory 0

$008079

1

2

3

4

$008079

1

2

3

4

Available for: Byte (BP), Word, Long Assembler Syntax: X:xxxx Additional Instruction Execution Cycles: 1 Additional Effective Address Program Words: 1

Figure 3-32. Absolute Addressing: 16-Bit Absolute Address

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3.6.5.4 24-Bit Absolute Address: xxxxxx
This addressing mode requires 2 words of instruction extension. The address of the operand is located in the extension words. No registers are used to form the address of the operand. When a long 32-bit memory location is accessed, the 24-bit absolute address is left shifted 1 bit before the access occurs. Figure 3-33 demonstrates the 24-bit absolute addressing mode.
Absolute Address Example: MOVE.W X:$418003,X0

Before Execution X0 15 XXXX 0 X0 15

After Execution $1234 0

X Memory 15 0 15

X Memory 0

$418003

1

2

3

4

$418003

1

2

3

4

Available for: Byte (BP), Word, Long Assembler Syntax: X:xxxxxx Additional Instruction Execution Cycles: 2 Additional Effective Address Program Words: 2

Figure 3-33. Absolute Addressing: 24-Bit Absolute Address

3.6.6 Implicit Address Modes
Some instructions make implicit reference to the program counter (PC), software stack, hardware stack, loop address register (LA), loop counter (LC), or status register (SR). For example, the DO instruction accesses the LA and LC registers without explicitly referencing them in the instruction. Similarly, the JSR, RTI, and RTS instructions access the PC, SR, and SP registers without explicitly referencing them in the instruction. The implied registers and their use are described in the individual instruction descriptions in Appendix A, “Instruction Set Details.”

3.6.7 Bit-Reverse Address Mode (DSP56800EX Core only)
The bit-reverse address mode, which is also known as reverse carry address mode, is useful for many DSC applications. It is available only on the DSP56800EX core. Reverse carry arithmetic is enabled for the R0 and R1 registers through programming the Modifier Register (M01). Reverse carry addressing is not available for the R2-R5, N, or SP registers. The default addressing mode for the R0 and R1 registers is linear addressing. Linear arithmetic is enabled for the R0 and R1 registers by programming the M01 register to 0xFFFF. The M01 register is set to 0xFFFF at reset.

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For both the DSP56800E and DSP56800EX cores, an M01 register with M01[15:14] = 0b00 configures R0 for modulo arithmetic, and an M01 register with M01[15:14] = 0b10 configures both R0 and R1 registers for modulo arithmetic. For the DSP56800E core, M01 register settings with M01[15:14] = 0b01 or 0b11 (but not M01 = 0xFFFF) are reserved. For the DSP56800EX core, an M01 register setting with M01[15:0] = 0x4000 (M01[15:14] = 0b01; M01[13:0] = 0x0000) configures R0 for reverse carry addressing, and an M01 register setting with M01[15:0] = 0xc000 (M01[15:14] = 0b11; M01[13:0] = 0x0000) configures R0 and R1 for reverse carry addressing.
NOTE:

Modulo address arithmetic applies to certain instructions that operate on R0 and R1 as well as certain address calculations that use and/or update R0 and R1. In contrast, reverse carry addressing applies only to address register indirect indexed by N = (Rn)+N address calculations. Also, reverse carry addressing applies only to word-sized or longword-sized operands. Reverse carry address modification is useful for bit-reversed FFT buffers. Reverse carry address modification is designed to work on a buffer that is aligned on a 0-modulo-(power-of-two size) address (word or longword). It is designed to start at the beginning of the buffer and step through the entire buffer. The user has the responsibility to loop through the buffer the correct number of times. Performing reverse carry address modification beyond this number of times will simply repeat the loop through the buffer. Reverse carry addressing is performed by doing the (Rn)+N next address calculation and propagating the carry in the reverse direction modulo the buffer size. That is, the carry is propagated from the MSB of the buffer address to the LSB. Reverse carry addressing works as follows. A power-of-two buffer size must be used = 2**k where k < 13. • • The buffer must be aligned on a 0-modulo (2**k) address. The initial value of Rn is the start of the buffer and N must be 2**(k-1).

When (Rn)+N addressing is used, the next Rn is calculated as follows: 1. The lower-order 14 bits of Rn and N are reversed: Rn_reversed[13:0] = Rn[0:13] N_reversed[13:0] = N[0:13] 2. The next Rn with lower-order bits [13:0] reversed is calculated (carry is ignored): next_Rn_reversed[13:0] = Rn_reversed[13:0] + N_reversed[13:0] 3. The next Rn is built by reversing the lower-order 14 bits of this result and appending it to the upper bits of Rn: next_Rn[23:0] = {Rn[23:14], next_Rn_reversed[0:13]} The user is responsible for stepping through the buffer for the correct number of times. Example In the following example: • • • 8 word buffer = 2**3; k = 3; base at 0x00_BDC8 initial: Rn = 0x00_BDC8, N = 0x00_0004 = 2**(k-1) = 2**2 do 8 iterations; within the buffer the reference order is 0,4,2,6,1,5,3,7

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ITERATION 1: Rn = 0x00_BDC8, N = 0x00_0004
Rn_reversed[23:0] = 0x00_84EF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_8CEF current_address[23:0] = 0x00_BDC8 <- 1st reference next_Rn[23:0] = 0x00_BDCC

ITERATION 2: Rn = 0x00_BDCC, N = 0x00_0004
Rn_reversed[23:0] = 0x00_8CEF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_94EF current_address[23:0] = 0x00_BDCC <- 2nd reference next_Rn[23:0] = 0x00_BDCA

ITERATION 3: Rn = 0x00_BDCA, N = 0x00_0004
Rn_reversed[23:0] = 0x00_94EF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_9CEF current_address[23:0] = 0x00_BDCA <- 3rd reference next_Rn[23:0] = 0x00_BDCE

ITERATION 4: Rn = 0x00_BDCE, N = 0x00_0004
Rn_reversed[23:0] = 0x00_9CEF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_A4EF current_address[23:0] = 0x00_BDCE <- 4th reference next_Rn[23:0] = 0x00_BDC9

ITERATION 5: Rn = 0x00_BDC9, N = 0x00_0004
Rn_reversed[23:0] = 0x00_A4EF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_ACEF current_address[23:0] = 0x00_BDC9 <- 5th reference next_Rn[23:0] = 0x00_BDCD

ITERATION 6: Rn = 0x00_BDCD, N = 0x00_0004
Rn_reversed[23:0] = 0x00_ACEF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_B4EF current_address[23:0] = 0x00_BDCD <- 6th reference next_Rn[23:0] = 0x00_BDCB

ITERATION 7: Rn = 0x00_BDCB, N = 0x00_0004
Rn_reversed[23:0] = 0x00_B4EF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_BCEF current_address[23:0] = 0x00_BDCB <- 7th reference next_Rn[23:0] = 0x00_BDCF

ITERATION 8: Rn = 0x00_BDCF, N = 0x00_0004

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Data Types and Addressing Modes Rn_reversed[23:0] = 0x00_BCEF + N_reversed[23:0] = 0x00_0800 ------------------------------------next_Rn_reversed[23:0] = 0x00_84EF <<< not used, would be 9th reference current_address[23:0] = 0x00_BDCF <- 8th reference next_Rn[23:0] = 0x00_BDC8 <<< not used, would be 9th reference

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Chapter 4 Instruction Set Introduction
The DSP56800E and DSP56800EX provide a powerful instruction set, enabling the efficient implementation of digital signal processing and general-purpose computing algorithms. The instruction set is designed around a large register set, with support for byte, word, and long memory accesses. It also has special support for powerful DSC capabilities, such as instructions with data moves that occur in parallel and hardware looping capabilities. The core architecture contains several functional units that operate in parallel: • • • • Data ALU AGU Program controller Bit-manipulation unit

The instruction set is designed to keep each of these units busy in every instruction cycle. Often a single instruction activates more than one functional unit, enabling the parallel execution of operations. This arrangement helps to achieve maximum speed, minimum power consumption, and minimum use of program memory. This chapter provides an introduction to the core instruction set. The instruction set has been divided into functional groups, simplifying how to locate the instructions that implement a particular function. The instructions, their parameters, and their use are summarized at the end of this chapter. For a full description of each instruction, consult Appendix A, “Instruction Set Details.”

4.1 Instruction Groups
The core instruction set can be divided into several general categories that are based on function: • • • • • • • • • Multiplication—integer and fractional multiplication and multiply-accumulate operations. Arithmetic—all arithmetic operations other than multiplication. Shifting—shift and rotate operations. Logic—Boolean logic functions, such as AND, OR, and NOT. AGU arithmetic—address calculation operations. Bit manipulation—instructions for manipulating values at the bit level. Looping—instructions that support iterative loops. Move—data movement operations. Program control—instructions that control execution flow.

Each instruction group is described in the following sections.
Freescale Semiconductor Instruction Set Introduction 4-1

Instruction Set Introduction

4.1.1 Multiplication Instructions
These instructions perform all of the multiplication operations within the data ALU. Optional data transfers (parallel moves) can be specified with some of the multiplication instructions. These transfers allow new data to be pre-fetched for use in instructions that follow, or they allow results calculated by previous instructions to be stored. Multiplication instructions execute in 1 instruction cycle. They may affect one or more of the condition code register bits. Table 4-1 lists the multiplication instructions available on both the DSP56800E core and the DSP56800EX core.
Table 4-1. Multiplication Instructions
Instruction IMAC.L IMACUS IMACUU IMPY.L IMPY.W IMPYSU IMPYUU MAC MACR MACSU MPY MPYR MPYSU Parallel Move? — — — — — — — Yes Yes — Yes Yes — Description Signed integer multiply-accumulate with full precision Unsigned/signed integer multiply-accumulate with full precision Unsigned/unsigned integer multiply-accumulate with full precision Signed integer multiply with full precision Signed integer multiply with integer result Signed/unsigned integer multiply with full precision Unsigned/unsigned integer multiply with full precision Signed fractional multiply-accumulate Signed fractional multiply-accumulate and round Signed/unsigned fractional multiply-accumulate Signed fractional multiply Signed fractional multiply and round Signed/unsigned fractional multiply

Table 4-2 lists additional 32-bit multiplication instructions available on the DSP56800EX core.
Table 4-2. Additional 32-Bit DSP56800EX Multiplication Instructions
Instruction IMAC32 IMPY32 IMPY64 IMPY64UU MAC32 Parallel Move? — — — — — Description Integer multiply-accumulate 32 bits Integer multiply 32 bits x 32 bits → 32 bits Integer multiply 32 bits x 32 bits → 64 bits Unsigned integer multiply 32bits x 32 bits → 64 bits Fractional multiply-accumulate 32 bits x 32 bits → 32 bits

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B — CMP.2 Arithmetic Instructions This group consists of all non-multiplication mathematical instructions.B CLR.W CLR CLR.BP — Freescale Semiconductor Instruction Set Introduction 4-3 . Table 4-3. although instructions that use more complex addressing modes may take longer.BP ADD. The instructions may affect one or more of the condition code register bits. although using register-based operands allows data move operations to be executed in parallel.B ADD.1. These instructions can operate on values located either in registers or in memory. also compare two registers. The arithmetic instructions typically execute in 1 instruction cycle.BP CLR. Arithmetic Instructions Instruction ABS ADC ADD ADD. Table 4-3 on page 4-3 lists the arithmetic instructions. comparison done on 8 bits Compare a byte value from memory with a register. Additional 32-Bit DSP56800EX Multiplication Instructions (Continued) Instruction MPY32 MPY64 Parallel Move? — — Description Fractional multiply 32 bits x 32 bits → 32 bits Fractional multiply 32 bits x 32 bits → 64 bits 4. comparison done on 8 bits Description CMP.W CMP Parallel Move? Yes — Yes — — — — Yes — — — — Yes Absolute value Add long with carry Add two registers Add byte value from memory to register Add byte value from memory to register Add long value from memory (or immediate) to register Add word value from memory (or immediate) to register Clear a 36-bit register value Clear a byte value in memory Clear a byte value in memory Clear a long value in memory Clear a word value in memory or in a register Compare a word value from memory (or immediate) with an accumulator.L CLR.L ADD.Instruction Groups Table 4-2. where the second is always an accumulator. comparison done on 36 bits Compare the byte portions of two registers or an immediate with the byte portion of a register.

BP NEG.BP SUB.L NEG. and N3 registers for the DSP56800EX core—with corresponding shadows Conditionally transfer one or two registers to other registers CMP. R3.L INC. comparison done on 16 bits Decrement byte in memory Decrement an accumulator or a long in memory Decrement upper word of accumulator. or a word in memory Divide iteration Increment byte in memory Increment an accumulator or a long in memory Increment upper word of accumulator. and M01 registers—as well as R2.BP DEC.L Parallel Move? — Description Compare a long value from memory (or an immediate value) with a register.W DIV INC.L SUB. or a word in memory Negate an accumulator Negate byte in memory Negate a long word in memory Negate a word in memory Normalize Round Saturate a value in an accumulator and store in destination Subtract long with carry Subtract two registers Subtract byte value from memory to register Subtract byte value from memory to register Subtract long value from memory to register Subtract word value from memory (or immediate) to register Shift accumulator left and subtract word value Sign extend a byte value in a register and store in destination Sign extend a value in an accumulator and store in destination Swap R0. word register.Instruction Set Introduction Table 4-3. R1. also compare the word portions of two registers.W SUBL SXT.B SUB.BP INC. word register.W NORM RND SAT SBC SUB SUB. R5. also compare the long portions of two registers.W NEG NEG.L SWAP — — Yes — — — Yes Yes — — — — Yes Yes — Yes — — — — Yes — — — Tcc — 4-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .B SXT.L DEC.W — DEC. N. Arithmetic Instructions (Continued) Instruction CMP. comparison done on 32 bits Compare a word value from memory (or immediate) with a register. R4.

Instruction Groups Table 4-3.BP TST.W ZXT.B Parallel Move? Yes Yes — — — — — Description Transfer data ALU register to an accumulator Test a 36-bit accumulator Test byte in memory or in a register Test byte in memory Test an accumulator or a long in memory Test a word in memory or in a register Zero extend a byte value in an register and store in destination Freescale Semiconductor Instruction Set Introduction 4-5 . Arithmetic Instructions (Continued) Instruction TFR TST TST.B TST.L TST.

L.L ROL.W LSL. They generally execute in 1 instruction cycle. Y0.W LSR. ASRR. except for the multi-bit shift instructions (ASLL.W ASR ASR16 ASRAC ASRR. which execute in 2 cycles. 4-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The ASL.3 Shifting Instructions The shifting instructions are used to perform shift and rotate operations within the data ALU.W ROR. and LSRR. Table 4-4 lists the shifting instructions. Table 4-4. and Y1 registers because the condition codes might not be calculated as expected.L).L ASRR. Shifting Instructions Instruction ASL1 ASL16 ASL.W ASLL.W ROL.1. These instructions may affect one or more of the condition code register bits.L LSRR.L.W LSR16 LSRAC LSRR.W Parallel Move? Yes — — — — Yes — — — — — — — — — — — — — — Description Arithmetic shift left (shift register 1 bit) Arithmetic left shift a register or accumulator by 16 bits Arithmetic shift left a 16-bit register (shift register 1 bit) Arithmetic multi-bit shift left a long value Arithmetic multi-bit shift left a word value Arithmetic shift right (shift register 1 bit) Arithmetic right shift a register or accumulator by 16 bits Arithmetic multi-bit shift right with accumulate Arithmetic multi-bit shift right a long value Arithmetic multi-bit shift right a word value Logical shift left a word-sized register Logical shift right (shift word-sized register 1 bit) Logical right shift a register or accumulator by 16 bits Logical multi-bit shift right with accumulate Logical multi-bit shift right a long value Logical multi-bit shift right a word value Rotate left on long register Rotate left on word register Rotate right on long register Rotate right on word register 1.L ROR.W instruction should be used instead.L ASLL.ASL should not be used to shift the 16-bit X0.Instruction Set Introduction 4.

B. Optional data transfers are not permitted with logical instructions. but are aliases to bit-manipulation instructions that perform the same function. No optional data transfers (parallel moves) can be specified with the AGU arithmetic instructions.Note that ANDC.1. Only the CMPA. Arithmetic instructions typically execute in 1 instruction cycle.L.4 Logical Instructions The instructions in this group perform Boolean logic operations.Instruction Groups 4. See Section 4. These instructions execute in 1 cycle. “The ANDC. ORC.W instructions modify the condition code register bits.W.2.L instruction. CMPA.1. Table 4-5. DECTSTA.W EORC NOT. although some instructions can operate on immediate data. Table 4-5 lists the logical instructions.W ANDC CLB EOR.1.L EOR. and NOTC Aliases. and NOTC are not true instructions. TSTA. AGU arithmetic instructions typically use AGU registers for operands. EORC. 4.W ORC Parallel Move? — — — — Yes — — — — — — — Description Logical AND on long registers Logical AND on word registers Logical AND immediate data on word in memory Count leading zeros or ones Logical exclusive OR on long registers Logical exclusive OR on word registers Logical exclusive OR immediate data on word in memory Logical complement on word registers Logical complement on word in memory Logical OR on long registers Logical OR on word registers Logical OR immediate data on word in memory 1. Table 4-6 on page 4-8 lists the AGU arithmetic instructions. which permits a single parallel move.L AND. and TSTDECA.5 AGU Arithmetic Instructions These instructions perform all of the address-calculation arithmetic operations within the address generation unit. although some of the operations may take additional cycles depending on the operand addressing mode. Logical Instructions Instruction1 AND. Freescale Semiconductor Instruction Set Introduction 4-7 . TSTA. ORC.” for more information.L OR. EORC. except with the EOR. TSTA.W.W NOTC OR.

Instruction Set Introduction Table 4-6. aligning SP for long memory accesses before performing the save Arithmetic 1 bit left shift an AGU register Arithmetic 1 bit right shift an AGU register Compare two AGU registers. comparison done on 24 bits Compare two AGU registers.L DECTSTA LSRA NEGA SUBA SXTA.B TSTA.W ZXTA.L TSTA.B ZXTA.L ALIGNSP Description Add register or immediate to AGU register Add to AGU register with 1 bit left shift of source operand Save old value of stack pointer onto stack.W 4-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W TFRA TSTA.W DECA DECA.W TSTDECA. comparison done on 16 bits Decrement an AGU register by one Decrement an AGU register by two Decrement and test an AGU register Logical 1 bit right shift an AGU register Negate an AGU register Subtract register or immediate from AGU register Sign extend a byte value in an AGU register Sign extend a word value in an AGU register Transfer one AGU register to another Test the byte portion of an AGU register Test the long portion of an AGU register Test the word portion of an AGU register Test and decrement the word portion of an AGU register Zero extend a byte value in an AGU register Zero extend a word value in an AGU register ASLA ASRA CMPA CMPA. AGU Arithmetic Instructions Instruction ADDA ADDA.B SXTA.

see Section 4. N. Table 4-9 lists the loop instructions. “AGU Pipeline Dependencies.2. or 4 instruction cycles.5.4.” on page 10-28 for more information. They can operate on any data memory location.1. The carry bit in the status register is the only condition code affected by these instructions. “Program Control Instructions. 3.1.1.7 Looping Instructions The looping instructions are used to perform program looping with minimal overhead. Looping Instructions Instruction DO DOSLC Description Load LC register with unsigned 16-bit loop count and start hardware loop Start hardware loop with signed 16-bit loop count already in LC register Freescale Semiconductor Instruction Set Introduction 4-9 . For similar instructions that change execution flow based on a bitfield test. or M01) can result in pipeline dependencies. see Section 8. called a bitfield.” Table 4-7 lists the bit-manipulation instructions available on both the DSP56800E core and the DSP56800EX core. “Hardware Looping. 4. or register. They all execute in 2. SP. within a word. Table 4-7. Using these instructions can dramatically increase the performance of iterative algorithms. See Section 10. peripheral.” on page 8-18. Table 4-9. For a full discussion of hardware looping and the looping instructions. Bitfield Instructions Instruction BFCHG BFCLR BFSET BFTSTH BFTSTL Bitfield test and change Bitfield test and clear Bitfield test and set Bitfield test for on condition Bitfield test for off condition Description Table 4-8 lists the additional bit-manipulation instruction available on the DSP56800EX core.6 Bit-Manipulation Instructions The bit-manipulation instructions are used to test or modify a set of one or more bits. The core architecture supports efficient hardware looping on a single instruction (using REP) or on a block of instructions (using DO). Additional DSP56800EX Bitfield Instruction Instruction BFSC Bitfield test and set/clear Description Using the bit-manipulation instructions to modify AGU registers (Rn.Instruction Groups 4.9. Table 4-8.

there are also parallel moves that can be used simultaneously with many of the arithmetic instructions.BP MOVE.W Description Move (signed) byte using word pointers and byte addresses Move (signed) byte using byte pointers and byte addresses Move unsigned byte using word pointers and byte addresses Move unsigned byte using byte pointers and byte addresses Move long using word pointers Move (signed) word using word pointers and word addresses (data or program memory) Move unsigned word using word pointers and word addresses (data or program memory) MOVEU.2.1. Move instructions that write an accumulator register to memory or a peripheral can also automatically saturate. See Section 10.5.3.L MOVE. 4-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .” Table 4-10 lists the move instructions. SP.B MOVEU.9 Program Control Instructions The program control instructions include branches. Looping Instructions (Continued) Instruction ENDDO REP Description Terminate current hardware DO loops Repeat immediately following instruction 4. N. jumps.8 Move Instructions The move instructions transfer data between core registers and memory or peripherals. The parallel moves appear in Table 4-43 on page 4-49 and Table 4-44 on page 4-50 and are discussed in detail in Section 3.4. conditional branches.BP MOVEU. “Instruction Set Details. or M01) with a MOVE instruction can result in an execution pipeline stall.W Writing AGU registers (Rn.Instruction Set Introduction Table 4-9. Table 4-10. conditional jumps. and other instructions that affect the program counter and software stack.1. or between two memory or peripheral locations.B MOVE. limiting the value written.” on page 3-11 and in Appendix A. “Parallel Moves.” on page 10-28 for more information. Also included in this instruction group are the STOP and WAIT instructions. which place the DSC chip in a low-power state. Table 4-11 lists the change-of-flow instructions. “AGU Pipeline Dependencies. 4. Move Instructions Instruction MOVE. In addition to the following move instructions.

“Programming Considerations. Program Control and Change-of-Flow Instructions Instruction Bcc BRA BRAD BRCLR BRSET BSR FRTID ILLEGAL Jcc JMP JMPD JSR RTI RTID RTS RTSD SWI SWI #<0–2> SWILP Branch conditionally Branch Delayed branch Branch if selected bits are clear Branch if selected bits are set Branch to subroutine Delayed return from fast interrupt Generate an illegal instruction exception Jump conditionally Jump Delayed jump Jump to subroutine Return from interrupt Delayed return from interrupt Return from subroutine Delayed return from subroutine Software interrupt at highest priority level Software interrupt at specified priority level Software interrupt at lowest priority level Description See Section 7.” on page 7-6 for other program control instructions that can be synthesized from existing core instructions. see Section 4.Instruction Groups Table 4-11. For information on the delayed program control instructions (BRAD. Miscellaneous Program Control Instructions Instruction DEBUGEV DEBUGHLT NOP STOP Generate debug event Enter debug mode No operation Stop processing (lowest power standby) Description Freescale Semiconductor Instruction Set Introduction 4-11 . FRTID.5. Table 4-12. JMPD. “Delayed Flow Control Instructions.” Table 4-12 lists the miscellaneous program control instructions.3. and RTSD). RTID.

a one’s-complement of the mask value is used when remapping to the BFCLR instruction.X:$400.Instruction Set Introduction Table 4-12. For the NOTC instruction. useful instruction mnemonics that are actually aliases to other instructions. the instruction appears as a BFSET instruction. Miscellaneous Program Control Instructions (Continued) Instruction WAIT Description Wait for interrupt (low power standby) 4. They are mapped as indicated in Table 4-13.2 Instruction Aliases The DSC core assembler provides a number of additional. using the bit-manipulation instructions. Each of these instructions is mapped to one of the core instructions and dis-assembles as such. which performs the same operation. a logical OR operation is performed on an immediate value with a location in memory. In Example 4-1.DST #xxxx. the core assembler provides the following operations: • • • • ANDC—logically AND a 16-bit immediate value with a destination EORC—logically exclusive OR a 16-bit immediate value with a destination NOTC—take the logical one’s-complement of a 16-bit destination ORC—logically OR a 16-bit immediate value with a destination These operations are not new instructions. To simplify implementing these operations. and NOTC Aliases The core instruction set does not support logical operations using 16-bit immediate data. It is possible to achieve the same result.DST #$FFFF. but aliases to existing bit-manipulation instructions.DST #xxxx.DST Note that for the ANDC instruction. Table 4-13. 4-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 4.X:$400.2. Example 4-1. EORC.1 The ANDC. If the assembled code is later dis-assembled.DST #xxxx. however. Set all bits of lower byte in X:$400 The assembler translates this instruction into BFSET #$00FF. Logical OR with a Data Memory Location ORC #$00FF. all bits in the 16-bit mask are set to one.DST DST #xxxx. ORC.DST #xxxx. Aliases for Logical Instructions with Immediate Data Remapped DSP56800E/ DSP56800EX Instruction BFCLR BFCHG BFCHG BFSET Desired Instruction Operands Operands ANDC EORC NOTC ORC #xxxx.

These remapping functions are discussed in the following sections.2. the core assembler examines the effective address calculation to see if the operand can be mapped to one that uses a simpler addressing mode.FFF FFF.FFF FF. Specifically. 4.Rn #xxxxxx. Instructions with Alternate Syntax Standard Syntax Operation ADDA Operands #xxxx.B instructions. 4.B SXT.Rn #xxxxxx.L ZXT.Rn ASL16 ASLA ASR16 LSR16 SAT SXT. SAT.Rn.L Alternate Syntax Operation ADDA Operands #xxxx.Rn #xxxxxx. the instruction appears with the standard syntax.FFF Rn.Rn.Rn FFF Rn FFF FFF FF FFF FF FFF Note that the alternate syntax is merely an alias to the regular instruction syntax.2 Instruction Operand Remapping The core assembler performs a few additional mapping functions. allow different source and destination register operands to be specified.Rn.FFF FFF. however.FFF ASL16 ASLA ASR16 LSR16 SAT SXT.L ZXT.FFF FF. when the assembler detects occurrences of the following addressing modes.L #xxxx. the core assembler provides an alternate syntax in which the operand is only specified once.Rn FFF.B FFF. For situations when they are the same.2 Addressing Mode Remapping When an instruction operand uses the index-by-6-bit-displacement or index-by-3-bit-displacement addressing modes. such as the ADDA.2.B SXT. When dis-assembled.Instruction Aliases 4. Often. Table 4-14. either to allow an alternative syntax for certain instructions or to simplify the addressing mode used by an instruction. it remaps them: • • X:(SP–xx) where the value of the 6-bit offset is “0” X:(SP–x) where the value of the 3-bit offset is “0” Freescale Semiconductor Instruction Set Introduction 4-13 .Rn #xxxxxx.Rn ADDA. with the register operand repeated. the source and destination registers are the same.B ADDA.FFF FFF.1 Duplicate Operand Remapping Several instructions.2. Table 4-14 lists the standard and duplicate-operand syntaxes for these instructions.Rn. and ZXT.Rn #xxxx.2.2.

reducing the number of delay-slot cycles that are available for instructions by the same number of cycles. Due to the design of the execution pipeline. where each delay slot consists of 1 program word. The additional cycles required to flush the pipeline are reflected in the total cycle count for each change-of-flow instruction. are shown in Table 4-15. “Pipeline Dependencies and Interlocks.Instruction Set Introduction In both cases. Table 4-15.3 Delayed Flow Control Instructions One particular class of instructions merits additional attention: the delayed flow control instructions. See Section 10.3.4. Note the BRA instruction that is used to return to the top of the loop. then each unused delay slot must be filled with an NOP instruction. The number of instructions is limited by the number of delay slots that are available with a given delayed instruction. 4. Example 4-2 shows a code fragment that reverses the contents of a buffer in memory that starts at the address contained in R0. These instructions are designed to increase throughput by eliminating execution cycles that are wasted when program flow changes. the pipeline stalls for 2 cycles while control is transferred back to the top of the loop.” on page 10-26 for more information. and the number of delay slots for each. The delayed instructions. the operand addressing mode is remapped to the X:(SP) addressing mode.1 Using Delayed Instructions The delayed instructions use the execution pipeline more efficiently by executing one or more of the instructions following the delayed instruction before execution is switched to the target address. The program controller stops fetching instructions at the current location and begins to fill the pipeline from the target address. 4-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The execution pipeline is said to stall while this switch occurs. 4. If a pipeline dependency occurs due to instructions executed in the delay slots. Delayed Instructions Delayed Instructions BRAD JMPD RTID RTSD FRTID Number of Delay Slots 2 2 3 3 2 The delay slots following each of these instructions must be filled with exactly the same number of instruction words as there are delay slots. If not all delay slots can be filled with valid instructions. the appropriate amount of interlock cycles are inserted by the core. A special group of instructions referred to as “delayed” instructions provide a mechanism for executing useful tasks during these normally wasted cycles. An instruction that affects normal program flow (such as branch or jump instruction) requires 2 or 3 additional instruction cycles to flush the execution pipeline.

SWI #0.. .. HWS.R1 . .X0 MOVE. LA. WAIT SWAP SHADOWS Move instructions that access program memory Any move clear or test instruction that accesses the SP.. subsequent code. or OMR registers The BFCHG.X:(R1)BRA SWAP_LOOP DONE . . 4. RTS. check if done yet if R0 >= R1. .X0 MOVE. Bcc. ENDDO JMP. we’re done perform the swap " " " branch back to top of loop pipeline stalls for 2 cycles #buflen-1.LC. .R0. JMPD.B. . check if done yet if R0 >= R1. . LA2.. put end of buffer in R1 A more efficient way to implement the reversal algorithm is to use the BRAD instruction instead of BRA. By using BRAD. Jcc.W X:(R0)+. and BFSET instructions (and the aliases to them: ANDC. or OMR registers ALIGNSP Tcc Freescale Semiconductor Instruction Set Introduction 4-15 . HWS.M01. Code Fragment with Regular Branch ADDA SWAP_LOOP CMPA R0. DOSLC. ..R1 BLE DONE BRAD SWAP_LOOP MOVE. BSR.W instructions during the 2 cycles that would normally be wasted due to the branch. LA. N3. EORC.W X0. or TSTDECA.W with the following operands: ADD. Example 4-3. FRTID ADD.2 Delayed Instruction Restrictions Not all instructions are allowed in delay slots. LC2.R0. SWI #1. SWI #2. subsequent code. LC2.W) that access the SP. we’re done delayed branch to top of loop swap occurs in the delay slots! #buflen-1. or OMR registers The clear or test instructions (except TSTA. The following instructions cannot be executed in a delay slot. RTI.Delayed Flow Control Instructions Example 4-2.. M01. TSTA.3. TSTA. put end of buffer in R1 Similar strategies can be used on subroutines and interrupt handlers. Code Fragment with Delayed Branch ADDA SWAP_LOOP CMPA R0. . BRA. NOTC. Example 4-3 on page 4-15 shows BRAD being used.W X0. RTSD.W.N3.R1 . • • • • • • • • • • • • DO.R1 BLE DONE MOVE. BRAD. RTID. DECTSTA. LC. SWI STOP. . and ORC) that access the SP.W X:(R0)+.L.LA2. The assembler detects these instructions and flags them as illegal.X:(SP-xx) SWILP. we can execute the two MOVE. LA2. SR. . BFCLR. M01. . where employing the RTSD and RTID instructions can eliminate the wasted cycles associated with the RTS and RTI instructions.W EEE. with the code rearranged appropriately.LA. JSR. REP.X:(R1)DONE . HWS. LC. SR. SR..LC2.. N3.

ROR. R1.4. ROL. instructions that update the status register are not allowed.W or TST.4. See Section 9.3. or N registers Any two instructions in the delay slots (including any hardware interlocks) with a total execution time greater than 3 cycles 4.3 Delayed Instructions and Interrupts Instructions that are executed in delay slots are not interruptible. 4. Sample Instruction Summary Table Operation MAC Operands (±)FFF1.L.W Any instruction in which the SP register is used as an address pointer.L. The number of instruction cycles that each operation takes to execute and the number of program words that it occupies is also listed. it is easy to determine the appropriate instruction for a given application.L. ROR. SBC. • ADC.Instruction Set Introduction • DEBUGHLT. no interrupts are serviced.L. The general form appears in Table 4-16.W on either the R0. ROL.FFF1. and ORC instruction aliases) that operate on the R0. BFCLR. R1. ROR. “Non-Interruptible Instruction Sequences. and addressing modes for each instruction. NOTC.3. EORC. which appear in the following list. ROL. R1.4 Instruction Set Summary This section presents the entire core instruction set in tabular form. supported operands.1 Using the Instruction Summary Tables The entries in the instruction summary tables give the name of the operation (the instruction mnemonic).W. and flags them as illegal. Table 4-16.” on page 9-10 for more information. From the time that execution begins for a delayed instruction to the end of execution for the instruction that occupies the last delay slot.W In addition to all of the preceding restrictions. or N register BFCHG. in an addressing mode. The tables show the instruction mnemonics. The assembler dis-allows the following: • • • • • • ADC. The assembler detects these cases. ROL. the instructions that can be in the delay slots for the FRTID instruction are further limited. With these tables. the legal operands. and a brief description of the operation. Because this instruction restores the value of the status register. 4. or in an AGU calculation Move instructions where the source or destination is the R0. ROR. or N registers CLR.FFF C 1 W 1 Comments Fractional multiply-accumulate. cycle and word counts. Any interrupt that occurs during this time is latched as pending and is not serviced until after the final delay-slot instruction. DEBUGEV There are additional restrictions on instructions that are allowed in delay slots for the RTID instruction. SBC. multiplication result optionally negated before accumulation 4-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W. or BFSET instructions (including the ANDC.

we can determine that the following are valid core instructions: MAC MAC MAC X0.Y0. MACR.Y0 X:(R1)+N. The Y0 register cannot be a destination for the second memory read. Table 4-17 shows the register sets that are available for the most important move instructions. not three. and post-update–with–N3 addressing modes are allowed. we see that the instructions in Example 4-4 are allowed. A + X0*Y0 -> A . or.4.” The summary tables and the notation definitions make it possible to determine whether or not a particular instruction is legal. which is used to describe a set of registers.Y1. Example 4-4. Register fields that are used in conjunction with AGU move instructions are listed in Table 4-18 on page 4-19. the difference is noted. Based on the entries in the summary tables for the MOVE.A .Y1.A -X0. The following tables outline the notation that is used to specify legal registers.X0 X:(R3)+N. Freescale Semiconductor Instruction Set Introduction 4-17 .W MACR X0. post-decrement. Consider the instruction in Example 4-5.A ADD Y0.X0 The instruction summary tables can also be used to determine if a particular instruction is not allowed. The post-update–by–N addressing mode is not allowed for the second memory read. using shorthand notation. the multiplication result is negated. This notation. we know that this instruction is invalid for the following reasons: • • • • • • The ADD instruction only takes two operands. for example.A X:(R2)-.Y1 X:(R1)+N.Instruction Set Summary The operands are specified using the register and immediate values that are allowed.2. as well as the information contained in Table 4-44. is explained in Section 4. and ADD instructions. The pointer R2 is not allowed for the first memory read. For the MAC instruction in Table 4-16.4. The X0 register cannot be a destination for the first memory read. A + X0*Y0 -> A . when there are a number of options. Whenever the supported set of registers varies due to whether the set is the source or destination of an operation. The post-decrement addressing mode is not available for the first memory read. Table 4-44 on page 4-50 shows all the registers and addressing modes that are allowed in a dual read instruction. Invalid Instruction ADD X0.X0 X:(R3)+. Valid Instructions MOVE. A . 4.Y0.2 Register Field Notation There are many different register fields that are used within the instruction summary tables.A +X0.Y0 Using the information in Table 4-33 on page 4-31 and Table 4-44 on page 4-50. “Register Field Notation.B X:(R0)+. If a “–” is specified.Y0. only the post-increment.X0 X:(R3)-. one of the core’s parallel move instructions.Y0 X:(R3)+.(X0*Y0) -> A The (+) in the operand entry for MAC indicates that an optional “+” or “–” sign can be specified before the input register combination. Example 4-5.

HHHH (source) A1. B.” on page 5-39 and Section 5. C1. C1. HHH. Y0. C. This field is identical to the FFF1 field. N Seven data ALU and seven AGU registers used as source registers. D Y R0–R5. HHHH. Writing word data to the 32-bit Y register clears the Y0 portion. Table 4-17.2. Five data ALU registers—four 32-bit MSP:LSP portions of the accumulators and one 32-bit Y data register (Y1:Y0) used as source register. B. B.” on page 5-6 for more information. Used for long memory accesses. Y1 Comments Seven data ALU registers—four 16-bit MSP portions of the accumulators and three 16-bit data registers used as source registers. N A. C. N A. Note the usage of A.L (source) A10. C10. Also see dddd. Y0. B1. Used for long memory accesses. and D1. Writing word data to the 32-bit Y register clears the Y0 portion. D1 X0. Y1 Seven data ALU registers—four 16-bit MSP portions of the accumulators and three 16-bit data registers used as destination registers. This table also shows the notation that is used for AGU registers in AGU arithmetic operations. HHHH. D10 Y R0–R5. B. C.1. N A10. 4-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . D Y X0. “Data Limiter.Instruction Set Introduction In some cases. Y0. and D1. The most commonly used fields in this table are Rn and RRR. Used for long memory accesses. B.8. C. C. B10. C1. D1 X0. C. C10. Note the usage of A.L. C1.L (destination) A.L (destination) Table 4-18 shows the register sets that are available for use for pointers in address-register-indirect addressing modes. D10 Y HHHH (destination) Seven data ALU and seven AGU registers used as destination registers. the notation that is used for specifying an accumulator determines whether or not saturation is enabled when the accumulator is being used as a source in a move or parallel move instruction. Register Fields for General-Purpose Writes and Reads Register Field HHH (source) Registers in This Field A1. Used for long memory accesses. B10. “Accessing the Accumulator Registers. Refer to Section 5. B.L (source) Five data ALU and seven AGU registers used as source registers.L. Y0. and D. Five data ALU and seven AGU registers used as destination registers. B1. D Y Five data ALU registers—four 32-bit MSP:LSP portions of the accumulators and one 32-bit Y data register (Y1:Y0) used as destination register. HHH (destination) A. D Y X0. Also see dddd. B1. B1. and D. HHH. Note the usage of A1. Y1 R0–R5. Y1 R0–R5. Note the usage of A1.

The most commonly used fields in this table are EEE and FFF. B. Y0. Note the usage of A1. R2. B1. D DD F X0. and three 16-bit data registers accessible during data ALU operations. C. but indicates that the MSP portion of the accumulator is in use. Y0. B Three 16-bit data registers. Y1 A. Table 4-19. Data ALU Registers Register Field FFF Registers in This Field A. Y0. D. D1 X0. This field is similar to FFF but is missing the 32-bit Y register. one 32-bit long register Y. C. Y Four 36-bit accumulators and one 32-bit long register accessible during data ALU operations. B1. R3 N3 Comments Eight AGU registers available as pointers for addressing and address calculations Seven AGU registers available as pointers for addressing and as sources and destinations for move instructions Four pointer registers available as pointers for addressing One index register available only for the second access in dual parallel read instructions Address modifier register Fast interrupt return register RRR Rj N3 M01 FIRA M01 FIRA Table 4-19 shows the register sets that are available for use in data ALU arithmetic operations. and D1. Used for instructions where Y is not a useful operand (use Y1 instead). Y1 Seven data ALU registers—four accumulators and three 16-bit data registers accessible during data ALU operations. fff A. D Y X0. C. C. Four 36-bit accumulators accessible during data ALU operations.Instruction Set Summary Table 4-18. Two 36-bit accumulators accessible during parallel move instructions and some data ALU operations. B. Y0. This field is identical to the HHH (source) field. C1. Seven data ALU registers—four 16-bit MSP portions of the accumulators and three 16-bit data registers accessible during data ALU operations. Address Generation Unit (AGU) Registers Register Field Rn Registers in This Field R0–R5 N SP R0–R5 N R0. B. Y1 Comments Eight data ALU registers—four 36-bit accumulators. Y1 A1. D X0. FFF1 FF A. C1. R1. It is very similar to FFF. EEE A. B. Freescale Semiconductor Instruction Set Introduction 4-19 .

D2 Y0. not as a source. R2. B2. which can also access the stack via the MOVE. OMR. B1. SR LA. Additional Register Sets for Move Instructions Register Field DDDDD Registers in This Field A. LC. D0 Extension and LS portion of the C and D accumulators. D2. R2. The registers in this field and HHHHH combine to make the DDDDD register field. A1. and D0 registers are not available within this field. not as a source. R5. C1 D. HHHHH A. Note that the C2. SP M01. It contains the contents of the HHHHH and SSSS register fields. X0 R0. C0.Instruction Set Introduction Table 4-19. N3 OMR. Table 4-20 shows additional register fields that are available for move instructions. B2. X0 SP. SP M01. C0. LC. R1. B1. D1 Y Y1. B1 Comments The 16-bit MSP portion of two accumulators accessible as source operands in parallel move instructions. This set designates registers that are written with unsigned values when written with word values. R5.L A2. See the dd register field for these registers SSSS R0. SR Miscellaneous set of registers that can be placed onto or removed from the stack 32 bits at a time. LC HWS dd C2. SR dddd. N3. R3 R4. Y0. B0 C. A0 B. Y is permitted only as a destination. B0 C. N3 LA. A1. Table 4-20. Writing word data to the 32-bit Y register clears the Y0 portion. Y1. Comments This table lists the CPU registers. D1 Y Y1. LA. 4-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Data ALU Registers (Continued) Register Field F1 Registers in This Field A1. C2. This list supplements the registers in the HHHH. D2. R1. HWS. B2. A2. A2. LA2. N. HWS OMR. X0 This set designates registers that are written with signed values when written with word values. C1 D. N. LC2. The registers in this field and SSSS combine to make the DDDDD register field. Y0. M01. Y is permitted only as a destination. A0 B.L field.L instruction. R3 R4. This register set supplements the DDDDD field.

In these tables.4 Instruction Summary Tables A summary of the entire core instruction set is presented in this section in tabular form. Table 4-21.Instruction Set Summary 4.3 Immediate Value Notation Immediate values. are presented in the instruction set summary using the notation presented in Table 4-21. There are separate fields for sources and destinations of move instructions. See Table 4-43 on page 4-49 and Table 4-44 on page 4-50 for information on parallel moves.4. Immediate Value Notation Immedate Value Field <MASK16> <MASK8> <OFFSET18> <OFFSET22> <OFFSET7> <ABS16> <ABS19> <ABS21> 16-bit mask value 8-bit mask value 18-bit signed PC-relative offset 22-bit signed PC-relative offset 7-bit signed PC-relative offset 16-bit absolute address 19-bit absolute address 21-bit absolute address Description 4. Table 4-22. Move Byte Instructions—Byte Pointers Operation MOVE. each instruction has two fields: • • C—Number of clock cycles that are required to execute the instruction W—Number of program words that are required by the instruction Descriptions of the parallel move instruction syntax (for those operations that support them) are located at the end of this section. including absolute and offset addresses. operands. the instructions are broken into several different categories and then listed alphabetically. and any relevant comments. The tables specify the operation.BP Source X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) X:(RRR+xxxxxx) X:xxxx X:xxxxxx Destination HHH C 1 W 1 Comments Move signed byte from memory HHH HHH HHH HHH HHH 2 2 3 2 3 1 2 3 2 3 Address = Rn+N Unsigned 16-bit offset 24-bit offset Unsigned 16-bit absolute address 24-bit absolute address Freescale Semiconductor Instruction Set Introduction 4-21 .4. In addition.

B HHH HHH HHH HHH HHH Destination HHH HHH HHH HHH HHH HHH HHH HHH X:(RRR+x) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–x) X:(SP) C 2 3 1 2 2 3 2 1 2 2 3 2 1 W 2 3 1 1 2 3 1 1 1 2 3 1 1 Comments Signed 16-bit offset 24-bit offset Pointer is SP x: offset ranging from 0 to 7 Signed 16-bit offset 24-bit offset x: offset ranges from 1 to 8 Pointer is SP x: offset ranges from 0 to 7 Signed 16-bit offset 24-bit offset x: offset ranges from 1 to 8 Pointer is SP 4-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .B Source X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP) MOVEU.BP HHH Destination HHH C 1 W 1 Comments Move unsigned byte from memory HHH HHH HHH HHH HHH X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) X:(RRR+xxxxxx) X:xxxx X:xxxxxx 2 2 3 2 3 1 1 2 3 2 3 1 Address = Rn+N Unsigned 16-bit offset 24-bit offset Unsigned 16-bit absolute address 24-bit absolute address Move signed byte to memory HHH HHH HHH HHH HHH 2 2 3 2 3 1 2 3 2 3 Address = Rn+N Unsigned 16-bit offset 24-bit offset Unsigned 16-bit absolute address 24-bit absolute address Table 4-23. Move Byte Instructions—Byte Pointers (Continued) Operation MOVEU. Move Byte Instructions—Word Pointers Operation MOVE.Instruction Set Introduction Table 4-22.B X:(RRR+x) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–x) X:(SP) MOVE.BP Source X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) X:(RRR+xxxxxx) X:xxxx X:xxxxxx MOVE.

L X:(Rn) X:(Rn)+ X:(Rn)– X:(SP)+ 2 2 3 2 2 3 1 1 2 3 1 2 3 1 dddd.L X:(Rn+N) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:xxxx X:xxxxxx 2 2 3 2 2 3 1 2 3 1 2 3 Freescale Semiconductor Instruction Set Introduction 4-23 .L C 1 W 1 Comments Move signed 32-bit long word from memory.L HHHH.Instruction Set Summary Table 4-24.L HHHH.L Source X:(Rn) X:(Rn)+ X:(Rn)– X:(SP)– Destination HHHH.L HHHH.L HHHH.L Address = Rn+N Signed 16-bit offset 24-bit offset Unsigned 6-bit offset.L HHHH. Move Long Word Instructions Operation MOVE. SP not permitted in dddd.L HHHH. does not modify bits 14–10 in SR Address = Rn+N Signed 16-bit offset 24-bit offset Unsigned 6-bit offset.L HHHH. note that Rn includes SP dddd. left shifted 1 bit Unsigned 16-bit address 24-bit address Move signed 32-bit long word to memory. left shifted 1 bit Unsigned 16-bit address 24-bit address HHHH.L HHHH.L HHHH. note that Rn includes SP X:(Rn+N) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:xxxx X:xxxxxx MOVE.L 1 1 Push 32 bits onto stack.L HHHH.L HHHH.L 1 1 Pop 32 bits from stack.L HHHH.

A1. Y0 A. C. Y1. B1 X0. Y0 A.W X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:xxxx X:xxxxxx X:<<pp X:aa SSSS SSSS SSSS SSSS RRR SSSS SSSS RRR RRR 2 1 2 3 2 2 3 1 1 1 1 2 3 1 2 3 1 1 Address = Rn+N Post-update of Rn register Signed 16-bit offset 24-bit offset Unsigned 6-bit offset Unsigned 16-bit address 24-bit address 6-bit peripheral address 6-bit absolute short address 4-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . C. B.W Source X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+x) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:xxxx X:xxxxxx X:<<pp Destination HHHHH C 1 W 1 Comments Move signed 16-bit integer word from memory HHHHH HHHHH HHH HHHHH HHHHH HHH HHHHH HHHHH X0.Instruction Set Introduction Table 4-25. B. Y1. B1 (parallel) 2 1 2 2 3 2 2 3 1 1 1 1 2 3 1 2 3 1 Address = Rn+N Post-update of Rn register x: offset ranging from 0 to 7 Signed 16-bit offset 24-bit offset Unsigned 6-bit offset Unsigned 16-bit address 24-bit address 6-bit peripheral address X:aa 1 1 6-bit absolute short address 1 SSSS 1 1 1 Refer to Table 4-44 on page 4-50. Move Word Instructions Operation MOVE. A1. Move signed 16-bit integer word from memory MOVEU.

W Source DDDDD Destination X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+x) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:xxxx X:xxxxxx X:<<pp C 1 W 1 Comments Move signed 16-bit integer word to memory DDDDD DDDDD HHH DDDDD DDDDD HHHH DDDDD DDDDD X0. Y0 A. N X0. Y0 A. Y1. Move Word Instructions (Continued) Operation MOVE. A1. Y1. C.Instruction Set Summary Table 4-25. C. B. A1. B1 R0–R5. B. N 2 1 2 2 3 2 2 3 1 1 1 1 2 3 1 2 3 1 Address = Rn+N Post-update of Rn register x: offset ranging from 0 to 7 Signed 16-bit offset 24-bit offset Unsigned 6-bit offset Unsigned 16-bit address 24-bit address 6-bit peripheral address X:aa 1 1 6-bit absolute short address Freescale Semiconductor Instruction Set Introduction 4-25 . B1 R0–R5.

MOVEU. x: offset ranges from 0 to 7 X:xxxx MOVEU.B1 X:(RRR+x) X:(SP) X:(SP–x) MOVE. and MOVE. The upper 15 bits of the address select the appropriate word location in memory.B instructions. Memory-to-Memory Move Instructions Operation MOVE. RRR used as a byte pointer 16-bit absolute address x: offset ranges from 0 to 7 Signed 16-bit offset x: offset ranges from 1 to 8 Signed 16-bit offset Move word from one memory location to another.B1 MOVE.BP.B.Instruction Set Introduction Table 4-26.W X:(Rn+xxxx) X:(Rn+x) X:xxxx X:xxxx X:xxxx X:xxxx X:xxxx X:xxxx 3 3 2 3 3 3 3 2 2 2 3 2 X:(SP–xx) X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+xxxx) X:xxxx MOVE. and the LSB selects the upper or lower byte of that word.The destination operand X:xxxx is always specified as a byte address for the MOVE.BP1 Source X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) Destination X:xxxx C 2 W 2 Comments Move byte from one memory location to another. 4-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L X:(SP–xx) X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn+xxxx) X:xxxx X:xxxx X:xxxx 3 2 2 2 X:xxxx X:xxxx X:xxxx X:xxxx X:xxxx X:xxxx 3 2 3 3 3 2 2 2 3 3 2 2 Signed 16-bit offset 16-bit absolute address Move long from one memory location to another X:xxxx X:xxxx X:xxxx 3 3 3 2 3 3 Signed 16-bit offset 16-bit absolute address 1. RRR used as a byte pointer X:xxxx X:xxxx 3 3 2 3 RRR used as a byte pointer Unsigned 16-bit offset.

Use MOVEU. D2. Sign extend the 16-bit immediate data to 36 bits when moving to an accumulator.L 2 2 #xxxxxxxx HHH. sign extend to 24 bits when moving to an AGU register. upper bits are sign extended). Move 16-bit immediate data to the first 64 locations of X data memory. Signed 16-bit immediate data. LSP portion is set to 0). Move unsigned 24-bit immediate value to AGU register.L 3 3 Move signed 32-bit immediate data to a 32-bit accumulator. Signed 5-bit integer data (data is put in the lowest 5 bits of the word portion of the register.W Source #<–64.63> Destination HHHH C 1 W 1 Comments Signed 7-bit integer data (data is put in the lowest 7 bits of the word portion of any accumulator. Signed 7-bit integer data (data put in the low portion of the word). X:aa 2 2 X:xxxx X:xxxxxx MOVEU. Move to 32-bit memory location. #xxxxxxxx #<–16. D0 registers.L 4 1 4 1 #xxxx HHHH. upper 8 bits and extension register are sign extended. X:xxxx 2 2 #xxxx HHHHH dd X:(Rn) X:(Rn+xxxx) X:(SP–xx) X:<<pp 2 2 2 3 2 2 2 2 2 3 2 2 Move 16-bit immediate data to the one of 64 locations in X data memory—peripheral registers.Instruction Set Summary Table 4-27.W for moves to the AGU with unsigned 16-bit immediate data. Immediate Move Instructions Operation MOVE.L #xxxx #xxxx SSSS X:xxxx 3 4 2 3 3 4 2 3 Unsigned 16-bit immediate data. C0. #xxxxxx RRR 3 3 Freescale Semiconductor Instruction Set Introduction 4-27 . Sign extend 16-bit value and move to 32-bit memory location.15> X:xxxx HHH. Move to C2.W MOVE.

LS.W Source DDDDD HHH MOVEU. Table 4-29.L instructions for data ALU registers (see Table 4-33 on page 4-31) and the TFRA instruction for AGU registers (see Table 4-37 on page 4-42). Move unsigned word to register. Move signed word to register.W HWS.L 1 1 Move pointer register to data ALU register. Conditional Register Transfer Instructions Data ALU Transfer Operation Source Tcc1 DD Destination F Source Destination 1 1 Conditionally transfer one register AGU Transfer C W Comments (No transfer) A B DD B A F R0 (No transfer) (No transfer) R1 Conditionally transfer one data ALU register and one AGU register A B B A R0 R0 R1 R1 1. 4-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . MOVE. Zero extend the 24-bit value contained in the RRR register. MOVEU.Instruction Set Introduction Table 4-28. N.The Tcc instruction does not support the HI. R1. and M01 registers with their shadow registers. Register-to-Register Move Instructions Operation MOVE. NOTE: Additional register-to-register move instructions include the TFR and SXT.HWS is not supported. and NR conditions.L RRR RRR HHH.W DDDDD Destination HHHHH RRR SSSS 1 1 C 1 W 1 Comments Move signed word to register.L HHH. NN. SWAP SHADOWS 1 1 This instruction swaps the value in the R0. It is the only instruction that accesses the shadow registers.

multiplication result optionally negated before accumulation. A.FFF1.Y0.FFF1. A1. C.L IMPY. Y0 A.Y1. Refer to Table 4-43 and Table 4-44.FFF B1.FFF Y0.FFF C1. C. Integer 16 × 16 multiply with 32-bit result. B.FFF A1.Y0. Move Word Instructions—Program Memory Operation1 MOVE.Y0.FFF (parallel) Refer to Table 4-43 and Table 4-44. Note: Assembler also accepts first two operands when they are specified in opposite order.Y0. Refer to Table 4-43 and Table 4-44.FFF (parallel) MPY FFF1.FFF C1. B1 R0–R5.FFF Y0. Y1.Y1. multiplication result optionally negated before addition.W P:(Rj)+ P:(Rj)+N X0.FFF C 1 1 1 W 1 1 1 Comments Integer 16 × 16 multiply-accumulate with 36-bit result. Y0.FFF –B1.FFF –A1.Y0.FFF –Y0.Y0. Fractional multiply where one operand negated before multiplication. When the destination is the Y register or an accumulator.FFF –Y1. 1 1 Fractional multiply-accumulate. Table 4-31. Y1.X0. B.Y1.FFF –Y0. A1 or B1 RRR C 5 W 1 Comments Read signed word from program memory MOVEU.These instructions are not allowed when the XP bit in the OMR is set (that is.W Source P:(Rj)+ P:(Rj)+N Destination X0.X0.FFF –Y1.FFF1. Note: Assembler also accepts first two operands when they are specified in opposite order. MAC (parallel) MACR (±)FFF1.fff Y1.FFF1.Y0.FFF Y1.X0.Y0. 1 1 Fractional MAC with round.W Operands FFF1.FFF –C1. N 5 1 Read unsigned word from program memory MOVE.FFF1.FFF –C1.Y1.X0. Freescale Semiconductor Instruction Set Introduction 4-29 . the LSP portion is unchanged by the instruction.L IMPY.Instruction Set Summary Table 4-30. when the instructions are executing from data memory). Data ALU Multiply Instructions Operation IMAC.W P:(Rj)+ P:(Rj)+N 5 1 Write word to program memory 1.fff FFF1. 1 1 Fractional multiply. Integer 16 × 16 multiply with 16-bit result.FFF (±)FFF1.

Y A1.3.A1.X0.A0.FFF –C1. result rounded.Y C0.B1.FFF1. This instruction is described in more detail in Section 5. The result is rounded.FFF –Y0.FFF –A1.D1. Refer to Table 4-43 and Table 4-44.FFF –B1.FFF –Y1.Y A0.C0.Y B0.Y1.A1.” on page 5-32.C0.D0.Y C0.D1.Y0.Instruction Set Introduction Table 4-31.Y1.5.Y B1.Y B0.Y C1. “Multi-Precision Integer Multiplication.D1. Data ALU Extended-Precision Multiplication Instructions Operation IMACUS Operands A0. “Multi-Precision Integer Multiplication.B1.D1.D1.” on page 5-32. “Multi-Precision Integer Multiplication.3.Y0.C0.5.Y B0.C1.Y C1. 4-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .D1.Y A0.FFF –Y1.Y A0.B0. Data ALU Multiply Instructions (Continued) Operation MPYR Operands FFF1.C1.Y A0. Note: Assembler also accepts first two operands when they are specified in opposite order.Y C 1 W 1 Comments Integer 16 × 16 multiply accumulate: F0 (unsigned) × F1 (signed).FFF –Y0.5.Y0.D0. IMPYSU 1 1 Integer 16 × 16 multiply: F1 (signed) × F0 (unsigned).Y A0.Y B1.Y B0.Y C0. Table 4-32.C1.3.C1.Y A0. This instruction is described in more detail in Section 5.Y A1.FFF –C1.Y C0. This instruction is described in more detail in Section 5.Y A0.” on page 5-32.C1. IMACUU 1 1 Integer 16 × 16 multiply accumulate: F0 (unsigned) × F1 (unsigned).Y0.D0.FFF (parallel) C 1 W 1 Comments Fractional multiply.C1.Y A1.Y A1.X0. Fractional multiply where one operand negated before multiplication.

FF A0. “Multi-Precision Integer Multiplication.” on page 5-32.Y A1.EEE Y0.Y1.A1. Comments Freescale Semiconductor Instruction Set Introduction 4-31 .EEE C 1 W 1 Comments Integer 16 × 16 multiply: F1 (unsigned) × F0 (unsigned).EEE Y0. Refer to Table 4-43 on page 4-49.5. This instruction is described in more detail in Section 5.Y A1.Instruction Set Summary Table 4-32.3.Y C1.EEE Y1.B0. The first operand is treated as signed and the second as unsigned.EEE Y0.C0.Y0.B ADD.EEE Y0. Add memory byte to register.Y A1.C0.D0.B1.D0. Refer to Table 4-43 and Table 4-44.FF B0.B1. “Multi-Precision Integer Multiplication.EEE Y1.EEE X:xxxx.C1.FF MACSU X0.Y0.Y1.EEE Y1.Y C1.EEE 2 2 3 2 2 3 1 1 1 1 C 1 W 1 Absolute value.” on page 5-32. Add 9-bit signed immediate.C1.C1.FF C0. Data ALU Extended-Precision Multiplication Instructions (Continued) Operation IMPYUU Operands A1. This instruction is described in more detail in Section 5.C0.EEE Y0.Y B1.Y1.D0.C0.FF C0. The first operand is treated as signed and the second as unsigned.C1.FF A0.Y0.Y A0.EEE Y0.Y B1.B0. Data ALU Arithmetic Instructions (Sheet 1 of 8) Operation ABS Operands FFF (parallel) ADC ADD Y.EEE X0. Table 4-33. 1 1 Integer 16 × 16 multiply: F0 (unsigned) × F0 (unsigned).D0.FF A0.A0.D0.F FFF.3.FF B0.D0.FFF (parallel) ADD. 36-bit addition of two registers.EEE Y0.C0.EEE Y0.BP #xxx.A1.C0.EEE X0.5.EEE X:xxxxxx. Add with carry (set C bit also).EEE Y1.A0. 1 1 16 × 16 => 32-bit unsigned/signed fractional MAC.Y0.EEE X0.Y1. MPYSU 1 1 16 × 16 => 32-bit signed/unsigned fractional multiply.

W. Comments Add memory long to register.EEE X:xxxx. Add a signed 16-bit immediate.EEE 2 3 3 2 3 4 3 1 2 1 1 2 1 2 3 2 2 1 2 1 Add register to memory word.X:xxxx #<0–31>. Clear a byte in memory.BP X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) X:(RRR+xxxxxx) X:xxxx X:xxxxxx 1 2 3 1 1 1 2 2 3 2 3 1 2 3 1 1 1 1 2 3 2 3 Clear a byte in memory.EEE X:xxxxxx.EEE X:(Rn+xxxx). Add an immediate integer 0–31. 4-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .EEE EEE.EEE #xxxx. Clear 36-bit accumulator and set condition codes.B X:(SP) X:(Rn+xxxx) X:(Rn+xxxxxx) CLR.Instruction Set Introduction Table 4-33.L Operands X:xxxx. Refer to Table 4-43 and Table 4-44.EEE X:(SP–xx).X:(SP–xx) EEE.fff X:xxxxxx. storing the result back to memory.W X:(Rn). Data ALU Arithmetic Instructions (Sheet 2 of 8) Operation ADD.fff C 2 3 2 W 2 3 2 Add a 16-bit immediate value sign extended to 32 bits to a data register. Also see CLR. ADD. Rn may be SP. CLR F (parallel) CLR. Add memory word to register.fff #xxxx.

This is beneficial because it clears the register without introducing any dependencies due to the pipeline.L Operands X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn+xxxx) X:(Rn+xxxxxx) X:xxxx X:xxxxxx CLR. Note: When clearing an AGU register.Instruction Set Summary Table 4-33.W #0. it is recommended to use MOVE.Rn.Y. X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+xxxx) X:(Rn+xxxxxx) X:aa X:<<pp X:xxxx X:xxxxxx 1 1 1 2 1 2 3 1 1 2 3 1 1 1 1 1 2 3 1 1 2 3 Clear a word in memory. Data ALU Arithmetic Instructions (Sheet 3 of 8) Operation CLR. MOVE.W #0. Freescale Semiconductor Instruction Set Introduction 4-33 . Not permitted for the 32-bit Y register—instead use Comments Clear a long in memory.W DDDDD (except Y) C 1 1 1 2 2 3 2 3 1 W 1 1 1 1 2 3 2 3 1 Clear a register. clear an entire AGU register when Rn is specified. Clear an entire accumulator when FF specified.

Compare the byte portion of a data register with an immediate integer 0–31.Instruction Set Introduction Table 4-33.EEE CMP. Data ALU Arithmetic Instructions (Sheet 4 of 8) Operation CMP Operands EEE.FF C 1 2 3 3 2 3 1 W 1 1 2 1 2 3 1 Compare accumulator with an immediate integer 0–31. Compare with a 9-bit signed immediate integer. X:xxxx.FF 2 2 (parallel) CMP. Compare memory word with 36 bit accumulator.fff #xxxx. Refer to Table 4-43 on page 4-49. Also see CMP.W for condition codes on 16 bits. Also see CMP.EEE CMP.FFF 2 2 3 1 2 2 3 1 Compare the 32-bit long portions of two data registers or accumulators.BP X:xxxx.W. Comments 36-bit compare of two accumulators or data registers.B EEE.FF #<0–31>. Compare the 8-bit byte portions of two data registers.EEE X:(Rn).EEE #<0–31>.EEE X:xxxxxx.FF X:xxxxxx. Note: Condition codes set based on 36-bit result.fff 2 3 2 2 3 2 Compare a 16-bit immediate value sign extended to 32 bits with a data register. 4-34 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .FF X:xxxx. Compare memory long with a data register. Compare memory byte with register.L FFF.FF X:(SP–xx). Compare accumulator with a signed 16-bit immediate. #xxxx.EEE 1 1 1 1 1 1 #xxx.FF X:(Rn+xxxx).fff X:xxxxxx.

DEC. Divide iteration. Compare the word portion of a data register with a signed 16-bit immediate. Freescale Semiconductor Instruction Set Introduction 4-35 . Compare memory word with a data register or the word portion of an accumulator.BP X:xxxx X:xxxxxx 3 4 1 3 4 1 3 4 4 3 4 1 1 3 4 1 3 4 2 3 1 2 3 1 1 2 1 2 3 1 1 2 3 1 2 3 DEC.Instruction Set Summary Table 4-33.EEE #<0–31>. X:(Rn). Data ALU Arithmetic Instructions (Sheet 5 of 8) Operation CMP. Increment byte in memory.EEE X:(Rn+xxxx).EEE 2 3 3 2 3 1 1 2 1 2 3 1 Compare the word portion of a data register with an immediate integer 0–31.L fff X:xxxx X:xxxxxx Decrement long.BP FFF1.EEE X:(SP–xx).EEE X:xxxxxx.W Operands EEE. DIV INC.W EEE X:(Rn) X:(Rn+xxxx) X:(SP–xx) X:xxxx X:xxxxxx (parallel) Decrement word.EEE 2 2 DEC.fff X:xxxx X:xxxxxx INC. Decrement byte in memory.L fff X:xxxx X:xxxxxx Increment long. #xxxx.EEE X:xxxx.EEE C 1 W 1 Comments Compare the 16-bit word portions of two data registers or accumulators. Increment long in memory. Refer to Table 4-43 on page 4-49. Decrement long in memory. Decrement word in memory using appropriate addressing mode.

36-bit subtraction of two registers. Increment word in memory using appropriate addressing mode. Two’s-complement negation. Refer to Table 4-43 and Table 4-44.BP X:xxxx X:xxxxxx NEG. Refer to Table 4-43 on page 4-49.BP #xxx.W Operands EEE X:(Rn) X:(Rn+xxxx) X:(SP–xx) X:xxxx X:xxxxxx (parallel) NEG FFF (parallel) NEG.FFF (parallel) SUB. Increment word. C 1 3 4 4 3 4 1 1 W 1 1 2 1 2 3 1 1 Refer to Table 4-43 on page 4-49. Subtract memory byte from register.EEE X:xxxxxx. Refer to Table 4-43 on page 4-49. Negate word in memory using appropriate addressing mode.L X:xxxx X:xxxxxx NEG. Subtract with carry (set C bit also).FFF (parallel) SBC SUB Y. Refer to Table 4-43 on page 4-49. Data ALU Arithmetic Instructions (Sheet 6 of 8) Operation INC. Saturate and transfer 32 bits independent of SA bit.W X:(Rn) X:(Rn+xxxx) X:(SP–xx) X:xxxx X:xxxxxx RND fff (parallel) SAT FF.EEE X:xxxx.EEE 2 2 3 2 2 3 1 1 1 1 1 1 3 4 3 4 3 4 4 3 4 1 2 3 2 3 1 2 1 2 3 1 Round.B SUB. Subtract 9-bit signed immediate. Comments 4-36 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Instruction Set Introduction Table 4-33.F FFF. Negate byte in memory. Negate long in memory.

Subtract memory word from register.fff C 2 3 2 W 2 3 2 Subtract a 16-bit immediate value. Transfer register to register.BP X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) X:(RRR+xxxxxx) X:xxxx X:xxxxxx Test a byte in memory using appropriate addressing mode. Comments Subtract memory long from register. Subtract a signed 16-bit immediate. TST. Freescale Semiconductor Instruction Set Introduction 4-37 . TST. Also see SXT.FFF FFF.L.EEE X:(SP–xx).B EEE X:(SP) X:(Rn+xxxx) X:(Rn+xxxxxx) 1 1 2 3 1 1 1 2 2 3 2 3 1 1 2 3 1 1 1 1 2 3 2 3 Test 8-bit byte in register. Sign extend long and transfer without saturating. Data ALU Arithmetic Instructions (Sheet 7 of 8) Operation SUB. SUB.L Operands X:xxxx.EEE 2 3 3 2 3 1 2 1 1 1 1 2 1 2 3 1 2 1 1 1 Subtract an immediate value 0–31.EEE #xxxx.EEE X:xxxxxx. Sign extend byte.EEE #<0–31>.EEE X:(Rn+xxxx). Refer to Table 4-43 and Table 4-44. Test a byte in memory using appropriate addressing mode.FFF FF.fff X:xxxxxx. Refer to Table 4-43 on page 4-49.W X:(Rn). from a data register. sign extended to 32 bits.Instruction Set Summary Table 4-33.L TFR FFF. SXT.fff #xxxx.EEE X:xxxx.fff (parallel) TST FF (parallel) 1 1 Test 36-bit accumulator. 36 bits.B SXT.

FFF 1 1 1 2 1 2 3 2 1 1 2 3 1 1 1 1 1 1 2 3 1 1 1 2 3 1 Zero extend byte.Instruction Set Introduction Table 4-33. Limiting is not performed if an accumulator is specified. Test a long in memory using appropriate addressing mode.L Operands fff X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:xxxx X:xxxxxx TST.B FFF. All registers are allowed except HWS and Y.W DDDDD (except HWS and Y) C 1 1 1 1 2 2 3 2 2 3 1 W 1 1 1 1 1 2 3 1 2 3 1 Test 16-bit word in register. X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+xxxx) X:(Rn+xxxxxx) X:(SP–xx) X:aa X:<<pp X:xxxx X:xxxxxx ZXT. Data ALU Arithmetic Instructions (Sheet 8 of 8) Operation TST. Test a word in memory using appropriate addressing mode. Comments Test 32-bit long in register. 4-38 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

FF A1.Y0. Data ALU Shifting Instructions Operation ASL Operands fff (parallel) ASL.W #<0–15>.Y0.Y0.FFF 1 1 1 1 C 1 W 1 Comments Arithmetic shift left entire register by 1 bit Refer to Table 4-43 and Table 4-44.FFF Y0.W ASL16 DD FFF. Arithmetic shift right of the first operand by 16 bits.X0.FFF Y1.Y1. place result in FFF ASLL.FF C1.Y1.Y0.FFF EEE.FFF C1.FFF Y1.FFF 1 1 1 1 Arithmetic shift right entire register by 1 bit Refer to Table 4-43 and Table 4-44. Arithmetic shift left 16-bit register by 1 bit Arithmetic shift left of the first operand by 16 bits.FF C1.FFF 2 1 ASLL.Y0.fff EEE.L 2 1 Arithmetic shift right by a 5-bit positive immediate integer Bi-directional arithmetic shift of destination by value in the first operand: positive –> right shift Freescale Semiconductor Instruction Set Introduction 4-39 .FFF ASR FFF (parallel) ASR16 FFF.FFF B1.fff EEE.Y1. placing result in the destination operand Arithmetic shift left by a 5-bit positive immediate integer Bi-directional arithmetic shift of destination by value in the first operand: positive –> left shift 1 1 Arithmetic shift left by a 4-bit positive immediate integer Arithmetic shift left of destination by value specified in 4 LSBs of the first operand Arithmetic shift left of the first operand by value specified in 4 LSBs of the second operand.Instruction Set Summary Table 4-34.FF Y0.FF Y0.Y0.FF #<0–31>.FFF A1.L #<0–31>.FF Y1.X0.Y1.Y0.X0.FF B1.FFF 1 1 ASRR.X0.Y0. placing result in the destination operand Arithmetic word shifting with accumulation ASRAC Y1.FFF C1.FFF Y0.

Y0.L ROL.FF A1.FFF ROL. places result in FFF Y1.FFF Y0.FF Y0. placing result in the destination operand (new bits zeroed) Logical word shifting with accumulation LSRAC Y1.Y1.Y0.fff EEE.FFF Y0.FFF A1.X0.FFF 1 1 Logical shift right by a 4-bit positive immediate integer (sign extends into FF2) Logical shift right of destination by value specified in 4 LSBs of the first operand (sign extends into FF2) Logical shift right of the first operand by value specified in 4 LSBs of the second operand.X0.FF Y1.FF Y0.FFF EEE.FF C1.X0.L ROR.FFF C1.FFF Y0.FFF Y1.W LSR.Instruction Set Introduction Table 4-34.Y1.Y0.X0.FFF C1.Y0.FFF LSL.Y0.FFF 1 1 1 1 1 1 1-bit logical shift left of word 1-bit logical shift right of word Logical shift right of the first operand by 16 bits.L 2 1 Logical shift right by a 5-bit positive immediate integer Bi-directional logical shift of destination by value in the first operand: positive –> right shift LSRR.FFF 1 1 LSRR.FFF C 1 W 1 Comments Arithmetic shift right by a 4-bit positive immediate integer Arithmetic shift right of destination by value specified in 4 LSBs of the first operand Arithmetic shift right of the first operand by value specified in 4 LSBs of the second operand.W ROR.FFF A1.Y0.FFF Y0.W LSR16 EEE EEE FFF.FF #<0–31>.W #<0–15>.Y0.W Operands #<0–15>.Y0.Y1.FFF B1.FFF C1. places result in FFF (sign extends into FF2) EEE.X0.X0.FFF Y1.FF B1.Y0.W F EEE F EEE 1 1 1 1 1 1 1 1 Rotate 32-bit register left by 1 bit through the carry bit Rotate 16-bit register left by 1 bit through the carry bit Rotate 32-bit register right by 1 bit through the carry bit Rotate 16-bit register right by 1 bit through the carry bit 4-40 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .FFF C1.FF C1. Data ALU Shifting Instructions (Continued) Operation ASRR.Y0.Y1.FFF B1.Y1.Y0.Y1.FFF Y1.Y0.

Data ALU Shifting Instructions (Continued) Operation SUBL Operands (parallel) C 1 W 1 Comments Refer to Table 4-43 on page 4-49. and NOTC can also be used to perform logical operations with an immediate value on registers and data memory locations.fff EEE.2.L Operands #<0–31>.EEE EEE.W #<0–31>.Instruction Set Summary Table 4-34.L FFF.EEE EEE FFF.EEE CLB FFF. “The ANDC.1. Data ALU Logical Instructions Operation AND. and NOTC Aliases. ORC.W NOT. 1 1 1 1 1 1 1 1 16-bit exclusive OR (XOR) One’s-complement (bit-wise) negation 32-bit logical OR 16-bit logical OR EOR. Table 4-36.F C 4 W 1 Comments Normalization iteration instruction for normalizing the F accumulator Freescale Semiconductor Instruction Set Introduction 4-41 .fff AND.W EEE.” for additional information.EEE 1 1 1 1 C 1 W 1 Comments AND with a 5-bit positive immediate integer (0–31) 32-bit logical AND AND with a 5-bit positive immediate integer (0–31) 16-bit logical AND Count leading bits (minus 1). EORC. Miscellaneous Data ALU Instructions Operation NORM Operands R0.EEE ANDC. Table 4-35. See Section 4.L OR. EORC.fff (parallel) 1 1 EOR.W OR. designed to operate with the ASLL and ASRR instructions 32-bit exclusive OR (XOR) Refer to Table 4-43 on page 4-49. ORC.fff FFF.

N 1 1 #xxxx.L DECTSTA Rn.Rn. AGU Arithmetic and Shifting Instructions Operation ADDA Operands Rn. Add first register with a 24-bit immediate value and store the result in Rn.Rn. Decrement AGU register by two.N 1 1 1 1 #xxxxx. HHH is accessed as a signed 16-bit word. Arithmetic shift right AGU register by 1 bit. Add unsigned 4-bit value to Rn. Add a data register left shifted 1 bit with an unsigned 16-bit immediate value and store the result in Rn. 24-bit compare between two AGU registers.Rn. Arithmetic shift left AGU register by 1 bit.Rn 4 2 #xxxxxx.Rn 3 3 #xxxx.Rn. HHH is accessed as a signed 16-bit word. Add a data register with an unsigned 16-bit value and store the result in Rn.W DECA DECA.Rn. HHH is accessed as a signed 16-bit word.L Rn.Rn Rn. Decrement and test AGU register. Decrement AGU register by one.Rn. Rn.HHH.Rn 5 3 ADDA.Rn 2 2 #xxxxxx. Add first register left shifted 1 bit with a 24-bit immediate value and store the result in Rn.Rn 2 2 #xxxxxx. Add first register left shifted 1 bit with an unsigned 16-bit immediate value and store the result in Rn.N 1 1 #<0–15>.Rn.Rn Rn Rn. Add first operand to the second and store result in the N register. Add a data register left shifted 1 bit with a 24-bit immediate value and store the result in Rn.Rn 3 3 #xxxx.Rn 1 1 Rn. Add a data register with a 24-bit immediate value and store the result in Rn.HHH. Add first operand left shifted 1 bit to the second and store result in the N register.Rn C 1 W 1 Comments Add first operand to the second and store the result in the second operand.Rn 4 2 #xxxxxx.HHH.Rn #<0–15>.Rn Rn Rn Rn 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4-42 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Add first register with a signed 17-bit immediate value and store the result in Rn. 16-bit compare between two AGU registers. Add an unsigned 4-bit value to an AGU register and store result in the N register. Add first operand left shifted 1 bit to the second and store the result in the second operand.HHH.Rn 5 3 ASLA ASRA CMPA CMPA. HHH is accessed as a signed 16-bit word.Instruction Set Introduction Table 4-37.

#<1–64>. then the C bit is set.X:xxxx #<MASK16>.L TSTA.W TFRA TSTA. Negate AGU register. Bit-Manipulation Instructions Operation BFCHG Operands #<MASK16>.W Rn Rn Rn.Rn Rn Rn Rn Rn Table 4-38. If all the targeted bits are set. Sign extend the value in an AGU register from bit 15. 1 1 1 1 1 1 3 1 1 1 1 1 1 1 Sign extend the value in an AGU register from bit 7. Zero extend the value in an AGU register from bit 15. the upper 8 bits are forced to zero. Test and decrement AGU register. Note: Only operates on the lower 16 bits of the register.Rn C 1 1 1 W 1 1 1 Comments Logical shift right AGU register by 1 bit. Comments BFCHG tests all the targeted bits defined by the 16-bit immediate mask. ZXTA. Oterwise it is cleared.DDDDD #<MASK16>. Test long portion of an AGU register.X:aa #<MASK16>. Freescale Semiconductor Instruction Set Introduction 4-43 .X:(SP–xx) #<MASK16>.SP SXTA.B TSTA.X:xxxxxx C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 All registers in DDDDD are permitted except HWS and Y. Then the operation inverts all selected bits.W TSTDECA. AGU Arithmetic and Shifting Instructions (Continued) Operation LSRA NEGA SUBA Operands Rn Rn Rn.X:(Rn) #<MASK16>.X:(Rn+xxxx) #<MASK16>.W Rn Rn 1 1 1 1 Zero extend the value in an AGU register from bit 7.Instruction Set Summary Table 4-37. Test word portion of an AGU register.B ZXTA. Transfer one AGU register to another. Subtract a 6-bit unsigned immediate value from the SP and store in the stack pointer.dd #<MASK16>.X:<<pp #<MASK16>. Subtract the first operand from the second and store the result in the second operand.B SXTA. Test byte portion of an AGU register.

X:xxxxxx C 2 2 2 3 3 2 2 3 4 2 2 2 3 3 2 2 3 4 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 2 2 2 3 2 2 2 3 4 2 2 2 3 2 2 2 3 4 BFTSTH tests all the targeted bits defined by the 16-bit immediate mask.X:xxxxxx BFSET #<MASK16>. BFSET tests all the targeted bits defined by the 16-bit immediate mask. Then the operation sets all selected bits. then the C bit is set.X:(Rn) #<MASK16>.dd #<MASK16>.dd #<MASK16>.X:<<pp #<MASK16>. If all the targeted bits are set. All registers in DDDDD are permitted except HWS and Y.X:aa #<MASK16>. Otherwise it is cleared. Otherwise it is cleared.X:<<pp #<MASK16>.DDDDD #<MASK16>. Bit-Manipulation Instructions (Continued) Operation BFCLR Operands #<MASK16>.X:xxxx #<MASK16>. Then the operation clears all selected bits. All registers in DDDDD are permitted except HWS and Y.dd #<MASK16>.X:<<pp #<MASK16>. If all the targeted bits are set.X:(SP–xx) #<MASK16>.X:aa #<MASK16>.X:(SP–xx) #<MASK16>. 4-44 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X:(Rn+xxxx) #<MASK16>. All registers in DDDDD are permitted except HWS and Y. then the C bit is set. Otherwise it is cleared.X:(SP–xx) #<MASK16>.DDDDD #<MASK16>.X:xxxx #<MASK16>.Instruction Set Introduction Table 4-38.X:(Rn+xxxx) #<MASK16>.DDDDD #<MASK16>.X:xxxx #<MASK16>.X:(Rn+xxxx) #<MASK16>.X:(Rn) #<MASK16>. If all the targeted bits are set.X:(Rn) #<MASK16>.X:aa #<MASK16>.X:xxxxxx BFTSTH #<MASK16>. Comments BFCLR tests all the targeted bits defined by the 16-bit immediate mask. then the C bit is set.

<OFFSET7> #<MASK8>.Instruction Set Summary Table 4-38.X:(SP–xx) #<MASK16>.X:(SP–xx).<OFFSET7> #<MASK8>.<OFFSET7> #<MASK8>. If all the targeted bits are clear.X:<<pp #<MASK16>.X:xxxxxx C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 Comments BFTSTL tests all the targeted bits defined by the 16-bit immediate mask.<OFFSET7> #<MASK8>. MASK8 specifies a 16-bit immediate value where either the upper or lower 8 bits contain all zeros.X:xxxxxx.DDDDD.X:aa. then the carry bit is set and a PC relative branch occurs.X:<<pp.X:<<pp.<OFFSET7> #<MASK8>.dd.<OFFSET7> BRSET #<MASK8>.X:(Rn) #<MASK16>.<OFFSET7> #<MASK8>. Branch-on-Bit-Manipulation Instructions Operation BRCLR Operands #<MASK8>.X:(SP–xx).X:(Rn+xxxx).<OFFSET7> #<MASK8>.<OFFSET7> #<MASK8>. then the carry bit is set and a PC relative branch occurs.X:(Rn+xxxx) #<MASK16>.<OFFSET7> #<MASK8>. then the C bit is set. Comments BRCLR tests all the targeted bits defined by the immediate mask.DDDDD #<MASK16>.X:(Rn+xxxx).X:xxxx.X:(Rn).<OFFSET7> #<MASK8>. All registers in DDDDD are permitted except HWS and Y.<OFFSET7> C 7/5 7/5 7/5 8/6 8/6 7/5 7/5 7/5 8/6 7/5 7/5 7/5 8/6 8/6 7/5 7/5 7/5 8/6 W 2 2 2 3 2 2 2 3 4 2 2 2 3 2 2 2 3 4 BRSET tests all the targeted bits defined by the immediate mask. All registers in DDDDD are permitted except HWS and Y. If all the targeted bits are set. MASK8 specifies a 16-bit immediate value where either the upper or lower 8 bits contain all zeros.X:aa.<OFFSET7> #<MASK8>.X:xxxx #<MASK16>. If all the targeted bits are clear.<OFFSET7> #<MASK8>. Bit-Manipulation Instructions (Continued) Operation BFTSTL Operands #<MASK16>. Otherwise it is cleared and no branch occurs. Table 4-39.X:aa #<MASK16>.dd.DDDDD.<OFFSET7> #<MASK8>.<OFFSET7> #<MASK8>.X:(Rn).dd #<MASK16>.X:xxxxxx.X:xxxx.<OFFSET7> #<MASK8>.<OFFSET7> #<MASK8>. Otherwise it is cleared and no branch occurs. Freescale Semiconductor Instruction Set Introduction 4-45 . All registers in DDDDD are permitted except HWS and Y. Otherwise it is cleared.

must fill 2 delay slots (2 program words) 18-bit signed PC-relative offset 22-bit signed PC-relative offset Delayed return from level 2 interrupt. restoring PC from the FIRA register and the Y register from the stack in a fast interrupt procedure. restoring 21-bit PC and SR from the stack <OFFSET18> 3 2 <OFFSET22> 4 3 BSR <OFFSET18> <OFFSET22> 5 6 2 2 3 1 FRTID Jcc <ABS19> <ABS21> 5/4 6/5 5 4 5 2 2 3 1 2 3 2 JMP (N) <ABS19> <ABS21> JMPD <ABS19> <ABS21> 3 3 JSR (RRR) 5 1 <ABS19> <ABS21> RTI 4 5 8 2 3 1 4-46 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Instruction Set Introduction Table 4-40. must fill 2 delay slots (2 program words) Push 21-bit return address and jump to target address contained in RRR register Push 21-bit return address and jump to 19-bit target address Push 21-bit return address and jump to 21-bit target address Return from interrupt. must fill 2 delay slots (2 program words) Delayed jump with 21-bit absolute address. must fill 2 delay slots (2 program words) Delayed branch with 22-bit signed offset. must fill 2 delay slots (2 program words) Delayed branch with 18-bit signed offset. Change-of-Flow Instructions Operation Bcc Operands <OFFSET7> <OFFSET18> <OFFSET22> BRA <OFFSET7> <OFFSET18> <OFFSET22> BRAD <OFFSET7> C 5/3 5/4 6/5 5 5 6 3 W 1 2 3 1 2 3 1 Comments 7-bit signed PC-relative offset 18-bit signed PC-relative offset 22-bit signed PC-relative offset 7-bit signed PC-relative offset 18-bit signed PC-relative offset 22-bit signed PC-relative offset Delayed branch with 7-bit signed offset. must fill 2 delay slots (2 program words) 19-bit absolute address 21-bit absolute address Jump to target contained in N register 19-bit absolute address 21-bit absolute address Delayed jump with 19-bit absolute address.

use A1. Last address is 16-bit absolute. B1. SR. C0.<ABS16> #<1–63>.Instruction Set Summary Table 4-40. DDDDD. “Non-Interruptible Instruction Sequences. Minimum of 2 instructions words required in the loop. C1. Last address is 21-bit absolute address. restoring 21-bit PC from the stack.<ABS16> C 3 W 2 Comments Load LC register with unsigned value and start hardware DO loop with 6-bit immediate loop count. D. N3. LC. M01. Last address is 16-bit absolute. LA2. D0. execute loop for specified number of times. OMR. LC2. Case of only 1 instruction word in loop body Load LC register with unsigned value. LC. B1. and HWS. Otherwise skip body of loop (adds 3 additional cycles). Executes in 3 cycles when there is a minimum of 2 instruction words in the loop. If LC is not equal to zero. Y. D. Any register is allowed except C2. Table 4-41. LA2. Last address is 21-bit absolute address.<ABS16> 6 7 3 2 <ABS21> 4 3 Freescale Semiconductor Instruction Set Introduction 4-47 . or D1 to avoid saturation when reading the accumulator. or D1 to avoid saturation when reading the accumulator.3. LA. When looping with a value in an accumuator. C1.” on page 9-10. restoring 21-bit PC and SR from the stack.4. C. and HWS.<ABS21> 5 4 2 3 #<1–63>. SR. start hardware DO loop with 16-bit loop count in register.<ABS21> DDDDD. Last address is 16-bit absolute. restoring 21-bit PC from the stack Delayed return from subroutine. OMR. When looping with a value in an accumuator.<ABS21> 8 3 Last address is 21-bit absolute address. DOSLC <ABS16> 3 2 If value in LC > 0. D0. Any register is allowed except C2. Otherwise skip body of loop (adds 2 additional cycles). Y. must fill 3 delay slots (3 program words) Return from subroutine. #<1–63>. LC2. Minimum of 2 instructions words required in the loop. M01. Looping Instructions Operation DO Operands #<1–63>. use A1. must fill 3 delay slots (3 program words) RTS RTSD 8 5 1 1 Information on delayed instruction execution is located in Section 9. Case of only 1 instruction word in loop body. N3. D2. Change-of-Flow Instructions (Continued) Operation RTID Operands C 5 W 1 Comments Delayed return from interrupt. Executes in 4 cycles when there is a minimum of 2 instruction words in the loop. C. LA. D2. C0.

Generate an interrupt at the highest priority level (level 3. Generate an interrupt at priority level 0. C.Instruction Set Introduction Table 4-41. When looping with a value in an accumuator. The number of cycles is dependent upon chip implementation. M01. SR. use A1. LC2. Y. No operation. Note: REP #<0–63> 2 1 Does not branch to the end of the loop. C1. Enter wait low-power mode. B1. non-maskable). Generate an illegal instruction exception. or D1 to avoid saturation when reading the accumulator. C0. D2. LA. pointing to an empty location. Any register is allowed except C2. Otherwise skip body of loop (adds 1 additional cycle). Looping Instructions (Continued) Operation ENDDO Operands C 1 W 1 Comments Remove one value from the hardware stack and update the NL and LF bits appropriately. start hardware REP loop with 16-bit loop count in register. D. and HWS. LC. Hardware repeat of a 1-word instruction with immediate loop count. DEBUGEV DEBUGHLT ILLEGAL 3 3 4 1 1 1 NOP STOP 1 * 1 1 SWI #<0–2> 1 1 SWI 4 1 SWILP WAIT 1 * 1 1 4-48 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 1. N3. OMR. can be used to verify interrupt handlers for illegal instructions. or 2 as specified by the instruction. D0. Enter the debug processing state. The number of cycles is dependent upon chip implementation. Generate an interrupt at the lowest priority level (lower than level 0). Generate a debug event. DDDDD 5 1 Table 4-42. LA2. If LC is not equal to zero. Enter stop low-power mode. Hardware repeat of a 1-word instruction with loop count specified in register. Control Instructions Operation ALIGNSP Operands C 3 W 1 Comments Save SP to the stack and align SP for long memory accesses.

F Y0.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.Y1. Table 4-43 summarizes the single parallel moves that are legal.F Y0.F MAC MPY MACR MAC C1.Y0.F Y0.A ADD SUB CMP TFR SAT EOR.F A1. Table 4-43. Memory writes are allowed in this case. and the F0 portion of both accumulators is set to $0000.F A.F C.X0.F X0.Y0.D.F C1.Y0. Single Parallel Move Instructions Data ALU Operation Operation MAC MPY MACR MPYR Operands Y1. Three types of parallel moves are supported: a move of data in memory to a register. Both extension registers are sign extended.F B1. Data transferred in a parallel move is always treated as a signed 16-bit word.5 Parallel Move Summary Tables The following tables show the instructions that support move operations that are executed in parallel with the execution of the primary instruction. a move of a register value to memory.Y0 C. 2.B B. Each instruction occupies only 1 program word and executes in 1 cycle.F X0 Y1 Y0 A B C A1 B1 Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N –C1.4.Y0.B X:(R1)+ AD 1.F Y1.W DEC.F Y1.Instruction Set Summary 4.L ABS ASL ASR CLR RND TST INC. or two simultaneous moves of data from memory to a register.The “AD” destination notation indicates that both the A and D accumulators are written with the same 16-bit value.W NEG SUBL2 F.Y0. Freescale Semiconductor Instruction Set Introduction 4-49 .F –C1.Y1.Y1.X0.F F A.

These instructions are not allowed when the XP bit in the OMR is set (that is. when the instructions are executing from data memory).B B.F C1. Data transferred in by each of the reads is always treated as a signed 16-bit word.C X:(R0)+.X0.F X0.X0.Instruction Set Introduction Examples of instructions with a single parallel move appear in Example 4-6.Y0.X0 X0.F A.A Y1.F Y0.A F First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Second Memory Read Source 2 X:(R3)+ X:(R3)– Destination 2 X0 Y0 Y1 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 C 4-50 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .A B B X:(R0)+. A.A TFR CLR ASL ASR MOVE. Each instruction occupies only 1 program word and executes in 1 cycle.F Y0.B B. Table 4-44. Dual Parallel Read Instructions Data ALU Operation1 Operation MAC MPY MACR MPYR ADD SUB Operands Y1.Y0.F Y1.X:(R0)+ X:(R0)+. Example 4-6.Y0.Y1 Y1.X:(R0)+ Table 4-44 summarizes the dual parallel read instructions that are legal.A -C1.W 1.F Y1. Examples of Single Parallel Moves MAC MAC MAC ASL ASL Y1.X0.X0.

Figure 4-1 summarizes these instructions to aid in choosing the correct instruction.W (16) * TFRA recommended for AGU register transfers Figure 4-1.L (32) SXT.W (16) SAT (32) SXT.W (16) MOVE. Moving Data in the Register Files Freescale Semiconductor Instruction Set Introduction 4-51 .W (16) MOVE.5 Register-to-Register Moves As the instruction set summary shows.Register-to-Register Moves 4. Data Registers TFR (36) A2 B2 C2 D2 A1 B1 C1 D1 Y1 ZXT.B (8) Y0 X0 ASL16 (36) ASR16 (36) LSR16 (36) MOVE.L (32) MOVE.B (8) Pointer Registers R0 R1 R2 R3 R4 R5 N SP TFRA* (24) MOVEU.W (16) MOVEU.L (24) A0 B0 C0 D0 MOVE. several different instructions are available for performing register-to-register moves.

Instruction Set Introduction 4-52 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

logical. and 36-bit operands) Logical operations (AND.) The data ALU can perform the following operations with a throughput of 1 cycle per instruction. OR. 16-. and 36-bit operands) Test and comparison (for 8-. Multiplication. except where noted: • • • • • • • • • • • • • • • • • • • Multiplication (with or without rounding) Multiplication with negated product (with or without rounding) Multiplication and accumulation (with or without rounding) Multiplication and accumulation with negated product (with or without rounding) Multi-precision multiplication support Addition and subtraction Increments and decrements (for 8-. and shifting operations are performed in this block. and that the bit-manipulation unit can also perform logical operations. 16-. and EOR) One’s-complement and two’s-complement negation Arithmetic and logical shifts Rotates Rounding Absolute values Sign extension and zero extension Saturation (limiting) on data ALU and move operations Conditional register moves Division iteration Normalization iterations (execute in 4 clock cycles) Multiple buses within the data ALU allow complex arithmetic operations (such as a multiply-accumulate) to execute in parallel with up to two memory transfers in a single execution cycle.Chapter 5 Data Arithmetic Logic Unit This chapter describes the architecture and operation of the data arithmetic logic unit (ALU). 32-. arithmetic. (Note that addition can also be performed in the address generation unit. Freescale Semiconductor Data Arithmetic Logic Unit 5-1 . 32-.

An arithmetic and logical multi-bit shifter. and Y1). Data ALU Programming Model 5-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The blocks and registers within the data ALU are explained in the following sections. A MAC output limiter. A single-bit accumulator shifter. and a block diagram is shown in Figure 5-2 on page 5-3.1 Data ALU Overview and Architecture The major components of the data ALU are: • • • • • • • Three 16-bit data registers (X0. Y0. 35 32 31 A B C D A2 B2 C2 D2 15 Y Y1 Y0 X0 A1 B1 C1 D1 0 16 15 A0 B0 C0 D0 0 Figure 5-1. A single-cycle multiply-accumulator (MAC) unit. C. Four 36-bit accumulator registers (A. B.Data Arithmetic Logic Unit 5. A data limiter. and D). A programming model of the data ALU unit is shown in Figure 5-1.

Data ALU Block Diagram 5. and Y0—that serve as data registers for operations in the data ALU. Y1 forms the most significant word and Y0 forms the least significant word. which is shown in Figure 5-3 on page 5-4.1. Y0) There are three independent 16-bit registers—X0.1 Data Registers (X0. Y1. Y1.Data ALU Overview and Architecture * For second access on dual parallel read XDB2* CDBR CDBW Limiter (accesses X0 and C only) Data Registers 35 32 31 A2 B2 C2 D2 16 15 A1 B1 C1 D1 Y1 Y0 X0 A0 B0 C0 D0 0 Optional Inverter Arithmetic/Logical Shifter Shifter/MUX Latch MUX Rounding Constant 36-Bit Accumulator Shifter OMR’s SA Bit MAC Output Limiter EXT:MSP:LSP Condition Code Generation Condition Codes to Status Register Figure 5-2. The 16-bit Y1 register and the 16-bit Y0 register can be concatenated together to form a 32-bit register called Y. Freescale Semiconductor Data Arithmetic Logic Unit 5-3 .

FF2 refers only to the 4-bit extension portion (bits 35–32). X0 Register Used in Operation and Loaded in Parallel ADD. FF0 (where FF0 represents A0. these registers can serve as sources for data ALU operations while new operands are loaded into them. X0 used and simultaneously loaded The Y1. C.Data Arithmetic Logic Unit 31 Y Y1 MSP 16 15 Y0 LSP 0 32-Bit Y Register Figure 5-3. in parallel. C1. With the use of parallel move instructions (see Section 3. or D0) The “FF” notation is used throughout this chapter and the rest of the manual in references to the accumulators.” on page 3-11). B.3. Only the X0 register can be written by the secondary read in a dual read instruction.A X:(R0)+. Different Components of an Accumulator (Using “FF” Notation) 5-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W X0. The various parts of an accumulator and the corresponding “FF” notation are shown in Figure 5-4. B2. This process is demonstrated in Example 5-1. All of the registers can be read or written using a parallel move. 5.X0 . Example 5-1. FF2 (where FF2 represents A2. Each 36-bit data ALU accumulator register is composed of three different portions: • • • 4-bit extension register. FF1 is the 16-bit most significant portion (bits 31–16).1. FF refers to the entire accumulator (bits 35–0). B0. independent. and FF0 is the 16-bit least significant portion (bits 15–0). C0. B1. or D2) 16-bit most significant product (MSP). FF1 (where FF1 represents A1. from memory. The 32-Bit Y Register—Composed of Y1 Concatenated with Y0 The data registers are used as source or destination operands for most data ALU operations. Y0. C2. The Y register is read or written as a long operand. Note that there is not actually an “FF” accumulator anywhere in the chip. 35 FF Extension (FF2) FF2 32 31 FF1 MSP (FF1) 16 15 FF0 LSP (FF0) 0 Long Portion of Accumulator (FF10) Entire Accumulator (FF) Figure 5-4. or D1) 16-bit least significant product (LSP). and X0 registers can be read or written as a byte or word operand.5. “Parallel Moves. 36-bit accumulator registers that serve as the source or destination for operations in the data ALU. D) The data ALU contains four. In this notation.2 Accumulator Registers (A.

whereas arithmetic and logical operations are completed in a single cycle. The MAC unit is pipelined to maintain a throughput of one instruction per cycle. This block performs multiplications.Data ALU Overview and Architecture As Figure 5-4 on page 5-4 shows. FF10 represents the concatenation of the FF1 and FF0 portions and is useful for manipulating 32-bit quantities.” on page 10-4. can come from memory. “Parallel Moves. Byte. NOTE: The C2.” on page 3-11). multiplication and arithmetic/logical. With the use of parallel move instructions (see Section 3. Y0. D1. The inputs of the MAC and logic unit can come from the seven data ALU registers (A1. See Section 5.2. word.1. and D0 portions of the C and D accumulators are generally not directly accessible through the instruction set. from memory. which is referred to as FF10 in this notation. Accumulator A Used in Operation and Stored in Parallel ADD. “Accessing Portions of an Accumulator. and other arithmetic operations. C1. Freescale Semiconductor Data Arithmetic Logic Unit 5-5 . Multiplication and MAC operations take 2 cycles to flow through the two pipeline stages. Arithmetic operations in the MAC unit occur independently and in parallel with memory accesses on the core data buses. It accepts up to three input operands and outputs one 36-bit result.2.W X0. The accumulators are used as source or destination operands for most data ALU operations. B1. additions. and long operands are all supported. 5. “Data ALU Execution Stages.9. with the exception of certain operations.” discusses methods for accessing the accumulators and strategies for using them properly.4 Single-Bit Accumulator Shifter The accumulator shifter is an asynchronous parallel shifter with a 36-bit input and a 36-bit output. Only the C register can be written by the secondary read in a dual read instruction. or to pre-shift values before they are passed on to the MAC unit (as occurs with the LSRAC instruction). This capability allows a parallel move instruction to update an accumulator in the same instruction in which the accumulator is used as the source for an ALU operation. in parallel.1. or long operand. Section 5. 5. Optional saturation and rounding are supported to ensure correct operation when 36-bit results are written to memory. these registers can serve as sources for data ALU operation while new operands are loaded into them. subtractions. D2. “Rounding. The MAC pipeline has two stages. A used and simultaneously stored Each register can be read or written as a byte.3 Multiply-Accumulator (MAC) and Logic Unit The multiply-accumulator (MAC) and logic unit is the main arithmetic processing unit in the data ALU. This process is demonstrated in Example 5-2.” for a more detailed discussion. C0.3.X:(R0)+ . and Y1).5. Example 5-2. In a parallel move instruction. word. “Accessing the Accumulator Registers. See Section 5.” for ways to access these registers.2.A A. More information on the two-stage execution of the MAC unit appears in Section 10. or can be immediate data.2. logical operations. it is also possible to directly address the 32-bit long-word portion of the accumulator. an accumulator register is specified only as a whole accumulator and not in portions. The accumulator shifter is used to perform single-bit shifts of entire accumulators (as with the ASL and ASR instructions).2. X0.

More information on the two-stage execution of the shifter unit appears in Section 10. and the second stage can add the result of the first stage to an accumulator in the ALU unit. This access method also allows for accumulators to be saved and restored without limiting. Using the full accumulator also provides limiting (or saturation) capability when storing the result of a computation would cause overflow.” for more information. The operation of the two limiter units is discussed in Section 5.Data Arithmetic Logic Unit 5. B10. the DSP56800E provides three methods for accessing the accumulators: • • • As an entire 36-bit register (FF) As a 32-bit long register for store operations (FF10) As individual component registers (FF2. Table 5-1 on page 5-7 summarizes the various possible accesses. See Section 5. “Accessing Portions of an Accumulator.2. It allows long variables to be written to memory and stored to other registers without saturation.1.6 Data Limiter and MAC Output Limiter DSC algorithms can calculate values larger than the data precision of the machine when processing real data streams. “Data ALU Execution Stages. but this treatment can create problems for processing real-time signals. Note that while the individual accumulator register portions are normally accessible. The unit is pipelined to maintain a throughput of one instruction per cycle for 16-bit shifting (one instruction per two cycles for 32-bit shifting). To eliminate the problems associated with overflow and underflow.6.2. and D0 are exceptions. To simplify the development of algorithms for signal processing and control. Refer to Section 5. Shifting is performed in the first stage. FF1. “Saturation and Data Limiting. the DSP56800E provides the optional saturation of results using two limiters: the data limiter and the MAC output limiter. The ability to access individual portions of an accumulator (FF2. see Section 5. Shifting operations take two cycles to flow through the two pipeline stages (three cycles for 32-bit shifts).2. Normally a processor simply overflows such a result.” for details on how to access these portions. 5.” Accessing 32-bit long values (A10. These are described in more detail in the following sections. or FF0) provides a great deal of flexibility when systems and control algorithms are implemented. or D10) is important for control tasks and general-purpose computing.” 5. The pipeline has two stages.” on page 10-4. allowing for the accurate manipulation of integer values. C0.8. “Saving and Restoring Accumulators.2 Accessing the Accumulator Registers The DSP56800E architecture provides four 36-bit accumulator registers for arithmetic operations. D2.1. C. Saturation is always disabled when portions of an accumulator are manipulated. “Data Limiter.5 Arithmetic and Logical Shifter An arithmetic and logical shifter block performs shifting of data ALU registers by an immediate value or by a value specified in a register. C10. FF1. or FF0) Accessing an entire accumulator (A.8. or D) is particularly useful for DSC tasks because it preserves the full precision of multiplication and other ALU operations. 5-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .1. preserving the full precision of a mathematical result. B.2. C2.2.

When used in an arithmetic operation: The FF1 register is used as a 16-bit source operand for an arithmetic operation. Accessing the Accumulator Registers Register A B C D Reading an Accumulator Register Using a MOVE.) Using a MOVE. the MOVEU.B.8.W instruction: The 16-bit value is written into the FF1 register.1.W instruction: The 16-bit value is written into the FF0 register. See Section 5.B instruction: The 8-bit value is written into the lower 8 bits of the FF1 portion of the register. “Data Limiter. The corresponding FF2 and FF1 portions are not modified.L. The upper 8 bits of the FF1 portion and the extension portion.L instruction: The 32 bits in the FF1 and FF0 portions of the accumulator are read. The upper 12 bits are ignored. parallel moves. A1 B1 C1 D1 Using a MOVE. Using a MOVE.BP). Using a MOVE. sign extended to 16 bits. The extension portion. and bit-manipulation operations are also supported. is read. A0 B0 Using a MOVE. The FF2 register is written with sign extension.W is supported. FF2.BP.) Not available as a destination. The corresponding FF2 and FF0 portions are not modified. Freescale Semiconductor Data Arithmetic Logic Unit 5-7 . Using a MOVE. Writing an Accumulator Register Using a MOVE. FF2.W instruction: The 16-bit value is written to the FF1 portion of the accumulator. A10 B10 C10 D10 A2 B2 Using a MOVE.B instruction: The lower 8 bits of FF1 are read. Saturation logic is bypassed on MOVE.B). If the extension bits are in use. Using a MOVE.W instruction. The FF0 portion is set to zero.W instruction: The 16-bit FF1 portion is read.W instruction: The 4 LSBs of the 16-bit value are written into the register. (See Figure 5-7 on page 5-10.W instruction: The 4-bit register. MOVEU. a 16-bit “limited” value is substituted.” When used in an arithmetic operation: All 36 bits are used without limiting. MOVEU.L instruction: All 32 bits of the CDBR bus are written to the FF1 and FF0 portions of the register. the 16-bit contents of the FF1 portion of the accumulator are read. is filled with sign extension. Using a MOVE. FF1 is also used for unsigned moves (MOVEU. Using a MOVE. are sign extended (zero extended on MOVEU. Long-word values must be written to the entire accumulator. FF1:FF0. The corresponding FF1 and FF0 portions are not modified.W) and with byte pointer operations (MOVE.W instruction: If the extension bits are not in use. Note: In all cases where MOVE.W instruction: The 16-bit FF0 register is read.Accessing the Accumulator Registers Table 5-1. (See Figure 5-8 on page 5-11. the FF0 portion is set to zero.

The entire accumulator register can also be accessed with the explicit execution of a MOVE instruction. C2. The extension can occur when FF is written from the CDBR (MOVE. The result of an ALU or multiplication operation is typically a full 36-bit value that. Contents from the 32-bit CDBR bus can be written to all accumulators (A. When an unsigned value is moved into an accumulator. B. making the value negative.W #$1234.W #$A987. Automatic sign extension causes this bit to be propagated into the extension register. C.1 Accessing an Entire Accumulator The accumulator registers serve as the source or destination for most data ALU operations. B2. or D2). or a MOVE. or D) with sign extension propagated to the 4-bit extension register (A2. ADD.W. no sign extension is performed when TFR transfers a smaller register to an accumulator. This result does not occur for the TFR instruction.B. 5-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the extension (FF2) portion of the accumulator must be cleared because the most significant bit might be set. MOVE.Data Arithmetic Logic Unit 5.1 Writing an Accumulator with a Small Operand Automatic sign or zero extension of the 36-bit accumulators is provided when the FF accumulator is written with a smaller size operand. or MOVE. Writing the Accumulator as a Whole A move instruction that moves one accumulator to another. If a word operand is to be written to an accumulator register (FF). Writing a Positive Value into 36-Bit Accumulator: MOVE.B. Note that all three portions of the accumulator are modified by these instructions. 5. or TFR from a 16-bit register to a 36-bit accumulator). when written to an accumulator.L. the FF0 portion is zeroed. the SAT instruction can be used to saturate the value in the 36-bit accumulator. behaves similarly. limiting with the full-scale positive or negative 32-bit values ($7FFF:FFFF or $8000:0000).B Before Execution B2 B X X X B1 X X X X B0 X X 0 B B2 F A 9 After Execution B1 8 7 0 0 B0 0 0 0 35 32 31 16 15 35 32 31 16 15 Figure 5-5.2.2.1.L instruction with an immediate value. affects the entire register. Figure 5-5 shows some examples of writing word values to an accumulator.B Before Execution B2 B X X X B1 X X X X B0 X X 0 B B2 0 1 2 After Execution B1 3 4 0 0 B0 0 0 0 35 32 31 16 15 35 32 31 16 15 Writing a Negative Value into 36-Bit Accumulator: MOVE. When the contents of the 36-bit accumulator need to be limited. Inputs for most arithmetic operations are also full-precision 36-bit accumulator values. the FF1 portion of the accumulator is written with the word operand. Unsigned loads of words or long words to an accumulator are performed using the technique in Example 5-3 on page 5-9. and the FF2 portion receives sign extension.L instruction) or with the results of certain data ALU operations (for example.L. SUB. MOVEU.

the overflow bit (V) in the status register is set. 5. Figure 5-6 on page 5-10 shows some examples of writing values to portions of the accumulator.” NOTE: Limiting is performed only when the entire 36-bit accumulator register (FF) is specified as the source for a data move or is transferred to another register. Saturation and limiting are explained in more detail in Section 5. Refer to Table 5-1 on page 5-7 for a summary of ways to access the accumulator registers.2. only the value transferred is limited to a full-scale positive or negative 16-bit value ($7FFF or $8000). NOTE: If the extension bits of an accumulator contain only sign extension (the E bit in the status register is not set). When an instruction uses the FF1 or FF0 notation instead of F.Accessing the Accumulator Registers Example 5-3.2 Using the Extension Registers The extension registers (FF2) offer protection against 32-bit overflow. When the result of an accumulation crosses the MSB of MSP (bit 31 of FF).8. “Saturation and Data Limiting.2. This same logic applies to the SAT instruction. When this loss occurs. and a read of an entire accumulator is identical to a read of just the FF1 portion. When limiting occurs. Freescale Semiconductor Data Arithmetic Logic Unit 5-9 . the instruction operates only on the 4-bit accumulator extension register without modifying the FF1 or FF0 portions of the accumulator. FF1. 5. the extension in use bit of the status register (E) is set. It is not performed when FF2. or FF0 is specified. after which the sign is lost beyond the MSB of the extension register.L X:(R0). When an instruction specifies FF2.2. where intermediate calculations might overflow. saturation is unnecessary. The extension in use bit is used to determine when to saturate the value of an accumulator when it is written to memory or when it is transferred to any data ALU register.B CLR. Up to 15 overflows or underflows are possible using the accumulator extension bits. the L flag in the status register is set.1. the instruction only operates on the specified 16-bit portion without modifying the other two portions. the content of the original accumulator is not affected (unless the same accumulator is specified as both source and destination). Unsigned Load of a Long Word to an Accumulator MOVE. This capability is particularly useful during the execution of DSC algorithms. If saturation occurs.” for a discussion of when it is appropriate to access an accumulator by its individual portions and when it is appropriate to access an entire accumulator.W B2 See Section 5. The extension register allows overflow during intermediate calculations without losing important information. “Accessing the Accumulator Registers.2 Accessing Portions of an Accumulator The instruction set provides for loading and storing one portion of an accumulator register without affecting the other two portions. Note that only one of the three portions of the accumulator is modified by each of these instructions—the other two portions remain unmodified.

it receives the low-order portion of the word.Data Arithmetic Logic Unit Writing the FF2 Portion: MOVE. the high-order portion is not used. 15 4 3 0 CDBR Bus Contents LSB of Not Used 15 Register FF2 Used as a Destination No Bits Present FF2 Register FF2 4 3 Word 0 Figure 5-7. the high-order portion (bits 15–4) is sign extended. When FF2 is read.W #$A987.A2 Before Execution A2 A X X X A1 X X X X A0 X X 0 A A2 D X X After Execution A1 X X X X A0 X X 0 35 32 31 16 15 35 32 31 16 15 Writing the FF1 Portion: MOVE. When FF2 is written. Writing the Accumulator by Portions Limiting does not occur for move instructions that specify one portion of an accumulator as the source operand. Writing the Accumulator Extension Registers (FF2) 5-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W #$ABCD.W #$1234. See Figure 5-8 on page 5-11.A1 Before Execution A2 A X X X A1 X X X X A0 X X 0 A A2 X 1 2 After Execution A1 3 4 X X A0 X X 0 35 32 31 16 15 35 32 31 16 15 Writing the FF0 Portion: MOVE.A0 Before Execution A2 A X X X A1 X X X X A0 X X 0 A A2 X X X After Execution A1 X X A 9 A0 8 7 0 35 32 31 16 15 35 32 31 16 15 Figure 5-6. See Figure 5-7. the register contents occupy the low-order portion (bits 3–0) of the word.

Write value first to A2 TFR A. Shift C2 into A1 with no sign extension MOVE.C .W R2.A . Example 5-4. the FF2 and FF0 portions are only accessible for the A and B registers.Accessing the Accumulator Registers 15 Register FF2 Used as a Source No Bits Present 4 3 FF2 0 Register FF2 LSB of Word 15 Sign Extension of FF2 4 3 Contents of FF2 0 CDBW Bus Contents Figure 5-8.W X0. Write C2 unsigned contents to final destination Example 5-5. and D0 accumulator portions are only accessible through a limited set of instructions: • • • • • • MOVE. with sign extension ASR16 C.A1 . Reading the Accumulator Extension Registers (FF2) Although the FF1 portion of every accumulator is accessible by all instructions. Transfer value from A to C accumulator Freescale Semiconductor Data Arithmetic Logic Unit 5-11 .R0 . Second technique MOVE.<register> BFCHG.X0 . BFTSTL BRSET. Shift C2 into X0 with sign extension MOVE.W A1. Shift the C1 register into C2 .C . Write C2 signed contents to final destination .R0 . BFSET. C0.A2 . Second technique. Writing a Value into the C2 Register .C1 ASL16 C . ORC.W R2. D2. ANDC. BFCLR. EORC. Reading the Contents of the C2 Register . First technique. The C2. Third technique (may saturate if SA = 1) MOVE. Write value first to C1 .W R3.W #xxxx. BRCLR Push register to stack (C2 and D2 only) Pop register from stack (C2 and D2 only) There are no other ways to read or write these accumulator portions directly. First technique MOVE. Shift the A1 register into C2 . Write value first to A1 ASL16 A. no sign extension LSR16 C. use the code in Example 5-4 and Example 5-5 (or similar code). NOTC BFTSTH. To read or write the values of C2 and D2.

Using the entire accumulator. 5. There is often no overflow protection when the result of an integer calculation is read. A2 receives sign extension . Because DSC algorithms process digital signals.2. “Saving and Restoring Accumulators. Reading a Word from an Accumulator with Saturation MOVE. 5-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Word move with saturation disabled . However. as in Example 5-6.A . Example 5-8.” The entire accumulator should also be used when long integers are loaded into the accumulators.3 Reading and Writing Integer Data to an Accumulator General integer and control processing typically uses 16-bit data. Example 5-9. Saturation is enabled Note the use of the A accumulator instead of the A1 register. as shown in Example 5-9.L A10.2. Saturation is ensured when the entire accumulator (FF) is specified as the source operand.2. the 36-bit result must often be written to a 16-bit memory location or D/A converter. Using this notation ensures that saturation is disabled.W X:(R0). Long word move without saturation Note the use of the A1 and A10 registers instead of the entire accumulator. A2 receives sign extension .4 Reading 16-Bit Results of DSC Algorithms A DSC algorithm can use the full 36-bit precision of an accumulator while performing DSC calculations such as digital filtering or matrix multiplications. Using the A accumulator enables saturation. A1 receives the 16-bit data .X:Long_Variable_1 . Reading an Integer Value from an Accumulator MOVE. Loading an Accumulator with an Integer Word MOVE. A. When an integer is loaded to an accumulator. Example 5-6. the accumulators are read with saturation disabled. is almost always preferable.X:Variable_1 MOVE.Data Arithmetic Logic Unit 5. it is important that saturation is enabled when a 36-bit accumulator value is converted to a 16-bit value so that signals that overflow 16 bits are clipped to the maximum positive or negative value appropriately.X:D_to_A_data .W A.L X:(R0). A0 receives the value $0000 In general. as demonstrated in Example 5-8. Such loading is accomplished using the instruction demonstrated in Example 5-6. Loading an Accumulator with a Long Integer MOVE.W A1. A1 receives the upper 16 of the 32 bits . as shown in Example 5-7. General integer and control processing does not use saturation or limiting. During integer processing. Typically. One exception to this rule is discussed in Section 5.A . Example 5-7. all accumulator loads of 16-bit data should clear the least significant portion of the accumulator and sign extend the extension portion. the A1 register should not be used when an accumulator is loaded with an integer. A0 receives the lower 16 of the 32 bits NOTE: It is not possible to use the A10 register when a long value is loaded into an accumulator.6. the 36 bits of the accumulator should reflect the 16-bit data correctly.

Restore A1 register MOVE. Restore extension register A faster way of saving and restoring accumulators is to access the stack 32 bits at a time.L A10.2.2. Save A0 register . Save extension register MOVE.W C1. as shown in Example 5-10. The MOVE.SP .X:(SP)+ . Example 5-12. clear A0 ASL16 A. such as in interrupt-handling routines. which can then be stored to memory or used for further computation. Restore A0 register MOVE.Sign extend D2.6 Saving and Restoring Accumulators There are times when an accumulator value must be saved to the stack. A0 set to $0000 MOVE.5 Converting a 36-Bit Accumulator to a 16-Bit Value There are three useful techniques for converting the 36-bit contents of an accumulator to a 16-bit value.C . “Status Register.Sign extend C2. Saturation is no longer required 5.W A. limiting only occurs when the extension register is in use.Extracting the A0 portion (no limiting) ASL16 A .A . Freescale Semiconductor Data Arithmetic Logic Unit 5-13 . where limiting is enabled. the accumulator must be saved with saturation disabled. because this instruction operates with saturation enabled and can inadvertently store the value $7FFF or $8000 if the extension register is in use.2.D .W A.Sign extend A2.A . the extension in use (E) bit of the status register is set. Reading a Long Value from an Accumulator with Limiting SAT A MOVE. the SAT instruction can be used. When the extension register is in use. This conversion is useful for processing word-sized operands (16 bits) because it guarantees that an accumulator contains correct sign extension and that the least significant 16 bits are all zeros. Point to first empty location MOVE.W X:(SP)-. Converting a 36-Bit Accumulator to a 16-Bit Value .Converting with no limiting MOVE.B .2. Saving the A accumulator to the stack ADDA #1. write A1.W A2. The solution is to save the individual portions of the accumulator. To be saved and restored properly.Accessing the Accumulator Registers There is no instruction for reading a long value from an accumulator with saturation enabled. If this function is required.Converting with limiting enabled MOVE.A1 .W A0. Save A1 register MOVE.” on page 8-7. 5. The three techniques appear in Example 5-11. Limit the value in the A accumulator .A2 .Sign extend A2.X:(SP)+ instruction should never be used when a value is being saved to the stack.Sign extend A2.W X:(SP)-.W A1. B0 set to $0000 . limit if required In the last technique.X:(SP)+ .W A.W A1.W X:(SP)-. Restoring the A accumulator from the stack MOVE.Sign extend B2. clear D0 .X:D_to_A_data . limit if required MOVE. write D1.X:(SP) . Refer to Section 8. Example 5-10. Saving and Restoring an Accumulator—Word Accesses . Example 5-11. as shown in Example 5-13 on page 5-14.A0 . as demonstrated in Example 5-12.

Bit Manipulation on a DSP56800E Accumulator . digital control. and other signal processing tasks. the stack pointer must be aligned to an odd word address. but it is available if desired. Integer arithmetic is typically used in controller code. For this reason. Example 5-14. “Accessing Long-Word Values Using Word Pointers. When calculations are performed in this mode. bit manipulation.L A2. Saturation can be selectively enabled and disabled so that intermediate calculations are performed without limiting and so that only the final results are limited. Note: A2 and A0 unmodified 5.can limit . Sets bits 11 through 8 and stores back to A1 . saturation is often used to prevent a problem that occurs without saturation: an output signal that is generated from a result where a computation overflows without saturation can be severely distorted (see Figure 5-27 on page 5-40). 5-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . for example) instead of the entire register.X:(SP) . Point to first empty location MOVE.A1 . saturation is not used when integers are processed.2. Saving the A accumulator to the Stack ADDA #2. A2 is sign extended and A0 is cleared .X:(SP)+ . Reads A1 with saturation disabled . array indexing and address computations. The “read” portion of this sequence is performed as if a MOVE. and written back to its original location. Typically. Saving and Restoring an Accumulator—Long Accesses . 5.A . and other general-purpose tasks.L A10. data is interpreted as fractional values. saturation must be disabled. In order for bit-manipulation operations to execute correctly. In this mode.7 Bit-Manipulation Operations on Accumulators The DSP56800E bit-manipulation instructions operate in a read-modify-write sequence: the value to be manipulated is read into a temporary register. vector and array processing. Save A1 and A0 registers . Reads A1 with saturation enabled .W instruction had been executed. as demonstrated in Example 5-14. Restoring the A accumulator from the Stack MOVE.Data Arithmetic Logic Unit Example 5-13. and thus may cause saturation to occur if an entire accumulator register is specified. Restore extension register In order for the accumulator to be pushed on the stack 32 bits at a time. modified according to the instruction.5. speech coders.A2 . bit-manipulation instructions should always be performed on the FF1 portion of a register (A1.L X:(SP)-. See Section 3. bit-exact algorithms. and computations are performed accordingly. Save extension register MOVE.L X:(SP)-.SP . Restore A1 and A0 (changes A2) MOVE.A .” on page 3-19 for more information. peripheral setup and handling.3 Fractional and Integer Arithmetic Fractional arithmetic is typically required for computation-intensive algorithms such as digital filters. BFSET using the A register BFSET #$0F00.3. Sets bits 11 through 8 and stores back to A1 . BFSET using the A1 register BFSET #$0F00.

999 999 999 5 15. Data Types and Range of Values Data Type Minimum Value Integer Unsigned byte Signed byte Unsigned word Signed word Unsigned long Signed long 0 –128 0 –32.767 4. long-word. Regardless of size.3. Freescale Semiconductor Data Arithmetic Logic Unit 5-15 . Signed fractional.535 32.999 999 999 5 255 127 65.147. refer to Section 3. The complete list of data types and their ranges appears in Table 5-2. One of these four types is used in each data ALU operation. “DSP56800E Data Types.Fractional and Integer Arithmetic 5.1 DSP56800E Data Types The DSP56800E architecture supports byte (8-bit). the four basic data types supported by the DSP56800E core are: • • • • Signed integer.294.999 969 482 4 0. and long-word (32-bit) integer data types.0 –1.All fractional values are rounded to 10 decimal digits of accuracy. It also supports word.967.0 0.147. Table 5-2. For more information on the DSP56800E data types.768 0 –2.483.” on page 3-5.648 Fractional1 Signed word Signed long word Signed 36-bit accumulator –1.483.295 2. Unsigned fractional.647 Maximum Value 1.2.0 –16. and accumulator (36-bit) fractional data types. Unsigned integer. word (16-bit).

B B. the MOVE.5. .W MOVE. and comparison operations are performed identically for both fractional and integer data values. FF2 contains sign extension and FF0 is cleared.A #64.W instruction loads the data into the FF1 portion of the accumulator as shown in Figure 5-10. . FF2 contains sign extension and FF0 is cleared.75) Save Result (limiting enabled) to Memory Figure 5-10.5 + 0. .X:RESULT .5” ($4000) into A (Sign extends A2 and clears A0) Load fraction value “0. Fractional Word Addition 5-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . .W instruction loads the data into the FF1 portion of the accumulator as shown in Figure 5-9. . .B B. . . . Load fraction value “0.X:RESULT .3.W #0.W ADD MOVE. To perform integer arithmetic operations with word-sized data. the decimal (or binary) point lines up correctly for fractional data in the two accumulators.W MOVE.25” ($2000) into B (Sign extends B2 and clears B0) Perform Fractional Word Addition (0.A A1. Note that the decimal (or binary) point lines up correctly for integer data in the two accumulators. Integer Word Addition Fractional word arithmetic is performed in a similar manner. The data ALU does not distinguish between the data types for these operations. Integer Addition of 2 Words: 32 + 64 = 96 Before Execution A $0 A2 B $0 B2 $0020 A1 $0040 B1 $0000 A0 $0000 B0 After Execution A $0 A2 $0060 A1 $0000 A0 MOVE. Load integer value “32” ($20) into A Accumulator (Sign extends A2 and clears A0) Load integer value “64” ($40) into B Accumulator (Sign extends B2 and clears B0) Perform Integer Word Addition (32 + 64 = $20 + $40 = $60 = 96) Save Result (without saturating) to Memory Figure 5-9.25. The MOVE.A #0. .2 Addition and Subtraction Addition. Again.5 + 0.W #32.25 = $4000 + $2000 = $6000 = 0.Data Arithmetic Logic Unit 5.25 = 0. .A A. . Fractional Addition: 0.75 Before Execution A $0 A2 B $0 B2 $4000 A1 $2000 B1 $0000 A0 $0000 B0 After Execution A $0 A2 $6000 A1 $0000 A0 MOVE.W ADD MOVE. subtraction.

L MOVE. .X:RESULT .25” ($2000) into B (Sign extends B2 and clears B0) (Note: Same format as a fractional long) Perform Fractional Long Addition (0. A10. .25. B .Fractional and Integer Arithmetic When a word-sized integer is added to a long-sized integer.5 + 0.L . . A10.A Load fraction long “0. no conversion is necessary because their binary points are the same. Fractional Addition of a Long and a Word: 0.L MOVE. B. . Integer Addition of a Long and a Word: 32 (long) + 64 (word) = 96 (long) Before Execution A $0 A2 $0000 A1 $0020 A0 After Execution A $0 A2 $0000 A1 $0060 A0 B $0 B2 $0040 B1 $0000 B0 B $0 B2 $0000 B1 $0040 B0 MOVE.L.5 (long) + 0.25 = $0:6000:0000 = 0. the word value must first be converted to a long value. Load integer long “32” ($20) into A Accumulator (Sign extends A2 and A1) Load integer word “64” ($40) into B Accumulator (Sign extends B2 and clears B0) Convert word value in B Accumulator to a long Perform Integer Word Addition (32 + 64 = $20 + $40 = $60 = 96) Save Result (limiting disabled) to Memory Figure 5-11.W ASR16 ADD MOVE.W ADD MOVE. .A .A instruction immediately before the MOVE. it is necessary to use the SAT A.X:RESULT . #0.A .75) Save Result (limiting disabled) to Memory Figure 5-12. Freescale Semiconductor Data Arithmetic Logic Unit 5-17 .B .5” ($4000:0000) into A (Sign extends A2) Load fraction word “0. #64. B. Adding a Word Integer to a Long-Word Integer When a word-sized fraction is added to a long-sized fraction as shown in Figure 5-12. .75 (long) Before Execution A $0 A2 B $0 B2 $4000 A1 $2000 B1 $0000 A0 $0000 B0 B After Execution A $0 A2 $0 B2 $6000 A1 $2000 B1 $0000 A0 0000 B0 MOVE. Adding a Word Fractional to a Long-Word Fractional If limiting is desired before the long value is written to memory.A .B . as shown in Figure 5-11.25 (word) = 0.L #32. . X:(R0).

signed. fractional result with the LSB always cleared. The difference amounts to a 1-bit shift of the final result. This intermediate result is then stored in one of the 36-bit accumulators. the intermediate results is rounded to 16 bits before being stored in the destination accumulator. fractional operands. MPYR. Comparison of Integer and Fractional Multiplication The MPY. and MACR instructions perform fractional multiplication and fractional multiply-accumulation.3.1 Fractional Multiplication Figure 5-14 on page 5-19 shows the multiplication of two 16-bit.Data Arithmetic Logic Unit 5. an extra zero bit is inserted in the LSB to give a 2N-bit result. as illustrated in Figure 5-13.3. 5-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The result of a fractional multiplication differs from the result of an integer multiplication.W. 5. signed. and the LSP is cleared.3. For correct integer multiplication.L. These types of multiplication are explained in more detail in the following sections. MAC. Any binary multiplication of two N-bit signed numbers gives a signed result that is 2N – 1 bits in length. Signed Multiplication: N × N = 2N – 1 Bits Integer S S S Fractional S X Signed Multiplier X Signed Multiplier S S MSP LSP S MSP LSP 0 N–1 Sign Extension N 2N Bits N 2N Bits N–1 Zero Fill Figure 5-13.L instructions perform integer multiplication. IMPY. with sign extension placed in the extension register.3 Multiplication The multiplication operation is not the same for integer and fractional arithmetic. The multiplication results in an intermediate 32-bit. For correct fractional multiplication. This (2N – 1)-bit result must then be properly placed in a field of 2N bits to fit correctly into the on-chip registers. The IMPY. an extra sign bit is inserted in the MSB to give a 2N-bit result. If rounding is specified (using the MPYR instruction). and IMAC.

W instruction to generate a 16-bit result in the FF1 portion of an accumulator Using the IMPY. The multiplication of two 16-bit.L instructions to generate a 36-bit full-precision result Each technique offers advantages for different types of computations. generating a 16-bit unrounded result. Fractional Multiplication (MPY) 5. Integer processing code usually requires only a 16-bit result.L and IMAC. signed. integer operands using the IMPY. provides this capability.Fractional and Integer Arithmetic Input Operand 1 16 Bits Input Operand 2 16 Bits s Signed Fractional Input Operands s X Signed Multiplier Signed 31-Bit Intermediate Multiplier Result s s 31 Bits Signed Fractional MPY Result EXT MSP 36 Bits LSP 0 Figure 5-14.W instruction gives a 16-bit.2 Integer Multiplication There are two techniques for performing integer multiplication on the DSC core: • • Using the IMPY. since greater precision is rarely needed. and the FF0 portion remains unchanged.3. Figure 5-15 on page 5-20 shows the multiply operation for integer arithmetic with a word-sized result. signed integer result that is placed in the FF1 portion of the accumulator.W.3. The corresponding extension register (FF2) is filled with sign extension. The word-size integer multiplication instruction. Freescale Semiconductor Data Arithmetic Logic Unit 5-19 . IMPY.

Data Arithmetic Logic Unit Input Operand 1 16 Bits Input Operand 2 16 Bits s Signed Integer Input Operands s X Signed Multiplier 16 Bits s 31 Bits Signed 31-Bit Intermediate Multiplier Result Signed Integer IMPY. with sign extension placed in the extension register (FF2).L) 5. Integer Multiplication with Long-Word-Sized Result (IMPY. Integer Multiplication with Word-Sized Result (IMPY.W Result (Sign Extension) MSP 16 Bits (Unchanged) Figure 5-15.3.L Result EXT MSP 36 Bits LSP Figure 5-16. when it is necessary to maintain the full 32-bit precision of an integer multiplication. The 32-bit long integer result is placed into the FF1 and FF0 portions of an accumulator. Input Operand 1 Signed Integer Input Operands 16 Bits s s Input Operand 2 16 Bits X Signed Multiplier Signed 31-Bit Intermediate Multiplier Result s s 31 Bits Signed Integer IMPY. Figure 5-16 shows an integer multiplication with a long-word result. The 5-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .3 Operand Re-Ordering for Multiplication Instructions The source operands for the three-operand multiplication and multiply-accumulate instructions must be specified in a particular order so that they are dispatched to the appropriate units in the data ALU.L instruction.3. use the IMPY.W) At other times.

S2.S2. The most general division algorithms are the fractional and integer algorithms for four-quadrant division.D IMPY.1 which generate both a quotient and a remainder.S2.3.S2. Y1 specified as first source operand This instruction performs the same function. calculating 1 bit of the result with each execution.L S1. X0 specified as first source operand This instruction specifies the two source operands in the wrong order (the X0 register cannot be specified as the first operand). Four-quadrant division is so called because it generates correct results for any combination of positive or negative dividends and divisors. and the divisor (denominator) is a 16-bit fractional or integer value. Note that none of the algorithms that are presented here apply to extended-precision division.S2.D IMAC. but with the operands in the proper order.S2. Algorithms for performing division can vary.A .D MPYR –S1.S2. 5. that the instruction dis-assembles as the re-ordered version.D IMPY. Note that the instruction always dis-assembles with the second ordering of operands. select the appropriate division algorithm. Freescale Semiconductor Data Arithmetic Logic Unit 5-21 .S2. Note.X0. which requires more than 16 quotient bits. consider the following key questions: • • • • • • • • Are both operands always guaranteed to be positive? Are operands fractional or integer? Is the quotient all that is needed.S2. The assembler replaces this instruction with the following: MPY -Y1. For example: MPY -X0. quicker algorithms can be used when positive numbers are divided or when the remainder is not required. The DIV instruction performs a single division iteration.D MAC –S1. depending on the values being divided and whether or not the remainder after integer division must also be calculated.A . To formulate the correct approach.Y1. A full division requires that the DIV instruction be executed 16 times.S2.L S1. Simpler. These algorithms require the most time to complete and use the most registers.D MPY S1.S2.4 Division Fractional and integer division of both positive and signed values is supported using the DIV instruction.D MACR S1.D MACR –S1. 1.D MPYR S1. however.Fractional and Integer Arithmetic DSP56800E assembler automatically rearranges the source operands for the following operations if they are not specified in the required order: MAC S1. or is the remainder needed as well? Will the calculated quotient fit in 16 bits in integer division? Are the operands signed or unsigned? How many bits of precision are in the dividend? What about overflow in fractional and integer division? Will there be “integer division” effects? Once you answer these questions. The dividend (numerator) is a 32-bit fractional or 31-bit integer value.D MPY –S1.D This re-ordering by the assembler has no impact on the execution of the instruction.W S1.

A1 <. A <. Clear carry bit: required for 1st DIV instr . Setup MOVE.W X0. signed quotient in Y1. A <. is in Y1 and the correct remainder is in A1) .A . Y1 <.Y1 . Signed Data (B1:B0 / X0) .Restored remainder BRCLR #$8000.A . If correct result is positive. it is the slowest and uses the most resources.N . Signed Data (B1:B0 / X0) .A . Example 5-15 presents one algorithm for division with fractional numbers and another algorithm for the division of integer numbers.Y1 . Setup ASL B . Because this algorithm handles the most general case. Force dividend positive EOR X0. Signed Division with Remainder .True quotient MOVE. Else negate to get correct negative result QDONE MOVE. Clear carry bit: required for 1st DIV instr .W B1.B .4.A . Save sign bit of dividend (B1) in MSB of A1 MOVEU. Else negate to get correct negative result QDONE MOVE. signed values. Save sign bit of dividend (B1) in MSB of A1 MOVEU. Y1 <. Force dividend positive EOR X0.W A0.SR . then done NEG B . Four-Quadrant Division of Integer.B . correct .1 General-Purpose Four-Quadrant Division This general-purpose algorithm generates both a correct quotient and a correct remainder when dividing any combination of positive or negative.WB1. two’s-complement.WB1.W X0.W A0.A BGE QDONE .A .W #0.Signed divisor ABS A . remainder in A1) 5-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Division REP 16 DIV X0.N.A0 NEG A ASR B . Save sign bit of dividend (B1) in MSB of N ABS B . (At this point.N. Four-Quadrant Division of Fractional.Data Arithmetic Logic Unit 5.W B1.SR . Correct quotient TFR B.N . division MOVE. then done NEG B .3. Shift required for correct integer remainder DONE .Restored remainder BRCLR #$8000.Y1 .Signed divisor ABS A .Y1 .DONE MOVE.A0 NEG A DONE .Division REP 16 DIV X0. A <.A BGE QDONE . Save sign bit of dividend (B1) in MSB of N ABS B .W #0. Generates Signed quotient and remainder . A1 <.Absolute value of divisor ADD B. the correctly signed quotient .True quotient MOVE.DONE MOVE. If correct result is positive. (At this point. A <.Absolute Value of divisor ADD B. Save sign bit of quotient in N bit of SR BFCLR #$0001. Shift of dividend required for integer . Save sign bit of quotient in N bit of SR BFCLR #$0001. Correct quotient TFR B. Generates Signed quotient and remainder .A . Example 5-15.

(At this point. The example presents different algorithms for the division of fractional and integer numbers.W B0. the positive quotient is in .SR . B0 but the remainder is not yet correct) ADD X0. the positive quotient is in . such as the following: 64 ÷ 9 = 7 (remainder 1) This operation can be calculated correctly with the code presented in Example 5-16. Clear carry bit: required for 1st DIV instruction REP 16 DIV X0.Y1 .B . Both algorithms generate the correct positive quotient and positive remainder. The example presents different algorithms for the division of fractional and integer numbers. (At this point. Example 5-16. Form positive quotient in B0 ADD X0. Save quotient in Y1 .4.B . remainder is in B1) 5.SR . Freescale Semiconductor Data Arithmetic Logic Unit 5-23 . Restore remainder in B1 .2 Positive Dividend and Divisor with Remainder If both the dividend and divisor are positive. the correct positive . Division of Positive Fractional Data (B1:B0 / X0) BFCLR #$0001. Division of Positive Integer Data (B1:B0 / X0) ASL B . Consider a simple positive division with a remainder. Shift of dividend required for integer . Required for correct integer remainder .4.3. Unsigned Division with Remainder . division BFCLR #$0001.3 Signed Dividend and Divisor with No Remainder An algorithm that is slightly more complex but still more efficient than the general-purpose algorithm can be used for signed values when a correct remainder is not required. signed. B0 and the positive remainder is in B1) . Clear carry bit: required for 1st DIV instruction REP 16 DIV X0. two’s-complement numbers. Restore remainder in B1 ASR B .B . The algorithms in Example 5-17 on page 5-24 are faster than the general-purpose algorithms because they generate the quotient only. Form positive quotient in B0 MOVE. a more efficient algorithm can replace the general-purpose four-quadrant approach.B .3. (At this point. The algorithms in this code are the fastest and require the least amount of program memory.Fractional and Integer Arithmetic 5. they do not generate a correct remainder.

W B.B .0 – 2–15 When the magnitude of the dividend is larger than the magnitude of the divisor.Y1 . If correct result is positive.SR . Save sign bit of quotient in N bit of SR BFCLR #$0001.Y1 . division MOVE. Correct quotient BGE DONE . Clear carry bit: required for 1st DIV instr . no remainder .B . (At this point.SR . signed.Y1 . Save Sign Bit of dividend (B1) in MSB of Y1 ABS B . Force dividend positive EOR X0.4. Setup MOVE. Save Sign Bit of dividend (B1) in MSB of Y1 ABS B . Four-Quadrant Division of Signed Integer Data (B1:B0 / X0) . Save sign bit of quotient in N bit of SR BFCLR #$0001. Force dividend positive EOR X0. (At this point. 5-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Correct quotient BGE DONE . the result must be a 16-bit.W B.3.0 ≤ quotient < +1. the correctly signed . Generates signed quotient only. correct) 5.Y1 . Four-Quadrant Division of Signed Fractional Data (B1:B0 / X0) . the result is always larger in magnitude than 1. Integer division can also overflow. For the division of fractional numbers. Else negate to get correct negative result DONE .4 Division Overflow Both integer and fractional division are subject to division overflow. Signed DIvision Without Remainder . then done NEG B . If correct result is positive. Shift of dividend required for integer . Division REP 16 DIV X0. Form positive quotient in B0 . Correct execution without overflow occurs only when the result of the division fits within the range of a signed 16-bit word: –2–15 ≤ quotient ≤ [215 – 1] The numerator should be scaled if necessary to ensure this condition. fractional value that satisfies the following equation: –1. this relation can never be satisfied. Else negate to get correct negative result DONE . Clear carry bit: required for 1st DIV instr . then done NEG B . quotient is in B0 but the remainder is not . no remainder . Generates signed quotient only.Data Arithmetic Logic Unit Example 5-17. Division REP 16 DIV X0. Overflow occurs when the correct value of the quotient does not fit into the destination available to store it. correct) . Setup ASL B . quotient is in B0 but the remainder is not . Form positive quotient in B0 .0. The dividend should be scaled to avoid this condition. the correctly signed .

Freescale Semiconductor Data Arithmetic Logic Unit 5-25 . “Instruction Set Details. Figure 5-18 on page 5-26 shows both right and left shifting of a 16-bit word.and 32-bit operands. “Instruction Set Introduction. logical operations are only performed on integer values.and 32-bit logical operations.1 Shifting 16-Bit Words The shifter performs single-cycle arithmetic or logical shifts of 0 to 15 bits on 16-bit word values. An arithmetic right shift of 1 bit corresponds to a signed division by two. but only for 16-bit operands.3. Typically. Y0.5 Logical Operations The logic unit in the data ALU can perform 16.3. an arithmetic left shift of 1 bit corresponds to a multiplication by two. and a logical right shift of 1 bit corresponds to an unsigned division by two. and EOR operations are supported for both 16.” for more information on the logical operation instructions. A logical NOT operation is also supported.Fractional and Integer Arithmetic 5. 5. 16-Bit Logical Operation: AND. See Chapter 4. 5. Logical operations on 32-bit values are performed on the FF1:FF0 portion of the accumulators and can also use the 32-bit Y register. they operate on the FF1 portion of an accumulator register or on any of the 16-bit data registers (X0. but the DSP56800E supports logical operations on fractional values as well.W Before Execution A2 A 1 2 3 A1 4 5 6 7 A0 8 9 0 A A2 1 0 0 #$F. 16.and 32-bit logical operations. Figure 5-17 shows examples of 16.6 Shifting Operations A variety of shifting operations can be done on both integer and fractional data values.” and the appropriate sections in Appendix A.and 32-Bit Logical Operations Logical AND. When logical operations are performed on 16-bit values. OR.L Before Execution A2 A 1 2 3 A1 4 5 6 7 A0 8 9 0 A A2 1 #$F. For both types of data.A After Execution A1 0 5 6 7 A0 8 9 0 35 32 31 16 15 35 32 31 16 15 32-Bit Logical Operation: AND.A After Execution A1 0 0 0 0 0 0 A0 0 9 0 35 32 31 16 15 35 32 31 16 15 Figure 5-17.6. and Y1). regardless of whether they represent integer or fractional values.3. All logical operations are performed on the raw bits that are contained in the operands.

nor are bits in the MSP ever shifted into the extension. 5.L instruction shifts right). the shifting is performed in the opposite direction by the absolute value of the number of bits to be shifted (for example.W) Figure 5-18. $AAAACCCC 32 Shifting Unit $4 4 $5555CCCC 32 Shifting Unit $4 4 EXT A F F MSP A A A A LSP C C C 0 A EXT 0 5 MSP 5 5 C C LSP C C 0 0 35 32 31 16 15 35 32 31 16 15 Example: Right Shifting (ASRR.2 Shifting 32-Bit Long Words The shifter can also perform arithmetic or logical shifts of 0 to 31 bits on 32-bit data. Note that sign extension is always performed for 16-bit shifts. the extension register is sign extended.L) Figure 5-19. The extension bits are never shifted into the MSP of an accumulator.W) Example: Left Shifting (ASLL. The extension bits are never shifted into the MSP of an accumulator. If the number of bits to shift is specified by a register and is a negative value. In the unusual case in which a negative value is shifted by zero and its destination is an accumulator. nor are bits in the MSP ever shifted into the extension. Figure 5-19 shows both right and left shifting of a 32-bit long word.3.6. At the end of an arithmetic shift. 5-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . an ASRR. If the number of bits to be shifted is specified using a data ALU register and is positive.Data Arithmetic Logic Unit $AAAA 16 $4 4 $AAAA 16 $5 4 Barrel Shifting Unit Barrel Shifting Unit EXT A F F MSP A A A 0 LSP 0 0 0 0 A EXT 0 5 MSP 5 4 0 0 LSP 0 0 0 0 35 32 31 16 15 35 32 31 16 15 Example: Right Shifting (ASRR.L instruction shifts left). the extension register of the destination is loaded with $F instead of $0. Arithmetic Shifts on 16-Bit Words At the completion of a 16-bit logical or arithmetic shift. the extension register is loaded with sign extension and the LSP is cleared. an ASRR. the shifting is performed in the direction indicated by the mnemonic (for example.L) Example: Left Shifting (ASLL. Arithmetic Shifts on 32-Bit Long Words At the completion of a 32-bit logical shift. the extension register is always cleared.

1. These instructions perform an operation based on the state of the condition codes.” on page 3-6) and which status bits are affected when comparing signed and unsigned numbers. 5. respectively. subtraction. but the condition code computations are different.4. filling the FF0 portion with $0000 and the extension register with what were previously the 4 LSBs of the original FF1 portion. For these two instructions.4 Shifting with Accumulation The ASRAC and LSRAC instructions are unique in that they arithmetically or logically right shift a 16-bit value into a 32-bit field and add the result to the previous value of the accumulator. Specifically.6. the original 16-bit value is represented as a 32-bit integer. LSR16 and ASR16 logically or arithmetically shift a 36-bit accumulator 16 bits to the right.4 Unsigned Arithmetic Operations The DSP56800E can perform both unsigned and signed arithmetic operations. The difference between signed and unsigned operations involves how the data is interpreted (Section 3. comparison.3. the FF1 portion must be shifted into the FF0 portion.3. and LSR16—shift an entire 36-bit accumulator by 16 bits in 1 cycle. and the FF2 portion must be shifted into the 4 LSBs of the FF1 portion.1 Condition Codes for Unsigned Operations Unsigned arithmetic operations such as addition. 5. the least significant bits of the MSP are shifted into the most significant bits of the LSP.6. The ASL16 instruction shifts a 36-bit accumulator 16 bits to the left.Unsigned Arithmetic Operations 5.2. as for signed computations. such as Bcc and Jcc. ASR16. In this manner. and comparison instructions work for both signed and unsigned values. The addition. The difference in the way condition codes are calculated is most evident with any of the conditional jump and branch instructions. multiplication. and in the same manner.3 Shifting Accumulators by 16 Bits Three instructions—ASL16. 5. the following conditions should be used for signed values: • • • • • • • • GE—greater than or equal to LE—less than or equal to GT—greater than LT—less than HS (high or same)—unsigned greater than or equal to LS (low or same)—unsigned less than or equal to HI (high)—unsigned greater than LO (low)—unsigned less than These conditions should be used instead for unsigned values: Note that the HS condition is identical to carry clear (CC) and that LO is identical to carry set (CS). and logical operations are performed with the same instructions. which may be set differently depending on whether a signed or unsigned calculation has been performed to generate the value tested by the instruction. “Data Formats. Freescale Semiconductor Data Arithmetic Logic Unit 5-27 . When it is necessary to convert a 16-bit value to a 32-bit integer. and are useful for converting 16-bit values to 32-bit long values that are unsigned and signed. subtraction.

use of the CM bit is not generally recommended. Place unsigned value in FF0 portion . exhibit this problem. Multiply 2 unsigned words The IMACUS and IMPYSU instructions are provided for multiplying one signed value and one unsigned value. Load 1 word from memory . Place unsigned value in FF0 portion .L for long words Using these instructions guarantees that the extension registers are not considered when condition codes are calculated. the recommended solution was to set the CM bit in the OMR register before using any of the unsigned jump and branch conditions (HS. “Instruction Set Details.B for bytes TST. among others.B0. and the other is in the lower portion (FF0). For DSP56800E code.” for more information on the placement of operands. and LO) after a TST or CMP instruction. instructions that exactly match the size of the data should be used: • • • TST. On the DSP56800. However. 5. 5-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .B and CMP.L and CMP. be careful.B LSR16 A LSR16 B IMPYUU A0.W X:(R0). See the entries for these instructions in Appendix A. LS. HI. Multiplication of 2 Unsigned Words MOVE. Again. Instead. The TST and CMP instructions.2 Unsigned Single-Precision Multiplication Unsigned multiplications are supported with the IMPYUU instruction. which accepts two 16-bit multiplicands from the lowest portion of the accumulators (FF0).Data Arithmetic Logic Unit Accumulator extension registers can also interfere with the correct calculation of condition codes for unsigned numbers when an arithmetic operation generates a 36-bit result. because one of the 16-bit multiplicands is in the upper portion (FF1) of an accumulator. Example 5-18.D . Load 1 word from memory . and the other is in the lower portion (FF0).W X:(SP-2). because one of the 16-bit multiplicands is in the upper portion (FF1) of an accumulator.W for words TST.4. This instruction is illustrated in Example 5-18.W and CMP. be careful with these instructions. Fractional unsigned multiplications are supported with the MPYSU and MACSU instructions.A MOVE.

assist in performing extended-precision addition and subtraction. Example 5-19.L X:$102. . Get Operand1 (Lower 32 bits.5 Extended. .Y ADC Y.A . with the carry out of the low-order addition added into the high-order portion.Y SUB Y. 64-Bit Subtraction X:$103:X:$102:X:$101:X:$100 – X:$203:X:$202:X:$201:X:$200 = A2:A1:A0:B1:B0 MOVE. .L X:$100.L X:$200.L X:$100. To assist in implementing these algorithms.and Multi-Precision Operations 5. with the second product offset by 16 bits so the products align properly. resulting in a 36-bit product.L X:$102.A MOVE.B MOVE. The high-order subtraction is then performed. .B MOVE.Y SBC Y.Y ADD Y. sign ext) bits) bits) bits) Subtraction is carried out in a similar manner. Figure 5-20 on page 5-30 shows the process for multiplying a 16-bit value with a 32-bit value. . the DSP56800E provides several instructions targeted toward extended-precision and multi-precision calculations. The 16-bit value is multiplied by each of the 16-bit halves of the larger value.and 32-bit operations that the DSP56800E architecture supports. .and Multi-Precision Operations Some algorithms require calculations that exceed the range or precision of the 16.5. Get Operand1 (Lower 32 Get Operand2 (Lower 32 First 32-bit addition. with any borrow being reflected in the carry bit in the status register.5.B MOVE. The final sum is stored in both the A and B registers. .L X:$200. .B .A MOVE. Example 5-19 illustrates the use of the ADC instruction in 64-bit addition.2 Multi-Precision Fractional Multiplication Two instructions are provided to assist with multi-precision multiplications: MPYSU and MACSU. sign ext. Freescale Semiconductor Data Arithmetic Logic Unit 5-29 .1 Extended-Precision Addition and Subtraction Two instructions. Example 5-20.) Get Operand2 (Lower 32 bits) First 32-bit subtraction Get Operand1 (Upper 32 bits) Get Operand2 (Upper 32 bits) Second 32-bit subtraction 5.L X:$202. . 32 bits at a time. ADC and SBC. 64-Bit Addition X:$103:X:$102:X:$101:X:$100 + X:$203:X:$202:X:$201:X:$200 = A2:A1:A0:B1:B0 MOVE.B MOVE. Get Operand1 (Upper 32 Get Operand2 (Upper 32 Second 32-bit addition bits. the low-order 32-bit subtraction is performed first. When these instructions are used. Two 64-bit operands in memory are summed. the multiplier accepts one signed two’s-complement operand and one unsigned two’s-complement operand.L X:$202. As illustrated in Example 5-20. and the results are summed. . 5.Extended. with the borrow subtracted to achieve the correct result.

as shown in the code in Example 5-21. Treating the lower half of the 32-bit input value as unsigned ensures that the correct value is generated for the later addition.Y1. The code for this figure appears in Example 5-22 on page 5-32. . Figure 5-21 on page 5-31 shows two 32-bit values being multiplied to generate a 64-bit result. 4 Instruction Words) MPYSU X0. Single-Precision-Times-Double-Precision Signed Multiplication The key to making the multiplication work is the use of the MPYSU instruction.A ASR16 A MAC X0. A2 A1 36 Bits A0 Figure 5-20. Single-Precision times Lower Portion 16-bit Arithmetic Right Shift Single-Precision times Upper Portion and added to Previous Extended-precision 32-bit multiplication works similarly. 5-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Data Arithmetic Logic Unit 32 Bits Y1 Y0 16 Bits X0 × Signed × Unsigned X0 × Y0 Signed × Signed X0 × Y1 + Sign Ext. Example 5-21. . .A . Fractional Single-Precision Times Double-Precision—Both Signed (4 Cycles.Y0.

Extended.and Multi-Precision Operations 32 Bits OP1UPR 32 Bits OP2UPR OP2LWR OP1LWR × Unsigned × Unsigned OP2LWR × OP1LWR Unsigned × Signed OP2LWR × OP1UPR Signed × Unsigned OP2UPR × OP1LWR Signed × Signed OP2UPR × OP1UPR + RES2UPR RES2LWR 64 Bits RES1UPR RES1LWR Figure 5-21. Double-Precision-Times-Double-Precision Signed Multiplication Freescale Semiconductor Data Arithmetic Logic Unit 5-31 .

3.W X:OP2UPR.B1.B1. X:RES1UPR:RES1LWR = Lower 32 bits of Fractional . Isolate upper 16 bits for accumulation IMAC.X:RES2 . Propagate bit 31 to EXT of D ASL D . Multi-precision integer multiplication is described in Section 5. Multiplying Two Fractional Double-Precision Values X:OP1UPR:X:OP1LWR × X:OP2UPR:X:OP2LWR (Both 32-Bit Operands Are Signed) .L to move 32-bit value to A MOVE. Result . second in FF1) IMACUS—multiply-accumulate with one unsigned and one signed operand (unsigned 16-bit operand located in FF0 portion. Result ROL.W X:OP1UPR.A0 . Get first operand from memory MOVE. signed in FF1) 5-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W X:OP2LWR.3 Multi-Precision Integer Multiplication Four provided instructions assist with multi-precision integer multiplications.L to move 32-bit value to B IMPYUU A0.B . X:RES2UPR:RES2LWR = Upper 32 bits of Fractional .D1 . Correction for Fractional Result (C => RES2UPR:RES2LWR. Perform upper portion of multiplication .L D10. MSP of D for RES1UPR . the multiplier accepts signed two’s-complement operands and unsigned two’s-complement operands.L D .Y1 .X:RES1 . Each instruction specifies not only which source operand is signed or unsigned.C .Y IMACUS A0. Signed x Unsigned Multiplication with Accumulation IMPYSU A1. Lower 16 bits Correspond to Lower 32 bits of Final Result ASL16 C.W X:OP1LWR.W Y1. Could use a MOVE. Result MOVE. Perform lower portion of multiplication LSR16 D.C . This type of multiplication can also be performed as a 32 × 32 → 64-bit integer multiplication with a final left shift of the result.B0 .L A1. Corresponds to lower 32 bits of Final Fractional . When these instructions are used.B0.. save lower 16 bits of final result MOVE.C .” 5. but also the location of the 16-bit operand (FF1 or FF0 portion of an accumulator): • • IMACUU—multiply-accumulate with two unsigned operands (first 16-bit operand located in FF0 portion. Get first operand from memory MOVE. ====> C2 may not be correct after the result is generated .Y . Accumulate result .L C . Could use a MOVE. D => RES1UPR:RES1LWR) SXT.Y . Unsigned x Signed Multiplication with Accumulation MOVE.5.5. Storing 64-bit Fractional Result in Memory MOVE. Isolate upper 16 bits for accumulation . Upper 16 bits Correspond to Upper 32 bits of Final Result ASR16 C .L C10. Result . Unsigned x Unsigned Multiplication.B0. Perform signed multiplication with upper 16 bits ADD Y. “Multi-Precision Integer Multiplication. Perform signed multiplication with upper 16 bits ADD Y. D has lower 32 bits of result .A . Corresponds to upper 32 bits of Final Fractional . Save lower 16 bits of result MOVE. Accumulate result .Data Arithmetic Logic Unit Example 5-22.D .C .L #0.. LSP of D for RES1LWR .

Also note that C2 in the final result is modified and does not contain valid data.C Multiplication .Signed x Signed 32-Bit Integer IMPYSU A1.5. Y1:Y0 = unsigned A0 x signed B1 + Y1:Y0 . 32 Bits A1 32 Bits A0 × B1 B0 Unsigned × Unsigned A0 × B0 Signed × Unsigned A1 × B0 Unsigned × Signed A0 × B1 + C2 C1 32 Bits C0 Figure 5-22. 32-Bit × 32-Bit –> 32-Bit Signed Integer Multiplication Example 5-23. Y1:Y0 = signed A1 x unsigned B0 . does not require the A1 × B1 product. Combine Results: final 32-bit result in C This example.B1.1 Signed 32-Bit × Signed 32-Bit with 32-Bit Result Figure 5-22 and Example 5-23 demonstrate a signed multiplication of two 32-bit long values that generates a 32-bit long integer result.B0. C2:C1:C0 = unsigned A0 x unsigned B0 . unsigned in FF0) IMPYUU—multiplication with two unsigned operands (2 cases) (each unsigned 16-bit operand located in the FF0 portion) (first 16-bit operand located in FF1 portion. which only affects the upper 32 bits of the result. Freescale Semiconductor Data Arithmetic Logic Unit 5-33 .B0.Y IMACUS A0.Y IMPYUU A0.3. Multiplying Two Signed Long Integers C1:C0 = A1:A0 × B1:B0 (Both 32-Bit Operands Are Signed) .C ADD Y0.Extended. which saves only the lower 32 bits of the result. second in FF0) The following sections demonstrate the use of these instructions in multi-precision integer multiplications.and Multi-Precision Operations • • IMPYSU—multiplication with one signed and one unsigned operand (signed 16-bit operand located in FF1 portion. 5.

which only affects the upper 32 bits of the result. does not require the A1 × B1 product. 5.3 Signed 32-Bit × Signed 32-Bit with 64-Bit Result Figure 5-24 on page 5-35 and Example 5-25 on page 5-35 demonstrate a signed multiplication of two 32-bit long values that generates a 64-bit full-precision integer result.B1. which saves only the lower 32 bits of the result. Also note that C2 in the final result is modified and does not contain valid data. 32-Bit × 32-Bit –> 32-Bit Unsigned Integer Multiplication Example 5-24.3.Data Arithmetic Logic Unit 5.5. C2:C1:C0 = unsigned A0 x unsigned B0 ADD Y0. 32 Bits A1 32 Bits A0 × B1 B0 Unsigned × Unsigned A0 × B0 Unsigned × Unsigned A1 × B0 Unsigned × Unsigned A0 × B1 + C2 C1 32 Bits C0 Figure 5-23.C .2 Unsigned 32-Bit × Unsigned 32-Bit with 32-Bit Result Figure 5-23 and Example 5-24 demonstrate an unsigned multiplication of two 32-bit long values that generates a 32-bit long integer result.Y .3.B0. Combine Results: final 32-bit result in C This example.Y .5. Multiplying Two Unsigned Long Integers C1:C0 = A1:A0 × B1:B0 (Both 32-Bit Operands Are Unsigned) .B0. Y1:Y0 = unsigned A0 x signed B1 + Y1:Y0 IMPYUU A0. 5-34 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Unsigned x Unsigned 32-Bit Integer Multiplication IMPYUU A1. Y1:Y0 = signed A1 x unsigned B0 IMACUU A0.C .

D LSR16 D.4 Other Applications of Multi-Precision Integer Multiplication In addition to the examples in Section 5. Align upper word of first product in C .and Multi-Precision Operations 32 Bits A1 32 Bits A0 × B1 B0 Unsigned × Unsigned A0 × B0 Signed × Unsigned A1 × B0 Unsigned × Signed A0 × B1 Signed × Signed A0 × B1 + C2 C1 C0 64 Bits D1 D0 Figure 5-24.Y IMACUS A0. C2:C1:C0 now contain upper result 5.” through Section 5. “Signed 32-Bit × Signed 32-Bit with 32-Bit Result. Y1:Y0 = unsigned A0 x signed B1 + Y1:Y0 .Y ADD Y.Y1 MOVE.3.3.B0.D1 ASR16 C. 32-Bit × 32-Bit –> 64-Bit Signed Integer Multiplication Example 5-25.” the multi-precision integer multiplication instructions can be applied in other cases.B. .B1.Extended. Y1:Y0 = signed A1 x unsigned B0 .3. The case of a signed 16-bit times a signed 32-bit with a 32-bit result is shown in Example 5-26 on page 5-36. Multiplying Two Signed Long Integers D2:D1:D0:C1:C0 = A1:A0 × B1:B0 (Both 32-Bit Operands Are Signed) . “Signed 32-Bit × Signed 32-Bit with 64-Bit Result.L A. Clears the 32-bit Y register .C ASL16 C0.5.C Multiplication with 64-Bit Result . D2:D1:D0 = unsigned A0 x unsigned B0 . such as the case of a signed 32-bit times an unsigned 32-bit.3.C IMAC.W Y1.5.C ASL16 X0.1.Y ADD Y.B0. .C IMPYSU A1. Copy next 16 bits of result to D1 . Freescale Semiconductor Data Arithmetic Logic Unit 5-35 . .5.Signed x Signed 32-Bit Integer IMPYUU A0.

and all bits to the left are merely the sign and sign extension. calculations can be performed. a normalized value has 1 sign bit and 31 significant digits. Bits to the left of the binary point should contain only the sign and sign extension. Y1:Y0 = signed A1 x signed B1 ADD Y0. The normalizing capabilities provided by the DSP56800E architecture can help correct this problem.B.B0. On the DSP56800E. Figure 5-26 on page 5-37 shows a second value before and after normalization.6 Normalizing For many algorithms. Multiplying Signed 16-Bit Word with Signed 32-Bit Long C1:C0 = A1 × B1:B0 (Both Operands Are Signed) . Normalizing a Small Negative Value The first value in Figure 5-25 is not normalized: the first significant bit in the value is bit 21. the value has been right shifted 3 bits to place the most significant bit to the right of the binary point. In this example. A value can be normalized. The second value in Figure 5-25 shows the same value normalized.C . when very small fractional values are worked with. The value has been left shifted 10 bits. 5.Data Arithmetic Logic Unit Example 5-26.1 Normalized Values On the DSP56800E architecture. Y1:Y0 = signed A1 x unsigned B0 TFR Y. there may not be enough binary digits in an accumulator to accurately reflect a value. Thus. in an accumulator register.L A. Figure 5-25 shows both non-normalized and normalized values in an accumulator. 5-36 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Y .6. Normalizing involves scaling a value to a known magnitude. Before Normalization A2 A F F F A1 E 4 6 C A0 3 1 0 A A2 F 9 1 After Normalization A1 B 0 C 4 A0 0 0 0 35 32 31 16 15 35 32 31 16 15 Figure 5-25.Y . maximum precision in calculations is required to ensure proper results. eliminating the sign-extension bits and placing the sign in bit 31 and the most significant bit in bit 30. a value is considered normalized if there are no significant digits to the left of the binary point. For example. the original magnitude can be saved. and the result can be scaled back to its original magnitude.C IMPY.Signed 16-Bit x Signed 32-Bit Integer Multiplication IMPYSU A1. a normalized value is one that has no significant digits to the left of the binary point. Combine Results: final 32-bit result in C 5.

NORM is executed repeatedly until the accumulator value is fully normalized.Normalizing Before Normalization A2 A 2 7 C A1 C 3 4 0 A0 0 0 0 A A2 0 4 After Normalization A1 F 9 8 6 8 A0 0 0 0 35 32 31 16 15 35 32 31 16 15 Figure 5-26. this alignment ensures that positive values p lie in the range 0. The CLB instruction is used to determine the number of leading zeros or ones in a value. The amount by which the values were shifted can be used to scale the normalized values back to their original magnitudes. so a TST instruction on the accumulator that is to be normalized must be executed before NORM to ensure that the condition codes are set properly. NORM must be executed 31 times to ensure that the value is fully normalized. fractional Freescale Semiconductor Data Arithmetic Logic Unit 5-37 . Example 5-28 shows this method.6.2 Normalizing Methods There are two methods for normalizing a value in an accumulator. Example 5-27 shows the general method.A .L X0. NORM has no effect on already normalized values. However. The other method executes much more quickly. Because up to 31 shifts might be required. establish condition codes for NORM . do 31 normalization steps . a REP instruction is used to execute NORM for the proper number of times. but is limited in the values it can normalize.0 and that negative values n lie in the range –1. Each time NORM is executed. and Z bits in the status register to determine how a value should be shifted. In Example 5-27. On the DSP56800E architecture. U. and a simple shift instruction normalizes the accumulator. place # of leading bits . Example 5-28. requiring only two instructions (the NORM technique requires 33 instructions to be executed). using the NORM instruction. Example 5-27. The NORM instruction can be used to normalize a full 36-bit accumulator. the A accumulator is normalized.5 < p < 1. the accumulator to be normalized is shifted 1 bit right or left.X0 ASLL. it is not possible to determine in advance how many shifts will be required to normalize a value. Because the extension portion of the accumulator is ignored by CLB. and the R0 register holds the number of shifts required to normalize A. Normalizing a Large Positive Value In both Figure 5-25 on page 5-36 and Figure 5-26. the normalized values are aligned so that the most significant bit is placed in bit 30. as necessary. is more flexible but slow.1 into X .5. Although it wastes time to execute NORM more times than is necessary. execute a normalization step The NORM instruction uses the E. 5. the CLB instruction only counts leading bits in the 32-bit MSP:LSP portion of the accumulator. At the end of the sequence in Example 5-27. There is a second method for normalizing an accumulator that is less flexible but much faster.A . so there are no adverse side effects.0 < n < –0. Normalizing with the NORM Instruction TST REP NORM A #31 R0. Unfortunately. and a second register is incremented. Normalizing with a Shift Instruction CLB A. shift A left to normalize This method is clearly more efficient. One.

the second register (R0 and X0 in Example 5-27 and Example 5-28 on page 5-37.BP—compare two byte values CMP. where the extension portion of the accumulator was considered when condition codes were calculated. consider a number of factors: • • • • • The size of the operands. Setting the CM bit in the operating mode register (OMR) meant that 32-bit mode was selected. this limitation should not be a problem. nor is it necessary.W—compare two word values CMP. For most applications. for example. “Condition Code Calculation. and 32-bit mode.2 Condition Codes and Data Sizes The DSP56800E properly calculates condition codes for all supported data types.1 Condition Code Modes In earlier generations of the DSP56800E architecture. where the the extension registers were ignored. 5. The calculation depends on the size and type of the data that is being manipulated. To understand how the value of the condition code bits is calculated after an operation. if it is necessary to consider the extension register when a value is normalized. Consider the compare instruction. the NORM technique must be used. two condition code modes were available: 36-bit mode. and 36-bit values. The DSP56800E instruction set supports four different versions of the compare instruction: • • • • CMP. A detailed discussion of condition code calculation appears in Appendix B. respectively) holds the amount by which the accumulator was scaled.Data Arithmetic Logic Unit values that are larger than one cannot be normalized. 16-bit register. Although both condition code modes are supported on the DSP56800E.7. word. or memory location Whether the instruction operates on the whole accumulator or only on a portion The current condition code mode Whether or not the MAC output limiter is enabled This section discusses how the condition code mode and data sizes affect the condition codes.7 Condition Code Calculation The results of calculations are reflected in the condition code flag bits. The DSP56800E instruction set supports test and compare instructions for byte. long.” 5.L—compare the lowest 32 bits of an accumulator with the lowest 32 bits of a second accumulator or with a 16-bit source CMP—compare an entire 36-bit accumulator with a second 36-bit accumulator or with a 16-bit source 5-38 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .B and CMP. This mode was useful for integer and control code because the extension registers are not typically used in those algorithms. as specified by the instruction The operation’s destination: accumulator. Regardless of the method that is used to normalize an accumulator.7. using 32-bit mode is not generally recommended. Thirty-two-bit condition code mode should only be used when exact compatibility with existing DSP56800 program code is required. However. so the exact data size can be specified at all times depending on the needs of the program. This value can be used later to scale the normalized accumulator back to its original magnitude. 5.

If a MOVE. with corresponding 8. Freescale Semiconductor Data Arithmetic Logic Unit 5-39 . saturation is equally applicable to integer arithmetic. the DSP56800E provides optional saturation of results through two limiters that are within the data ALU. As an alternative to overflow. When a MOVE. or data limiting. and when the contents of the selected source accumulator can be represented in the destination operand size without overflow (that is. condition codes are based on 8. The data limiter saturates values when moving data out of an accumulator with a move instruction or parallel move. Data Limiter Saturation Extension Bits in Use in Selected Accumulator? No Yes Yes MSB of FF2 (Don’t care) 0 1 Output of Limiter onto the CDBW Bus Same as input—unmodified MSP $7FFF—maximum positive value $8000—maximum negative value Although the following examples all involve fractional data and arithmetic. but one of the two operands can be a 16-bit word. Saturation is especially important when data is run through a digital filter whose output goes to a digital-to-analog converter (DAC). the data limiter places a “limited” data value in the destination that has maximum magnitude and the same sign as the source accumulator. Normally a processor simply overflows its result when this generation occurs. Without saturation. CMP. and CMP.or 16-bit source operands.B. In each case.8. The MAC output limiter limits the output of the data ALU’s MAC unit.Saturation and Data Limiting In the CMP.L and CMP instructions generate condition codes on 32. but overflow creates problems for processing real-time signals. condition codes are calculated based on the size that is specified in or implied by the instruction opcode.W instruction specifies an accumulator (FF) as a source.W instructions. the data limiter does not saturate and the register contents are stored unmodified. Table 5-3 summarizes these scenarios.or 16-bit results. a flag is set and latched in the status register. the output data could incorrectly switch from a large positive number to a large negative value. 5. which guarantees that values are always within a given range. Table 5-3. respectively. The value of the accumulator is not changed.8 Saturation and Data Limiting DSC algorithms can generate values that are larger than the data precision of the machine when real data streams are processed.1 Data Limiter The data limiter protects against overflow by selectively limiting when an accumulator register is read as a source operand in a move instruction. The solution is saturation. This process is called “saturation arithmetic. the accumulator extension register is not in use). The CMP.BP.” When limiting occurs. which would almost certainly cause unwanted results.W instruction is used and the contents of the selected source accumulator cannot be represented in the destination operand size without overflow. 5. The value in the accumulator is not changed. since saturation “clips” the output data instead of allowing arithmetic overflow. Test logic in the extension portion of each accumulator register detects overflows so that the limiter can substitute one of two constants to minimize errors that are due to overflow.and 36-bit results.

$0 8000 0000 in hexadecimal) If this accumulator is read with a MOVE.W #$7FFC. .W A. . 0 0 0 0 . Write $8002 to memory (limiter disabled) 5-40 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .. +1.. . . $7FFF in hexadecimal) This value is clearly closer than –1. . .X:(R0)+ INC. Example of Saturation Arithmetic Example 5-29 is a simple illustration of positive saturation.0 IERRORI = 2. Note that the contents of the original accumulator are NOT changed. . Example 5-29. .X:(R0)+ INC. . the limited value would be: 0.W A1.W A MOVE..A INC.0 3 0 15 0 15 0 100.111 1111 1111 1111 (+ 0.0 in the X0 register greatly differs from the value of +1. . .X:(R0)+ INC.0 in fractional decimal.W A.0 is to the original value..W A. A = $0:7FFD:0000 Write $7FFD to memory (limiter enabled) A = $0:7FFE:0000 Write $7FFE to memory (limiter enabled) A = $0:7FFF:0000 Write $7FFF to memory (limiter enabled) A = $0:8000:0000 <=== Write $7FFF to memory A = $0:8001:0000 Write $7FFF to memory A = $0:8002:0000 Write $7FFF to memory Overflows 16 bits! (limiter saturates) (limiter saturates) (limiter saturates) .0 in the source accumulator. ..W A. . Figure 5-27..000 0000 0000 0000 0000 0000 0000 0000 (in binary) (+1.. . . . . the 16-bit X0 register contains the following value after the move instruction. . .X0 instruction.11 15 0 X0 = +0.. . . . .X:(R0)+ . .W A. In this case. .0 fractional decimal. . 0 1 0 0 .X:(R0)+ INC. B.W A.W A1.. assuming signed fractional arithmetic: 1. .. .X:(R0)+ INC. C. it is preferable to write the maximum (“limited”) value that the destination can assume.W A MOVE. Without Limiting—MOVE.X0 With Limiting—MOVE. . . . . . . In this example.000031 Limiting automatically occurs when the 36-bit operands A. Initialize A = $0:7FFC:0000 . which disables limiting.W A MOVE.W A MOVE.Data Arithmetic Logic Unit Figure 5-27 graphically demonstrates the advantages of saturation arithmetic.0 3 0 15 0 15 0 35 0 0 . . . the A accumulator contains the following 36-bit value to be read to a 16-bit destination: 0000 1.999969 fractional decimal.00 15 0 X0 = –1.W instruction. ..999969 IERRORI = . overflow has occurred. . 0 0 A = +1. .. . . ... To minimize the error due to overflow.W A1. . 0 0 A = +1. . In this example.W A MOVE. $8000 in hexadecimal) This result is clearly in error because the value –1.. 0 1 0 0 .. 0 0 0 0 .000 0000 0000 0000 (–1. . . . . Demonstrating the Data Limiter—Positive Saturation MOVE.X0 35 0 0 . ..X:(R0)+ MOVE. .0 011..0. . .W A MOVE. and thus introduces less error. . or D are read with a MOVE.W A.

X:(R0)+ . Consider the simple example in Example 5-31 on page 5-42. . and so on. a delay of 2 instruction cycles is necessary before the new saturation mode becomes active. which saturates the value of the source accumulator and stores the result in a data ALU register. instead of writing an overflowed value to memory.W A MOVE. . Demonstrating the Data Limiter—Negative Saturation MOVE.X:(R0)+ DEC. Initialize A = $F:8003:0000 . . In the final instruction of the example. The MAC output limiter can be enabled by setting the SA bit in the operating mode register (see Section 8. Example 5-30. NOTE: When the SA bit in the OMR is modified.” on page 8-6).W #$8003.X:(R0)+ DEC. the maximum positive value that can be represented by a signed.W A MOVE.W A. . .X:(R0)+ DEC. the positive result can no longer be written to a 16-bit memory location without overflow.1. So. So.X:(R0)+ MOVE. addition.W A. instead of writing an overflowed value to memory.2 MAC Output Limiter The MAC output limiter optionally saturates or limits results that are calculated by data ALU arithmetic operations such as multiplication. the data limiter writes the most negative 16-bit number. rather than the entire accumulator. Write $7FFD to memory (limiter disabled) Once the accumulator decrements to $7FFF in Example 5-30. it does not affect the accumulator.W A MOVE. $8000. Example 5-30 is a simple illustration of negative saturation. “Saturation (SA)—Bit 4.W A.3.W A MOVE. It is also used when the SAT instruction is executed. .W A.Saturation and Data Limiting Once the accumulator increments to $8000 in Example 5-29.X:(R0)+ DEC. Note that the data limiter affects only the value written to memory. the limiter is disabled because the register is specified as A1. . 5. A = $F:8002:0000 Write $8002 to memory (limiter enabled) A = $F:8001:0000 Write $8001 to memory (limiter enabled) A = $F:8000:0000 Write $8000 to memory (limiter enabled) A = $F:7FFF:0000 <=== Write $8000 to memory A = $F:7FFE:0000 Write $8000 to memory A = $F:7FFD:0000 Write $8000 to memory Overflows 16 bits! (limiter saturates) (limiter saturates) (limiter saturates) . . 16-bit word. the negative result can no longer fit into a 16-bit memory location without overflow. rounding. the data limiter writes $7FFF.W A MOVE.W A1.A DEC. . . incrementing.2. Limiting is bypassed when individual portions of the accumulator.W A MOVE. .W A.X:(R0)+ DEC. Freescale Semiconductor Data Arithmetic Logic Unit 5-41 .8. are read (as in the last line of the example).W A.

W A INC.W A ADD. ASRAC. IMACUU MPYSU. A = $0:7FFE:0000 . but condition code computation as well.2. the value of the most positive 32-bit number. when the SA bit is set.L. LSRR. Set SA bit-—enables MAC Output Limiter .3 Instructions Not Affected by the MAC Output Limiter The MAC output limiter is always disabled (even if the SA bit is set) when the following instructions are executed: • • • ASLL. LSR16.OMR MOVE. EXT[0]. is written instead. $7FFF:FFFF. Table 5-4. MACSU 5-42 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . with no limiting The MAC output limiter affects not only the results calculated by the instruction.W • • • ASLL.A NOP INC.L.” on page B-3 for more information.A .8.W A INC. ASR16.1. an overflowed value is not written to back to the A accumulator. IMPY. A = $0:7FFF:FFFF <=== Saturates to 16 bits! . LSRR.W. 5. with no limiting $0:7FFF:FFFF $0:7FFF:FFFF $0:7FFF:FFFF $F:8000:0000 $F:8000:0000 $F:8000:0000 Result as calculated. and MSP[15]. the saturation logic in the MAC output limiter prevents it from growing larger because it can no longer fit into a 16-bit memory location without overflow. Demonstrating the MAC Output Limiter BFSET #$0010.W A INC.W #$7FFC. MAC Unit Outputs with Saturation Enabled EXT[3] 0 0 0 0 1 1 1 1 EXT[0] 0 0 1 1 0 0 1 1 MSP[15] 0 1 0 1 0 1 0 1 Result Stored in Accumulator Result as calculated. IMPYUU. LSRAC IMAC.W A INC.W ASL16. ASRR.W.L. A = $0:7FFD:0000 . See Section B. The saturation logic operates by checking 3 bits of the 36-bit result out of the MAC unit—EXT[3]. A = $0:7FFF:FFFF <=== Saturates to 16 bits! .L IMPYSU.W #9.Data Arithmetic Logic Unit Example 5-31. Initialize A = $0:7FFC:0000 . As shown in Table 5-4. IMACUS. A = $0:7FFF:FFFF <=== Saturates to 16 bits! Once the accumulator increments to $7FFF in Example 5-31. So. ASRR. A = $0:7FFF:0000 . IMPY. “MAC Output Limiter.L. these 3 bits determine whether saturation is performed on the MAC unit’s output and whether to saturate to the maximum positive value ($7FFF:FFFF) or to the maximum negative value ($8000:0000).

The RND instruction simply rounds a value in the accumulator register that is specified by the instruction. saturation may occur when a value is transferred from one accumulator to another with the TFR instruction.B. In the A accumulator. TST.B.BP.B. TST. In addition.L instruction.W. NOTE: When the rounding bit is modified. TST. and MPYR. or D0) is cleared. The MAC output limiter only affects operations performed in the data ALU.B. LSP < $8000). SBC DEC. Convergent rounding solves the problem of this boundary case by rounding down if the number is even (bit 16 equals zero) and rounding up if the number is odd (bit 16 equals one). SUBL ADD. 5. B0.W. ROR. such as the AGU or program controller. DIV. SXT. In this particular case. CMP. for instructions where the destination is one of the four accumulators. MACR. In contrast.L. C0. LSP > $8000) and rounds down any value below one-half (that is. Note also that if the MAC output limiter is enabled.W. CLB. NEG. the results are eventually biased in that direction.BP CMP. EOR. In the DSP56800E. SUB. If it is always rounded one way.W instruction is not affected by the MAC output limiter except when the first operand is not a register (that is.L • • • • • AND. there is a delay of 2 instruction cycles before the new rounding mode becomes active. The DSC core implements two types of rounding: convergent rounding and two’s-complement rounding. use the SXT.Rounding • • • • • AND. whereas the MPYR or MACR instructions perform a regular MPY or MAC operation and then round the result.BP.B.W. it is a memory location or an immediate value) and the second operand is X0.L ADC. this point is between the A1 register’s LSB and the A0 register’s MSB. No other condition code bits are affected. The type of rounding is selected by the rounding bit (R) of the OMR. or Y1.BP. (Note that saturation can still occur when a rounded result is moved to a 16-bit destination).W LSL.W.W. Each rounding instruction rounds the result to a single-precision value so that the value can be stored in memory or in a 16-bit register.B. two’s-complement rounding always rounds this number up.L The CMP.9 Rounding The DSP56800E architecture provides three instructions that can perform rounding—RND. ROR. It has no effect on instructions executed in other functional blocks. The usual rounding method rounds up any value above one-half (that is. ZXT.L SXT.BP.BP. the rounding point is between bits 16 and 15 of a 36-bit value.W. Y0. ADD. ROL. CMP.BP TST.W. TST.L. The question arises as to which way the number one-half (LSP equals $8000) should be rounded. INC. ROL. the calculation of the U bit might be affected if saturation occurs. OR. OR. Freescale Semiconductor Data Arithmetic Logic Unit 5-43 . LSR.L. the FF0 portion of the destination accumulator (A0. EOR.L NOT. SUB. To move a 32-bit value from one accumulator to another without limiting when the MAC output limiter is enabled.

2. If the 16 LSBs of the result at this point are $0000. For most values. then clear bit 16 of the result.” is the default rounding mode. Figure 5-28 on page 5-45 shows the four possible cases for convergent rounding a number in one of the four accumulators. — Saturate to $F:8000:0000 if negative.9. 3. Clear the LSP of the result before writing to a destination accumulator. They only differ when the least significant 16 bits of the final result before rounding are exactly $8000. 5-44 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Add the value $0:0000:8000 to the accumulator (for the RND instruction) or to the final result without rounding (for the MACR instruction). this mode and two’s-complement rounding round identically. In this case. 4. If the SA bit in the OMR is set and the accumulator extension is in use: — Saturate to $0:7FFF:0000 if positive.Data Arithmetic Logic Unit 5. also called “round to the nearest even number.1 Convergent Rounding Convergent rounding. The algorithm for convergent rounding is as follows: 1. convergent rounding rounds down the value if the number is even (bit 16 equals zero) and rounds up the value if it is odd (bit 16 equals one).

Rounding Case I: If A0 < $8000 (1/2). then round up (add 1 to A1) Before Rounding 1 A2 A1 A0 A2 A1 A0* XX......XXX0101 000....XX XXX. then round up (add 1 to A1) Before Rounding 1 A2 A1 A0 A2 A1 A0* XX...XX XXX.XXX0100 000.XXX0100 1000. then round down (add nothing) Before Rounding 0 A2 A1 A0 A2 A1 A0* XX..000 35 32 31 16 15 0 After Rounding Case III: If A0 = $8000 (1/2)..XX XXX. performed during RND.... MACR XX. Convergent Rounding Freescale Semiconductor Data Arithmetic Logic Unit 5-45 ....XX XXX..XX XXX..XXX 35 32 31 16 15 0 XX.......XX XXX......XXX0100 000.XXX 35 32 31 16 15 0 XX......... then round down (add nothing) Before Rounding 0 A2 A1 A0 A2 A1 A0* XX..000 35 32 31 16 15 0 After Rounding Case IV: If A0 = $8000 (1/2)......XX XXX...000 35 32 31 16 15 0 *A0 is always clear.....XXX0110 000.. and the LSB of A1 = 0 (even)...XXX0100 011XXX...000 35 32 31 16 15 0 After Rounding Case II: If A0 > $8000 (1/2)...000 35 32 31 16 15 0 XX.... and the LSB = 1 (odd)....XXX0101 1000...000 35 32 31 16 15 0 After Rounding Figure 5-28.....XX XXX..... MPYR...XXX0100 1110XX.

X X X 35 32 31 16 15 0 XX.. then round up (add 1 to A1) Before Rounding 1 A2 A1 A0 A2 A1 A0* XX. MACR XX..5 ($8000). Case I: A0 < 0..9. Example Code for Two’s-Complement Rounding MOVE.A BFSET #$0020. . X X X X X .. . . during a rounding operation..3 Rounding Examples Example 5-32 shows program code that demonstrates two’s-complement rounding.5 ($8000)... .9. 3. .......000 35 32 31 16 15 0 AA0050 After Rounding Figure 5-29.XX XXX. then round down (add nothing) Before Rounding 0 A2 A1 A0 A2 A1 A0* X X . 5. . ..XXX0101 000... . If the SA bit in the OMR is set and the extension is in use: — Saturate to $0:7FFF:0000 if positive.. and Example 5-33 demonstrates convergent rounding. ...XXX0100 000..L #VALUE. Figure 5-29 shows the two possible cases.2 Two’s-Complement Rounding When this type of rounding is selected through setting the rounding bit in the OMR.XX XXX. performed during RND. one is added to the bit to the right of the rounding point (bit 15 of A0) before the bit truncation.XXX 35 32 31 16 15 0 *A0 is always clear. .. Example 5-32. — Saturate to $F:8000:0000 if negative. . MPYR... Add the value $0:0000:8000 to the accumulator (for the RND instruction) or to the final result without rounding (for the MACR instruction). then. Two’s-Complement Rounding The algorithm for two’s-complement rounding is as follows: 1. 2. X X X 0 1 0 0 0 1 1 0 X.. Clear the LSP of the result before writing to a destination accumulator. .. Load A Accumulator Set the R bit for two’s-complement rounding (2 cycles required for R bit to be valid) (2 cycles required for R bit to be valid) Round A accumulator 5-46 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . ....Data Arithmetic Logic Unit 5.000 35 32 31 16 15 0 After Rounding Case II: A0 >= 0.XX XXX.XXX0101 1110X..OMR NOP NOP RND A ..

L #VALUE. In this case. Table 5-5.A BFCLR #$0020. .Rounding Example 5-33. Boundary case: LSP of value is $8000 and MSP is even.OMR NOP NOP RND A . the algorithms generate different results! Boundary case: LSP of value is $8000 and MSP is odd. both have the same result. . In this case. Simple case: both round up to same value. The two algorithms give different results in one of the four cases. Rounding Results for Different Values Value to be Rounded $1234:0397 Convergent Rounding Result $1234:0000 Two’s-Complement Rounding Result $1234:0000 Comments Simple case: both round down to same value. Example Code for Convergent Rounding MOVE. . . $1234:C397 $1234:8000 $1235:0000 $1234:0000 $1235:0000 $1235:0000 $1235:8000 $1236:0000 $1236:0000 Freescale Semiconductor Data Arithmetic Logic Unit 5-47 . Load A Accumulator Clear the R bit for convergent rounding (2 cycles required for R bit to be valid) (2 cycles required for R bit to be valid) Round A accumulator Table 5-5 shows four sets of results when four different values are substituted for the placeholder “#VALUE” in Example 5-32 and Example 5-33 on page 5-47.

Data Arithmetic Logic Unit 5-48 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

so bus transfers occur in parallel with AGU calculations. A 24-bit secondary address adder unit. The AGU calculates effective addresses for instruction operands and directly executes the address arithmetic instructions. The AGU contains two arithmetic units—a primary address arithmetic unit for complex address calculations. word.Chapter 6 Address Generation Unit The address generation unit (AGU) performs all address calculation and generation for the DSP56800E core. Byte. AGU operations are performed on internal AGU buses. Two single-bit shifters for byte addressing. Extensive pointer arithmetic operations are provided for even greater flexibility. The primary address arithmetic unit supports both linear and modulo address arithmetic. and long-word data memory accesses are also available for use by applications. The two arithmetic units can update up to two 24-bit addresses every instruction cycle: one for primary memory accesses using XAB1 or PAB.and 16-bit pointers. Support is built into the AGU for applications that require both 24. and a secondary address adder for simple calculations. Figure 6-1 on page 6-2 presents a block diagram of the AGU on the DSP56800E core. simplifying the implementation of some useful data structures. 6. It supports both linear and modulo arithmetic calculations. The DSP56800EX core contains additional shadow registers not reflected in this diagram. The major components of the address generation unit are: • • • A 24-bit primary address arithmetic unit. Freescale Semiconductor Address Generation Unit 6-1 .1 AGU Architecture The address generation unit (AGU) consists of the registers and logic used to calculate the effective address of data operands in memory. All AGU operations are performed in parallel with other chip functions to minimize address-generation overhead. and one for secondary memory accesses performed on XAB2.

217) locations in data memory and 221 (2. respectively. places its data on the core data bus for reads (CDBR) and on the second data bus (XDB2).Address Generation Unit CDBR CDBW Secondary Offset Register N3 To R3 15 Modifier Registers M01 0 23 Pointer Registers R0 R1 0 15 0 Primary Arithmetic Unit R2 R3 R4 R5 N Secondary Adder Short or Long Immediate Data SP R3 Only pass. 6-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Address Generation Unit Block Diagram (DSP56800E Core) Figure 6-2 illustrates a dual parallel read instruction. >>1 Byte Select PAB XAB1 XAB2 Figure 6-1.152) locations in program memory. and the second operand is addressed with XAB2.X0 Secondary Read (Uses XAB2 and XDB2) Figure 6-2. Byte.” on page 3-11 for more discussion of parallel memory moves. The primary operand is addressed with XAB1.1. <<1 pass. Dual Parallel Read Instruction The AGU can directly address 224 (16.3.Y0 Primary Read (Uses XAB1 and CDBR) X:(R3)+N3. and long-word accesses are supported. as in indexing and post-updating. See Section 3. All three buses can generate addresses to on-chip or off-chip memory.5. MOVE. in turn. 6. “Parallel Moves.W X:(R4)+N. The data memory.777.097. which uses 1 program word and executes in 1 instruction cycle. word.1 Primary Address Arithmetic Unit The primary address arithmetic unit is used when AGU arithmetic instructions are performed and when complex operand effective addresses are calculated.

Although all of the address pointer registers and the SP are available for most addressing modes.2 Secondary Address Adder Unit The secondary address adder unit is used for address update calculations on the R3 register.1. and N3) on the DSP56800EX core The eight 24-bit registers can be used as pointers in the register-indirect addressing modes.3 Single-Bit Shifting Units Two single-bit shifters are present to support byte addressing. Modulo arithmetic is described in detail in Section 6. The adder unit can increment.2 AGU Programming Model The AGU programming model. M01. specify the type of arithmetic to be performed for the R0 and R1 address registers. which is used for the secondary read in dual memory read instructions (see Figure 6-2 on page 6-2). and M01) on the DSP56800E and DSP56800EX cores. More information on byte addressing. This unit performs only linear arithmetic. N. The shadowed registers provide extra pointer registers for interrupt routines or for system-control software. there are some addressing modes that only work with a specific address pointer register. The contents of the modifier register. All other address registers—R2–R5. or modulo arithmetic.” 6. consists of 14 programmable registers: • • • • • • Six 24-bit address registers (R0–R5) A 24-bit stack pointer register (SP) A 24-bit offset register (N. and on the shift operations that are performed on byte addresses. R3. Freescale Semiconductor Address Generation Unit 6-3 . “Memory Access and Pointers. “Linear and Modulo Address Arithmetic. N.1. which may also be used as an address register) A 16-bit offset register (N3) A 16-bit modifier register (M01) Four shadow registers (shadows of R0. decrement. Modulo arithmetic on the R0 and R1 pointer registers is enabled with the M01 register. The N register can also be used as an index or offset by the six address pointer registers. 6. which Figure 6-3 on page 6-4 illustrates. modulo arithmetic is not supported.” on page 3-17. 6. These special cases appear in Table 6-1 on page 6-6. R4.8. can be found in Section 3. and SP—always operate with linear arithmetic. for general-purpose computing. or add the contents of the N3 register to R3.5. for circular buffers and other useful data structures. and five additional shadow registers (shadows of R2. R1. R5.AGU Programming Model Calculations in the primary address arithmetic unit can be performed using either linear arithmetic.

2.2.4. minimizing access time to internal and external data and program memory. taking care that the stack area does not overlap any other data area. The address registers can directly drive the core’s three address buses. Address Generation Unit Programming Model NOTE: Pipeline dependencies might be encountered when the AGU registers are modified. It is always used as a word pointer (see Section 3. The stack pointer register can be used to access byte. Only the R0–R3 registers can be used to access on-chip or off-chip program memory.” on page 3-17).Address Generation Unit 23 Pointer Registers R0 R1 R2 R3 R4 R5 N SP 0 Secondary Offset Register 15 0 N3 Modifier Registers 15 M01 0 Figure 6-3. The offset register. 6-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . can also be used as an address register. N) The address register file consists of six 24-bit registers. This register is not initialized to a known value after reset.” on page 10-28 for more information.1. R0–R5. “Word and Byte Pointers. The SP register can be used by a program to access data on the software stack. 6.2. and long values in data memory. and they can be used as byte or word pointers (see Section 3. which push the current program counter and status register on the stack.1 Address Registers (R0–R5.” on page 3-17). N. These instructions include jumps to subroutines and interrupt handlers. or it can be used implicitly by instructions that store information on the stack as part of their regular operation. Applications need to explicitly establish the base of the stack after reset. 6. word. Note that the software stack grows upward when values are pushed onto it. “AGU Pipeline Dependencies.5.5. and long values in data memory. including the R3 register when it is used in the secondary access of a dual read instruction.2 Stack Pointer Register (SP) The stack pointer register (SP) is a 24-bit register that is used to access the software stack.1. Any address register can be used for accessing either on-chip or off-chip data memory. word. “Word and Byte Pointers. which are typically used as pointers to memory. Refer to Section 10. The address registers can be used to access byte.

or SP registers.2. N. The DSP56800EX core provides the same four registers as well as five additional shadow registers corresponding to the R2. The contents of the four registers are exchanged with their shadowed counterparts. This swapping is accomplished through executing the SWAP SHADOWS instruction. which read two values from data memory. R4. executing the SWAP SHADOWS instruction a second time restores the original values. and M01 address registers. R1. Thus.2. When the N register is used as an offset for accessing long memory locations. R3. During processor reset this register is set to $FFFF.3 Offset Register (N) The N register is one of the most powerful registers in the AGU. “Configuring Modulo Arithmetic.2. 6. its value is shifted to the left by 1 bit before it is passed to the primary arithmetic unit for calculating the effective address.3. When the N register is used as an offset for post-updating. It must be explicitly programmed by the user.6 Shadow Registers The DSP56800E provides four shadow registers corresponding to the R0. The N3 register is sign extended to 24 bits and passed to the secondary address adder unit for post-updating the R3 pointer register. Programming the modifier register is discussed in Section 6. The shadow registers are not directly accessible. but become available when their contents are swapped with the contents of the corresponding AGU core registers.8. the N offset is a long offset. 6. R5. which enables linear arithmetic for the R0 and R1 registers.” NOTE: The M01 register should never be used for general-purpose storage because its value affects calculations with the R0 and R1 pointers.5 Modifier Register (M01) The modifier register (M01) specifies whether linear or modulo arithmetic is used when a new address is calculated. N. In addition to functioning as an address pointer similar to the R0–R5 registers. Freescale Semiconductor Address Generation Unit 6-5 . This modifier register is automatically read when the R0 or R1 address register is used in an address calculation.4 Secondary Read Offset Register (N3) The secondary read offset register (N3) is a 16-bit register that is used for post-updating the R3 pointer register in dual read instructions.AGU Programming Model 6. 6. When the original values of the registers are required. in this case. NOTE: The shadow register corresponding to M01 is not initialized by the core at reset. its value is truncated to 16 bits and then sign extended to 24 bits before being passed to the primary arithmetic unit for post-updating. and N3 address registers.2. it can also be used for indexed and post-update addressing modes. This register has no effect on address calculations done with the R2–R5.

No Pointer for single parallel move. Refer to Section 6. The type of address arithmetic to be performed. See Section 6. Pointer for P: memory moves. Pointer for P: memory moves. Pointer for P: memory moves. Refer to Section 6. “Fast Interrupt Processing. Fast interrupts are described in Section 9. Shadowed for use with fast interrupt processing on the DSP56800EX core.” for a discussion of the arithmetic types.8. Shadowed for use with fast interrupt processing. Supports legacy addressing modes (Rj+N) and (Rj+xxxx).” on page 9-6. Optional destination register for Tcc transfer. Table 6-1 summarizes the capabilities of each address register. but is specified by the address modifier register (M01). Yes Pointer for single parallel move and for primary access in dual parallel reads. Supports legacy addressing modes (Rj+N) and (Rj+xxxx). Pointer for single parallel move and for primary access in dual parallel reads.8. Capabilities of the Address Pointer Registers Pointer Register R0 Addressing Modes Allowed (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) Modulo Allowed? Yes Capabilities and Notes Counter for the NORM instruction. Table 6-1.3. Supports legacy addressing modes (Rj+N) and (Rj+xxxx). linear or modulo. Not all of the registers work identically.” on page 6-26 for interpretation of base pointer and offset in update by index addressing mode.4. is not encoded in the instruction. The SWAP instruction enables the shadow registers to be used to minimize the overhead during normal interrupt processing. “Base Pointer and Offset Values in Modulo Instructions. the R3 register is the only register that is available for the secondary read in instructions that perform two data memory moves. 6.Address Generation Unit Using shadow registers as dedicated address registers during fast interrupt processing can greatly reduce the considerable overhead incurred by saving and restoring registers when exception handlers are entered and exited.8. however. “Linear and Modulo Address Arithmetic.4. Shadowed for use with fast interrupt processing. R1 (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) R2 6-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Table 6-1 indicates whether or not modulo arithmetic is supported for a given register. “Base Pointer and Offset Values in Modulo Instructions.2. Optional source register for Tcc transfer.” on page 6-26 for interpretation of base pointer and offset in update by index addressing mode. Depending on the register. For example.3 Using Address Registers The DSP56800E AGU provides several address registers that can be used as pointers for accessing memory.2. there are additional capabilities or restrictions of use.

” on page 3-17.4 Byte and Word Addresses As discussed in Section 3. RTID and FRTID instructions. Freescale Semiconductor Address Generation Unit 6-7 . “Word and Byte Pointers. Pointer for P: memory moves. R4 No Pointer for primary access in dual read instructions. SP No Supports 1-word indexed addressing with 6-bit offset for word moves. Shadowed for use with fast interrupt processing. Shadowed for use with fast interrupt processing on the DSP56800EX core. Supports legacy addressing modes (Rj+N) and (Rj+xxxx). SP is always used as a word pointer to properly support stack operations. Figure 6-4 on page 6-8 shows the differences between the memory maps. N No Available not only as a pointer register.Byte and Word Addresses Table 6-1. the DSP56800E supports two types of addresses for data memory accesses: word and byte. Used implicitly by the JSR. May be post-updated with N3 register. RTI. RTSD. Capabilities of the Address Pointer Registers (Continued) Pointer Register R3 Addressing Modes Allowed (Rn) (Rn)+ (Rn)– (Rn)+N (R3)+N3 (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (RRR+x) (Rn+xxxx) (Rn+xxxxxx) (Rn) (Rn)+ (Rn)– (Rn)+N (Rn+N) (SP–x) (SP–xx) (Rn+xxxx) (Rn+xxxxxx) Modulo Allowed? No Capabilities and Notes Pointer for single parallel move and for secondary access in dual parallel reads. R5 No Shadowed for use with fast interrupt processing on the DSP56800EX core.1.5. 6. the memory map is interpreted somewhat differently. Shadowed for use with fast interrupt processing on the DSP56800EX core. RTS. but also as indexing and post-update register. Supports legacy addressing mode (SP+N). Depending on the type of address used.

” and “xxxxxx” that appear in Table 6-2 on page 6-9 for long word accesses are the values that are actually encoded by the assembler. All immediate offsets and absolute addresses for long-word moves must be even values because long words must be located on an even word address boundary. and longs from data memory.BP” extension are used. Table 6-2 on page 6-9 shows the word address in data memory that is accessed for the different addressing modes and data types when word pointers are used.” “xxxx.Address Generation Unit Word Addresses X Memory 15 0 Byte Addresses X Memory 7 0 7 0 $2003 $2002 $2001 $2000 $88 $66 $44 $22 $77 $55 $33 $11 Identical Memory Locations $4006 $4004 $4002 $4000 $88 $66 $44 $22 $77 $55 $33 $11 Figure 6-4. As shown in Figure 6-4. For the post-update addressing modes. Program memory accesses are always performed with word addresses. address register values are interpreted as word addresses. Byte Addresses When word addresses are used. since the low-order bit is guaranteed to be zero). each unique address refers to a different 16-bit word in memory. The table describes what the hardware does after the instruction has been encoded by the assembler. which have been divided by two during assembly. NOTE: Byte addresses can not be used for accessing program memory. Byte addresses are used to locate individual bytes in memory. locations X:$2000 and X:$2001 refer to adjacent 16-bit words. This is often referred to as “little-endian” byte ordering. words. NOTE: The values “xx. using word addressing). the LSB of the offset before the right shift selects the upper or lower byte. the address in Rn is used for the memory access and then is post-updated using the arithmetic shown in Table 6-2. 6-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 6. including those that explicitly perform a word or long-word access. the AGU left shifts the absolute value 1 bit to generate the correct word address or offset. it divides the absolute address and offset values by two before generating the opcode (no information is lost.5 Word Pointer Memory Accesses Instructions that use address registers as word pointers can access bytes. When the assembler encounters these instructions. Addresses X:$4000 and X:$4001 refer to 2 bytes contained in the same word (the word at X:$2000. Address register values are interpreted as byte addresses only when instructions with the “. Byte and word addresses are distinguished by the instruction that uses them. When the instruction is executed. For byte accesses. Note that data is stored in memory with the least significant byte occupying the lowest memory location. Word vs. For most instructions.

The lower 16 bits of N are sign extended to 24 bits and added to Rn.Word Pointer Memory Accesses Table 6-2. — SP–xx SP–(xx<<1) 6-bit one extended. Hardware Implementation of Addressing Mode Arithmetic— Word Pointers to Data Memory Addressing Mode No update X:(Rn) Post-increment X:(Rn)+ Post-decrement X:(Rn)– Post-update by offset N X:(Rn)+N Address for Byte Access — Address for Word Access Rn Address for Long Access Rn Comments — Rn+1 Rn+2 Post-increment occurs after access. SP–(x>>1) — — Rn+(xxxx>>1) Rn+xxxx Rn+(xxxx<<1) Signed 16-bit offset. 2. — Rn–1 Rn–2 — Rn+N — Indexed by offset N X:(Rn+N) Indexed by 3-bit offset X:(RRR+x) Indexed by 6-bit offset X:(SP–xx) Indexed by 3-bit offset X:(SP–x) Indexed by 16-bit offset X:(Rn+xxxx) Indexed by 24-bit offset X:(Rn+xxxxxx) 6-bit absolute short X:aa 6-bit peripheral short X:<<pp 16-bit absolute address2 X:xxxx 24-bit absolute address2 X:xxxxxx — Rn+N Rn+(N<<1) RRR+(x>>1) Rn+x — Offset x from 0 to 7. and the destination is an absolute byte address. SP pointer only. In this case. which varies depending on the specific implementation of the chip. — 0000xx — — 00FFxx1 00xxxx — — (00xxxx<<1) — xxxxxx (xxxxxx<<1) 1. Post-decrement occurs after access.The upper 18 bits are hard-wired to a specific area of memory. 3-bit one extended. the source address is specified with a word pointer.The X:xxxx and X:xxxxxx addressing modes are allowed for byte accesses when they are used as the destination address in a byte memory to memory move instruction. Rn+(xxxxxx>>1) Rn+xxxxxx Rn+(xxxxxx<<1) Signed 24-bit offset. Freescale Semiconductor Address Generation Unit 6-9 .

MOVE.B x:(r0+3).x0 MOVE.x0 MOVE.B -. selects lower .B x:(sp).B x:(sp-4). word address = $3fff. “Accessing Long-Word Values Using Word Pointers. . specifically the use of the N offset register.W#$2000.5. selects MOVE.2 Accessing Long Words Long words are always accessed with word pointers.B instructions. two adjacent 16-bit word values are accessed: the word specified in the pointer. Example 6-1.B x:(r0+2). When a long-word value is read or written to memory. selects MOVE.R0 used as a word pointer. .x0 . selects upper . the particular byte to access within the word is determined by the offset that is specified in the instruction. load R0 pointer with the value $2000 (can be either a byte or word pointer) load the stack pointer (SP) with $4000 (SP must always be a word pointer) lower upper lower upper lower byte byte byte byte byte byte byte byte byte byte . word address = $3ffe.B x:(sp-2).x0 . MOVEU.x0 word pointer.B x:(r0+0). word address = $3ffe. Because word pointers typically select an entire 16-bit word at once.B instruction. the offset values are all specified in bytes.x0 MOVE. SP Address Pointers MOVEU. selects upper .SP always used as a MOVE.R0 . see Section 3. selects MOVE. Note the arithmetic performed by the AGU in calculating the long-word address.x0 MOVE. word address = $2000. offset is a byte offset MOVE.B -.x0 .x0 . selects . Accessing Bytes with the MOVE.3.” on page 3-19 for more information.B x:(sp-3). Note that. selects MOVE.) Example 6-2 on page 6-11 demonstrates several long-word accesses.B x:(r0+4). Load the R0. selects lower .5. and the word that immediately follows in memory.B and MOVEU.B x:(r0+1). word address = $2000. (An exception is when the SP register is used to access long-word values. word address = $2001. Even offset values (or an offset of zero) select the lower byte in a word.B x:(sp-1). while odd offsets select the upper byte.W#$4000. selects lower 6.5. word address = $2001. 6-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . even though word pointers are being used. Example 6-1 demonstrates accessing byte values in memory using the MOVE. MOVE.x0 .B Instruction . word address = $4000.SP .Address Generation Unit 6.1 Accessing Bytes Word pointers can be used to access bytes in memory with the MOVE. offset is a byte offset . word address = $2002. word address = $3fff.

. word pointers should always be used when structure elements are accessed.L N.R3 MOVEU.Fourth Example -. the address is $1004.Initialize Registers MOVEU.$CC $12345678 $FFFF .B x:(R3+1). initialize base address .5. Byte values in the structure can still be accessed with the MOVE.B and MOVEU. Example 6-3.L X:(R2). make a copy of R2 .Second Example -.R3 MOVE. When the address is calculated for the memory access. word.Bx:(R3+2). 4th is $DD 1 long containing $12345678 1 word containing $FFFF (instructions located in program memory) set up base to data structure read with offset of 1 byte from R3 read with offset of 2 bytes from R3 read with offset of 4 words from R3 read with offset of 2 words from R3 CODESTART ORG P: MOVE.A MOVEU.3 Accessing Data Structures Data structures and unions (such as those used in the C and C++ programming languages) typically contain a mixture of data types.R3 . .Third Example -. initialize register index value .C MOVE. Accesses X:$1005:X:$1004 .Calculating the New Address (similar to second example) ADDA. 2nd is $BB 3rd is $CC. Where word offsets are used. Calculated Address = $1004 MOVE.L X:(R3+N).B instructions. Because it is not possible to access word or long-word variables with a byte pointer.L x:(R3+2). Accessing Elements in a Data Structure STRUCT1 ORG DCB DCB DCL DC x:$7000 $BB.L X:(R2+4). . which use word pointers. . The resulting address in each case is $1008. stored in R3. .W#4. and long-word variables and has its base address.A . the N register value is treated as a long-word offset.First Example -.$AA $DD. Data Structure named “STRUCT1” four chars: 1st is $AA. Accesses X:$1005:X:$1004 .B MOVE. The code in Example 6-3 shows the initialization of a data structure and code used to access the elements.R2 TFRA R2. since the long-word versions of MOVE and ADDA are used. in the other two examples. .L #STRUCT1.W x:(R3+4).Indexing with Offset Register N (N = 4) MOVE. The structure contains byte. . Each of the four accumulators are loaded with a different structure variable. . Calculated Address = $1008 MOVE.R2 .Word Pointer Memory Accesses Example 6-2. Accesses X:$1009:X:$1008 .A .W#$1000. 6.N . .A . Consider an example structure in data memory.Calculating the New Address (similar to first example) ADDA N.Indexing with Displacement MOVE. .A . Addressing Mode Examples for Long Memory Accesses .d Freescale Semiconductor Address Generation Unit 6-11 . a word pointer. the R2 and R3 registers are offset by 4 long words (8 words). Structure elements are accessed with offsets from this base through using the (R3+x) and (R3+xxxx) addressing modes.L X:(R3). Accesses X:$1009:X:$1008 In the second and fourth examples.

D Instruction Note that.B instructions instead of MOVE. specifies an offset value of two. This requirement exists because the R3 register is used as a word pointer. 6-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L X:(R3+2). This value is specified because constant offsets for both word and long-word memory accesses are always specified in words. for instructions that move bytes. which loads the long-word variable into D. the offset is specified in the number of words. the accumulators hold the following values: Before Execution A B C D X X X X X X X X X X X X A B C D $F $0 $F $0 After Execution $FFBB $00CC $FFFF $1234 $0000 $0000 $0000 $5678 Note that the last instruction in Example 6-3. for word and long instructions. the offset is specified in the number of bytes.D instruction is shown in Figure 6-5. Executing the MOVE.B and MOVEU. whereas. Also note that accesses to bytes in the data structure in Example 6-3 on page 6-11 require the MOVE.Address Generation Unit After the code in Example 6-3 on page 6-11 is executed. Before Execution D X X X Memory 15 $7004 $7003 $7002 $7001 $7000 $FFFF $1234 $5678 $DD $BB $CC $AA 0 $7004 $7003 $7002 $7001 $7000 15 $FFFF $1234 $5678 $DD $BB $CC $AA X D $0 After Execution $1234 X Memory 0 Word Long $5678 4 Bytes R3 $7000 + R3 $7000 N $9876 << 1 N $9876 M01 $FFFF Short Immediate Value from the Instruction Word M01 $FFFF Figure 6-5.BP.BP and MOVEU. The operation performed by the MOVE.L X:(R3+2).

6 Byte Pointer Memory Accesses Instructions that use address registers as byte pointers can only access bytes from data memory.5. Note that the X:xxxx and X:xxxxxx addressing modes specify an absolute byte address. “Word Pointer Memory Accesses. right shifted 1 bit. only the lower half of data memory can be accessed. However.BP. such as MOVE.5. An address register value is interpreted as a byte pointer when an instruction with a “. NOTE: Bytes can not be accessed in the top half of data memory using byte pointers.5. Table 6-3.4 Accessing Program Memory Program memory accesses are always performed with word pointers. The address of the word that is accessed in memory is the byte address from the table. Table 6-4 on page 6-14 shows the byte address that is accessed for the different byte pointer addressing modes. as discussed in Section 6.BP or CLR.” apply to program memory accesses. The addressing modes that can be used when program memory is accessed appear in Table 6-3.3.BP” extension is used. many fewer addressing modes are supported. The general rules for word pointer accesses. Addressing Mode Arithmetic—Program Memory Addressing Mode Post-increment P:(Rj)+ Post-update by offset N P:(Rj)+N Address for Word Access Rn+1 Comments Word accesses only Rn+N Word accesses only 6. the LSB of the byte address in the table selects the upper or lower byte.Byte Pointer Memory Accesses 6. Bytes can still be accessed in the complete data memory space using word pointers. but if byte pointers are used. with the upper n – 1 bits specifying the correct word in memory and the LSB selecting the upper or lower byte.” through Section 6. Freescale Semiconductor Address Generation Unit 6-13 . “Accessing Data Structures.

Although it is possible to access bytes in memory with either type of pointer. Addressing Mode Arithmetic—Byte Pointers to Data Memory Addressing Mode No update X:(RRR) Post-increment X:(RRR)+ Post-decrement X:(RRR)– Post-update by offset N X:(RRR)+N Indexed by offset N X:(RRR+N) Indexed by 3-bit offset X:(RRR+x) Indexed by 6-bit offset X:(SP–xx) Indexed by 3-bit offset X:(SP–x) Indexed by 16-bit offset X:(RRR+xxxx) Indexed by 24-bit offset X:(RRR+xxxxxx) 6-bit absolute short X:aa 6-bit peripheral short X:pp 16-bit absolute address X:xxxx 24-bit absolute address X:xxxxxx Address for Byte Access RRR Comments Not allowed for SP register RRR+1 Not allowed for SP register RRR–1 Not allowed for SP register — RRR+N Not allowed for SP register — Must use MOVE. Word pointers can be used to access a data element of any size.B with word pointer — — Must use MOVE.6.B with word pointer Zero-extended 16-bit offset.Address Generation Unit Table 6-4.BP is used.B or MOVEU.B instruction is used. not allowed for SP register Not allowed for SP register RRR+xxxx RRR+xxxxxx — — 00xxxx xxxxxx 6. Word Pointers Both the MOVE. there are times when using a byte pointer makes more sense than using a word pointer.1 Byte Pointers vs. and at other times the opposite is true. When the MOVE.B or MOVEU. When MOVE. The difference between them is how the address register operand is interpreted. the address register operand is treated as a word pointer. Note that word pointers have full visibility of the complete 32Mbyte data memory space.B and MOVE. the address register operand is treated as a byte pointer. only the lower half of data memory can be accessed.BP instructions (and their unsigned counterparts) can be used to access bytes in memory. so they should be used when mixed data is 6-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . but when byte pointers are used.

selects MOVE.B x:(r0+0). word address = $1002. the pointer is always interpreted as a word pointer. word MOVE. Comparison of MOVE. regardless of whether an instruction uses a pointer as a byte or word pointer.B x:(r0+1). $1002.BP is used. For each instruction in Example 6-4. they are often used to store string values. selects MOVE. SP Address Pointers MOVEU.Byte Pointer Memory Accesses accessed (such as occurs in data structures). Example 6-4 demonstrates the difference between the MOVE. Freescale Semiconductor Address Generation Unit 6-15 . which causes R0 to be interpreted as a byte pointer.B x:(sp-2).BPx:(r0+4).B x:(r0+4). selects upper .R0 used as a word pointer. The DSP56800E instruction set makes it easy to access and manipulate byte arrays through the use of byte pointers.x0 MOVE. $1001. MOVEU. selects .x0 MOVE. word address = $2002. word address = $2000. so using a word pointer in a post-update addressing mode to access a byte array would only access every other byte. word MOVE. post-updating word pointers always occurs in word addresses. MOVE.x0 . Load the R0. load R0 pointer with the value $2000 (can be either a byte or word pointer) load the stack pointer (SP) with $4000 (SP must always be a word pointer) offset is address = address = address = address = address = a byte $1000.BPx:$2005. offset is a byte offset MOVE. selects MOVE.BP” suffix.SP . $1001. the address pointer R0 is loaded with the value $2000.B x:(sp-1). word address = $2001.x0 .SP always used as a MOVE. word address = $4000. the comment shows the word address where the access occurs as well as the byte that is selected (upper or lower byte of the word).x0 .x0 .B x:(r0+3).2 Byte Arrays Byte arrays are a common data structure in many applications. $1000.x0 . word MOVE.B -. Using byte pointers fixes this problem. The first two move instructions access the fifth and eighth array elements. offset is a byte offset .R0 used as a byte pointer. word address = $2000.B is used). The code in Example 6-5 on page 6-16 shows an eight-element byte array being initialized and also shows accesses to the array. The base of the array is loaded first as a byte pointer via the assembler’s lb() function.BPx:(r0+1). word address = $3ffe. selects upper byte lower upper lower upper lower byte byte byte byte byte byte byte byte byte byte . word MOVE. word address = $3fff. selects lower .x0 .x0 .x0 word pointer. Locations near the word address $2000 are accessed when R0 is interpreted as a word pointer (when MOVE. Locations near the word address $1000 are accessed when MOVE. respectively.BPx:(r0+3).B x:(r0+2). selects MOVE.x0 MOVE. and the last two move instructions demonstrate sequential accesses to byte elements.B instructions using numerical values. .6. MOVE. offset selects selects selects selects selects lower upper lower upper lower byte byte byte byte byte . word MOVE. MOVE.B Instructions .x0 . Example 6-4.B x:(sp). word address = $2001. However. selects lower In Example 6-4.BPx:(r0+2). selects lower .BPx:(r0+0). The offsets for all instructions that are accessing bytes from memory are always byte offsets.B x:(sp-3).BP and MOVE.W#$2000.W#$4000. Otherwise.x0 MOVE. . selects upper .B x:(sp-4).x0 . word address = $3fff.B -. Byte pointers are only used if an instruction contains the “.x0 . MOVE. The base of the array is then reloaded.BP and MOVE. word address = $3ffe.x0 .BP -.R0 . 6.

.W#@lb(ARRAY1).B X:(R1+7). read first array element and advance pointer MOVE. 6th is $66 7th is $77.BPX:(R1)+.$11 $44. 8th is $88 CODESTART ORG P: . the values in the accumulator registers are: Before Execution A B C D X X X X X X X X X X X X A B C D $0 $0 $0 $0 After Execution $0055 $0088 $0011 $0022 $0000 $0000 $0000 $0000 Recall that constant offset values are always specified in bytes when byte accesses are performed. 4th is $44 5th is $55.A . the eighth element in the array is read. (instructions located in program memory) MOVEU. .BPX:(R1+7).BPX:(R1+4).$33 $66.C .$77 . read with offset of 4 bytes from R1 (byte pointer) MOVEU.B .Address Generation Unit Example 6-5. Accessing Elements in an Array of Bytes ARRAY1 ORG DCB DCB DCB DCB X:$3000 $22. Because R1 is a byte pointer and an offset of 7 bytes has been specified. set up byte pointer to base of array MOVE. . read second array element and advance pointer After the code in Example 6-5 has been executed.R1. 2nd is $22 3rd is $33.D . . 6-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .R1.BPX:(R1)+. set up byte pointer to base of array MOVE.$55 $88. read with offset of 7 bytes from R1 (byte pointer) MOVEU.B is executed. Figure 6-6 on page 6-17 demonstrates the AGU arithmetic that is performed when the instruction MOVE. Array of Bytes named “ARRAY1” 1st is $11.W#@lb(ARRAY1).

BP X:(R1+7). the byte address $6007 is accessed to load the B accumulator. Freescale Semiconductor Address Generation Unit 6-17 . the byte is actually retrieved from the upper half of the word that is located at the address $3000.Byte Pointer Memory Accesses Before Execution B X X X B $0 After Execution $0088 $0000 X Memory Word Addresses 15 0 Word Address: $3003 Byte Select: 1 (upper) $3003 $3002 $3001 $3000 $88 $66 $44 $22 $77 $55 $33 $11 >>1 $3003 $3002 $3001 $3000 15 X Memory 0 $88 $66 $44 $22 $77 $55 $33 $11 LSB $6007 R1 $6000 + Byte Address: $6007 N $9876 N $9876 R1 $6000 M01 $FFFF Short Immediate Value from the Instruction Word M01 $FFFF Figure 6-6. Executing the MOVEU. Note that because this address is a byte address.B Instruction As Figure 6-6 shows.

AGU Address Arithmetic Instructions Instruction Address Calculation Rn = Rn+Rm Rn = Rn+(Rm<<1) N = Rn+Rm N = Rn+(Rm<<1) Rn = #x+Rn N = #x+Rn Rn = #xxxx+Rm Rn = #xxxx+(Rm<<1) Rn = #xxxx+HHH #x is a 4-bit unsigned value.Rm. For more detailed information.HHH.L Rm. but the condition codes are set based on the lowest 16 bits of the result. Comments ADDA Rm. HHH—data ALU register that is treated as a signed 16-bit value. The result is not stored.L #xxxxxx.Rn ADDA.7 AGU Arithmetic Instructions In addition to the address arithmetic performed by the various addressing modes.Rn ADDA Rm.Rn ADDA.Rn DECTSTA Rn Rn = (Rm<<1) Rn = (Rn>>1) Rn–Rm Rn–Rm Rn = Rn–1 Arithmetic right shift. “Instruction Set Details. #xxxx is an unsigned 16-bit value. HHH—data ALU register that is treated as a signed 16-bit value. Table 6-5 summarizes the AGU arithmetic instructions. HHH—data ALU register that is treated as a signed 16-bit value. The result is not stored. calculating results the same way for both. Decrement by one and then set the condition codes. HHH—data ALU register that is treated as a signed 16-bit value. #xxxx is an unsigned 16-bit value.Rn ASRA Rn CMPA Rm. #xxxxxx is a signed 24-bit value.L #xxxx. 6-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The AGU arithmetic instructions enable more complex address calculations.L #xxxxxx. #xxxxxx is a signed 24-bit value. #xxxx is a signed 17-bit value.Rn ADDA.Rm.L Rm. #xxxx is an unsigned 16-bit value.L #xxxx.HHH.Rn ADDA #x. #x is a 4-bit unsigned value.” Table 6-5.HHH.N ADDA #xxxx. #xxxx is an unsigned 16-bit value.Rn Rn = #xxxxxx+Rm Rn = #xxxxxx+(Rm<<1) Rn = #xxxxxx+HHH ADDA. These instructions make no distinction between word and byte pointers. #xxxx is an unsigned 16-bit value.Rm.Address Generation Unit 6.Rn Rn = #xxxx+(HHH<<1) ADDA #xxxxxx. refer to the appropriate entry in Appendix A.Rn.Rn CMPA.N ADDA #x. the AGU supports a number of powerful instructions for directly manipulating address registers.Rn ADDA #xxxxxx.Rn ADDA.Rm.Rn ADDA #xxxx. but the condition codes are set based on the 24-bit result.W Rm.N ADDA.Rn Rn = #xxxxxx+(HHH<<1) ASLA Rm.Rn.Rn.HHH.

Zero extend a byte value. Sign extend the upper 8 bits of a register using the value of bit 15 for sign extension.Rn TSTA.L Rn TSTDECA.B Rn TSTA.Rn SUBA #xx. Decrement by two.W Rn Rn = Rn & 0x0000FF Rn = Rn & 0x00FFFF Section 6.AGU Arithmetic Instructions Table 6-5.” lists the AGU arithmetic instructions that can be affected by modulo arithmetic.B Rn SXTA.W Rn Rn–0 Rn = Rn–1 ZXTA. Test the lower 16 bits of the value in the Rn register. Negate register value DECA Rn DECA.B Rn ZXTA. but the condition codes are set based on the result.3.L Rn LSRA Rn NEGA Rn SUBA Rm. AGU Address Arithmetic Instructions (Continued) Instruction Address Calculation Rn = Rn–1 Rn = Rn–2 Rn = (Rn>>1) Rn = –(Rn) Rn = Rn–Rm SP = SP–#xx Rn = sign_extend(Rn. set the condition codes. Transfer one 24-bit register to another. and then decrement the register.W Rn (Rn & 0x00FFFF)–0 TSTA.W Rn TFRA Rm. Sign extend the upper 16 bits of a register using the value of bit 7 for sign extension. Logical right shift.8. but the condition codes are set based on the lower 8 bits of the result.5.15) Rn = Rm (Rn & 0x0000FF)–0 #x is a 6-bit unsigned value. Test byte—the result is not stored anywhere. Test word—the result is not stored. Freescale Semiconductor Address Generation Unit 6-19 . Zero extend a word value. Test long—the result is not stored. but the condition codes are set based on the lower 16 bits of the result.SP SXTA. “Modulo Addressing for AGU Arithmetic Instructions. Comments Decrement by one.7) Rn = sign_extend(Rn.

Modulo arithmetic allows the creation of special data structures in memory. rather than by moving large blocks of data. N. 6. A circular buffer is a block of sequential memory locations with a special property: a pointer into the buffer is limited to the buffer’s address range. Data is manipulated by updating address registers (pointers) rather than moving large blocks of data. The DSP56800E architecture provides support for these algorithms by implementing modulo arithmetic in the address generation unit. Many DSC and standard control algorithms require the use of specialized data structures. Addresses are normally considered unsigned. the pointer is “wrapped” back to the beginning of the buffer. offsets are considered signed. Linear arithmetic is performed on the R2–R5. and must be manually set according to the address arithmetic selection when shadow registers are swapped. N. –1. This behavior is achieved by performing modulo arithmetic when the buffer pointers are incremented or decremented. Memory accesses using the R2-R5. is used in the address calculations. and SP registers. and SP registers at all times. Similarly.8 Linear and Modulo Address Arithmetic When an arithmetic operation is performed in the address generation unit. Modulo arithmetic is not available for the R2–R5. FIFOs. The 24-bit offset register N. See Figure 6-7. and stacks.Address Generation Unit 6. The M01 register is set to $FFFF on reset. Using these structures allows data to be manipulated simply by updating address register pointers. such as circular buffers.8.8. decrementing a pointer that is located at the beginning of the buffer wraps the pointer to the end. or a displacement value). Linear arithmetic is required for general purpose address computation and is found on all microprocessors. two modes of address computation can be used: linear or modulo arithmetic. 6-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The shadow register for M01 is not initialized on reset. When a buffer pointer is incremented such that it would point past the end of the buffer. It is performed using 24-bit two’s-complement addition and subtraction. N. consider a circular buffer. or immediate data (+1.1 Linear Address Arithmetic The alternative to modulo address arithmetic is linear arithmetic. as found on general-purpose microprocessors.2 Understanding Modulo Arithmetic To understand modulo address arithmetic. Linear arithmetic is enabled for the R0 and R1 registers through setting the modifier register (M01) to $FFFF. 6. and SP pointers are always performed with linear arithmetic. Modulo arithmetic is enabled for the R0 and R1 registers through programming the modifier register (M01).

The lower boundary of the range in which the pointer registers will wrap is the value in the R0 or R1 register with the low-order k bits all set to zero. the address range is not arbitrary.3. “Configuring Modulo Arithmetic. The lower bound of the range is calculated by taking the size of the buffer. programming the M01 register enables the R0 and R1 address pointers to wrap in the buffer area. and the pointers wrap correctly in the circular buffer. For example: for a buffer size of M. but limited based on the value placed in M01. This value is the buffer size rounded up to the next higher power of two. After a buffer is established in memory. Freescale Semiconductor Address Generation Unit 6-21 . See Section 6. 2k would be 64. Due to the design of the modulo arithmetic unit.Linear and Modulo Address Arithmetic Upper Boundary: Lower Boundary + M01 Address Pointer Circular Buffer M01 = Size of Modulo Region Minus One Lower Boundary: k LSBs Are All Zeros Address of Lower Boundary: 23 Base Address k k–1 .8.. the smallest value of k is calculated such that 2k > M. effectively rounding the value down to the nearest multiple of 2k (64 in this case). rounding it up to the next higher power of two.. The address range within which the address pointers will wrap is determined by the value that is placed in the M01 register and by the address that is contained within one of the pointer registers. and then rounding the address contained in the R0 or R1 pointer down to the nearest multiple of that value. For a value M of 37. Modulo arithmetic is enabled through programming the M01 register with a value that is one less than the size of the circular buffer.” for exact details on programming the M01 register. Once modulo arithmetic is enabled. 1 0 0 0 0 0 0 Figure 6-7. updates to the R0 or R1 register using one of the post-increment or post-decrement addressing modes are performed with modulo arithmetic. This example is shown in Figure 6-8. Circular Buffer The modulo arithmetic unit in the AGU simplifies the use of a circular buffer by handling the address pointer wrapping for you.

only the low-order k bits are modified. 6.3. “Memory Locations Not Accessible Using Modulo Arithmetic.2. there is a range of addresses between M and 2k – 1 (37 and 63 in the preceding example) that are not addressable. but it also affects the AGU arithmetic instructions. the sizes of both buffers are the same.3 Configuring Modulo Arithmetic As noted in Section 6. M01 = (size of the buffer in bytes) – 1. 37-Location Circular Buffer When modulo arithmetic is performed on the buffer pointer register. This single register enables modulo arithmetic for both the R0 and R1 registers. 6-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The pointers can refer to the same or different buffers as desired. Section 6. M01.1 Configuring for Byte and Word Accesses Modulo arithmetic affects not only the arithmetic used in calculating effective addresses for move instructions.” modulo arithmetic is enabled through programming the address modifier register.3.8.” discusses this issue in greater detail.8. If the size of the buffer is not an even power of two. in order for modulo arithmetic to be enabled for the R1 register. fixing the address range of the buffer. The algorithm used to update the pointer register (R0 in this case) is as follows: R0[23:k] = R0[23:k] R0[k–1:0] = (R0[k–1:0] + offset) MOD (M01 + 1) Note that this algorithm can result in some memory addresses being inaccessible using modulo addressing.8. However. When both pointers use modulo arithmetic. Table 6-6 shows how the M01 register is correctly programmed for instructions that perform byte or word memory accesses as well as for the AGU arithmetic instructions. “Understanding Modulo Arithmetic. it must be enabled for the R0 register as well. For byte memory accesses: • • Modulo arithmetic is performed on byte addresses. 6.8. the upper 24 – k bits are held constant.9.Address Generation Unit Memory $00B0 (Unavailable Addresses) Upper Boundary: $00A4 Lower Bound + Size – 1 = Upper Bound $009F Initial R0 Pointer Value Circular Buffer Lower Boundary: $0080 Lower Bound Relative to R0 Figure 6-8.

.. Freescale Semiconductor Address Generation Unit 6-23 . Programming the M01 Register—Byte and Word Accesses 16-Bit M01 Register Contents $0000 $0001 $0002 ... $3FFE $3FFF $4000 .2 Configuring for Long Word Accesses The modifier register must be programmed a little differently when long-word data is to be accessed. Modulo 16383 Modulo 16384 (Reserved) . R0 and R1 pointers R0 and R1 pointers — . $FFFE $FFFF Address Arithmetic Performed (Reserved) Modulo 2 Modulo 3 .Linear and Modulo Address Arithmetic For word memory accesses: • • Modulo arithmetic is performed on word addresses.. Since each long-word location in the modulo buffer uses up two word memory locations. (Reserved) (Reserved) Modulo 2 Modulo 3 .8. $BFFE $BFFF $C000 .... $4000–$8000. — R0 and R1 pointers NOTE: The reserved sets of modifier values ($0000.. and $C000–$FFFE) must not be used.. Table 6-6.. Modulo 16383 Modulo 16384 (Reserved) . which means that M01 will always be programmed with an odd value.. M01 = (size of the buffer in words) – 1. The behavior of the modulo arithmetic unit is undefined for these values and might result in erratic program execution. the size of the modulo buffer in words must always be an even number.... $7FFF $8000 $8001 $8002 ... 6.. — — R0 and R1 pointers R0 and R1 pointers ...3.. R0 pointer only R0 pointer only — . (Reserved) Linear Arithmetic Pointer Registers Affected — R0 pointer only R0 pointer only ....

calculate M01 as follows: M01 = ( 2 × 4 ) – 1 = 8–1 = 7 The four 32-bit locations would require 8 words of data memory. so the M01 register is programmed with the value “$0007. For example. M01 = 2 × (size of the buffer in long words) – 1 Table 6-7 on page 6-25 shows how the M01 register is correctly programmed for long memory accesses. Note that all valid entries in this table are odd values.Address Generation Unit For long-word memory accesses: • • Modulo arithmetic is performed on word addresses. which results from the fact that 2 words are allocated for each long value in the modulo buffer. to create a circular buffer with four 32-bit locations.” 6-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

(Not available) Modulo 16382 (Not available) Modulo 16384 (Reserved) .... and all even values) must not be used...... $3FFC $3FFD $3FFE $3FFF $4000 .....Linear and Modulo Address Arithmetic Table 6-7.. $FFFE $FFFF Address Arithmetic Performed (Reserved) Modulo 2 (Not available) Modulo 4 (Not available) . The behavior of the Freescale Semiconductor Address Generation Unit 6-25 .......... $C000–$FFFE. (Not available) Modulo 16382 (Not available) Modulo 16384 (Reserved) . R0 and R1 pointers R0 and R1 pointers R0 and R1 pointers R0 and R1 pointers — . Programming the M01 Register—Long-Word Accesses 16-Bit M01 Register Contents $0000 $0001 $0002 $0003 $0004 . $4000–$8000. $7FFF $8000 $8001 $8002 $8003 $8004 .. (Reserved) Linear Arithmetic Pointer Registers Affected — R0 pointer only R0 pointer only R0 pointer only R0 pointer only .. (Reserved) (Reserved) Modulo 2 (Not available) Modulo 4 (Not available) . — R0 and R1 pointers NOTE: The reserved sets of modifier values ($0000. $BFFC $BFFD $BFFE $BFFF $C000 . — — R0 and R1 pointers R0 and R1 pointers R0 and R1 pointers R0 and R1 pointers . R0 pointer only R0 pointer only R0 pointer only R0 pointer only — .

9.5. The remaining 14 bits of M01 hold the size of the buffer minus one. — X:(Rn+>>xxxxxx) Rn >>xxxxxx 6-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .8. “Supported Memory Access Instructions. The high-order 2 bits of the M01 register determine the arithmetic mode for R0 and R1.1 Operand Placement Table Table 6-8 shows which operand is used as a base pointer and which is used as offset value for the addressing modes (X: notation) or instructions listed below. For example. Table 6-8.” on page 6-34. the base pointer is Rn and the offset value is N. there is always a “base pointer” and an “offset value” or “update value”.Address Generation Unit modulo arithmetic unit is undefined for these values and might result in erratic program execution. A value of 10 for M01[15:14] selects modulo arithmetic for both R0 and R1. “Restrictions on the Offset Register.8. This table only applies to instructions where: • • modulo arithmetic is enabled. Rn must be positive for correct modulo operation. In the X:(Rn)+N addressing mode. then Table 6-8 can be ignored.” on page 6-29). A value of 00 for M01[15:14] selects modulo arithmetic for R0. and R0 (or R1) are used as source registers in the addressing mode or instruction.4.2. the base pointer is Rn and the update value is N. The base pointer specifies an AGU register or absolute address which points to a location in the modulo buffer.8. 6. A value of 11 disables modulo arithmetic.4 Base Pointer and Offset Values in Modulo Instructions For all instructions supporting modulo arithmetic (see Section 6. and the size of the offsets are subject to the restriction in Section 6.8. If either of these conditions is not true. 6. in the X:(Rn+N) addressing mode. The offset (update) value is an immediate offset or AGU register which specifies the amount used as an offset or an update to the pointer. Base Pointer and Offset/Update for DSP56800E Instructions Addressing Mode or Instruction X:(Rn) X:(Rn)+ X:(Rn)X:(Rn)+N X:(Rn+N) X:(RRR+x) X:(Rn+>xxxx) X:(Rn+>xxxx) Base Pointer Rn Rn Rn Rn Rn RRR Rn >xxxx Offset Value (Update Value) (no offset) +1 -1 N N x >xxxx Rn Comments — — — — — — — Alternate use for this addressing mode.

Rx ADDA.4. there are no restrictions on which operand is used as pointer and which is used as offset.Rx.Rx.Rx 6.3 for the case where the immediate value is negative.2 Example of Incorrect Modulo Operation Using the above table.Ry TSTDECA.L Rx.8.HHH.N ADDA.Ry ADDA #>>xxxxxx.Ry ADDA.Linear and Modulo Address Arithmetic Table 6-8.N ADDA #>xxxx.HHH.4.W Rx Ry Ry #>xxxx #>>xxxxxx Rx Rx Rx Ry Rx Rx Rx Rx Rx -1 -2 -1 Rx -1 The following four instructions will not perform modulo arithmetic because R0 and R1 are not source operands for the instruction.Rx ADDA #x.N ADDA #x.Ry.8.Rx #>>xxxxxx. As a result.Ry DECA Rx DECA. we can see that the example below incorrectly uses the modulo addressing mode because the pointer and offset are not mapped to the correct operands.4.Ry ADDA.L #>>xxxxxx.Rx. • • • • ADDA ADDA #>xxxx.Rx.Ry Ry Ry Rx Rx #>xxxx Rx Rx Rx #x #x Rx #>xxxx ADDA #>>xxxxxx.Ry ADDA Rx.Ry. — — — — — See Section 6. — See Section 6. Rn must be positive for correct modulo operation.L Rx DECTSTA Rx SUBA Rx.Rx.HHH. Base Pointer and Offset/Update for DSP56800E Instructions Addressing Mode or Instruction X:(Rn+>>xxxxxx) Base Pointer >>xxxxxx Offset Value (Update Value) Rn Comments Alternate use for this addressing mode.HHH.8. — — — — — — — — — ADDA Rx.L #>xxxx.3 for the case where the immediate value is negative.L #>>xxxxxx. Freescale Semiconductor Address Generation Unit 6-27 .Rx.Ry ADDA #>xxxx.Ry #>>xxxxxx Rx Rx #>>xxxxxx ADDA.L Rx.Rx ADDA.Rx.L #>xxxx.

. then modulo operation works correctly if the following formula is used: Offset = Buffer_Size .4.W#$008000. .4.L #$008000. then simply use the instruction as shown in the example below: Example 6-7.INCORRECT .R0 . NOT Rn Offset Value used in addressing mode NOTE: placed in Rn.Desired_Offset Example 6-8.3 Special Case . this can also be accomplished using the ADDA instruction. buffer size = 5 Base Pointer for modulo buffer NOTE: placed in N. If the immediate offset satisfies the size restriction in Section 6. Adding “–2” to a Modulo Pointer BUFF_SIZE EQU 5 MOVEU.1 Case 1. .4. Base Pointer for modulo buffer . Modulo Enabled.W#BUFF_SIZE-1.M01 MOVE. This is because only a single modulo wraparound is detected.Address Generation Unit Example 6-6.4.R0 . Adding Positive Offset to a Modulo Pointer BUFF_SIZE EQU 5 MOVEU.R0 ADDA #(BUFF_SIZE-2).Initialization MOVEU.ADDA Instructions in Modulo Arithmetic It is possible to use the ADDA instruction to add or subtract immediate offsets from a pointer when modulo arithmetic is enabled. 6.3.4 Restrictions on the Offset Values Modulo addressing will work correctly with the post-update addressing mode.X0 . the 16-bit absolute value |N| must be less than or equal to M01 + 1 for proper modulo addressing.base pointer in N . .R0 ADDA #3. Part 2 . as long as it satisfies the following condition: • If an offset N is used in the address calculations.N MOVEU. If the immediate offset satisfies the size restriction in Section 6. the ADDA instruction can be used.W X:(R0+N).pointer/offset placement violates rules in Table 6-8 MOVE. buffer size = 5 . .4.offset value in R0 The solution to the above example would be to place $008000 into R0 and #-2 into N.W#$5-1. Adding a Negative Immediate Offset to a Pointer In the case where a negative value is to be added to a pointer.8.3.W#-2. Performs incorrect arithmetic .8. Part 1 .8.8. Update base pointer using positive value 6.L #$008000.M01 MOVEU.M01 MOVE.8.4. Then the instruction works correctly. . Update base pointer by -2 6. NOT N . (Rn)+N. Modulo Enabled. buffer size = 5 . Invalid Use of the Modulo Addressing Mode . Adding a Positive Immediate Offset to a Pointer In the case where a positive value is to be added to a pointer. 6. Modulo Enabled. Base Pointer for modulo buffer .W#$BUFF_SIZE-1.2 Case 2.8. 6-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .4.R0 .4.

another copy .W X:(R0-50).5 Supported Memory Access Instructions Depending on the size of the memory values that are being accessed when modulo arithmetic is enabled. different addressing modes and instructions are supported.R0 .5. Example 6-9.R0 .W X:(R0+50).M01.W X:(R0+N). On Example 6-9.8.Note: offset <= BUFF_SIZE TFRA N. Initialization MOVEU. “Base Pointer and Offset Values in Modulo Instructions. Modulo Enabled. offset in N MOVE. Buffer Size .8. where Rn is R0 or R1: (Rn) (Rn)– (Rn+N) (Rn+xxxx) (Rn)+ (Rn+xxxxxx) The addressing modes that support modulo arithmetic for byte accesses when word pointers are used are more limited: (Rn+x) (Rn+xxxx) (Rn+xxxxxx) Freescale Semiconductor Address Generation Unit 6-29 .1 Modulo Addressing for Word Memory Accesses The DSP56800E core’s address generation unit supports modulo arithmetic for the following address-register-indirect modes when Rn is R0 or R1: (Rn) (Rn+N) (Rn+xxxx) (Rn)+ (Rn)+N (Rn+xxxxxx) (Rn)– (Rn+x) Modulo arithmetic can also be programmed for both the R0 and the R1 pointers. offset is 50 MOVE. the correct usage of offset values is demonstrated. “Configuring Modulo Arithmetic.2 Modulo Addressing for Byte and Long Memory Accesses Modulo arithmetic is also supported for both byte and long memory accesses.” on page 6-26) used as offset values are subject to this same constraint.Offset Values Satisfying Restriction BUFF_SIZE EQU 64 .X0 .X0 .X0 .4. 6.R0 .W X:(R0)+N. Modulo Arithmetic works correctly for the following instructions: MOVE. Base Pointer for modulo buffer MOVE. Offset register . offset in N 6. Offset register .L #$008000. offset in N MOVE.X0 .Linear and Modulo Address Arithmetic Modulo addressing also requires that any immediate values or AGU registers (see Section 6.W #50.8.8. When byte pointers are used. offset in R4 SUBA N. the following addressing modes support modulo address arithmetic.” 6. offset is -50 ADDA R4. Correct Usage .3. buffer size = 64 MOVE.R4 .5.8.N . as shown in Section 6.W#BUFF_SIZE-1.

L SUBA DECTSTA Refer to Section 6.ADDA Instructions in Modulo Arithmetic. 6-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 6. The application locates this buffer at X:$800 in memory.8.8.3.1 In order for the AGU to be configured correctly to manage this circular buffer.” on page 6-28 for special considerations on the ADDA instruction. 1. when modulo arithmetic is used while accessing long-word values.3.6 Simple Circular Buffer Example Suppose a five-location circular buffer is needed for an application.8. “Special Case . the following two pieces of information are needed: • • The size of the buffer: 5 words The location of the buffer: X:$0800–X:$0804 Modulo addressing is enabled for the R0 pointer through writing the size minus one ($0004) to M01[13:0] and writing 00 to M01[15:14].5. This location is arbitrary—any location in data memory would suffice. See Figure 6-9. any of the following addressing modes can be used: (Rn) (Rn)– (Rn+N) (Rn+xxxx) (Rn)+ (Rn+xxxxxx) Be careful to configure the M01 register properly based on the type of data that is being accessed when modulo arithmetic has been enabled.8.3 Modulo Addressing for AGU Arithmetic Instructions The DSP56800E address generation unit also supports using modulo address arithmetic with some AGU instructions.Address Generation Unit Finally.” for more information.W For those supported AGU instructions that have more than one operand.4. NOTE: ADDA. “Configuring Modulo Arithmetic. modulo arithmetic will be used if any of the source operands is a register for which modulo arithmetic has been enabled.L DECA. 6. See Section 6. The supported instructions are the following: ADDA* DECA TSTDECA.

the pointer value “wraps” back to $0800. Initializing the Circular Buffer MOVEU.W X:(R0)+. Consider the source code in Example 6-12 on page 6-32. Example 6-10. Note that the initial value of R0 does not have to be X:$0800 to establish this address as the lower bound of the buffer.W X:(R0)+. First time accesses location $0800 and bumps the pointer to location $0801 Second accesses at location $0801 Third accesses at location $0802 Fourth accesses at location $0803 Fifth accesses at location $0804 and bumps the pointer to location $0800 .W#(5-1).W X:(R0)+. rather than incrementing from $0804 to $0805. Example 6-11. from $0800 to $0801. Freescale Semiconductor Address Generation Unit 6-31 .X0 MOVE. . where R0 is post-incremented by three rather than one. The behavior is similar when the buffer pointer register is incremented by a value greater than one.W X:(R0)+. .R0 . which is eight. $0802. The pointer register correctly “wraps” from $0803 to $0801—the pointer does not have to land exactly on the upper or lower bound of the buffer for the modulo arithmetic to wrap the value properly.X0 MOVE. .Linear and Modulo Address Arithmetic $0804 Circular Buffer R0 $0800 M01 Register = Size – 1 = 5 – 1 = $0004 Figure 6-9. The source code in Example 6-10 shows the initialization of the example buffer. . . Simple Five-Location Circular Buffer The location of the buffer in memory is determined by the value of the R0 pointer when it is used to access memory. Accessing the Circular Buffer MOVE. as in Example 6-11.X0 MOVE. .W X:(R0)+.W#$0800. ..X0 . Sixth accesses at location $0800 <=== NOTE . For the first several memory accesses.X0 MOVE.W X:(R0)+. it is often convenient to set R0 to the beginning of the buffer. Seventh accesses at location $0801 .X0 MOVE.X0 MOVE. The value in R0 is then rounded down to the nearest multiple of eight.W X:(R0)+. For the base address to be X:$0800.X0 MOVE. R0 is initialized to the value of the lower boundary The buffer is used simply through being accessed with MOVE instructions. The size of the memory buffer (five in this case) is rounded up to the nearest power of two.. and so forth. However. the initial value of R0 must be in the range X:$0800–X:$0804. The effect of modulo address arithmetic becomes apparent when the buffer is accessed multiple times. Initialize the buffer for five locations R0 can be initialized to any location within the buffer.W X:(R0)+. . the buffer pointer is incremented as expected. . and so forth.M01 MOVEU. When the pointer reaches the top of the buffer. For simplicity. .

and bumps the pointer to location $0804 .W#3. then the addresses of the lower and upper boundaries of the circular buffer will fit in this open area for J = 2: Lower boundary = (J × 64) = (2 × 64) = 128 = $0080 Upper boundary = (J × 64) + 36 = (2 × 64) + 36 = 164 = $00A4 — The exact area of memory in which a circular buffer is prepared is specified by picking a value for the address pointer register. 1. Initialize “bump value” to 3 . Thus. derive the characteristics of the lower boundary of the circular buffer. In this case.X0 MOVE.W X:(R0)+N. In this example. Fourth accesses at . Instructions that post-decrement the buffer pointer also work correctly.X0 MOVE. the value would be 2k ≥ 37.N NOP NOP MOVE. Executing the instruction MOVE.W X:(R0)+N.. selecting a value of 139 ($008B) for R0 would locate the circular buffer between locations 128 and 164 ($0080 to $00A4) in memory since the upper 18 (from a total of 24 – k) bits of the address indicate that the lower boundary is 128 ($0080).Address Generation Unit Example 6-12. From k.X0 when the value of R0 is $0800 will correctly set R0 to $0804. Since the k number of least significant bits of the address of the lower boundary must all be zeros. . 4. If modulo arithmetic is to be enabled only for the R0 address register. it can be no larger than 16.W X:(R0)+N. — The location of the circular buffer in memory is determined by the upper (24 – k) bits of the address pointer register that is used in a modulo arithmetic operation.384 locations. then the buffer base address must be some multiple of 2k.R0 MOVEU. Initialize the pointer to $0800 . k = 6. .8.7 Setting Up a Modulo Buffer The following steps detail the process of setting up and using the 37-location circular buffer that is shown in Figure 6-8 on page 6-22. Third accesses at location $0801 . For example. In addition. R0 or R1. First time accesses location $0800 and bumps the pointer to location $0803 Second accesses at location $0803 and wraps the pointer around to $0801 . Determine the value for the M01 register.W#$0800.X0 . the result is the following: M01 = # locations – 1 = 37 – 1 = 36 = $0024 — If modulo arithmetic is to be enabled for both the R0 and R1 address registers. 6-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X0 MOVE. Find the nearest power of two that is greater than or equal to the circular buffer size. Accessing the Circular Buffer with Post-Update by Three MOVEU. — Select the size of the desired buffer. be sure to set the high-order bit of M01. Locate the circular buffer in memory. so the base address is some multiple of 26 = 64. In this case: M01 = # locations – 1 + $8000 = 37 – 1 + 32768 = 32804 = $8024 2.W X:(R0)+N.W X:(R0)-. 6.. which gives a value of k = 6. the pointer register does not need to be incremented. 3. whose value is inclusively between the desired lower and upper boundaries of the circular buffer. . if there is an open area of memory from locations 111 to 189 ($006F to $00BD).

the result is data-dependent and unpredictable except for the special case where N is a multiple of the block size. 6.” 7. the modulo arithmetic operation occurs when an instruction is executed that uses any of the addressing modes in Section 6. (|N|) used when performing modulo arithmetic is less than or equal to M01. “Supported Memory Access Instructions. “Wrapping to a Different Bank. the primary address arithmetic unit automatically wraps the address pointer around by the required amount. 2k M (Rn) ± N MOD M01 where N = 2k (L = 1) 2k M Figure 6-10. — If the result of the arithmetic calculation would exceed the upper or lower bound. 2k: N = L × (2k). as shown in Figure 6-10. 2k. 5. when the absolute value of the offset register N.8 Wrapping to a Different Bank Normally. wrapping around is correctly performed.8. it must be selected as follows: |N| ≤ M01 + 1 |N| refers to the absolute value of the contents of the offset register.8. However.8. if |N| is greater than M01. 6. the pointer Rn is updated using linear arithmetic to the same relative address that is L blocks forward in memory. the size and exact location of the circular buffer is defined once a value is assigned to the M01 register and to the address pointer register (R0 or R1) that will be used in a modulo arithmetic calculation. is discussed in Section 6. — The special case where N is a multiple of the block size. — If the offset register is used in a modulo arithmetic calculation.” with the R0 (or R1.Linear and Modulo Address Arithmetic In summary. — Once the appropriate registers are set up. Perform the modulo arithmetic calculation. if enabled) register. where L is a positive integer. Linear Addressing with a Modulo Modifier Freescale Semiconductor Address Generation Unit 6-33 . Select a value for the offset register if it is used in modulo operations. In this special case.8.5. Determine the upper boundary of the circular buffer: upper boundary = lower boundary + number of locations – 1.

the buffer size is 37. there are some potential side effects that must be noted. 6. resulting in unusual behavior. be careful in selecting the value of N. there are some restrictions and limitations that relate to the fact that the base address of a buffer must be a power of two. 6-34 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . However. or the no-update addressing mode makes these locations available. a MOVE. In Figure 6-8 on page 6-22. if the post-update addressing mode—(Rn)+N—is used. Thus. there are locations above the upper boundary that are not accessible through modulo addressing.1 When a Pointer Lies Outside a Modulo Buffer If a pointer is outside the valid modulo buffer range.9 Side Effects of Modulo Arithmetic Due to the way modulo arithmetic is implemented by the DSP56800E.8. 6. and an operation occurs that causes R0 or R1 to be updated. which is not a power of two. M01 =5. since R0 is outside the boundary. This requirement means that for buffers that are not an exact power of two. and that the modulo arithmetic unit can only detect a single wraparound.9. which the AGU cannot detect. These locations are still accessible when modulo arithmetic is not performed. absolute addresses.8.3 Memory Locations Not Accessible Using Modulo Arithmetic When the size of a modulo buffer is not a power of two. Lower boundaries for modulo buffers always begin on an address where the lowest k bits are zeros—that is.8. 6. there is a range of memory locations immediately after the buffer that are not accessible with modulo addressing. The smallest power of two that is greater than 37 is 64. Specifically. For example. for example.(M01 + 1) for the new contents of R0 and sets it to 0. 6. the address calculation is R0 + N . Using linear addressing (with the R2–R5 pointers).2 Restrictions on the Offset Register The modulo arithmetic unit in the AGU is only capable of detecting a single wraparound of an address pointer.W B. These 27 locations are between the upper boundary + 1 = $00A5 and the next power-of-two boundary address – 1 = $00C0 – 1 = $00BF. As a result. implementing a bank of parallel IIR filters) or N-dimensional arrays. there are 64 – 37 = 27 memory locations that are not accessible with modulo addressing. This technique is useful in sequentially processing multiple tables (for example.Address Generation Unit Note that this case requires that the offset N must be a positive two’s-complement integer. Values of |N| that are larger than the size of the buffer may result in the Rn address value wrapping twice. and N = 0) would apparently leave R0 unchanged since N is zero. a power of two.X:(R0)+N instruction (where R0 = 6. The primary address arithmetic unit will automatically wrap around the address pointer by the required amount. Care should be taken to ensure that the R0 and R1 pointers always point into a valid modulo buffer when modulo address arithmetic is enabled.8. This can result in the pointer register being updated with an unexpected value. the contents of the pointer are still updated using modulo arithmetic.9.9. The 16-bit absolute value |N| must be less than or equal to M01 + 1 for proper modulo addressing.

It also covers the use of the ANDC. NOTE: The bitfield operations cannot be performed on program memory locations. The bit-manipulation unit can perform the following operations: • Testing selected bits in a 16-bit word: — BFTSTH: Test a selected set of bits for all ones — BFTSTL: Test a selected set of bits for all zeros • Testing selected bits in the upper or lower byte of a word and branching accordingly: — BRSET: Branch if a selected set of bits is all ones — BRCLR: Branch if a selected set of bits is all zeros • Testing and modifying bits in a 16-bit word: — BFSET: Test and then set a selected set of bits — BFCLR: Test and then clear a selected set of bits — BFCHG: Test and then invert a selected set of bits — BFSC: Test and then set/clear bitfield (DSP56800EX core only) The bit-manipulation unit is connected to the major data buses within the core. enabling it to manipulate data ALU registers. A variety of programming techniques for using the bit-manipulation instructions more effectively is also presented. or inverting any bits that are specified in a 16-bit mask. the Y register. which test and update a value in a single atomic. non-interruptible operation. clearing. There is no need to transfer data to dedicated bit-manipulation unit registers. AGU registers. Test-and-set instructions are especially useful for implementing semaphores and other key system-programming operations. the bit-manipulation unit does not have any registers.Chapter 7 Bit-Manipulation Unit The bit-manipulation unit performs bitfield operations on data memory and registers within the core. and NOTC instructions for performing logical operations with immediate data. in fact. Freescale Semiconductor Bit-Manipulation Unit 7-1 . It is capable of testing. This design greatly improves program and compiler efficiency. or the HWS register. setting. and peripheral registers as well as locations in memory. This chapter describes the architecture and operation of the bit-manipulation unit. EORC. ORC. This unit also performs test-and-set operations.

1 Bit-Manipulation Unit Overview and Architecture The bit-manipulation unit contains the following: • • • • 8-bit mask shifting unit 16-bit masking unit 16-bit testing unit 16-bit logic unit A block diagram of the bit-manipulation unit appears in Figure 7-1.1 8-Bit Mask Shift Unit The 8-bit mask shift unit performs two dedicated functions: • • Right shifting an 8-bit immediate mask from the upper byte of a word to the lower byte of a word. 7.Bit-Manipulation Unit 7. See Example 7-1 on page 7-3. zeroing the upper 8 bits of the mask Passing the upper 8 bits of the immediate mask to the 16-bit masking unit. DSC Core Registers Data Memory Locations Peripheral Registers CDBR CDBW IP-BUS Interface PDB Optional 8-Bit Mask Shift 16-Bit Masking Unit Test with 16-Bit Mask 16-Bit Logic Unit Bit-Manipulation Unit To Carry Bit in the Status Register Figure 7-1. 7-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . zeroing out the lower 8 bits of the mask This shifter is used when the BRCLR and BRSET instructions are executed.1. These instructions test only the upper or lower byte of a word. Bit-Manipulation Unit Block Diagram The blocks within the bit-manipulation unit are explained in the following sections.

7. and BFSET instructions: • • • • • • Tests the selected bits for ones Sets the C bit if all tested bits are one Clears the C bit if not all tested bits are ones Tests the selected bits for zeros Sets the C bit if all tested bits are zero Clears the C bit if not all tested bits are zeros For the BFTSTL and BRCLR instructions: These testing steps are performed before any modifications are made to the operand (by the BFCHG. the testing logic performs the following: For the BFTSTH.X0. The result of the test is then recorded in the status register’s carry bit.2 16-Bit Masking Logic The 16-bit masking logic selects which of the bits in a 16-bit word will be operated on by the bit-manipulation unit. All other bits in the X0 register (bits 15–8 and bits 3–0) are ignored and not modified by this instruction.LABEL1. Immediate Mask = $00F0 Note that bit masks are always specified with the use of an immediate value. 7. Bits that are set to one in the mask are tested when the bit-manipulation operation is performed. Example 7-2 demonstrates an instruction that specifies a bit mask. Examples of Byte Masks in BRSET and BRCLR Instructions BRCLR #$0081. BFTSTL. BRSET. BFCHG. and BFSET instructions).1. This unit can optionally be bypassed. Bits that are set to zero in the mask are ignored. Example 7-2.X:$3. Immediate Mask in lower byte BRSET #$81. and BFSET) work with a full 16-bit mask. Based on the instruction used. so no shifting is required. passing through a 16-bit mask directly to the 16-bit masking unit.3 16-Bit Testing Logic The 16-bit testing logic tests all bits that are specified in the immediate mask value. Freescale Semiconductor Bit-Manipulation Unit 7-3 .Bit-Manipulation Unit Overview and Architecture Example 7-1.LABEL1. bits 7–4.X0.LABEL1. The DSP56800E instruction set does not support mask values in a register. BFCLR. Immediate Mask in lower byte BRCLR #$8100. BFCLR. The 4 bits that are set to one. BFCLR.1. BFCHG. and only these 4 bits are tested and then cleared by the bit-manipulation unit. Using a Mask to Operate on Bits 7–4 BFCLR #$00F0. It is capable of determining if the selected bits are either all ones or all zeros. Immediate Mask in upper byte The other bit-manipulation instructions (BFTSTH.X0 . Only the carry bit in the status register is affected. are selected by the 16-bit masking unit. The result of the test is stored in the status register’s carry bit.

1 Testing Bits The bit-manipulation unit can test a set of bits within an operand. Example 7-3 presents an example of an instruction that performs this operation.4 16-Bit Logic Unit The 16-bit logic unit performs any modifications to the operand value before it is written back to the original register or memory location. In most cases. This unit performs the following operations for the following instructions: • • • BFCHG—Inverts the bits selected by the 16-bit mask BFCLR—Clears the bits selected by the 16-bit mask BFSET—Sets the bits selected by the 16-bit mask Any bit that is not selected by the 16-bit mask is not modified. 7. Testing Bits in an Operand BFTSTL #$000F.2 Conditional Branching The bit-manipulation unit can test a set of bits in an operand and execute a conditional branch based on the result of the test. 2. 7.1. 4. a 16-bit mask is reduced to 8 bits. 3.Bit-Manipulation Unit 7. Test lower 4 bits of memory location 7. “16-Bit Testing Logic.3. Write the result of this test to the C bit in the status register (SR).2.” 5. Create a 16-bit mask directly from the instruction itself. Test all of the selected bits within this value. This testing operation is performed by the following instructions: • • BFTSTH BFTSTL The basic operations performed are: 1. Example 7-3. but for the BRSET and BRCLR instructions. Check for whether all selected bits are zeros or ones.2. where either the upper or lower eight bits are zeros. as described in Section 7. A description of each operation appears in its own subsection. Read the 16-bit operand from memory or from a register.X:$C000 .1. Use the mask to select the desired bits within the 16-bit operand that was already read from an on-chip register or memory location. This operation is performed by the following instructions: • • BRCLR BRSET 7-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the instruction directly provides the 16-bit mask.2 Bit-Manipulation Unit Operation There are three different types of operations performed by the bit-manipulation unit.

” 2. and NOTC With the use of the following four operations. Freescale Semiconductor Bit-Manipulation Unit 7-5 . Perform steps 1 through 5 in Section 7. or set all bits selected by the 16-bit mask.2. Clear upper byte of memory location 7.” process selected bits in the original 16-bit source using the 16-bit logic unit and write the results back to their original source.LABEL4 . Write this modified result back to the 16-bit source operand. ORC. Example 7-5.” on page 4-11 for additional information. Invert. “Testing Bits. 3. Example 7-4 presents an example of an instruction that performs this operation.1. EORC.X:(R0) . This operation is performed by the following instructions: • • • • BFCHG BFCLR BFSET BFSC (DSP56800EX core only) The basic operations performed are: 1. Perform steps 1 through 5 in Section 7. EORC. the bit-manipulation unit gives the DSP56800E core the capability to perform logical operations with immediate data: • • • • ANDC—logically AND a 16-bit immediate value with an operand EORC—logically exclusive OR a 16-bit immediate value with an operand ORC—logically OR a 16-bit immediate value with an operand NOTC—take the logical one’s-complement of a 16-bit destination The operations ANDC. in addition to performing the testing that is described in Section 7. ORC. The instructions that perform these operations.1.3 Modifying Selected Bits The bit-manipulation unit can perform logical operations on selected bits in an operand. and NOTC are not instructions. Note that these three steps are a non-interruptible sequence because they are implemented within a single bit-manipulation instruction. Example 7-4.2.3 ANDC. Branch to the specified target address if the result of the test performed is True. and NOTC The basic operations performed are: 1.1. they are aliases to the bit-manipulation instructions that are identified in the preceding list. Otherwise. Example 7-5 presents an example of an instruction that performs this operation. See Section 4.3. “16-Bit Testing Logic. Branching on Bits in an Operand BRSET #$8000. and NOTC Aliases. clear. ORC. ORC. Clearing Bits in an Operand BFCLR #$FF00.1. continue program execution with the next sequential instruction. EORC.2. Branch to LABEL4 if MSB set in X:(Rn) 7. “Testing Bits.ANDC.X:(R0). EORC.” 2. “The ANDC.2.

” on page 5-14 for more information.5. that the ANDC instruction alias inverts the mask.5.5 Programming Considerations In order to use the bit-manipulation unit effectively. and the other byte in the word should be set to zero.and 32-bit rotate instructions.1 Bit-Manipulation Operations on Registers There are some potential side effects to consider when performing bit-manipulation operations on AGU registers or the accumulators: When bit-manipulation operations (BFCHG. 16. some considerations must be kept in mind when writing code that uses it. 7. Incrementing and decrementing of memory locations. Take special care when performing a bitfield operation on one of the data ALU accumulator registers. the 8-bit mask to be used should be placed in the upper or lower byte of the 16-bit mask.” for more details. 7. The following sections describe the recommended approach to take. The bit-manipulation capabilities within the data ALU unit include: • • • • • 16.2. In general. The data ALU instructions complement the capabilities of the bit-manipulation unit. so the byte mask should be padded with ones instead of zeros. and a variety of programming techniques that can be employed.2 Bit-Manipulation Operations on Byte Values The bit-manipulation instructions are designed to manipulate 16-bit quantities.or 32-bit bi-directional logical and arithmetic shifting. In all but the last case. This arrangement might have potentially adverse side effects when memory-mapped peripheral registers are operated on. the upper 8 bits of the register are set to zero. 7-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .or 32-bit logical operations. This ensures that only bits in the appropriate byte are affected. Saturation may occur when an accumulator is accessed by the bit-manipulation unit. 7. or BFSET) are performed on 24-bit AGU registers. however. Together these two units provide very powerful bit-manipulation capabilities for efficient control processing. Note. It is possible. Note that these operations still access and store 16-bit quantities. operations are performed directly on the registers within the data ALU unit. BFCLR. “Data Arithmetic Logic Unit. The mask is simply set so that only 1 byte is operated on.7. Single-bit arithmetic and logical shifts. Single-bit 16.Bit-Manipulation Unit 7. “Bit-Manipulation Operations on Accumulators. See Section 5. when using the bit-manipulation unit. to perform bit-manipulations on byte values by carefully selecting the 16-bit mask. however.4 Other Bit-Manipulation Capabilities The bit-manipulation unit is supplemented by the capabilities found within the DSP56800E’s data ALU unit. Refer to Chapter 5.

2. The offset that is added to the pointer is the offset value in bytes.X:$1000 . For even byte addresses.1 Absolute Addresses For absolute addresses. and the lower 8 bits of the mask are zeroed.2 Word Pointers with Byte Offsets A technique that is similar to the one described in Section 7. and the upper 8 bits of the mask are zeroed. Freescale Semiconductor Bit-Manipulation Unit 7-7 . the 8-bit mask is placed in the upper 8 bits of the 16-bit mask. the 8-bit mask is placed in the upper 8 bits of the 16-bit mask. and the upper 8 bits of the mask are zeroed. Two examples appear in Example 7-6. ===> 8-bit mask in upper byte of 16-bit mask. (8-bit mask placed in upper byte) Similar techniques can be used for performing bit operations on bytes with other addressing modes. for upper byte at word address ORC #$F800. Bit Operation . the following rules apply: • • • The address used in the bit-manipulation instruction is the byte address. arithmetically right shifted 1 bit.1. (8-bit mask placed in lower byte) . ===> 8-bit mask in lower byte of 16-bit mask. the 8-bit mask is placed in the lower 8 bits of the 16-bit mask. AND the value $1F with a byte in data memory . Example 7-6. “Absolute Addresses.Programming Considerations 7. the technique that is outlined in Section 7.X:$1000 .” is used for synthesizing an address. For odd byte addresses. for lower byte at word address ANDC #$FF1F.3. such as (Rn+xxxx). Bit Operation .5.5.5. In this case.2. the following rules apply: • • • • The base address is stored in an Rn register as a word pointer. “Using Complex Addressing Modes. For even byte addresses. OR the value $F8 with a byte in data memory .5. Logical Operations on Bytes in Memory .2. and the lower 8 bits of the mask are zeroed. For addresses with byte offsets. the 8-bit mask is placed in the lower 8 bits of the 16-bit mask. 7.” can be used for manipulating a byte referenced through a word pointer with a byte offset. Two examples appear in Example 7-7 on page 7-8. For odd byte addresses. logically right shifted 1 bit.

N = Rn + (byte offset >> 1) ANDC #$F8FF. Example 7-8. N = (Rn+xxxx) BFSET #MASK. Perform operation with synthesized address 7. 7. BFSET #MASK. BFCLR #MASK.4 Synthetic Conditional Branch and Jump Operations The flexible instruction set of the DSP56800E architecture allows new bit-manipulation operations to be synthesized with the use of existing DSP56800E instructions. Table 7-1 lists operations that can be synthesized in this manner.X:(N) . the lower byte at word address X:$1001) ===> Word Pointer = $1000. . N = (Rn+Rm) BFCLR #MASK. Then the bit-manipulation operation is performed with the X:(N) addressing mode.5. AND the value $1F with the byte in data memory (that is. Bit-Manipulation Operations Using Complex Addressing Modes .Rn. AGU arithmetic can be performed to emulate the desired addressing mode. Bit Operation .X:(Rn+xxxx) Operation — performed in two instructions ADDA #xxxx.5. Operations Synthesized Using DSP56800E Instructions Operation JRCLR JRSET BR1CLR BR1SET Description Jumps if all selected bits in bitfield clear Jumps if all selected bits in bitfield set Branches if at least 1 selected bit in bitfield is clear Branches if at least 1 selected bit in bitfield is set 7-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Table 7-1.X:(N) .N . byte offset = 3 ===> 8-bit mask in upper byte of 16-bit mask ADDA #1. . N = Rn + (byte offset >> 1) ANDC #$FF1F. the upper byte at word address X:$1001) ===> Word Pointer = $1000. Logical Operations on Bytes Using Word Pointers . byte offset = 2 ===> 8-bit mask in lower byte of 16-bit mask ADDA #1.Bit-Manipulation Unit Example 7-7. with the resulting address stored in the N register. . (8-bit mask placed in lower byte) AND the value $F8 with the byte in data memory (that is. (8-bit mask placed in upper byte) .3 Using Complex Addressing Modes It is possible to create bit-manipulation operations with more complex addressing modes. Bit Operation .N .Rn. This section presents some of these useful operations that are not directly supported by the DSP56800E instruction set but that can be efficiently synthesized by the user.X:(N) .N . Similar techniques can be used for performing bit operations on bytes with other addressing modes. Perform operation with synthesized address .X:(Rn+Rm) Operation — performed in two instructions ADDA Rm. . Example 7-8 shows code that emulates more complex addressing modes.Rn. . .Rn.N .X:(N) .

overflows. it would be more useful to branch if at least 1 bit in the mask matched. they can use the same addressing modes as those bit-manipulation instructions. 16-bit mask allowed BCC LABEL10 . the BRSET and BRCLR instructions only allow branches to locations that are up to 64 locations away from the current instruction.X:<ea> . BR1SET Operation — performed in two DSP56800E instructions BFTSTL #MASK. 7-. Like BRSET and BRCLR. the design of these instructions is such that all the bits in the mask must match the value being tested. 19.5.4.4. In some cases. 7. JRSET Operation — performed in two DSP56800E instructions BFTSTH #MASK.or 21-bit jump address allowed JRSET and JRCLR use the BFTSTH and BFTSTL instructions to perform the bitfield test. 7. depending on the selected bits in a bitfield. However.X:<ea> . 16-bit mask allowed BCC LABEL10 . or other condition codes. and they can only test an 8-bit bitfield. or the branch is not taken. 18-. See Example 7-10. 16-bit mask allowed JCS LABEL9 . 19. Example 7-10.X:<ea> . allowed . they perform a bitfield test and branch based on the result. However. NOTE: None of these operations are actual DSP56800E instructions. 22-bit signed PC-relative offset . Thus. 16-bit mask allowed JCS LABEL9 .Programming Considerations Table 7-1. Operations Synthesized Using DSP56800E Instructions (Continued) Operation JR1CLR JR1SET Description Jumps if at least 1 selected bit in bitfield is clear Jumps if at least 1 selected bit in bitfield is set Several operations for jumping and branching can be emulated. The JRSET and JRCLR operations allow jumps to anywhere in the program address space and can specify a 16-bit mask.5.X:<ea> . BR1CLR Operation — performed in two DSP56800E instructions BFTSTH #MASK. Example 7-9. since they branch to a different address based on a bitfield comparison.1 JRSET and JRCLR Operations The JRSET and JRCLR operations are very similar to the BRSET and BRCLR instructions. 22-bit signed PC-relative offset . JRSET and JRCLR Operations . 18-. JRCLR Operation — performed in two DSP56800E instructions BFTSTL #MASK.2 BR1SET and BR1CLR Operations The BRSET and BRCLR instructions are very useful. The BR1SET and BR1CLR operations provide just that functionality. allowed Freescale Semiconductor Bit-Manipulation Unit 7-9 . 7-. they are macros that can be created from existing instructions.or 21-bit jump address allowed . BR1SET and BR1CLR Operations .

and 21-bit jump to absolute address allowed .X:<ea> .3 JR1SET and JR1CLR Operations The JR1SET and JR1CLR operations function almost identically to the BR1SET and BR1CLR operations that are described in Section 7. “BR1SET and BR1CLR Operations. These operations allow the same addressing modes as the BFTSTH and BFTSTL instructions. the BR1SET and BR1CLR operations can also specify a 16-bit mask. JR1SET Operation — performed in two DSP56800E instructions BFTSTL #MASK. 7-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . See Example 7-11. JR1SET and JR1CLR Operations .5.X:<ea> . JR1CLR Operation — performed in two DSP56800E instructions BFTSTH #MASK. allowing jumps to anywhere in the program address space. Example 7-11.5. as compared to an 8-bit mask for BRSET and BRCLR.and 21-bit jump to absolute address allowed The JR1SET and JR1CLR operations specify a 16-bit mask and a 19-bit target address.” The JR1SET and JR1CLR operations differ from the BR1SET and BR1CLR operations in that the former pair uses absolute addressing. 19. 19.4.2. 16-bit mask allowed JCC LABEL11 .Bit-Manipulation Unit In addition to having the ability to branch based on a single bit. 7. These operations allow the same addressing modes as the BFTSTH and BFTSTL instructions.4. 16-bit mask allowed JCC LABEL11 .

It also contains dedicated circuitry to accelerate looping operations. It fetches and decodes instructions. and directs program flow. including reset and exception processing. “Processing States. see Chapter 10. coordinates the other core units in executing the instructions. are covered in Chapter 9. including details on stack handling and no-overhead hardware looping. As the figure shows. This chapter describes the program controller’s function. including exception processing. Freescale Semiconductor Program Controller 8-1 .Chapter 8 Program Controller The program controller is perhaps the most important unit in the DSC core.” For more in-depth information on the execution pipeline.1 Program Controller Architecture A block diagram of the program controller is given in Figure 8-1 on page 8-2.” 8. The different processing states. “Instruction Pipeline. the following major blocks are located within the program controller: • • • • • Instruction latch and decoder Program counter (PC) Hardware stack Looping control unit Interrupt control unit The blocks and registers within the program controller are explained in the following sections.

Program Controller PAB CDBR CDBW 21-Bit Incrementer Program Counter 20 PC Hardware Stack 23 HWS0 HWS1 20 Fast Interrupt Return Address 0 FIRA PDB 0 15 Instruction Latch 0 0 LF NL Instruction Decoder Control Signals 23 Loop Address LA LA2 15 Loop Counter LC LC2 Looping Control 0 Interrupt Controller (Located Outside the DSC Core) IPR 0 Interrupt Control Interrupt Arbitration Interrupt Request |1.1 Instruction Latch and Decoder The instruction latch is a 16-bit internal register that is used to hold instruction opcodes that are fetched from memory. Program Controller Block Diagram 8. SR) 15 OMR SR MODA.|0 Bits from SR Operating Mode and Status Register (OMR. The instruction decoder uses the contents of the instruction latch to control and synchronize the other execution units in performing the specified operation. 8-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .1. MODB Signals 0 Control Bits to DSC Core Condition Codes from Data ALU or AGU Status and Control Bits to DSC Core Interrupt Priority Update 12 0 FISR Fast Interrupt Status Register Figure 8-1.

6 Interrupt Controller The interrupt controller is responsible for arbitrating all interrupt requests from the core and on-chip resources. See Section 8. “Hardware Stack Register. “Program Counter Extension (P0–P4)—Bits 10–14. and a non-maskable hardware stack overflow interrupt occurs. For more information on the hardware looping capabilities that are included in the core. resulting in substantial time savings. and then it checks the priority of the highest request against the interrupt mask bits for the DSC core (I1 and I0 in the SR). The lowest 16 bits are stored in the PC register.2 Program Counter The program counter (PC) is a 21-bit register that contains the address of the next item that is to be fetched from program memory. which performs interrupt arbitration and indicates when an enabled interrupt request is pending.1. 8. When the stack limit is exceeded. There is no interrupt on hardware stack underflow. see Section 8.” on page 9-2. The PC can point to instructions. no instruction can manipulate it directly.5 Interrupt Control Unit The interrupt control unit coordinates interrupt and exception processing in the core. It stores the address of the first instruction in a loop. Under normal operation.” for more information. last-in-first-out (LIFO) stack that is used to enable the nesting of hardware loops. “Interrupt Controller. It is assisted in this task by the interrupt controller (located outside the core). DO.4 Hardware Stack The hardware stack is a 2-deep. or addresses of operands.3 Looping Control Unit The looping control unit controls the hardware-accelerated looping capability in the core. NOTE: The interrupt controller is not part of the DSC core.1. the oldest loop information (top-of-loop address and LF bit) is lost.” 8.” 8.” Interrupt arbitration and the exception processing state are discussed in Section 9. See Section 8.5. If the requesting interrupt has higher priority than the current priority level of the DSC core. The hardware stack can be manipulated under program control using the hardware stack register (HWS). With the REP.2.2. “Exception Processing State. all references to this register are implicit. and DOSLC instructions.2. then the unit generates a single enabled interrupt request signal to the interrupt control unit within the core. but it is included on any chip that is based on the DSP56800E or DSP56800EX core. “Hardware Looping.1. 8.6.1. while the top 5 bits are located in the upper word of the status register (SR).3. The program counter value is split between two locations in the core.10. 24-bit-wide. so execution of an outer hardware loop can continue when an inner hardware loop has completed. data operands. Freescale Semiconductor Program Controller 8-3 . which is discussed in Section 8. It typically arbitrates among all available interrupt requests.7.Program Controller Architecture 8.1.1. program loops can be executed with very little overhead.

Program Controller Programming Model 8.Program Controller 8. It is used to configure the memory map and the operation of the data ALU. SR) 15 0 OMR SR 20 0 23 0 23 0 20 Figure 8-2. The operating mode register’s format is described in the following register display and in Table 8-1 on page 8-5.1 Operating Mode Register The operating mode register (OMR) is a 16-bit register that controls the current operating mode of the processor.2. 8-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Program Counter PC Loop Address LA LA2 Hardware Stack HWS0 HWS1 Fast Interrupt Return Address FIRA 15 0 Loop Counter LC LC2 0 Fast Interrupt Status Register 12 0 FISR Operating Mode and Status Register (OMR.2 Program Controller Programming Model The programming model for the program controller consists of seven user-accessible registers and two special registers for fast interrupt processing: • • • • • • • Status register (SR) Operating mode register (OMR) Hardware stack register (HWS) Two loop address registers (LA and LA2) Two loop count registers (LC and LC2) Fast interrupt return address register (FIRA) Fast interrupt status register (FISR) Figure 8-2 depicts the registers graphically. and it reflects the status of these and other units in the core.

This bit is dependent on the individual chip's implementation. or BFSET instructions should be used instead of a MOVE instruction to prevent the accidental modification of other bits. Operating Mode—Selects the memory map and operating mode This bit is dependent on the individual chip’s implementation. 0 = Convergent rounding. 1 = Fetched from X (data) memory. the BFCLR.” Reserved Bits 14–9 CM Bit 8 XP Bit 7 SD Bit 6 R Bit 5 SA Bit 4 EX Bit 3 These bits are reserved and always read zero. 1 = Nested DO loop active. 0 = 36-bit values are used. When individual bits in the OMR are modified. 1 = 32-bit values are used. Freescale Semiconductor Program Controller 8-5 .Program Controller Programming Model OMR BIT 15 NL TYPE RESET rw 0 0 0 0 0 14 13 12 11 Operating Mode Register 10 9 8 CM rw 0 0 0 7 XP rw 0 6 SD rw 0 5 R rw 0 4 SA rw 0 3 EX rw — 0 2 1 MB rw — BIT 0 MA rw — Table 8-1. BFCHG. Condition Code Mode—Selects whether 36-bit or 32-bit values are used for condition codes X or P Memory Select—Determines the memory space from which instructions are fetched Stop Delay—Selects length of wake-up time from stop mode Rounding—Selects the rounding method Saturation—Enables automatic saturation in the data ALU External X Memory Select—Forces all data memory access to be in external memory Reserved Bit 2 MB and MA Bits 1–0 Reserved This bit is reserved and always reads zero. 0 = Internal data memory accesses. 0 = Saturation disabled. “Hardware Stack. Note: See Section 8. Dependent on individual chip’s implementation. OMR Bit Descriptions Name NL Bit 15 Description Nested Looping—Indicates whether a nested hardware DO loop is active or whether HWS has been written to at least two times without being read Reserved Settings 0 = No nested DO loop active. 0 = Fetched from P (program) memory. 1 = Data memory accesses are external. NOTE: When a bit of the OMR is changed by an instruction. 1 = Saturation enabled.4. 1 = Two’s-complement rounding. a delay of 2 instruction cycles is necessary before the new mode comes into effect.

When the bit is set. such as multiplication or addition. Their initial values after reset are typically established by external mode select pins. This bit is cleared by processor reset. In most cases. when the bit is cleared. A long wake-up time can be useful to allow a crystal oscillator to settle before resuming instruction execution.5 Stop Delay (SD)—Bit 6 The stop delay (SD) bit selects the amount of time it takes to wake up from stop mode.2. and other instructions that round values are executed. which can be supplemented by external data memory as needed. 8.6 X or P Memory (XP)—Bit 7 The X or P memory (XP) bit is used to select the memory space—program or data—from which instructions are fetched. The two rounding modes are discussed in Section 5. After the chip leaves the reset state. this bit is cleared and instructions are fetched from program memory.” for more information on executing programs from data memory. When the SA bit is set. MB and MA can be changed under program control. MACR. Consult the appropriate device’s user’s manual for more information on the EX bit.1.1. Automatic saturation is discussed in detail in Section 5. On devices that support execution from both memory spaces.2. Normally. This bit is cleared by processor reset.6. a DSP56800E– or DSP56800EX–based device has some quantity of on-chip data memory.2.8.1.2. When cleared.2. this bit can be set so that instructions are fetched from data memory. a delay is inserted before the processor exits stop mode. 8. When set. This bit is cleared by processor reset. 8.1. saturation is performed on the results of all basic arithmetic operations. “Executing Programs from Data Memory. Typically. “MAC Output Limiter. “Rounding.2 External X Memory (EX)—Bit 3 The external X memory (EX) bit can be used to configure the location of data memory. the processor exits quickly from stop mode. two’s-complement rounding (always round up) is used.2. The EX bit can be used by a chip to select whether both on-chip and external memories are used or whether all data memory accesses are sent to external memory. The exact effect of the EX bit depends on the architecture of a given device.” on page 5-41. 8.3 Saturation (SA)—Bit 4 The saturation (SA) bit enables automatic saturation in the data ALU on 32-bit arithmetic results. saturation occurs only when an accumulator is written to memory. before they are stored in an accumulator.1 Operating Mode (MA and MB)—Bits 0–1 The operating mode (MB and MA) bits are used to select the operating mode and memory map.1. The exact length of the delay depends on the particular DSC device that is being used. Refer to Section 8. This bit is cleared by processor reset. This automatic saturation is useful for bit-exact DSC algorithms that do not recognize or cannot take advantage of the extension registers that are available with each accumulator.Program Controller 8. 8-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Consult the specific DSC device’s reference manual for more information about how these bits are established on reset and about their specific effect on operation. Consult the device’s user’s manual for more information.4 Rounding (R)—Bit 5 The rounding (R) bit selects the type of rounding that is used when RND. 8.9.1. convergent rounding is selected.” on page 5-43.2.

1. Freescale Semiconductor Program Controller 8-7 . When this bit is set. This bit is cleared by processor reset. See Section 8.2. then the program is currently executing a DO loop that is nested inside another DO loop. N. programs should not set the CM bit unless it is required for compatibility with the DSP56800 architecture. In general. If this bit is clear. If this bit is set. The DSP56800E and DSP56800EX instruction set contains test and compare instructions for byte.1.1.Program Controller Programming Model 8. including the current interrupt priority level. 8. The condition code register reflects various properties of the values that result from instruction execution. The bit has been renamed for the DSP56800E and DSP56800EX in the interest of clarity. REP looping does not affect this bit. and Z condition codes are calculated based on 32-bit results.7 Condition Code Mode (CM)—Bit 8 The condition code mode (CM) bit selects whether condition codes are calculated with 36-bit or 32-bit data ALU results.2. The mode register reflects and defines the operating state of the DSC core.2 Status Register The status register (SR) is a 16-bit register that consists of an 8-bit mode register (MR) and an 8-bit condition code register (CCR). The NL bit is also affected by any direct accesses to the hardware stack register.2.” for a more detailed discussion. obviating the need for the CM bit functionality. “Hardware Stack. a nested DO loop is not being executed. MR occupies the high-order 8 bits of the SR. and 36-bit values in the accumulators. See Section B.” on page B-3 for a more detailed description of the effect of the CM bit on the condition codes. CCR occupies the low-order 8 bits. 8. long-word. The NL bit is cleared on processor reset. NOTE: The CM bit on the DSP56800E and DSP56800EX architecture is identical in function to the DSP56800’s CC bit.8 Nested Looping (NL)—Bit 15 The nested looping (NL) bit reflects the status of hardware DO loops and the hardware stack. the C. V. word.3. This bit is used by the looping hardware to correctly save and restore the contents of the hardware stack.4. “Condition Code Mode. these condition codes are generated based on 36-bit results. When this bit is cleared.

” P4–P0 Bits 14–10 I1–I0 Bits 9–8 Dependent on execution. SR Bit Descriptions Name LF Bit 15 Description Loop Flag—Indicates whether a program loop is active or whether HWS has been written to at least once without being read Program Counter Extension—Bits 20–16 of the program counter Interrupt Mask—Masks or enables the four interrupt levels Settings 0 = No DO loop active. 1 = Not normalized. AGU arithmetic instructions. Note: See Section 8. all CCR bits are cleared. 0 = Normalized. During processor reset. 1 = Limiting has been performed. flow control instructions. 8-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 1 = DO loop active. 00 01 10 11 = Allow all interrupts. 0 = Result was positive. = Mask levels 0. bit-manipulation instructions. 0 = Extension not in use. 0 = Result was non-zero. Bits in the MR are affected by processor reset. Bits in the CCR portion of the status register are affected by data ALU operations. and many others. and 2. 1 = Result was zero. and so forth. 1 = Accumulator value is large. 1 = Carry out occurred during operation. exception processing. = Mask level 0. “Hardware Stack.Program Controller SR BIT 15 LF TYPE RESET rw 0 14 P4 r 0 13 P3 r 0 12 P2 r 0 11 P1 r 0 10 P0 r 0 Status Register 9 I1 rw 1 8 I0 rw 1 7 SZ rw 0 6 L rw 0 5 E rw 0 4 U rw 0 3 N rw 0 2 Z rw 0 1 V rw 0 BIT 0 C rw 0 Table 8-2. 1 = Extension in use. 1 = Result was negative. the interrupt mask bits in the MR are both set.4. 0 = No carry occurred during operation. The program extension bit values depend on the value of the reset vector. = Mask levels 0 and 1. and the LF bit is cleared. 0 = Result did not overflow. 0 = No limiting performed. 1 = Result overflowed destination. 1. SZ Bit 7 L Bit 6 E Bit 5 U Bit 4 N Bit 3 Z Bit 2 V Bit 1 C Bit 0 Size—Indicates growth beyond a certain point in the size of an accumulator value Limit—Indicates whether data limiting has been performed since this bit was last cleared Extension in Use—Indicates whether an accumulator extension register is in use Unnormalized—Shows whether a result value is normalized or not Negative—Indicates whether result of last operation was negative or positive Zero—Indicates whether result of last operation was zero or not Overflow—Indicates whether result of last operation overflowed its destination Carry—Set if a carry out or borrow was generated in addition or subtraction 0 = Accumulator value is small.

Thus. If overflow does not occur.” on page 5-38 and in Appendix B. “Condition Code Calculation. It is set under the following circumstances: • • • • If an addition operation results in a carry out of the MSB of the result If a borrow was necessary when a subtraction operation was performed When all bits specified by the mask are set (or cleared. otherwise it is considered positive. “Condition Code Calculation.2 Overflow (V)—Bit 1 The overflow (V) bit is set if the result of an arithmetic operation overflows (is too large to fit in) the size of the specified destination.Program Controller Programming Model A description of each of the bits in the status register appears in the following subsections. the U bit is computed as follows: U = (Bit 31 ⊕ Bit 30) Normalized values have the property that. the BFCLR. If the MSB of the result is not set.0 is satisfied.7. this condition means that bits 31 and 30 of the result should be different.5 Unnormalized (U)—Bit 4 The unnormalized (U) bit is set if the value resulting from an operation is not normalized. For an accumulator result. A value is considered normalized if all bits to the right of the binary point are significant. If the result is non-zero. the relation is –1. Freescale Semiconductor Program Controller 8-9 .2. this bit is always cleared. The descriptions that are given for the CCR bits are the standard definitions.0 < n < –0.2. the relation 0. More information on the condition code bits is found in Section 5. but these bits may be set or cleared slightly differently depending on the instruction that is being executed.1 Carry (C)—Bit 0 The carry (C) bit is used to reflect a variety of conditions. or BFSET instructions should be used instead of a MOVE instruction to prevent the accidental modification of other bits. A value is considered negative if the MSB is set.5 < p < 1. this bit is always cleared. 8.2.4 Negative (N)—Bit 3 The negative (N) bit is set if the result of an operation is negative. 8.5. for a negative value n.” NOTE: When individual bits in the SR are modified.2.2.2. BFCHG. This bit is not affected by the OMR’s CM bit.2. 8.3 Zero (Z)—Bit 2 The zero (Z) bit is set if the result of an operation is equal to zero. depending on the instruction) in their corresponding operand for bit-manipulation instructions When the last bit that is to be shifted or rotated out of the MSB or LSB of an operand in a shift or rotate operation is a one When not set under one of these conditions. 8. this bit is cleared. for a positive number p. this bit is cleared.2. 8.2.2.

2. the bits in the extension register are significant and must be considered when additional computations are performed or when the accumulator is written to memory. 1. Table 8-3 shows the exceptions that are permitted and masked for the various settings of I1 and I0. 8. 3 IPL 3 Exceptions Masked None IPL 0 IPL 0. 1. 8. 8-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .3. 3. The current priority level of the processor may be changed under software control. This bit is not affected by the OMR’s CM bit. Table 8-3. When they are not all the same. 2. this bit is set.2. The L bit is cleared only by a processor reset or by an instruction that specifically clears it.9 Interrupt Mask (I0–I1)—Bits 8–9 The interrupt mask (I1 and I0) bits set the interrupt priority level (IPL) that is needed for an interrupt source to interrupt the processor. Interrupt Mask Bits Settings I1 0 0 1 1 I0 0 1 0 1 Exceptions Permitted IPL 0. 1 IPL 0.2. The SZ bit is cleared only by a processor reset or by an instruction that specifically clears it. Otherwise.2. LP IPL 1. See the application note Implementation of Fast Fourier Transforms on Freescale’s Digital Signal Processors (document order number APR4/D) for information on implementing FFT algorithms on the DSC core. 3 IPL 2. 2. the extension portion of an accumulator (bits 35–32) just holds sign extension and can be ignored.6 Extension in Use (E)—Bit 5 The extension in use (E) bit is cleared if the high-order 5 bits (bits 35–31) of a 36-bit result are the same (00000 or 11111). When the high-order 5 bits all contain the same value. “Exception Processing State.2. 2 Exception processing is explained in detail in Section 9.8 Size (SZ)—Bit 7 The size (SZ) bit is a latching bit (sticky bit) that indicates that word growth is occurring in an algorithm. The bit is set when a 36-bit accumulator is moved to data memory and bits 30 and 29 of the source accumulator are not the same.7 Limit (L)—Bit 6 The limit (L) bit is a latching bit (sticky bit) that is set if the overflow bit is set or if the data limiters perform a limiting operation.2. 8.2.” on page 9-2. Both interrupt mask bits are set to one during processor reset. It is not affected otherwise.Program Controller 8. The setting of the SZ bit occurs via the following computation: SZ = SZ | (Bit 30 ⊕ Bit 29) This bit is especially useful for attaining maximum accuracy when a block-floating-point fast Fourier transform (FFT) is performed.2.

This arrangement ensures that LC is backed up properly when LC is loaded under program control. The LF bit is cleared during processor reset. If the loop counter is not one. The contents of LC are copied to LC2 whenever a DO instruction is executed or when an instruction is executed that explicitly modifies the LC register. The loop count register can be read and written under program control. or REP instruction).10 Program Counter Extension (P0–P4)—Bits 10–14 The program extension (P4–P0) bits form bits 20 through 16 of the program counter. 8. DOSLC. They are restored from the stack when an RTS.2. the program loop is terminated.3 Loop Count Register The loop count register (LC) is a special 16-bit counter that specifies the number of times to repeat a hardware loop (one that is begun with a DO.2.2.” for more information on how accesses to the hardware stack affect the value in LF.11 Loop Flag (LF)—Bit 15 The loop flag (LF) bit is set when a hardware (DO or DOSLC) loop is initiated or when a value is written under program control to the hardware stack. RTSD.” for a full discussion of hardware looping. Reading the hardware stack or terminating a DO or DOSLC loop causes LF to be set to the value in the OMR’s NL bit.2. such as Freescale Semiconductor Program Controller 8-11 .Program Controller Programming Model 8. See Section 8. RTI.2. NOTE: The values read (from reading the SR) are not guaranteed to be valid. and P0 corresponds to bit 16. NOTE: This bit should never be explicitly cleared by a move or bitfield instruction when the NL bit in the OMR register is set. 8. Instructions that change the value of the status register do not affect these bits. “Nested Looping (NL)—Bit 15. it is decremented by one and the program loop is repeated.” REP looping does not affect this bit. “Hardware Stack.2. When the last instruction in a hardware program loop is reached. P4 corresponds to the MSB of the 21-bit program address. See Section 8. as when a nested hardware loop is begun. If the loop counter is one. The LC register is also updated with the contents of the LC2 register when a loop is exited. the contents of the loop counter register are tested. The program extension bits are stacked by the JSR and BSR instructions for subroutines and interrupts because the complete status register is pushed by these instructions.4. 8. they cannot be directly modified. NOTE: Because these bits represent part of the program counter.2. Bits 15–0 of the program counter are found in the PC register.8. See Section 8.1.5. This capability gives software programs access to the value of the current loop iteration. “Hardware Looping.4 Loop Count Register 2 The loop count register 2 (LC2) is a 16-bit register that is used to save the value that is in LC whenever LC is modified. or RTID instruction is executed.

the contents of LA are copied to LA2 before the end-of-loop address for the inner loop is stored in LA. 8. and it is used by the looping hardware to determine when the end of a loop has been reached.L instruction. LC2 may be pushed onto or popped from the software stack under program control.4. When the register is read as a 32-bit long with a MOVE.2. “Hardware Stack. the second stack location is not directly accessible.” for more information on nested hardware loops.” for a full discussion hardware looping. This capability allows an application to save and restore this register when necessary.5. the value in LA2 is copied back to LA to allow the outer loop to continue. 8-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . When it is written as a 32-bit long by a MOVE. The HWS register is accessed with standard MOVE instructions.L instruction. When the register is read as a 32-bit long by a MOVE.” for more information.2. See Section 8. the value in the LC2 register is copied back into the LC register when the OMR's NL bit is set. Reading from or writing to HWS can affect the LF bit in the status register and the NL bit in the operating mode register. 8. as well as the alignment of the stack pointer. Critical bits in the status register (SR) and operating mode register (OMR).8 Fast Interrupt Status Register The fast interrupt status register (FISR) is a 13-bit register that is used to hold the state of the DSC core during fast interrupt processing. This capability allows an application to save and restore this register when necessary.6 Loop Address Register 2 The loop address 2 register (LA2) is a 24-bit register that is used to save the value of LA when a DO loop that is nested within another DO loop is executed. 8. at which point the contents of LA2 are copied to it. The value in the LA register is set when the DO instruction is executed. 8.Program Controller when LC is loaded with a loop count before DOSLC is executed.5 Loop Address Register The loop address (LA) register holds the location of the last instruction word in a hardware DO loop.5. only the lower 24 bits are stored in LA.2. When a DO or DOSLC loop terminates. See Section 8. When a DO or DOSLC instruction is executed. Accesses to HWS always read or write the value on the top of the stack. “Hardware Looping. When it is written as a 32-bit long by a MOVE. only the lower 24 bits are stored on the hardware stack.7 Hardware Stack Register The hardware stack register (HWS) is used to manipulate the program controller’s hardware stack under program control.L instruction. the upper 8 bits of the destination register are zero extended. are copied into the FISR at the beginning of fast interrupt processing. The LA register can be read or written using a MOVE instruction. See Section 8.L instruction. the upper 8 bits of the destination are zero extended.2. When the nested loop terminates. LA2 may be read from and written to the stack under program control. “Hardware Looping. and it may also be updated when a DO loop that is nested in another DO loop is exited. The value in the FISR is used to restore the core state when a fast interrupt processing routine is exited.

” on page 9-6 for more information on fast interrupt processing and on the use of the FISR register. which allows the stack pointer to be restored to its original value after interrupt processing is complete. N. This register is not affected by processor reset. and C bits as well as the operating mode register’s NL bit. “Fast Interrupt Processing. I1. I0. See Section 9. Value in status register on interrupt. Value in status register on interrupt.3. FISR Bit Descriptions Name Undefined Bits 15–13 SPL Bit 12 LF Bit 11 NL Bit 10 I1–I0 Bits 9–8 SZ Bit 7 L Bit 6 E Bit 5 U Bit 4 N Bit 3 Z Bit 2 V Bit 1 C Bit 0 Undefined Description Settings These bits are undefined and should be ignored. Stack Pointer LSB—Contains a copy of the LSB of the SP register Loop Flag—Contains a copy of the LF bit in the status register Nested Looping—Contains a copy of the NL bit in the operating mode register Interrupt Mask—Contains a copy of the I1 and I0 bits in the status register Size—Contains a copy of the SZ bit in the status register Limit—Contains a copy of the L bit in the status register Extension in Use—Contains a copy of the E bit in the status register Unnormalized—Contains a copy of the U bit in the status register Negative—Contains a copy of the N bit in the status register Zero—Contains a copy of the Z bit in the status register Overflow—Contains a copy of the V bit in the status register Carry—Contains a copy of the C bit in the status register Value in stack pointer on interrupt. Value in status register on interrupt. Value in status register on interrupt. Value in status register on interrupt. Value in status register on interrupt. Value in status register on interrupt. Value in status register on interrupt. E. Z.2. FISR BIT 15 14 13 12 SPL TYPE rw Fast Interrupt Status Register 11 LF rw 10 NL rw 9 I1 rw 8 I0 rw 7 SZ rw 6 L rw 5 E rw 4 U rw 3 N rw 2 Z rw 1 V rw BIT 0 C rw Table 8-4. U. Value in operating mode register on interrupt. Freescale Semiconductor Program Controller 8-13 .Program Controller Programming Model The FISR holds copies of the status register’s LF. The SPL bit holds a copy of the LSB of the stack pointer (SP). V. Value in status register on interrupt. Value in status register on interrupt. SZ. L.2.

although typically accesses are made using the stack pointer register (SP). Example 8-1.X:(SP) . erratic behavior may result. NOTE: Be careful when initializing the stack pointer to set aside enough space for the stack.SP .L A10. there is a more efficient technique in terms of both time and space. as shown in Example 8-1. Increment the SP (1 cycle. Performed in 2 cycles. for creating variables that are local to a subroutine.L A10. the software stack should be located in on-chip memory. and because the SP register always points at the item that is on the top of the stack. the stack pointer must be pre-incremented when values are pushed on the stack.SP . Placing One value onto the software stack . 2 instruction words ADDA #2.X:(SP)+ MOVE. Instead of repeating the two-instruction sequence for each value to be stored. implement the push operations that are shown in Example 8-2. 5 instruction words ADDA #2. If the address space used by the stack overlaps other data areas.9 Fast Interrupt Return Address The fast interrupt return address (FIRA) is a 21-bit register that holds a copy of the program counter when fast interrupt processing is initiated. Place value onto the stack For pushing multiple values to the stack. or for any other temporary-storage needs. Faster technique for pushing four values onto the software stack . The stack can also be used for passing parameters to subroutines. 8.3 Software Stack The software stack is a last-in-first-out (LIFO) stack of arbitrary depth that is located in data memory. Example 8-2. 8. The initial value for the stack pointer is the lower boundary of the stack—the software stack on the core grows up as values are pushed onto it.X:(SP)+ MOVE. Increment the SP (1 cycle. Pushing a Value on the Software Stack .L B10.Program Controller 8. <== No post-increment SP on last MOVE 8-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . This process involves two instructions. and it must be set in software before the stack can be used. This register is not affected by processor reset.3. Finishes in 5 cycles.2. For maximum performance. 1 Word) MOVE. This address is used to return control to the interrupted program when the fast interrupt service routine is complete.X:(SP) . The stack pointer value is undefined after reset.L R0. Any instruction that accesses data memory can be used to access locations on the stack. The JSR and BSR instructions use the software stack for saving the program counter and status register when a subroutine or interrupt service routine is called.L R1. 1 Word) MOVE.1 Pushing and Popping Values Because the stack grows up in memory. Pushing Multiple Values on the Software Stack .X:(SP)+ MOVE.

Finishes in 4 cycles.L X:(SP)-.R1 MOVE.2 Subroutines The JSR and BSR instructions are used to call subroutines. these instructions pop the program counter and status register from the stack.Software Stack Popping values from the software stack is fairly straightforward. When the interrupt service routine is complete. Data Memory SP Status Register (Contains P4–P0) Return Address (16 LSBs) Figure 8-3. as shown in Figure 8-3. Figure 8-3 shows the software stack after a JSR has been executed. When an exception occurs. with a service routine target address as its argument.A10 .R0 MOVE. 8. SP left pointing at previous top of stack 8. Effects of the JSR Instruction on the Stack The RTS and RTSD instructions pop the PC and SR off the stack when a subroutine is exited. the return address (the value in the program counter) is pushed onto the stack.3. Popping Values from the Software Stack .L X:(SP)-. in that order. Like the RTS and RTSD instructions. If there is a JSR instruction at that location. Only the P4–P0 bits are actually updated in the SR. To pop the four values that are saved on the stack in Example 8-2 on page 8-14. Unlike RTS and RTSD. When a JSR or BSR is executed. but use them to restore the status bits in SR. the remaining bits are discarded.L X:(SP)-.B10 MOVE. the return address is saved by pushing both the PC and the SR. With the use of the post-decrement addressing mode. This restoration ensures that the processor state is not changed by the actions of the interrupt service routine. the code in Example 8-3 can be executed. Freescale Semiconductor Program Controller 8-15 . 4 instruction words MOVE.3 Interrupt Service Routines Entries in the DSC core interrupt and exception vector table frequently consist of a JSR instruction. the RTI and RTID instructions do not discard the contents of the stored status register. Because the high-order 5 bits of the program counter are contained in the status register. Example 8-3. The JSR instruction stacks the program counter (the return address from the interrupted program) and status register. onto the stack.3.L X:(SP)-. the program counter is moved to the address of the appropriate entry in the vector table. an RTI or RTID instruction is executed. it is fetched and executed in the same way that a JSR would normally be executed. Popping four values from the software stack . values can be popped from the stack in a single instruction.

W X:$35. Example 8-4 also illustrates the creation and use of local variables on the stack. see Section 9. “Interrupt and Exception Processing. 8.W X:$21.. Stack locations that are above the status register and return address can be set aside for local variables by incrementing the stack pointer the required number of words.W X0. Subroutine Call with Passed Parameters ADDA #1. Store sum in 2nd variable (other instructions.WX:(SP-7). The stack frame created by the code in Example 8-4 is shown in Figure 8-4 on page 8-17.Program Controller Note that if the fast interrupt processing method is used to handle an interrupt. Example 8-4. Parameters can be passed to a subroutine by placing these variables on the software stack immediately before a JSR to the subroutine is performed.W X0. Variables that are local to a subroutine can also be conveniently allocated on the stack.. Local variables can then be accessed relative to the stack pointer. such as parameter passing to subroutines and local variables.SP MOVE. For more information on both types of interrupt processing. .4 Parameter Passing and Local Variables The software stack supports structured programming techniques. .2. Allocate room for local variables (instructions) MOVEU.X:(SP) JSR ROUTINE1 SUBA #2. . the process is quite different.W X:(R0).R0 .X:(SP)+ MOVE. . ADDA #4.SP . (pre-increment before pushing two variables) Pointer variable to be passed to subroutine (push onto stack) 2nd variable to be passed to subroutine (push onto stack) *** Execute Subroutine *** Remove the two passed parameters from stack when done ROUTINE1 . These techniques can be used for both assembly language programming as well as high-level language compilers. Get 2nd variable MOVE. . . 8-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . .” These passed parameters can then be accessed in the called subroutine with the use of SP-relative addressing modes.SP RTS .) SUBA #4. This process is demonstrated in Example 8-4.X0 .SP .B .X0 MOVE.B MOVE.” on page 9-4.3. Placing these variables on the stack is referred to as building a “stack frame. Get pointer variable MOVE.X0 MOVE. as subroutine parameters are.W B.3.X:(SP-6) . Get data pointed to by pointer variable ADD X0.W X:(SP-6). and it does not involve a JSR to an interrupt service routine.

The value in the first HWS location (HWS0) is copied to the second (HWS1). the address is popped off the stack. 3. overwriting the previous value. The hardware stack can also be manipulated under program control with the use of standard MOVE instructions. 4. 8. register 3. the stack is always accessed through the hardware stack register (HWS). Although there are two locations on the stack. so the correct return address is popped from the stack. Clears the OMR’s NL bit Freescale Semiconductor Program Controller 8-17 . either through a MOVE instruction or by the DO and DOSLC instructions saving the looping state. the following occur: 1. 2. The hardware stack is updated when a hardware DO loop is entered or exited. overwriting the previous LF value 2. be careful to de-allocate space that is reserved on the stack for local variables.4 Hardware Stack The hardware stack is a last-in-first-out (LIFO) stack that consists of two 24-bit internal registers. The SR’s LF bit is copied to the OMR’s NL bit.Hardware Stack X Data Memory SP 4th Local Variable 3rd Local Variable 2nd Local Variable 1st Local Variable Status Register Return Address 2nd Passed Parameter 1st Passed Parameter Figure 8-4. Executing a DO or DOSLC instruction (or a write to HWS) pushes the address of the first instruction in the loop onto the stack. Copies the OMR’s NL bit to the SR’s LF bit. Reads or writes to the HWS access or modify the top location in the stack. Copies the value in the second hardware stack register to the first. Example Stack Frame Before a subroutine is exited. The appropriate value is written to the top hardware stack register. overwriting the previous NL value. When a value is written to HWS. or top. When the loop terminates. Reading a value from HWS does the following: 1. The LF bit in the status register is set. The stack pointer should be decremented so that it points to the saved status register before the RTS instruction is executed.

If a repeat loop must be interruptible. See Section 8. There is no interrupt on hardware stack underflow.L A10. The number of times the instruction should be repeated is specified by the parameter to the REP instruction. the program counter is frozen and interrupts are disabled. two DO loops are active) and a DO or DOSLC instruction (or a write to HWS) is executed. “DO Looping. If the count specified is zero. Until the repeat loop is complete. Clear 2 words in memory The instruction that is to be repeated (MOVE. the instruction following REP is skipped. as shown in Table 8-5. Two types of hardware-accelerated loops are supported: fast repetition of a single instruction a specified number of times. Repeat Loop Example MOVE.W #0. To ensure the integrity of the hardware stack values. the core includes special hardware to accelerate loops. make certain that a program never puts the processor in the illegal state that this table specifies. and more traditional multi-instruction loops.5. a hardware stack overflow interrupt occurs because there is no more space on the hardware stack to support a third DO loop. 2 words at a time. especially in DSC algorithms. which is either a 6-bit immediate or 16-bit register value.L in this case) is fetched only once from program memory. In order to speed up these critical algorithms.1 Repeat (REP) Looping Repeat looping.5. using the REP instruction. 8-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The instruction that is to be repeated is the one that immediately follows REP. Set up hardware repeat of the following instruction . Clear the A Accumulator . executes a single 1-word instruction a number of times. In this example. Hardware Stack Status NL 0 0 1 1 LF 0 1 0 1 DO Loop Status No DO loops active Single DO loop active (Illegal) Two DO loops active # Words of Hardware Stack 0 1 — 2 If both the NL and LF bits are set (that is.2. 64 words are cleared in data memory. Example 8-5. using the DO and DOSLC instructions. and execution continues with the subsequent instruction.” The repeat count that is specified in the REP instruction must be a positive value.X:(R0)+ . Avoid this illegal state by ensuring that the LF bit is never explicitly cleared when the NL bit is set. Table 8-5.A REP #32 MOVE. a DO loop should be used instead. Example 8-5 demonstrates repeat looping on the move instruction.5 Hardware Looping Loops are one of the most common software constructs. 8. using the REP instruction. 8.Program Controller The state of the NL and LF bits can be used to determine the status of program looping and thus of the hardware stack.

and the LA register is loaded with the address of the last instruction word in the loop. the LA2 register is copied to LA. but assumes that the loop count has already been placed in the LC register. DO loops can be nested up to two deep. SWAP SHADOWS. the hardware stack is popped (and the popped value is discarded). accelerating more complex algorithms.A MOVE. If the value in LC is greater than one. as occurs with any hardware stack push. The DOSLC instruction does not modify the LC and LC2 registers. DEBUGHLT. loops initiated with DO are interruptible. 8.END_CPY MOVE. or ALIGNSP instruction. the LC2 register is copied to LC. LC is decremented and the loop is re-started from the top. For a DO instruction. the following events occur: 1. Hardware DO looping (DO or DOSLC) executes a block of instructions for the number of specified times. SWILP. When the end of the loop is reached. An instruction that accesses program memory. If LC is equal to one. the loop count is specified with a 6-bit unsigned value or 16-bit register value. The DOSLC instruction works identically to DO.L A10. 3. A Tcc. the contents of the LC register are copied to the LC2 register.X:(R1)+ END_CPY .Hardware Looping The REP instruction can only be used to repeatedly execute single-word instructions. Unlike REP loops. the loop has been executed for the proper number of times and should be exited. Instructions in the loop are then executed. DO Loop Example DO #40.L X:(R0)+. The address of each instruction is compared to the value in LA to see if it is the last instruction in the loop. The address of the first instruction in the program loop (top-of-loop address) is pushed onto the hardware stack.2 DO Looping The DO instruction performs hardware looping on a single instruction or a block of instructions. and the NL bit in the operating mode register is Freescale Semiconductor Program Controller 8-19 . SWI #x. If a 16-bit address is specified. When a hardware loop ends. A SWI. or STOP instruction. Repeat looping cannot be used on: • • • • • • An instruction that is more than 1 program word in length. WAIT. DEBUGEV. The old contents of the LA register are copied to the LA2 register. Any instruction that changes program flow. Example 8-6 demonstrates hardware DO looping on a block of two instructions. 2. This example copies a block of forty 32-bit memory locations from one area of memory to another. the upper 8 bits of LA are cleared. When a hardware loop is initiated with a DO or DOSLC instruction. and LC is loaded with the loop count that the instruction specifies. the loop count register is checked to see if the loop should be repeated. This push sets the LF bit and updates the NL bit. Example 8-6. Copy a 32-bit memory location . When the DO instruction is executed. A REP or ENDDO instruction. Set up hardware DO loop .5.

use one of the techniques discussed in Section 8.” 8. 8. a DO loop terminates if the count specified is zero.5.5. respectively. a DOSLC loop will also terminate. 8. When the inner loop of a nested loop terminates naturally. the instructions in the body of the loop are skipped.Program Controller copied to the LF bit. An example of this process appears in Example 8-7.5.4.A MOVE. If the NL bit is not set. Copy a 32-bit memory location . Thus. and the internal looping state will be reset correctly.1 Allowing Current Block to Finish and Then Exiting One method for terminating a DO loop is to modify the loop counter register so that the remainder of the instructions in the loop are executed. .5. DO X0.L X:(R0)+. Instruction execution then continues at the address that immediately follows the end-of-loop address.X0 . “Allowing Current Block to Finish and Then Exiting. The OMR's NL bit is then cleared. A loop count of zero can only be specified by using a register that is loaded with zero as the argument to the DO instruction.END_CPY MOVE. the hardware stack will be popped. Note that an immediate loop count of zero (for the DO instruction) is not allowed and will be rejected by the assembler. a two-deep hardware stack allows for a maximum of two nested loops. Loop count is zero upon entry . DO Loop Special Case MOVE. but so that the loop does not return to the top of the loop. This modification can be accomplished through explicitly setting the value in LC to one: MOVEU. if the LC register is zero or negative. or if a zero or negative loop count is specified for DOSLC. If it is necessary to terminate a DO loop early.X:(R1)+ END_CPY . so repeat loops can be nested within DO loops.L A10.5.” and Section 8. the LA2 and LC2 registers are copied into the LA and LC registers. “Immediate Exit from a Hardware Loop. Example 8-7. the LA and LC registers are not modified when a loop is terminated or skipped. 8-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .4 Terminating a DO Loop A DO loop normally terminates when the body of the loop has been executed for the specified number of times (the end of the loop has been reached. Alternately. Similarly. restoring these two registers with their values for the outer loop.LC Because the loop is allowed to complete.W #0. or by placing a zero in the LC register and executing DOSLC. .1. One hardware stack location is used for each nested DO or DOSLC loop. and execution continues with the instruction immediately following the loop body.4. The REP instruction does not use the hardware stack.2. A loop is determined to be a nested inner loop if the OMR’s NL bit is set. and LC is one).4.3 Specifying a Loop Count of Zero If a loop count of zero is specified for the DO instruction. which causes the body of the loop to be skipped entirely.W #1.

DO #LoopCount. without executing any more iterations in the loop. The loop is then initiated with the DOSLC instruction.LABEL (instructions in loop) Bcc EXITLP . use the ENDDO instruction. Writing a value to LC causes the previous value in LC to be copied to LC2. . Two examples of code that show how to perform immediate exits appear in Example 8-8.4. “Instruction Descriptions.5. the DOSLC instruction should be used. ENDDO only cleans up the hardware stack and the internal loop processing state. which assumes that the count has previously been loaded into LC.Hardware Looping This technique should not be used to terminate a loop that is nested within another loop. LABEL DO #LoopCount. (other instructions in loop (skipped if immediate exit)) BRA EXITLP OVER . “Immediate Exit from a Hardware Loop. A BRA or JMP instruction must be used to stop the execution of instructions within the body of the loop.” on page A-7. .LABEL (instructions) Bcc OVER . Immediate Exit from Hardware Loop . .” for the correct usage of this instruction). NOTE: There are restrictions on the location of instructions that modify the LC register with respect to the end of the loop. additional cycle for BRA for normal loop exit . Example 8-8.5.2. Freescale Semiconductor Program Controller 8-21 .5 Specifying a Large Immediate Loop Count The DO instruction allows an immediate value up to 63 to be specified for the loop count. A 16-bit immediate loop count can be loaded into the LC register before the loop is started.2 Immediate Exit from a Hardware Loop When it is necessary to break out of a loop immediately. LABEL 8.5. executed each iteration ENDDO . . executed only for immediate termination BRA LABEL (instructions) -----. .2. In cases where it is necessary to specify a value that is larger than 63. thus destroying the outer loop’s count. Note that the ENDDO instruction does not cause execution to jump to the end of the loop. 8. See the sections concerning DO and DOSLC in Section A. 1 additional cycle for ENDDO when exiting .alternate method -----ENDDO OVER . A nested DO loop can be terminated by using the ENDDO instruction (see Section 8. loop if exit via Bcc OVER .4. Example 8-9 on page 8-22 demonstrates this technique.

Specify a loop count greater than 63 using the LC register (delay required due to pipeline) . Set up hardware DO loop . including NOP if no useful instruction can be placed in the sequence.X0 MOVE. and dual loop address registers act as a LIFO stack for hardware looping state information.X0 DO #10. . 8.5.. Using the DOSLC Instruction MOVEU. Example 8-10. . or to nest a REP loop within a DO loop or within two nested DO loops.W A1. (body of DO loop) .W X:(R0)+.LC NOP NOP DOSLC LABEL (instructions) . The hardware stack. Example 8-10 demonstrates a repeat loop nested within a DO loop. (read first value) .X:(R1)+ END_NST .6 Nested Hardware Looping The DSC core architecture allows one hardware-accelerated DO loop to be nested within another. LABEL Note that a delay of 2 instruction words must be inserted between the instruction that updates LC and the DOSLC instruction. The following sections describe the nesting of hardware loops. . 8.W A REP #8 ADD X0. It is possible to nest one hardware DO loop within another.2 Nesting a DO Loop Within a DO Loop Nested looping of DO and DOSLC loops is permitted on the DSC core architecture. accumulate eight values .. 8. Because the hardware stack only contains two locations. Each of these words can consist of any instruction.1 Nesting a REP Loop Within a DO Loop A hardware repeat loop can be nested within a hardware DO loop without any additional setup or processing. Example 8-11 on page 8-23 demonstrates one hardware loop nested within another.6.6.W#2048. In this example.A X:(R0)+. Example of a REP Loop Nested Within a DO Loop MOVE. The loop count. 8-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the repeat loop accumulates 8 values and stores the result for 10 different blocks of data. hardware DO and DOSLC loops can only be stacked two deep.Program Controller Example 8-9. and the state of the LF and NL bits are maintained for an outer loop when a nested hardware loop is executed.END_NST CLR.5. dual loop count. store result of eight accumulated values Note that the REP instruction does not affect the value of the loop count for the outer DO loop. Start loop with count already in LC . .5. the “top-of-loop” address.

(required by pipeline) #4. only the lower 221 locations in data memory can be accessed in data-memory execution mode. (body of innermost loop) . a NOP instruction has been placed between the loop end labels to ensure that they end on different instructions.5.W A ASL B END_INNR DECTSTAR5 BGT OUTER .END_INNR INC.6 Executing Programs from Data Memory The core is designed with the ability to execute programs stored in data memory. (bump to unoccupied stack location) . In Example 8-11. the outer and inner loops must not end on the same instruction. and the memory places its result on the XDB2 bus. (body of innermost loop) . Note that. Program instructions and interrupt vectors are downloaded into data memory. it is useful for executing diagnostic and test code on parts where program memory resides in ROM. Inner DO loop . Branch to top of loop .6. 8. Any useful instruction could be substituted for the NOP. Example of Nested DO Loops ADDA #1. Figure 8-5 on page 8-24 shows the memory map in this mode. Example 8-12. Decrement Outer Loop Counter . where they can be executed later. .END_OUTR #3. 8.Executing Programs from Data Memory Example 8-11. due to dependencies in the execution pipeline. Software loops should only be used when necessary. When instructions from data memory are executed. Although this capability is not intended for high-throughput DSC applications. Load R5 for four outer loop iterations As compared to a hardware loop. Outer Inner (body (body loop loop: saves LC->LC2.W#4. . Freescale Semiconductor Program Controller 8-23 . one of the loops can always be performed with standard software looping techniques. Example 8-12 demonstrates a hardware DO loop that is nested in a regular software loop.R5 OUTER DO #4. a software loop involves considerably more looping overhead. because the program address bus (PAB) is only 21 bits wide. or in code where execution time is not critical. . LA->LA2 of innermost loop) of innermost loop) Note that.SP CLR.3 Nesting a DO Loop Within a Software Loop If more than two loops need to be nested. Example of Nested Looping in Software MOVEU.W A DO DO INC. the core drives the address of the instruction onto the XAB2 bus.END_INNR A B . where the execution units expect to find it.W ASL END_INNR NOP END_OUTR . The data on this bus is then internally transferred to the PDB bus.

It is not possible to have the core exit reset and then go straight into data-memory execution mode. Internal program memory is not accessible in this mode.Program Controller $FFFFFF 16M × 16 Data Memory Space $0 Interrupt Vectors 0 The XP bit in OMR enables this operating mode. The interrupt vector table can also be located in these memory spaces. Data Memory (EX = 0) $FFFFFF Locations above $1FFFFF are not accessible in data-memory execution mode. $1FFFFF $00FFFF $00FF80 On-Chip Peripherals External Data On. This event places the device back into normal program-memory execution mode.and off-chip data memory can hold both data and program instructions to be executed. the XP bit in the OMR register is cleared. Example Data-Memory Execution Mode Memory Map When reset occurs. $0 $0 Memory On-Chip Data Memory Figure 8-5. 8-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Program Memory $1FFFFF External program memory is not accessible in this mode.

(wait for interrupts to be disabled) NOP . (indicates code located in program memory) . Download the desired program—including interrupt vectors. Disable Interrupts NOP . 3. only a single NOP instruction must be inserted between the BFSET instruction that sets the XP bit and the JMP instruction (rather than two). Beginning address of program in data memory ORG P: . and data constants—into data memory. (wait for interrupts to be disabled) NOP . 4. Enable data memory instruction fetches NOP . Example 8-13 shows the sequence that must be used when a 19-bit target address is used: Example 8-13.1 Entering Data-Memory Execution Mode A specific sequence must be followed to switch to executing programs from data memory. To enter data-memory execution mode. (fetched but not executed) NOP . Disable interrupts in the status register (SR). . . (wait for mode to switch) NOP . (fetched but not executed) NOP .X:BEGIN_X. 19-Bit Target Address BEGIN_X EQU $1000 . Depending on the size of the target address specified in the JMP to instructions in data memory. Freescale Semiconductor Program Controller 8-25 . Set the XP bit in the operating mode register (OMR).Forces 19-bit Address JMP >XMEM_TARGET . and a different assembler forcing operator is specified in the JMP instruction.OMR .Executing Programs from Data Memory 8. interrupt service routines. . (wait for interrupts to be disabled) NOP . Jump to the first instruction in data memory. NOTE: Must Use Assembler Forcing Operator . (wait for mode to switch) . (fetched but not executed) ORG P:BEGIN_X. This code sequence is given in Example 8-14 on page 8-26. These steps translate into one of two code sequences. Jump to 1st instruction in data memory NOP . Remember to re-enable interrupts If a 21-bit target address is specified. 2. the code sequence is slightly different. perform the following steps: 1. In particular. (both must be the same value) XMEM_TARGET . a slightly different sequence must be used. 5.SR . (wait for interrupts to be disabled) NOP . Re-enable interrupts from code in data memory (if desired). Entering Data Memory Execution.6. (wait for interrupts to be disabled) BFSET #$0080. which are shown in Example 8-13 and Example 8-14 on page 8-26. Exact Sequence for Steps 3 through 5 BFSET #$0300.

(wait for interrupts to be disabled) NOP . 8. (wait for interrupts to be disabled) BFSET #$0080.6. Disable interrupts in the status register.Forces 21-bit address JMP >>XMEM_TARGET. NOTE: The code that is used to enter data-memory execution mode must contain the exact number of NOP instructions that is shown in Example 8-13 on page 8-25 or Example 8-14. 8-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . . (fetched but not executed) NOP . and when it is necessary to begin executing instructions from the program memory space. Enable data memory instruction fetches NOP . must be known absolute addresses. Either the code sequence given in Example 8-15 on page 8-27 or the one in Example 8-16 on page 8-27 must be used for exiting data-memory execution mode. the following sequence of operations must be performed: 1. Exact Sequence for Steps 3 through 5 BFSET #$0300. . There can be no jumps or branches to instructions within this sequence. 2. (fetched but not executed) ORG P:BEGIN_X. Re-enable interrupts from code that is located in program memory space. Clear the XP bit in the operating mode register.SR .OMR .X:BEGIN_X. Jump to the return location in the program memory space.2 Exiting Data-Memory Execution Mode When executing instructions from data memory is no longer required. This technique defines the target code address as the same absolute address in both program and data memory. The sequence that is used depends on the size of the target address specified by the JMP instruction. (fetched but not executed) NOP . NOTE: Must Use Assembler Forcing Operator -. (wait for interrupts to be disabled) NOP . Entering Data Memory Execution. 3. (wait for mode to switch) . The target addresses of the JMP instructions in Example 8-13 on page 8-25 and Example 8-14. Labels should not be used unless the technique that is shown in the examples is employed. Jump to 1st instruction in data memory NOP . which causes the assembler to generate the correct JMP target address. (wait for interrupts to be disabled) NOP . (wait for interrupts to be disabled) NOP . 21-Bit Target Address BEGIN_X EQU $1000 . . 4. which are located in data memory. Beginning address of program in data memory ORG P: . it is very important that the instruction segment between setting the XP bit (or clearing it) and the JMP instruction should not be single stepped. Remember to re-enable interrupts Choose the location of the first instruction in data memory carefully. (indicates code located in program memory) . Disable Interrupts NOP .Program Controller Example 8-14. Because of the nature of this operation. (both must be the same value) XMEM_TARGET .

(wait for interrupts to be disabled) NOP .6. (wait for mode to switch) . (wait for interrupts to be disabled) NOP . (wait for interrupts to be disabled) NOP . (wait for interrupts to be disabled) NOP . (fetched but not executed) NOP .” also apply when exiting data-memory execution. “Entering Data-Memory Execution Mode. (indicates code located in program memory) The rules for determining the target address of the JMP instruction that are discussed in Section 8. Disable data memory instruction fetches NOP . (wait for mode to switch) NOP . NOTE: Freescale Semiconductor Program Controller 8-27 .X:BEGIN_X.SR . Exiting Data-Memory Execution Mode. (wait for interrupts to be disabled) NOP . Disable interrupts NOP . (fetched but not executed) ORG . Exiting Data-Memory Execution Mode. . Jump to 1st instruction in program memory NOP . Remember to re-enable interrupts P: . (wait for interrupts to be disabled) BFCLR #$0080. 19-Bit Target Address ORG P:BEGIN_X. . (wait for interrupts to be disabled) NOP . PMEM_TARGET . (fetched but not executed) NOP . . NOTE: Must Use Assembler Forcing Operator -. (wait for interrupts to be disabled) BFCLR #$0080. . (code located in data memory) .X:BEGIN_X. Example 8-16. Disable data memory instruction fetches NOP . (fetched but not executed) ORG .Forces 19-bit address JMP >PMEM_TARGET . 21-Bit Target Address ORG P:BEGIN_X.OMR . (fetched but not executed) NOP . (wait for interrupts to be disabled) NOP . Jump to 1st instruction in program memory NOP .OMR . NOTE: Must Use Assembler Forcing Operator . . (indicates code located in prgm mem) If a 21-bit target address must be specified for the JMP instruction.Executing Programs from Data Memory Example 8-15. . Exact Sequence for Steps 1 through 3 BFSET #$0300. .1.SR . . (wait for mode to switch) . (wait for interrupts to be disabled) NOP . Disable interrupts NOP . (code located in data memory) . . Remember to re-enable interrupts P: . Exact Sequence for Steps 1 through 3 BFSET #$0300. (fetched but not executed) NOP . . the code sequence in Example 8-16 must be used.Forces 21-bit address JMP >>PMEM_TARGET. PMEM_TARGET .

8-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 8. There can be no jumps or branches to instructions within this sequence.6. During the transition in and out of data-memory execution mode. The interrupt vector table and all interrupt service routines must be copied to data memory because program memory is completely disabled when data-memory execution mode is active. Interrupts must be disabled when data-memory execution mode is entered or exited. interrupts must be disabled.4 Restrictions on Data-Memory Execution Mode The following restrictions apply when programs are executed from data memory: • • • Instructions that perform two reads from data memory are not permitted. Instructions that access program memory are not permitted. 8. Instructions that perform one parallel move operation are allowed in this mode.6. It is only necessary to provide interrupt vectors and service routines for interrupts that will actually occur during data memory execution.Program Controller The code that is used to exit data-memory execution mode must contain the exact number of NOP instructions that is shown in Example 8-15 or Example 8-16 on page 8-27.3 Interrupts in Data-Memory Execution Mode Regular interrupt processing is supported in data-memory execution mode.

The processing states are: • • • • • • Normal—the normal instruction execution state.Chapter 9 Processing States The DSP56800E core has six processing states. Additional information on the normal processing state can be found in Section 10. Debug—a debugging state where the core is halted and the Enhanced On-Chip Emulation (Enhanced OnCE) module is enabled and used for debug activity. The states reflect the variety of operating modes that are available to a DSP56800E device. and it is always in one of these states. the core exits the processing state it was in previously and immediately enters the reset processing state. interrupts.2.6. Each of these processing states is considered in the following pages. These processing states are available when programs are executed normally from program memory and when instructions are fetched from data memory (see Section 8. which include low-power and debug capabilities. 9. Reset—the state where the core is forced into a known reset state. if debugging is not active. and selected peripherals are shut down. 9. “Normal Pipeline Operation.2 Reset Processing State The processor enters the reset processing state when a hardware reset signal is asserted.1 Normal Processing State The normal processing state is the typical state of the processor. Freescale Semiconductor Processing States 9-1 .” on page 10-3. Exception—the interrupt processing state. Stop—a low-power state where the core. The first program instruction is fetched upon exiting this state. When the reset terminal to the core is asserted.” on page 8-23). The core is held in reset during power up through the assertion of the RESET terminal. making this the first processing state entered by the DSC. Wait—a low-power state where the core is shut down but the peripherals and interrupts remain active. where it performs normal instruction execution. “Executing Programs from Data Memory. The core enters the normal processing state after reset. The reset processing state takes precedence over all other processing states. where the core transfers program control from its current location to an interrupt service routine using the interrupt vector table.

” 9. When an exception occurs. When the interrupt routine is terminated. Consult the appropriate device’s user’s manual for details. It is also possible for the core to enter the debug processing state upon exiting reset when system debug is underway. There are many sources for interrupts on the DSP56800E Family of chips. from the on-chip peripherals. The chip operating mode bits (MA and MB) in the OMR are loaded from external mode select pins. and some of these sources can generate more than one interrupt. Interrupts and exceptions can be generated by conditions inside the core. The following sections discuss the interrupt priority levels. Upon entering the interrupt service routine.3 Exception Processing State In the exception processing state.Processing States On devices with a computer operating properly (COP) timer. control is transferred from the currently executing program to an interrupt service routine. establishing the operating mode of the chip. the ways in which interrupts are processed.” Several types of exceptions are supported: interrupts. Interrupt requests can be generated from conditions within the core. An interrupt that is enabled can also be used to exit the DSC’s low-power wait processing state. which are caused by the execution of an instruction. — All bits in the operating mode register (except MA and MB) are cleared. See Section 9. the core exits the exception processing state and enters the normal processing state. on-chip peripherals or interrupt request pins. or from external pins. In digital signal processing. such as illegal instructions. Interrupts are also useful for system calls in an operating system and for servicing peripherals. The reset vector or vectors are specific to a particular DSP56800E–based device. or from external sources. which are generated by the core. and instruction level exceptions. The core begins instruction execution at the program memory address that is defined by the address of the reset vector that is provided to the core. The DSP56800E supports an unlimited number of exceptions. There may be different vector addresses for different reset sources. 2. the DSP56800E core recognizes and processes interrupts and exceptions. “Debug Processing State. The DSP56800E core features a prioritized interrupt vector scheme to provide faster interrupt servicing. such as an interrupt request signal. The DSP56800E core remains in the reset processing state until the cause for reset is de-asserted. 3. such as the RESET signal or the COP and RTI timer. it is also possible for the COP timer to assert the RESET signal if the timer reaches zero. The interrupt priority structure is discussed in Section 9. The internal registers are set to their reset state: — The modifier register (M01) is set to $FFFF. — The interrupt mask bits (I1 and I0) in the status register are both set to one. — The status register’s (SR) loop flag and condition code bits are cleared. some common uses of interrupts are to transfer data between the data memory and a peripheral device or to begin execution of a DSC algorithm upon the reception of a new sample. the interrupted program resumes execution. “Interrupt Priority Structure. Core interrupts and instruction level exceptions have a fixed priority level (there are software interrupt instructions for requesting an interrupt at each of the five priority levels). the following occurs: 1. When the reset trigger is deasserted.3. 9-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .1. forcing the core into the reset processing state. peripheral and debug port interrupts may be programmed to one of three priority levels or be disabled. The DSP56800E core enters the normal processing state upon exiting reset.6. and the various sources for interrupts and exceptions. the debug port.

such as peripherals and external interrupt requests. SWI #2 instruction. SWI #0 instruction On-chip peripherals. Table 9-1. Table 9-1 shows the different interrupt priority levels. It is also possible for a higher-priority exception to interrupt the interrupt handler of a lower-priority exception. 1. 3 IPL 0. 1. can only be generated by the SWILP instruction. Enhanced OnCE interrupts Illegal instruction. IRQA and IRQB. Enhanced OnCE interrupts. Priority levels 0–2 are used for programmable interrupt sources. Table 9-2 shows the CCPL values. including the SWILP.Exception Processing State 9. SWI instruction. If a reset occurs. Interrupt sources with a priority level that is lower than the CCPL are rejected. Reset conditions take precedence over all interrupt priorities. the chip immediately enters the reset processing state. 0 1 1 IPL 0 and SWILP 1 0 2 IPL 2. higher-priority exceptions take precedence. 2. misaligned data access Interrupt Sources 2 Maskable . The lowest priority level. IRQA and IRQB. are maskable. The CCPL is determined from the I1 and I0 bits in the status register. Current Core Interrupt Priority Levels I1 0 I0 0 CCPL 0 Exceptions Accepted IPL 0.1 Interrupt Priority Structure The DSP56800E architecture supports five interrupt priority levels. in ascending priority. 1. Interrupt sources with a priority level that is equal to or greater than the CCPL are accepted.3. The interrupt controller only accepts non-maskable interrupts (level 3). 1 and SWILP 1 1 3 IPL 3 IPL 0. hardware stack overflow. . Levels LP. 2 and SWILP Freescale Semiconductor Processing States 9-3 . The interrupt controller accepts all non-maskable interrupts and any unmasked interrupts that are programmed at level 1 or 2. Interrupt Priority Level Summary IPL LP 0 1 Description Maskable Maskable Maskable Priority Lowest . and 2. LP. The interrupt controller accepts all non-maskable interrupts and any unmasked interrupts that are programmed at level 2. SWI #1 instruction. Level 3 interrupts are generated by the core. IRQA and IRQB. Enhanced OnCE interrupts On-chip peripherals. SWILP instruction On-chip peripherals. 0. 3 and SWILP IPL 1. The current core interrupt priority level (CCPL) defines which interrupt priority levels will be accepted and which will be rejected by the core. 3 Non-maskable Highest When exceptions or interrupts occur simultaneously. Table 9-2. 2. Level 3 is the highest priority and is non-maskable. Non-maskable interrupts (level 3) are always accepted. 3 Exceptions Masked None Comments The interrupt controller accepts any unmasked interrupt.

Although the interrupt request is valid. 9.3. except for fast interrupts. which leave the priority level at level 3). Program flow has been transferred to the interrupt handler for the serial port.3. For some interrupt sources. 9-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Other interrupt sources. not program memory. A higher-priority interrupt (at level 2. Programmable interrupt sources other than those in the debug port can be set to one of the maskable priority levels (0.or 3-word JSR instruction.2. consider a simple example with nested interrupts. Now consider that a second peripheral. transferring control to the interrupt service routine. Program control is then transferred to the address specified by the vector provided. “Fast Interrupt Processing. the interrupt level is pre-assigned. 3. The CCPL was updated from level 0 to level 2. control is returned to the original program at the point at which it was interrupted. When the chip is in data-memory execution mode (see Section 8.2. the interrupting device provides a vector number to the core.” on page 8-23). Once the handling routine has completed processing the interrupt. because the CCPL will be restored to its original level (level 0). a timer with interrupt priority level 0. such as on-chip peripherals. and control is passed to an interrupt handling routine. Figure 9-1 on page 9-5 shows an example of the vector table. Enhanced OnCE interrupt sources can be programmed as level 1. The core has recognized this interrupt and entered the exception processing state. 1. support a programmable priority level. or 3 or as disabled. which does not update the CCPL. the interrupt vector table is located in data memory. A serial port on a chip has requested a level 1 interrupt when the core’s CCPL was at level 0. Assume that the following have already taken place: 1.2 Interrupt and Exception Processing When an interrupt or exception occurs. or 2) or be disabled. When an exception or interrupt is recognized and the CCPL is low enough to allow it to be processed. the CCPL is automatically updated to be one higher than the level of the interrupt (except for the case of SWILP. which is one level higher than the priority of the recognized interrupt (level 1). The location of the interrupt handling routine that is to be executed is determined with the interrupt vector table. such as the SWI instructions and non-maskable interrupts. and the interrupt vector is fetched appropriately from data memory when entering exception processing. If the interrupt request can be latched as pending. which are covered in Section 9. or the case of level 3 interrupts. At this address. and the level 1 routine would resume later after the level 2 handler completed. “Executing Programs from Data Memory. if desired). Each interrupt vector typically holds a 2.” When an interrupt occurs. the current program is stopped. Interrupt vectors are typically located in a block of memory locations in program memory (although interrupt vectors can be located anywhere in the program memory map. the interrupt will be serviced after the current interrupt service routine completes. The CCPL is set to level 3 on reset. generates an interrupt. the CCPL is set back to its original value.6.Processing States Every interrupt source has an associated priority level. for instance) would interrupt the level 1 service routine. To better understand the interrupt priority structure. When the interrupt service routine finishes. the interrupt will not be acknowledged and serviced because the peripheral’s priority level is lower than the core’s CCPL. the JSR instruction is fetched and executed. This updating prevents interrupts that have the same or a lower priority level from interrupting the handler for the current interrupt. 2. 2.

The case where the first instruction is not a JSR and the priority level is 0. the operation of the interrupted program may be affected. Handler Address Vector #23 Vector #22 JSR Handler Address JSR JSRs to Normal Interrupt Handler Routines . 5. 1. The CCPL is raised to be one higher than the level of the current interrupt. but it is only available for level 2 interrupts. Figure 9-1. 4. normal interrupt processing is used to handle an interrupt or exception. 2. otherwise. . The interrupt routine that is located at the target address of the JSR is then executed. and then it unfreezes the PC. Normal interrupt processing is supported for all types of interrupts. The JSR instruction is executed. the following occurs: 1. however. is automatically saved when an interrupt occurs.Exception Processing State Interrupt Vector Table . .2. If it is any other instruction and level 2. 3. so it does not need to be saved by the handler. The program counter is frozen. fast interrupt processing is used. The type of interrupt processing that will be performed is determined by the opcode that is located in the vector for a given interrupt and by the priority level of the interrupt source. Interrupt Vector Table Two types of interrupt processing routines are supported: normal and fast. .3. saving the original program counter and status register on the software stack. 9. or 3 is not permitted. The currently executing instruction is allowed to complete. Freescale Semiconductor Processing States 9-5 . When an interrupt occurs. normal interrupt processing occurs. If the instruction is a JSR. The status register. . Fast interrupt processing requires substantially less overhead. . Be careful in the interrupt handler routine to save any registers that will be used.1 Normal Interrupt Processing Under most circumstances. but it involves a certain amount of overhead. and all subsequent instructions are flushed from the pipeline. . . The program controller fetches the JSR instruction that is located at the vector for this interrupt.

fast interrupt processing resembles normal interrupt processing: the core performs steps 1–3 in Section 9. is performed when the instruction that is located in the appropriate slot in the vector table is not a JSR. the interrupt routine should be terminated by an RTI or RTID instruction.3.3. The following additional steps are performed: 1. The status register (with the exception of the P4–P0 bits) and the NL bit in the operating mode register are copied to the fast interrupt status register (FISR). “Nested Interrupts. which is available only for level 2 interrupts. the interrupt controller intercepts the normal vector table processing and inserts the absolute address into the core via the VAB bus. 9-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .2. These instructions return control to the interrupted program and restore the status register to its original value.3. The stack pointer (SP) is aligned for long-word accesses.2. Since the interrupt controller is external to the core. the 568xx family of chips has implemented a scheme whereas. 2. Please refer to the specific chip implementation for complete description of fast interrupt processing. 9. When the core recognizes that fast interrupt processing should be used—by determining that the interrupt is a level 2 interrupt and that the instruction in the vector is not a JSR—fast interrupt processing is initiated. In this implementation.3. chip implementations of this core can provide an alternate scheme in detecting fast interrupt processing. Fast interrupt processing has lower overhead than normal processing and should be used for all low-latency or time-critical interrupts.” for fast interrupt processing as well. Normal interrupts can be nested (refer to Section 10.2 Fast Interrupt Processing The default implementation of fast interrupt processing in the DSP56800E core. the IRQ selected for fast interrupt processing and the address of the code for the fast interrupts are coded in special chip registers.Processing States Interrupt Vector Table Main Program Interrupt Subroutine JSR Jump Address (LBL) n1 n2 ii2 ii3 ii4 Interrupt Routine PC Resumes Operatio n Explicit Return From Interrupt (RTI) iin RTI Figure 9-2. The description of fast interrupt throughout this manual follows the default implementation prescribed by the DSP56800E core. 3. “Normal Interrupt Processing.1. Control Flow in Normal Interrupt Processing When interrupt processing is complete. The frozen program counter (return address) is copied to the fast interrupt return address register (FIRA).” on page 10-11). Initially. For example.

If it is located in the vector table. can be interrupted by a higher-priority interrupt. N3. to avoid the overlap problem of a fast interrupt service routine with more than 2 words. RTI. Interrupt Vector Table Main Program Fast Interrupt Subroutine ii0 ii1 n1 n2 ii2 ii3 FRTID Explicit Return From Fast Interrupt (FRTID) di0 di1 PC Resumes Operation Figure 9-3. and the stack pointer is advanced to an empty 32-bit location. a delayed return from a fast interrupt. RTSD. Restores the SR and the NL bit in the OMR from the FISR register 5. It is more practical to have the interrupt vector for a fast interrupt handler to point to a location outside the main portion of the interrupt vector table. Pops the Y register off the stack and restores the stack pointer to its original value 4. This instruction performs the following: 1. and M01 on the DSP56800E core.Exception Processing State 4. rendering them unusable. 2. Swaps the shadowed registers back to their original values 2. The shadowed registers (R0. returning control to the interrupted program Note that fast interrupt handlers. 5. Sets the PC to the value in the FIRA register. Decrements the SP by two 3. The first instruction in the interrupt vector table is the first instruction of the level 2 interrupt service routine for its associated interrupt source. BSR. R1. RTID Freescale Semiconductor Processing States 9-7 . note that the code for the handling routine may overlap the locations of other vectors. and M01 on the DSP56800EX core) are swapped with their shadows. The code for a fast interrupt routine might be contained entirely in the interrupt vector table or might reside outside the table at a user-determined location. Control Flow in Fast Interrupt Processing A fast interrupt handling routine is terminated with the FRTID instruction. The following instructions are not allowed in the first four instructions of a fast interrupt service routine: – JSR. or all Rn. N. N. Execution of the fast interrupt handling routine then continues with the execution of the instruction in the interrupt’s vector. RTS. The Y register is pushed onto the stack. like interrupt handlers that are executed in normal interrupt processing mode. The execution of a fast interrupt service routine always conforms to the following rules: 1.

The first 5 instruction words in a fast interrupt service routine cannot contain an instruction that accesses program memory.3 Interrupt Sources Interrupt requests on a DSP56800E–based chip are generated by one of three sources: hardware sources outside the core (peripherals. a level 2 interrupt service routine typically occupies more than 2 program words in the interrupt vector table. and the size and location of the vector table. can be found in the user’s manual for the particular DSP56800E–based device. Fast interrupts are not nestable because fast interrupts are only available as level 2 interrupts—one level 2 interrupt cannot interrupt another level 2 interrupt. ALIGNSP – REP. The instructions for the level 2 interrupt service routine are located directly in the interrupt vector table unless a jump or branch transfers control out of the vector table. 5. 9. DOSLC 3. SWILP.Processing States – BRA. debug port exceptions).3. Bcc. Consult the user’s manual for the particular DSP56800E–based device. data access exceptions.3. interrupt request signals). To prevent one level 2 fast interrupt from interrupting another.3. JMP. 9. DO. 9. SWI #n. DEBUGHLT – DEBUGEV when programmed to halt the core – SWI. hardware sources within the core (illegal instructions. A fast interrupt handler can still be interrupted by a level 3 interrupt. As a result. 4. Exact information on possible interrupt sources. JMPD – STOP.3. Each interrupt source has at least one associated interrupt vector—the address to which program flow is transferred when an interrupt occurs. the status register’s I1 and I0 bits should not be explicitly changed during a fast interrupt service routine.1 External Hardware Interrupt Sources Interrupt and reset sources outside the core are unique to a chip’s particular configuration of peripherals and so on. The interrupt source provides the location of the appropriate vector to the interrupt control hardware. and software interrupt instructions.3. BRAD. Interrupt vectors are located in a block of memory called the interrupt vector table. WAIT.2 Hardware Interrupt Sources Within the Core The hardware interrupt sources within the core include the following: • • • • Illegal instruction interrupts Hardware stack overflow interrupts Misaligned data access interrupts Debugging (Enhanced OnCE) interrupts 9-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

no other instructions are executed between the illegal instruction and the first JSR instruction that is fetched from the interrupt vector table in the exception processing state.3. See Chapter 11.” for more information on the capabilities of the Enhanced OnCE module. It occurs when a 32-bit long-word value is accessed from data memory and the address that is used to access the data is misaligned. which provides integrated debugging support for the DSP56800E.3. See Section 3.” on page 3-19 for more information on the correct alignment for long-word values in memory. handling this interrupt can be used for diagnostic purposes—to locate the faulty code.2 Hardware Stack Overflow Interrupt The hardware stack overflow interrupt is a non-maskable level 3 interrupt source. might not generate an exception even though these opcodes are not supported and thus are considered illegal. Note that the illegal instruction exception is not necessarily generated for all invalid opcodes.3. It can be used to test the illegal instruction interrupt service routine.2. However. but that perform no useful work. 9. A long-word value must be accessed from memory using an even word address.1 Illegal Instruction Interrupt The illegal instruction interrupt is a non-maskable level 3 interrupt source. The illegal instruction interrupt is serviced immediately following the attempted execution of an undefined operation code—that is.2. the value must be accessed using an odd word address when it is accessed via the stack pointer register. This address can be used to locate the illegal instruction in memory. “Hardware Stack.2. “JTAG and Enhanced On-Chip Emulation (Enhanced OnCE). a misaligned data access interrupt is generated.4. In the latter case. Freescale Semiconductor Processing States 9-9 . is capable of generating interrupts. If the long word is not aligned in this manner. The Enhanced OnCE interrupts can be disabled or programmed to one of three different priority levels—level 1 through level 3. 9.3. It is generated when the DSP56800E core identifies an instruction as invalid.3.5. 9. The hardware stack overflow interrupt is non-recoverable and is used primarily for debugging. These interrupts provide the Enhanced OnCE module with the capability of executing instructions.3 Misaligned Data Access Interrupt The misaligned data access interrupt is a non-maskable level 3 interrupt source.3. The ILLEGAL instruction is a mnemonic for one of the invalid instruction opcodes.” on page 8-17). Opcodes with addressing modes that are not technically illegal.4 Debugging (Enhanced OnCE) Interrupts The Enhanced On-Chip Emulation module.3. The address of the instruction that immediately follows the illegal instruction is pushed on the stack when the illegal instruction exception handler is entered.3. Encountering the hardware stack overflow interrupt request means that more than two values have been stacked onto the hardware stack and that the oldest top-of-loop address has been lost (see Section 8.2. The hardware stack overflow refers only to the hardware stack and is not affected by the software stack operation. “Accessing Long-Word Values Using Word Pointers.3. except when SP is used in an indirect addressing mode. It is not possible to recover from an illegal instruction exception because critical state information is lost when an invalid instruction is executed.Exception Processing State 9.

When one of these sequences is executed. does not update the CCPL. As a result. SWI #1. SWI’s ability to mask out lower-level interrupts makes it very useful for setting breakpoints in monitor programs.3 Software Interrupt Instructions The DSP56800E instruction set contains instructions that trigger an interrupt. As a result. 9.3.Processing States 9. the SWILP instruction can schedule code for execution after all of the interrupt handlers have completed execution. the request is latched as pending by the interrupt controller and will be serviced only after the core’s CCPL is lowered to a level that is less than or equal to the priority of the instruction.3. In this case.3. interrupts are effectively disabled until after the last instruction in the sequence. The instruction can also be used for making a system call in a simple operating system. These instructions are commonly used for debugging purposes or operating system calls. Executing these instructions generates an interrupt request at the specified priority level.1 SWI Instruction—Level 3 The SWI instruction generates a non-maskable level 3 interrupt request. This instruction executes in 1 clock cycle.2 SWI #x Instructions—Levels 0–2 The SWI #0. where its low priority will not be recognized until all other interrupt handlers have completed execution. interrupts cannot occur between the instructions: • A delayed flow control instruction (such as JMPD) and the instructions in the delay slots 9-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . a minimum of 3 additional clock cycles are executed before the core forces three NOPs into the pipeline and executes the JSR located in the vector table. the interrupt is recognized by the core. Used in this manner. and SWI #2 instructions are maskable interrupt sources. the request is latched as pending by the interrupt controller and will be serviced only after the core’s CCPL is lowered to level 0. 9. These instructions execute in 1 clock cycle.3.3. This instruction is typically executed within other interrupt handlers. up to three instructions immediately after the SWILP instruction may be executed before the interrupt is serviced.3 SWILP Instruction—Lowest Priority The operation of the SWILP instruction is very similar to the operation of the maskable SWI instructions. If the SWILP instruction is executed when the CCPL is greater than level 0. However. This request is serviced immediately following the execution of the SWI instruction. the lowest-priority interrupt. any priority interrupt can be generated.3. If the SWI #x instruction is executed with a priority level that is lower than the CCPL. up to three instructions immediately after the SWI #x instruction may be executed before the interrupt is serviced.3.3. Note that the SWI #2 instruction can also be used for fast interrupt processing. no other instructions are ever executed between the SWI instruction and the first instruction of the interrupt handler. Depending on the instruction that is used. It is possible for a level 0 interrupt request to interrupt the handler for SWILP.3. there are certain sequences of instructions that are not interruptible.3. In the following sets of instructions. the interrupt is recognized by the core. If the CCPL is at level 0. Processing SWILP. Executing SWILP generates the lowest-priority interrupt request that is available. If the interrupt requested by the SWI #x instruction is at a priority level greater than or equal to the CCPL. A minimum of 3 additional clock cycles are executed before the core forces three NOPs into the pipeline and executes the first instruction located in the vector table. 9.3. interrupts can only occur between the execution of two instructions.4 Non-Interruptible Instruction Sequences In general. 9. and each typically has its own vector address.3.

Wait Processing State • • A REP instruction and the instruction that is to be repeated A 1-word Bcc instruction and either of the following: — A multi-word instruction — A 1-word instruction and the instruction that immediately follows it • • A multi-word Bcc and the instruction immediately after the Bcc BRSET or BRCLR and either of the following: — A multi-word instruction — A 1-word instruction and the instruction that immediately follows it • • • • • A Jcc instruction and the instruction that is executed immediately after the Jcc A Tcc instruction with an R0. (interrupt may occur before BRSET) Begins Non-Interruptible Sequence ===> No interrupt allowed before ASL ===> No interrupt allowed before DEC (interrupt allowed before MOVE) If the branch is not taken.R1 register transfer and the instruction that immediately follows it An ADD. Freescale Semiconductor Processing States 9-11 . Example 9-1. (interrupt allowed if branch taken) . .X0 LABEL ADD X0. by design. interrupts will be disabled until after the DEC.EEE instruction and the instruction that immediately follows it An SWI at the highest priority level and the instruction that immediately follows it (see following paragraph on SWI) Any of the last 3 program words in a hardware DO or DOSLC loop during the last iteration of the hardware loop Consider the code fragment in Example 9-1. . Thus. .W X:$3400 MOVE.X0. This mode is entered by executing the WAIT instruction. no interrupts can occur between the execution of the SWI instruction and the processor’s direct entry into the exception processing state. instead. If the branch is taken. Any interrupts that occur during the time that is taken to execute these three instructions will be deferred until the end of this sequence. as noted in the preceding list.W X:(SP-xx). but where clocks continue to run to the on-chip peripherals and to the interrupt controller.A . the instruction immediately after the SWI will not be executed. the processor directly enters the exception processing state. .4 Wait Processing State One of the DSP56800E core’s low-power-consumption states is wait mode.W Y0. The SWI instruction is designed so that upon execution. After a delay.W instruction is executed. interrupts can occur between the BRSET and ADD instructions. BRSET is an instruction that causes interrupts to be temporarily disabled. 9. BRSET Non-Interruptible Sequence NOP BRSET #34. the processor enters a state where the internal clock to the core is disabled and clocks to the memories are typically disabled.LABEL ASL A DEC. The SWI instruction is included in this list because of the nature of this instruction.

The RESET signal is asserted. This mode is entered by executing the STOP instruction. the following events can bring the core out of the stop processing state: • • • • An external pin is asserted. as defined by the I1 and I0 bits in the status register. 9-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .1 Wait Mode Timing The timing for entering and exiting the wait processing state is determined by the architecture of the particular DSP56800E–based device being used. Likewise. where it processes the recognized interrupt request. In a typical system architecture. Any of these actions will re-activate the oscillator. After a delay. The clock is also disabled to selected peripherals on the chip. and the WAIT instruction simply executes five NOPs. 9. the interrupt controller. If disabled. All peripheral and external interrupts are typically cleared on entering the stop state. and any on-chip memories are disabled. the internal core clock. An on-chip timer reaches zero.4.2 Disabling Wait Mode The DSP56800E core supports the permanent disabling of the wait processing state. clocks to the processor and peripherals will be re-enabled. Debug actions in the JTAG/Enhanced OnCE unit occur. wait mode can never be entered. Upon completing the NOP cycles. If an interrupt is used to wake the processor from stop mode.5 Stop Processing State The second of the DSP56800E core’s low-power-consumption states is stop mode. The priority levels of the peripherals remain as they were before the STOP instruction was executed. The interrupt must be enabled (unmasked) and must be at a higher priority level than the core’s current interrupt priority level.Processing States Wait mode is exited when an interrupt request is sent to the core. Upon exiting this mode. Consult that device’s user’s manual for exact wait mode timing information. The on-chip peripherals are held in their respective individual reset states. 9. 9. Wait mode is also exited when the chip is reset. program execution continues with the instruction that immediately follows the WAIT instruction. after a clock stabilization delay. and. but it may continue to run to the PLL block or to a timer block. the program continues execution in the exception processing state. the processor will enter the reset processing state if a reset signal was the cause for waking from stop mode. Consult the specific DSP56800E–based device’s user’s manual for more information on disabling wait mode.4. The clock stabilization delay period is determined by the stop delay (SD) bit in the operating mode register (OMR). or by certain debug actions in the JTAG/Enhanced OnCE unit. In this state the core consumes the lowest amount of power. the first code to be executed on leaving stop mode is either the interrupt handler for that request or the instruction immediately following the STOP instruction (see the user’s manual for a particular DSP56800E–based device for more details). Hardware stack overflows that were pending remain pending.

6 Debug Processing State The debug processing state is a state where the core is halted and placed under the control of the Enhanced OnCE debug port.Debug Processing State 9.2 Disabling Stop Mode The DSP56800E core supports the permanent disabling of the stop processing state. Freescale Semiconductor Processing States 9-13 . program execution continues with the instruction that immediately follows the STOP instruction. This is useful for applications where the core must not be halted. Upon completing the NOP cycles. Consult the specific DSP56800E device’s user’s manual for more information on disabling stop mode. It is also possible to use the debug port without entering the debug processing state. stop mode can never be entered. 9.5. Serial data is shifted in and out of this port.5. 9.1 Stop Mode Timing The timing for entering and exiting stop mode is determined by the architecture of the particular DSP56800E–based device being used. If disabled. and the STOP instruction simply executes five NOPs. and it is possible to execute instructions from this processing state. Consult the specific device’s user’s manual for more information on stop mode timing.

Processing States 9-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

resulting in higher execution throughput. The eight stages of the pipeline are shown in Figure 10-1. because certain code sequences can introduce pipeline dependencies. The eight stages overlap instruction fetches. and instruction execution. can affect overall performance if they are not addressed. Although it takes as many as 8 clock cycles to fill the pipeline and to complete the execution of the first instruction. and the resultant pipeline stalls. and to finish execution. including those circumstances that can result in pipeline dependencies. Although the execution pipeline is composed of many stages.Chapter 10 Instruction Pipeline The DSP56800E architecture is built around an eight-stage execution pipeline. Knowledge of the pipeline is useful. These dependencies. DSP56800E Eight-Stage Pipeline Instructions typically require 7 or 8 clock cycles to be fetched. however. to be decoded. its operation is largely hidden from the user. subsequent instructions typically complete execution on each clock cycle thereafter. depending on their complexity. AGU arithmetic instructions complete execution in the Address Generation stage. Pre-Fetch 1 (P1) Pre-Fetch 2 (P2) Instruction Fetch (IF) Instruction Decode (ID) Address Generation (AG) Operand Pre-Fetch 2 (OP2) Execute and Operand Fetch (EX) Execute 2 (EX2) Figure 10-1. Freescale Semiconductor Instruction Pipeline 10-1 . operand fetches. Most instructions will complete and be retired (their results written back and condition codes updated) by the end of the Execute stage of the pipeline. The following sections describe the pipeline in detail. Some more complex instructions require additional processing and are retired in the Execute 2 stage.

It is at this point in the pipeline that the instruction is identified. and their abbreviations. are as follows: 1. 8.L. Execute 2 (EX2)—Multiplications. Instruction Fetch (IF)—Program memory places the instruction opcode onto the program data bus (PDB).Instruction Pipeline 10. data memory places its value onto the primary and secondary data read buses (CDBR and XDB2). The execution of data ALU operations in the pipeline is discussed in more detail in Section 10. Operand Pre-Fetch 2 (OP2)—Data memory latches the data address and begins data memory access. 7. “Data ALU Execution Stages.” 10-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Data ALU calculations other than those that are listed previously are performed in the data ALU’s arithmetic unit and are stored in the destination data ALU register when they are executed using Late Execution. Instruction Decode (ID)—The instruction latch latches and decodes the opcode. and the multiplication result is stored in an intermediate pipeline latch. Address Generation (AG)—The address generation unit (AGU) drives data memory access addresses onto the primary and secondary data address buses (XAB1 and XAB2). For a memory write operation. Address and AGU calculations (including transfers done with the TFRA instruction) are performed in the AGU’s arithmetic units and are stored in the destination AGU register. ASRR.L. and LSRR. Execute and Operand Fetch (EX)—For a memory read.L take an additional cycle since they are 2-cycle instructions). and multi-bit shift instructions complete in this stage in the data ALU’s arithmetic unit. 5. All data ALU calculations other than those that are previously listed are performed in the data ALU’s arithmetic unit and are stored in the destination data ALU register.2. 3. such as memory accesses and calculations. and the various pipeline stages. Pre-Fetch 2 (P2)—Program memory latches the instruction address and begins program memory access. unless they are executed using Late Execution. Multiplications and MACs begin in this stage in the data ALU’s arithmetic unit. 2. 6. and the value or values are captured in the move’s destination registers.1 Pipeline Stages The eight stages of the pipeline. Table 10-1 on page 10-3 shows the relationship between fundamental operations. and the temporary result is stored in an intermediate pipeline latch. Pre-Fetch 1 (P1)—The address of the instruction that is to be fetched is driven onto the program address bus (PAB).2. and the final result is stored in the destination data ALU register (ASLL. 4. Multi-bit shifting instructions (arithmetic and logical) begin in this stage in the data ALU’s arithmetic unit. data that is to be written to data memory is placed onto the core data bus for writes (CDBW). MACs.

W instruction — NORM instruction — ALIGNSP instruction — REP instruction 10. P2. 10. The processor fetches only 1 instruction word per clock cycle. Mapping Fundamental Operations to Pipeline Stages Operation Instruction fetch Data memory access AGU calculation Data ALU calculation—Normal Data ALU calculation—Late Data ALU calculation—multiplication and shifts Pipeline Stages P1.2. the memory latches the address on the second cycle. if an instruction is more than 1 instruction word in length. IF AG. These include the following: • • • • • • Instructions longer than 1 instruction word Instructions using an addressing mode that requires more than 1 cycle for the address calculation Data ALU arithmetic instructions with one operand in memory Instructions causing a change of flow Instructions accessing program memory Special instructions: — Multi-bit shifting instructions that operate on 32-bit values — TSTDECA. it fetches each additional word with an additional cycle before fetching the next instruction.Normal Pipeline Operation Table 10-1. require more than 1 clock cycle to complete. This requirement applies when accessing both program and data memory. EX2 Note that memory accesses take place across three stages of the pipeline: an address is provided in the first cycle of an access. however. and the memory drives the corresponding data bus on the third cycle. EX AG EX EX2 EX. OP2. Freescale Semiconductor Instruction Pipeline 10-3 . allowing most instructions to be retired at a rate of one instruction per clock cycle.2 Normal Pipeline Operation Normal instruction execution occurs in an eight-stage pipeline. and when fetching both instructions and operands. Certain instructions.1 General Pipeline Operations Pipelining allows instruction executions to overlap so that the execution of one pipeline stage for a given instruction occurs concurrently with the execution of other pipeline stages for other instructions. Table 10-2 on page 10-4 demonstrates simultaneous execution through the pipelining of the five instructions that are found in Example 10-1 on page 10-4.

Two-Stage Execution—Multiplication. 2-word. . contains an instruction extension word (typically an absolute address or immediate value).C MOVE.2 Data ALU Execution Stages Data ALU instructions are executed in the last two stages of the pipeline. 1-word. and multi-bit shifting instructions that begin execution in the Execute phase and complete in the Execute 2 phase.X:$0C00 INC. . Then. All instructions are referred to by their n abbreviations before they reach the Instruction Decode stage of the pipeline. which is labeled n4e. Late Execution—Arithmetic and logical instructions that begin and complete execution in the Execute 2 phase. • 10-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . These instructions place the data ALU into Late mode. 10.W C1. MOVE instructions are notated as “mov. multiply-accumulate. .W B. as Table 10-2 demonstrates. As shown in Table 10-2. Multi-Cycle Execution—Data ALU instructions that execute in more than 1 clock cycle. that are executed in the pipeline.W C .Instruction Pipeline Example 10-1.W X:(R0). n4. 1-word. Data ALU instructions execute in one of four ways: • • • Normal Execution—Arithmetic and logical instructions that begin and complete execution in the Execute phase. Instruction Pipelining Instruction Cycle Pipeline Stage 1 P1 (Pre-Fetch 1) P2 (Pre-Fetch 2) IF (Instruction Fetch) ID (Instruction Decode) AG (Address Generation) OP2 (Operand Pre-Fetch 2) EX (Execute and Operand Fetch) EX2 (Execute 2) n1 2 n2 n1 3 n3 n2 n1 4 n4 n3 n2 mov1 5 n4e n4 n3 add mov 6 n5 n4e n4 mov add mov 7 • n5 n4e mov mov add mov 8 • • n5 mov mov mov add — 9 • • • inc mov mov mov — 10 • • • • inc mov mov — 11 • • • • • inc mov — • • • • • • • • — 1. the instructions are referred to by name (or by a shortened version thereof) to reflect that they have been identified. throughput remains high due to the pipelining. respectively.2.B MOVE. n1: n2: n3: n4: n5: 1-word.A ADD A. Table 10-2. Example Code to Demonstrate Pipeline Flow MOVE. 1-word. 1-cycle 1-cycle 1-cycle 2-cycle 1-cycle instruction instruction instruction instruction instruction The abbreviations n1 and n2 refer to the first and second instructions. it takes an additional clock cycle to fetch and process the extension word.In all of the pipeline tables in this chapter. The fourth instruction. . Execute and Execute 2.” It can be seen that although each instruction takes many clock cycles to complete execution.

When a multiplication or multi-bit shifting instruction is encountered. and multi-cycle data ALU instructions—except ASLL. Each of these instructions uses two pipeline stages and places the data ALU into the Late Execution state.L. LSRR. it is processed using Two-Stage Execution (still executing in a single cycle). such as n2. is executed immediately after a data ALU instruction is executed in the Late state. An instruction requiring condition codes.L.Normal Pipeline Operation Data ALU instructions such as ADD. They occur when: • When a data ALU dependency occurs. Example 10-2 on page 10-6 contains a code sequence demonstrating the behavior of the pipeline with a variety of different instructions. ASRR.L.W. IMPYUU MAC. and LSRR. The transitions between states are determined as follows: • • • Instructions that are not executed in the data ALU. There are three conditions where the data ALU can cause pipeline dependencies. The data ALU then remains in the Late state until a non–data ALU instruction is executed.L. MPYR MACSU. MPY. MPYSU ASLL. Two-stage instructions and the ASLL. or logic operation on the immediately following instruction.L. ASRR. LSRR.L instructions place the data ALU into the Late state. Freescale Semiconductor Instruction Pipeline 10-5 . complete before the final stage of the pipeline.W ASLL. The result of a data ALU instruction that is executed in the Late state is used in the immediately following two-stage instruction as the source register to a multiplication or multi-bit shifting operation. A dependency does not occur if the result is used in an accumulation. All other instructions keep the data ALU in its current state. and it places the data ALU into the Late Execution state. and LSRR.L. and NEG are typically executed by the data ALU using Normal Execution. ASRR. CMP. MACR. Note how instructions that are executed using Normal Execution.W IMACUS. arithmetic. such as Bcc. and n4.L. The complete list of two-stage instructions follows.W. IMPYSU. ASRR. TST.L ASRAC. IMPY.L—place the data ALU into the Normal state.L. LSRAC The result of a data ALU instruction that is executed in the Late state is used in the immediately following instruction as the source register in a move instruction. interlocking hardware on the core automatically stalls the core for 1 cycle to remove the dependency. n3. • • • • • • • • • IMAC. IMACUU. IMPY.

W (n4). n11: Two-Stage (Execute and Execute 2) . n1: n2: n3: n4: Non-data ALU (restores to Normal state) Normal Execution (Execute phase) Normal Execution (Execute phase) Normal Execution (no dependency) . Demonstrating the Data ALU Execution Stages NOP ADD X0. and n9) Pipeline stall because result of SUB (n9) is not available for write to memory (n10) until the end of cycle #17 Pipeline stall because result of ASRR.A ASL A MOVE. .W A. . .X:(R0)+ MPY X0.A MAC X0.X:(R0)+ ASRR.W (n11) is not available for conditional branching (n12) until cycle #20 10-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . n7: Two-Stage (Execute and Execute 2) n8: Two-Stage (Execute and Execute 2) n9: Late Execution (Execute 2 phase) n10: (dependency occurs--1 stall cycle) Non-data ALU (restores to Normal state) .A MOVE. . n12: (dependency occurs--1 stall cycle) . since the ASL is done in Execute Pipeline stall occurs because the result of MPY (n5) is not available for write to memory (n6) until the end of cycle #12 No pipeline effect between successive MAC and data ALU instructions (n7.W #3.Y0. Non-data ALU (restores to Normal state) . Non-data ALU (restores to Normal state) Table 10-3. n5: Two-Stage (Execute and Execute 2) .Y0. .A SUB Y1.A BNE LABEL .Instruction Pipeline Example 10-2.B MOVE.Y0. Execution of Data ALU Instructions in the Pipeline Pipeline Stage P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 n1 2 n2 n1 3 n3 n2 n1 4 n4 n3 n2 5 n5 n4 n3 6 n6 n5 n4 7 n7 n6 n5 8 n8 n7 n6 9 n9 n8 n7 — 10 — — — 11 12 13 14 • 15 — — — 16 • • n12 17 — — — — 18 • • • bcc — 19 • • • • bcc — 20 • • • • • bcc — asrr 21 • • • • • • bcc — n10 n11 n12 n9 n8 n10 n11 n12 n9 n10 n11 — nop add asl mov mpy — add — asl add — mov mac mac sub — mov asrr — mov mpy asl add — mov mac mac sub — mov asrr — — mov mpy asl — mov mac mac sub — mpy mov mac mac — — mov asrr — mov mpy — — mov asrr — — mac mac sub Several pipeline effects occur in the code in Example 10-2: • • • • • No pipeline effect between ASL (n3) and MOVE. n6: (dependency occurs--1 stall cycle) . .X:(R0)+ MAC X0. n8.W A.W B. .

Freescale Semiconductor Instruction Pipeline 10-7 . “Interrupt Latency. Note in this example that these 2 additional processing cycles are not real stages in the pipeline.3.3 Pipeline During Interrupt Processing The instruction pipeline functions slightly differently when processing interrupt requests.1 Standard Interrupt Processing Pipeline Figure 10-2 on page 10-8 shows the program flow and pipeline during standard interrupt processing. However. they are performed in the interrupt controller.” 10. On a typical chip implementation. This addition effectively makes the interrupt pipeline 10 levels deep. these cycles do affect the overall processing time for an interrupt. This assertion occurs during the Interrupt Request stage. refer to Section 10. the program interrupt controller asserts an interrupt request to the core. The two additional stages are as follows: • • Interrupt Arbitration (Int Arbitr) Interrupt Request (Int Req) The Interrupt Arbitration stage is required for arbitrating among all the different possible requesting sources. Beyond the standard eight-stage pipeline.3. For an exact calculation of interrupt latency. two extra stages are required. and they do not directly affect the operation of the pipeline. Rather. so they can be considered additional pipeline stages for the purpose of calculating interrupt latency.8. additional cycles are required for arbitrating and interrupting the core. If a valid interrupt is found at a high enough priority level after this arbitration is performed.Pipeline During Interrupt Processing 10.

Instruction Pipeline Interrupt Vector Table Main Program Interrupt Subroutine JSR Jump Address (LBL) n1 n2 ii2 ii3 ii4 Interrupt Routine PC Resumes Operation Explicit Return From Interrupt (RTI) iin RTI (a) Instruction Flow Interrupt Requests Sampled by the Arbiter Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 n2 n3 n4 n1 — — n1 — n1 ii1 ii1 ii0 — — — n1 ii1 ii1 ii1 jsr — — — n1 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — ii5 ii4 ii3 ii2 jsr jsr jsr — • ii5 ii4 ii3 ii2 jsr jsr — • • ii5 ii4 ii3 ii2 jsr — • • • rti ii4 ii3 ii2 — • • • rti rti ii4 ii3 ii2 • • • rti rti rti ii4 ii3 • • • rti rti rti rti ii4 • • • rti rti rti rti — n2 • • rti rti rti rti — • n2 • rti rti rti rti — • • n2 rti rti rti rti — • • • n2 rti rti rti — 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 i = Interrupt Arbitration and Request ii = Interrupt instruction word ii0 = First word of JSR instruction ii1 = Second word of JSR instruction ii5 = RTI instruction n = Normal instruction word (b) Interrupt Pipeline Figure 10-2. Standard Interrupt Processing 10-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

or “delay slots. When the core recognizes an interrupt request. Upon entering the interrupt service routine after executing the JSR instruction.” on page 4-12 for more information on the RTID instruction. “Delayed Flow Control Instructions. 10.Pipeline During Interrupt Processing When an interrupt request is asserted. Note the difference between Figure 10-3 and Figure 10-2 on page 10-8 from cycle #13 onward: the di0–di2 instructions are executed before control returns to instruction n2.” must always be filled. the interrupt controller takes 2 cycles to arbitrate between interrupts and to send an interrupt request to the core. See Section 4. and the CCPL has been updated to reflect the new priority level. and the JSR instruction is fetched from the interrupt vector table. which is saved on the stack by the JSR. During this time. the core returns to the normal processing state. even though instructions n2–n4 had already begun to be fetched. it takes several cycles to execute. When the interrupt handler completes (by executing the RTI instruction). Because the RTI instruction manipulates the software stack and causes execution flow to change. The interrupt processing pipeline when RTID is used is given in Figure 10-3 on page 10-10. then NOP instructions must be placed in the unfilled slots. To help reduce the overhead that is required in processing an interrupt. points to instruction n2.2 The RTID Instruction In the example interrupt processing pipeline that is presented in Figure 10-2 on page 10-8. most of the time that is needed to execute the (admittedly short) interrupt routine is taken up by the JSR and RTI instructions. the pipeline continues to function normally. These instruction words. Freescale Semiconductor Instruction Pipeline 10-9 .3. The return address. The RTID instruction performs the same function as RTI. If it is not possible to fill all of the delay slots with useful instructions. as in cycle #5 in Figure 10-2 on page 10-8. The PC was not updated to point past n2. but it reduces overhead by executing the instructions in the 3 subsequent program words before returning control to the interrupt program. an alternative to the RTI instruction is provided: the delayed return from interrupt (RTID). the transition to the exception processing state begins. control returns to the interrupted program. Any instructions in the pipeline that have not yet been decoded are replaced with NOPs.3. since the PC was frozen as soon as the interrupt was recognized.

Execution of the RTID Instruction 10-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Instruction Pipeline Interrupt Vector Table Main Program Interrupt Subroutine ii2 JSR Jump Address (LBL) n1 n2 ii3 PC Resumes Operation iin RTID di0 Explicit Return From Interrupt (RTID) di1 di2 Interrupt Routine (a) Instruction Flow Interrupt Requests Sampled by the Arbiter Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 n2 n3 n4 n1 — — n1 — n1 ii1 ii1 ii0 — — — n1 ii1 ii1 ii1 jsr — — — n1 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — ii5 ii4 ii3 ii2 jsr jsr jsr — di0 ii5 ii4 ii3 ii2 jsr jsr — di1 di0 ii5 ii4 ii3 ii2 jsr — di2 • • • • • • • • • n2 • • • n2 • • • n2 • • • 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 di1 di2 di0 di1 di2 rtid rtid rtid rtid rtid di0 di1 di2 n2 ii4 ii3 ii2 — rtid rtid rtid rtid rtid di0 di1 di2 ii4 rtid rtid rtid rtid rtid di0 di1 ii3 ii2 ii4 rtid rtid rtid rtid rtid di0 ii3 ii4 — — — — — i = Interrupt Arbitration and Request ii = Interrupt instruction word ii0 = First word of JSR instruction ii1 = Second word of JSR instruction ii5 = RTID instruction di = Instruction in RTID delay slot n = Normal instruction word (b) Interrupt Pipeline Figure 10-3.

Instead.3 Nested Interrupts Interrupts on the DSP56800E architecture can be nested. This re-enabling occurs at cycle #11 in Figure 10-4 on page 10-12. one exception can interrupt another exception’s interrupt service routine if it has a higher priority. This scenario is illustrated in Figure 10-4 as interrupt request i2a. the exception that is serviced will not be the original interrupt request. higher-priority interrupt request occurs after cycle #4. This condition is true only when the first interrupt request is at a lower priority level than the exception that is caused by the instruction at n1. and it is processed before the interrupt handler for request i1 resumes.3.4 SWI and Illegal Instructions During Interrupt Processing Another case of interest is where a first interrupt request begins the interrupt pipeline and the instruction at n1 in Figure 10-4 on page 10-12 is a non-maskable SWI instruction or an illegal instruction.Pipeline During Interrupt Processing 10. The SWI and illegal instructions execute in 4 clock cycles. The second interrupt request interrupts the processing of the first at cycle #13.3. it is not arbitrated until after interrupts are re-enabled in cycle #11. If the vector table contains a 3-word JSR instruction. the core can safely re-enable interrupts because the return address will be stacked properly before another interrupt can occur. interrupts are permitted between the JSR instruction and the first instruction in the interrupt service routine (ii2). Upon completion of these cycles. no interrupts are allowed between the JSR and the first instruction in the interrupt service routine (ii2). If a second. Once the JSR instruction reaches the point in the pipeline where it has begun execution. During initial interrupt processing. If the vector table contains a 2-word JSR instruction. Freescale Semiconductor Instruction Pipeline 10-11 . the core will service the SWI or illegal instruction exception that is caused by instruction n1. 10. Interrupts are disabled during cycles #4 through #10. interrupts are disabled.

Instruction Pipeline Interrupt Vector Table Interrupt Handler Interrupt Subroutine JSR 1st ISR — ii8 1st ISR — ii9 1st ISR — ii10 Jump Address (LBL) 2nd ISR — ii2 2nd ISR — ii3 2nd ISR — ii4 Interrupt Routine PC Resumes Operation Explicit Return From Interrupt (RTI or RTID) 2nd ISR — iin 2nd ISR — RTI (a) Instruction Flow First Interrupt Request Sampled by the Arbiter Interrupt Requests Again Sampled by the Arbiter Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i1 4 i2 i1 5 6 7 8 9 10 11 i2a 12 13 14 15 16 17 18 19 20 21 22 i2 ii1 ii1 ii0 — — — n1 ii1 ii1 ii1 jsr — — — n1 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — i2a ii5 ii4 ii3 ii2 jsr jsr jsr — ii0 ii5 ii4 — ii2 jsr jsr — ii1 ii0 ii5 — — ii2 jsr — ii1 ii1 ii0 — — — ii2 — ii1 ii1 ii1 jsr — — — ii2 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — ii5 ii4 ii3 ii2 jsr jsr jsr — ii6 ii5 ii4 ii3 ii2 jsr jsr — ii7 ii6 ii5 ii4 ii3 ii2 jsr — n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 n2 n3 n4 n1 — — n1 — n1 i = Interrupt Arbitration and Request ii = Interrupt instruction word ii0 = First word of JSR instruction ii1 = Second word of JSR instruction n = Normal instruction word (b) Interrupt Pipeline Figure 10-4. Interrupting an Interrupt Handler (Nested Interrupt) 10-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

3. ii0 refers to the first instruction word in the fast interrupt handler. Fast Interrupt Processing Freescale Semiconductor Instruction Pipeline 10-13 . and ii4 refers to the FRTID instruction.5 Fast Interrupt Processing Pipeline Figure 10-5 shows the program flow. and the corresponding pipeline. Interrupt Vector Table Main Program Fast Interrupt Subroutine ii0 ii1 n1 n2 ii2 ii3 FRTID Explicit Return From Fast Interrupt (FRTID) di0 di1 PC Resumes Operation (a) Instruction Flow Interrupt Requests Sampled by the Arbiter Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 ii2 ii3 ii4 ii5 n1 n2 n3 n4 ii0 ii1 ii2 ii3 ii4 n1 n2 n3 n4 ii0 ii1 ii2 ii3 n1 — — — ii0 ii1 ii2 n1 — — — ii0 ii1 n1 — — — ii0 n1 — — — n1 — — ii6 ii5 ii4 ii3 ii2 ii1 ii0 — ii7 ii6 di0 ii4 ii3 ii2 ii1 ii0 n2 ii7 di1 di0 frtid ii3 ii2 ii1 n3 n2 ii7 di1 di0 frtid ii3 ii2 • n3 n2 — di1 di0 frtid ii3 • • n3 n2 — di1 di0 frtid • • • n3 n2 — di1 di0 • • • • n3 n2 — di1 • • • • • n3 n2 — • • • • • • n3 n2 • • • • • • • n3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 i = Interrupt Arbitration and Request ii = Interrupt instruction word n = Normal instruction word (b) Interrupt Pipeline Figure 10-5.Pipeline During Interrupt Processing 10. The instructions ii5 and ii6 are the 2 instruction words filling the FRTID’s delay slots. during fast interrupt processing. Within the pipeline.

even if a level 3 interrupt is received.3.Instruction Pipeline 10. the first few instructions in a fast interrupt service routine cannot be interrupted. it is not sampled by the interrupt arbiter until instruction cycle #13 (as shown in the figure). Even if a level 3 interrupt is received prior to this point in the pipeline. Note that the instructions in the FRTID’s 2 delay slots cannot be interrupted. Figure 10-6 on page 10-15 shows the fast interrupt pipeline and the point at which interrupts are re-enabled and subsequent interrupts can be arbitrated. 10-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . However.6 Interrupting a Fast Interrupt Service Routine Fast interrupt service routines can be interrupted by a level 3 interrupt. so at least 7 clock cycles in the fast interrupt routine are executed without being interrupted.

Pipeline During Interrupt Processing Interrupt Vector Table Level 2 Interrupt Handler Level 3 Interrupt Subroutine ii4 ii5 ii6 ii7 ii8 FRTID dly0 dly1 JSR Jump Address ii2 ii3 ii4 Interrupt Routine PC Resumes Operation Explicit Return From Interrupt (RTI or RTID) iin RTI (a) Instruction Flow Level 2 Interrupt Request Sampled by the Arbiter Level 3 Interrupt Request Sampled by the Arbiter Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 ii2 ii3 ii4 ii5 n1 n2 n3 n4 ii0 ii1 ii2 ii3 ii4 n1 n2 n3 n4 ii0 ii1 ii2 ii3 n1 — — — ii0 ii1 ii2 n1 — — — ii0 ii1 n1 — — — ii0 n1 — — — n1 — — ii6 ii5 ii4 ii3 ii2 ii1 ii0 — ii7 ii6 ii5 ii4 ii3 ii2 ii1 ii0 ii8 ii7 ii6 ii5 ii4 ii3 ii2 ii1 4 5 6 7 8 9 10 11 12 13 i 14 15 16 17 18 19 20 21 i ii9 ii8 ii7 ii6 ii5 ii4 ii3 ii2 ii0 ii9 ii8 — ii6 ii5 ii4 ii3 ii1 ii0 ii9 — — ii6 ii5 ii4 ii2 ii1 ii0 — — — ii6 ii5 • ii2 ii1 ii0 — — — ii6 • • ii2 ii1 ii0 — — — • • • ii2 ii1 ii0 — — • • • • ii2 ii1 ii0 — i = Interrupt Arbitration and Request ii = Interrupt instruction word n = Normal instruction word (b) Interrupt Pipeline Figure 10-6. Interrupting a Fast Interrupt Routine Freescale Semiconductor Instruction Pipeline 10-15 .

fast interrupt service routine where the following occur: • • A fast interrupt request is received. Even if a level 3 priority interrupt is received. as the figure shows. In this case. Simultaneously with this request or a short time after it is received. the fast interrupt routine completes and control returns to the main program before the second interrupt request is serviced. exactly one instruction from the main program will be executed before the second interrupt is serviced. slightly different from the one shown in Figure 10-7. In Figure 10-7 on page 10-17. or 2. the interrupt will be successfully arbitrated in cycle #12 after the contents of the status register have been restored by the FRTID instruction in cycle #11. by this time. the FRTID instruction has restored the status register to its original value. the interrupt will be successfully arbitrated in cycle #11. it is not sampled by the interrupt arbiter until instruction cycle #11. The point at which interrupts are re-enabled after the exception processing state is exited is shown in the interrupt pipeline in Figure 10-7. This allows a minimum of 2 instruction cycles from the main program to be executed before the second interrupt is serviced.3. the second interrupt is level 0. three-instruction. Consider a second case. 10-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . in which the second interrupt is level 3. All interrupt priority levels are eligible already by cycle #11 because. This arrangement allows a minimum of 5 clock cycles in the fast interrupt routine to be executed without being interrupted. 1. In this case.7 FIRQ Followed by Another Interrupt Figure 10-7 on page 10-17 shows the fast interrupt pipeline for the case of a short. 3-word interrupt service routine. For this short. Additional cycles will be executed if n2 is more than 2 cycles or if n3 is a multi-cycle instruction.Instruction Pipeline 10. a second interrupt is received. Interrupt arbitration begins again in cycle #11.

Pipeline During Interrupt Processing Main Program FRTID dly0 dly1 Level 2 Fast Interrupt n1 n2 n3 n4 n5 n6 JSR Jump Address Level 0–2 General Interrupt (a) Instruction Flow—Fast Interrupt Routine Followed by Another Interrupt Level 2 Fast Interrupt Request Sampled by the Arbiter Second Interrupt Request Sampled by the Arbiter Pipe Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 ii2 n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 — — — n1 — — n1 — n1 n3 ii2 ii1 frtid — — — n1 n2 n3 ii2 dly0 frtid — — — n3 n2 n3 dly1 dly0 frtid — — n4 n3 n2 — dly1 dly0 frtid — 4 5 6 7 8 9 10 11 i 12 i i n5 n4 n3 n2 — dly1 13 14 15 16 17 18 19 20 i n6 n5 n4 n3 n2 — ii0 n6 n5 — n3 n2 — ii1 ii0 n6 — — n3 n2 — ii2 ii1 ii0 — — — n3 n2 • ii2 ii1 ii0 — — — n3 • • ii2 ii1 ii0 — — — • • • ii2 ii1 ii0 — — • • • • ii2 ii1 ii0 — dly0 dly1 frtid dly0 dly1 i = Interrupt Arbitration and Request ii = Interrupt Instruction Word n = Normal Instruction Word (b) Interrupt Pipeline—Servicing an Interrupt Immediately After a Fast Interrupt Routine Figure 10-7. Interrupting After Completing the Fastest Fast Interrupt Routine Freescale Semiconductor Instruction Pipeline 10-17 .

which is shown in the box in the ID stage of the pipeline. Since interrupts can only occur when instructions complete execution. the 2-cycle FRTID instruction (with 2 delay slots). If 3 cycles were executed before the FRTID instruction (a case that is not shown in the figure). Interrupt arbitration begins again in cycle #11. the pending level 3 interrupt must wait 1 cycle before continuing into the exception processing state. At this point. the level 3 interrupt is successfully arbitrated and exception processing begins. a second interrupt at level 3 is received. This wait is indicated by the jagged arrow in Figure 10-8 on page 10-19. However. 10-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Instruction Pipeline Figure 10-8 on page 10-19 shows the fast interrupt pipeline for the case of a fast interrupt service routine where the following occur: • • Two cycles are executed before the FRTID instruction. exception processing would be delayed 2 cycles instead of the 1 cycle shown in the figure. Simultaneously to this execution or a short time afterwards. is a non-interruptible sequence.

Interruption by Level 3 Interrupt During FRTID Execution Freescale Semiconductor Instruction Pipeline 10-19 .Pipeline During Interrupt Processing Main Program ii0 ii1 FRTID dly0 dly1 n1 n2 n3 n4 n5 n6 JSR Jump Address Level 2 Fast Interrupt Level 3 General Interrupt (a) Instruction Flow—Fast Interrupt Routine Followed by Another Interrupt Level 2 Fast Interrupt Request Sampled by the Arbiter Second Interrupt Request (Level 3) Sampled by the Arbiter Pipe Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 ii2 n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 — — — n1 — — n1 — n1 ii3 ii2 ii1 ii0 — — — n1 ii4 ii3 ii2 ii1 ii0 — — — ii5 II4 ii3 frtid ii1 ii0 — — n2 II5 II4 dly0 frtid ii1 ii0 — (Wait 1 Cycle) 4 5 6 7 8 9 10 11 i 12 13 14 15 16 17 18 19 20 i n3 n2 II5 dly1 ii0 n3 n2 — ii1 ii0 n3 — — ii2 ii1 ii0 — — — • ii2 ii1 — — — — • • ii2 ii0 — — — — • • • ii1 ii0 — — — • • • ii2 ii1 ii0 — — • • • • ii2 ii1 ii0 — dly0 dly1 frtid dly0 dly1 ii1 ii0 frtid dly0 dly1 ii1 frtid dly0 dly1 i = Interrupt Arbitration and Request ii = Interrupt Instruction Word n = Normal Instruction Word (b) Interrupt Pipeline—Servicing an Interrupt Immediately After a Fast Interrupt Routine Figure 10-8.

successful arbitration occurs in cycle #12 because the FRTID instruction must first restore the status register. The level 3 interrupt completes successful arbitration 1 cycle earlier. Consider another scenario that is not shown in Figure 10-9: If the instructions in the FRTID’s 2 delay slots execute in 3 clock cycles. arbitration begins 1 cycle earlier in cycle #11. the exception processing state is entered at the same time. If the second interrupt request is level 3. a second interrupt is received. Simultaneously with this request or a short time after it is received. then 1 instruction from the main program. The exception processing state. Since the second cycle of the FRTID instruction executes after the completion of the instructions in the delay slots. control does not return to the main program but instead immediately enters the second interrupt. can only be entered upon the completion of an instruction. however. 10-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . will be executed before the second interrupt is entered.Instruction Pipeline Figure 10-9 on page 10-21 shows the fast interrupt pipeline for the case of a short fast interrupt service routine where the following occur: • • A fast interrupt request is received. If the second interrupt is level 0. or 2. 1. the instructions in the FRTID’s are multi-cycle instructions such that the 2 delay slots execute in 4 cycles. regardless of the priority level of the second interrupt. In this case. For the fast interrupt service routine in this example. This is true anytime the instructions in the FRTID’s delay slots execute in 4 or more cycles. n2.

Pipeline During Interrupt Processing Main Program FRTID dly0 dly1 Level 2 Fast Interrupt n1 n2 n3 n4 n5 n6 JSR Jump Address Level 0–3 General Interrupt (a) Instruction Flow—Fast Interrupt Routine Followed by Another Interrupt Level 2 Fast Interrupt Request Sampled by the Arbiter Second Interrupt Request Sampled by the Arbiter Pipe Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 ii0 ii1 ii2 n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 — — — n1 — — n1 — n1 ii3 ii2 ii1 frtid — — — n1 n2 ii3 ii2 dly0 frtid — — — n3 n2 ii3 dly0 dly0 frtid — — n4 n3 n2 dly1 dly0 dly0 frtid — 4 5 6 7 8 9 10 11 i 12 i i n5 n4 n3 dly1 13 14 15 16 17 18 19 20 i n6 n5 n4 — ii0 n6 n5 — — ii1 ii0 n6 — — — ii2 ii1 ii0 — — — — • ii2 ii1 ii0 — — — — • • ii2 ii1 ii0 — — — • • • ii2 ii1 ii0 — — • • • • ii2 ii1 ii0 — dly1 dly1 dly0 dly1 dly1 dly0 dly0 dly1 dly1 frtid dly0 dly0 dly1 dly1 i = Interrupt Arbitration and Request ii = Interrupt Instruction Word n = Normal Instruction Word (b) Interrupt Pipeline—Servicing an Interrupt Immediately After a Fast Interrupt Routine Figure 10-9. Second Interrupt Case with 4 Cycles Executed in FRTID Delay Slots Freescale Semiconductor Instruction Pipeline 10-21 .

3. For purposes of calculation.1 Interrupt Latency Interrupt latency is calculated as follows: Latency = Execution time of instruction n1 + 4 clock cycles (1 for arbitration and 3 NOPs) + the number of clock cycles to execute the JSR (4 or 5 cycles) + wait states when the JSR instruction pushes the PC and SR to the stack + wait states due to program fetches of n3. “Non-Interruptible Instruction Sequences.” 10-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .3.4. See Figure 10-10. See Section 10. “Cases That Increase Interrupt Latency.3.3.” on page 9-10). Interrupt Latency Calculation 10. The interrupt can only take place on instruction boundaries (which are subject to the non-interruptible sequences that are described in Section 9. The length of execution of an instruction can affect interrupt latency.8 Interrupt Latency Interrupt latency is the time between when an interrupt request first appears and when the first instruction in an interrupt service routine is actually executed.Instruction Pipeline 10. Interrupt Request Sampled by the Arbiter First Instruction in Handler Reaches Instruction Decode Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 n1 n2 n3 n4 ii0 ii1 ii1 n1 n2 n3 n4 ii0 ii1 n1 n2 n3 n4 ii0 n1 — — — n1 — — n1 — n1 ii1 ii1 ii1 jsr — — — n1 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — • ii4 ii3 ii2 jsr jsr jsr jsr • • ii4 ii3 ii2 jsr jsr jsr • • • ii4 ii3 ii2 jsr jsr • • • • ii4 ii3 ii2 jsr • • • • • ii4 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ii3 ii4 ii2 ii3 ii4 Figure 10-10. This first instruction is defined as the instruction that is executed immediately after the JSR from the interrupt vector table. n4.8.3.8. interrupt latency is defined here as the time between when the interrupt controller first arbitrates among the interrupt sources and when the first instruction in an interrupt handler is latched into the instruction latch and is ready to be executed. and ii0–ii3 (or ii0–ii4 if the JSR instruction executes in 5 cycles) The largest execution time for instruction n1 is 8 clock cycles (when n1 is an RTI or RTS instruction).

regardless of the number of times that the second instruction is repeated. instruction fetches are re-initiated and pending interrupts can be serviced. these two instructions are treated as a single 2-word instruction.3. Interrupt Latency Calculation—Non-Interruptible Instructions The STOP instruction places the core into the stop processing state. The REP instruction and the instruction that it repeats are not interruptible. Section 9.3. “Non-Interruptible Instruction Sequences.4. During the execution of n2 in Figure 10-12. where interrupts are not recognized. and ii0–ii2 10. no interrupts will be serviced. Instead. An enabled interrupt brings the core out of this low-power state. are non-interruptible. Interrupt Requests Sampled by the Arbiter First Instruction Reaches Decode Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 i i n1 n2 n3 n4 n1 n2 n3 n1 n2 n5 n4 n3 n6 n5 n4 n7 n6 n5 n8 n7 n6 n3 n2 ii0 n8 n7 — n3 n2 ii1 ii0 n8 — — n3 n2 ii1 ii1 ii0 — — — n3 n2 ii1 ii1 ii1 jsr — — — n3 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — • ii4 ii3 ii2 jsr jsr jsr jsr • • ii4 ii3 ii2 jsr jsr jsr • • • ii4 ii3 ii2 jsr jsr • • • • ii4 ii3 ii2 jsr • • • • • ii4 ii3 ii2 • • • • • • ii4 ii3 • • • • • • • ii4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 bcc bcc bcc n2 bcc bcc bcc bcc bcc bcc bcc bcc bcc bcc bcc bcc Figure 10-11. and when the condition evaluates to false.2 Re-Enabling Interrupt Arbitration The time when interrupt arbitration is allowed to resume is calculated as follows: Re-enable = Execution time of instruction n1 + 4 clock cycles (1 for arbitration and 3 NOPs forced into pipeline) + 3 clock cycles (first 3 cycles executing the JSR instruction) + wait states when the JSR instruction pushes the PC and SR to the stack + wait states due to program fetches of n3. the two instructions immediately following the Bcc. n2 and n3.Pipeline During Interrupt Processing 10.3 Cases That Increase Interrupt Latency Some special cases increase interrupt latency.3.8. Such sequences increase latency. Instruction fetches are suspended and are re-activated only after the repeat loop is finished (see Figure 10-12 on page 10-24).8. Freescale Semiconductor Instruction Pipeline 10-23 . The WAIT instruction places the core into the wait processing state. Figure 10-11 demonstrates such a case. When the instruction n1 is a 1-word conditional branch instruction. When the loop finally completes. n4.” on page 9-10 documents instruction sequences that are not interruptible.

Instruction Pipeline Interrupt Synchronized and Recognized as Pending Main Program n2 n2 n1 (REP #4) n2 n3 Interrupts Re-Enabled n4 n5 n6 JSR Jump Address Process Interrupt: Fetch JSR Instruction from the Interrupt Vector Table Repeat 4 Times n2 n2 Instruction n2 Replaced per the REP Instruction (a) Instruction Flow Interrupt Requests Sampled by the Arbiter Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 i i% rep n2 rep n2 rep n2 rep rep rep n2 rep rep n2 n2 rep rep n2 n2 n2 rep rep n2 n2 n2 n2 rep — n2 n2 n2 n2 — — n2 n2 n2 i% i% i% i% i% i% i ii0 ii1 ii0 ii1 ii1 ii0 — — — n2 n2 ii1 ii1 ii1 jsr — — — n2 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — • ii3 ii2 jsr jsr jsr jsr — • • ii3 ii2 jsr jsr jsr jsr • • • ii3 ii2 jsr jsr jsr 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 i = Interrupt Arbitration and Request i% = Interrupt Request rejected by core and remains pending ii = Interrupt instruction word n = Normal instruction word (b) Interrupt Pipeline Figure 10-12. 10-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Interrupt Latency and the REP Instruction 10.3.4 Delay When Enabling Interrupts via CCPL Another case of interest is the time from the enabling of an interrupt by updating the CCPL in the status register until the time when the interrupt controller first arbitrates with the newly modified CCPL and an already pending interrupt is serviced.8.

The following notation is used in the figure: • • • n1 is a 1-cycle instruction that modifies the SR register. In this example. ii0 is the first word of the JSR instruction. and Pending Interrupt Is Serviced EE Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 2 3 4 5 6 7 8 i i n1 n2 n3 n4 n5 n6 p0 n1 n2 n3 n4 n5 p1 p0 n1 n2 n3 n4 p1 p0 n1 n2 n3 p1 p0 n1 n2 p1 p0 n1 p1 p0 p1 n7 n6 n5 n4 n3 n2 n1 p0 n8 n7 n6 n5 n4 n3 n2 — n9 n8 n7 n6 n5 n4 n3 n2 ii0 n9 n8 — n6 n5 n4 n3 ii1 ii0 n9 — — n6 n5 n4 ii1 ii1 ii0 — — — n6 n5 ii1 ii1 ii1 jsr — — — n6 ii2 ii1 ii1 jsr jsr — — — ii3 ii2 ii1 jsr jsr jsr — — ii4 ii3 ii2 jsr jsr jsr jsr — • ii4 ii3 ii2 jsr jsr jsr — • • ii4 ii3 ii2 jsr jsr — • • • ii4 ii3 ii2 jsr — • • • • ii4 ii3 ii2 — • • • • • ii4 ii3 ii2 9 10 11 12 13 14 15 16 17 18 19 20 21 Figure 10-13. the instruction is n6. the program interrupt controller arbitrates the already pending interrupts. Enabling Interrupts Arbitrates with NEW CCPL. and interrupt processing begins. The “remaining execution time of ‘Instruction at Int Req’” is the number of cycles from the time that the interrupt request reaches the Int Req stage for the pipeline to the time when this instruction completes the pipeline’s decode stage. In cycle #8. In Figure 10-13.Pipeline During Interrupt Processing This case is demonstrated in Figure 10-13. ii0 is the first word that is fetched from the interrupt vector table for the interrupt that is serviced. lowering the CCPL. The single-cycle instruction n1 in this example writes to the status register. The actual write to the CCPL occurs at the end of cycle #7 (the Execute 2 stage is not used by instruction n1). Freescale Semiconductor Instruction Pipeline 10-25 . An interrupt is now recognized as valid. but now with a lower CCPL. which modifies CCPL (the beginning of cycle #4 in Figure 10-13). Delay When Updating the CCPL The exact calculation of the time to recognize and process a pending interrupt after modifying the CCPL is measured from the decode of instruction n1. They can be a single multi-cycle instruction or two single-cycle instructions. p0 and p1 are the 2 instruction cycles that are executed immediately before instruction n1. Write to SR Changes the CCPL. the “Instruction at Int Req” is defined as the instruction in the Instruction Decode stage of the pipeline when the pending interrupt is at the Int Req stage of the pipeline. to the first decode cycle of the first instruction that is fetched from the vector table after a pending interrupt is recognized (beginning of cycle #13): Delay =Execution time of instruction n1 + 3 clock cycles for n1 to reach the end of the Execute phase + 1 clock cycle for arbitration with updated CCPL + remaining execution time of “Instruction at Int Req” (see following discussion) + 3 clock cycles for NOPs forced into pipeline + any pipeline core stalls due to data memory dependencies or wait states for p0 and p1 + wait states due to program fetches of n2 through n5 – 1 clock cycle if n1 is a 2-cycle instruction that writes an immediate to the SR In the preceding equation.

In the third case. There are three methods for handling pipeline dependencies: 1. the assembler generates an error. affecting the execution of a sequence of instructions. Example 10-3 and Table 10-4 on page 10-27 illustrate this type of dependency. there are certain instruction sequences that can cause the pipeline to stall.4 Pipeline Dependencies and Interlocks The pipeline is normally transparent to the user. 10. the remaining execution time is 2 cycles. 10. Most of these pipeline dependencies and resulting interlocks occur because the result of an operation occurring very deep in the pipeline is used by the immediately following instructions that are in earlier stages in the pipeline. the assembler issues a warning and inserts the appropriate number of NOP instructions between the dependent instructions. the “remaining execution time” is 1 cycle. If a 2-word. Data ALU dependencies fall into three different categories: • • • Interlocks due to two-stage data ALU execution Dependencies with OMR bits taking effect Dependencies on reading status bits in the SR In most cases. Instruction sequence restrictions—the instruction sequence is not allowed In the first case. and the pipeline automatically stalls for the required number of cycles. and the sequence must be re-coded. 10-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . rather. However. In some instances. the remaining execution time is 1 because there is only 1 remaining instruction cycle once the Int Req takes place. The preceding timing calculation also applies when pending interrupts are already waiting and interrupts are enabled by instruction n1. In the second case. the pipeline will automatically stall when one of these dependencies occurs.4. affecting program execution. such as the status register (SR). 2-cycle instruction is contained in n5 and n6. Hardware interlocking—the DSC automatically stalls the pipeline 1 or more cycles 2. dependencies are detected in hardware. the DSC does not stall the pipeline. If n6 is a 2-cycle instruction with its first decode cycle in cycle #9.1 Data ALU Pipeline Dependencies There are some cases within the data ALU unit where the nature of the pipeline can result in interlocks and stalls. Handling by development tools—the assembler automatically inserts NOP instructions 3. Dependencies and interlocks can also occur when there is contention for an internal resource. NOP instructions are automatically inserted between instructions by the assembler to correct the dependency.Instruction Pipeline In the example in Figure 10-13 on page 10-25. One common dependency occurs when results that are calculated in the Execute 2 stage of the pipeline are used as input operands in an immediately following two-stage instruction.

.D MPY D1. . . not multiplication. Note also that n7 completes in Execute 2.C AND. there are no pipeline dependencies. .Y0.A . . Data ALU Operand Dependency Pipeline Pipeline Stage Int Arbitr Int Req P1 P2 IF ID AG OP2 EX EX2 n1 n2 n3 n1 n2 n1 n4 n3 n2 n5 n4 n3 n6 n5 n4 n7 n6 n5 n8 n7 n6 n9 n8 n7 — — — — n10 n9 n8 • n10 n9 — — — — • • n10 • • • • • • • • • • • • mpy — asll • • • • • • mpy — • • • • • • • mpy • • • • • • • • • • • • • • • • Instruction Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 nop add sub mpy mac — mpy and — asll asla mpy — add sub mpy mac — mpy and — asll asla mpy — — asll — — asll — add sub mpy mac — mpy and — mpy — add sub mpy mac — — — mpy mac mpy and It should be noted that there are no pipeline effects when the data ALU executes instructions using Late Execution as long as the following instruction neither writes the results to memory nor depends on the condition codes that are generated. .W A.D MAC X0.C1.C ASLL. n1: Non-data ALU (restores to Normal state) n2: Normal Execution (Execute phase) n3: Normal Execution (Execute phase) n4: Two-Stage (Execute and Execute 2) n5: Two-Stage (Execute and Execute 2) n6: Two-Stage (Execute and Execute 2) n7: Late Execution (Execute 2 phase) n8: Two-Stage (Execute and Execute 2) n9: Non-data ALU (restores to Normal state) n10: Two-Stage (Execute and Execute 2) Operand dependencies occur in the example between n5 and n6 and between n7 and n8. Example 10-4. Note that no operand dependency exists with the D register between n4 and n5 because it is used only in accumulation. . .B MPY B1. Table 10-4. Data ALU Operand Dependencies NOP ADD X0.A SUB A.X0.W #3.A ASL A TFRA R2. . Case with No Data ALU Pipeline Dependencies MAC X0.Pipeline Dependencies and Interlocks Example 10-3. since the pipeline is forced Late by n6.X:(R0)+ ADD X0.W Y0. Instruction n9 removes a potential dependency by resetting the pipeline to the Normal state. As the associated pipeline in Table 10-5 on page 10-28 shows. . n1: n2: n3: n4: n5: n6: performed in Execute and Execute 2 Late Execution (Execute 2 phase) Late Execution (Execute 2 phase) Non-data ALU (restores to Normal state) (no dependency) Normal Execution (Execute phase) Freescale Semiconductor Instruction Pipeline 10-27 . .C . This situation is demonstrated in Example 10-4. . .C ASLA R0 MPY C1.A SUB Y1.Y0. . Note that n2 and n3 in this example complete in the Execute 2 stage because the pipeline is placed in the Late state by n1.R1 MOVE.D1.

The MOVE. Pipeline Dependency with AGU Registers MOVE.4. which would normally occur at cycle #6 for n2 in Table 10-6 on page 10-29. used in a TFRA instruction.R0 MOVE. interlocking hardware on the core automatically stalls the core for 2 cycles. Data ALU Pipeline with No Dependencies Instruction Cycle Pipeline Stage 1 P1 P2 IF ID AG OP2 EX EX2 mac 2 sub mac 3 asl sub mac 4 tfra asl sub mac 5 mov tfra asl sub mac 6 add mov tfra asl sub mac 7 • add mov tfra asl sub mac 8 • • add mov tfra asl — mac 9 • • • add mov — — sub 10 • • • • add mov — asl 11 • • • • • add mov — • • • • • • • add — • • • • • • • • — • • • • • • • • • 10. When these conditions occur.2 AGU Pipeline Dependencies Dependencies that are similar to those presented for the data ALU can occur with the address generation unit. or SP) is modified using a move or bit-manipulation instruction. Many pipeline dependencies are caused by the fact that addresses are issued early in the pipeline (AG stage). however.L instruction (n1). while registers are written deeper within the pipe (EX stage). n3: Use value in x0 just read from memory A pipeline interlock occurs between n1 and n2 because the address for the MOVE. updates the R0 register very deep in the pipeline—at cycle #7. The most frequently occurring dependencies take place when an AGU register (R0–R5. n2: Use same register as an address . n1: Write AGU pointer register . A dependency occurs if the same register is used within the next 2 immediately following instruction cycles and if it is: • • • • used as a pointer in an addressing mode. used as an offset in an addressing mode. N.L A10.X0 ADD X0. 10-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . used as an operand in an AGU calculation.W instruction (n2) is formed at the Address Generation stage of the pipeline. This AGU dependency is demonstrated in Example 10-5.B . a hardware interlock occurs and the DSC automatically stalls the pipeline 1 or 2 cycles. Because the R0 register is available for use in cycle #8.Instruction Pipeline Table 10-5. Example 10-5.W X:(R0). affecting the execution of a sequence of instructions.

n2: Use same register to access memory .w — — — 9 • • n5 n4 add mov. There are some special cases where there are no AGU dependencies.R1 ADDA R0. the DSC does not automatically stall the pipeline.W X:(R1)-. n7: Use same register to access memory Freescale Semiconductor Instruction Pipeline 10-29 .l 5 n5 n4 n3 — mov. and SP. n3: Write AGU pointer register with immediate .A MOVE.C . n1: Write AGU pointer register with immediate . n6: Copy one AGU pointer register to another .w — — 10 • • • n5 n4 add mov. there are no dependencies when a register is loaded with a TFRA instruction. Instead.R0 MOVE. n5: Use same register to access memory .l 8 • n5 n4 add mov. n4: Use same register in AGU calculation . the development tools automatically insert the appropriate number of NOP instructions to ensure that the program executes as intended.Pipeline Dependencies and Interlocks Table 10-6. AGU Write Dependency Pipeline Pipeline Stage P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 n1 2 n2 n1 3 n3 n2 n1 4 n4 n3 n2 mov. Example 10-6 and Table 10-7 on page 10-30 illustrate this case.l 7 — — — mov.l 6 — — — — — mov.W#$4.w — — mov. N.B TFRA R1.W X:(R2).w — 11 • • • • n5 n4 add — • • • • • • n5 n4 — • • • • • • • n5 n4 • • • • • • • • n5 If a dependency is caused by a modification of the N3 or M01 registers by a move or bit-manipulation instruction.W #3.W X:(R0).R1 MOVE. There is no dependency when immediate values are written to the address pointer registers—R0–R5. or if a bit-manipulation operation is performed on the N register. Example 10-6. Case Without AGU Pipeline Dependencies MOVEU. Similarly.R2 MOVE.

W N. within the same instruction. R5 stored with R5 post-update This type of dependency occurs whenever an address pointer register is used as the source in a store instruction. AGU Pipeline With No Dependencies Pipeline Stage P1 P2 IF ID AG OP2 EX EX2 Instruction Cycle 1 n1 2 n2 n1 3 n3 n2 n1 4 n4 n3 n2 movu 5 n5 n4 n3 mov movu 6 n6 n5 n4 mov mov movu 7 n7 n6 n5 add mov mov movu 8 • n7 n6 mov add mov mov — 9 • • n7 tfra mov add mov — 10 • • • mov tfra mov add — 11 • • • • mov tfra mov — • • • • • • mov tfra — • • • • • • • mov — • • • • • • • • — 10. N. The addressing mode is one of the three post-update addressing modes: — Post-increment — Post-decrement — Post-update by offset register The inserted stall cycles effectively make these instructions 3-cycle instructions. N stored with N post-update . the same pointer is being updated (modified) by an addressing mode.3 Instructions with Inherent Stalls There is an infrequently used class of move instructions that introduce stalls into the pipeline due to pipeline effects. Example 10-7 shows three instructions that fall into this category. MOVE Instructions That Introduce Stalls MOVE.X:(R5)+N . The assembler will issue a warning when any of these instructions are encountered.X:(R1)+ MOVE. The stalls are inserted so that the register is updated by the addressing mode after being used as the source register in the move instruction. There is no dependency if the register is used as a destination in the move instruction.Instruction Pipeline Table 10-7.X:(N)MOVE. R1 stored with R1 post-update .4. The source of the move is an AGU register (R0–R5. 10-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . or SP). Example 10-7.W R1.W R5. The pipeline automatically inserts 2 stall cycles when move instructions that satisfy all of the following characteristics are executed: • • • • The instruction is a move from a register to data memory. while. Example 10-8 on page 10-31 shows this case and other instances where there is no dependency. The AGU register that is used for the effective address is the same AGU register that is used as the source of the move instruction.

3. The solution to this problem is to insert instructions that require at least 2 cycles to execute between the load of LC and the DOSLC instruction.X0 ADD X0. and REP hardware looping mechanisms. In particular. a dependency occurs when the LC register is loaded prior to executing one of the hardware looping instructions. . the assembler will insert as many NOP instructions as necessary to ensure that the code executes correctly. Dependency with Load of LC and Start of Hardware Loop MOVEU.W X:(R3)+. R5 stored with no R5 post-update 10. .WX:(N)-. Example 10-9.X:(R1)+ MOVEU.B LABEL . N loaded with N post-update . Instructions with No Stalls MOVE.W R2. 2-word DOSLC loop n3 n4 In the code sequence in Example 10-9.W R5.LC DOSLC LABEL MOVE.N MOVE. . n1: Write to LC immediately followed by: n2: 3-cycle. none of the hardware looping instructions can be executed immediately after a value is placed in the LC register.WR0.1 Dependencies with Hardware Looping There are a few dependencies that occur when one is working with the DO.Pipeline Dependencies and Interlocks Example 10-8. Due to the architecture of the instruction pipeline. R2 stored with R1 post-update . DOSLC. the value that is loaded into LC in the first instruction is not available when it is needed by the DOSLC instruction: 2 more cycles are required before it is available in the right place in the pipeline. If instructions are not inserted to correct this problem.4. Freescale Semiconductor Instruction Pipeline 10-31 . Example 10-9 shows a code sequence that has such a dependency.X:(R5+N) .

Instruction Pipeline 10-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

as is required by a traditional emulator system. The DSP56800E Enhanced OnCE module is a Freescale-designed module that is used to develop and debug application software used with the chip. commonly called the JTAG port). Other features allow for hardware breakpoints. The Enhanced OnCE module permits full-speed. This module allows non-intrusive interaction with the DSC and is accessible either through the pins of the JTAG interface or by software program control of the DSP56800E core. the Enhanced On-Chip Emulation module (Enhanced OnCE) and the core test access port (TAP. The DSP56800E JTAG port is used to provide an interface for the Enhanced OnCE module to the DSC JTAG pins. Because their operation is dependent upon the architecture of a specific DSP56800E device. No user-accessible resources need to be sacrificed to perform debugging operations. the exact implementation is necessarily device dependent. memory. all in a special debug environment. Using these modules allows the user to insert the DSC chip into a target system while retaining debug control. Both are accessed through a common JTAG/Enhanced OnCE interface. This chapter presents an overview of the capabilities of the JTAG and Enhanced OnCE modules. This TAP controller is designed to be incorporated into a chip multi–JTAG TAP Linking Module (JTAG TLM) system. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-1 . The JTAG TLM is a dedicated. non-intrusive emulation on a user’s target system. test access port (TAP) system that is compatible with the IEEE Standard 1149. Two modules.1 Enhanced OnCE Module The Enhanced OnCE module provides emulation and debug capability directly on the chip. the monitoring and tracking of program execution. since it eliminates the need for a costly cable to bring out the footprint of the chip. This capability is especially important for devices without an external bus. and on-chip peripherals. IEEE Standard Test Access Port and Boundary-Scan Architecture. This section describes the Enhanced OnCE emulation environment for use in debugging real-time embedded applications.Chapter 11 JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) The DSP56800E Family includes extensive integrated support for application software development and real-time debugging.1a-1993. and the ability to examine and modify the contents of registers. user-accessible. eliminating the need for expensive and complicated stand-alone in-circuit emulators (ICEs). Among the many features of the Enhanced OnCE module is the support for data communication between the DSC chip and the host software development and debug systems in real-time program execution. 11. work together to provide these capabilities.

write. write.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) Because emulation capabilities are tied to the particular implementation of a DSP56800E–based device. 11. word. read. Although the Enhanced OnCE module is currently contained in the DSP56800E core. Additional debugging and emulation capabilities may be provided on particular DSP56800E-based devices. The Enhanced OnCE module can be viewed as a 11-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . 11. Consult the user’s manual for the particular device for more information. or long data type accesses Save or restore the current state of the chip’s pipeline Display the contents of the real-time instruction trace buffer Return to normal user mode from debug mode These capabilities will be explained in more detail in the following sections.1 Enhanced OnCE Module Capabilities The capabilities of the Enhanced OnCE module include the following: • • • • • • • • • • Examine or modify the contents of any core or memory-mapped peripheral register Examine and modify program or data memory Step at full speed on one or more instructions Save a programmable change-of-flow instruction capture to the trace buffer Display the contents of the real-time instruction trace buffer Allow the transfer of data between the core and external host in real-time program execution by using peripheral-mapped transmit and receive registers Access Enhanced OnCE registers and programming model by either the DSP56800E software or the debugging system through the JTAG port Provide status of Enhanced OnCE events in a status register or on an output pin from the core Count a variety of events including clock cycles and instructions executed Enter debug mode in any of the following ways: — microprocessor instruction — the actions of the Enhanced OnCE module — the core JTAG port — a special debug request input pin to the core • • • • • Interrupt or break into debug mode on program memory addresses (fetch.1. the user’s manual for the appropriate device should be consulted for complete details on implementation and supported functions. etc. It is this block that executes DSP56800E instructions. or read and write access) and for byte. they are conceptually shown separate in this picture for a simpler understanding of the debug port capabilities.2 Enhanced OnCE System Level View A system level view of the Enhanced OnCE module resources is shown in Figure 11-1. the DSP56800E core contains the core’s execution units. core register files. or read and write access) Interrupt or break into debug mode on accesses to data memory or on-chip peripheral registers (read. In this conceptual diagram.

and its own units: • Enhanced OnCE Control Unit. the EOnCE module operates in parallel with the DSP56800E core.Enhanced OnCE System Level View separate module which acts concurrently with the DSP56800E core. which contains: — Enhanced OnCE Control — Step Counter — Realtime Data Transfer Unit • • Breakpoint Unit Trace Buffer Program Memory Data Memory DSP56800E Core System Buses IP-Bus Bridge PIC EOnCE Control JTAG JTAG Pins Breakpoint Unit Trace Buffer IP-BUS Figure 11-1. This module contains its own programming model. DSP56800E On-Chip System with Debug Port After being properly initialized and programmed for breakpoint triggering and associated actions. simple Enhanced OnCE instructions. the Enhanced OnCE module can do the following: • • • • • • Receive new Enhanced OnCE commands Read / Write Enhanced OnCE registers through the JTAG interface (can also be accessed through the DSP56800E core’s system buses) Monitor DSP56800E buses for breakpoint conditions Capture DSP56800E program addresses when appropriate in the Trace Buffer Generate any of several different Enhanced OnCE interrupt requests Halt the DSP56800E core upon a certain debug event so it enters the Debug processing state If the DSP56800E core has been halted by entering the Debug processing state. As the DSP56800E core is executing instructions. the Enhanced OnCE module is still capable of receiving new commands as well as reading or writing any of the Enhanced OnCE registers. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-3 .

The JTAG port can also act as a completely independent module.1 External Interaction via JTAG Development and debugging systems can control Enhanced OnCE debugging actions by communicating with the Enhanced OnCE via the JTAG port. The two methods are discussed below.3 Accessing the Enhanced OnCE Module Resources in the Enhanced OnCE module can be accessed either through the JTAG port or under software program control from the DSC core. All of the Enhanced OnCE resources are available serially through the normal JTAG access protocol. it has no impact on the function of the core. and its external serial interface is used by the Enhanced OnCE module for sending and receiving debugging commands and data. The interface for both modules is handled by the JTAG port. transparently passing all communication between the Enhanced OnCE and the host development system. 11. and Trace Buffer) are actually located inside the DSP56800E core. A special JTAG instruction is executed to enable communication with the Enhanced OnCE module. The JTAG acts as an external interface controller for the Enhanced OnCE. the DSP56800E JTAG and Enhanced OnCE modules are tightly coupled. Figure 11-2 shows a block diagram of the JTAG/Enhanced OnCE modules and the JTAG terminals used in the external interface. the JTAG module transparently transfers all data that is received on the JTAG port to the Enhanced OnCE module. The figure is only conceptual and was drawn this way to better demonstrate how these individual blocks are used in a DSP56800E system. When it is disabled. which communicates with the host software development and debug systems. These two methods allow debugging activity to be controlled either by a host development system or by a program that is executing on the DSP56800E device. When interacting via JTAG. 11. While Enhanced OnCE communication is active. The JTAG port enables interaction with the debug capabilities provided by the Enhanced OnCE.3.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) NOTE: The Enhanced OnCE blocks shown in Figure 11-1 (EOnCE Control. Breakpoint Unit. 11-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

2 Core Access to the Enhanced OnCE Module The core can also access the Enhanced OnCE module directly executing DSP56800E instructions which access the Enhanced OnCE module as memory mapped registers. Access to the Enhanced OnCE module from the DSC core is enabled through a set of memory-mapped registers. and monitor its actions under program control. When accessed in this manner. there is no need to access the port via JTAG. Core access provides the ability to initialize the Enhanced OnCE module. This technique operates independent of the JTAG port.Accessing the Enhanced OnCE Module Enhanced OnCE JTAG Enhanced OnCE Command Status & Control Enhanced OnCE Instruction Queue CORE_TDI CORE_TDO TMS TCK TLM_RES_B CORETAP_EN CORE_TLM_SEL Test Access Port Controller PAB Step Logic Step Counter TX/RX Logic Transmit Register Receive Register Trace Buffer (Eight stages) PAB XAB1 Breakpoint Logic PAB Event Counter CDBR / CDBW Figure 11-2. allowing access to the port via normal instruction execution. JTAG/Enhanced OnCE Interface Block Diagram 11. It also allows data to be uploaded or downloaded between the core and each of the four Enhanced OnCE submodules. Both polled and interrupt driven communication between the core and the Enhanced OnCE module is supported where appropriate. All of the Enhanced OnCE resources are available through the memory mapped registers.3. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-5 . use its resources.

1 Using the Debug Processing State The Debug processing state is a state where the core is halted. similar to the generation of a breakpoint trigger. where state information can be easily read and modified.4 Enhanced OnCE and the Processing States The DSP56800E core supports six different processing states (see Table 11-1). A low power state where the core is shut down but the peripherals and the interrupt machine remain active. Table 11-1. breakpoints and other resources can be initialized and setup for debugging. and on-chip registers and memory locations can be examined and modified. A low power state where the core. 11. and most (if not all) of the peripherals are shut down. The state of interrupt processing.4. It is also possible for the core to enter the Debug processing state immediately upon exiting reset to setup a debug session before the core begins executing instructions. Any of the following can place the core in the Debug processing state: • • Hardware reset with JTAG DEBUG_REQUEST in the JTAG Instruction Register (IR) JTAG DEBUG_REQUEST placed in the JTAG IR during — STOP mode — WAIT mode — wait states • Pulling the core debug_req_b pin low for three peripheral clock cycles 11-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Processing States State Normal Reset Exception Wait Stop Debug Description The state of the core where instructions are normally executed. where the core transfers program control from its current location to an interrupt service routine using the interrupt vector table.3 Other Supported Interactions The DSP56800E supports two instructions. This prevents accidental access to the Enhanced OnCE resources. The DEBUGEV instruction causes a debugging event to be generated. DEBUGEV and DEBUGHLT.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) An unlocking sequence must first be executed by the core to gain access to the Enhanced OnCE module. The state where the core is halted and all registers in the Enhanced On-Chip Emulation (EOnCE) port of the processor are accessible for program debug.3. The first program instruction is fetched upon exiting this state. 11. The chip is often placed in the Debug processing state to initialize the Enhanced OnCE module for a debug system. placing it in the Debug processing state. the interrupt machine. The DEBUGHLT instruction is used to halt the core. 11. The state where the core is forced into a known reset state. Core access to the Enhanced OnCE module can optionally be disabled via the JTAG port to prevent programs from affecting the Enhanced OnCE module’s operation. that will trigger actions in the Enhanced OnCE module when executed by the DSP56800E core.

The core JTAG TAP will bring the core out of Stop or Wait modes when DEBUG_REQUEST is decoded in the TAP IR. all core clocks are disabled and it is not possible to access the Enhanced OnCE module. Instead. The Enhanced OnCE module also has the capability to generate interrupt requests in response to difference debug events. The JTAG interface provides the means of polling the device status (sampled in the capture-IR state). the event is serviced by executing a dedicated interrupt service routine. The Enhanced OnCE exception trap is available to the user so that when a debug event is detected. an interrupt can be generated and the program can initiate the appropriate handler routine. A small amount of additional power above the minimum possible will be expended by the core TAP logic if the core TAP is utilized during Stop mode.4. typically executed in the Normal processing state. In this state. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-7 . This allows the core to perform many different actions in response to Debug events without halting the core.2 Debugging and the Other Processing States It is not necessary. to place the core in the Debug processing state to initialize the module. An alternative technique is to first setup the desired Enhanced OnCE resources and then to enable these resources. This can either be done through the JTAG port or through Core access via setup routines located in an application. however. each with its own dedicated interrupt vectors in the DSP56800E interrupt vector table. NOTE: Care must be taken when the core is in the Stop processing states.Enhanced OnCE and the Processing States • • • • Execution of the DEBUGHLT instruction while the EOnCE is powered up Step Counter expires while configured for debug request Trace Buffer is full and configured for debug request Breakpoint Unit Triggers occurs when programed for debug request 11.

control.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11. DSP56800E software can directly program. Alternatively. although it operates independently. and communicate with the Enhanced OnCE module. This enables emulation and debug processing to occur independently of the main DSP56800E processor core instructions in a non-intrusive fashion.4. The operations of the Enhanced OnCE module can occur independently of the main DSP56800E core logic. and control portion of the Enhanced OnCE module handles the processing of emulation and debugging commands from a host development system. each of which performs a different task: • • • • • Command. and Control The command. these submodules provide a full-featured emulation and debug environment. The Enhanced OnCE module can also enable the core to enter debug mode. status.3 Enhanced OnCE Module Architecture The Enhanced OnCE module is composed of several submodules.4.3. Additional bits are provided to report the condition of the Trace Buffer. requiring no core resources. which is responsible for coordinating all emulation and debugging activity. status. 11.1 Command. 11-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . instruction execution Breakpoint unit Step counter Change-of-flow trace buffer Enhanced OnCE transmit and receive registers Together. control. Communication with the external host system are provided by the JTAG port module and passed transparently through to this logic. Status. External communication with the Enhanced OnCE module is handled via the JTAG port. Status bits can be examined to determine which source caused the processor was halted.

4. control trace buffer or counter operation. the breakpoint unit can generate an interrupt.2. The DSP56800E Enhanced OnCE breakpoint unit includes two trigger modules. reads.2 Breakpoint Unit Traditionally. 11. In response to a breakpoint trigger.3. breakpoints can never be set on data memory locations. since these registers are implemented as data-memory-mapped registers. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-9 .3. It can also be programmed for data memory reads.” on page 11-13. Triggering is also possible for on-chip peripheral register accesses.4. the occurrence of a particular number of events.4. or halt the core. The DSP56800E Enhanced OnCE breakpoint unit provides a breakpoint unit with hardware trigger generation blocks containing address comparators for setting breakpoints on program or data memory accesses.1 Trigger Blocks The first trigger block.Enhanced OnCE and the Processing States 11. shown in Figure 11-4.4. Figure 11-3 is a diagram of the breakpoint unit. This technique is limiting in that breakpoints can only be set in RAM at the beginning of an opcode and not on an operand. writes. processors have set a breakpoint in program memory by replacing the instruction at the breakpoint address with an illegal instruction that causes a breakpoint exception. Breakpoint Unit Block Diagram The Breakpoint Unit capabilities will be demonstrated in detail in Section 11. or a combination of these conditions. “Effectively Using the Debug Port. XAB1 [0:PAB] [0:PAB] CDBR/CDBW Read/Write Fetch Trigger 1 Trigger 2 32-bit Mask DEBUGEV instruction Overflow or saturation Combining Logic 16-Bit Counter Select Action Output Action Breakpoint Interrupt Start Trace Buffer Halt Trace Buffer Figure 11-3. In addition. These conditions include accessing a particular memory location or value. and combining logic to trigger breakpoints from a substantially wider variety of conditions than traditional processors. writes or memory accesses. a 16-bit counter. Breakpoints can be set on program ROM as well as program RAM locations. can be programmed for program fetches. or accesses.

the counter can instead independently count clock cycles or instructions executed between two points of interest. writes. Trigger 1 Logic The second trigger block. Trigger 2 Logic 11. can be programmed for program fetches. or data memory reads. shown in Figure 11-5. In capture mode. In capture mode. In triggering mode.2. the counter is used to count occurrences of a desired trigger condition. It is also possible to mask bits in the second trigger block to only examine desired bit fields.4. CDRB/CDBW PAB Read/Write Fetch Memory Address Multiplexer 24 Breakpoint 2 Address Register 24 JTAG Core Peripheral Bus Comparator Breakpoint 2 Mask Register JTAG Core Peripheral Bus Mask Optional Inverter Match 2 Figure 11-5.3. the breakpoint counter can also be cascaded with the step counter to create a 40-bit counter for longer time measurements.2 16-bit Counter The breakpoint unit contains a 16-bit counter which can be programmed to act in one of two different modes. or 32-bit data. 16. or accesses on 8. 11-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) XAB1 PAB Read/Write Fetch Memory Address Multiplexer 24 Breakpoint 1 Address Register 24 JTAG Core Peripheral Bus Comparator Match 1 Figure 11-4.

3.” on page 11-13.2. BRSET. 11.3 Combining Logic The breakpoint unit combining logic supports combinations of breakpoints.4 Change-of-Flow Trace Buffer To ease debugging activity and to help keep track of program flow. forward or backward—captures the target addresses for the Bcc. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-11 . To complete the execution history. Interrupt—Buffer capture is stopped and an interrupt occurs. “Effectively Using the Debug Port. The pointer is then decremented while reading the eight buffer locations to obtain a sequential trace of these instructions back in time.5 Realtime Data Transfer Unit The Realtime Data Transfer Unit enables the user to transmit data from the DSP56800E processor core to the external host through the JTAG port. A 24-bit instruction step counter provides for up to 16. This buffer is capable of capturing any combination of the following execution flow events: • • • Interrupts—captures the address of the interrupt vector and the target address of returns Subroutines—captures the target address of JSR and BSR instructions Conditional branches. 11.3. This counter can be used very effectively in combination with the Breakpoint Unit capabilities for more complex debugging scenarios.4. Once the eight-position buffer is filled. This capability allows the user to single step through a program or to execute whole functions at a time.4.3 Step Counter This submodule also provides the capability for full-speed instruction stepping. This allows for the execution of OR and AND operations as well as the sequencing of more than one breakpoint.3.4. and enables the core to receive data from the external host.4. a circular pointer is used to indicate the location of the buffer that holds the address of the most recent change-of-flow instruction.4. Starting and stopping capture into the buffer is programmable.3.777. Enter debug—Buffer capture is stopped and core enters debug mode. a read-only buffer is provided that tracks the change-of-program-flow execution history of an application. there are several programmable options for what action the Enhanced OnCE module takes: • • • • No action—Buffer continues to capture change of flows. Halt buffer—Buffer capture is stopped.216 instructions to be executed at full speed before the processor core is interrupted (or halted) and enters the Debug processing state. so it is possible for the user to reconstruct the program execution flow extending back quite a number of instructions. The trace buffer is intended to provide a snapshot of the recent execution history of the DSP56800E processor core. in real-time program execution. and BRCLR instructions Sequential program flow can be assumed to have occurred between the recorded instructions. so capture only occurs when it is needed. This will be demonstrated in detail in Section 11.4. 11. whether taken or not.Enhanced OnCE and the Processing States 11. The Enhanced OnCE module provides flexible control over the trace buffer. It can store the address of the most recent change-of-flow instruction as well as the addresses of the previous seven change-of-flow instructions. Jcc.

interrupts can be enabled separately for the transmit and receive portions. signalling to the core that the Realtime Data Transfer Unit should be serviced. Status bits indicate when the transmit or the receive portion need servicing. The core writes to the transmit register and reads the receive register in parallel via the DSP56800E instruction set.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 32 1 Serial Input 32-bit RX Data Shifter 1 Serial Output 32-bit TX Data Shifter 32 TXRX Status Register TX Data Interrupt RX Data Interrupt Core Data Buses Figure 11-6. and the host writes to the receive register and reads the transmit register serially through the JTAG interface. 11-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Realtime Data Transfer Unit The 32-bit transmit and receive registers are memory mapped in the core’s data memory. Similarly. Communication between these registers and the core can be either polled or interrupt driven.

Step Counter — Started upon Exiting Debug State with Breakpoint Active 11. This is the configuration used.4. the Breakpoint Unit can now generate a Breakpoint Unit Trigger for halting the core upon this trigger and entering the Debug processing state.1 Usage upon Exiting the Debug Processing State In its simplest usage. the Step Counter can be used for full speed execution of a programmable number of clock cycles before performing an action. This section demonstrates how to best program the above modules and what triggering is available. “Capture Counter. it can be used to create a 40-bit Capture Counter as shown in Section 11. Step Counter — Started upon Exiting Debug State In another simple usage. when single stepping.4.4.4. In this case. 11.4.1.4.Enhanced OnCE and the Processing States 11.4. for example.1.2 Step Counter Actions Table 11-7 lists the possible actions when using the Step Counter.3.4. If not needed for either of these.1 Using the Step Counter The 24-bit step counter can be used in the two manners presented below. 11.” on page 11-20. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-13 .4 Effectively Using the Debug Port Different features in the above blocks of the Enhanced OnCE module can be used together and programmed in different manners for handling complex as well as simpler debugging problems. 24-Bit Step Counter Select Action Exit Debug State Breakpoint Unit Trigger Halt Core Figure 11-8. the Step Counter can be used for full speed execution of a programmable number of clock cycles before performing an action. Exit Debug State 24-Bit Step Counter Select Action Halt Trace Buffer Halt Core Figure 11-7.4. It also shows what actions are allowed once a particular debug event or set of events has occurred. the Breakpoint Unit still generate a Breakpoint Unit Trigger for everything except halting the core and entering the Debug processing state. In this case.

” on page 11-19.4.” on page 11-23. Table 11-2.2. “Combining the Breakpoint Unit with the Step Counter. Step Counter reaches zero OR Breakpoint Unit Trigger arrives Enter Debug state Case SC-3 11.4. These four different inputs are then combined in the Combining Logic to get the final Breakpoint Unit Trigger.4. There are also inputs for DEBUGEV instruction execution as well as an overflow condition within the core.4.4.3. 11-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The breakpoint triggering capabilities can be examined using the block diagram in Figure 11-9.3.3. Triggers for the Capture Counter will be covered in Section 11.4. This unit is capable of generating two triggers. “Capture Counter.4.1. which can then be used to perform one of several different actions or can also be passed to a different block such as the step counter.3. can also be configured to work with the Breakpoint Unit. as well as the Capture Counter as discussed in Section 11.2 Using the Breakpoint Unit The Breakpoint Unit is used to generate trigger(s) for any one of the following: • • • Traditional breakpointing Start and/or Stop triggers for Trace Buffer Capture Start and/or Stop triggers for measuring cycles executed in the Capture Counter This section covers the first two uses.3 Other Step Counter Configurations The Step Counter. Step Counter Operation Start Step Counter Case SC-1 Case SC-2 Exit Debug State Trigger for Step Counter Action Step Counter reaches zero Action Performed Enter Debug state Halt Trace Buffer Capture when Step Counter reaches zero.4.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11.” on page 11-20. covered in Section 11. “Using the Capture Counter with the Step Counter.4.4.

Enhanced OnCE and the Processing States XAB1 [0:PAB] [0:PAB] CDBR/CDBW Read/Write Fetch Trigger 1 Trigger 2 32-bit Mask DEBUGEV instruction Overflow or saturation Combining Logic 16-Bit Counter Select Action Output Action Breakpoint Interrupt Start Trace Buffer Halt Trace Buffer Figure 11-9. Breakpoint Unit Block Diagram Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-15 .

The occurrence of either asserts the trigger. where N is the programmed 16-bit counter value. the trigger is asserted. or 32-bit match on a data value on the CDB bus.4.4. On Nth occurrence of a match. Trigger 2 configured to look for an 8-bit. or access. Trigger 2 configured to look for match on the PAB bus. data read. the trigger is asserted. On 1st occurrence of a match. The trigger is asserted when “expr1” occurs OR when “expr2” occurs. followed by “expr2”. On Nth occurrence of a match. Trigger 2 configured to look for match on the PAB bus. the trigger is asserted. where N is the programmed 16-bit counter value.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11. The trigger is asserted on the Nth occurrence of detecting the expression. On Nth occurrence of a match.2. the trigger is asserted. write. Trigger 1 configured to look for match on the XAB1 bus. any bits in the value can be masked to look at only a portion of the data value. The notation for these tables is explained below: Table 11-3. When this occurs. where N is the programmed 16-bit counter value. The trigger is asserted when “expr1” occurs at the same time as when “expr2” occurs. the condition becomes true and the trigger is asserted. On 1st occurrence of a match. This is particularly useful for examining a data value at a particular location in data memory. In addition. This is used when breakpoints are ORed or ANDed together. The trigger is only asserted on data accesses from memory. PAB-1* XAB1 XAB1* PAB-2 PAB-2* CDB — Data Value Fetch Access F/R/W/A R/W/A (expression)* expr1 OR expr2 expr1 AND expr2 expr1 ==> expr2 11-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the trigger is asserted.1 Listing the Breakpoint Unit Triggers Available The full set of breakpoint triggers which can be created by this unit is shown in Table 11-4 and Table 11-5. write. the trigger is asserted. Trigger 1 configured to look for match on the PAB bus. “expr1” must first occur. Trigger 1 configured to look for match on the XAB1 bus. The trigger is asserted on any data access to the memory — data read. Both must occurrence for the trigger to be asserted. The trigger is only asserted on instruction fetches from program memory. On 1st occurrence of a match. the trigger is asserted. 16-bit. It is not asserted if data is accessed from the program memory. The trigger is asserted on any access to the memory — instruction fetch. On 1st occurrence of a match. or access. where Table 11-4 contains most of the unit’s triggering capability and is combined with the capabilities of Table 11-5 to get the final Breakpoint Unit Trigger generated from the unit. It is not asserted for instruction fetches from the memory. Notation used in Breakpoint Unit Triggering Notation PAB-1 Description Trigger 1 configured to look for match on the PAB bus.

Trigger 1 ORed Triggers PAB-1 — Fetch (PAB-1 — Fetch PAB-1* — Access PAB-1 — Access (PAB-1 — Access PAB-2* — Fetch PAB-2 — Fetch OR OR OR OR OR OR OR PAB-2* — Fetch PAB-2 — Fetch)* PAB-2 — Fetch PAB-2* — Fetch PAB-2 — Fetch)* XAB1 — Access XAB1* — Access 1st Fetch on PAB Trig1. or 1st F Trig2) Nth Access on PAB Trig1. (1st F on PAB Trig1. (1st R/W/A XAB1 Trig1 and CDB Trig2) Sequenced Triggers PAB-1* — Fetch PAB-2 — Fetch PAB-1* — Access PAB-1 — Access PAB-2* — Fetch PAB-2 — Fetch XAB1* — R/W/A XAB1 — R/W/A PAB-2* — Fetch PAB-2 — Fetch ==> ==> ==> ==> ==> ==> ==> ==> ==> ==> PAB-2 — Fetch PAB-1* — Fetch PAB-2 — Fetch PAB-2* — Fetch PAB-1 — Access PAB-1* — Access PAB-2 — Fetch PAB-2* — Fetch XAB1 — R/W/A XAB1* — R/W/A Nth F on PAB Trig1 followed by 1st F PAB Trig2 1st F on PAB Trig2 followed by Nth F PAB Trig1 Nth A on PAB Trig1 followed by 1st F PAB Trig2 1st A on PAB Trig1 followed by Nth F PAB Trig2 Nth F on PAB Trig2 followed by 1st A PAB Trig1 1st F on PAB Trig2 followed by Nth A PAB Trig1 Nth R/W/A XAB1 Trig1 followed 1st F PAB Trig2 1st R/W/A XAB1 Trig1 followed Nth F PAB Trig2 Nth F PAB Trig2 followed 1st R/W/A XAB1 Trig1 1st F PAB Trig2 followed Nth R/W/A XAB1 Trig1 Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-17 . or 1st Fetch Trig2 Nth occur. or 1st F Trig2) Nth F on PAB Trig2. or 1st A on XAB1 1st F on PAB Trig2. or Nth Fetch Trig2 Nth occur.Enhanced OnCE and the Processing States Table 11-4. First Part of Breakpoint Unit Trigger(s)— 16-bit Counter Available for Triggering First Breakpoint Trigger Op Second Breakpoint Trigger Comments Single Triggers PAB-1* — F/R/W/A XAB1* — R/W/A (none) (none) Nth occurrence of F/R/W/A on PAB bus. (1st A on PAB Trig1. or 1st Fetch Trig2 1st Access on PAB Trig1. Trigger 1 Nth occurrence of R/W/A on XAB1 bus. or Nth A on XAB1 ANDed Triggers (XAB1 — R/W/A AND CDB — Data Value)* Nth occur.

4. Table 11-6. Other actions can be found in further sections which use “Breakpoint Unit Trigger” as a triggering condition. Breakpoint Unit Trigger — 16-bit Counter Available for Triggering Breakpoint Unit Trigger Case 1 Case 2 (First Part of Breakpoint trigger) OR Enabled DEBUGEV OR Enabled Limiting (First Part of Breakpoint trigger) => (Enabled DEBUGEV OR Enabled Limiting) This is true except for the cases where the Breakpoint Unit is used to generate both the Start and Stop triggers.4. one of the terminals available as an output of the Enhanced OnCE module. Possible Breakpoint Unit Actions Trigger for Action Case BK1 Case BK2 Case BK3 Case BK4 Case BK5 Breakpoint Unit Trigger Action Performed Enter Debug state Generate Breakpoint Unit Interrupt Request Start Trace Buffer Capture Halt Trace Buffer Capture Signal Watchpoint The “Signal Watchpoint” action listed above refers to simply toggling the event terminal. 11-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .2. 11.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) Table 11-4. First Part of Breakpoint Unit Trigger(s)— 16-bit Counter Available for Triggering First Breakpoint Trigger Op Second Breakpoint Trigger Comments Generation of Two Triggers — Start and Stop PAB-1 — Fetch => Start Trace Buffer PAB-1 — Access => Start Trace Buffer PAB-2 — Fetch => Start Trace Buffer — PAB-2 — Fetch => Stop Trace Buffer PAB-2 — Fetch => Stop Trace Buffer PAB-1 — Access => Stop Trace Buffer Start Trace Buffer on 1st Fetch on PAB Trig1 and Stop Trace on 1st Fetch on PAB Trigger 2 Start Trace Buffer on 1st Access on PAB Trig1 and Stop Trace on 1st Fetch on PAB Trigger 2 Start Trace Buffer on 1st Fetch on PAB Trig2 and Stop Trace on 1st Access on PAB Trigger 1 — — The final Breakpoint Unit trigger will then be one of the following: Table 11-5.2 Breakpoint Unit Actions Once a valid Breakpoint Unit Trigger has occurred. one of the following actions can be performed.

XAB1 [0:PAB] [0:PAB] CDBR/CDBW Read/Write Fetch Breakpoint 1 Breakpoint 2 32-bit Mask DEBUGEV instruction Overflow or saturation Combining Logic 16-Bit Counter Breakpoint Unit Trigger 24-Bit Step Counter Select Action Select Action Step Counter Halt Halt Trace Interrupt Core Buffer Start Trace Buffer Figure 11-10. Triggering the Step Counter with the Breakpoint Unit 11.4.2. Halt Trace Buffer Capture when Step Counter reaches zero.Enhanced OnCE and the Processing States 11.3 Combining the Breakpoint Unit with the Step Counter The breakpoint unit can work in conjunction with the 24-bit step counter so that the action is taken a specified number of clock cycles after the breakpoint condition is detected.4.4.4 Breakpoint Unit — Step Counter Actions Table 11-7 lists the possible actions when using the Step Counter.4. Case BKSC3 Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-19 . This configuration is illustrated in Figure 11-10. where the Breakpoint Unit can use any of the configurations in Table 11-4 and Table 11-5. Breakpoint Unit — Step Counter Operation Start Step Counter Case BKSC1 Case BKSC2 Breakpoint Unit Trigger Trigger for Step Counter Action Step Counter reaches zero Action Performed Enter Debug state Generate Step Counter Interrupt Request Start Trace Buffer Capture when Breakpoint Unit Trigger arrives. Table 11-7.2.

The Non-Cascaded configuration (Figure 11-11) uses the 16-bit counter providing count values up to 216.3.4.3 Capture Counter The Breakpoint Unit can also be configured as a Capture Counter to measure the number of clocks executed between two different points. the 16-bit breakpoint counter is configured to count clocks between two different points and is no longer available for generating breakpoint triggers. The Capture Counter can be configured as 16-bits or 40-bits. The triggers supported are shown in Table 11-8.4.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11. Starting and Stopping the Capture Counter — Non-Cascaded Counter Start Trigger Case CCT1 Case CCT2 Case CCT3 Case CCT4 Case CCT5 Case CCT6 Case CCT7 PAB Trigger 1 PAB Trigger 2 Breakpoint Unit Trigger Exit Reset or Debug state Execute DEBUGEV Limit occurs Execute DEBUGEV or Limit occurs Counter Stop Trigger PAB Trigger 2 PAB Trigger 1 Enter Debug state Breakpoint Unit Trigger Breakpoint Unit Trigger Breakpoint Unit Trigger Breakpoint Unit Trigger 11-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Table 11-8. Capture Counter — 16-bit Configuration (Non-Cascaded) The Capture Counter is configured by the user to count any of the three inputs to the MUX above: • • • Clocks executed Clocks executed without Wait States Instructions executed The counter measures any of these three values between two different points — the counter start trigger and the counter stop trigger. Start Clocks Clocks w/o Wait States Instructions Executed MUX 16-Bit Breakpoint Counter Select Action Status Bits Stop Counter Interrupt Halt Core Figure 11-11.1 16-Bit Capture Counter (Non-Cascaded) In this case.4.4. 11.

Trigger 1 1st R/W/A on XAB1 Bus. and no longer available for breakpoint triggering. First Part of Breakpoint Unit Trigger— 16-bit Counter in Capture Mode First Breakpoint Trigger Op Second Breakpoint Trigger Comments Single Triggers PAB-1 — F/R/W/A XAB1 — R/W/A (none) (none) 1st F/R/W/A on PAB Bus. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-21 . Trigger 1 ORed Triggers PAB-1 — Fetch PAB-1 — Access PAB-2 — Fetch OR OR OR PAB-2 — Fetch PAB-2 — Fetch XAB1 — Access 1st Fetch on PAB Trig1 or 1st Fetch PAB Trig2 1st Access on PAB Trig1 or 1st Fetch PAB Trig2 1st F on PAB Trig2 or 1st Access XAB1 Trig1 ANDed Triggers XAB1 — R/W/A AND CDB — Data Value 1st R/W/A on XAB1 Trig1 and CDB Data Val Trig2 Sequenced Triggers PAB-1 — Fetch PAB-1 — Access PAB-2 — Fetch XAB1 — R/W/A PAB-2 — Fetch ==> ==> ==> ==> ==> PAB-2 — Fetch PAB-2 — Fetch PAB-1 — Access PAB-2 — Fetch XAB1 — R/W/A 1st F on PAB Trig1 followed by 1st F PAB Trig2 1st A on PAB Trig1 followed by 1st F PAB Trig2 1st F on PAB Trig2 followed by 1st A PAB Trig1 1st R/W/A XAB1 Trig1 followed 1st F PAB Trig2 1st F PAB Trig2 followed 1st XAB1 R/W/A Trig2 Generation of Two Triggers — Start and Stop PAB-1 — Fetch => Start Capture Ctr PAB-1 — Access => Start Capture Ctr PAB-2 — Fetch => Start Capture Ctr — PAB-2 — Fetch => Stop Capture Ctr PAB-2 — Fetch => Stop Capture Ctr PAB-1 — Access => Stop Capture Ctr Start Capture on 1st Fetch on PAB Trig 1 and Stop Capture on 1st Fetch on PAB Trig2 Start Capture on 1st Access on PAB Trig 1 and Stop Capture on 1st Fetch on PAB Trig2 Start Capture on 1st Fetch on PAB Trig 2 and Stop Capture on 1st Access on PAB Trig1 — — Note that the triggers above do not support the ability of triggering on the Nth occurrence because the 16-bit counter is now dedicated to counting operations.Enhanced OnCE and the Processing States Cases CCT1 and CCT2 directly use the first and second triggers of the Breakpoint Unit as Start and Stop triggers. These remaining cases use any of the triggers supported in Table 11-9: Table 11-9. The remaining cases use the Breakpoint Unit to generate either the Start trigger (case CCT3) or the Stop trigger (remaining cases).

11.trigger only if the Stop trigger arrives before the counter expires. Breakpoint Unit Trigger — for 16-bit Capture Counter Breakpoint Unit Trigger Case 1 Case 2 (First Part of Breakpoint trigger) OR Enabled DEBUGEV OR Enabled Limiting (First Part of Breakpoint trigger) => (Enabled DEBUGEV OR Enabled Limiting) NOTE: The equation in Table 11-10 above can be used except for the cases entitled “Generation of Two Triggers — Start and Stop” where the Breakpoint Unit is used to generate both the Start and Stop triggers.4.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) The final Breakpoint Unit trigger will then be one of the following: Table 11-10.2 Actions for 16-Bit Capture Counter (Non-Cascaded) Table 11-11 shows the actions which can be performed when the Capture Counter expires. Note the unusual triggering which can be performed to check that the counter expires before a Stop trigger arrives.4. the reverse triggering is also supported . CZ Signal Watchpoint Enter Debug state Generate EOnCE Interrupt Request Signal Watchpoint Capture Counter reaches zero before Counter Stop Trigger occurs Action Performed Enter Debug state Generate EOnCE Interrupt Request 11-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Similarly. Possible Capture Counter Actions — Non-Cascaded Trigger for Action Case CC1 Case CC2 — OR — Case CC3 Case CC4 Case CC5 Case CC6 Case CC7 Capture Counter reaches zero (for cases where no Stop Trigger is configured) Counter Stop Trigger occurs before Capture Counter reaches zero Set Capture Counter status bits — CS.3. Table 11-11.

This configuration is illustrated in Figure 11-12. 11.4. Table 11-12. Similarly.3 Using the Capture Counter with the Step Counter The Capture Counter can also work in conjunction with the 24-bit step counter so that the action is taken a specified number of clock cycles after a Capture Counter trigger is generated. Start Clocks Clocks w/o Wait States Instructions Executed MUX Stop Capture Counter Trigger 16-Bit Breakpoint Counter 24-Bit Step Counter Start Trace Buffer Select Action Step Counter Halt Halt Trace Interrupt Core Buffer Figure 11-12. Halt Trace Buffer Capture when Step Counter reaches zero.trigger only if the Stop trigger arrives before the Capture Counter expires. Enter Debug state Generate Step Counter Interrupt Request Start Trace Buffer Capture when Capture Counter reaches zero. where the Breakpoint Unit can use any of the configurations in Table 11-9 and Table 11-10.4.4.4 16-bit Capture Counter — Step Counter Actions Table 11-12 shows the actions which can be performed in this configuration. Triggering the Step Counter with the Capture Counter This configuration also uses the Start-Stop triggers listed in Table 11-8. Halt Trace Buffer Capture when Step Counter reaches zero.3.Enhanced OnCE and the Processing States 11. Note the unusual triggering which can be performed to check that the Capture Counter expires before a Stop trigger arrives.3.4. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-23 . the reverse triggering is also supported . Possible Capture Counter Actions — Non-Cascaded Trigger for Action Case CCSC1 Case CCSC2 Case CCSC3 Capture Counter reaches zero before Counter Stop Trigger occurs => Step Counter reaches zero — OR — Capture Counter reaches zero => Step Counter reaches zero (for cases where no Stop Trigger is configured) Case CCSC4 Case CCSC5 Case CCSC6 Counter Stop Trigger occurs before Capture Counter reaches zero => Step Counter reaches zero Action Performed Enter Debug state Generate Step Counter Interrupt Request Start Trace Buffer Capture when Capture Counter reaches zero.

4. BRSET. This configuration is illustrated in Figure 11-12. BRCLR instructions Change-of-Flow Case 1 —captures the target address of backward branches of Bcc. BRCLR instructions 11-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Capture Counter — 40-bit Configuration (Cascaded) This configuration also uses the Start-Stop triggers listed in Table 11-8.3. BRSET. BRCLR instructions Change-of-Flow Case 0 —captures target address of Jcc or forward branches of Bcc. 11. the Capture Counter can also be cascaded with the 24-bit step counter to provide 40-bit counting operations.4 Programmable Trace Buffer The Trace Buffer is used to the change-of-flows selected by the user. allowing any combination of these to be selected by the user: • • • • • Interrupts—captures the address of the interrupt vector and target address of RTI and FRTID Subroutines—captures target address of JSR and BSR instructions Change-of-Flow Not Taken —captures target address of Bcc. BRSET. where the Breakpoint Unit can use any of the configurations in Table 11-9 and Table 11-10.4.4.4.5 40-Bit Capture Counter (Cascaded) If additional counter bits are needed.3.4. Jcc. Separate control bits are available for the following five cases.6 Actions for 40-Bit Capture Counter (Cascaded) The actions supported by this configuration are the same as those listed in Table 11-11. 11.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11. Start Clocks Clocks w/o Wait States Instructions Executed MUX 16-Bit Breakpoint Counter Stop 24-Bit Breakpoint Counter Select Action Status Bits Counter Interrupt Halt Core Figure 11-13.4.

Enhanced OnCE and the Processing States PAB Conditional Branches and Jumps Interrupts. Subroutines Address Selection Start Capture 8-Location Trace buffer Stop Capture Trace Buffer Full Select Action Status Bits Halt Trace Buffer Halt Capture Interrupt Core Figure 11-14. The Breakpoint Unit Trigger can use any of the configurations in Table 11-9 and Table 11-10. Possible Actions on Trace Buffer Full Action Performed Case TBF1 No Action Performed — Trace Buffer continues to capture new addresses. Programmable Trace Buffer Several different options are available for starting and/or stopping Trace Buffer capture (Table 11-13). Buffer Capture Halted — TBH is asserted Buffer Capture Halted — Enter Debug state Buffer Capture Halted — Generate Trace Buffer Interrupt Request Case TBF2 Case TBF3 Case TBF4 Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-25 . In addition. Trace Buffer capture can also be programmed to stop once it has filled (Table 11-14). overwriting the old addresses as needed. Starting and Stopping Trace Buffer Capture Start Trigger Case 1 Case 2 Case 3 PAB Trigger 1 Breakpoint Unit Trigger Exit Debug state Stop Trigger PAB Trigger 2 — Breakpoint Unit Trigger The Trace Buffer can be programmed to perform any of the actions listed in Table 11-14 when the Trace Buffer is full: Table 11-14. Table 11-13.

“Using the Capture Counter with the Step Counter. • • • • • • • • • • • • Fetch. or read or write of specific data address Example: XAB1 == $0C0000. Read.4.” on page 11-19 and Section 11. or read or write of specific program address Example: PAB == $000080.5 Example Breakpoint Scenarios The following are examples of the variety of conditions that can trigger a breakpoint or step counter action.3.4. write.4.” on page 11-23. “Breakpoint Unit — Step Counter Actions.2.4.4.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) The Trace Buffer can also be configured to Start and Stop capture as shown in Section 11.4. The nth occurrence of an instruction Example: 500 occurrences of PAB == $008794. Either of two instructions Example: PAB == $3792 || PAB == $7E45 A sequence of two instructions Example: PAB == $3792 → PAB == $7E45 The nth occurrence of an instruction followed by another instruction Example: 1037 occurrences of PAB == $394 → PAB == 7E45 Write a specific value to a data address Example: XAB1 == $00FFE7 && CDBW == $AAAA Read value from data address Example: XAB1 == $00FFE7 && CDBR == $5555 Read a data value other than the one specified from a particular data address Example: XAB1 == $00FFE7 && CDBR != $AAAA Read or write a particular set of bits from/to a data address Example: XAB1 == $00FFE7 && CDBW[2:0] == 011b Either of two program addresses or a DEBUGEV instruction followed by n instructions Example: PAB == $3792 || PAB == $7E45 || DEBUGEV → 4000 instructions A sequence of two program addresses followed by a DEBUGEV instruction followed by n instructions Example: PAB == $3792 → PAB == $7E45 → DEBUGEV → 4000 instructions The nth occurrence of an instruction followed by another instruction followed by an overflow condition followed by m instructions Example: 900 occurrences of PAB == $3792 → PAB == $7E45 → OV → 9 instructions A particular bit pattern not occurring at a specific data address followed by n instructions Example: XAB1 == $00FFE7 && CDB[14:12] != 011b → 20. write. read. 11.3.000 instructions The nth occurrence of the above condition followed by m instructions Example: 400 occurrences of (XAB1 == $00FFE7 && CDB[14:12] != 011b) → 350 instructions • • • 11-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

part. consult the user’s manual for the specific device. The JTAG TLM is a dedicated. IEEE Standard Test Access Port and Boundary-Scan Architecture. For a full description of the interface signals.5 JTAG Port The DSP56800E core Joint Test Action Group (JTAG) test access port (TAP) provides the interface for the Enhanced OnCE module to the DSC JTAG pins. This TAP controller is designed to be incorporated into a chip multi–JTAG TAP Linking Module (JTAG TLM) system. If the core TAP is not incorporated into a JTAG TLM system it will not be compliant with the IEEE 1149.JTAG Port 11. Commands for the JTAG port are completely independent from the DSP56800E instruction set. and revision numbers of the DSP56800E core via the JTAG port. user-accessible. All JTAG data is sent over this interface.5. part. Problems associated with testing high-density circuit boards have led to the development of this standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG. test access port (TAP) system that is compatible with the IEEE Standard 1149. 11. and version numbers) Provides a means of accessing the Enhanced OnCE module controller and circuits to control a target system Provides a means of entering the debug mode of operation Bypasses the TAP through a single-bit register in the Shift-DR-Scan path The following sections provide an overview of the port’s architecture and commands. It is implemented as a serial interface to occupy as few external pins on the device as possible. but the TAP will still serve as an interface to the core Enhanced OnCE module.1a-1993. process technology. which provides a unique ID for each revision of the DSP56800E core. This register enables a development system to determine the manufacturer. 11. The JTAG module contains the DSP56800E identification register. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-27 . Enhanced OnCE commands and data from the host system can also sent over this interface if accessed via JTAG.2 JTAG Port Architecture The JTAG port consists of the following components: • • • Serial communication interface Command decoder and interpreter DSP56800E identification register The serial interface provides the communication link between the core and the host development or debug system.1 JTAG Capabilities The DSP56800E JTAG port has the following capabilities: • • • • Provides queried identification information for the DSP56800E core (manufacturer.1a-1993 standard.5. Specific details on the implementation of the JTAG port for a given DSP56800E–based device are provided in the user’s manual for that device. technology process. and they are executed in parallel by the JTAG logic. Commands sent to the JTAG module are decoded and processed by the command decoder.

Test Mode Select Input—This input pin is used to sequence the core JTAG TAP controller’s state machine. and will return to Run-Test/Idle when the pin is deasserted in the Update-DR state. It is sampled on the rising edge of TCK. The core JTAG TAP also uses the TLM_RESET_B pin to provide an asynchronous reset of the core JTAG port from the chip JTAG TLM. The core pin functions are described in Table 11-15. TDO. and TMS signals. CORE_TDO. JTAG Pin Descriptions Pin Name CORE_TDI Pin Description Test Data Input—This input pin to the core provides a serial input data stream to the core TAP and the EOnCE module. Test Data Output—This output pin provides a serial output data stream from the core TAP and the EOnCE module. CORE_TDO TCK TMS TLM_RESET_B CORE_TAP_EN CORE_TLM_SEL The core JTAG TAP must be enabled (CORE_TAP_EN asserted) before the core JTAG state machine will follow the transitions and state of the TMS pin. The core TAP will only leave the Run-Test/Idle state to enter the DR or IR states while the CORE_TAP_EN pin is asserted. If TRST is present on a chip the core TLM_RESET_B pin will always be asserted whenever TRST is asserted. When the enable signal is asserted.2. comes from the chip TLM module and gates the input TMS signal to force the TAP controller to the Run-Test/Idle state when the enable signal is deasserted (logic 0). It is driven in the Shift-IR and Shift-DR controller states of the core TAP state machine. the TAP controller will follow the transitions and state of the input pin TMS signal. TCK. Test Reset—This input pin. When accessing the EOnCE module through the JTAG TAP. comes from the chip TLM and provides an asynchronous reset signal to the JTAG TAP controller. TDI and TDO are the serial input and output. 11-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . A fifth pin TRST is an optional asynchronous reset pin for the chip JTAG TLM system (refer to the particular chip users manual to see if this pin is available). It is sampled on the rising edge of TCK. TCK. Core TAP Enable—This input. TMS. the maximum frequency for TCK is 1/4 the maximum frequency specified for the Hawk Version 2 core. TCK is the serial clock input and TMS is an input used to selectively step through the JTAG state machine. Test Clock Input—This input pin provides the clock to synchronize the test logic and shift serial data to and from the core EOnCE/JTAG port. These pins for the core JTAG port are CORE_TDI. a JTAG TAP requires a minimum of 4 pins to support TDI.5.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11. Table 11-15.1a-1993 specification. Core TLM Selects—This output from the core JTAG TAP selects the chip TLM register for the data register to be scanned. respectively.1 JTAG Terminal Description As described in the IEEE 1149..

A third register. JTAG Port Programming Model 11. is read only. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-29 . There are 2 read/write registers in the JTAG port: the IR.5.2 Core JTAG Programming Model Figure 11-15 shows the programming models for the core JTAG registers.JTAG Port 11.5.3 Core JTAG Port Block Diagram A block diagram of the JTAG port is shown in Figure 11-16. the Core Identification Register. 3 2 1 0 INSTRUCTION Core JTAG B3 B2 B1 B0 Instruction Register Reset = $2 ID—(IR = $2) Core Identification Register Reset = Core ID Read 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYPASS—(IR = $F) Core JTAG Bypass Register Reset = $0 Read/Write 0 Figure 11-15.2.2. and the core Bypass Register.

respectively.4 Core TAP Controller The TAP controller is a sixteen state synchronous finite state machine. The shifting. NOTE: The core JTAG port oversees the shifting of data into and out of the EOnCE port through the CORE_TDI and CORE_TDO pins.5. 11-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge of TCK. When the tlm_res_b signal is deasserted and the core_tap_en pin is asserted. The TAP controller will asynchronously be reset to the Test-Logic-Reset state upon assertion low of tlm_res_b pin. the TAP controller responds to changes of the TMS and TCK signals. is guided by the same tap controller used when shifting core JTAG Instruction Register (IR) information. 11. Core JTAG Block Diagram The TAP controller provides access to the IR through the core JTAG port.2. in this case. used to sequence the core JTAG port through its valid operations: • • • • Serially shift in or out a core JTAG instruction Update (and decode) the core JTAG Instruction Register Serially output the core ID code Serially shift in or out and update the EOnCE registers. The other core JTAG registers must be individually selected by the IR. Transitions from one state to another occur on the rising edge of TCK. The TAP controller is shown in Figure 11-17.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) To EOnCE Port CORE_TDI Instruction Register Decode CORE_TDO Core ID Register Core Bypass Register TMS TCK TLM_RESET_B CORE_TAP_EN CORE_TLM_SEL From EOnCE Port TAP Controller Figure 11-16.

After this is selected. by core_tap_en pin assertion. Freescale SemiconductorJTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11-31 . Asserting the tlm_reset_b pin low asynchronously forces the core JTAG state machine into the Test-Logic-Reset state. Test-Logic-Reset 1 0 Run-Test/Idle 0 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 0 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 1 Select-IR-Scan 0 Capture-IR 0 Shift-IR 1 0 1 1 Figure 11-17. The core TAP controller executes the last instruction decoded until a new instruction is entered at the Update-IR state or until the Test-Logic-Reset state is entered. TAP Controller State Diagram There are two paths through the 16-state machine. When using the core JTAG port to access EOnCE module registers. accesses are first enabled by shifting the ENABLE_EOnCE instruction into the core JTAG IR.JTAG Port When the core_tap_en pin is deasserted the TAP controller returns to the Run-Test/Idle state at the next rising edge of TCK and remains there until the TAP is re-enabled to follow the transitions and state of the TMS signal. The Shift-IR_Scan path is used to capture and load core JTAG instructions into the core JTAG IR. The Shift-DR_Scan path captures and loads data into the other core JTAG registers. the EOnCE module registers and commands are read and written through the core JTAG pins using the Shift-DR_Scan path.

The core JTAG TAP will bring the core out of Stop or Wait modes when DEBUG_REQUEST is decoded in the TAP IR. A small amount of additional power above the minimum possible will be expended by the core TAP logic if the core TAP is utilized during Stop mode. Since all Hawk V2 core clocks are disabled during Stop mode. 11-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . that is invoked by the Hawk V2 core executing a STOP instruction.JTAG and Enhanced On-Chip Emulation (Enhanced OnCE) 11.3 JTAG Port Restriction — STOP Processing State The core features a low-power stop mode. the JTAG interface provides the means of polling the device status (sampled in the capture-IR state).5.

“Instruction Descriptions.” provides additional details about the notation for opcode encoding.” explains most of the notation that is used in Section A.5. “Condition Code Calculation.1 Notation Each instruction description abbreviates operands using the notation that is contained in the following tables. “Notation. Section A. Table A-1 on page A-2 defines the register notation that is used in general read and write operations.Appendix A Instruction Set Details This appendix contains detailed information about each instruction of the DSC core instruction set. see Appendix B. Section A. condition codes.1. and instruction timing.” which shows the syntax of all allowed instructions and summarizes addressing modes.2.” A. “Instruction Opcode Encoding. Freescale Semiconductor Instruction Set Details A-1 . For more detailed information on condition codes.

and D1. Y1 R0–R5. Note the usage of A1. Table A-2 on page A-3 shows the registers that are available for use as pointers in address-register-indirect addressing modes.L. The most common fields that are used in this table are Rn and RRR. HHH (destination) A. Used for long memory accesses. C. N A. B1.L (destination) A. N Five data ALU and seven AGU registers that are used as destination registers. and D. Note the usage of A. D1 X0. B. HHH. B10. Y0. B. HHHH. B1. C. D Y X0. N A10. D10 Y R0–R5. Y0. HHHH (source) A1. C1. B1. C1.L (source) Five data ALU and seven AGU registers that are used as source registers. D Y Five data ALU registers—four 32-bit MSP:LSP portions of the accumulators and one 32-bit Y data register (Y1:Y0) that is used as a destination register. Note the usage of A. Y0. and D. C1. Also see dddd. C.Table A-1. N Seven data ALU and seven AGU registers that are used as source registers. Used for long memory accesses. C1. HHH. Five data ALU registers—four 32-bit MSP:LSP portions of the accumulators and one 32-bit Y data register (Y1:Y0) that is used as a source register. This table also shows the notation that is used for AGU registers in AGU arithmetic operations. HHHH. D Y X0. D Y R0–R5. B. and D1. Y1 Seven data ALU registers—four 16-bit MSP portions of the accumulators and three 16-bit data registers that are used as destination registers. Y1 R0–R5. Note the usage of A1. B10. C10. A-2 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . B. This field is identical to the FFF1 field. Used for long memory accesses. Y1 Comments Seven data ALU registers—four 16-bit MSP portions of the accumulators and three 16-bit data registers that are used as source registers.L (destination) A. Register Fields for General-Purpose Writes and Reads Register Field HHH (source) Registers in this Field A1. Writing word data to the 32-bit Y register clears the Y0 portion. C10. D1 X0.L (source) A10.L. Used for long memory accesses. C. D10 Y HHHH (destination) Seven data ALU and seven AGU registers that are used as destination registers. C. Also see dddd. B. Writing word data to the 32-bit Y register clears the Y0 portion. Y0. C. B. B1.

Address Generation Unit (AGU) Registers Register Field Rn Registers in this Field R0–R5 N SP R0–R5 N R0. C1. The most common field that is used in this table is FFF. Y1 A1. This field is identical to the HHH (source) field. Y1 Seven data ALU registers—four accumulators and three 16-bit data registers that are accessible during data ALU operations. Three 16-bit data registers. Y0. B. Four 36-bit accumulators that are accessible during data ALU operations.Table A-2. Y0. R1. This field is similar to FFF but is missing the 32-bit Y register. fff A. and D1. B. C. R2. Y0. B Four 36-bit accumulators and one 32-bit long register that are accessible during data ALU operations. B. D X0. Y1 A. C1. D Y A. R3 N3 Comments Eight AGU registers that are available as pointers for addressing and address calculations Seven AGU registers that are available as sources and destinations for move instructions Four pointer registers that are available as pointers for addressing One index register that is available only for the second access in dual parallel read instructions Address modifier register Fast interrupt return register RRR (or SSS) Rj N3 M01 FIRA M01 FIRA Table A-3 shows the register set that is available for use in data ALU arithmetic operations. The 16-bit MSP portions of two accumulators that are accessible as source operands in parallel move instructions. B. Two 36-bit accumulators that are accessible during parallel move instructions and some data ALU operations. D1 X0. Y0. Used for instructions where Y is not a useful operand (use Y1 instead). one 32-bit long register Y. It is very similar to FFF. Data ALU Registers Register Field FFF Registers in this Field A. Note the usage of A1. EEE A. C. D X0. C. Y1 Comments Eight data ALU registers—four 36-bit accumulators. D Y X0. B1. B1 Freescale Semiconductor Instruction Set Details A-3 . B1. and three 16-bit data registers that are accessible during data ALU operations. C. Table A-3. Seven data ALU registers—four 16-bit MSP portions of the accumulators and three 16-bit data registers that are accessible during data ALU operations. FFF1 FF DD F F1 A1. but it indicates that the MSP portion of the accumulator is in use.

D1 Y Y1. A0 B. N3. The registers in this field and SSSS combine to make the DDDDD register field. Note that the C2. B2. HHHHH A. LA2. A0 B. LC2. B0 C. B1. which also can access the stack via the MOVE. OMR. LC HWS dd C2.L A2. LC. not as a source. D2. SR Miscellaneous set of registers that can be placed onto or removed from the stack 32 bits at a time. This register set supplements the DDDDD field. HWS OMR. Y1. Y is permitted only as a destination. D0 Extension and LS portion of the C and D accumulators. X0 R0. N3 OMR. It contains the contents of the HHHHH and SSSS register fields. R2. The registers in this field and in HHHHH combine to make the DDDDD register field. HWS. M01. B1. D1 Y Y1. R1. A1. R2. SR LA. Additional Register Fields for Move Instructions Register Field DDDDD Registers in this Field A. Y0. R5. Table A-4.Table A-4 shows additional register fields that are available for move instructions. X0 This set designates registers that are written with signed values when they are written with word values. A2. C0. Writing word data to the 32-bit Y register clears the Y0 portion. Y0. See the dd register field in this table for these registers SSSS R0. SP M01. SR dddd. N. R3 R4. B2. LA. This list supplements the registers in the HHHH. This set designates registers that are written with unsigned values when they are written with word values. C1 D. SP M01. R1. C0. Y is permitted only as a destination. R3 R4. D2. N. B2.L field. C1 D. N3 LA.L instruction. C2. and D0 registers are not available within this field. R5. not as a source. A1. LC. B0 C. A-4 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . D2 Y0. A2. Comments This field lists the CPU registers. X0 SP.

7 Section A.7 Section A.7 Section A.5.5. Opcode Encoding Fields Encoding Field AAA AA AAAAAA aaa aaaaaa Aaaaaaa bb bbb BBBBB BBBBBB BBBBBBB ccc CCC CCCC DD dddd ddddd DDDDD hhhhh SSSS EEE F FF fff FFF GGG GGG GGGG Description Top 3 address bits for branch Top 2 address bits for branch 6-bit positive offset for X:(R2+xx) addressing mode Data ALU register (excluding Y) 6-bit negative offset for X:(SP–xx) addressing mode 7-bit signed offset for branch instructions Accumulator Data ALU register 5-bit signed integer immediate 6-bit signed integer immediate 7-bit signed integer immediate 16-bit data ALU register or accumulator portion Condition code specifier Condition code specifier 16-bit data ALU register Special 32-bit stack push/pop register Full set of DSP56800E registers Full set of DSP56800E registers DALU set registers Non-DALU set registers Data ALU register (excluding Y) A or B accumulator Accumulator Accumulator or Y Data ALU register Data ALU register Parallel move destination register 24-bit AGU pointer register or 16-bit data ALU register Location Section A.7 Table A-7 Table A-17 Table A-18 Table A-7 Table A-13 Table A-12 Table A-11 Table A-11 Table A-11 Table A-7 Table A-7 Table A-7 Table A-7 Table A-7 Table A-10 Table A-14 Table A-10 Freescale Semiconductor Instruction Set Details A-5 .5. Table A-5.5.7 Section A.5.7 Table A-7 Table A-7 Section A.5.7 Table A-7 Section A.5.7 Section A.5.Table A-5 provides an alphabetical overview of the fields and refers to the additional section and tables that contain the precise encoding values.

7 Table A-9 Table A-8 Table A-8 Table A-10 Table A-10 Table A-10 Section A.7 Table A-9 Table A-9 Table A-8 Table A-16 Table A-16 Table A-10 Table A-10 Section A.5.5.Table A-5.5. Opcode Encoding Fields (Continued) Encoding Field hhh hhhh iii iiii JJ JJJ JJJJJ m MM nnn NNN Ppppppp QQ qqq QQQ RR RRR SSS U Data ALU register Full set of DSP56800E registers 3-bit offset for X:(Rn+x) and X:(SP–x) addressing modes 4-bit unsigned integer immediate 16-bit data ALU register Accumulator or 16-bit data ALU register Two input registers for three-operand instructions Addressing mode specifier Addressing mode specifier 24-bit AGU pointer register or 16-bit data ALU register 24-bit AGU pointer register 7-bit absolute address for X:<<pp addressing mode 16-bit data ALU register Two input registers for three-operand instructions Two input registers for three-operand instructions R0–R3 pointer registers 24-bit AGU pointer register 24-bit AGU pointer register Single bit to indicate lower or upper byte in BRSET and BRCLR Dual parallel read destination registers Description Location Table A-13 Table A-13 Table A-19 Section A.7 vvvv Table A-15 Certain core instructions use symbols in the instruction field to represent operands or addressing modes in the opcodes. Instruction Field Symbols Symbol Q1 Q2 Q3 Q4 X:<ea_m> Meaning First source register in the QQQ field Second source register in the QQQ field First source register in the QQ field Second source register in the QQ field Addressing mode of ‘m’ field in single parallel move or the first operand in a dual parallel read Reference Table A-8 on page A-332 Table A-8 on page A-332 Table A-16 on page A-345 A-6 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Table A-6. These symbols are listed in Table A-6.

1.5. Instruction Field Symbols Symbol X:<ea_v> X:<ea_MM> Meaning Addressing mode of ‘vvvv’ field in the second operand of a dual parallel read Addressing mode of ‘MM’ field for memory access Reference Table A-15 on page A-344 Table A-16 on page A-345 A. “Condition Code Calculation. these fields include the parenthetical comment “(parallel move).2 Instruction Descriptions The following section describes each instruction in the instruction set in complete detail. Whenever an instruction uses an accumulator as both a destination operand for a data ALU operation and as a source for a parallel move operation. For a more thorough discussion of condition code calculation. refer to Appendix B. the parallel move operation uses the value in the accumulator prior to the execution of any data ALU operation. although it does not discuss those that are referenced by the parallel move portion of the instruction. For instructions that allow parallel moves. The example discusses the contents of all the registers and memory locations that are referenced by the opcode and operand portion of the instruction.” For more information about the notation that is used in the “Instruction Opcode” sections of the instruction descriptions.” The “Operation” and “Assembler Syntax” fields appear at the beginning of each description.” Freescale Semiconductor Instruction Set Details A-7 .” Every description also includes an example.Table A-6. A brief overview of the condition codes that are affected by each instruction is presented in each instruction’s “Condition Codes Affected” section. see Section A. “Instruction Opcode Encoding. “Notation. Aspects of each instruction description are explained in Section A.

data limiting will occur to value $F:8000:000.ABS Operation: |D| → D |D| → D (one parallel move) (no parallel move) Absolute Value Assembler Syntax: ABS ABS D D (one parallel move) (no parallel move) ABS Description: Take the absolute value of the destination operand (D) and store the result in the destination accumulator or 16-bit register. When saturation is enabled (SA = 1 in the OMR register). If saturation is not enabled.0 when interpreted as a decimal fraction). fixed-point. Example: ABS A X:(R0)+. the ABS instruction causes an overflow to occur since the result cannot be correctly expressed using the standard 36-bit. update R0 After Execution FFF2 A0 SR 0301 0 A2 0000 A1 SR 000E A0 0311 Before Execution F A2 FFFF A1 Explanation of Example: Prior to execution. take ABS value. move data into Y0. The execution of the ABS instruction takes the two’s-complement of that value and returns $0:0000:000E. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extended portion of accumulator result is in use Set according to the standard definition of the U bit Set if MSB of result is set Set if result equals zero Set if overflow has occurred in result A-8 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the 36-bit A accumulator contains the value $F:FFFF:FFF2. the value will remain unchanged.Y0 . two’s-complement data representation. . Note: When the D operand equals $8:0000:0000 (–16. Duplicate destination is not allowed when this instruction is used in conjunction with a parallel read.

GGG 0 15 0 1 0 12 1 11 G G G 8 F 7 0 1 0 4 0 3 m R R 0 ABS FFF 0 1 1 1 0 1 F F F 0 1 0 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-9 .ABS Instruction Fields: Operation ABS Operands FFF Absolute Value C 1 W 1 Absolute value.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.X:<ea_m> 0 15 0 0 0 12 1 11 G G G 8 F 7 0 1 0 4 0 3 m R R 0 ABS F X:<ea_m>.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed. Memory writes are allowed in this case. Instruction Opcodes: 15 12 11 8 7 4 3 0 ABS F GGG. 2. Comments ABS Parallel Moves: Data ALU Operation Operation ABS2 Operands F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.

Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L E U N Z V C — — — — — — — Set if overflow has occurred in result Set if the extended portion of accumulator result is in use Set according to the standard definition of the U bit Set if bit 35 of accumulator result is set Set if accumulator result is zero. cleared otherwise Set if overflow has occurred in accumulator result Set if a carry (or borrow) occurs from bit 35 of accumulator result A-10 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .ADC Operation: S + C + D →D (no parallel move) Add Long with Carry Assembler Syntax: ADC S. In addition. Example: ADC Y. The ADC instruction automatically sign extends the 32-bit Y register to 36 bits and adds this value to the 36-bit accumulator. the initial value of C is set to one.1. Note: C is set correctly for multi-precision arithmetic.” on page 5-29) when it is necessary to add together two numbers that are larger than 32 bits (as in 64-bit or 96-bit addition).A . using long-word operands only when the extension register of the destination accumulator (FF2) contains only sign extension information (bits 31 through 35 are identical in the destination accumulator).5. “Extended-Precision Addition and Subtraction. and the condition codes are set appropriately.D (no parallel move) ADC Description: Add the source operand (S) and the carry bit (C) to the second operand. is added into the LSB of this 36-bit operation. add Y and carry to A After Execution 8000 A0 8000 Y0 SR 0301 0 A2 4001 A1 2000 Y1 SR 0001 A0 8000 Y0 0300 Before Execution 0 A2 2000 A1 2000 Y1 Explanation of Example: Prior to execution. and the 36-bit accumulator contains the value $0:2000:8000. C. and store the result in the destination (D). the 32-bit Y register—which is composed of the Y1 and Y0 registers—contains the value $2000:8000. Usage: This instruction is typically used in multi-precision addition operations (see Section 5. The source operand (register Y) is first sign extended internally to form a 36-bit value before being added to the destination accumulator. The 36-bit result is stored back in the A accumulator. The carry bit. The result is not affected by the state of the saturation bit (SA). The Y1:Y0 register pair is not affected by this instruction.

ADC Instruction Fields: Operation ADC Operands Y.F Add Long with Carry C 1 W 1 Comments Add with carry (set C bit also) ADC Instruction Opcodes: 15 12 11 8 7 4 3 0 ADC Y.F 0 1 1 1 0 1 0 0 F 0 0 0 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-11 .

Before Execution 0 A2 X0 0058 A1 0002 R2 N Explanation of Example: Prior to execution. Similarly. C is always set correctly using accumulator source operands. Y0. In this case.ADD Operation: S+D→ S+D→ S+D→ D D D (no parallel move) (one parallel move) (two parallel reads) Add Assembler Syntax: ADD ADD ADD S. A-12 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .A X:(R2)+N. if the source operand is one of the four accumulators. When the destination is X0. the FF1 portion (properly sign extended) is used in the 16-bit addition. update R2 After Execution 1234 A0 0 A2 X0 002001 FFFFFF SR 0300 005A A1 3456 R2 N 002000 FFFFFF SR 0310 1234 A0 This instruction can be used for both integer and fractional two’s-complement data.D (no parallel move) (one parallel move) (two parallel reads) ADD Description: Add the source register to the destination register and store the result in the destination (D). If the destination is a 36-bit accumulator.X0 . or Y1.D S. the 16-bit X0 register contains the value $0002. the FF2 and FF0 portions are ignored.D S. The ADD instruction automatically appends the 16-bit value in the X0 register with 16 LS zeros. load X0. if the destination is the Y register. Note: The carry bit (C) in the CCR is set correctly using word or long-word source operands if the extension register of the destination accumulator contains sign extension from bit 31 of the destination accumulator. Usage: Example: ADD X0. and the 36-bit A accumulator contains the value $0:0058:1234. and adds the result to the 36-bit A accumulator. 16-bit addition. sign extends the resulting 32-bit long word to 36 bits. A new word is read into the X0 register and address register R2 is updated by –1. the FF2 portion is ignored. 16-bit addition is performed. 16-bit source registers are first sign extended internally and concatenated with 16 zero bits to form a 36-bit operand (the Y register is only sign extended).

F A. Freescale Semiconductor Instruction Set Details A-13 .This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.F Y1.A Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.B B.ADD Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 Add ADD CCR 6 L 5 E 4 U 3 N 2 Z 1 V 0 C 8 I0 7 SZ SZ L E U N Z V C — — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extended portion of the accumulator result is in use Set if the result is unnormalized Set if the high-order bit of the result is set Set if the result equals zero Set if overflow has occurred in the result Set if a carry occurs from the high-order bit of the result Instruction Fields: Operation ADD Operands FFF.F C. Parallel Moves: Data ALU Operation Operation ADD2 Operands X0. 2.FFF C 1 W 1 Comments 36-bit add two registers. Memory writes are allowed in this case.F Y0.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.

F A. when the instructions are executing from data memory).This instruction is not allowed when the XP bit in the OMR is set (that is. A-14 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .F Y0.F Y1.B B. 2.ADD Parallel Dual Reads: Data ALU Operation1 Operation ADD2 Operands X0.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.A Add ADD Second Memory Read Source 2 X:(R3)+ X:(R3)– Destination 2 X0 First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Y0 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 Y1 C 1.

reg2 0 1 1 0 0 0 v v F v 1 0 0 m 0 v Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-15 .ADD Instruction Opcodes: 15 Add ADD 8 7 4 3 0 12 11 ADD FFF.F X:<ea_m>.reg2 ~F.X:<ea_m> 0 15 0 0 0 12 0 11 G G G 8 F 7 J J J 4 0 3 m R R 0 ADD DD.F X:<ea_m>.GGG 0 15 0 1 0 12 0 11 G G G 8 F 7 1 1 0 4 0 3 m R R 0 ADD DD.F GGG.reg1 X:<ea_v>.reg1 X:<ea_v>.GGG 0 15 0 1 0 12 0 11 G G G 8 F 7 0 0 0 4 0 3 m R R 0 ADD ~F.FFF 0 15 1 1 1 12 1 11 0 F F 8 F 7 b b b 4 0 3 0 0 0 0 ADD C.F GGG.F X:<ea_m>.F GGG.F X:<ea_m>.F X:<ea_m>.X:<ea_m> 0 15 0 0 0 12 0 11 G G G 8 F 7 1 1 0 4 0 3 m R R 0 ADD C.X:<ea_m> 0 15 1 1 0 12 0 11 0 v v 8 F 7 v J J 4 0 3 m 0 v 0 ADD 0 15 0 0 0 12 0 11 G G G 8 F 7 0 0 0 4 0 3 m R R 0 ADD ~F.GGG 0 15 0 1 0 12 0 11 G G G 8 F 7 J J J 4 0 3 m R R 0 ADD DD.

The result is not affected by the state of the saturation bit (SA). Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is unnormalized Set if bit 7 of the result is set Set if the result equals zero Set if overflow has occurred in the result Set if a carry occurs from bit 7 of the result Instruction Fields: Operation ADD. Explanation of Example: Prior to execution. The condition codes are calculated based on the 8-bit result.EEE C 2 W 2 Comments Add 9-bit signed immediate Instruction Opcodes: 15 12 11 8 7 4 3 0 ADD. which are calculated based on the 20-bit result. Usage: Example: ADD. the 36-bit A accumulator contains the value $0:3122:1234.EEE 0 1 0 0 0 1 E E E 1 0 0 0 0 1 0 iiiiiiiiiiiiiiii Timing: Memory: 2 oscillator clock cycle 2 program word A-16 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The 8-bit result ($77) is stored back into the low-order 8 bits of A1.A .B Operation: S+D→ D Add Byte (Word Pointer) Assembler Syntax: (no parallel move) ADD. If the destination is a 16-bit register. add hex 55 to A accumulator After Execution 1234 A0 SR 0300 0 A2 3177 A1 SR 1234 A0 0310 Before Execution 0 A2 3122 A1 This instruction can be used for both integer and fractional two’s-complement data.B #$55.B #xxx. The value is internally sign extended to 20 bits before the operation. The immediate integer is used to represent 8-bit unsigned values from 0 to 255 as well as the signed range: –128 to 127. it is first correctly sign extended before the 20-bit addition is performed.D ADD.B instruction automatically sign extends the immediate value to 20 bits and then adds the result to the A2:A1 portion of the A accumulator.B (no parallel move) Description: Add a 9-bit signed immediate integer to the 8-bit portion of the destination register. and store the result in the destination (D). with the exception of the E and U bits.ADD.B Operands #xxx. The ADD.B S.

Usage: Example: ADD. with the exception of the E and U bits. The value is internally sign extended to 20 bits before the operation. If the destination is a 16-bit register.D ADD.A Before Execution 0 A2 3122 A1 1234 A0 FF55 . add byte at word address $2000 . the 36-bit A accumulator contains the value $0:3122:1234.BP X:$4000. (word address) X:$2000 SR 0300 SR 0310 Explanation of Example: Prior to execution.BP (no parallel move) (no parallel move) Description: Add a byte stored in memory to the 8-bit portion of the destination register. The condition codes are calculated based on the 8-bit result. Absolute addresses are expressed as byte addresses. which are calculated based on the 20-bit result.BP S.BP instruction automatically sign extends the memory byte to 20 bits and then adds the result to the A2:A1 portion of the A accumulator. The 8-bit result ($77) is stored back into the low-order 8 bits of A1. The ADD.ADD. to A accumulator After Execution 0 A2 3177 A1 X:$2000 1234 A0 FF55 This instruction can be used for both integer and fractional two’s-complement data. and store the result in the destination (D). Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is unnormalized Set if bit 7 of the result is set Set if the result equals zero Set if overflow has occurred in the result Set if a carry occurs from bit 7 of the result Freescale Semiconductor Instruction Set Details A-17 . The result is not affected by the state of the saturation bit (SA). it is first correctly sign extended before the 20-bit addition is performed.BP Operation: S+D→ D Add Byte (Byte Pointer) Assembler Syntax: ADD.

address is expressed as byte address Instruction Opcodes: 15 12 11 8 7 4 3 0 ADD.BP X:xxxxxx.EEE 1 0 1 1 1 0 0 0 0 0 A 1 A E A E 0 E A 1 1 0 1 0 A 0 A 1 A 1 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 2–3 oscillator clock cycles 2–3 program words A-18 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .EEE 0 1 0 0 0 1 E E E 1 0 0 0 1 1 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADD.BP Comments Add memory byte to register.BP Instruction Fields: Operation ADD.BP Add Byte (Byte Pointer) Operands X:xxxx.BP X:xxxx.EEE C 2 3 W 2 3 ADD.EEE X:xxxxxx.ADD.

Usage: Example: ADD. Before Execution 0 A2 6666 A1 X:$4001 X:$4000 SR Explanation of Example: Prior to execution. The ADD.L S.D ADD. with the exception of the E and U bits. to A accumulator After Execution 1111 A0 2222 1111 0300 0 A2 8888 A1 X:$4001 X:$4000 SR 2222 A0 2222 1111 032A This instruction can be used for both integer and fractional two’s-complement data. add long value at word address $4001:4000 .A .L Operation: S+D→ D (no parallel move) Add Long Assembler Syntax: ADD. Absolute addresses pointing to long elements must always be even aligned (that is. and store the result in the destination (D).L (no parallel move) Description: Add a long-word value in memory or a 16-bit signed immediate value to the second operand.L instruction automatically sign extends the long value at address X:$4001:4000 to 36 bits and adds the result to the A accumulator. the 36-bit A accumulator contains the value $0:6666:1111. Condition codes are calculated based on the 32-bit result.ADD. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extended portion of the 36-bit result is in use Set if the 36-bit result is unnormalized Set if bit 31 of the result is set Set if bits 31–0 of the result are zero Set if overflow has occurred in the result Set if a carry occurs from bit 31 of the result Freescale Semiconductor Instruction Set Details A-19 . Source values are internally sign extended to 36 bits before the addition. which are calculated based on the 36-bit result for accumulator destinations. pointing to the lowest 16 bits).L X:$4000. The 32-bit result ($8888:2222) is stored back into the accumulator.

ADD.L Instruction Fields: Operation ADD.L Operands X:xxxx.L #xxxx.fff 0 1 0 0 0 1 f f f 1 0 0 0 1 1 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADD.L X:xxxxxx.fff Add Long C 2 3 2 W 2 3 2 Comments Add memory long to register ADD.fff 0 1 0 0 0 1 f f f 1 0 0 0 0 1 1 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 ADD.L Add a 16-bit immediate value sign extended to 32 bits to a data register Instruction Opcodes: 15 12 11 8 7 4 3 0 ADD.L X:xxxx.fff #xxxx.fff X:xxxxxx.fff 1 0 1 1 1 0 0 0 0 0 A 1 A f A f 0 f A 1 1 0 1 0 A 0 A 1 A 1 A 1 AAAAAAAAAAAAAAAA Timing: Memory: 2–3 oscillator clock cycles 2–3 program words A-20 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

Condition codes are calculated based on the size of the destination. and store the result in the destination (D).D ADD.W (no parallel move) Description: Add the source operand to the second operand (register or memory). The ADD.W Operation: S+D→ D (no parallel move) Add Word Assembler Syntax: ADD.ADD. The addition is then performed as a 20-bit operation. The source operand (except for a short immediate operand) is first sign extended internally to form a 20-bit value. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L E U N Z V C — — — — — — — Set if overflow has occurred in the result Set if the extended portion of the 20-bit result is in use Set if the 20-bit result is unnormalized Set if the high-order bit of the result is set Set if the result equals zero (accumulator bits 35–0 or bits 15–0 of a 16-bit register) Set if overflow has occurred in the result Set if a carry occurs from the high-order bit of the result Freescale Semiconductor Instruction Set Details A-21 .A . this value is concatenated with 16 zero bits to form a 36-bit value when the destination is one of the four accumulators.W instruction automatically sign extends the immediate value to 20 bits and adds the result to accumulator A.W #3. A short immediate (0–31) source operand is zero extended before the addition. The result is stored back in A. the 36-bit A accumulator contains the value $0:0058:1234. Before Execution 0 A2 0058 A1 Explanation of Example: Prior to execution. Usage: Example: ADD.W S. add decimal 3 to A After Execution 1234 A0 SR 0300 0 A2 005B A1 SR 1234 A0 0310 This instruction can be used for both integer and fractional two’s-complement data.

EEE X:xxxx.EEE #xxxx.X:xxxx #<0–31>. storing the result back to memory Add an immediate integer 0–31 (zero extended) Add a signed 16-bit immediate A-22 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W Operands X:(Rn).EEE Add Word C 2 3 3 2 3 4 3 1 2 W 1 2 1 2 3 2 2 1 2 Comments Add memory word to register ADD.W Add register to memory word.EEE X:xxxxxx.EEE X:(Rn+xxxx).W Instruction Fields: Operation ADD.ADD.EEE X:(SP–xx).X:(SP–xx) EEE.EEE EEE.

EEE 1 0 1 1 1 0 0 0 0 0 A 1 A E A E 0 E A 1 1 0 1 0 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 1–4 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-23 .W X:(SP–xx).W X:xxxxxx.W X:xxxx.W #<0–31>.W EEE.EEE 0 1 0 0 0 1 E E E 1 0 1 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADD.X:(SP–xx) 0 1 0 0 0 0 E E E 1 a a a a a a $E702 15 12 11 8 7 4 3 0 ADD.W X:(Rn).EEE 0 1 0 0 0 1 E E E 1 0 0 0 1 0 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADD.EEE 0 15 1 0 0 12 0 11 0 E E 8 E 7 1 a a 4 a 3 a a a 0 ADD.ADD.EEE 0 1 0 0 0 1 E E E 1 0 0 0 0 0 0 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 ADD.W #xxxx.W Instruction Opcodes: 15 Add Word ADD.EEE 0 15 1 0 0 12 0 11 1 E E 8 E 7 0 0 B 4 B 3 B B B 0 ADD.W 8 7 4 3 0 12 11 ADD.W EEE.X:xxxx 0 1 1 1 0 1 E E E 1 0 1 0 1 1 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADD.EEE 0 15 1 0 0 12 0 11 1 E E 8 E 7 1 0 1 4 R 3 1 R R 0 ADD.W X:(Rn+xxxx).

4.N #<0–15>. and store the result in the second AGU register. and the result is stored in address register R1.Rn #xxxxxx. Condition Codes Affected: The condition codes are not affected by this instruction Instruction Fields: Operation ADDA Operands Rn.Rn.Rn #xxxxxx.Rn #xxxxxx. while R1 initially contains $17C624. add hex 254 to R0 and store the result in R1 After Execution R0 005000 Before Execution R0 005000 R1 17C624 R1 005254 Explanation of Example: The address pointer register R0 initially contains $005000. Add an unsigned 4-bit value to an AGU register and store result in the N register. Refer to Section 6. HHH is accessed as a signed 16-bit word. Immediate values that are less than 24 bits in length are either sign extended or zero extended to 24 bits before the addition takes place. HHH is accessed as a signed 16-bit word. Add a data register with an unsigned 16-bit value and store the result in Rn.N #xxxx. Add unsigned 4-bit value to Rn.Rn #xxxx.D (no parallel move) S1.Rn C 1 1 1 1 2 2 3 3 4 5 W 1 1 1 1 2 2 3 3 2 3 Comments Add first operand to the second and store the result in the second operand.ADDA Operation: S+D→D S1 + S2 → D (no parallel move) (no parallel move) Add AGU Register Assembler Syntax: ADDA ADDA S.D (no parallel move) ADDA Description: Add an AGU register or immediate value to an AGU register or a data ALU register. Add first register with a signed 17-bit immediate value and store the result in Rn.8. A-24 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .R0. The addition is performed using 24-bit two’s-complement arithmetic.Rn #xxxx.Rn.R1 .R0. Example: ADDA #$254. Add first register with a 24-bit immediate value and store the result in Rn.Rn” in Modulo Addressing. or the N register.S2.Rn #<0–15>.Rn. An alternate syntax for the preceding instruction if the second source and the destination are the same. the immediate hexadecimal value 254 is added to the value in R0.R1 instruction is executed. a separate address pointer register.3 on page 6-28 when using “ADDA #<immediate_value>. Add a data register with a 24-bit immediate value and store the result in Rn.HHH. Add first operand to the second and store result in the N register. An alternate syntax for the preceding instruction if the second source and the destination are the same. When the ADDA #$254.Rn Rn.HHH.Rn.

Rn.Rn.Rn Add AGU Register ADDA 8 7 4 3 0 15 12 11 1 15 0 0 0 12 i 11 i i i 8 0 7 1 1 1 4 R 3 0 R R 0 ADDA #<0–15>.ADDA Instruction Opcodes: ADDA #<0–15>.Rn 1 0 0 0 V 0 1 0 n 0 1 n R n R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA #xxxxxx.8. Freescale Semiconductor Instruction Set Details A-25 .N 1 15 0 0 0 12 i 11 i i i 8 0 7 1 1 1 4 R 3 1 R R 0 ADDA #xxxx.Rn 1 1 1 0 1 0 0 0 0 0 A 1 A 1 A 0 0 h A 0 1 1 1 h A R A h A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA #xxxxxx.3 on page 6-28 when ADDA is used in Modulo Arithmetic.HHH.Rn.HHH.Rn 1 1 1 0 1 0 0 0 0 0 A 0 A 1 A 0 0 n A 0 1 1 1 n A R A n A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA Rn.4.Rn 1 0 0 0 0 1 1 0 h 0 1 h R h R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA #xxxx.Rn 1 15 0 0 0 12 1 11 0 0 1 8 n 7 0 1 n 4 R 3 n R R 0 ADDA Rn.N 1 0 0 0 1 1 0 1 n 0 1 n R n R R Timing: Memory: Note: 1–5 oscillator clock cycle(s) 1–3 program word(s) Refer to Section 6.Rn.

Usage: The ADDA. When the ADDA.L instruction can accomplish this in one step. The immediate value $4000 is then added to the shifted value. and add it either to the destination or to the other source operand (S1).R1 .L #$4000. The ADDA.D (no parallel move) Description: Left shift one of the source operands by one (S or S2).L instruction is most useful for accessing arrays of long words in memory.L ADDA.R1 instruction is executed.R0. resulting in the intermediate value $000088.ADDA.L Operation: Add to Left-Shifted AGU Register Assembler Syntax: ADDA.L ADDA.S2.R0.D (no parallel move) S1. R0 is internally shifted 1 bit to the left. add $4000 to left-shifted R0 and store the . The address of an element in the array is calculated by adding the base address to the index value multiplied by 2 (since long words occupy 2 words in memory). while R1 initially contains $000624. Condition Codes Affected: The condition codes are not affected by this instruction. A-26 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L #$4000. and the result ($004088) is stored in address register R1. result in R1 After Execution R0 000044 Before Execution R0 000044 R1 000624 R1 004088 Explanation of Example: The address pointer register R0 initially contains $000044. Example: ADDA.L (S << 1) + D → D (no parallel move) S1 + (S2 << 1) → D (no parallel move) S. Store the result in the destination AGU register (D).

left shifted 1 bit.ADDA. to the second.Rn 1 15 0 0 0 12 1 11 0 0 0 8 n 7 0 1 n 4 R 3 n R R 0 ADDA.N 1 0 0 0 1 1 0 0 n 0 1 n R n R R Timing: Memory: 1–5 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-27 .L Instruction Fields: Operation ADDA. and store the result in Rn. and store the result in Rn An alternate syntax for the preceding instruction if the second source and the destination are the same Add first register.L #xxxxxx. left shifted 1 bit. with a 24-bit immediate value.Rn #xxxxxx.L #xxxxxx. left shifted 1 bit.Rn #xxxxxx. left shifted 1 bit.L Rn.Rn #xxxx.L Operands Add first operand.Rn. HHH is accessed as 16-bit signed Rn. and store result in the N register Add first register.Rn. with an unsigned 16-bit immediate value. with unsigned 16-bit immediate value.L Rn.Rn.Rn #xxxx. left shifted 1 bit.Rn 1 0 0 0 0 0 1 1 n 0 1 n R n R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA.Rn Instruction Opcodes: 15 12 11 8 7 4 3 0 ADDA. and store the result in the second operand Add first operand.N #xxxx.L #xxxx.HHH.Rn.Rn 1 0 0 0 0 1 1 1 h 0 1 h R h R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA. with a 24-bit immediate value. left shifted 1 bit.Rn Add to Left-Shifted AGU Register C 1 1 2 2 3 3 4 5 W 1 1 2 2 3 3 2 3 Comments ADDA.HHH.Rn #xxxxxx. store result in Rn.L Rn.Rn 1 1 1 0 1 0 0 0 0 0 A 0 A 1 A 1 0 n A 0 1 1 1 n A R A n A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA. HHH is accessed as 16-bit signed Add data register. to the second. and store the result in Rn An alternate syntax for the preceding instruction if the second source and the destination are the same Add data register.Rn 1 1 1 0 1 0 0 0 0 0 A 1 A 1 A 1 0 h A 0 1 1 1 h A R A h A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 ADDA.L #xxxx.Rn.HHH.HHH.Rn.

push long word on stack After Execution X:$1007 X:$1006 X:$1005 Before Execution SP ‘Y1’ ‘Y0’ 0000 1001 5499 0000 X:$1004 X:$1003 X:$1001 X:$1000 5499 0000 SP X:$1002 X:$1001 X:$1000 Explanation of Example: The SP register initially has a value of $001001. ALIGNSP MOVE. The MOVE.L Y. it is only incremented by two. After ALIGNSP is executed. The value of the SP previous to the alignment adjustment is placed on the stack (as a long word) so the stack can be restored to its original state.L instruction adds two to the SP (for the post-increment) after pushing register Y onto the stack. Since the initial value of SP is odd. setting the final SP value to $001007.X:(SP)+ . and SP is updated. The ALIGNSP instruction guarantees that the SP points to an odd word address and that at least 2 words are available to receive the long-word value. the original value is pushed onto the stack. align the stack for a long word . the SP has a new value of $001005.ALIGNSP Operation: If SP is odd: SP + 2 → SP else if SP is even: SP + 3 → SP SP → X:(SP) SP + 2 → SP Align Stack Pointer Assembler Syntax: ALIGNSP ALIGNSP(no parallel move) Description: The ALIGNSP instruction aligns the stack pointer register (SP) correctly for a long-word value to be pushed onto the stack. The SP should point to the (odd) upper word address of the long word in order for it to be pushed and popped properly. pointing to an empty location Instruction Opcodes: 15 12 11 8 7 4 3 0 ALIGNSP 1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 Timing: Memory: 3 oscillator clock cycles 1 program word A-28 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Instruction Fields: Operation ALIGNSP Operands C 3 W 1 Comments Save SP to the stack and align SP for long memory accesses. Condition Codes Affected: The condition codes are not affected by this instruction. Usage: Example: ALIGNSP should be used to align the stack prior to pushing a long-word value.

and store the result in the destination.L Operation: S•D→D (no parallel move) where • denotes the logical AND operator AND Long Assembler Syntax: AND.A . Usage: This instruction is used for the logical AND of two registers or of a register and a small immediate value.A instruction performs a logical AND operation on the 32-bit value in the Y register and on bits 31–0 of the A accumulator (A10). If the source is a 16-bit register. bits 35–32 remain unchanged. The remaining bits of the destination accumulator are not affected. and it stores the 36-bit result in the A accumulator. The result is not affected by the state of the saturation bit (SA). the 32-bit Y register contains the value $7F00:00FF. and the 36-bit A accumulator contains the value $6:1234:5678. the AND operation is performed on the source and bits 31–0 of the accumulator. If the destination is a 36-bit accumulator. Example: AND.L S. The ANDC instruction is appropriate for performing an AND operation on a 16-bit immediate value and a register or memory location. it is first zero extended to form a 32-bit operand. The AND. it is first internally concatenated with 16 zero bits to form a 32-bit operand.AND. If the source is an immediate 5-bit constant.D AND. logically AND Y with A10 After Execution 5678 A0 00FF Y0 SR 0302 6 A2 1200 A1 7F00 Y1 SR 0078 A0 00FF Y0 0300 Before Execution 6 A2 1234 A1 7F00 Y1 Explanation of Example: Prior to execution. This instruction is a 32-bit operation.L (no parallel move) Description: Perform a logical AND operation on the source operand and the destination operand.L Y. Bits 35–32 in the A2 register are not affected by this instruction.L Y. When the destination is an accumulator. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V — Set if bit 31 of accumulator or register result is set — Set if bits 31–0 of accumulator or register result are zero — Always cleared Freescale Semiconductor Instruction Set Details A-29 .

fff AND Long C 1 1 W 1 1 Comments AND.fff 0 15 1 0 0 12 0 11 1 f f 8 f 7 1 1 B 4 B 3 B B B 0 AND.L #<0–31>.fff FFF.fff 0 1 1 1 1 0 f f f b b b 1 1 0 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-30 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L AND with a zero-extended 5-bit positive immediate integer (0–31) 32-bit logical AND Instruction Opcodes: 15 12 11 8 7 4 3 0 AND.L Operands #<0–31>.AND.L FFF.L Instruction Fields: Operation AND.

A instruction performs a logical AND operation on the 16-bit value in the X0 register and on bits 31–16 of the A accumulator (A1). If the destination is a 36-bit accumulator. and the 36-bit A accumulator contains the value $6:1234:5678.W X0.W Operation: S•D→D S • D[31:16] → D[31:16] where • denotes the logical AND operator AND Word Assembler Syntax: (no parallel move) (no parallel move) AND. The remaining bits of the destination accumulator are not affected.W S.W AND. Example: AND. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V — Set if bit 31 of accumulator result or MSB of register result is set — Set if bits 31–16 of accumulator result or all bits of register result are zero — Always cleared Freescale Semiconductor Instruction Set Details A-31 . If the source is an immediate 5-bit constant.D S. the 16-bit X0 register contains the value $7F00. Usage: This instruction is used for the logical AND of two registers or of a register and a small immediate value. the operation is performed on the source and bits 31–16 of the accumulator.D AND. The ANDC instruction is appropriate for performing an AND operation on a 16-bit immediate value and a register or memory location. it is first zero extended to form a 32-bit operand. and store the result in the destination. The AND.W X0.W (no parallel move) (no parallel move) Description: Perform a logical AND operation on the source operand (S) and the destination operand (D). The result is not affected by the state of the saturation bit (SA). Bits 35–32 in the A2 register and bits 15–0 in the A0 register are not affected by this instruction. and it stores the 36-bit result in the A accumulator.A .AND. logically AND X0 with A1 After Execution 5678 A0 6 A2 X0 SR 030F 1200 A1 7F00 SR 0301 5678 A0 Before Execution 6 A2 X0 1234 A1 7F00 Explanation of Example: Prior to execution. This instruction is a 16-bit operation.

EEE 0 15 1 0 1 12 0 11 1 E E 8 E 7 1 1 B 4 B 3 B B B 0 AND.EEE EEE.AND.W Operands #<0–31>.W #<0–31>.EEE 0 1 1 1 1 0 E E E a a a 1 0 0 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-32 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W EEE.W Instruction Fields: Operation AND.EEE AND Word C 1 1 W 1 1 Comments AND.W AND with a zero-extended 5-bit positive immediate integer (0–31) 16-bit logical AND Instruction Opcodes: 15 12 11 8 7 4 3 0 AND.

” This instruction performs a read-modify-write operation on the destination and requires two destination accesses. Freescale Semiconductor Instruction Set Details A-33 . $FFFF) and the mask value $0055 and stores the result in X:$5000. Instruction Fields: Refer to the section on the BFCLR instruction for legal operand and timing information. The C bit is set because all of the bits selected by the inverted value of the mask are set.X:$5000 . and store the results back into the destination. AND with immediate data After Execution X:$5000 SR 0055 0301 Before Execution X:$5000 SR FFFF 0300 Explanation of Example: Prior to execution.ANDC Operation: Logical AND Immediate Assembler Syntax: ANDC ANDC ANDC #xxxx • D → D (no parallel move) #xxxx • X:<ea> → X:<ea> (no parallel move) where • denotes the logical AND operator #iiii. It will dis-assemble as a BFCLR instruction. Description: Perform a logical AND operation on a 16-bit immediate data value with the destination operand. Execution of the instruction performs a logical AND operation on the 16-bit value in X:$5000 (that is. with the 16-bit immediate value inverted (one’s-complement) and used as the bit mask. the instruction executes two NOPs and sets the C bit. the C bit is not updated as is done for all other destination operands. Bits 14–10 of the mask operand must be set. the 16-bit X memory location X:$5000 contains the value $FFFF. C is also modified as described in “Condition Codes Affected. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: For this destination only.D (no parallel move) #iiii. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the one’s-complement of the mask are set Cleared if at least 1 bit specified by the one’s-complement of the mask is not set Note: If all bits in the mask are set. All SR bits except bits 14–10 are updated with values from the bitfield unit.X:<ea>(no parallel move) Implementation Note: This instruction is implemented by the assembler as an alias to the BFCLR instruction. Example: ANDC #$0055.

update R3 and Y0 After Execution 0222 A0 SR 0300 4 A2 0222 A1 SR 0444 A0 0373 This instruction can be used to cast a long to an integer value. A duplicate destination is not allowed when ASL is used in conjunction with a parallel read. and a zero is shifted into the LSB of the destination. Before Execution A A2 0111 A1 Explanation of Example: Prior to execution. the E bit of CCR (bit 5) is set because the extension portion of the result is in use. and the L bit of CCR (bit 6) is set because an overflow has occurred. refer to ASL. The MSB of the destination prior to the execution of the instruction is shifted into C. the 36-bit A accumulator contains the value $A:0111:0222. The U bit of CCR (bit 4) is set because the result is not normalized. If the destination is the Y register. For arithmetic shifts left on 16-bit registers.W. shift A left by 1. Usage: Example: ASL A X:(R3)+N. and store the result in the destination.Y0. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V C — — — — — — — — Set according to the standard definition of SZ (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extension portion of accumulator result is in use Set according to the standard definition of the U bit Set if bit 35 of accumulator result is set Set if accumulator result equals zero Set if bit 35 of accumulator result is changed due to left shift Set if bit 35 of accumulator was set prior to the execution of the instruction A-34 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The V bit of CCR (bit 1) is also set because bit 35 of A has changed during the execution of the instruction.ASL Operation: (see following figure) Arithmetic Shift Left Assembler Syntax: ASL ASL ASL D D D 0 D2 D1 D0 (no parallel move) (one parallel move) (two parallel reads) ASL : C Description: Arithmetically shift the destination operand (D) 1 bit to the left. C is set by the operation because bit 35 of A was set prior to the execution of the instruction. the MSB is bit 31. Execution of the ASL instruction shifts the 36-bit value in the A accumulator 1 bit to the left and stores the result back in the A accumulator. A new value for register Y0 is read and address register R3 is updated by the contents on index register N.

The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed. ASL Parallel Moves: Data ALU Operation Operation ASL2 Operands F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1. Memory writes are allowed in this case.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.ASL Instruction Fields: Operation ASL Operands fff Arithmetic Shift Left C 1 W 1 Comments Arithmetic shift left entire register by 1 bit. Freescale Semiconductor Instruction Set Details A-35 . 2.

when the instructions are executing from data memory).reg2 fff 0 15 1 1 1 12 0 11 1 v v 8 F 7 v 1 1 4 0 3 m 0 v 0 ASL 0 1 1 1 0 0 f f f 1 1 0 0 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word A-36 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .GGG 0 15 0 1 1 12 0 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 ASL F X:<ea_m>.ASL Parallel Dual Reads: Data ALU Operation1 Operation ASL2 Operands F Arithmetic Shift Left ASL Second Memory Read Source 2 X:(R3)+ X:(R3)– Destination 2 X0 First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Y0 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 Y1 C 1.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. 2.X:<ea_m> 0 15 0 0 1 12 0 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 ASL F X:<ea_m>. Instruction Opcodes: 15 12 11 8 7 4 3 0 ASL F GGG.This instruction is not allowed when the XP bit in the OMR is set (that is.reg1 X:<ea_v>.

refer to ASL.W 15 0 ASL. Y0. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L E U N Z V C — — — — — — — Set if overflow has occurred in result Set if the extension portion of the result is in use Set according to the standard definition of the U bit Set if bit 15 of result is set Set if the result equals zero Set if bit 15 of result is changed due to left shift Set if bit 15 of was set prior to the execution of the instruction Freescale Semiconductor Instruction Set Details A-37 . is shifted into C. the 16-bit register is first sign extended and concatenated to 16 zero bits to form a 36-bit operand.ASL. For arithmetic shifts left on the Y register or accumulator. the 16-bit Y0 register contains the value $C000. and store the result in the destination register. C is set by the operation because bit 15 of Y0 was set prior to the execution of the instruction. For the purpose of calculating condition code.W Y0 . This instruction is used only when the destination is X0.W (no parallel move) D 0 C Description: Arithmetically shift the destination operand (D) 1 bit to the left. or Y1 register. bit 15 of the destination prior to the execution of the instruction. shift Y0 left by 1 After Execution C000 Y0 SR 0300 2000 Y1 SR 8000 Y0 0309 Before Execution 2000 Y1 Explanation of Example: Prior to execution. Example: ASL. Execution of the ASL. The MSB. The N bit is set because the MSB of the result is set.W Operation: (see following figure) : Arithmetic Shift Left Assembler Syntax: ASL.W instruction shifts the 16-bit value in Y0 by 1 bit to the left and stores the result back in Y0. and a zero is shifted into the LSB of the destination.

W Arithmetic shift left entire register by 1 bit Instruction Opcodes: 15 12 11 8 7 4 3 0 ASL.W Instruction Fields: Operation ASL.ASL.W DD 0 1 1 1 0 0 1 D D 1 1 0 0 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word A-38 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W Operands DD Arithmetic Shift Left C 1 W 1 Comments ASL.

the Y register contains the value to be shifted ($0000:7FFF). This operation effectively places the LSP of the source register into the MSP of the destination register. When the destination operand is a 16-bit register. The result is not affected by the state of the saturation bit (SA). Bits are shifted into the extension register (FF2) if the destination is an accumulator. the destination is cleared. and store the result in the destination (D). store in A After Execution 3456 A0 7FFF Y0 0 A2 7FFF A1 0000 Y1 0000 A0 7FFF Y0 Before Execution 0 A2 3456 A1 0000 Y1 Explanation of Example: Prior to execution. When both the source and destination are 16-bit registers.A . Example: ASL16 Y. The contents of the destination register are not important prior to execution because they have no effect on the calculated value. Instruction Fields: Operation ASL16 Operands FFF.D ASL16 (no parallel move) Description: Arithmetically shift the source operand to the left by 16 bits. the LSP of an accumulator or Y register is written to it.ASL16 Operation: S << 16 → D Arithmetic Shift Left 16 Bits Assembler Syntax: (no parallel move) ASL16 S.FFF FFF C 1 1 W 1 1 Comments Arithmetic shift left the first operand by 16 bits. The ASL16 instruction arithmetically shifts the value $0000:7FFF by 16 bits to the left and places the result in the destination register A. The low-order 16 bits of the destination are always set to zero. placing result in the destination operand An alternate syntax for the preceding instruction if the source and the destination are the same Instruction Opcodes: 15 12 11 8 7 4 3 0 ASL16 FFF. Condition Codes Affected: The condition codes are not affected by this instruction.FFF 0 1 1 1 1 1 F F F b b b 0 1 0 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-39 . shift Y left 16 bits.

Rn 1 0 0 0 0 0 0 0 n 0 1 n R n R R Timing: Memory: 1 oscillator clock cycle 1 program word A-40 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . and the R0 register contains $00B360.D ASLA (no parallel move) Description: Arithmetically shift the source address register 1 bit to the left. Example: ASLA R1. Condition Codes Affected: The condition codes are not affected by this instruction.ASLA Operation: S << 1 → D 1-Bit Left Shift AGU Register Assembler Syntax: (no parallel move) ASLA S. shift R1 left 1 bit and store in R0 After Execution R0 008888 Before Execution R0 00B360 R1 004444 R1 004444 Explanation of Example: Prior to execution. Instruction Fields: Operation ASLA Operands Rn.R0 .Rn Rn C 1 1 W 1 1 Comments Arithmetic shift left AGU register by 1 bit An alternate syntax for the preceding instruction if the source and the destination are the same Instruction Opcodes: 15 12 11 8 7 4 3 0 ASLA Rn. Execution of the ASLA instruction shifts the value in R1 by 1 bit to the left and stores the result ($008888) in the R0 register. and store the result in the destination register. the R1 register contains the value $004444.

A Before Execution 0 A2 0123 A1 2000 Y1 SR 4567 A0 0024 Y0 0300 . the A accumulator contains the value to be shifted ($0123:4567). or the MSP of an accumulator. the extension word (A2) is filled with sign extension.ASLL. For 36. Since the destination is an accumulator. maintaining sign integrity.L instruction arithmetically shifts the value $0123:4567 by 4 bits to the left and places the result in the destination register A. Store the result back in the destination (D) with zeros shifted into the LSB. If the shift count in a register is negative (bit 15 is set).D S. the MSP:LSP are shifted with sign extension from bit 31 (the FF2 portion is ignored). and the Y0 register contains the amount by which to shift ($04). Example: ASLL. Y0. The result is not affected by the state of the saturation bit (SA).L (no parallel move) (no parallel move) If S[15] = 0 or S is not a register. the direction of the shift is reversed.L S. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z — Set if MSB of result is set — Set if result equals zero Freescale Semiconductor Instruction Set Details A-41 .L ASLL.and 32-bit destinations. The shift count can be a 5-bit positive immediate integer or the value contained in X0.D ASLL. The ASLL. shift A left by amount in Y0 and store in A After Execution 0 A2 1234 A1 2000 Y1 SR 5670 A0 0024 Y0 0300 Explanation of Example: Prior to execution. D << S → D (no parallel move) Else D >> –S → D (no parallel move) Description: Arithmetically shift the second operand to the left by the value contained in the 5 lowest bits of the first operand (or by an immediate integer).L Operation: Multi-Bit Arithmetic Left Shift Long Assembler Syntax: ASLL.L Y0. Y1.

FFF 0 1 1 1 1 1 F F F a a a 1 1 1 0 Timing: Memory: 2 oscillator clock cycles 1 program word A-42 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .ASLL.FFF C 2 2 W 1 1 Comments ASLL.fff EEE.L Arithmetic shift left by a 5-bit positive immediate integer Bi-directional arithmetic shift of destination by value in the first operand: positive –> left shift Instruction Opcodes: 15 12 11 8 7 4 3 0 ASLL.fff 0 15 1 0 0 12 0 11 1 f f 8 f 7 0 1 B 4 B 3 B B B 0 ASLL.L Instruction Fields: Operation ASLL.L #<0–31>.L EEE.L Multi-Bit Arithmetic Left Shift Long Operands #<0–31>.

W Operation: S1 << S2 → D D << S → D Multi-Bit Arithmetic Left Shift Word Assembler Syntax: ASLL.W instruction arithmetically shifts the value $AAAA by 4 bits to the left and places the result in the destination register A. The ASLL. Since the destination is an accumulator.W ASLL. or the MSP of an accumulator. The contents of the destination register are not important prior to execution because they have no effect on the calculated value. and the least significant 4 bits of the X0 register contain the amount by which to shift ($4). respectively (or by an immediate integer). the Y1 register contains the value to be shifted ($AAAA). shift Y1 left by amount in X0 and store in A After Execution F A2 AAA0 A1 AAAA Y1 X0 SR 0000 A0 8000 Y0 0014 0308 Explanation of Example: Prior to execution.X0. N is cleared. Example: ASLL.D S. Freescale Semiconductor Instruction Set Details A-43 .D ASLL. the extension word (A2) is filled with sign extension. For 36. and the LSP (A0) is cleared.A Before Execution 0 A2 3456 A1 AAAA Y1 X0 SR 3456 A0 8000 Y0 0014 0300 .W Y1. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z Note: — Set if MSB of result is set — Set if result equals zero If the CM bit is set. a value in a 16-bit register. When the destination is a 16-bit register.and 32-bit destinations.ASLL. The result is not affected by the state of the saturation bit (SA). and stores the result in the destination (D) with zeros shifted into the LSB. only the MSP is shifted and the LSP is cleared.W (no parallel move) (no parallel move) (no parallel move) (no parallel move) Description: This instruction can have two or three operands. condition codes are based on the 16-bit result. The shift count can be a 4-bit positive integer.S2. It arithmetically shifts the source operand S1 or D to the left by the value contained in the lowest 4 bits of either S2 or S.W S1. with sign extension from bit 31 (the FF2 portion is ignored).

FFF C 1 1 1 W 1 1 1 ASLL.FFF 0 15 1 1 1 12 1 11 1 F F 8 F 7 a a a 4 1 3 0 1 0 0 ASLL.W #<0–15>.FFF Y1. place result in FFF Instruction Opcodes: 15 12 11 8 7 4 3 0 ASLL.FFF A1.Y1.FFF B1.FFF Y1.X0.FFF Y0.FFF 0 15 1 0 1 12 1 11 1 F F 8 F 7 1 1 1 4 B 3 B B B 0 ASLL.W Q1.Y0.Q2.ASLL.FFF C1.FFF C1.W Instruction Fields: Operation ASLL.Y0.FFF EEE.W Multi-Bit Arithmetic Left Shift Word Operands #<0–15>.W EEE.X0.FFF 0 1 1 1 0 0 F F F Q Q Q 1 1 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-44 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Y0.W Comments Arithmetic shift left by a 4-bit positive immediate integer Arithmetic shift left destination by value specified in 4 LSBs of the first operand Arithmetic shift left the first operand by value specified in 4 LSBs of the second operand.Y0.Y1.FFF Y0.

ASR Operation: (see following figure) Arithmetic Shift Right Assembler Syntax: ASR ASR ASR D D D C MSB ASR (no parallel move) (one parallel move) (two parallel reads) (parallel move) D2 D1 D0 Description: Arithmetically shift the destination operand (D) 1 bit to the right and store the result in the destination accumulator. and update R3 After Execution AAAA B0 SR 0300 C B2 5555 B1 SR 5555 B0 0328 Before Execution 8 B2 AAAA B1 Explanation of Example: Prior to execution. The N bit of CCR (bit 3) is set because bit 35 of the result in A is set. C is cleared by the operation because bit 0 of A was cleared prior to the execution of the instruction.Y0. When the destination register is Y or a 16-bit register. The LSB of the destination prior to the execution of the instruction is shifted into C. Example: ASR B X:(R3)+. A duplicate destination is not allowed when ASR is used in conjunction with a parallel read. The E bit of CCR (bit 5) is set because the extension portion of B is used by the result. the 36-bit B accumulator contains the value $8:AAAA:AAAA. divide B by 2. the MSB is bit 31 or bit 15. Freescale Semiconductor Instruction Set Details A-45 . respectively. Execution of the ASR instruction shifts the 36-bit value in the B accumulator 1 bit to the right and stores the result back in the B accumulator. load Y0. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V C Note: — — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if data limiting has occurred during parallel move Set if the extension portion of result is in use Set according to the standard definition of the U bit Set if MSB of result is set Set if result equals zero Always cleared Set if bit 0 of source operand was set prior to the execution of the instruction Condition code results depend on the size of the destination operand. and the MSB of the destination is held constant.

ASR Parallel Moves: Data ALU Operation Operation ASR2 Operands F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed. A-46 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Memory writes are allowed in this case. 2.ASR Instruction Fields: Operation ASR FFF Arithmetic Shift Right Operands C 1 W 1 Comments Arithmetic shift right entire register by 1 bit.

GGG 0 15 0 1 1 12 1 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 ASR F X:<ea_m>.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. when the instructions are executing from data memory).X:<ea_m> 0 15 0 0 1 12 1 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 ASR F X:<ea_m>.reg1 X:<ea_v>. Instruction Opcodes: 15 12 11 8 7 4 3 0 ASR F GGG.This instruction is not allowed when the XP bit in the OMR is set (that is.reg2 0 15 1 1 1 12 0 11 1 v v 8 F 7 v 1 0 4 0 3 m 0 v 0 ASR FFF 0 1 1 1 0 0 F F F 1 1 0 1 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-47 . 2.ASR Parallel Dual Reads: Data ALU Operation1 Operation ASR2 Operands F Arithmetic Shift Right ASR Second Memory Read Source 2 X:(R3)+ X:(R3)– Destination 2 X0 First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Y0 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 Y1 C 1.

When the destination operand is a 16-bit register. shift sign bit in Y right by 16 bits and sign extend After Execution A1A0 Y0 0000 X0 A3A2 Y1 A1A0 Y0 FFFF X0 Before Execution A3A2 Y1 Explanation of Example: Prior to execution. Example 2: ASR16 Y. The contents of the destination register are not important prior to execution because they have no effect on the calculated value. The result is not affected by the state of the saturation bit (SA). If the source is a 16-bit register or the Y register. both the extension register and MSP are shifted. the ASR16 instruction arithmetically shifts the value of the sign bit by 16 bits to the right with sign extension. For example. Before Execution 0 A2 3456 A1 A1A2 Y1 Explanation of Example: Prior to execution.X0 . shift long in Y right by 16 bits and place in A After Execution 3456 A0 A3A4 Y0 F A2 FFFF A1 A1A2 Y1 A1A2 A0 A3A4 Y0 This instruction can be used to cast an integer to a long value. If the source is an accumulator. the sign information is written to it. and places the result in the destination register A. Usage: Example 1: ASR16 Y.D ASR16 (no parallel move) Description: Arithmetically shift the source operand to the right by 16 bits. The ASR16 instruction arithmetically shifts the value $A1A2:A3A4 by 16 bits to the right. the Y register contains the value to be shifted ($A3A2:A1A0). the 4 bits of the EXT are written to the lower 4 bits of the destination register with sign extension.A . A-48 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . sign extending to the left. Condition Codes Affected: The condition codes are not affected by this instruction. if the source is an accumulator. propagating the sign bit through the MSP (and the extension register for accumulator destinations). sign extends to a full 36 bits. the msb (sign bit) is written with sign extension.ASR16 Operation: S >> 16 → D Arithmetic Shift Right 16 Bits Assembler Syntax: (no parallel move) ASR16 S. and places the result in the destination register X0. This operation effectively places the MSP of the source register into the LSP of the destination register. and store the result in the destination (D). the Y register contains the value to be shifted ($A1A2:A3A4). Since the destination is a 16-bit register. The contents of the destination register are not important prior to execution because they have no effect on the calculated value.

FFF FFF C 1 1 W 1 1 Comments ASR16 Arithmetic shift right the first operand by 16 bits. An alternate syntax for the above instruction if the source and the destination are the same.ASR16 Instruction Fields: Operation ASR16 Arithmetic Shift Right 16 Bits Operands FFF.FFF 0 1 1 1 1 1 F F F b b b 0 1 1 0 Timing: 1 oscillator clock cycle 1 program word Memory: 1 program word Freescale Semiconductor Instruction Set Details A-49 . Instruction Opcodes: 15 12 11 8 7 4 3 0 ASR16 FFF. placing result in the destination operand.

and store the result back in the register. Instruction Fields: Operation ASRA Operands Rn C 1 W 1 Comments Arithmetic shift right AGU register by 1 bit Instruction Opcodes: 15 12 11 8 7 4 3 0 ASRA Rn 1 0 0 0 0 1 0 1 0 0 1 1 R 0 R R Timing: Memory: 1 oscillator clock cycle 1 program word A-50 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .ASRA Operation: D >> 1 → D 1-Bit Arithmetic Shift Right AGU Register Assembler Syntax: (no parallel move) ASRA D (no parallel move) ASRA Description: Arithmetically shift the address register operand 1 bit to the right. Execution of the ASRA instruction shifts the value in the R0 register 1 bit to the right and stores the result ($C059B0) back in R0. arithmetically shift R0 to the right 1 bit After Execution R0 C059B0 Before Execution R0 80B360 Explanation of Example: Prior to execution. Example: ASRA R0 . the R0 register contains $80B360. Condition Codes Affected: The condition codes are not affected by this instruction.

and accumulate the result with the value in the destination (D).S2.ASRAC Operation: Arithmetic Right Shift with Accumulate Assembler Syntax: ASRAC S1. the Y1 register contains the value that is to be shifted ($C003). Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z Note: — Set if bit 35 of accumulator result is set — Set if accumulator result equals zero If the SA bit is set. accumulate in A After Execution 0099 A0 8000 Y0 X0 SR 00F4 0300 F A2 FC00 A1 C003 Y1 X0 SR 3099 A0 8000 Y0 00F4 0308 This instruction is typically used for multi-precision arithmetic right shifts. The ASRAC instruction arithmetically shifts the value $C003 by 4 bits to the right and accumulates this result with the value that is already in the destination register A.D ASRAC (S1 >> S2) + D → D (no parallel move) (no parallel move) Description: Arithmetically shift the first 16-bit source operand (S1) to the right by the value contained in the lowest 4 bits of the second source operand (S2).A . and the destination accumulator contains $0:0000:0099.X0. the N bit is equal to bit 35 of the result. Operand S1 is internally sign extended and concatenated with 16 zero bits to form a 36-bit value before the shift operation. The result is not affected by the state of the saturation bit (SA). Freescale Semiconductor Instruction Set Details A-51 . the N bit is equal to bit 31 of the result. arithmetic right shift Y1 by 4 and . the X0 register contains the amount by which to shift ($4). If the SA bit is clear. Before Execution 0 A2 0000 A1 C003 Y1 Explanation of Example: Prior to execution. Usage: Example: ASRAC Y1.

FF Y1.FF 0 1 1 1 0 0 0 F F Q Q Q 0 1 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-52 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .FF B1.Y0.FF C 1 W 1 Comments ASRAC Arithmetic word shift with accumulation Instruction Opcodes: 15 12 11 8 7 4 3 0 ASRAC Q1.FF C1.FF C1.FF Y0.FF Y0.X0.Y1.Y0.Q2.Y0.Y0.FF A1.ASRAC Instruction Fields: Operation ASRAC Arithmetic Right Shift with Accumulate Operands Y1.X0.Y1.

Since the count is a negative number.L Y0. store result in A After Execution 0 A2 1234 A1 2000 Y1 SR 5670 A0 FFFC Y0 0300 Explanation of Example: Prior to execution. For 36.L ASRR.and 32-bit destinations. with sign extension from bit 31 (the FF2 portion is ignored).A Before Execution 0 A2 0123 A1 2000 Y1 SR 4567 A0 FFFC Y0 0300 . The ASRR. Freescale Semiconductor Instruction Set Details A-53 . and store the result back in the destination (D). the A accumulator contains the value that is to be shifted ($0123:4567). shift A right by the amount in Y0 and . or the MSP of an accumulator.D ASRR. and the Y0 register contains the amount by which to shift ($FFFC). If the shift count in a register is negative (bit 15 is set). the value will be shifted left. the shift is reversed—that is.L S. The shift count can be a 5-bit positive immediate integer or the value contained in X0. the direction of the shift is reversed.D S. D >> S → D (no parallel move) Else D << –S → D (no parallel move) Description: Arithmetically shift the second operand to the right by the value contained in the 5 lowest bits of the first operand (or by an immediate integer).L instruction arithmetically shifts the value $0123:4567 by 4 bits to the left and places the result in the destination register A. the MSP:LSP are shifted. maintaining sign integrity. Example: ASRR. Y0. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z Note: — Set if the MSB of the result is set — Set if the result equals zero Condition code results depend on the size of the destination operand. The result is not affected by the state of the saturation bit (SA).L (no parallel move) (no parallel move) If S[15] = 0 or S is not a register.ASRR.L Operation: Multi-Bit Arithmetic Right Shift Long Assembler Syntax: ASRR. Y1.

fff EEE.FFF C 2 2 W 1 1 Comments ASRR.L #<0–31>.fff 0 15 1 0 0 12 1 11 1 f f 8 f 7 1 1 B 4 B 3 B B B 0 ASRR.FFF 0 1 1 1 1 1 F F F a a a 1 1 0 0 Timing: Memory: 2 oscillator clock cycles 1 program word A-54 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L EEE.L Arithmetic shift right by a 5-bit positive immediate integer Bi-directional arithmetic shift of destination by value in the first operand: positive –> right shift Instruction Opcodes: 15 12 11 8 7 4 3 0 ASRR.ASRR.L Instruction Fields: Operation ASRR.L Multi-Bit Arithmetic Right Shift Long Operands #<0–31>.

arithmetic right shift of 16-bit Y1 by .S2. For 36.and 32-bit destinations. or the MSP of an accumulator.W Y1. arithmetic right shift of 16-bit A1 by . Example 2: ASRR. with sign extension from bit 31 (the FF2 portion is ignored). Freescale Semiconductor Instruction Set Details A-55 .D ASRR. and the Y0 register contains the number by which to shift (least 4 bits of $FFF1 = 1).W (no parallel move) (no parallel move) (no parallel move) (no parallel move) Description: This instruction can have two or three operands. least 4 bits of Y1 After Execution 4567 A0 000F Y0 SR 0300 F A2 D555 A1 0001 Y1 SR 0000 A0 000F Y0 0308 Before Execution 0 A2 AAAA A1 0001 Y1 Explanation of Example: Prior to execution.W instruction arithmetically shifts the value $AAAA by 1 bit to the right and places the result in the destination register A with sign extension (the LSP is cleared).W S1. a value in a 16-bit register. The shift count can be a 4-bit positive integer.W instruction arithmetically shifts the sign extended value $AAAA by 1 bit to the right and places the result in the destination register A (the LSP is cleared). the Y1 register contains the value that is to be shifted ($AAAA).W ASRR. A1 contains the value that is to be shifted ($AAAA).A . The result is not affected by the state of the saturation bit (SA). The ASRR.W Y1.W Operation: S1 >> S2 → D D >> S → D Multi-Bit Arithmetic Right Shift Word Assembler Syntax: ASRR.ASRR.D S. least 4 bits of Y0 After Execution 5678 A0 FFF1 Y0 SR 0300 F A2 D555 A1 AAAA Y1 SR 0000 A0 FFF1 Y0 0308 Before Execution 0 A2 1234 A1 AAAA Y1 Explanation of Example: Prior to execution. The contents of the destination register are not important prior to execution because they have no effect on the calculated value. only the MSP is shifted and the LSP is cleared. and the Y1 register contains the amount by which to shift ($1). respectively (or by an immediate integer). Arithmetically shift either the source operand S1 or D to the right by the value contained in the lowest 4 bits of either S2 or S. The ASRR.A . and store the result in the destination (D).Y0. Example 1: ASRR.

FFF C 1 1 1 W 1 1 1 Comments Arithmetic shift right by a 4-bit positive immediate integer Arithmetic shift right the destination by value specified in 4 LSBs of the first operand Arithmetic shift right of the first operand by value specified in 4 LSBs of the second operand.FFF Y1.FFF 0 15 1 0 1 12 1 11 1 F F 8 F 7 1 1 0 4 B 3 B B B 0 ASRR.FFF 0 1 1 1 0 0 F F F Q Q Q 0 0 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-56 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Y1.X0.Y0.W 15 LF 14 P4 Multi-Bit Arithmetic Right Shift Word ASRR.X0.W Operands #<0–15>.FFF A1.FFF B1.FFF Y0.W EEE.FFF Y0.FFF C1.Y0.Y0.Q2.W 1 V 0 C Condition Codes Affected: MR 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z N Z — Set if MSB of result is set — Set if result equals zero Instruction Fields: Operation ASRR.FFF Y1.FFF C1.Y0.ASRR.W Q1.FFF 0 15 1 1 1 12 1 11 1 F F 8 F 7 a a a 4 1 3 0 0 0 0 ASRR.W #<0–15>.FFF EEE.Y1. place result in FFF Instruction Opcodes: 15 12 11 8 7 4 3 0 ASRR.

18. The term “cc” specifies the following: “cc” Mnemonic CC (HS*) — carry clear (higher or same) CS (LO*) — carry set (lower) EQ GE GT HI* LE LS* LT NE NN NR — equal — greater than or equal — greater than — higher — less than or equal — lower or same — less than — not equal — not normalized — normalized C=0 C=1 Z=1 N⊕V=0 Z + (N ⊕ V) = 0 C•Z=1 Z + (N ⊕ V) = 1 C+Z=1 N⊕V=1 Z=0 Z + (U • E) = 0 Z + (U • E) = 1 Condition * Only available when CM bit set in the OMR Xdenotes the logical complement of X +denotes the logical OR operator •denotes the logical AND operator ⊕denotes the logical exclusive OR operator Example: BNE INC. The PC contains the address of the next instruction. If the specified condition is not true. 7. or 22 bits. <LABEL A A .Bcc Operation: If (cc). The offset can be 7.W LABEL ADD B. and program execution continues with the first INC. program execution skips the two INC. then PC + <OFFSET> → PC else PC + 1 → PC Branch Conditionally Assembler Syntax: Bcc Bcc Bcc <OFFSET7> <OFFSET18> <OFFSET22> Bcc Description: If the specified condition is true.W INC. branch to LABEL if Z condition is zero Freescale Semiconductor Instruction Set Details A-57 .” Explanation of Example: In this example. if the Z bit is zero when the BNE instruction is executed.and 18-bit offsets are sign extended to 21 bits.W instructions and continues with the ADD instruction. program execution continues at the location PC + displacement. no branch is taken.A See Table 3-14 on page 3-27 for usage of forcing operator “<LABEL. and program execution continues sequentially. the PC is incremented. the program counter is incremented by one.W instruction. If the specified condition is false. The Bcc instruction uses a PC-relative offset of two for this example.

4. and the second applies if it is not. Bcc Condition Codes Affected: The condition codes are tested but not modified by this instruction. Instruction Fields: Operation Bcc Operands <OFFSET7> <OFFSET18> <OFFSET22> C1 5 or 3 5 or 4 6 or 5 W 1 2 3 7-bit signed offset 18-bit signed offset 22-bit signed offset Comments 1. Instruction Opcodes: 15 12 11 8 7 4 3 0 Bcc <OFFSET7> 1 15 0 1 0 12 C 11 C C C 8 0 7 A a a 4 a 3 a a a 0 Bcc <OFFSET18> 1 1 1 0 0 C C C 0 1 1 0 1 C A A AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 Bcc <OFFSET22> 1 1 1 1 1 1 0 0 0 0 A C A C A C 0 0 A 1 1 1 1 0 A 1 A C A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 3–6 oscillator clock cycles 1–3 program word(s) A-58 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Bcc Restrictions: Branch Conditionally Refer to Section 10. The first value applies if the branch is taken.” on page 10-26.The clock-cycle count depends on whether the branch is taken. “Pipeline Dependencies and Interlocks.

those bits that are cleared in the immediate value are ignored in the destination. Bits 14–10 of the mask operand must be cleared. Freescale Semiconductor Instruction Set Details A-59 . Before Execution X:$5000 SR 0010 0301 Explanation of Example: Prior to execution. the instruction executes two NOPs and sets the C bit.X:<ea> (no parallel move) #iiii. otherwise. C is cleared. does not set C (because all of the selected bits were not set). and then complements the bits. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: For this destination only. All SR bits except bits 14–10 are updated with values from the bitfield unit. Those bits that are set in the immediate value are the same bits that are tested and changed in the destination. in a data memory location After Execution X:$5000 SR 0300 0300 This instruction is very useful in performing I/O and flag bit manipulation. If all selected bits are set.D (no parallel move) Description: Test all selected bits of the destination operand.X:$5000 . For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. C is set. A 16-bit immediate value is used to specify which bits are tested and changed. 8. Usage: Example: BFCHG #$0310. and store the result in the destination. Execution of the BFCHG instruction tests the state of bits 4. 8. the C bit is not updated as is done for all other destination operands. the 16-bit X memory location X:$5000 contains the value $0010. test and change bits 4. and 9 in X:$5000. This instruction performs a read-modify-write operation on the destination memory location or register and requires two destination accesses. Then complement the selected bits.BFCHG Operation: Test Bitfield and Change Assembler Syntax: BFCHG (<bitfield> of destination) → (<bitfield> of destination)BFCHG BFCHG #iiii. and 9 .

dd #<MASK16>. All registers in DDDDD are permitted except HWS and Y.X:<<pp #<MASK16>. A-60 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X:aa #<MASK16>.BFCHG Instruction Fields: Operation BFCHG Operands Test Bitfield and Change C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 Comments BFCHG #<MASK16>.X:(Rn) #<MASK16>. then the C bit is set. Otherwise it is cleared.X:xxxx #<MASK16>. If all targeted bits are set.X:(Rn+xxxx) #<MASK16>.X:xxxxxx BFCHG tests all targeted bits defined by the 16-bit immediate mask.DDDDD #<MASK16>. Then the instruction inverts all selected bits.X:(SP–xx) #<MASK16>.

dd 1 0 0 0 0 1 0 0 0 1 0 1 0 0 d d iiiiiiiiiiiiiiii Timing: Memory: 2–4 oscillator clock cycles 2–4 program words Freescale Semiconductor Instruction Set Details A-61 .X:aa 1 0 1 0 0 1 0 1 1 0 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.X:xxxx 1 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.DDDDD Test Bitfield and Change BFCHG 7 4 3 0 15 12 11 8 1 0 0 0 0 1 0 1 0 1 0 d d d d d iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.X:<<pp 1 0 1 0 0 1 0 1 1 1 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.X:(Rn) 1 0 0 0 0 1 0 0 0 1 0 0 R 0 R R iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.X:(Rn+xxxx) 1 0 0 0 0 1 0 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.BFCHG Instruction Opcodes: BFCHG #<MASK16>.X:xxxxxx 1 1 1 0 1 0 0 0 0 0 A 1 A 0 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.X:(SP–xx) 1 0 1 0 0 1 0 0 1 1 a a a a a a iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCHG #<MASK16>.

Bits 14–10 of the mask operand must be cleared. A-62 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the 16-bit X memory location X:$5000 contains the value $7FF5. and store the result in the destination. C is cleared. those bits that are cleared in the immediate value are ignored in the destination.D BFCLR (no parallel move) (no parallel move) 0 →(<bitfield> of destination) (no parallel move) Description: Test all selected bits of the destination operand. the instruction executes two NOPs and sets the C bit. If all selected bits are set. Those bits that are set in the immediate value are the same bits that are tested and cleared in the destination.BFCLR Operation: Test Bitfield and Clear Assembler Syntax: BFCLR BFCLR #iiii. Then clear the selected bits. Before Execution X:$5000 SR 7FF5 0300 Explanation of Example: Prior to execution. Execution of the BFCLR instruction tests the state of bits 4.X:<ea> #iiii. A 16-bit immediate value is used to specify which bits are tested and cleared. C is set. 8. 8. and 9 in X:5000. and then clears the selected bits. the C bit is not updated as is done for all other destination operands. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. otherwise.X:$5000 . an on-chip peripheral register After Execution X:$5000 SR 7CE5 0301 This instruction is very useful in performing I/O and flag bit manipulation. Usage: Example: BFCLR #$0310. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: For this destination only. and 9 in . All SR bits except bits 14–10 are updated with values from the bitfield unit. test and clear bits 4. sets the C bit (because all the selected bits were set). This instruction performs a read-modify-write operation on the destination memory location or register and requires two destination accesses.

Then the instruction clears all selected bits.BFCLR Instruction Fields: Operation BFCLR Operands Test Bitfield and Clear C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 Comments BFCLR #<MASK16>. then the C bit is set. All registers in DDDDD are permitted except HWS and Y.X:<<pp #<MASK16>. If all the targeted bits are set.X:xxxxxx BFCLR tests all the targeted bits defined by the 16-bit immediate mask.dd #<MASK16>.X:xxxx #<MASK16>.X:aa #<MASK16>. Otherwise it is cleared.X:(SP–xx) #<MASK16>.X:(Rn+xxxx) #<MASK16>.DDDDD #<MASK16>. Freescale Semiconductor Instruction Set Details A-63 .X:(Rn) #<MASK16>.

DDDDD Test Bitfield and Clear 15 12 11 8 7 4 BFCLR 3 0 1 0 0 0 0 0 0 1 0 1 0 d d d d d iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.X:<<pp 1 0 1 0 0 0 0 1 1 1 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.X:(Rn) 1 0 0 0 0 0 0 0 0 1 0 0 R 0 R R iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.X:xxxxxx 1 1 1 0 1 0 0 0 0 0 A 0 A 0 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.X:aa 1 0 1 0 0 0 0 1 1 0 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.BFCLR BFCLR #<MASK16>.X:xxxx 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.X:(SP–xx) 1 0 1 0 0 0 0 0 1 1 a a a a a a iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.dd 1 0 0 0 0 0 0 0 0 1 0 1 0 0 d d iiiiiiiiiiiiiiii Timing: Memory: 2–4 oscillator clock cycles 2–4 program words A-64 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X:(Rn+xxxx) 1 0 0 0 0 0 0 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFCLR #<MASK16>.

clears the C bit (because none of the selected bits was set).BFSET Operation: Test Bitfield and Set Assembler Syntax: BFSET BFSET #iiii. set bits in peripheral register After Execution X:$5000 SR FF00 0300 This instruction is very useful in performing I/O and flag bit manipulation. otherwise. Freescale Semiconductor Instruction Set Details A-65 . 11. Bits 14–10 of the mask operand must be cleared. Before Execution X:$5000 SR 3300 0301 Explanation of Example: Prior to execution. C is cleared. Then set the selected bits. Usage: Example: BFSET #$CC00. and then sets the selected bits. the 16-bit X memory location X:$5000 contains the value $3300. Execution of the instruction tests the state of bits 10.D BFSET (no parallel move) (no parallel move) 1 → (<bitfield> of destination) (no parallel move) Description: Test all selected bits of the destination operand. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: For this destination only.X:<ea> #iiii. 14. A 16-bit immediate value is used to specify which bits are tested and set.X:$5000 . This instruction performs a read-modify-write operation on the destination memory location or register and requires two destination accesses. the C bit is not updated as is done for all other destination operands. All SR bits except bits 14–10 are updated with values from the bitfield unit. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. the instruction executes two NOPs and sets the C bit. Those bits that are set in the immediate value are the same bits that are tested and set in the destination. those bits that are cleared in the immediate value are ignored in the destination. and store the result in the destination memory. If all selected bits are set. C is set. and 15 in X:$5000.

DDDDD #<MASK16>. Then the instruction sets all selected bits. then the C bit is set.BFSET Instruction Fields: Operation BFSET Operands Test Bitfield and Set C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 Comments BFSET #<MASK16>.X:(Rn+xxxx) #<MASK16>.dd #<MASK16>. If all the targeted bits are set. A-66 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X:(Rn) #<MASK16>. Otherwise it is cleared. All registers in DDDDD are permitted except HWS and Y.X:<<pp #<MASK16>.X:xxxx #<MASK16>.X:xxxxxx BFSET tests all the targeted bits defined by the 16-bit immediate mask.X:(SP–xx) #<MASK16>.X:aa #<MASK16>.

DDDDD Test Bitfield and Set BFSET 8 7 4 3 0 15 12 11 1 0 0 0 0 0 1 1 0 1 0 d d d d d iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.X:xxxx 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.dd 1 0 0 0 0 0 1 0 0 1 0 1 0 0 d d iiiiiiiiiiiiiiii Timing: Memory: 2–4 oscillator clock cycles 2–4 program words Freescale Semiconductor Instruction Set Details A-67 .X:xxxxxx 1 1 1 0 1 0 0 0 0 0 A 0 A 1 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.X:<<pp 1 0 1 0 0 0 1 1 1 1 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.X:(Rn+xxxx) 1 0 0 0 0 0 1 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.X:(Rn) 1 0 0 0 0 0 1 0 0 1 0 0 R 0 R R iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.BFSET Instruction Opcodes: BFSET #<MASK16>.X:aa 1 0 1 0 0 0 1 1 1 0 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.X:(SP–xx) 1 0 1 0 0 0 1 0 1 1 a a a a a a iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFSET #<MASK16>.

Before Execution X:$5000 SR 0FF0 0300 Explanation of Example: Prior to execution.X:<ea>(no parallel move) BFTSTH#iiii. the instruction executes two NOPs and sets the C bit.BFTSTH Operation: Test Bitfield High Assembler Syntax: BFTSTH Test <bitfield> of destination for ones(no parallel move) BFTSTH#iiii. the 16-bit X memory location X:$FFE2 contains the value $0FF0. A-68 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. an on-chip peripheral register After Execution X:$5000 SR 0FF0 0301 This instruction is very useful for testing I/O and flag bits. test high bits 4. otherwise.D (no parallel move) Description: Test all selected bits of the destination operand. 8. and 9 in . Usage: Example: BFTSTH #$0310. and 9 in X:$FFE2 and sets the C bit (because all the selected bits were set). Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: Bits 14–10 of the mask operand must be cleared.X:5000 . 8. C is cleared. Execution of the instruction tests the state of bits 4. Those bits that are set in the immediate value are the same bits that are tested in the destination. If all selected bits are set. those bits that are cleared in the immediate value are ignored in the destination. A 16-bit immediate value is used to specify which bits are tested. C is set. This instruction performs two destination accesses.

X:(Rn+xxxx) #<MASK16>.X:(Rn) Test Bitfield High C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 Comments BFTSTH BFTSTH tests all the targeted bits defined by the 16-bit immediate mask.X:(SP–xx) #<MASK16>.X:<<pp #<MASK16>. All registers in DDDDD are permitted except HWS and Y. then the C bit is set. If all the targeted bits are set.DDDDD #<MASK16>. #<MASK16>.X:xxxxxx Freescale Semiconductor Instruction Set Details A-69 . Otherwise it is cleared.X:xxxx #<MASK16>.X:aa #<MASK16>.dd #<MASK16>.BFTSTH Instruction Fields: Operation BFTSTH Operands #<MASK16>.

X:aa 1 0 1 0 1 1 0 1 1 0 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.X:xxxx 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.X:xxxxxx 1 1 1 0 1 0 0 0 0 1 A 1 A 0 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.X:(SP–xx) 1 0 1 0 1 1 0 0 1 1 a a a a a a iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.dd 1 0 0 0 1 1 0 0 0 1 0 1 0 0 d d iiiiiiiiiiiiiiii Timing: Memory: 2–4 oscillator clock cycles 2–4 program words A-70 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .BFTSTH Instruction Opcodes: BFTSTH #<MASK16>DDDDD Test Bitfield High BFTSTH 8 7 4 3 0 15 12 11 1 0 0 0 1 1 0 1 0 1 0 d d d d d iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.X:(Rn) 1 0 0 0 1 1 0 0 0 1 0 0 R 0 R R iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.X:(Rn+xxxx) 1 0 0 0 1 1 0 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.X:<<pp 1 0 1 0 1 1 0 1 1 1 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTH #<MASK16>.

an on-chip peripheral register After Execution X:$5000 SR 0CC0 0301 This instruction is very useful for testing I/O and flag bits. Usage: Example: BFTSTL #$0310. the 16-bit X memory location X:$5000 contains the value $0CC0. C is set. C is cleared.X:<ea>(no parallel move) BFTSTL#iiii. 8. Those bits that are set in the immediate value are the same bits that are tested in the destination. those bits that are cleared in the immediate value are ignored in the destination. and 9 in . otherwise.D (no parallel move) Description: Test all selected bits in the destination operand. If all selected bits are clear. test low bits 4. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. Execution of the instruction tests the state of bits 4. 8.X:$5000 Before Execution X:$5000 SR 0CC0 0300 . the instruction executes two NOPs and sets the C bit. Explanation of Example: Prior to execution. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: Bits 14–10 of the mask operand must be cleared. Freescale Semiconductor Instruction Set Details A-71 .BFTSTL Operation: Test Bitfield Low Assembler Syntax: BFTSTL Test <bitfield> of destination for zeros (no parallel move) BFTSTL#iiii. This instruction performs two destination accesses. A 16-bit immediate value is used to specify which bits are tested. and 9 in X:$5000 and sets the C bit (because all the selected bits were cleared).

X:xxxxxx A-72 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . If all the targeted bits are clear.BFTSTL Instruction Fields: Operation BFTSTL Operands #<MASK16>.DDDDD #<MASK16>.X:(SP–xx) #<MASK16>. #<MASK16>. All registers in DDDDD are permitted except HWS and Y. then the C bit is set.X:aa #<MASK16>.X:xxxx #<MASK16>.X:(Rn) Test Bitfield Low C 2 2 2 3 3 2 2 3 4 W 2 2 2 3 2 2 2 3 4 Comments BFTSTL BFTSTL tests all the targeted bits defined by the 16-bit immediate mask.X:(Rn+xxxx) #<MASK16>. Otherwise it is cleared.dd #<MASK16>.X:<<pp #<MASK16>.

X:<<pp 1 0 1 0 1 0 0 1 1 1 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.BFTSTL Instruction Opcodes: BFTSTL #<MASK16>DDDDD Test Bitfield Low BFTSTL 8 7 4 3 0 15 12 11 1 0 0 0 1 0 0 1 0 1 0 d d d d d iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.X:xxxx 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.dd 1 0 0 0 1 0 0 0 0 1 0 1 0 0 d d iiiiiiiiiiiiiiii Timing: Memory: 2–4 oscillator clock cycles 2–4 program words Freescale Semiconductor Instruction Set Details A-73 .X:xxxxxx 1 1 1 0 1 0 0 0 0 1 A 0 A 0 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.X:aa 1 0 1 0 1 0 0 1 1 0 p p p p p p iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.X:(SP–xx) 1 0 1 0 1 0 0 0 1 1 a a a a a a iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.X:(Rn+xxxx) 1 0 0 0 1 0 0 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.X:(Rn) 1 0 0 0 1 0 0 0 0 1 0 0 R 0 R R iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 BFTSTL #<MASK16>.

execution resumes here Explanation of Example: In this example. 18-bit. The displacement is a 7-bit.W instructions and continues with the ADD instruction. A BRA instruction cannot be repeated using the REP instruction. Instruction Fields: Operation BRA Operands <OFFSET7> <OFFSET18> <OFFSET22> C 5 5 6 W 1 2 3 7-bit signed offset 18-bit signed offset 22-bit signed offset Comments LABEL A A . Condition Codes Affected: The condition codes are not affected by this instruction. jump to instruction at “LABEL” . program execution skips the two INC.BRA Operation: PC + <OFFSET> → PC Branch Assembler Syntax: BRA BRA BRA <OFFSET7> <OFFSET18> <OFFSET22> BRA Description: Branch to the location in program memory at PC + displacement.A . Example: BRA INC. The BRA instruction uses a PC-relative offset of two for this example. these two instructions are skipped Instruction Opcodes: 15 12 11 8 7 4 3 0 BRA <OFFSET7> 1 15 0 1 0 12 1 11 0 0 1 8 0 7 A a a 4 a 3 a a a 0 BRA <OFFSET18> 1 1 1 0 0 0 0 1 0 1 1 0 1 1 A A AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 BRA <OFFSET22> 1 1 1 1 1 1 0 0 0 0 A 0 A 0 A 1 0 0 A 1 1 1 1 0 A 1 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 5–6 oscillator clock cycles 1–3 program word(s) A-74 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . or 22-bit signed value that is sign extended to form the PC-relative offset.W INC.W LABEL ADD B. Restrictions: A BRA instruction used within a DO loop cannot begin at the LA or LA – 1 within that DO loop. The PC contains the address of the next instruction.

. before the branch! Freescale Semiconductor Instruction Set Details A-75 . these two increments are executed . The displacement is a 7-bit.3.BRAD Operation: Execute instructions in next 2 words PC + <OFFSET> → PC Delayed Branch Assembler Syntax: BRAD BRAD BRAD <OFFSET7> <OFFSET18> <OFFSET22> BRAD Description: Branch to the location in program memory at PC + displacement. Example: BRAD INC.W .. The PC contains the address of the next instruction. Refer to Section 4. delayed branch to “LABEL” .W INC. 18-bit.2. LABEL ADD B. Restrictions: A BRAD instruction used within a DO loop cannot begin at the LA or LA – 1 within that DO loop. but first execute the instruction or instructions in the following 2 program words.A Explanation of Example: In this example. A BRAD instruction cannot be repeated using the REP instruction. and then it continues with the ADD instruction that follows LABEL.W instructions that follow the BRAD instruction. LABEL A A . or 22-bit signed value that is sign extended to form the PC-relative offset. the program executes the two INC. Condition Codes Affected: The condition codes are not affected by this instruction.” on page 4-14. “Delayed Instruction Restrictions.

must fill 2 delay slots Instruction Opcodes: 15 12 11 8 7 4 3 0 BRAD <OFFSET7> 1 15 0 1 0 12 1 11 0 1 1 8 0 7 A a a 4 a 3 a a a 0 BRAD <OFFSET18> 1 1 1 0 0 0 1 1 0 1 1 0 1 1 A A AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 BRAD <OFFSET22> 1 1 1 1 1 1 0 0 0 0 A 0 A 1 A 1 0 0 A 1 1 1 1 0 A 1 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 3–4 oscillator clock cycles 1–3 program word(s) A-76 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . must fill 2 delay slots Delayed branch with 22-bit signed offset. must fill 2 delay slots Delayed branch with 18-bit signed offset.BRAD Instruction Fields: Operation BRAD Operands <OFFSET7> <OFFSET18> <OFFSET22> C 3 3 4 Delayed Branch W 1 2 3 Comments BRAD Delayed branch with 7-bit signed offset.

LABEL A A . and the branch is taken.BRCLR Operation: Branch if Bits Clear Assembler Syntax: BRCLR Branch if <bitfield> of destination is all zeros (no parallel move) BRCLR #<MASK8>. next two instructions . If all the selected bits are clear. and program execution continues at the location in program memory at PC + displacement.W LABEL ADD Before Execution X:$5000 SR FF00 0300 B.X:$5000. the 16-bit X memory location X:$5000 contains the value $FF00. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: — Bits 14–10 of the mask operand must be cleared. Since C is set.A After Execution X:$5000 SR FF00 0301 #$0068. C is set. Those bits that are set in the immediate value are the same bits that are tested in the destination.AA Description: Test all selected bits of the destination operand. Explanation of Example: Prior to execution.AA BRCLR #<MASK8>. Usage: Example: BRCLR INC. C is set.W INC. Otherwise. 5. Execution of the BRCLR instruction tests the state of bits 3. and execution continues with the next sequential instruction.X:<ea>. C is cleared. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. program execution is then transferred to the address offset from the current program counter by the displacement that is specified in the instruction. those bits that are cleared in the immediate value are ignored in the destination. and 6 in X:$5000 and sets the C bit (because all the mask bits were clear). Freescale Semiconductor Instruction Set Details A-77 . are bypassed This instruction is useful in performing I/O flag polling. A 16-bit immediate value is used to specify which bits are tested.D.

X:(Rn+xxxx).AA #<MASK8>. If all the targeted bits are clear. All registers in DDDDD are permitted except HWS and Y.AA #<MASK8>. AA specifies a 7-bit PC-relative offset.The first cycle count refers to the case when the condition is true and the branch is taken. A-78 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .AA #<MASK8>. where either the upper or lower 8 bits contain all zeros.dd.X:xxxx. then the carry bit is set and a PC-relative branch occurs.AA W 2 2 2 3 2 2 2 3 4 BRCLR tests all the targeted bits defined by the immediate mask.BRCLR Instruction Fields: Operation BRCLR Branch if Bits Clear C1 7/5 7/5 7/5 8/6 8/6 7/5 7/5 7/5 8/6 BRCLR Comments Operands #<MASK8>.X:<<pp.X:aa. Otherwise it is cleared and no branch occurs.AA #<MASK8>.AA #<MASK8>.X:(SP–xx). The second cycle count refers to the case when the condition is false and the branch is not taken.AA #<MASK8>.X:(Rn).AA #<MASK8>.X:xxxxxx. MASK8 specifies a 16-bit immediate value.DDDDD. 1.AA #<MASK8>.

X:xxxxxx.X:xxxx.AA 1 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.AA 1 0 0 0 1 0 1 0 0 1 0 0 R 0 R R iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.X:(SP–xx).X:(Rn+xxxx).BRCLR Instruction Opcodes: BRCLR #<MASK8>.dd.X:<<pp.AA 1 0 0 0 1 0 1 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.AA 1 0 0 0 1 0 1 0 0 1 0 1 0 0 d d iiiiiiiiUAaaaaaa Timing: Memory: 5–8 oscillator clock cycles 2–4 program words Freescale Semiconductor Instruction Set Details A-79 .X:aa.DDDDD.AA 1 0 1 0 1 0 1 1 1 0 p p p p p p iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.AA Branch if Bits Clear BRCLR 8 7 4 3 0 15 12 11 1 0 0 0 1 0 1 1 0 1 0 d d d d d iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.X:(Rn).AA 1 0 1 0 1 0 1 1 1 1 p p p p p p iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.AA 1 1 1 0 1 0 0 0 0 1 A 0 A 1 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.AA 1 0 1 0 1 0 1 0 1 1 a a a a a a iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRCLR #<MASK8>.

A 16-bit immediate value is used to specify which bits are tested. and program execution continues at the location in program memory at PC + displacement. the 16-bit X memory location X:$5000 contains the value $0FF0. C is cleared. next two instructions .AA BRSET #<MASK8>.LABEL A A .D. program execution is then transferred to the address offset from the current program counter by the displacement that is specified in the instruction.W INC. and execution continues with the next sequential instruction. If all the selected bits are set. A-80 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . C is set. Those bits that are set in the immediate value are the same bits that are tested in the destination.X:<ea>. Since C is set. C is set and the branch is taken.BRSET Operation: Branch if Bits Set Assembler Syntax: BRSET Branch if <bitfield> of destination is all ones (no parallel move) BRSET #<MASK8>. Execution of the BRSET instruction tests the state of bits 8 and 10 in X:$5000 and sets the C bit (because all the mask bits were set).W LABEL ADD Before Execution X:$5000 SR 0FF0 0300 B. are bypassed This instruction is useful in performing I/O flag polling. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: — Bits 14–10 of the mask operand must be cleared. Otherwise.X:$5000.A After Execution X:$5000 SR 0FF0 0301 #$0500. Explanation of Example: Prior to execution.AA Description: Test all selected bits of the destination operand. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. those bits that are cleared in the immediate value are ignored in the destination. Usage: Example: BRSET INC.

Freescale Semiconductor Instruction Set Details A-81 . MASK8 specifies a 16-bit immediate value. AA specifies a 7-bit PC-relative offset. The second cycle count refers to the case when the condition is false and the branch is not taken.AA #<MASK8>.dd.The first cycle count refers to the case when the condition is true and the branch is taken. Otherwise it is cleared and no branch occurs.X:(Rn). If all the targeted bits are set.DDDDD.AA #<MASK8>. 1.X:aa. then the carry bit is set and a PC-relative branch occurs.AA #<MASK8>.AA #<MASK8>.AA #<MASK8>.X:(SP–xx).X:(Rn+xxxx).AA #<MASK8>.BRSET Instruction Fields: Operation BRSET Operands Branch if Bits Set C1 7/5 7/5 7/5 8/6 8/6 7/5 7/5 7/5 8/6 BRSET Comments W 2 2 2 3 2 2 2 3 4 #<MASK8>.X:xxxx. where either the upper or lower 8 bits contain all zeros.X:<<pp.X:xxxxxx.AA BRSET tests all the targeted bits defined by the immediate mask.AA #<MASK8>. All registers in DDDDD are permitted except HWS and Y.AA #<MASK8>.

X:(SP–xx).DDDDD.AA 1 0 1 0 1 1 1 1 1 1 p p p p p p iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.X:(Rn).BRSET Instruction Opcodes: BRSET #<MASK8>.AA 1 0 0 0 1 1 1 0 0 1 0 1 0 0 d d iiiiiiiiUAaaaaaa Timing: Memory: 5–8 oscillator clock cycles 2–4 program words A-82 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .AA Branch if Bits Set BRSET 8 7 4 3 0 15 12 11 1 0 0 0 1 1 1 1 0 1 0 d d d d d iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.AA 1 0 1 0 1 1 1 1 1 0 p p p p p p iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.X:xxxxxx.X:(Rn+xxxx).X:aa.AA 1 0 1 0 1 1 1 0 1 1 a a a a a a iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.AA 1 0 0 0 1 1 1 0 0 1 0 0 R 1 R R AAAAAAAAAAAAAAAA iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.AA 1 0 0 0 1 1 1 0 0 1 0 0 R 0 R R iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.X:xxxx.dd.AA 1 1 1 0 1 0 0 0 0 1 A 1 A 1 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.AA 1 0 0 0 1 1 1 0 0 1 0 1 0 1 0 0 AAAAAAAAAAAAAAAA iiiiiiiiUAaaaaaa 15 12 11 8 7 4 3 0 BRSET #<MASK8>.X:<<pp.

” on page 10-26.BSR Operation: SP + 1 → SP PC → X:(SP) SP + 1 → SP SR → X:(SP) PC + <OFFSET> → PC Branch to Subroutine Assembler Syntax: BSR <OFFSET18> or <OFFSET22> BSR Description: Place the PC and SR on the software stack and branch to the location in program memory at PC + displacement.4. program execution is transferred to the subroutine at the PC-relative address that is represented by LABEL. Instruction Fields: Operation BSR Operands <OFFSET18> <OFFSET22> C 5 6 W 2 3 18-bit signed offset 22-bit signed offset Comments Instruction Opcodes: 15 12 11 8 7 4 3 0 BSR <OFFSET18> 1 1 1 0 0 0 1 0 0 1 1 0 1 1 A A AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 BSR <OFFSET22> 1 1 1 1 1 1 0 0 0 0 A 0 A 1 A 0 0 0 A 1 1 1 1 0 A 1 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 5–6 oscillator clock cycles 2–3 program words Freescale Semiconductor Instruction Set Details A-83 . “Pipeline Dependencies and Interlocks. The displacement is an 18-bit or 22-bit signed value that is sign extended to form the PC-relative offset.or 22-bit signed value. Restrictions: Refer to Section 10. Condition Codes Affected: The condition codes are not affected by this instruction. The relative offset that is given by the label can be an 18. branch to PC-relative address “LABEL” Explanation of Example: In this example. Example: BSR LABEL . The PC contains the address of the next instruction.

and only the bits in the FF10 portion are counted. and place that number minus one in the destination. After the CLB A.D CLB (no parallel move) If S[MSB] = 0 (# of leading zeros – 1) in S → D else (# of leading ones – 1) in S → D Description: Count the number of leading bits in the source operand. and the X0 register contains $AAAA.X0 . this instruction may be followed by the operation ASLL. The result is not affected by the state of the saturation bit (SA). result minus one in X0 After Execution 4836 A0 X0 7FFF 0 A2 D7B2 A1 X0 4836 A0 0001 Before Execution 0 A2 D7B2 A1 SR 030F SR 0301 Explanation of Example: The A register initially contains the value $F:D7B2:4836. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V — Set if the high-order bit of the result is set — Set if the result is zero — Always cleared Instruction Fields: Operation CLB Operands FFF.L instruction to normalize a number. the number of zeros in the source operand (minus one) is placed in the destination. This instruction is used in conjunction with the ASLL. designed to operate with the ASLL and ASRR instructions A-84 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .EEE C 1 W 1 Comments Count leading bits (minus one).L X0. the value $0001 is placed in X0.X0 instruction is executed.CLB Operation: Count Leading Bits Assembler Syntax: CLB S. Example: CLB A. since there are two leading ones in the value contained in A10. placing . the extension portion is ignored. count leading bits in A. In order to normalize A. If the source register is an accumulator.A (the resulting normalized number would be $F:AF64:906C). The bits to count are based on the high-order bit of the source operand: if the high-order bit is zero.

CLB Instruction Opcodes: CLB FFF.EEE Count Leading Bits CLB 8 7 4 3 0 15 12 11 0 1 1 1 1 0 E E E b b b 1 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-85 .

Instruction Fields: Operation CLR Operands F C 1 W 1 Comments Clear 36-bit accumulator and set condition codes. Example: CLR A A. Data limiting may occur during a parallel write. Condition Codes Affected: MR 15 LF 14 * 13 * 12 * 11 * 10 * 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V Note: — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if data limiting has occurred during parallel move Always cleared Always set Always cleared Always set Always cleared This instruction operates only on the A and B accumulator registers. and the saturation value $7FFF is written to memory. Also see CLR. The CLR.W instruction should be used to clear any of the other registers (including A and B if desired).W. Execution of the CLR A instruction sets the A accumulator to zero.X:(R0)+. save A into memory before clearing it After Execution 789A A0 SR 032F 0 A2 0000 A1 SR 0000 A0 03D5 Before Execution 2 A2 3456 A1 Explanation of Example: Prior to execution. the 36-bit A accumulator contains the value $2:3456:789A.CLR Operation: 0→D 0→D 0→D (no parallel move) (one parallel move) (two parallel reads) Clear Accumulator Assembler Syntax: CLR CLR CLR D D D (no parallel move) (one parallel move) (two parallel reads) CLR Description: Set the A or B accumulator to zero. A-86 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

Freescale Semiconductor Instruction Set Details A-87 . 2.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed. Memory writes are allowed in this case.CLR Parallel Moves: Data ALU Operation Operation CLR2 Clear Accumulator CLR Parallel Memory Move Operands F Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.

This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.CLR Parallel Dual Reads: Data ALU Operation1 Operation CLR2 Operands F Clear Accumulator CLR Second Memory Read Source 2 X:(R3)+ X:(R3)– Destination 2 X0 First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Y0 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 Y1 C 1.This instruction is not allowed when the XP bit in the OMR is set (that is. Instruction Opcodes: 15 12 11 8 7 4 3 0 CLR F 0 15 1 1 1 12 0 11 1 1 1 8 F 7 1 0 0 4 0 3 1 1 1 0 CLR F GGG.X:<ea_m> 0 15 0 0 0 12 1 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 CLR F X:<ea_m>. 2. when the instructions are executing from data memory).reg2 0 1 1 1 0 1 v v F v 0 1 0 m 0 v Timing: Memory: 1 oscillator clock cycle 1 program word A-88 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .GGG 0 15 0 1 0 12 1 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 CLR F X:<ea_m>.reg1 X:<ea_v>.

B X:(Rn+xxxx) 1 1 0 1 1 0 0 1 1 1 1 0 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR. Instruction Fields: Operation CLR.B (no parallel move) Description: Set a byte in memory to zero.B Operands X:(SP) X:(Rn+xxxx) X:(Rn+xxxxxx) C 1 2 3 W 1 2 3 Comments Clear a byte in memory using appropriate addressing mode Instruction Opcodes: 15 12 11 8 7 4 3 0 CLR.CLR.B X:(SP-1) .B Operation: 0→D (no parallel move) Clear Byte (Word Pointer) Assembler Syntax: CLR.B D CLR.B X:(Rn+xxxxxx) 1 1 1 1 1 0 0 1 0 1 A 0 A 0 A 1 0 1 A 1 1 1 1 0 A R A 0 A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.B X:(SP) 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-89 . Condition Codes Affected: The condition codes are not affected by this instruction. Addresses are expressed as word pointers. clear a byte in the stack After Execution 3333 2222 004443 X:$4443 X:$4442 SP 3333 0022 004443 Before Execution X:$4443 X:$4442 SP Explanation of Example: The contents of the upper byte from stack address $004442 are cleared. Example: CLR.

Example: CLR.BP (no parallel move) Description: Set a byte in memory to zero.BP D CLR. Note that this address is equivalent to the upper byte of word address $1832.BP X:$3065 Before Execution Byte Addresses X Memory 7 0 07 . A-90 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . An absolute address is expressed as a byte address.CLR. Condition Codes Affected: The condition codes are not affected by this instruction. set byte at (byte) address $3065 to zero After Execution Byte Addresses 7 X Memory 0 07 $3068 $3066 $3064 $3062 88 66 44 22 77 55 33 11 $3068 $3066 $3064 $3062 88 66 00 22 77 55 33 11 Explanation of Example: The byte value in X memory at byte address $3065 is cleared.BP Operation: 0→D (no parallel move) Clear Byte (Byte Pointer) Assembler Syntax: CLR.

BP X:<ea_MM> 1 15 1 0 1 12 1 11 0 0 1 8 1 7 0 1 M 4 N 3 M N N 0 CLR.BP X:xxxxxx 1 1 1 1 1 0 0 1 0 1 A 0 A 0 A 1 0 1 A 1 1 1 1 1 A 1 A 1 A 0 A 1 AAAAAAAAAAAAAAAA Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-91 .BP X:(RRR+xxxxxx) 1 1 1 1 1 0 0 1 0 1 A 0 A 0 A 1 0 1 A 1 1 1 1 0 A N A 1 A N A N AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.BP Instruction Fields: Operation CLR.BP X:(RRR+xxxx) 1 1 0 1 1 0 0 1 1 1 1 0 N 1 N N AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.BP Clear Byte (Byte Pointer) Operands X:(RRR) X:(RRR)+ X:(RRR)– X:(RRR+N) X:(RRR+xxxx) X:(RRR+xxxxxx) X:xxxx X:xxxxxx C 1 1 1 2 2 3 2 3 W 1 1 1 1 2 3 2 3 Comments Clear a byte in memory CLR.BP X:xxxx 1 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.BP Instruction Opcodes: 15 12 11 8 7 4 3 0 CLR.CLR.

and it indicates the address of the lower half of the long word. The destination address of the long word that is to be cleared must be an even word pointer value.L Operation: 0→D (no parallel move) Clear Long Assembler Syntax: CLR.L Operands X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn+xxxx) X:(Rn+xxxxxx) X:xxxx X:xxxxxx C 1 1 1 2 2 3 2 3 W 1 1 1 1 2 3 2 3 Comments Clear a long in memory A-92 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Condition Codes Affected: The condition codes are not affected by this instruction.L D CLR. set long word at address $3000 to zero After Execution X Memory 15 0 Word Addresses X Memory 15 0 Before Execution Word Addresses $3002 $3001 $3000 $2FFF 4444 3333 2222 1111 $3002 $3001 $3000 $2FFF 4444 0000 0000 1111 Explanation of Example: The long-word value in X memory at the address $3000 is cleared.CLR.L X:$3000 . Example: CLR.L (no parallel move) Description: Set a long word in memory to zero. Instruction Fields: Operation CLR.

L X:xxxx 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.L X:<ea_MM> 1 15 1 0 1 12 1 11 1 1 1 8 0 7 0 1 M 4 R 3 M R R 0 CLR.L 8 7 4 3 0 12 11 CLR.L Instruction Opcodes: 15 Clear Long CLR.L X:(Rn+xxxxxx) 1 1 1 1 1 0 0 1 0 1 A 1 A 1 A 1 0 0 A 1 1 1 1 0 A R A 0 A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.CLR.L X:(Rn+xxxx) 1 1 0 1 1 1 1 1 0 1 1 0 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.L X:xxxxxx 1 1 1 1 1 0 0 1 0 1 A 1 A 1 A 1 0 0 A 1 1 1 1 1 A 1 A 1 A 0 A 1 AAAAAAAAAAAAAAAA Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-93 .

W D CLR.W X:$3000 . the entire register is cleared. Note: This instruction should be used instead of the CLR instruction for clearing accumulator registers in all new programs. If an accumulator register or an AGU address register is specified. and it clears an entire AGU register when Rn is specified.CLR.W Operation: 0→D (no parallel move) Clear Word Assembler Syntax: CLR. Clear a word in memory. Example: CLR. Condition Codes Affected: The condition codes are not affected by this instruction. X:(Rn) X:(Rn)+ X:(Rn)– X:(Rn+N) X:(Rn)+N X:(Rn+xxxx) X:(Rn+xxxxxx) X:aa X:<<pp X:xxxx X:xxxxxx 1 1 1 2 1 2 3 1 1 2 3 1 1 1 1 1 2 3 1 1 2 3 A-94 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W (no parallel move) Description: Set a word in memory or in an ALU register to zero. set word at (word) address $3000 to zero After Execution X Memory 15 0 Word Addresses X Memory 15 0 Before Execution Word Addresses $3002 $3001 $3000 $2FFF 4444 3333 2222 1111 $3002 $3001 $3000 $2FFF 4444 3333 0000 1111 Explanation of Example: The word value in X memory at the address $3000 is cleared. Instruction Fields: Operation CLR.W Operands DDDDD C 1 W 1 Comments Clear a register. The instruction clears an entire accumulator when FF is specified.

W X:(Rn+xxxx) 1 1 0 1 1 1 1 1 0 1 0 0 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.W Instruction Opcodes: 15 Clear Word CLR.W X:(Rn)+N 1 15 1 0 1 12 1 11 1 1 1 8 0 7 1 0 1 4 R 3 1 R R 0 CLR.W 8 7 4 3 0 12 11 CLR.W DDDDD 1 15 0 0 0 12 D 11 D D D 8 D 7 0 0 0 4 1 3 1 1 1 0 CLR.W X:xxxxxx 1 1 1 1 1 0 0 1 0 1 A 1 A 1 A 1 0 0 A 1 1 1 1 1 A 1 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-95 .W X:aa 1 1 0 0 1 1 1 1 0 0 p p p p p p 15 12 11 8 7 4 3 0 CLR.W X:(Rn+xxxxxx) 1 1 1 1 1 0 0 1 0 1 A 1 A 1 A 1 0 0 A 1 1 0 1 0 A R A 0 A R A R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.W X:xxxx 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CLR.CLR.W X:<<pp 1 1 0 0 1 1 1 1 0 1 p p p p p p 15 12 11 8 7 4 3 0 CLR.W X:<ea_MM> 1 15 1 0 1 12 1 11 1 1 1 8 0 7 0 0 M 4 R 3 M R R 0 CLR.

compare Y0 and A.D (one parallel move) (no parallel move) CMP Description: Subtract the first operand from the second operand and update the CCR without storing the result. and updates the CCR (leaving the A accumulator unchanged). update R1 After Execution 0000 A0 0024 Y0 SR 0300 0 A2 0020 A1 2000 Y1 SR 0000 A0 0024 Y0 0319 Before Execution 0 A2 0020 A1 2000 Y1 Explanation of Example: Prior to execution.A X0. if the first operand is one of the four accumulators. subtracts the result from the 36-bit A accumulator. If the second operand is a 36-bit accumulator. In order for the carry bit (C) to be set correctly as a result of the subtraction.X:(R1)+N . Example: CMP Y0. This note particularly applies to the case in which the source is extended to compare 16-bit operands. Y0. the FF1 portion (properly sign extended) is used in the 16-bit subtraction (the FF2 and FF0 portions are ignored). 16-bit subtraction is performed. so that FF2 might not represent the correct sign extension. 16-bit source registers are first sign extended internally and concatenated with 16 zero bits to form a 36-bit operand. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V C — — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extension portion of the result is in use Set if result is not normalized Set if bit 35 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 35 of the result A-96 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . such as X0 with A1. The destination can be improperly sign extended by writing the FF1 portion explicitly prior to executing the compare.A instruction automatically appends the 16-bit value in the Y0 register with 16 LS zeros.D S. or Y1. and the 16-bit Y0 register contains the value $0024. the operands must be properly sign extended. Usage: Note: This instruction can be used for both integer and fractional two’s-complement data.CMP Operation: D–S D–S (one parallel move) (no parallel move) Compare Assembler Syntax: CMP CMP S. When the second operand is X0. In this case. save X0. the 36-bit A accumulator contains the value $0:0020:0000. sign extends the resulting 32-bit long word to 36 bits. Execution of the CMP Y0.

W for condition codes on 16 bits.FF X:xxxxxx.FF X:(Rn+xxxx). See CMP.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed. Compare memory word with 36 bit accumulator.F A. Memory writes are allowed in this case.FF #xxxx. Parallel Moves: Data ALU Operation Operation CMP2 Operands X0. Freescale Semiconductor Instruction Set Details A-97 . Compare accumulator with a signed 16-bit immediate.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. Note: Condition codes are set based on a 36-bit result.F C.FF Compare C 1 2 3 3 2 3 1 2 W 1 1 2 1 2 3 1 2 Comments CMP 36-bit compare two accumulators or data registers.B B.FF X:xxxx.FF #<0–31>. Also see CMP.W. Compare accumulator with an immediate integer 0–31. 2.F Y1.CMP Instruction Fields: Operation CMP Operands EEE.A Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.FF X:(SP–xx).F Y0.EEE X:(Rn).

CMP Instruction Opcodes: 15 Compare CMP 8 7 4 3 0 12 11 CMP #<0–31>.F X:<ea_m>.F GGG.FF 0 1 0 1 1 1 0 F F 1 0 0 0 1 0 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP X:xxxxxx.GGG 0 15 0 1 1 12 1 11 G G G 8 F 7 1 1 0 4 0 3 m R R 0 CMP DD.X:<ea_m> 0 15 0 0 1 12 1 11 G G G 8 F 7 0 0 0 4 0 3 m R R 0 CMP ~F.F GGG.FF 0 15 1 0 1 12 1 11 1 0 F 8 F 7 1 0 1 4 R 3 1 R R 0 CMP X:(Rn+xxxx).EEE 0 15 1 1 1 12 1 11 0 E E 8 E 7 a a a 4 0 3 1 0 0 0 CMP X:(Rn).FF 1 0 1 1 1 0 0 1 0 1 A 1 A 0 A F 0 F A 1 1 0 1 0 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP ~F.X:<ea_m> 0 15 0 0 1 12 1 11 G G G 8 F 7 J J J 4 0 3 m R R 0 CMP DD.X:<ea_m> 0 15 0 0 1 12 1 11 G G G 8 F 7 1 1 0 4 0 3 m R R 0 CMP C.FF 0 1 0 1 1 1 0 F F 1 0 0 0 0 0 0 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 CMP C.FF 0 15 1 0 1 12 1 11 0 0 F 8 F 7 1 a a 4 a 3 a a a 0 CMP X:xxxx.FF 0 15 1 0 1 12 1 11 1 0 F 8 F 7 0 0 B 4 B 3 B B B 0 CMP #xxxx.GGG 0 0 1 1 1 G G G F 0 0 0 0 m R R Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) A-98 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .F X:<ea_m>.F X:<ea_m>.FF 0 1 0 1 1 1 0 F F 1 0 1 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP X:(SP–xx).F GGG.GGG 0 15 0 1 1 12 1 11 G G G 8 F 7 J J J 4 0 3 m R R 0 CMP EEE.

the 36-bit A accumulator contains the value $0:0020:0000. compare value in A accumulator to hex 24 After Execution 0000 A0 SR 0300 0 A2 0020 A1 SR 0000 A0 0319 Before Execution 0 A2 0020 A1 Explanation of Example: Prior to execution. the A accumulator is unchanged.A . The two operands are subtracted to perform the comparison. in which case the low-order 8 bits of the FF1 portion are used. Example: CMP. Both registers and immediate values are sign extended internally to 20 bits before comparison. Usage: Note: This instruction can be used for both integer and fractional two’s-complement data. This instruction subtracts 8-bit operands. sign extends the low-order 8 bits of A1. Execution of the CMP. and subtracts the immediate from the accumulator.CMP. The result is not affected by the state of the saturation bit (SA).B #$24. unless the register is an accumulator. the low-order 8 bits of the register is used for the comparison. The CCR is updated based on the result of the 8-bit comparison. The result of the subtraction operation is not stored.B Operation: D–S (no parallel move) Compare Byte Assembler Syntax: CMP.B S. and the CCR is updated accordingly. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is not normalized Set if bit 7 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 7 of the result Freescale Semiconductor Instruction Set Details A-99 .B instruction automatically sign extends the immediate value to 20 bits.B (no parallel move) Description: Compare 8-bit portions of two registers or a register and an immediate value.D CMP. When a register is specified.

EEE 0 1 0 1 1 1 E E E 1 0 0 0 0 1 0 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 CMP.EEE #<0–31>.B Compare the 8-bit byte portions of two data registers Compare the byte portion of a data register with an immediate integer 0–31 Compare with a 9-bit signed immediate integer Instruction Opcodes: 15 12 11 8 7 4 3 0 CMP.B #xxx.B Instruction Fields: Operation CMP.CMP.EEE #xxx.B #<0–31>.EEE Compare Byte C 1 1 2 W 1 1 2 Comments CMP.EEE 0 1 1 1 1 0 E E E a a a 0 1 0 1 Timing: Memory: 1–2 oscillator clock cycle(s) 1–2 program word(s) A-100 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .EEE 0 15 1 0 1 12 0 11 1 E E 8 E 7 0 1 B 4 B 3 B B B 0 CMP.B Operands EEE.B EEE.

compare byte at X:$3065 and A After Execution 0 A2 0020 A1 0000 A0 X Memory 7 0 07 88 66 44 22 77 55 33 11 Byte Addresses Byte Addresses $3068 $3066 $3064 $3062 SR 0300 SR 0319 Explanation of Example: Prior to execution. in which case the low-order 8 bits of the FF1 portion are used. The low-order 8 bits of the register is used for the comparison. The two operands are subtracted to perform the comparison. and then it subtracts the memory value from the accumulator.BP X:$3065. The result of the subtraction operation is not stored.BP instruction automatically sign extends the memory byte and low-order 8 bits of A1 to 20 bits.CMP. The result is not affected by the state of the saturation bit (SA).D CMP. unless the register is an accumulator. Usage: Note: This instruction can be used for both integer and fractional two’s-complement data.BP Operation: D–S (no parallel move) Compare Byte (Byte Pointer) Assembler Syntax: CMP. Execution of the CMP.BP (no parallel move) Description: Compare a byte in memory with the 8-bit portion of a register. and the CCR is updated accordingly. Example: CMP. This instruction subtracts 8-bit operands. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is not normalized Set if bit 7 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 7 of the result Freescale Semiconductor Instruction Set Details A-101 . the 36-bit A accumulator contains the value $0:0020:0000. and location $3065 in data memory contains $44. Note that this address is equivalent to the upper byte of word address $1832. Both the register and the byte located in memory are sign extended internally to 20 bits before the comparison.A Before Execution 0 A2 0020 A1 7 $3068 $3066 $3064 $3062 0000 A0 X Memory 0 07 88 66 44 22 77 55 33 11 . the A accumulator is unchanged. The CCR is updated based on the result of the 8-bit comparison.BP S.

EEE X:xxxxxx.BP X:xxxx.BP X:xxxxxx.BP Instruction Fields: Operation CMP.EEE 0 1 0 1 1 1 E E E 1 0 0 0 1 1 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP.EEE 1 0 1 1 1 0 0 1 0 1 A 1 A E A E 0 E A 1 1 0 1 0 A 0 A 1 A 1 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 2–3 oscillator clock cycles 2–3 program words A-102 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .BP Compare Byte (Byte Pointer) Operands X:xxxx.EEE C 2 3 W 2 3 CMP.BP Comments Compare memory byte with register Instruction Opcodes: 15 12 11 8 7 4 3 0 CMP.CMP.

32-bit compare of Y and A After Execution 0000 A0 0000 Y0 SR 0300 0 A2 0020 A1 0024 Y1 SR 0000 A0 0000 Y0 0319 This instruction can be used for both integer and fractional two’s-complement data.A instruction automatically sign extends both operands to 36 bits and then subtracts the Y register from the accumulator. The result of the subtraction operation is not stored.D CMP.CMP.L S. The CCR is updated based on the result of the 32-bit comparison. Usage: Note: Example: CMP. The result is not affected by the state of the saturation bit (SA). Execution of the CMP.L Y. The two operands are subtracted to perform the comparison. or a register and a 16-bit immediate value (sign extended to 32 bits). and the CCR is updated accordingly. This instruction subtracts 32-bit operands. a register and a long word in memory. both registers are unchanged.L (no parallel move) Description: Compare 32-bit portions of two registers.A . the 36-bit A accumulator contains the value $0:0020:0000. All values are sign extended internally to 36 bits before the comparison.L Operation: D–S (no parallel move) Compare Long Assembler Syntax: CMP.L Y. Before Execution 0 A2 0020 A1 0024 Y1 Explanation of Example: Prior to execution. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 36-bit result is in use Set if the 36-bit result is not normalized Set if bit 31 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 31 of the result Freescale Semiconductor Instruction Set Details A-103 .

FFF X:xxxx. sign extended to 32 bits.fff 0 1 0 1 1 1 f f f 1 0 0 0 0 1 1 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 CMP.fff 1 0 1 1 1 0 0 1 0 1 A 1 A f A f 0 f A 1 1 0 1 0 A 0 A 1 A 1 A 1 AAAAAAAAAAAAAAAA Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) A-104 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L X:xxxxxx.L Compare the 32-bit long portions of two data registers or accumulators Compare memory long with a data register Compare a 16-bit immediate value.fff X:xxxxxx.L Instruction Fields: Operation CMP.L #xxxx.CMP.fff 0 1 0 1 1 1 f f f 1 0 0 0 1 1 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP.fff Compare Long C 1 2 3 2 W 1 2 3 2 Comments CMP.FFF 0 15 1 1 1 12 1 11 0 F F 8 F 7 b b b 4 0 3 1 1 1 0 CMP.L Operands FFF.L X:xxxx. with a data register Instruction Opcodes: 15 12 11 8 7 4 3 0 CMP.fff #xxxx.L FFF.

Example: CMP.W S.W Operation: D–S (no parallel move) Compare Word Assembler Syntax: CMP. Execution of the CMP. The CCR is updated based on the 16-bit result. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is not normalized Set if bit 15 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 15 of the result Freescale Semiconductor Instruction Set Details A-105 . The CCR is updated based on the result of the subtraction. The result of the subtraction operation is not stored. and the CCR is updated based on the result. compare Y0 and A After Execution 0000 A0 0024 Y0 SR 0300 0 A2 0020 A1 2000 Y1 SR 0000 A0 0024 Y0 0319 Before Execution 0 A2 0020 A1 2000 Y1 Explanation of Example: Prior to execution. with the exception of the U and E bits. Usage: Note: This instruction can be used for both integer and fractional two’s-complement data. The operands are subtracted. the 36-bit A accumulator contains the value $0:0020:0000. This instruction subtracts 16-bit operands. the FF1 portion is compared. Five-bit immediate values are zero extended to 20 bits.D CMP.CMP. When an accumulator is used as one of the operands.W (no parallel move) Description: Compare two 16-bit operands.W Y0.A .W Y0.A instruction automatically sign extends the 16-bit value in Y0 to 20 bits and subtracts the result from the FF2:FF1 portion of the A accumulator. Neither the Y0 nor the A registers are changed. and the 16-bit Y0 register contains the value $0024. Registers and 16-bit immediate values are sign extended internally to 20 bits before the subtraction is performed. which are based on the 20-bit result.

EEE #xxxx.W Operands EEE.W Instruction Fields: Operation CMP.CMP.EEE X:xxxx.EEE #<0–31>.EEE X:(Rn+xxxx).EEE X:(SP–xx).EEE X:(Rn).EEE Compare Word C 1 2 3 3 2 3 1 2 W 1 1 2 1 2 3 1 2 Comments CMP.EEE X:xxxxxx.W Compare the 16-bit word portions of two data registers or accumulators Compare memory word with a data register or the word portion of an accumulator Compare the word portion of a data register with an immediate integer 0–31 Compare the word portion of a data register with a signed 16-bit immediate A-106 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

EEE 0 15 1 1 1 12 1 11 0 E E 8 E 7 a a a 4 0 3 1 1 0 0 CMP.W X:xxxx.W X:(SP–xx).DD 0 15 1 0 1 12 1 11 1 1 D 8 D 7 0 0 B 4 B 3 B B B 0 CMP.W #<0–31>.FF 0 15 1 0 0 12 1 11 1 0 F 8 F 7 1 0 1 4 R 3 1 R R 0 CMP.CMP.DD 0 1 0 1 1 1 1 D D 1 0 1 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP.W #<0–31>.W X:(Rn+xxxx).DD 0 15 1 0 1 12 1 11 0 1 D 8 D 7 1 a a 4 a 3 a a a 0 CMP.W 8 7 4 3 0 12 11 CMP.W #xxxx.DD 0 1 0 1 1 1 1 D D 1 0 0 0 1 0 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP.FF 0 15 1 0 0 12 1 11 1 0 F 8 F 7 0 0 B 4 B 3 B B B 0 CMP.FF 0 15 1 0 0 12 1 11 0 0 F 8 F 7 1 a a 4 a 3 a a a 0 CMP.DD 0 1 0 1 1 1 1 D D 1 0 0 0 0 0 0 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 CMP.DD 0 15 1 0 1 12 1 11 1 1 D 8 D 7 1 0 1 4 R 3 1 R R 0 CMP.W X:(SP–xx).W X:xxxx.W #xxxx.W X:(Rn).W X:(Rn).FF 0 1 0 0 1 1 0 F F 1 0 0 0 1 0 0 AAAAAAAAAAAAAAAA Freescale Semiconductor Instruction Set Details A-107 .W Instruction Opcodes: 15 Compare Word CMP.FF 0 1 0 0 1 1 0 F F 1 0 0 0 0 0 0 iiiiiiiiiiiiiiii 15 12 11 8 7 4 3 0 CMP.FF 0 1 0 0 1 1 0 F F 1 0 1 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP.W EEE.W X:(Rn+xxxx).

CMP.DD 1 0 1 1 1 0 0 1 0 1 A 1 A 1 A D 0 D A 1 1 0 1 0 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 1–3 oscillator clock cycle(s) 1–3 program word(s) A-108 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .FF 1 0 1 1 1 0 0 0 0 1 A 1 A 0 A F 0 F A 1 1 0 1 0 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 CMP.W 8 7 4 3 0 12 11 CMP.W Instruction Opcodes:(continued) 15 Compare Word CMP.W X:xxxxxx.W X:xxxxxx.

D CMPA (no parallel move) Description: Compare two AGU address registers by subtracting the source from the destination.R1 instruction subtracts R0 from R1 and updates the CCR. R1 contains the value $002473.R1 . the R0 register contains the value $082473. compare R0 and R1 After Execution R0 R1 SR 082473 002473 0309 Before Execution R0 R1 SR 082473 002473 0300 Explanation of Example: Prior to execution. and update the CCR based on the result of the subtraction. and the status register (SR) contains $0300. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V C — — — — Set if bit 23 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a borrow occurs from bit 23 of the result Instruction Fields: Operation CMPA Operands Rn.Rn C 1 W 1 Comments 24-bit compare between two AGU registers Instruction Opcodes: 15 12 11 8 7 4 3 0 CMPA Rn.CMPA Operation: D–S (no parallel move) Compare AGU Registers Assembler Syntax: CMPA S. Execution of the CMPA R0. Example: CMPA R0.Rn 1 0 0 0 1 1 1 1 n 0 1 n R n R R Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-109 . leaving the registers unchanged. The result of the subtraction operation is not stored.

and it should be used when only 16-bit address comparisons are required. and the status register (SR) contains $0300.Rn C 1 W 1 Comments 16-bit compare between two AGU registers Instruction Opcodes: 15 12 11 8 7 4 3 0 CMPA.W (no parallel move) (no parallel move) Description: Compare the low-order 16 bits of two AGU address registers by subtracting the source from the destination.W S. Explanation of Example: Prior to execution. the R0 register contains the value $082473.Rn 1 0 0 0 1 1 1 0 n 0 1 n R n R R Timing: Memory: 1 oscillator clock cycle 1 program word A-110 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Usage: Example: CMPA. Execution of the CMPA. In this case.CMPA.W R0. compare R0 and R1 After Execution R0 R1 SR 082473 002473 0304 This instruction is provided for compatibility with the DSP56800 CMPA instruction.W Operation: D–S Compare AGU Registers (Word) Assembler Syntax: CMPA.D CMPA. R1 contains the value $002473. and update the CCR based on the result of the subtraction.W Rn. both address registers are considered equal.W Operands Rn. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V C — — — — Set if bit 15 of the result is set Set if result equals zero Set if overflow has occurred in result Set if a borrow occurs from bit 15 of the subtraction Instruction Fields: Operation CMPA. The result of the subtraction operation is not stored. leaving the registers unchanged.R1 instruction subtracts the low-order 16 bits of R0 from the low-order 16 bits of R1 and updates the CCR.W R0.R1 Before Execution R0 R1 SR 082473 002473 0300 .

Note: This instruction is equivalent to the DSP56800 DEBUG instruction. see the manual for the appropriate DSC device. Instruction Fields: Operation DEBUGEV Operands C 3 W 1 Generate a debug event Comments Instruction Opcodes: 15 12 11 8 7 4 3 0 DEBUGEV 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 Timing: Memory: 3 oscillator clock cycles 1 program word Freescale Semiconductor Instruction Set Details A-111 . Programs that are being ported from the DSP56800 should use this instruction in place of the DEBUG instruction to remain compatible with the DSP56800 behavior. For more information on the Enhanced OnCE port and hardware debugging support. Condition Codes Affected: No condition codes are affected.DEBUGEV Operation: Generate a debugging event Generate Debug Event Assembler Syntax: DEBUGEV DEBUGEV Description: Generate a debugging event in the Enhanced OnCE module.

if this state is enabled in the Enhanced OnCE unit. Condition Codes Affected: No condition codes are affected. see the manual for the appropriate DSC device. If this state is not enabled. Please see the DEBUGEV instruction for information on DSP56800–compatible debugging. then the processor simply executes two NOPs and continues program execution. Note: This instruction is not compatible with the DSP56800 DEBUG instruction.DEBUGHLT Operation: Enter the debug processing state Enter Debug Mode Assembler Syntax: DEBUGHLT DEBUGHLT Description: Enter the debug processing state and wait for Enhanced OnCE port commands. Instruction Fields: Operation DEBUGHLT Operands C 3 W 1 Comments Enter debug processing state Instruction Opcodes: 15 12 11 8 7 4 3 0 DEBUGHLT 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 Timing: Memory: 3 oscillator clock cycles 1 program word A-112 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . For more information on the Enhanced OnCE port and hardware debugging support.

The condition codes are calculated based on the 8-bit result. $FF. The result is not affected by the state of the saturation bit (SA). with a borrow (the carry bit is set). Execution of the DEC. The low-order 8 bits of the result are stored back to memory. $3068 $3066 $3064 $3062 88 66 00 22 77 55 33 11 $3068 $3066 $3064 $3062 88 66 FF 22 77 55 33 11 SR 0300 SR 0319 Explanation of Example: Prior to execution. The result is negative since bit 7 is set. Usage: Example: DEC.BP instruction decrements this value by one and generates the result. The value is internally sign extended to 20 bits before being decremented. decrement the byte at (byte) address $3065 After Execution Byte Addresses 7 X Memory 0 07 This instruction is typically used when integer data is processed.DEC. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is unnormalized Set if bit 7 of the result is set Set if the result is zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 7 of the result Freescale Semiconductor Instruction Set Details A-113 . with the exception of the E and U bits. Note that this address is equivalent to the upper byte of word address $1832. which are calculated based on the 20-bit result. Absolute addresses are expressed as byte addresses.BP D DEC. the value at byte address X:$3065 is $00.BP Operation: D–1→D Decrement Byte (Byte Pointer) Assembler Syntax: DEC.BP X:$3065 Before Execution Byte Addresses X Memory 0 7 7 0 .BP (no parallel move) (no parallel move) Description: Decrement a byte value in memory.

BP Comments Decrement byte in memory Instruction Opcodes: 15 12 11 8 7 4 3 0 DEC.DEC.BP X:xxxxxx 1 0 1 1 1 0 0 0 0 1 A 1 A 1 A 0 0 0 A 1 1 0 1 0 A 0 A 1 A 1 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 3–4 oscillator clock cycles 2–3 program words A-114 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .BP X:xxxx 0 1 0 0 1 1 1 0 0 1 0 0 0 1 1 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DEC.BP Instruction Fields: Operation DEC.BP Decrement Byte (Byte Pointer) Operands X:xxxx X:xxxxxx C 3 4 W 2 3 DEC.

L Operation: D–1→D (no parallel move) Decrement Long Assembler Syntax: DEC. the 32-bit value at location $2001:2000 is $1000:0000.L X:$2000 .L instruction subtracts this value by one and generates $0FFF:FFFF.L (no parallel move) Description: Decrement a long-word value in a register or memory. When an operand located in memory is operated on. Execution of the DEC. the low-order 32 bits of the result are stored back to memory.DEC. Usage: Example: DEC. Before Execution X Memory $2001 $2000 $1FFF 1000 0000 8000 $2001 $2000 $1FFF 0FFF FFFF 8000 SR 0300 0301 SR 0310 Explanation of Example: Prior to execution. Absolute addresses pointing to long elements must always be even aligned (that is. The condition codes are calculated based on the 32-bit result. pointing to the lowest 16 bits). decrement value in location: $2001:2000 by 1 After Execution X Memory This instruction is typically used when integer data is processed.L D DEC. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the result is in use Set if the 32-bit result is unnormalized Set if bit 31 of the result is set Set if the result is zero Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 31 of the result Freescale Semiconductor Instruction Set Details A-115 . The CCR is updated based on the result of the subtraction.

L Instruction Fields: Operation DEC.DEC.L fff 0 1 1 1 0 0 f f f 0 0 1 1 0 1 1 Timing: Memory: 1–4 oscillator clock cycle(s) 1–3 program word(s) A-116 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .L X:xxxx 0 1 0 0 1 1 1 0 0 1 0 0 0 1 1 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DEC.L Instruction Opcodes: 15 12 11 8 7 4 3 0 DEC.L X:xxxxxx 1 0 1 1 1 0 0 0 0 1 A 1 A 1 A 0 0 0 A 1 1 0 1 0 A 0 A 1 A 1 A 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DEC.L Operands fff X:xxxx X:xxxxxx Decrement Long C 1 3 4 W 1 2 3 Decrement long Decrement long in memory Comments DEC.

X0 . condition code calculations follow the rules for 20-bit arithmetic. Decr the 20 MSBs of A. Freescale Semiconductor Instruction Set Details A-117 . A Before Execution 0 A2 0001 A1 Explanation of Example: Prior to execution.W D D DEC.X0 A After Execution 0033 A0 SR 0300 0 A2 0000 A1 SR 0033 A0 0314 This instruction is typically used when integer data is processed. update R2. otherwise.W Operation: D–1→D D–1→D (one parallel move) (no parallel move) Decrement Word Assembler Syntax: DEC. A new value is read in parallel and stored in register X0. the 36-bit A accumulator contains the value $0:0001:0033. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V C Note: — — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extension portion of the result is in use Set if result is unnormalized Set if bit MSB of the result is set Set if the result is zero (20 MSB for accumulator destinations) Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 15 of the result (bit 35 for accumulators) When the destination is one of the four accumulators. The condition codes are calculated based on the 16-bit result (or on the 20-bit result for accumulators).W (one parallel move) (no parallel move) Description: Decrement a 16-bit destination by one. only the EXT and MSP portions of the accumulator are used and the LSP remains unchanged.DEC. If the destination is an accumulator.W DEC. the rules for 16-bit arithmetic apply. Usage: Example: DEC. Execution of the DEC.W A X:(R2)+.W instruction decrements by one the upper 20 bits of the A accumulator and sets the zero bit in the CCR. the address register R2 is post-incremented.

W2 Operands F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.W Instruction Fields: Operation DEC. Comments DEC. Parallel Moves: Data ALU Operation Operation DEC.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. 2.DEC.W Operands EEE X:(Rn) X:(Rn+xxxx) X:(SP–xx) X:xxxx X:xxxxxx Decrement Word C 1 3 4 4 3 4 W 1 1 2 1 2 3 Decrement word.W Decrement word in memory using appropriate addressing mode. Memory writes are allowed in this case. A-118 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .

GGG 0 15 0 1 0 12 0 11 G G G 8 F 7 0 0 1 4 0 3 m R R 0 DEC.W F GGG.W X:xxxx 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DEC.W X:(Rn) 0 15 1 0 0 12 1 11 1 1 0 8 0 7 1 0 1 4 R 3 1 R R 0 DEC.W X:(Rn+xxxx) 0 1 0 0 1 1 1 0 0 1 0 1 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DEC.X:<ea_m> 0 15 0 0 0 12 0 11 G G G 8 F 7 0 0 1 4 0 3 m R R 0 DEC.W 8 7 4 3 0 15 12 11 0 15 1 1 1 12 0 11 0 E E 8 E 7 0 0 0 4 1 3 0 1 1 0 DEC.W Instruction Opcodes: DEC.W X:(SP–xx) 0 15 1 0 0 12 1 11 0 1 0 8 0 7 1 a a 4 a 3 a a a 0 DEC.W F X:<ea_m>.W X:xxxxxx 1 0 1 1 1 0 0 0 0 1 A 1 A 1 A 0 0 0 A 1 1 0 1 0 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 1–4 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-119 .W EEE Decrement Word DEC.DEC.

DECA Operation: D–1→D Decrement AGU Register Assembler Syntax: (no parallel move) DECA D (no parallel move) DECA Description: Decrement a value in an AGU pointer register. Condition Codes Affected: The condition codes are not modified by this instruction. Instruction Fields: Operation DECA Operands Rn C 1 W 1 Comments Decrement AGU register by one Instruction Opcodes: 15 12 11 8 7 4 3 0 DECA Rn 1 0 0 0 0 1 0 0 1 0 1 1 R 0 R R Timing: Memory: 1 oscillator clock cycle 1 program word A-120 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . decrement R0 After Execution R0 002221 This instruction can be used to step backwards through a memory buffer. the R0 register contains $002222. Usage: Example: DECA R0 . Execution of the DECA R0 instruction causes the value in R0 to be reduced by one. The full 24-bit value of the pointer register is used when decrementing. and the result ($002221) is stored back in R0. Before Execution R0 002222 Explanation of Example: Prior to execution.

L D DECA.L Operands Rn C 1 W 1 Comments Decrement AGU register by two Instruction Opcodes: 15 12 11 8 7 4 3 0 DECA.L Rn 1 0 0 0 0 1 0 0 1 0 1 1 R 1 R R Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-121 . Since each long word consists of 2 words. Example: DECA. Usage: This instruction is used to step backwards through a memory buffer that is composed of long-word values. and the result ($002220) is stored back in R0.DECA. the R0 register contains $002222. Condition Codes Affected: The condition codes are not modified by this instruction. Execution of the DECA. Instruction Fields: Operation DECA.L (no parallel move) Description: Decrement a value in an AGU pointer register by two.L R0 Before Execution R0 002222 . The full 24-bit value of the pointer register is used when decrementing. this instruction can be used to step through a buffer by every other word. decrement R0 by 2 After Execution R0 002220 Explanation of Example: Prior to execution.L Operation: D–2→D Decrement Long in AGU Register Assembler Syntax: (no parallel move) DECA.L R0 instruction causes the value in the R0 to be reduced by two.

The full 24-bit value of the pointer register is used when decrementing. and the result ($002221) is stored back in R0. Execution of the DECTSTA R0 instruction causes the value in R0 to be reduced by one. testing to see that the pointer is still valid after each step. decrement R0 and then compare to 0 After Execution R0 002221 This instruction can be used to step backwards through a memory buffer. the R0 register contains $002222. Usage: Example: DECTSTA R0 Before Execution R0 002222 . SR 0308 SR 0300 Explanation of Example: Prior to execution. and the CCR is updated accordingly. updating the condition codes based on the comparison. The updated value in R0 is then compared with zero. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V C — — — — Set if bit 23 of the result is set Set if all bits in the result are zero Set if overflow has occurred in result Set if a borrow occurs from bit 23 of the result Instruction Fields: Operation DECTSTA Operands Rn C 1 W 1 Comments Decrement and test AGU register Instruction Opcodes: 15 12 11 8 7 4 3 0 DECTSTA Rn 1 0 0 0 0 1 0 0 1 0 1 0 R 1 R R Timing: Memory: 1 oscillator clock cycle 1 program word A-122 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .DECTSTA Decrement and Test AGU Register DECTSTA Operation: D–1→D D–0 (no parallel move) Assembler Syntax: DECTSTA D (no parallel move) Description: Decrement a value in an AGU pointer register and then compare the result to zero.

The DIV instruction calculates 1 quotient bit based on the divisor and the previous partial remainder. C0. this instruction will divide the destination operand (D)—dividend or numerator—by the source operand (S)—divisor or denominator—and store the result in the destination accumulator. the destination operand holds both the partial remainder and the formed quotient. which has (32 – N) bits of precision and whose N MSBs are zeros. The DIV instruction uses a non-restoring division algorithm that consists of the following operations: 1. The formed quotient occupies the low-order portion of the destination accumulator (A0 or B0. Therefore. The formed quotient is the true quotient if the true quotient is positive. once the divide is complete. One bit of the formed quotient is shifted into the LSB of the destination accumulator at the start of each DIV iteration. This condition ensures that the magnitude of the quotient is less than one (that is.D (no parallel move) DIV C. executing the DIV instruction N times produces an N-bit quotient and a 32-bit remainder. 16 DIV iterations are required. After the execution of the first DIV instruction.” on page 5-21. 2. Each DIV iteration calculates 1 quotient bit using a non-restoring division algorithm (see the description that follows). The 32-bit dividend must be a positive value that is correctly sign extended to 36 bits and that is stored in the full 36-bit destination accumulator. where N is the number of bits of precision that is desired in the quotient (1 < N < 16). valid results are obtained only when |D| < |S|. After the correct number of iterations. (The division of signed numbers is handled using the techniques documented in Section 5. The result is not affected by the state of the saturation bit (SA). For fractional division. the formed quotient must be negated.3.4. D2 Else C. it is necessary to reverse the last DIV operation and restore the remainder to obtain the true remainder. C is moved into the LSB (bit 0) of the accumulator. Freescale Semiconductor Instruction Set Details A-123 . To produce an N-bit quotient. D2 D1 D0 D1 D0 D1 + S D1 D1 – S D1 Description: This instruction is a divide iteration that is used to calculate 1 bit of the result of a division. or D0) and is a positive fraction.DIV Operation: (see following figure) If D[35] ⊕ S[15] = 1 Then Divide Iteration Assembler Syntax: DIV S. “Division. The 36-bit destination accumulator is shifted 1 bit to the left. In general. the DIV instruction is executed N times. for a full-precision (16-bit) quotient. Thus. The 16-bit divisor is a signed value and is stored in the source operand. Shift the partial remainder and the quotient. it is fractional) and precludes division by zero. The partial remainder is not a true remainder and must be corrected (due to the non-restoring nature of the division algorithm) before it may be used. If the true quotient is negative. An exclusive OR operation is performed on bit 35 of the destination operand and bit 15 of the source operand. The partial remainder occupies the high-order portion of the destination accumulator and is a signed fraction. Compare the source and destination operand sign bits.) This instruction can be used for both integer and fractional division.

” on page 5-21 shows the correct usage of this instruction for fractional and integer division routines. the addition or subtraction operation correctly sets the C bit with the next quotient bit. the source operand S is added to the accumulator. the sign bits were the same). The 16-bit source operand (signed divisor) is either added to or subtracted from the MSP of the destination accumulator (FF1 portion).” on page 5-21 for a complete description of a division algorithm. Usage: The DIV iteration instruction can be used in one of several different division algorithms. or if it is not necessary also to calculate a remainder. bit 35 after sign extension for the Y register) is changed as a result of the instruction’s left shift operation.DIV Divide Iteration DIV 3. “Division.A . Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L V C Example: DIV — Set if overflow bit V is set — Set if the MSB of the destination operand (bit 35 for an accumulator. divide A by Y0 After Execution 0000 A0 0004 Y0 0 A2 0E00 A1 2000 Y1 SR 0001 A0 0004 Y0 0301 Before Execution 0 A2 0702 A1 2000 Y1 SR 0301 Explanation of Example: This example shows only a single iteration of the division instruction. Section 5. A-124 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . discusses in detail issues related to division.4. and the result is stored back into the MSP of the destination accumulator. The division routine is greatly simplified if both operands are positive. Due to the automatic sign extension of the 16-bit signed divisor. the source operand S is subtracted from the accumulator. If the result of the exclusive OR operation was zero (that is. V is cleared — Set if MSB of the result is zero (bit 35 for an accumulator. depending on the needs of an application. Calculate the next quotient bit and the new partial remainder.3. Please refer to Section 5.3. and provides several examples. “Division. otherwise. If the result of the exclusive OR operation in the first step was one (that is.4. the sign bits were different). bit 35 after sign extension for the Y register) Y0.

DIV Instruction Fields: Operation DIV Operands FFF1.fff 0 1 1 1 1 0 f f f c c c 1 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-125 .fff Divide Iteration C 1 W 1 Divide iteration Comments DIV Instruction Opcodes: 15 12 11 8 7 4 3 0 DIV FFF1.

2. If the value in LC is greater than one. The address of each instruction is compared to the value in LA to see if it is the last instruction in the loop. the contents of the LC register are copied to the LC2 register. 3. Example 1: DO MOVE. A-126 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . This push sets the LF bit and updates the NL bit. #40. as occurs with any hardware stack push. a DO loop can be interrupted. and the NL bit in the operating mode register is copied to the LF bit. The address of the first instruction in the program loop (top-of-loop address) is pushed onto the hardware stack. and LC is loaded with the loop count that the instruction specifies. and whose range of execution is terminated by the destination operand. the LC2 register is copied to LC.A .END_CPY . Set up hardware DO loop X:(R0)+. No overhead other than the execution of the DO instruction is required to set up this loop. If a 16-bit address is specified. Instruction execution then continues at the address that immediately follows the end-of-loop address. The source operand specifies the loop count and can be either an immediate 6-bit unsigned value or an on-chip register value. DO loops can be nested up to two deep. the following events occur: 1. the upper 8 bits of LA are cleared. Copy a 32-bit memory location A10. the loop count register is checked to see if the loop should be repeated. Therefore. the instructions are actually fetched each time through the loop.D DO Operation When Loop Completes (End-of-Loop Processing): If NL == 1 LC2 → LC. If LC is equal to one. accelerating more complex algorithms. When the end of the loop is reached. The DO instruction performs hardware looping on a single instruction or a block of instructions. When a DO loop is executed.or 21-bit absolute address. When a hardware loop ends. and the LA register is loaded with the address of the last instruction word in the loop. and the destination operand is a 16. the LA2 register is copied to LA. When the DO instruction is executed. LC is decremented and the loop is re-started from the top. the loop has been executed for the proper number of times and should be exited. LC → LC2 LA → LA2 LF → NL PC → HWS0 S → LC D → LA 1 → LF Start Hardware DO Loop Assembler Syntax: DO S.L MOVE. The old contents of the LA register are copied to the LA2 register.X:(R1)+ . Instructions in the loop are then executed. LA2 → LA HWS1 → HWS0 NL → LF 0 → NL Description: Begin a hardware DO loop that is to be repeated for the number of times specified in the instruction’s source operand. When a hardware DO loop is initiated. the hardware stack is popped (and the popped value is discarded).DO Operation: HWS0 → HWS1.L END_CPY Explanation of Example: This example copies a block of forty 32-bit memory locations from one area of memory to another.

Freescale Semiconductor Instruction Set Details A-127 . Thus. the end-of-loop addresses must also be nested and are not allowed to be equal. #0. so the instructions in the body of the loop are skipped. Example 2: MOVE.2. a two-deep hardware stack allows for a maximum of two nested loops. The contents of the second HWS location (HWS1) are written into the first HWS location (HWS0).X0 X0. use one of the techniques discussed in Section 8. the end-of-loop absolute address in the source code must represent the address of the instruction after the last instruction in the loop. the NL bit is written into the LF. restoring these two registers with their values for the outer loop. When DO loops are nested. A loop count of zero can only be specified by using a register that is loaded with zero as the argument to the DO instruction.A .5. DO loops can also be nested as shown in Section 8.W . the LA2 and LC2 registers are copied into the LA and LC registers. DO MOVE.L MOVE. . “Nested Hardware Looping.4. or by placing a zero in the LC register and executing DOSLC.5. The LF is cleared by a hardware reset. so repeat loops can be nested within DO loops. Note that an immediate loop count of zero for the DO instruction is not allowed and will be rejected by the assembler.5.X:(R1)+ . When the inner loop of a nested loop terminates naturally. A loop is determined to be a nested inner loop if the OMR’s NL bit is set.” on page 8-22. The REP instruction does not use the hardware stack.END_CPY . Instruction fetches now continue at the address of the instruction that follows the last instruction in the DO loop.1. If the NL bit is not set. which causes the body of the loop to be skipped entirely. “Allowing Current Block to Finish and Then Exiting. This process occurs to accommodate the case in which the last instruction in the DO loop is a multiple-word instruction. If it is necessary to terminate a DO loop early. and execution continues with the instruction immediately following the loop body. and the NL bit is cleared.DO Start Hardware DO Loop DO Explanation of Example:(continued) One hardware stack location is used for each nested DO or DOSLC loop.” on page 8-20 and Section 8. “Nesting a DO Loop Within a DO Loop.6. The assembler generates an error message when DO loops are improperly nested. Note: The assembler calculates the end-of-loop address that is to be loaded into LA by subtracting one from the absolute address specified in the destination operand. a DO loop terminates if the count specified is zero. Thus.” on page 8-22. Loop count is zero upon entry X:(R0)+. A DO loop normally terminates when the body of the loop has been executed for the specified number of times (the end of the loop has been reached. and LC is one). Alternately.6. During the end-of-loop processing. the LA and LC registers are not modified when a loop is terminated or skipped. .L END_CPY Explanation of Example: A loop count of zero is specified. Note: Any data dependencies due to pipelining also apply to the pair of instructions formed by the last instruction in the DO loop and the first instruction of the DO loop. respectively. Copy a 32-bit memory location A10.

” The END label is located at the first instruction past the end of the DO loop. In this example. begin DO loop . nested REP loop repeat this instruction last instruction in DO loop (outside DO loop) DO Explanation of Example: This example illustrates a DO loop with a REP loop nested within the DO loop. . “Pipeline Dependencies and Interlocks.DO Example 3: DO MOVE. The DO loop executes “cnt1” times while the ASL instruction inside the REP loop executes for a number of times equal to “cnt1” × “cnt2.W END Start Hardware DO Loop #cnt1.END X:(R0). Condition Codes Affected: MR 15 LF 14 * 13 * 12 * 11 * 10 * 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C LF — L — Set when a DO loop is in progress Set if data limiting occurred Restrictions: Refer to Section 10. . “cnt1” values are fetched from memory. each value is left shifted by “cnt2” counts and is stored back in memory.X:(R0)+ : .” on page 10-26. as mentioned previously.A #cnt2 A A.4. A-128 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W REP ASL MOVE. .

If LC value is zero. SR. C.<ABS16> #<1–63>. C0. and HWS. body of loop is skipped (adds 2 instruction cycles). D.<ABS16> 1 1 1 0 1 0 0 t 0 0 B B B B B B AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DO #<1–63>.<ABS16> #<1–63>.<ABS21> DDDDD. LA. D0. C1. B1. or D1 to avoid saturation when reading the accumulator.DO Instruction Fields: Operation DO Operands #<1–63>. Only 1 instruction word in the loop (t = 1 in the opcode field). D2. LC2.<ABS16> 1 1 1 0 1 0 1 1 0 0 0 d d d d d AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DO DDDDD.<ABS21> Start Hardware DO Loop C 3 4 5 6 7 8 W 2 3 2 3 2 3 Comments DO At least 2 instruction words in the loop (t = 0 in the opcode field). Y. LC.<ABS21> 1 1 1 1 1 1 0 0 0 1 A 0 A 0 A t 0 0 A 0 1 B 1 B A B A B A B A B AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DO DDDDD. M01.<ABS21> #<1–63>. OMR. Instruction Opcodes: 15 12 11 8 7 4 3 0 DO #<1–63>. When looping with a value in an accumulator.<ABS21> 1 1 1 1 1 1 0 0 0 1 A 0 A 1 A 1 0 0 A 0 1 0 1 d A d A d A d A d AAAAAAAAAAAAAAAA Timing: Memory: 3–8 oscillator clock cycles 2–3 program words Freescale Semiconductor Instruction Set Details A-129 . Note: The immediate value of zero is not allowed.<ABS16> DDDDD. Any DDDDD register is allowed except C2. LA2. N3. use A1.

LA2 → LA HWS1 → HWS0 NL → LF 0 → NL Description: Begin a hardware DO loop that is to be repeated for the number of times specified in the loop counter (LC) register. Condition Codes Affected: MR 15 LF 14 * 13 * 12 * 11 * 10 * 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C LF — Restrictions: Set when a DO loop is in progress Refer to Section 10. A-130 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W . Example: MOVEU.W NEG MOVE. If the value in LC is zero or negative. The destination operand D can be a 16.W END #count. The END label is located at the first instruction past the end of the DO loop. See the section on the DO instruction for more information on hardware looping..or 21-bit absolute address. For a number of words in the buffer equal to “count. and writes the values back. negates them.X:(R0)+ : .LC END X:(R0)..4. begin DO loop with value in LC .” the loop reads word values from a buffer in memory. The value of LC must be loaded prior to executing this instruction.DOSLC Operation: HWS0 → HWS1. last instruction in DO loop . “Pipeline Dependencies and Interlocks. load LC register . negate value from buffer .” on page 10-26. (outside DO loop) Explanation of Example: This example illustrates a DO loop with a pre-existing value for LC. DOSLC MOVE.A A A. LA → LA2 LF → NL PC → HWS0 D → LA 1 → LF DO Loop with Value in LC Assembler Syntax: DOSLC D DOSLC Operation When Loop Completes (End-of-Loop Processing): If NL == 1 LC2 → LC. the instructions in the body of the loop are skipped.

DOSLC Instruction Fields: Operation DOSLC Operands <ABS16> <ABS21> DO Loop with Value in LC C 3 4 W 2 3 Comments DOSLC If LC ≤ 0. the body of the loop is skipped. Instruction Opcodes: 15 12 11 8 7 4 3 0 DOSLC <ABS16> 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 DOSLC <ABS21> 1 1 1 1 1 1 0 0 0 0 A 1 A 1 A 1 0 0 A 0 1 0 1 1 A 1 A 0 A 0 A 1 AAAAAAAAAAAAAAAA Timing: Memory: 3–4 oscillator clock cycles 2–3 program words Freescale Semiconductor Instruction Set Details A-131 . adding 3 additional cycles. A minimum of 2 instruction words is required in the loop. The assembler will generate an error if the loop body is less than 2 words.

Note: Restrictions: Refer to Section 10. and the NL bit is cleared. it must be read before the execution of the ENDDO instruction.A CONTINU . Initially. the LF is restored from the NL bit. if this action is desired. . restore all DO regisY0. . a JMP or BRA instruction (such as JMP NEXT) must be included after the ENDDO instruction to transfer program control to the first instruction past the end of the DO loop. get current value of loop counter (LC) compare loop counter with value in Y1 go to ONWARD if LC not equal to Y1 LC equal to Y1. Example: DO times : MOVE.W CMP JNE ENDDO ters JMP CONTINU ENDLP MOVE. execute loop ending at ENDLP for (Y0) Explanation of Example: This example illustrates the use of the ENDDO instruction to terminate the current DO loop. “Pipeline Dependencies and Interlocks. go to NEXT LC not equal to Y1. If the value of the current DO LC is needed. . The value of the LC is compared with the value in the Y1 register to determine if execution of the DO loop should continue. . Normally.4. A-132 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .A Y1. Condition Codes Affected: The condition codes are not affected by this instruction. . but this instruction can terminate a loop before normal completion. The ENDDO instruction updates the program controller registers appropriately but does not automatically jump past the end of the loop.W ENDLP : : #$1234. The contents of the second HWS location are written into the first HWS location.ENDDO Operation: If NL == 1 LC2 → LC.ENDLP .X0 . The ENDDO instruction updates certain program controller registers but does not automatically jump past the end of the DO loop.” on page 10-26. and the top-of-loop address is purged from the HWS. This must be done explicitly by the programmer if it is desired. Thus. a hardware DO loop is terminated when the last instruction of the loop is executed and the current LC equals one. . continue DO loop (last instruction in DO loop) (first instruction AFTER DO loop) LC. LA2 → LA HWS1 → HWS0 NL → LF 0 → NL End Current DO Loop Assembler Syntax: ENDDO ENDDO Description: Terminate the current hardware DO loop immediately.

ENDDO Instruction Fields: Operation ENDDO Operands End Current DO Loop C 1 W 1 Comments ENDDO Remove one value from the hardware stack and update the NL and LF bits appropriately Note: Does not branch to the end of the loop Instruction Opcodes: 15 12 11 8 7 4 3 0 ENDDO 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-133 .

and the 36-bit B accumulator contains the value $5:5555:CC89. and store the result in the destination. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V — Set if bit 31 of accumulator result or the MSB of the register result is set — Set if bits 31–0 of accumulator result or all bits of the register result are zero — Always cleared A-134 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The remaining bits of the destination accumulator are not affected. If an exclusive OR of a 16-bit immediate value with a register or memory location is desired. The other bits of the destination remain unchanged.Exclusive OR of Y with B10 After Execution CC89 B0 FF00 Y0 SR 030F 5 B2 AA55 B1 FF00 Y1 SR 3389 B0 FF00 Y0 0309 This instruction is used for the logical exclusive OR of two registers. Usage: Example: EOR.L operation is performed on the source and bits 31–16 of the destination.fff (no parallel move) C.F (one parallel move) where ⊕ denotes the logical exclusive OR operator Description: Perform a logical exclusive OR operation on the source operand with the destination operand.L Y.L EOR.L Operation: S ⊕ D→ D (no parallel move) S ⊕ D → D (one parallel move) Logical Exclusive OR Long Assembler Syntax: EOR.EOR. The EOR. The result is not affected by the state of the saturation bit (SA). This instruction is a 32-bit operation. Before Execution 5 B2 5555 B1 FF00 Y1 Explanation of Example: Prior to execution.L EOR. the EOR.L FFF. the 32-bit Y register contains the value $FF00:FF00. The the extension portion (B2) is not affected by the operation.B .L Y. If the source is a 16-bit register.B instruction performs a logical exclusive OR operation on the 32-bit value in the Y register with bits 31–0 of the B accumulator (B10) and stores the 36-bit result in the B accumulator. If the destination is a 36-bit accumulator. the EORC instruction is appropriate. the exclusive OR operation is performed on the source with bits 31–0 of the accumulator.

Instruction Opcodes: 15 12 11 8 7 4 3 0 EOR.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. 2.L C.F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.L2 Operands C.X:<ea_m> 0 15 0 0 1 12 1 11 G G G 8 F 7 0 1 0 4 0 3 m R R 0 EOR.L Logical Exclusive OR Long Operands FFF.EOR.L Parallel Moves: Data ALU Operation Operation EOR. EOR.fff 0 1 1 1 1 0 f f f b b b 1 1 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-135 .The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.F GGG.L Instruction Fields: Operation EOR.fff C 1 W 1 Comments 32-bit exclusive OR (XOR). Memory writes are allowed in this case.L C.L FFF.F X:<ea_m>.GGG 0 15 0 1 1 12 1 11 G G G 8 F 7 0 1 0 4 0 3 m R R 0 EOR.

If an exclusive OR of a 16-bit immediate value with a register or memory location is desired.B instruction performs a logical exclusive OR operation on the 16-bit value in the Y1 register with bits 31–16 of the B accumulator (B1) and stores the 36-bit result in the B accumulator. the EORC instruction is appropriate. The remaining bits of the destination accumulator are not affected. the 16-bit Y1 register contains the value $FF00.W Operation: Logical Exclusive OR Word Assembler Syntax: EOR.W EOR.W S.Exclusive OR of Y1 with B1 After Execution 6789 B0 8000 Y0 SR 030F 5 B2 AA55 B1 FF00 Y1 SR 6789 B0 8000 Y0 0309 Before Execution 5 B2 5555 B1 FF00 Y1 This instruction is used for the logical exclusive OR of two registers.D EOR.EOR. The EOR.W Y1. and the 36-bit B accumulator contains the value $5:5555:6789.D S. and store the result in the destination. This instruction is a 16-bit operation. Explanation of Example: Prior to execution. The lower word of the accumulator (B0) and the extension byte (B2) are not affected by the operation. If the destination is a 36-bit accumulator. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V — Set if bit 31 of accumulator result or MSB of register result is set — Set if bits 31–16 of accumulator result or all bits of register result are zero — Always cleared A-136 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The result is not affected by the state of the saturation bit (SA).W (no parallel move) (no parallel move) S ⊕ D → D (no parallel move) S ⊕ D[31:16] → D[31:16] (no parallel move) where ⊕ denotes the logical exclusive OR operator Description: Perform a logical exclusive OR operation on the source operand (S) with the destination operand (D). Usage: Example: EOR.W Y1. the exclusive OR operation is performed on the source with bits 31–16 of the accumulator.B .

W Instruction Fields: Operation EOR.W Logical Exclusive OR Word Operands EEE.W Instruction Opcodes: 15 12 11 8 7 4 3 0 EOR.EOR.EEE C 1 W 1 Comments 16-bit exclusive OR (XOR) EOR.W EEE.EEE 0 1 1 1 1 0 E E E a a a 1 0 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-137 .

Exclusive OR with immediate data After Execution X:$5000 SR 5AA5 0300 Before Execution X:$5000 SR 5555 0300 Explanation of Example: Prior to execution. Bits 14–10 of the mask operand must be cleared. Execution of the instruction tests the state of bits 4–11 in X:$5000. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C For destination operand SR: All SR bits except bits 14–10 are updated with values from the bitfield unit.” This instruction performs a read-modify-write operation on the destination and requires two destination accesses. For other destination operands: L — Set if data limiting occurred during 36-bit source move C — Set if all bits specified by the mask are set Cleared if at least 1 bit specified by the mask is not set Note: If all bits in the mask are cleared. and store the results back into the destination.X:$5000. Instruction Fields: Refer to the section on the BFCHG instruction for legal operand and timing information.D EORC (no parallel move) (no parallel move) #xxxx ⊕ X:<ea> → X:<ea>(no parallel move) #xxxx ⊕ D → D(no parallel move) where ⊕ denotes the logical exclusive OR operator Implementation Note: This instruction is implemented by the assembler as an alias to the BFCHG instruction. and it uses the 16-bit immediate value as the bit mask. C is also modified as described in “Condition Codes Affected. the instruction executes two NOPs and sets the C bit.X:<ea> #iiii. the 16-bit X memory location X:$5000 contains the value $5555. A-138 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . This instruction will dis-assemble as a BFCHG instruction.EORC Operation: Logical Exclusive OR Immediate Assembler Syntax: EORC EORC #iiii. Example: EORC #$0FF0. and then complements the bits. Description: Perform a logical exclusive OR operation on a 16-bit immediate data value with the destination operand (D). does not set C (because all of the selected bits were not set).

restoring 21-bit PC and SR from the stack.2.2. Instruction Fields: Operation FRTID Operands C 2 W 1 Comments Delayed return from interrupt.2.” on page 9-6. then return from fast interrupt service routine Description: Refer to Section 9.3. “Delayed Instruction Restrictions.3. “Fast Interrupt Processing. must fill 2 word slots Instruction Opcodes: 15 12 11 8 7 4 3 0 FRTID 1 1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 Timing: Memory: 2 oscillator clock cycles 1 program word Freescale Semiconductor Instruction Set Details A-139 .FRTID Operation: Delayed Return from Fast Interrupt Assembler Syntax: FRTID FRTID Swap shadow registers. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C All bits are set according to the value removed from the stack Restrictions: Refer to Section 4.” on page 4-14.

Usage: The ILLEGAL instruction provides a means for testing the interrupt service routine that is executed when an illegal instruction is encountered. This instruction is made available so that code can be written to test and verify interrupt handlers for illegal instructions. Since REP is uninterruptable. Of course. Instruction Fields: Operation ILLEGAL Operands C 4 W 1 Comments Execute the illegal instruction exception. If the ILLEGAL instruction is in a DO loop at the LA and the instruction at the LA – 1 is being interrupted. The ILLEGAL instruction is not used in normal programming. the ILLEGAL interrupt service routine should abort further processing. and so on are located at the LA. and the processor should be re-initialized. This capability allows a user to verify that the interrupt service routine can correctly recover from an illegal instruction and re-start the application.ILLEGAL Operation: Illegal Instruction Interrupt Assembler Syntax: ILLEGAL ILLEGAL (no parallel move) Begin illegal instruction exception routine Description: Normal instruction execution is suspended. Condition Codes Affected: The condition codes are not affected by this instruction. After servicing the interrupt. Example: ILLEGAL Explanation of Example: See the description. REP. This situation is due to the same mechanism that causes LC to be decremented twice if JSR. then LC will be decremented twice. and illegal instruction exception processing is initiated. The purpose of the illegal interrupt is to force the DSC into an illegal instruction exception for test purposes. program control returns to the address of the second word that follows the ILLEGAL instruction. the result of repeating an ILLEGAL instruction is that the interrupt is not taken until after the REP completes. Executing an ILLEGAL instruction is a fatal error. Instruction Opcodes: 15 12 11 8 7 4 3 0 ILLEGAL 1 1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 Timing: Memory: 4 oscillator clock cycles 1 program word A-140 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the exception routine should indicate this condition and cause the system to be re-started. The interrupt priority level bits (I1 and I0) are set to 11 in the status register.

Y Before Execution 0 A2 0 B2 0002 A1 0004 B1 0000 Y1 SR FFFF A0 1234 B0 0002 Y0 0300 After Execution 0 A2 0 B2 0002 A1 0004 B1 0000 Y1 SR FFFF A0 1234 B0 000A Y0 0310 Explanation of Example: Prior to execution.L (no parallel move) Description: Multiply the two signed 16-bit source operands.L A1.L Operation: D + (S1 × S2) → D Integer Multiply with Accumulate Long Assembler Syntax: (no parallel move) IMAC. adds the resulting sign-extended product to the 32-bit Y register. and stores the 32-bit signed result ($0000:000A) into Y. the A accumulator contains the value $0:0002:FFFF.S2.D IMAC. Example: IMAC. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L E U N Z V — — — — — — Set if overflow has occurred in result Set if the extension portion of the result is in use Set if the result is unnormalized Set if bit 35 (or 31) of the result is set Set if the result is zero Set if overflow has occurred in result Condition codes are calculated based on the 36-bit result if the destination is an accumulator.L S1. the B accumulator contains $0:0004:1234. If an accumulator is used as the destination. and on the 32-bit result if the destination is the Y register.B1. and add the 32-bit integer product to the destination (D). Both source operands must be located in the FF1 portion of an accumulator. Freescale Semiconductor Instruction Set Details A-141 . The result is not affected by the state of the saturation bit (SA).L instruction multiplies the 16-bit signed value in A1 by the 16-bit signed value in B1. The destination for this instruction can be an accumulator or the Y register. and the 32-bit Y register contains $0000:0002.IMAC. the product is first sign extended from bit 31 and a 36-bit addition is then performed. Execution of the IMAC.

L Instruction Fields: Operation IMAC.L FFF1.IMAC.FFF1.L Integer Multiply with Accumulate Long Operands FFF1.fff 0 1 1 0 1 1 f f f J J J J J 0 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-142 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .FFF1.L Integer 16 × 16 multiply-accumulate with 32-bit result Instruction Opcodes: 15 12 11 8 7 4 3 0 IMAC.fff C 1 W 1 Comments IMAC.

the A accumulator contains the value $0:FFFF:0002.Y 0 1 1 1 0 0 1 0 1 q q q 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-143 .5.Y Operands B0. multiply unsigned A0 and signed B1. and add the 32-bit integer product to the destination (D).” on page 5-32 for an example that uses the IMACUS instruction.3. Condition Codes Affected: The condition codes are not modified by this instruction.Y C0.B1. The order of the registers is important. See Section 5. The first source register (S1) must contain the unsigned value. add to Y After Execution 0 A2 0 B2 FFFF A1 FFFE B1 0000 Y1 0002 A0 1234 B0 0000 Y0 Explanation of Example: Prior to execution.Y A0. the B accumulator contains $0:FFFE:1234.l. Execution of the IMACUS instruction multiplies the 16-bit unsigned value in A0 by the 16-bit signed value in B1.IMACUS Operation: D + (S1 × S2) → D Integer MAC Unsigned and Signed Assembler Syntax: IMACUS S1.q2.Y Before Execution 0 A2 0 B2 FFFF A1 FFFE B1 0000 Y1 0002 A0 1234 B0 0004 Y0 .Y C 1 W 1 Comments Integer 16 × 16 multiply-accumulate: F0 (unsigned) × F1 (signed) Instruction Opcodes: 15 12 11 8 7 4 3 0 IMACUS q1. and stores the result ($0000:0000) into Y.C1. and the second source (S2) must contain the signed value to produce the correct integer multiplication.h.D IMACUS (no parallel move) (S1 unsigned. S2 signed) Description: Multiply one unsigned 16-bit source operand by one signed 16-bit operand. The result is not affected by the state of the saturation bit (SA). and the 32-bit Y register contains $0000:0004. Usage: This instruction is used to perform extended-precision multiplication calculations.S2.D1. The destination for this instruction is always the Y register.A1. for example.C1. adds the resulting 32-bit product to the 32-bit Y register.B1.C1. “Multi-Precision Integer Multiplication. It provides a method for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication is performed. Example: IMACUS A0.D1.Y C0.Y B0.D1.Y A0.Y A0.. Instruction Fields: Operation IMACUS A0.

C1.D IMACUU (no parallel move) (S1 unsigned. See Section 5. Execution of the IMACUU instruction multiplies the 16-bit unsigned value in A0 by the 16-bit unsigned value in B1.C1.A1.q2.5. Example: IMACUU A0.D1.Y C 1 W 1 Comments Integer 16 × 16 multiply-accumulate: F0 (unsigned) × F1 (unsigned) Instruction Opcodes: 15 12 11 8 7 4 3 0 IMACUU q1. S2 unsigned) Description: Multiply the two unsigned 16-bit source operands (S1 and S2). add to Y After Execution 0 A2 0 B2 FFFF A1 FFFE B1 0002 Y1 0002 A0 1234 B0 0000 Y0 Explanation of Example: Prior to execution.Y 0 1 1 1 0 0 1 1 1 q q q 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word A-144 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .D1.Y B0.3.Y C0.Y Before Execution 0 A2 0 B2 FFFF A1 FFFE B1 0000 Y1 0002 A0 1234 B0 0004 Y0 .Y A0. and the 32-bit Y register contains $0000:0004.Y C0. adds the resulting 32-bit product to the 32-bit Y register. Usage: This instruction is used to perform extended-precision multiplication calculations. Condition Codes Affected: The condition codes are not modified by this instruction. “Multi-Precision Integer Multiplication. the A accumulator contains the value $0:FFFF:0002.IMACUU Operation: D + (S1 × S2) → D Integer MAC Two Unsigned Values Assembler Syntax: IMACUU S1. and stores the 32-bit unsigned result ($0002:0000) into Y. The result is not affected by the state of the saturation bit (SA).D1.C1.” on page 5-32 for an example that uses the IMACUU instruction.l. It provides a method for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication is performed.B1.S2.Y A0.B1. the B accumulator contains $0:FFFE:1234. Instruction Fields: Operation IMACUU Operands A0. for example.Y A0. and add the 32-bit integer product to the destination (D). The destination for this instruction is always the Y register.h. multiply unsigned in A0 and B1.Y B0.

Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L E U N Z V — — — — — — Set if overflow has occurred in result Set if the extension portion of the result is in use Set if the result is unnormalized Set if bit 35 (or 31) of the result is set Set if the result is zero Set if overflow has occurred in result Condition codes are calculated based on the 36-bit result if the destination is an accumulator. Y0.L A1. integer mult with 32-bit result After Execution 0 A2 0 B2 0002 A1 FFFE B1 FFFF Y1 SR FFFF A0 1234 B0 FFFC Y0 0318 Explanation of Example: Prior to execution. The negative bit is set to indicate the sign of the result.IMPY.Y Before Execution 0 A2 0 B2 0002 A1 FFFE B1 0001 Y1 SR FFFF A0 1234 B0 37A2 Y0 0300 . the result is sign extended from bit 31 into the extension portion (FF2) of the accumulator. Both source operands must be located in the FF1 portion of an accumulator or in X0. and the 32-bit Y register contains $0001:37A2.L instruction multiplies the 16-bit (signed) positive value in A1 by the (signed) negative 16-bit value in B1. and place the 32-bit product in the destination (D). Freescale Semiconductor Instruction Set Details A-145 . the B accumulator contains $0:FFFE:1234. and stores the (signed) 32-bit negative result ($FFFF:FFFC) into Y. the A accumulator contains the value $0:0002:FFFF.L S1. Example: IMPY. If an accumulator is used for the destination.B1. and on the 32-bit result if the destination is the Y register. The destination for this instruction can be an accumulator or the Y register.L (no parallel move) Description: Multiply the two signed 16-bit source operands. or Y1.L Operation: S1 × S2 → D Integer Multiply Long Assembler Syntax: (no parallel move) IMPY. Execution of the IMPY.D IMPY. The result is not affected by the state of the saturation bit (SA).S2.

L FFF1.L Instruction Fields: Operation IMPY.IMPY.fff Integer 16 × 16 multiply with 32-bit result Instruction Opcodes: 15 12 11 8 7 4 3 0 IMPY.L Operands Integer Multiply Long C 1 W 1 Comments IMPY.L FFF1.FFF1.fff 0 1 1 0 1 1 f f f J J J J J 0 1 Timing: Memory: 1 oscillator clock cycle 1 program word A-146 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .FFF1.

and A2 is sign extended. the A accumulator contains the value $4:0002:1234.Y0.W instruction integer multiplies the (signed) positive value in A1 and the (signed) negative value in Y0.D IMPY. while the lowest 16 bits are stored in the destination register. The result is not affected by the state of the saturation bit (SA).W A1. The order of the first two operands is not important. When SA or CM are set.S2. signed.W Operation: S1 × S2 → D Integer Multiply Word Assembler Syntax: (no parallel move) IMPY. If the destination is an accumulator. In this case.W (no parallel move) Description: Perform an integer multiplication on the two 16-bit. Example: IMPY. Usage: This instruction is useful in general computing when it is necessary to multiply two integers and the nature of the computation can guarantee that the result fits in a 16-bit destination. and store the lowest 16 bits of the integer product in the destination (D). Freescale Semiconductor Instruction Set Details A-147 . integer 16-bit multiplication After Execution F A2 FFFC A1 2000 Y1 SR 1234 A0 FFFE Y0 0308 Explanation of Example: Prior to execution. and the data ALU register Y0 contains the 16-bit (signed) negative integer value $FFFE. The V bit is set if the calculated integer product does not fit into 16 bits. it is better to place the result in the MSP (FF1 portion) of an accumulator because more instructions have access to this portion than to the other portions of the accumulator. the product is stored in the MSP with sign extension while the LSP remains unchanged. Execution of the IMPY.A Before Execution 4 A2 0002 A1 2000 Y1 SR 1234 A0 FFFE Y0 0300 . the N bit is set to the value in bit 15 of the result. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C L N Z V Note: — — — — Set if overflow has occurred in the 16-bit result Set if bit 15 of the result is set Set if the 16-bit result or 20 MSBs of a destination accumulator equal zero Set if overflow occurs in the 16-bit result A 31-bit integer product is calculated for this instruction. The negative bit is set to indicate the sign of the result.IMPY.W S1. When SA and CM are zero. the N bit is set to the value in bit 30 of the internally computed result. integer source operands (S1 and S2). and stores the (signed) negative result ($FFFC) in A1. A0 remains unchanged.

W Instruction Fields: Operation IMPY.FFF Y0.FFF 0 1 1 1 0 0 F F F Q Q Q 1 0 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-148 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .Q2.Y0.FFF Integer Multiply Word C 1 W 1 Comments IMPY.W Operands Y1.FFF C1. Note: Assembler also accepts the first two operands when they are specified in the opposite order.Y1. the LSP portion is unchanged by the instruction.Y1.FFF B1.Y0.FFF Y1.Y0. When the destination is the Y register or an accumulator.Y0.FFF A1.IMPY.W Q1.FFF Y0.X0.FFF C1.W Integer 16 × 16 multiply with 16-bit result. Instruction Opcodes: 15 12 11 8 7 4 3 0 IMPY.X0.

Execution of the IMPYSU instruction multiplies the 16-bit (signed) negative value in A1 by the 16-bit (unsigned) positive value in B0 and stores the (signed) negative result ($FFFF:FFFC) into Y.l. The destination for this instruction is always the Y register. The result is not affected by the state of the saturation bit (SA). It provides a method for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication is performed.Y C 1 W 1 Comments Integer 16 × 16 multiply: F1 (signed) × F0 (unsigned) Instruction Opcodes: 15 12 11 8 7 4 3 0 IMPYSU q1.D0. and the 32-bit Y register contains $1234:5678. Condition Codes Affected: The condition codes are not modified by this instruction.Y B1. and place the 32-bit integer product in the destination (D).S2. multiply signed A1 to unsigned B0.IMPYSU Operation: S1 × S2 → D Integer Multiply Signed and Unsigned Assembler Syntax: IMPYSU S1. Example: IMPYSU A1. Instruction Fields: Operation IMPYSU A1.Y C1.B0. The first source register (S1) must contain the signed value. Usage: This instruction is used to perform extended-precision multiplication calculations. “Multi-Precision Integer Multiplication.D0. See Section 5.C0.Y 0 1 1 1 0 0 1 0 0 q q q 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-149 . for example.C0. The order of the registers is important.Y Operands B1.q2.D IMPYSU (no parallel move) (S1 signed. the A accumulator contains the value $0:FFFE:1234.B0. store in Y After Execution 0 A2 0 B2 FFFE A1 0000 B1 FFFF Y1 1234 A0 0002 B0 FFFC Y0 Explanation of Example: Prior to execution. the B accumulator contains $0:0000:0002.h. S2 unsigned) Description: Multiply one signed 16-bit source operand by one unsigned 16-bit operand.Y C1.3.A0.Y Before Execution 0 A2 0 B2 FFFE A1 0000 B1 1234 Y1 1234 A0 0002 B0 5678 Y0 .Y A1.C0.5.” on page 5-32 for an example that uses the IMPYSU instruction.Y A1. and the second source (S2) must contain the unsigned value to produce the correct integer multiplication.D0.Y A1.

5. It provides a method for calculating one of the intermediate values that is needed when a 32-bit × 32-bit multiplication is performed.” on page 5-32 for an example that uses the IMPYUU instruction. Condition Codes Affected: The condition codes are not modified by this instruction. See Section 5. store in Y After Execution 0 A2 0 B2 FFFE A1 0000 B1 0001 Y1 1234 A0 0002 B0 FFFC Y0 Explanation of Example: Prior to execution. the 32-bit product is stored in the MSP:LSP with zeros propagated in the extension portion (FF2) of the accumulator. A-150 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .B0. and the 32-bit Y register contains $1234:5678. Usage: This instruction is used to perform extended-precision multiplication calculations. multiply two unsigned integers. the B accumulator contains $0:0000:0002. If the destination is an accumulator. for example. the A accumulator contains the value $0:FFFE:1234.Y Before Execution 0 A2 0 B2 FFFE A1 0000 B1 1234 Y1 1234 A0 0002 B0 5678 Y0 . S2 unsigned) Description: Multiply the two unsigned 16-bit source operands (S1 and S2). The result is not affected by the state of the saturation bit (SA).D IMPYUU (no parallel move) (S1 unsigned. Example: IMPYUU A1.3.IMPYUU Operation: S1 × S2 → D Unsigned Integer Multiply Assembler Syntax: IMPYUU S1.S2. Execution of the IMPYUU instruction multiplies the 16-bit (positive) unsigned value in A1 by the 16-bit unsigned value in B0 and stores the unsigned result ($0001:FFFC) into Y. “Multi-Precision Integer Multiplication. and place the 32-bit product in the destination (D).

D0.C0.l.Y A0.A0.B0.C0.l.D0.l.C0.Y C1.C0.h.D0.C0.Y C1.D0.FF C0.FF C 1 W 1 IMPYUU Comments Integer 16 × 16 multiply: F1 (unsigned) × F0 (unsigned) 1 1 Integer 16 × 16 multiply: F0 (unsigned) × F0 (unsigned) Instruction Opcodes: 15 12 11 8 7 4 3 0 IMPYUU q1.FF 0 15 1 1 1 12 0 11 0 0 F 8 F 7 q q q 4 0 3 1 1 1 0 IMPYUU q1.Y A1.FF A0.FF A0.Y A1.D0.Y B1.q2.D0.q2.FF C0.Y A1.FF A0.Y 0 1 1 1 0 0 1 1 0 q q q 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-151 .A0.Y B1.C0.IMPYUU Instruction Fields: Operation IMPYUU Unsigned Integer Multiply Operands A1.FF B0.B0.FF B0.

The condition codes are calculated based on the 8-bit result.INC. The low-order 8 bits of the result are stored back to memory. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 20-bit result is in use Set if the 20-bit result is unnormalized Set if bit 7 of the result is set Set if the result is zero Set if overflow has occurred in result Set if a carry occurs from bit 7 of the result A-152 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Execution of the INC. The value is internally sign extended to 20 bits before being incremented. the value at byte address X:$3065 is $00. with the exception of the E and U bits.BP (no parallel move) Description: Increment a byte value in memory. Note that this address is equivalent to the upper byte of word address $1832. . Usage: Example: INC.BP Operation: D+1→D Increment Byte (Byte Pointer) Assembler Syntax: (no parallel move) INC. The result is not affected by the state of the saturation bit (SA). which are calculated based on the 20-bit result.BP D INC. increment the byte at (byte) address $3065 After Execution Byte Addresses X Memory 07 7 0 Byte Addresses 7 X Memory 07 0 $3068 $3066 $3064 $3062 88 66 00 22 77 55 33 11 $3068 $3066 $3064 $3062 88 66 01 22 77 55 33 11 SR 0300 SR 0310 Explanation of Example: Prior to execution.BP X:$3065 Before Execution This instruction is typically used when integer data is processed.BP instruction increments this value by one and generates the result $01. Absolute addresses are expressed as byte addresses.

BP X:xxxx 0 1 0 0 1 1 1 0 1 1 0 0 0 1 1 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 INC.BP Instruction Fields: Operation INC.BP Instruction Opcodes: 15 12 11 8 7 4 3 0 INC.BP X:xxxxxx 1 0 1 1 1 0 0 0 0 1 A 1 A 1 A 0 0 1 A 1 1 0 1 0 A 0 A 1 A 1 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 3–4 oscillator clock cycles 2–3 program words Freescale Semiconductor Instruction Set Details A-153 .INC.BP Increment Byte (Byte Pointer) Operands X:xxxx X:xxxxxx C 3 4 W 2 3 Comments Increment byte in memory INC.

L Operation: D+1→D (no parallel move) Increment Long Assembler Syntax: INC. pointing to the lowest 16 bits). The condition codes are calculated based on the 32-bit result. Usage: Example: INC.L instruction adds one to the A accumulator. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C E U N Z V C — — — — — — Set if the extension portion of the 36-bit result is in use Set if the 36-bit result is unnormalized Set if bit 31 of the result is set Set if the result is zero Set if overflow has occurred in result Set if a carry occurs from bit 31 of the result A-154 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the low-order 32 bits of the result are stored back to memory. Execution of the INC.INC. increment value in A by one After Execution 0000 A0 SR 0300 0 A2 0020 A1 SR 0001 A0 0310 This instruction is typically used when integer data is processed. When an operand located in memory is operated on.L Description: Increment a long-word value in a register or memory.L D (no parallel move) INC. Absolute addresses pointing to long elements must always be even aligned (that is.L A . The CCR is updated based on the result of the addition. the 36-bit A accumulator contains the value $0:0020:0000. Before Execution 0 A2 0020 A1 Explanation of Example: Prior to execution.

L X:xxxxxx 1 0 1 1 1 0 0 0 0 1 A 1 A 1 A 0 0 1 A 1 1 0 1 0 A 0 A 1 A 1 A 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 INC.INC.L Instruction Opcodes: 15 12 11 8 7 4 3 0 INC.L Operands fff X:xxxx X:xxxxxx Increment Long C 1 3 4 W 1 2 3 Increment long Increment long in memory Comments INC.L fff 0 1 1 1 0 0 f f f 0 0 1 0 0 1 1 Timing: Memory: 1–4 oscillator clock cycle(s) 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-155 .L X:xxxx 0 1 0 0 1 1 1 0 1 1 0 0 0 1 1 1 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 INC.L Instruction Fields: Operation INC.

W instruction increments by one the upper 20 bits of the A accumulator and sets the E and U bits in the CCR. A-156 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V C Note: — — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extension portion of the result is in use Set if result is unnormalized Set if MSB of the result is set Set if the result is zero (20 MSB for accumulator destinations) Set if overflow has occurred in result Set if a carry (or borrow) occurs from bit 15 of the result (bit 35 for accumulators) When the destination is one of the four accumulators.W A X:(R0)+. Usage: Example: INC. Execution of the INC. the rules for 16-bit arithmetic apply.INC. otherwise.X0 . update X0 and R0 After Execution 0033 A0 SR 0300 1 A2 0000 A1 SR 0033 A0 0330 This instruction is typically used when integer data is processed. only the EXT and MSP portions of the accumulator are used and the LSP remain unchanged. condition code calculations follow the rules for 20-bit arithmetic.W D D INC. Before Execution 0 A2 FFFF A1 Explanation of Example: Prior to execution.W Operation: D+1→D D+1→D (one parallel move) (no parallel move) Increment Word Assembler Syntax: INC. A new value is read in parallel and stored in register X0. the address register R0 is post-incremented. Increment the 20 MSBs of A and .W (one parallel move) (no parallel move) Description: Increment a 16-bit destination by one. If the destination is an accumulator.W INC. the 36-bit A accumulator contains the value $0:FFFF:0033. The condition codes are calculated based on the 16-bit result (or on the 20-bit result for accumulators).

This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. Memory writes are allowed in this case.W Increment word in memory using appropriate addressing mode.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.W Instruction Fields: Operation INC. 2.INC. Comments INC.W Operands EEE X:(Rn) X:(Rn+xxxx) X:(SP–xx) X:xxxx X:xxxxxx Increment Word C 1 3 4 4 3 4 W 1 1 2 1 2 3 Increment word.W2 Operands F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1. Parallel Moves: Data ALU Operation Operation INC. Freescale Semiconductor Instruction Set Details A-157 .

W F X:<ea_m>.W X:xxxx 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 INC.W Instruction Opcodes: INC.W F GGG.W X:xxxxxx 1 0 1 1 1 0 0 0 0 1 A 1 A 1 A 0 0 1 A 1 1 0 1 0 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA Timing: Memory: 1–4 oscillator clock cycle(s) 1–3 program word(s) A-158 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .X:<ea_m> 0 15 0 0 0 12 0 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 INC.W EEE Increment Word INC.GGG 0 15 0 1 0 12 0 11 G G G 8 F 7 0 1 1 4 0 3 m R R 0 INC.W X:(Rn+xxxx) 0 1 0 0 1 1 1 0 1 1 0 1 R 0 R R AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 INC.W X:(Rn) 0 15 1 0 0 12 1 11 1 1 0 8 1 7 1 0 1 4 R 3 1 R R 0 INC.W X:(SP–xx) 0 15 1 0 0 12 1 11 0 1 0 8 1 7 1 a a 4 a 3 a a a 0 INC.W 8 7 4 3 0 15 12 11 0 15 1 1 1 12 0 11 0 E E 8 E 7 0 0 0 4 0 3 0 1 1 0 INC.INC.

jump to LABEL if carry bit is set A A Freescale Semiconductor Instruction Set Details A-159 . program execution continues at the effective address specified in the instruction.4. the PC is incremented and program execution continues sequentially. LABEL . If the specified condition is not true. The Jcc instruction uses a 19-bit absolute address for this example.W instructions and continues with the ADD instruction. Restrictions: Refer to Section 10. “Pipeline Dependencies and Interlocks. no jump is taken.or 21-bit absolute address. then S → PC else PC + 1 → PC Jump Conditionally Assembler Syntax: Jcc S {<ABS19> or <ABS21>} Jcc Description: If the specified condition is true.” on page 10-26. the program counter is incremented by one.W LABEL ADD B.Jcc Operation: If (cc). Condition Codes Affected: The condition codes are tested but not modified by this instruction. if C is one when the JCS instruction is executed. and program execution continues with the first INC. The term “cc” specifies the following: “cc” Mnemonic CC (HS*)— carry clear (higher or same) CS (LO*)— carry set (lower) EQ— equal GE— greater than or equal GT— greater than LE— less than or equal LT— less than NE— not equal NN— not normalized NR— normalized * Only available when CM bit is set in the OMR Xdenotes the logical complement of X +denotes the logical OR operator •denotes the logical AND operator ⊕denotes the logical exclusive OR operator C=0 C=1 Z=1 N⊕V=0 Z + (N ⊕ V) = 0 Z + (N ⊕ V) = 1 N⊕V=1 Z=0 Z + (U • E) = 0 Z + (U • E) = 1 Condition Example: JCS INC.A Explanation of Example: In this example.W INC. program execution skips the two INC.W instruction. If the specified condition is false. The effective address is a 19.

Jcc Instruction Fields: Operation Jcc Operands <ABS19> <ABS21> Jump Conditionally C1 5 or 4 6 or 5 Jcc Comments W 2 3 19-bit absolute address 21-bit absolute address 1. Instruction Opcodes: 15 12 11 8 7 4 3 0 Jcc <ABS21> 1 1 1 1 1 1 0 0 0 0 A C A C A C 0 0 A 1 1 0 1 1 A 0 A C A 0 A 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 Jcc <ABS19> 1 1 1 0 0 C C C 0 1 0 1 A C A A AAAAAAAAAAAAAAAA Timing: Memory: 4–6 oscillator clock cycles 2–3 program words A-160 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The first value applies if the jump is taken. and the second applies if it is not.The clock-cycle count depends on whether the jump is taken.

4. “Pipeline Dependencies and Interlocks. Restrictions: Refer to Section 10. Instruction Fields: Operation JMP Operands (N) <ABS19> <ABS21> C 5 4 5 W 1 2 3 Comments Jump to target contained in N register 19-bit absolute address 21-bit absolute address Instruction Opcodes: 15 12 11 8 7 4 3 0 JMP <ABS21> 1 1 1 1 1 1 0 0 0 0 A 0 A 0 A 1 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 JMP (N) 1 15 1 1 0 12 0 11 1 1 1 8 0 7 0 0 1 4 1 3 1 1 1 0 JMP <ABS19> 1 1 1 0 0 0 0 1 0 1 0 1 A 1 A A AAAAAAAAAAAAAAAA Timing: Memory: 4–5 oscillator clock cycles 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-161 . program execution is transferred to the address represented by LABEL. Condition Codes Affected: The condition codes are not affected by this instruction.JMP Operation: S → PC Unconditional Jump Assembler Syntax: JMP JMP S {(N) or <ABS19> or <ABS21>} Description: Jump to program memory at the location given by the instruction’s effective address.” on page 10-26. The DSC core supports up to 21-bit program addresses.bit absolute address. Example: JMP LABEL Explanation of Example: In this example.or 21. which can be the value in the N register or a 19.

” on page 10-26. delayed JMP to label . execute the next two 1-word instructions or the next single 2-word instruction following the JMPD instruction before jumping to the destination address. first delay slot . second delay slot (unused) . must fill 2 delay slots Instruction Opcodes: 15 12 11 8 7 4 3 0 JMPD <ABS21> 1 1 1 1 1 1 0 0 0 0 A 0 A 1 A 1 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 JMPD <ABS19> 1 1 1 0 0 0 1 1 0 1 0 1 A 1 A A AAAAAAAAAAAAAAAA Timing: Memory: 2–3 oscillator clock cycles 2–3 program words A-162 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .JMPD Operation: Delayed Unconditional Jump Assembler Syntax: JMPD S {<ABS19> or <ABS21>} JMPD Execute instructions in next 2 words S→ PC Description: Jump to program memory at the location that is given by the instruction’s effective address. Condition Codes Affected: The condition codes are not affected by this instruction. That is. must fill 2 delay slots Delayed jump with 21-bit absolute address.. LABEL LABEL #1.. Instruction Fields: Operation JMPD Operands <ABS19> <ABS21> C 2 3 W 2 3 Comments Delayed jump with 19-bit absolute address.4.X0 . program execution is transferred to the address represented by LABEL after the two 1-word instructions following the JMPD instruction are executed.3. “Pipeline Dependencies and Interlocks. Refer to Section 4.W NOP . Restrictions: Refer to Section 10. Example: JMPD ADD. “Delayed Instruction Restrictions.2. but execute the following 2 words of instructions before completing the jump.” on page 4-14. JMP target address Explanation of Example: In this example.

program execution is transferred to the subroutine at the address that is represented by LABEL. jump to absolute address indicated by “LABEL” Explanation of Example: In this example.JSR Operation: SP + 1 PC SP + 1 SR S → SP → X:(SP) → SP → X:(SP) → PC Jump to Subroutine Assembler Syntax: JSR JSR S {(RRR) or <ABS19> or <ABS21>} Description: Jump to subroutine in program memory located at the effective address specified by the operand. “Pipeline Dependencies and Interlocks.4. The DSC core supports program addresses up to 21 bits wide. The operand can be a 19. Example: JSR LABEL . Instruction Fields: Operation JSR Operands (RRR) <ABS19> <ABS21> C 5 4 5 W 1 2 3 Comments Push 21-bit return address and jump to target address contained in the RRR register Push 21-bit return address and jump to 19-bit target address Push 21-bit return address and jump to 21-bit target address Instruction Opcodes: 15 12 11 8 7 4 3 0 JSR <ABS21> 1 1 1 1 1 1 0 0 0 0 A 0 A 1 A 0 0 0 A 1 1 0 1 1 A 0 A 1 A 0 A 0 AAAAAAAAAAAAAAAA 15 12 11 8 7 4 3 0 JSR (RRR) 1 15 1 1 0 12 0 11 1 1 0 8 0 7 0 0 1 4 N 3 1 N N 0 JSR <ABS19> 1 1 1 0 0 0 1 0 0 1 0 1 A 1 A A AAAAAAAAAAAAAAAA Timing: Memory: 4–5 oscillator clock cycles 1–3 program word(s) Freescale Semiconductor Instruction Set Details A-163 . Restrictions: Refer to Section 10.or 21-bit absolute address or a register.” on page 10-26. Condition Codes Affected: The condition codes are not affected by this instruction.

Example: LSL. The C bit is set because bit 31 of B1 was set prior to the execution of the instruction. and the remaining portions of the accumulator are not modified. The result is not affected by the state of the saturation bit (SA).W D LSL. D2 D1 Unchanged D0 0 Description: Logically shift 16 bits of the destination operand (D) by 1 bit to the left. and store the result in the destination.W B . Execution of the LSL. The overflow bit V is always cleared. and zero is shifted into the LSB of D1 (bit 16 if the destination is a 36-bit accumulator). Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V C — — — — Set if bit 31 of an accumulator result or bit 15 of a 16-bit register result is set Set if the MSP of result or all bits of a 16-register result are zero Always cleared Set if bit 31 of accumulator or bit 15 of a 16-bit register was set prior to the execution of the instruction A-164 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W Operation: (see following figure) Logical Shift Left Word Assembler Syntax: LSL. the result is stored in the MSP of the accumulator (FF1 portion). If the destination is a 36-bit accumulator. The N bit is also set because bit 31 of accumulator B is set.LSL. multiply B1 by 2 After Execution 00AA B0 SR 0302 6 B2 8AAA B1 SR 00AA B0 0309 Before Execution 6 B2 C555 B1 Explanation of Example: Prior to execution.W (no parallel move) C Unch.W instruction shifts the 16-bit value in the B1 register by 1 bit to the left and stores the result back in the B1 register. the 36-bit B accumulator contains the value $6:C555:00AA. The MSB of the destination (bit 31 if the destination is a 36-bit accumulator) prior to the execution of the instruction is shifted into C.

LSL.W EEE 0 1 1 1 0 0 E E E 1 1 1 0 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-165 .W Instruction Opcodes: 15 12 11 8 7 4 3 0 LSL.W Instruction Fields: Operation LSL.W EEE Logical Shift Left Word Operands C 1 W 1 Comments 1-bit logical shift left word LSL.

W (no parallel move) Unch.W Operation: (see following figure) 0 Logical Shift Right Word Assembler Syntax: LSR.W D LSR. Execution of the LSR. If the destination is a 36-bit accumulator. and the remaining portions of the accumulator are not modified.W B . the result is stored in the MSP of the accumulator (FF1 portion).LSR. The Z bit of CCR (bit 2) is also set because the result in B1 is zero. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z V C — — — — Always cleared Set if the MSP of result or all bits of a 16-register result are zero Always cleared Set if bit 31 of accumulator or bit 15 of a 16-bit register was set prior to the execution of the instruction A-166 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .W instruction shifts the 16-bit value in the B1 register by 1 bit to the right and stores the result back in the B1 register. The result is not affected by the state of the saturation bit (SA). The overflow bit (V) is always cleared. C is set by the operation because bit 0 of B1 was set prior to the execution of the instruction. the 36-bit B accumulator contains the value $F:0001:00AA. divide B1 by 2 (B1 considered unsigned) After Execution 00AA B0 SR 0302 F B2 0000 B1 SR 00AA B0 0305 Before Execution F B2 0001 B1 Explanation of Example: Prior to execution. and store the result in the destination. The LSB of the destination (bit 16 if the destination is a 36-bit accumulator) prior to the execution of the instruction is shifted into C. D2 D1 Unchanged D0 C Description: Logically shift 16 bits of the destination operand (D) by 1 bit to the right. Example: LSR. and zero is shifted into the MSB of D1 (bit 31 if the destination is a 36-bit accumulator).

W Instruction Opcodes: 15 12 11 8 7 4 3 0 LSR.LSR.W EEE 0 1 1 1 0 0 E E E 1 1 1 1 0 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-167 .W EEE Logical Shift Right Word Operands C 1 W 1 Comments 1-bit logical shift right word LSR.W Instruction Fields: Operation LSR.

Before Execution 0 A2 3456 A1 A1A2 Y1 Explanation of Example: Prior to execution. shift MSP of Y into A0 After Execution 3456 A0 A3A4 Y0 0 A2 0000 A1 A1A2 Y1 A1A2 A0 A3A4 Y0 This instruction can be used to cast an unsigned integer to a long value. Usage: Example: LSR16 Y.FFF 0 1 1 1 1 1 F F F b b b 0 1 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word A-168 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . The LSR16 instruction logically shifts the value $A1A2:A3A4 by 16 bits to the right. When the destination operand is a 16-bit register. the MSP of an accumulator or Y register is written to it. zero extending to the left. and store the result in the destination (D).FFF FFF C 1 1 W 1 1 Comments Logical shift right the first operand by 16 bits. the destination is cleared. If both the source and destination are 16-bit registers. zero extends to a full 36 bits. and places the result in the destination register A.A. the Y register contains the value to be shifted ($A1A2:A3A4).LSR16 Operation: S >> 16 → D Logical Shift Right 16 Bits Assembler Syntax: (no parallel move) LSR16 S. Condition Codes Affected: The condition codes are not affected by this instruction. If the source is an accumulator. This operation effectively places the MSP of the source register into the LSP of the destination register. placing result in the destination operand (new bits zeroed) An alternate syntax for the preceding instruction if the source and the destination are the same Instruction Opcodes: 15 12 11 8 7 4 3 0 LSR16 FFF. Instruction Fields: Operation LSR16 Operands FFF. both the extension register and MSP are shifted. . The contents of the destination register are not important prior to execution because they have no effect on the calculated value. The result is not affected by the state of the saturation bit (SA). propagating zero bits through the MSP and the extension register (for accumulator destinations).D LSR16 (no parallel move) Description: Logically shift the source operand to the right by 16 bits.

logically shift R0 to the right 1 bit After Execution R0 505050 Before Execution R0 A0A0A0 Explanation of Example: Prior to execution. and store the result back in the register.LSRA Operation: D >> 1 → D Logical Shift Right AGU Register Assembler Syntax: (no parallel move) LSRA D (no parallel move) LSRA Description: Logically shift the address register operand 1 bit to the right. Instruction Fields: Operation LSRA Operands Rn C 1 W 1 Comments Logical shift right AGU register by 1 bit Instruction Opcodes: 15 12 11 8 7 4 3 0 LSRA Rn 1 0 0 0 0 1 0 1 0 0 1 1 R 1 R R Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-169 . and stores the result ($505050) back in R0. Condition Codes Affected: The condition codes are not affected by this instruction. the R0 register contains $A0A0A0. Example: LSRA R0 . Execution of the LSRA R0 instruction shifts the value in the R0 register 1 bit to the right.

the lowest 4 bits of the X0 register contain the amount by which to shift ($4). A-170 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . the N bit is equal to bit 31 of the result. The LSRAC instruction logically shifts the value $C003 by 4 bits to the right and accumulates this result with the value that is already in accumulator A. Operand S1 is internally zero extended and concatenated with 16 zero bits to form a 36-bit value before the shift operation.LSRAC Operation: Logical Shift Right with Accumulate Assembler Syntax: LSRAC S1. Usage: Example: LSRAC Y1. Before Execution 0 A2 0000 A1 C003 Y1 Explanation of Example: Prior to execution. the Y1 register contains the value to be shifted ($C003).S2. The result is not affected by the state of the saturation bit (SA). N is equal to bit 35 of the result. and accumulate the result with the value in the destination (D).D LSRAC (no parallel move) (S1 >> S2) + D →D (no parallel move) Description: Logically shift the first 16-bit source operand (S1) to the right by the value contained in the lowest 4 bits of the second source operand (S2).A . and the destination accumulator contains $0:0000:0099. logical right shift Y1 by 4 and .X0. accumulate in A After Execution 0099 A0 8000 Y0 X0 SR 00F4 0300 0 A2 0C00 A1 C003 Y1 X0 SR 3099 A0 8000 Y0 00F4 0300 This instruction is used for multi-precision logical right shifts. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z Note: — Set if bit 35 of accumulator result is set — Set if accumulator result equals zero If the SA bit is set. if SA is cleared.

Y0.Y0.FF Y0.Y0.FF B1.FF C1.Y1.Y0.FF Y0.FF C 1 W 1 Comments LSRAC Logical word shift right with accumulation Instruction Opcodes: 15 12 11 8 7 4 3 0 LSRAC Q1.X0.Y1.X0.Q2.FF Y1.LSRAC Instruction Fields: Operation LSRAC Logical Shift Right with Accumulate Operands Y1.FF C1.FF A1.FF 0 1 1 1 0 1 0 F F Q Q Q 0 1 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-171 .

and 32-bit destinations.L S.L Operation: Multi-Bit Logical Right Shift Long Assembler Syntax: LSRR. If the shift count in a register is negative (bit 15 is set).A Before Execution F A2 F123 A1 0010 Y1 SR 3456 A0 8000 Y0 0300 . Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C N Z Note: — Set if the MSB of the result is set — Set if the result equals zero Condition code results are set according to the size of the destination operand. For 36. The result is not affected by the state of the saturation bit (SA). Y0. A-172 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . Example: LSRR. The LSRR. D >> S → D (no parallel move) Else D << –S → D (no parallel move) Description: Logically shift the second operand to the right by the value contained in the 5 lowest bits of the first operand (or by an immediate integer).L instruction logically shifts the destination accumulator 16 bits to the right and places the result back in A. left shift 32-bit A10 by Y1 After Execution 0 A2 0000 A1 0010 Y1 SR F123 A0 8000 Y0 0300 Explanation of Example: Prior to execution.L LSRR. with zero extension from bit 31 (the FF2 portion is ignored). $F:F123:3456. or the MSP of an accumulator.L (no parallel move) (no parallel move) If S[15] = 0 or S is not a register.D S. Y1.D LSRR. and store the result back in the destination (D).L Y1. the A accumulator contains the value to be shifted.LSRR. and the Y1 register contains the amount by which to shift ($10 = 16). the direction of the shift is reversed. The shift count can be a 5-bit positive immediate integer or the value contained in X0. the MSP:LSP are shifted.

LSRR.fff 0 15 1 0 0 12 1 11 1 f f 8 f 7 0 1 B 4 B 3 B B B 0 LSRR.FFF 0 1 1 1 1 1 F F F a a a 1 1 0 1 Timing: Memory: 2 oscillator clock cycles 1 program word Freescale Semiconductor Instruction Set Details A-173 .L Logical shift right by a 5-bit positive immediate integer Bi-directional logical shift destination by value in the first operand: positive –> right shift Instruction Opcodes: 15 12 11 8 7 4 3 0 LSRR.L #<0–31>.FFF C 2 2 W 1 1 Comments LSRR.L EEE.L Instruction Fields: Operation LSRR.fff EEE.L Multi-Bit Logical Right Shift Long Operands #<0–31>.

W S. logical right shift of 16-bit A1 by .A Before Execution F A2 AAAA A1 0001 Y1 SR 4567 A0 000F Y0 0300 . with zero extension from bit 31 (the FF2 portion is ignored). The LSRR.W (no parallel move) (no parallel move) (no parallel move) (no parallel move) Description: This instruction can have two or three operands.Y0. Example 1: LSRR. least 4 bits of Y0 After Execution 0 A2 5555 A1 AAAA Y1 SR 0000 A0 FFF1 Y0 0300 Explanation of Example: Prior to execution. For 36.D LSRR.D S1. and the Y1 register contains the amount by which to shift ($1). and the Y0 register contains the amount by which to shift (least 4 bits of $FFF1 = 1).and 32-bit destinations. logical right shift of 16-bit Y1 by . and store the result in the destination (D). A1 contains the value that is to be shifted ($AAAA). the Y1 register contains the value to be shifted ($AAAA). least 4 bits of Y1 After Execution 0 A2 5555 A1 0001 Y1 SR 0000 A0 000F Y0 0300 Explanation of Example: Prior to execution. The LSRR.W Y1. The shift count can be a 4-bit positive integer. The contents of the destination register are not important prior to execution because they have no effect on the calculated value.W Operation: D >> S → D S1 >> S2 → D Multi-Bit Logical Right Shift Word Assembler Syntax: LSRR. Example 2: LSRR.W instruction logically shifts the value $AAAA by 1 bit to the right and places the result in the destination register A (the LSP is cleared). Logically shift the source operand S1 or D to the right by the value contained in the lowest 4 bits of either S2 or S. only the MSP is shifted and the LSP is cleared. or the MSP of an accumulator. respectively (or by an immediate integer).A Before Execution 0 A2 3456 A1 AAAA Y1 SR 3456 A0 FFF1 Y0 0300 . A-174 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .LSRR.W LSRR. The result is not affected by the state of the saturation bit (SA).W Y1.W instruction logically shifts the zero-extended value $AAAA by 1 bit to the right and places the result in the destination register A (the LSP is cleared). a value in a 16-bit register.S2.

FFF C1.X0.Y0.W EEE.FFF C 1 1 1 W 1 1 1 Comments Logical shift right by a 4-bit positive immediate integer (sign extends into FF2) Logical shift right destination by value specified in 4 LSBs of the first operand (sign extends into FF2) Logical shift right the first operand by value specified in 4 LSBs of the second operand.FFF C1.FFF Y1.W 15 LF 14 P4 Multi-Bit Logical Right Shift Word LSRR.FFF 0 15 1 0 1 12 1 11 1 F F 8 F 7 0 1 0 4 B 3 B B B 0 LSRR.X0.Y1. sign extends into FF2 Instruction Opcodes: 15 12 11 8 7 4 3 0 LSRR.W #<0–15>.FFF EEE.W 1 V 0 C Condition Codes Affected: MR 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z N Z — Set if MSB of result is set — Set if accumulator result equals zero Instruction Fields: Operation LSRR.FFF Y0.Y0.W Q1.W Operands #<0–15>.Y0.FFF Y1. places result in FFF.FFF Y0.Q2.Y1.FFF 0 1 1 1 0 1 F F F Q Q Q 0 0 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-175 .FFF 0 15 1 1 1 12 1 11 1 F F 8 F 7 a a a 4 1 3 0 0 1 0 LSRR.LSRR.FFF A1.FFF B1.Y0.

MAC Operation: D + (S1 × S2) → D (no parallel move) D + (S1 × S2) → D (one parallel move) D + (S1 × S2) → D (two parallel reads) Multiply-Accumulate Assembler Syntax: MAC MAC MAC (+)S1.000305176).A X:(R0)+.S2.S2.000015259). the 16-bit Y0 register contains the value $0200 (or fractional value 0.019531250). two reads Before Execution 0 A2 0000 A1 FF00 Y1 X0 SR 8000 A0 0200 Y0 0280 0300 After Execution 0 A2 000A A1 FF00 Y1 X0 SR 8000 A0 0300 Y0 0288 0310 Explanation of Example: Prior to execution. Execution of the MAC instruction multiplies the 16-bit signed value in the X0 register by the 16-bit signed value in Y0 (yielding the fractional product result of $000A:0000 = 0. the high-order 16 bits of the result are then stored.X0 .” on page 5-18). the 16-bit X0 register contains the value $0280 (or fractional value 0.D S1. The fractional product is first sign extended before the 36-bit addition (or subtraction) is performed. Condition Codes Affected: MR 15 LF 14 P4 13 P3 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z 1 V 0 C SZ L E U N Z V — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extension portion of accumulator result is in use Set according to the standard definition of the U bit Set if MSB of result is set Set if accumulator result equals zero Set if overflow has occurred in accumulator result A-176 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor . In parallel. fractional MAC. and add or subtract the 32-bit fractional product to or from the destination (D).015625).Y0 X:(R3)+.D MAC (no parallel move) (one parallel move) (two parallel reads) Description: Multiply the two signed 16-bit source operands. and the two address registers (R0 and R3) are post-incremented by one. adds the resulting 32-bit product to the 36-bit A accumulator.00320435) back into the A accumulator. “Multiplication. or Y1. Both source operands must be located in the FF1 portion of an accumulator or in X0. If the destination is one of the 16-bit registers.X0. Y0.3. X0 and Y0 are updated with new values that are fetched from the data memory.D (+)S1. When the destination is a 16-bit register. Usage: This instruction is used for the multiplication and accumulation of fractional data or integer data when a full 32-bit product is required (see Section 5.3. this instruction is useful only for fractional data. and the 36-bit A accumulator contains the value $0:0000:8000 (or fractional value 0. and stores the result ($0:000A:8000 = 0.S2. Example: MAC Y0. it is first sign extended internally and concatenated with 16 zero bits to form a 36-bit operand before the operation to the fractional product.

Y0.X0.Y0. Freescale Semiconductor Instruction Set Details A-177 .F C1. Parallel Dual Reads: Data ALU Operation1 Operation MAC2 Operands Y1.F Y0.The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.Y0.Y0.F –C1. 2.X0.X0.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.F A1.F Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N X0 Y1 Y0 A B C A1 B1 1.Y0.F Y1.FFF C 1 W 1 Comments MAC Fractional multiply-accumulate.This instruction is not allowed when the XP bit in the OMR is set (that is.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode. multiplication result optionally negated before accumulation.Y0.F Y0. Parallel Moves: Data ALU Operation Operation MAC2 Operands Y1.Y1.F First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Second Memory Read Source 2 X:(R3)+ X:(R3)– Destination 2 X0 Y0 Y1 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 C 1.F C1. 2.MAC Instruction Fields: Operation MAC Multiply-Accumulate Operands (±)FFF1.Y1.F B1.F –C1.FFF1.X0. when the instructions are executing from data memory).F C1.Y1.Y0.F Y0.F Y1. Memory writes are allowed in this case.

F X:<ea_m>.reg1 X:<ea_v>.GGG 0 15 0 1 1 12 0 11 G G G 8 F 7 Q Q Q 4 1 3 m R R 0 MAC FFF1.F GGG.X:<ea_m> 0 15 0 0 0 12 1 11 G G G 8 F 7 Q Q Q 4 1 3 m R R 0 MAC Q1.X:<ea_m> Multiply-Accumulate MAC 8 7 4 3 0 15 12 11 0 15 0 0 1 12 0 11 G G G 8 F 7 Q Q Q 4 1 3 m R R 0 MAC –C1.F GGG.FFF1.reg2 –FFF1.F X:<ea_m>.Q4.Q2.F X:<ea_m>.Q2.FFF 0 15 1 1 0 12 1 11 0 F F 8 F 7 J J J 4 J 3 J 0 0 0 MAC Q1.FFF1.MAC Instruction Opcodes: MAC –C1.Q2.FFF 0 15 1 1 0 12 0 11 1 v v 8 F 7 v Q Q 4 1 3 m 0 v 0 MAC 0 1 1 0 1 1 F F F J J J J J 1 0 Timing: Memory: 1 oscillator clock cycle 1 program word A-178 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .GGG 0 15 0 1 0 12 1 11 G G G 8 F 7 Q Q Q 4 1 3 m R R 0 MAC Q3.Q2.

015625). and stores the rounded result ($0:000A:0000 = 0. If two’s-complement rounding is utilized (R bit is set).S2. followed by the rounding operation.S2. add or subtract the 32-bit fractional product to or from the third operand.9. or Y1. and the two address registers (R0 and R3) are post-incremented by one. Execution of the MACR instruction multiplies the 16-bit signed value in the X0 register by the 16-bit signed value in Y0 (yielding the fractional product result of $000A:0000 = 0. X0 and Y0 are updated with new values that are fetched from the data memory. In parallel. convergent rounding is selected. and the high-order 16 bits of the result are then stored.D MACR (no parallel move) (one parallel move) (two parallel reads) D + (S1 × S2) + r → D (no parallel move) D + (S1 × S2) + r → D (one parallel move) D + (S1 × S2) + r → D (two parallel reads) Description: Multiply the two signed 16-bit source operands. In this example. “Rounding. If the destination is one of the 16-bit registers.S2. Before Execution 0 A2 0000 A1 FF00 Y1 Explanation of Example: Prior to execution.” on page 5-43 for more information about the rounding modes. Y0. Note that the rounding operation always zeros the LSP of the result if the destination (D) is an accumulator or the Y register. the 16-bit X0 register contains the value $0280 (or fractional value 0. Refer to Section 5. The addition is then followed by the rounding operation.019531250). the 16-bit Y0 register contains the value $0200 (or fractional value 0.X0. Both source operands must be located in the FF1 portion of an accumulator or in X0.000335693.000015259). Freescale Semiconductor Instruction Set Details A-179 . and round and store the result in the destination (D). fractional with rounding After Execution 8000 A0 0200 Y0 X0 SR 0280 0300 0 A2 000A A1 FF00 Y1 X0 SR 0000 A0 0300 Y0 0288 0310 This instruction is used for the multiplication.Y0 X:(R3)+. This instruction uses the rounding technique that is selected by the R bit in the OMR.MACR Operation: Multiply-Accumulate and Round Assembler Syntax: MACR MACR MACR (+)S1. the default rounding technique (convergent rounding) is performed (bit R in the OMR is cleared).D S1. The fractional product is first sign extended before the 36-bit addition is performed. rounds the result.00320435).000305176) back into the A accumulator. the result in accumulator A is $0:000B:0000 = 0. accumulation.X0 .000305176).D S1. and rounding of fractional data. Usage: Example: MACR Y0. adds the resulting 32-bit product to the 36-bit A accumulator ($0:000A:8000 = 0. it is first sign extended internally and concatenated with 16 zero bits to form a 36-bit operand before being added to the fractional product. and the 36-bit A accumulator contains the value $0:0000:8000 (or fractional value 0. two’s-complement rounding is selected. when the R bit is set.A X:(R0)+. multiply-accumulate . When the R bit is cleared (default mode).

The case where the destination of the data ALU operation is the same register as the destination of the parallel read operation is not allowed.F A1.X0. Parallel Moves: Data ALU Operation Operation MACR2 Operands Y1.F C1.Y0.F Y0.X0.Y0.F B1. 2.F C1.FFF C 1 W 1 Comments Fractional MAC with round.Y1. A-180 DSP56800E and DSP56800EX Core Reference Manual Freescale Semiconductor .MACR Condition Codes Affected: 15 LF 14 P4 13 Multiply-Accumulate and Round MACR 1 V 0 C MR 12 P2 11 P1 10 P0 9 I1 8 I0 7 SZ 6 L 5 E CCR 4 U 3 N 2 Z P3 SZ L E U N Z V — — — — — — — Set according to the standard definition of the SZ bit (parallel move) Set if limiting (parallel move) or overflow has occurred in result Set if the extended portion of accumulator result is in use Set according to the standard definition of the U bit Set if MSB of result is set Set if result equals zero Set if overflow has occurred in result Instruction Fields: Operation MACR Operands (±)FFF1. multiplication result optionally negated before addition.F Y0.F X0 Y1 Y0 A B C A1 B1 Parallel Memory Move Source X:(Rj)+ X:(Rj)+N Destination1 X0 Y1 Y0 A B C A1 B1 X:(Rj)+ X:(Rj)+N 1.Y1.Y0.FFF1. Memory writes are allowed in this case.F Y1.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.Y0.

FFF 0 15 1 1 0 12 1 11 0 F F 8 F 7 J J J 4 J 3 J 1 0 0 MACR Q1.F C1.Y0.FFF1.X:<ea_m> 0 15 0 0 1 12 1 11 G G G 8 F 7 Q Q Q 4 1 3 m R R 0 MACR Q1.X0.Q2.This instruction occupies only 1 program word and executes in 1 cycle for every addressing mode.FFF 0 1 1 0 1 1 F F F J J J J J 1 1 Timing: Memory: 1 oscillator clock cycle 1 program word Freescale Semiconductor Instruction Set Details A-181 .MACR Parallel Dual Reads: Multiply-Accumulate and Round MACR Second Memory Read Data ALU Operation1 Operation MACR2 Operands Y1.F X:<ea_m>. 2. when the instructions are executing from data memory).F GGG.F Y1.Y0.FFF1.This instruction is not allowed when the XP bit in the OMR is set (that is.F Y0.Q2.F X:<ea_m>. Instruction Opcodes: 15 12 11 8 7 4 3 0 MACR FFF1.X0.reg1 X:<ea_v>.reg2 0 15 1 1 1 12 0 11 1 v v 8 F 7 v Q Q 4 1 3 m 0 v 0 MACR –FFF1.F First Memory Read Source 1 X:(R0)+ X:(R0)+N X:(R1)+ X:(R1)+N X:(R4)+ X:(R4)+N X:(R0)+ X:(R0)+N X:(R4)+ X:(R4)+N Destination 1 Y0 Y1 Source 2 X:(R3)+ X:(R3)– Destination 2 X0 Y0 X:(R3)+ X:(R3)+N3 X:(R3)+ X:(R3)+N3 X0 Y1 C 1.GGG 0 15 0 1 1 12 1 11 G G G 8 F 7 Q Q Q 4 1 3 m R R 0 MACR Q3