1. Introduction and block diagram of SPI 2. Specifications of ADS1299 3. Applications of ADS1299 4. Architecture of ADS1299 5. PIN specifications of SPI 6. Calculations 7. Operation 8. Flow chart for Master Device 9. State machine of master device 10. master device program in VHDL

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SPI(serial peripheral interface) controller

1.INTRODUCTION:The Serial Peripheral Interface bus is a synchronous serial data link standard, named by Motorola, that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial buses. SPI is often referred to as SSI (Synchronous Serial Interface).

The basic block diagram of SPI is shown here

Fig.1 Basic SPI block diagram SPI mainly contains four basic signals >MOSI (master out, slave in) >MISO(master in , slave out) >SS(slave select or enable) >SCLK(slave or clock)


Since SPI is a full duplex communication it requires two bus lines. MOSI bus is required to send data from master to slave device. MISO bus is required to send data from slave device to master. And SS pin is used to select the slave device and SCLK is the spi clock pulse. Here we are developing the SPI master device for the ADS1299 slave as reference slave device. The ADS1299 is a 24-bit ADC(Analog to Digital convertor) from the TI (Texas Instrumentation ) industry. 2.Specifications of ADS1299 are as follows >Eight Low-Noise PGAs and Eight High-Resolution Simultaneous-Sampling ADCs >Low Power: 5 mW/channel >Input Bias Current: 300 pA >Data Rate: 250 SPS to 16 kSPS >CMRR: –110 dB > Programmable Gain: 1, 2, 4, 6, 8, 12, or 24 >Unipolar or Bipolar Supplies: – Analog: 4.75 V to 5.25 V – Digital: 1.8 V to 3.6 V >Built-In Oscillator >Internal or External Reference >Flexible Power-Down, Standby Mode >SPI™-Compatible Serial Interface >Operating Temperature Range: –40°C to +85°C


3.APPLICATIONS • Medical Instrumentation (EEG and ECG) Including: – EEG, Bispectral index (BIS), Evoked audio potential (EAP), Sleep study monitor • High-Precision, Simultaneous, Multichannel Signal Acquisition

4.The Architecture of ADS1299 is shown below

Fig.2 ADS1299 architecture


It has 8 input analog channels, each having both positive and negative inputs. Each analog signal is modulated and encoded as 24-bit data. It operates at maximum of 2.048MHz speed. So that it can modulate in the range of 250SPS to 16kSPS (samples per second). The data will be transferred to any master device by SPI interface with control signals. The more explanation about the architecture can be found in ADS1299 datasheet… DRDY (DATA ready) bar signal indicates the data is ready in the slave buffer, that means the conversion has been finished and the slave buffer is filled with 24-bits. PWDN bar is a power down signal active low. It is used to power down the device. START signal is active high signal. When it is connected to logic-‘1’ the ADC conversion will starts. 5.Pins used in the communication DRDY_bar = generated by slave device GPIO-(4 to 1)= These are not used CLK = generated by internal oscillator of ADS1299 SCLK = it is generated by Master device CLKSEL = clock select signal of ADS1299. Will be connected to 0v to select internal clock oscillator. DIN = Data input from the Master device (MOSI) DOUT = Data output from the slave device (MISO) PWDN_bar= used by ADS1299 and is connected to logic ‘1’ to discard the signal START = used by ADS1299. Connected to logic ‘1’ always to start ADC conversion CS_bar = used by ADS1299 and generated by Master device RESET_bar=active low, used by slave device. Is connected using switch.


Choosing of the slave clock SCLK depends on different parameters. The following formula determines the slave clock period required for the chosen parameters.

Where tSCLK= slave clock period

tDR= data rate (fdr range 250 sps-to-16kSPS) NBITS= ADC resolution (number of bits per sample) NCHANNELS=number of analog channels present in the device
When we choose 925 SPS data rate the tsclk will be (1/900)-4(1/2.048x10^-6)

tsclk < tsclk < Fsclk >

------------------------------------24x 8+24 5.134990676 x 10^-6 194.742 KHz

thus we are choosing the slave clock frequency greater than 194KHz i.e. we can choose 200KHz frequency when the sampling rate is 900 SPS. The minimum possible Fsclk slave clock frequency is 100KHz.


The master device will be implemented on FPGA. The master will be coded as it should compatible with ADS1299 data converter SPI. While interfacing ADS1299 to the master device the slave device should be preprogrammed so that its internal register can load its appropriate values.

7.Operation:The Timing Diagram explains the operation of the master slave communication

Fig.3 Timing Diagram of SPI We have chosen the maximum clock frequency as the master clock frequency i.e., 2.048MHz. And the slave clock becomes 200KHz. The master device will communicate with the slave device whenever it receives either DRDY bar (Data ready ) signal from the slave device that it indicates the data is ready to transmit to the master or when the master device wants to communicate with slave device it generates Transmit buffer full (Tx_BUFF_FULL) signal which is active high. The master will also generates the chip select signal when it receives the Tx_BUFF_FULL and the device select signal. When master receives the DRDY active low signal from the corresponding slave device it generates the chip select (CS_bar) signal as active low for the duration of 24 clock cycles i.e., until the data transmission completed. Here the master and slave devices are connected in a standard fashion so that DAISY_IN signal will not be used. Here we designed the master device to communicate with one slave device. We can improve it communicate with more slaves by adding extra signals.


8.Flow Chart:-



Tx_BUFF=” 0”


Rising_edg e(clk)

CS_bar=’1 ’

DRDY=’0’ or Tx_BUFF_FULL=1

For I in 23 downto 0 loop CS_bar=’0’; MOSI=S_buff(23); S_buf(23 dwto10)=s_buf(22 dwto 0) S_buf(0)=MISO Rx_buff=S_buf S_buf=Tx_buff 9



Entity : spi Architecture: spi r Rx_BUFF[23:0] r T x_BUFF_FULL r S_BUFF[23:0] r INT _bar

m osi CS_bar m iso clk Sreg0
clk ce No clock enable r T x_BUFF[23:0]


S2 /010/ S3 Tx_BUFF="0000000000000000" T x_BUFF_FULL<='0' /011/ sclk='1' Tx_BUFF /= "0000000000000000" S4 /100/ S1 /001/ sclk='0' sclk='1' S5 /101/

T x_BUFF_FULL<='1'

INT_bar='1' and INT_bar='0' or Tx_BUFF_FULL='1'Tx_BUFF_FULL='0' S6 /110/ sclk='0'

for i in 23 downto 0 loop CS_bar<='0'; M OSI <=S_BUFF(23); S_BUFF(23 downto 1)<=s_BUFF(22 downto 0); S_BUFF(0)<=M ISO; end loop; Rx_BUFF<=S_BUFF; S_BUFF<=T x_BUFF;


10.MASTER DEVICE implementation using VHDL code;-

-- Name:SPI_Master.vhd -- designer:Thati Anand -- This code is to implement on FPGA. it works as SPI(serial peripheral interface) Master --controller. -- the slave device to this master is ADS1299 SPI block. -- Specifications -- ADS1299 SPI requires minimum 110KHz clock frequency b'coz ADS1299 runs at --2.25MHz(MAX) -- here we are using 200KHz clock pulse -- we are using 5 pins DRDY_bar, CS_bar, MISO, MOSI, SCLK -- DRDY_bar is generated when the data is ready to transmit in the slave buffer -- ADC settings -- ID=1Eh; CONFIG1=F0h,CONFIG2=C2h;CONFIG3=60h;LOFF=00h and remaining registers --are loaded with default values -----------------------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity SPI_MASTER is GENERIC (DATA_WIDTH : INTEGER:=24);


PORT(SCLK:INOUT STD_LOGIC; -- Slave clock INT_bar:INOUT STD_LOGIC; --Interrupt input generated at slave as DRDY_bar MOSI:INOUT STD_LOGIC; -- Master out slave in MISO:INOUT STD_LOGIC; -- master in slave out CS_bar:OUT STD_LOGIC -- slave chip select signal bar ); end SPI_MASTER;

architecture SPI of SPI_MASTER is signal clk:std_logic; signal S_BUFF: STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); signal Rx_BUFF: STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); signal Tx_BUFF: STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); signal Tx_BUFF_FULL:STD_LOGIC; begin clk_gen:process begin --clock generation for i in 1 to 24 loop clk<='1'; SCLK<=clk; wait for 2.5 us; clk<='0';


SCLK<=clk;wait for 2.5 us; end loop; end process clk_gen;


begin if Tx_BUFF="000000000000000000000000" then Tx_BUFF_FULL<='0'; else Tx_BUFF_FULL<='1'; end if;

if rising_edge(SCLK) then if INT_bar='0' or Tx_BUFF_FULL='1' then for i in 1 to 24 loop CS_bar<='0'; MOSI<=S_BUFF(23); S_BUFF(23 DOWNTO 1)<=S_BUFF(22 DOWNTO 0); S_BUFF(0)<=MISO; end loop; else

CS_bar<='1'; end if; Rx_BUFF<=S_BUFF; S_BUFF<=Tx_BUFF; end if; end process SPI; DUT:process begin wait for 5 ns; MISO<=’1’; INT_bar<='0'; INT_bar<='1'; Tx_BUFF<="010100000101000001010000"; wait for 5 us; wait; end process DUT; end SPI;