ADS_1174 Data_converter Programming

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INDEX

1.Introduction 2.Architecture of ADS1174 3. PIN description 4.Timing characteristics of Frame sync format 5. Flow chart 6.State diagram 7.VHDL programming

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ADS1174 interfacing to the FPGA

1.Introduction:2

ADS1174 is a programmable 4-channel 16-bit resolution Analog to Digital converter manufactured by Texas Instruments. Channel can be selected by the programmer and the output is available at SPI. 1FEATURES: > Simultaneously Sample Four Channels ·>Selectable Operating Modes: High-Speed: 52kSPS Data Rate, 31mW/ch Low-Power: 10kSPS Data Rate, 7mW/ch > AC Performance: 25kHz Bandwidth 97dB SNR –105dB THD ·>DC Performance: 2mV/°C Offset Drift 2ppm/°C Gain Drift > Digital Filter: Linear Phase Response Passband Ripple: ±0.005dB Stop Band Attenuation: 100dB >Selectable SPI™ or Frame Sync Serial Interface

>Simple Pin-Driven Control > Low Sampling Aperture Error >Specified from –40°C to +105°C
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> Analog Supply: 5V > I/O Supply: 1.8V to 3.3V > Digital Core Supply: 1.8V

2.The Architecture of the ADS1174 is shown here:-

ADS1174 is 64-pin IC. The Analog 4 input channels are having both the positive and negative inputs each. It’s clock frequency is 27MHz and the maximum sampling rate is 52kSPS.

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Here we are using 25MHz frequency to run the ADC. Delta sigma is used to sample the input signal and digital filter converts the each sample into 16-bits digital data.

3.PINS used to Interface:>DRDY_bar/FSYNC >SCLK >DOUT[4:1] >DIN >TEST[1:0] >FORMAT[2:0] >CLK >SYNC_bar >PWDN_bar[4:1] >CLKDIV >DIV DRDY_bar/FSYNC is the output pin from the ADS1174 it indicates the conversion completed. When conversion completed DRDY_bar pin goes low / FSYNC pin goes high. We can select either of one by setting FORMAT bits. SCLK this is used for serial communication. This is the input clock signal to the ADS1174. DOUT[4:1] are the outputs from the ADS1174 pins. The output from each pin is corresponds to its input analog input. These can be selected by PWDN_bar bits.

DIN is the output from the master device and serial data input to the ADS1174. Here we are not using this pin because we are not sending any information to the slave device.

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TEST[1:0] are used to operate the device in normal mode and test mode. We are sending 00 to these pins so that it will operate in normal mode. FORMAT[2:0] Selects between Frame-Sync/SPI protocol, TDM/discrete data outputs, fixed/dynamic position TDM data, and modulator mode/normal operating mode. Here we sent “101” so that it will select Framesync and Discrete mode operation. CLK is the input signal to the ADS1174. We are choosing 25MHz clock. SYNC_bar is active low to synchronize all input channels. PWDN_bar is used power down the input channels. These can also be used to select the channels. We send “1110” to select the channel-1. CLKDIV is the input to the ADS1174. It is connected to 0v so that the device can operate in high speed mode. The sampling frequency will be maximum. DIV is the daisy_chain input signal to the ADS1174. It is connected to 0v to abort the daisy_chain operation.

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4.Timing Characteristics of Frame Synchronous Format:-

FSYNC will be high when the A to D conversion completed i.e., the data is waiting in the SPI buffer and then it goes low.

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The timing requirements are

5.Flow chart :
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The flow chart of ADS1174 interfacing circuit with FPGA

Start

FORMAT=”101”; CLKDIV=’0’ TEST=”00”;MODE=’0’; SYNC=’0’; PWDN_=”1110”;

Clk=1

FSYNC=1

For I in 15 downto 0 Rx_buff(i)=DOUT(1);

Buff=Rx_buff;

6.State_Machine Diagram :End 9

Entity : ads1174 Architecture: ads1174

DOUT 1

FORMAT [2:0]

FSYNC

CLKDIV

T EST [1:0]

r buff[15:0] r Rx_buff[15:0]

MODE clk Sreg0
clk ce No clock enable

SYNC_bar

PWDN_bar[4:1]

clk='0' S1 /00/ clk='1' FORMAT <="101"; CLKDIV<='0'; clk='1' EST <="00";MODE<='0';SYNC_bar<='0'; T PWDN_bar<="1110";

S4 /11/

buff<=Rx_buff;

FSYNC='0' S2 /01/

clk='1' clk='0' S3 /10/ FSYNC='1' for i in 15 downto 0 loop Rx_buff(i)<=DOUT 1; end loop;

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7.VHDL Programming:-

-- ADC (ADS1174) control programming -- Thati.Anand -- It is 16-bit 4-channel ADC run at max 27Mhz -- sampling rate is 52kSPS (samples per second) max when it in highseed mode -- set mode pin to '0' for higher speed operation -- set sclk/clk=1 -- set FORMAT pins to 101 to operate in Frame_synchronus and Discrete mode -- clkDiv='0'(52ksps) and sync_bar='0' -- test[1:0]="00" for normal operation -- running at 25MHz=sclk=clk Tclk=0.04us

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ADS_1174 IS PORT(CLK:INOUT STD_LOGIC; -- clock SCLK:INOUT STD_LOGIC; -- spi clock FSYNC:IN STD_LOGIC; -- fsync or drdy data ready signal CLKDIV:OUT STD_LOGIC; -- clock division

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MODE:OUT STD_LOGIC; -- mode selection highspeed SYNC_BAR:OUT STD_LOGIC; -- synchronus signal DIN:OUT STD_LOGIC; -- data out

TEST:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); --test signal "00" DOUT:INOUT STD_LOGIC_VECTOR(4 DOWNTO 1); --data out from the ADS1174 FORMAT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --data receiving format PWDN_BAR:OUT STD_LOGIC_vECTOR(4 DOWNTO 1) --channel setting ); END ADS_1174; ARCHITECTURE ADS_1174 OF ADS_1174 IS signal clock:std_logic; signal buff:std_logic_vector(15 downto 0); BEGIN FORMAT <= "101"; -- frame-synch, discrete CLKDIV <= '0'; --52ksps TEST <= "00"; --normal operation MODE <= '0'; --high speed mode SYNC_BAR <= '0'; -- sync operation PWDN_BAR <= "1110"; -- channel-1 CLK_GEN:PROCESS BEGIN

-- wait for 0.04 us;
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for i in 1 to 1000 loop clock <= '1'; SCLK <= clock; -- clock period 0.04 us = 25 MHz CLK <= clock; wait for 0.02 us; clock <= '0'; SCLK <= clock; CLK <= clock; wait for 0.02 us; end loop; END PROCESS CLK_GEN;

PROCESS VARIABLE Rx_BUFF:STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN IF rising_edge(CLK) THEN IF FSYNC = '1' THEN -- if data is ready for i in 15 downto 0 loop Rx_BUFF(i) := DOUT(1); --loading channel-1 data into buffer register end loop; END IF;

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buff <= Rx_BUFF; end if; wait; END PROCESS;

END ADS_1174;

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