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S

Training Manual

Direct View Television


DX-1A Chassis
Models: KV-32XBR400 KV-36XBR400

Circuit Description and Troubleshooting Course: DTV-02

Table of Contents
Introduction DTV Converter Boxes
USA Analog Transmission Format USA Digital Transmission Formats Digital TV (DTV) Converter Boxes

2 3
3 5 5

Testing

35

Horizontal Drive / H Pincushion Correction / Filament Voltage


Basic Horizontal Drive Circuit PMW Circuit Filament Voltage

37
37 37 39

New Features Overall Block SD to HD Conversion Concept Video Block Picture with Picture Power ON Block
Power Supplies Standby Power Supply Primary & Secondary Power Supplies

9 11 15 21 27 29
29 29 29

G2 Circuit HV Converter Block


Start Up Protection / Shutdown HV Adjustment Testing

41 43
43 43 43 45

Communications Dynamic Focus Block


Static Focus Concept Dynamic Focus Concept Circuitry Adjustment

47 51
51 51 51 55

Primary Power Supply


Start Up Regulation Testing

31
31 31 33

DQP Circuit Corner Focus Correction Convergence Circuit


Concept Circuitry

57 61
61 61

Secondary Power Supply


Start Up Regulation

35
35 35

Adjustment

61

Appendix
Service Mode Display Digital Satellite System Converter Box DTV Set Top Box IEEE-1394 DX-1A Chassis Assembly Board Replacement HV Adj. check Bulletin 492 i ii iii iv vii viii ixi

Picture Tilt Correction Vertical Pincushion Correction Circuit


Concept Adjustment

63 65
65 65

Vertical Process Audio Block Diagram


Features Signal Path

67 71
71 71

Self Diagnostic Block Self Diagnostic Circuit

73 75

NOTES

Introduction
This model KV32XBR400 is a high resolution TV designed to bridge the gap between the current analog TV sets and the forthcoming high definition digital TV (HDTV) sets. This set can accept the current standard resolution NTSC TV transmissions, DVD, VHS, and Camcorder video signals, convert them, and display them on a high-resolution TV screen. An external set top converter box is necessary to receive Digital TV programs. Related Models

Circuitry Information
The power consumption and self-diagnostics remain the same as other Sony TVs. This sets change to high-resolution video results in circuitry changes to the video processing, horizontal frequency (fixed at 33.75kHz), and high voltage generation.

Power Consumption at 120Vac Snow 1.2 A Dark screen/video 1 1.1 A Surge 6 A (degaussing)

DX-1A TV Chassis Models Model KV32XBR400 KV36XBR400 Screen size 32 diagonal 36 diagonal Aspect Ratio 4:3 4:3 MSRP
Item General Servicing Information Location Circuits on A & D boards. Indicator on front panel. Comments Standby/Timer LED blinks to ID problem area. Self Diagnostics Filament Voltage High Voltage Converter G2 (Screen adjustment) Focus Control

$1999.99 $2499.99

Higher Resolution Inputs


This TV can also accept standard resolution 480p or high resolution 1080i video signal formats from an external HDTV, satellite, or cable converter box as component video (Y, Pb, Pr) inputs. These 480p and 1080i signals can have a wide 16:9 aspect ratio. If they do, the display will be in letterbox format with black above and below the picture on the 4:3 aspect ratio picture tube of these TV sets. Only the Digital TVs 720p resolution video format cannot be displayed on this set. The picture will not be synchronized.
KV32XBR400 / KV36XBR400Inputs Name RF Video 1-4 + Stereo jacks Video 5-6 + Stereo Jacks Control S NTSC S or Composite video: Standard resolution 480 interlaced lines (480i). Component video: Standard Resolution 480i, 480p or High Resolution 1080i format Sony Format Source VHF, UHF, Cable Video tape recorder, camcorder, DVD player, TiVO recorder DTV, Satellite, or Cable Converter box Audio Equipment

From 7V, A Bd The CRT filament (Primary PS) and HOT voltage comes from 2 transformer, D Bd. sources. D board near flyback On the CRT board AFC signal from HOT turns ON HV Converter. Adjustment is in the board replacement guide (appendix).

Adjust for sharp picture center and sides Filament Voltage - This CRT voltage comes from two sources: Unregulated 7V supply from the Primary Power Supply on the A board (used as a preheat). The HOT (horizontal output transformer) after a 6Vdc regulator on the D board (main filament voltage supply).
High Voltage Generation - An independent HV oscillator circuit with a special high frequency flyback transformer regulates the HV to 31.5kV. The HV converter stage is turned on only after the Horizontal drive signal from the HOT is detected.

On the FBT

DTV Converter Boxes


In order to compare converter box specifications you need to understand how resolution is measured in the interlaced and progressive scan methods. With this information you can also determine which one of the 18 digital formats offers better resolution.

picture is not seen and the picture is normally over-scanned (larger than the TV screen). Therefore, the TV resolution is said to be 480 (horizontal) lines instead of the transmitted 525 lines.

USA Analog Transmission Format


Interlaced and Progressive Scanning In the NTSC television transmission format a complete picture (frame) consists of two pictures (fields) interlaced together. Each half picture is a field of 262.5 scanned lines. Therefore a complete picture is 262.5 x 2 = 525 lines. The two scanned fields are interlaced so the second field of 262.5 lines fits in-between the first field.
Interlaced Scan

Resolution
The two most popular methods of measuring picture resolution are in pixels (dots) or in lines. Incremental dots called pixels are often associated with monitors. Lines of resolution is a measurement for TVs. In the monitor specifications, the number of vertical pixels is listed first. In the TV specifications, the number of horizontal lines is listed first. For these examples of specifications, a high-resolution monitor and (digital) TV standard were chosen:
Monitor Spec 1024 X 1800

Field 1

Field 2

Frame

1024 x 1800 pixels

If a picture is not interlaced, it is a progressive scan image (not NTSC format). This means the entire picture frame is presented in the first scan and a second picture is presented in the second scan.
Progressive Scan

TV Spec

X Field 1 = Frame 1080 x 1920 lines

Although the semantics are different (vertical pixels/horizontal lines), the first number in both specifications is the maximum number of black to white transitions that can occur as you count from the top of the screen to the bottom. In the current NTSC (National Television Standards Committee) TV transmission standard, 525 horizontal lines are transmitted but only about 480 lines are visible. This is because the vertical blanking area above the

30 or 60 Frames? In the NTSC standard the first field takes 1/60 second to scan a screen of 262.5 lines. Then a slightly smaller vertical sync pulse in the second field is created and the second picture field is shifted lower than the first to fit in-between. The second field also takes 1/60 sec., completing the entire picture frame in 1/60 + 1/60 = 2/60 sec = 1/30 sec.

DTV Set Top Converter Boxes (as of July, 2000)


RF Inputs Ch 1-125 Cable DTV * Ch 2-69 Analog TV Small dish Satellite Ch 1-99 Digital TV X X X X X X X X X X X X Video Output Standard Resolution High Resolution Format (# Horiz lines) Audio Output Digital Analog

Comp Video

RGB,H,V **

RF(Ch 3/4)

IEEE 1394

Y, Pr, Pb

S Video

Optical

L&R

Coax

Mfg. Model RCA DTC-100 Panasonic TU-HDST50 TU-HDS20 Pioneer SH-DO7 SH-D505 Mitsubishi SR-HD400 SR-HD500 Sony DTR-HD1 SAT-HD100 Sharp TUDTV1000 Proscan PSHD105 Samsung SIRT100

X X X X X

X X X

X X

X ? ? ? ? X X X X X X

X X X X X X X X X X X X

X X X X X X X X X X

X X X X X X X

X X X

X X X

? ?

? ?

VGA 1080i/540p 720p BNC ? 1080i *** BNC 1080i/ 720p/480p ? ? phono 1080i VGA 1080i/480p VGA/ 1080i/480p BNC VGA 1080i/540p ? 1080i/480p

X X X X X X X X X X X X

X X X X X X X X X X X X X X

X = Yes ? = insufficient information blank = No

* DTV must be 8VSB modulation (like terrestrial ATSC DTV transmissions) ** VGA = computer monitor jack (15 pin D type) BNC = BNC connectors, one for each of the signals *** Connection to Pioneer model PRO-700HD TV only.

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30I Picture Format 1/60 sec. Field 1 1/60 sec. Field 2 = 2/60 second or 1/30

USA Digital Transmission Formats


There are 18 digital transmission formats approved by the ATSC (Advanced Television Standards Committee) in the USA. The first six offer HD (high definition/resolution) signals in a 16x9 aspect ratio. The remaining 12 formats are SD (standard definition) signals in progressive (p) or interlaced (i) scan. Note that the 480p signal can be a 4:3 or 16:9 aspect ratio transmission.

The NTSC format is commonly written as 30i picture format because it takes 1/30 of a second to complete an interlaced picture. Aspect Ratio Although the first pictures were round, later TV pictures adopted a rectangular shape. The aspect ratio of these pictures is the same as they are today, 4 x 3 ratio.
3 4 16 9

18 Digital Transmission Formats Resolution 1. 1080x1920 2. 3. 4. 720 x 1280 5. 6. 7. 480x 704 8. 9. Aspect Ratio 16:9 16:9 16:9 16:9 16:9 16:9 16:9 16:9 16:9 Frame 30 i 30 p 24 p 60 p 30 p 24 p 60 p 30 i 30 p Resolution 10. 480x 704 11. 12. 13. 14. 15. 480x 640 16. 17. 18. Aspect Ratio 16:9 4:3 4:3 4:3 4:3 4:3 4:3 4:3 4:3 Frame 24 p 60 p 30 i 30 p 24 p 60 p 30 i 30 p 24 p

Movie theaters show films in a wider 16x9 aspect ratio. This 16x9 picture is also the way most films are shot. To present the original 16x9 picture on a 4x3 TV screen, one of two common methods is adopted to fit the picture: In method 1, the 16x9 picture is cropped or cut off at the left and right. The main action part of the picture (usually the center or near center) is the only part transmitted.
Method 1 Cropping Center of 16 x 9 picture Shaded area Cropped/ removed

A standard definition transmission contains less data, permitting space for another digital video stream to coexist on the same frequency (channel). Therefore, a station can have more than one program stream on a digital channel. The maximum number of programs is six.

In method 2, the 16x9 picture is shrunken and placed on the TV screen. The entire picture is seen but with black areas above and below the picture. This method of viewing the entire 16x9 picture on a 4x3 set is called a Letterbox picture. Letterbox pictures can be selected on some DVD players and TV sets from the menu if the DVD or TV transmissions offer it.
Method 2 Letterbox Entire 16x9 Picture

Digital TV (DTV) Converter Boxes


TV broadcasters are transmitting their analog signals on one channel and their DTV signals on another. A list of their analog and digital channel assignments by state is located at www.transmitter.com. To receive a DTV station on an analog TV, a set top converter box is used. The box receives digital RF and outputs analog composite video to the TV. The boxes can also output higher resolution video signals to a high-resolution analog TV. These cable boxes are flexible at their input and outputs:

RF inputs:
Channels 1-99 Digital TV The TV converter boxes listed in the chart all decode DTV signals from off the air (terrestrial) in the USA and Canada. These TV stations conform to the DTV ATSC format that approves an 8VSB modulation method. The new digital channel numbers are frequencies within the current analog Channels 2-69. Ch 1-125 Cable DTV At this time some cable TV companies are providing DTV service using 8VSB modulation and other cable companies sell DTV service using QAM modulation. The 8VSB modulation means this method is probably the same as the off the air ATSC (DTV) signal. This means if the DTV converter boxes can receive the cable band, they can decode the cable DTV signal. Cable companies using a QAM (Quadrature Amplitude) Modulation method require their DTV boxes for processing. 950-1.45GHz Satellite In competition with cable companies are Direct Broadcast System (DBS) companies that provide satellite TV channels. The larger analog signal DBS dishes that operate on the C band were not as popular as the smaller Ku band digital signal dishes. A satellite manufacture can either provide the TV service directly to the consumer, rent transponders (space) to other providers, or both. Some of the larger companies are:

A few converter boxes can receive digital satellite signals. This combination of DTV and satellite decoding in one box is feasible because the decoding circuitry is similar. It is uncertain if these converter boxes can decode the new satellite high definition DTV signals.

Video Outputs
The converter boxes output standard resolution and high-resolution signals. All the boxes can down convert a 1080, 720 or 480 line input signal into a standard resolution 480i picture for an analog TV. This standard resolution output comes from the S or composite video jacks of the box. For the higher resolution TVs that are coming out now, there is a component (Y, Pr, Pb) and/or RGB output from the box. The RGB +sync output could be five individual BNC jacks or a single VGA connector, such as the ones found on the back of a home computer for its monitor. After the correct mechanical connection is made, the signal format from the box must match that of the high resolution TV. The boxs output signal formats are menu selectable for box to TV compatibility. For example if the TV accepts 1080i signal format, the boxs output must correspond with the same output signal format. If a 1080 format DTV signal is received, the box will convert it from an RF signal, unscramble it, separate the audio, video and data, and then uncompress the audio and video. The video will be changed into component video or RGB voltages that are input to the TV. The sync is on the Y line in the component video signal. If a standard resolution 480 format DTV signal is received, the same signal processing occurs but there is an additional scan converter to double the information before leaving as a 1080i format signal for the hich scan TV.

Satellite Manufactures GM Hughes Electronics EchoStar/Dish Network (HD 1080i) DBSC (Direct Broadcast Satellite Corp) Direct Sat Tempo ACC (advanced Communications Corp)

Providers Direct TV PrimeStar

Audio Outputs
All the converter boxes have composite video output and corresponding analog audio L&R channel outputs. Some boxes have digital optical and/ or coax outputs for a Dolby AC-3 decoder (often in a receiver). One converter box has an IEEE 1394 output for decoding the signal in a SVHS

Satellite reception is vulnerable to rain scattering the signal and the suns microwave energy overpowering the satellite signal. The solar outages may occur only for minutes during the time span of a week or two during the spring and fall equinoxes. At these times the sun is behind the target satellite adding noise to the signal.

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recorder. The IEEE-1394 format is also called i.LINK, or Firewire because of the convenience or high speed. Customarily, both video and audio is sent on this 4-wire cable. More about the IEEE-1394 format is found in the appendix of this book. Dolby is a registered trademark of Dolby laboratories. Fire Wire is a trademark of Apple Computer Inc.

i.LINK is a trademark of Sony.

NOTES

New Features
FD Wega Picture Tube
The Sony flat screen picture tube is a full flat screen inside and outside.
Sony FD Glass screen Electron beam Non-Sony Picture Tube

Parent Menu
This allows the owner to block TV programs according to their content. Entering the owners four-number password enables viewing of the blocked programs. The owners password can be cleared with the master password 4357 (HELP). The owners password can also be reset from the service mode by pressing 8, then enter.

Set Up Menu - 16:9 Enhanced


A 480p input signal can be in 4:3 or 16:9 video format.

Favorite Channel Preview


Pressing the Favorites remote button reduces the main picture and displays a small picture of another (favorite) station. As you move the joystick down the list of numbers, the preview picture changes to that station. Select that station by pressing enter.
Favorite Channel Display

Letterbox picture

16:9 Pix

Black border

Preview Main Pix

The wide 16:9 video format produces a picture on a 4:3 picture tube that is too tall. From the Auto/ON/OFF selections of the set up menu, choose 16:9 Enhanced = ON to reduce the vertical size of the picture so the picture is the correct aspect ratio. The Auto selection reduces the picture size if there is an ID-1 signal in the vertical blanking area of the input signal. The ID-1 signal identifies the video signal as 4:3 or 16:9 format. Sony 16:9 camcorders insert the ID-1 information into the video during recording.

Channel Numbers

New Picture Mode = Pro


The basic video modes are Vivid for use in bright daylight, Standard for reduced brightness in the home, and Movie for evenings. The Pro video mode is new. This mode darkens the picture and centers its dark to bright operating range for the widest dynamic picture swing. This mode is meant for pro movie watchers in a darkened room where the subtle dark to gray changes are made evident. The video settings (picture, brightness, color, etc) can be changed in any mode.

Video Menu - DRC-MF


Select an Interlace or Progressive mode display from the Video menu under DRC-MF. Interlace is selected when watching moving images. The Progressive mode is selected only when many non-moving images are displayed, such as text or a still photograph. Selecting the Progressive mode stops the flickering that occurs in an interlaced picture when the two interlaced fields are not exactly the same. This interlace/progressive is not an option with a 1080i input

NOTES

10

11

Overall Block
The only conventional block within this TV is the vertical block. The remaining blocks are different because this TV is a high-resolution type with a Wega flat screen. Therefore, changes to the power supply, horizontal frequency, convergence, focus, and video processing support the improved picture. Power Supply The power supply is in three parts to divide the load on the boards:
Power Supplies Board Standby Primary Power Supply Secondary Power Supply A A Purpose Outputs Standby 15V, 7V, & 5V. Outputs Set 9V, Set 5V, & Set 3.3V to local parts on the A, B, & BD boards. Outputs Pri-Pre 15V to start the Secondary PS. Outputs +200V, +135V, +24V (audio), Main 12V, Main 9V, & Main 5V to the D board.

V Pin Distortion

Top & bottom lines bowed in (exaggerated)

Horizontal Deflection The higher 33.75kHz horizontal frequency is made by IC201 and fed to the H Drive/Output stage on the D board. The output stage is fed regulated voltage from the +135V Secondary power supply via the PWM circuit of IC5002. The horizontal drive stage not only supplies the H Deflection yoke (H DY) with scan voltage, but also supplies G2 and filament voltage for the CRT. A regulated +200V is also output to supply the RGB output amplifiers on the C board. Horizontal AFC pulses from this stage are needed by the convergence and dynamic focus stages for sync. The AFC pulses are used to start the HV Converter. HV Converter Regulated HV and focus voltage is made by the HV Converter stage. It uses +200V from the secondary power supply to run and AFC pulses from the horizontal deflection stage to start. Horizontal Pincushion Correction To keep the lines at the left and right of the screen straight, an east/west (E/W) H pincushion correction signal is made in IC201. The E/W signal is used to modulate the PWM IC5002 that controls picture width. By changing the width line-by-line, the left and right sides in the large picture can be straightened.

The Primary power supply starts the secondary supply using a Pri-Pre 15V line. Once the Secondary power supply operates, Main 9V outputs to start the horizontal and vertical oscillators in Y/C CRT Drive IC201. Vertical Deflection In some Sony TV sets, there is no V Drive output the Y/C IC until data and clock are input. Unlike these TV sets, this IC201s vertical will output when power is applied. The sync source is dependent upon whether progressive, interlace or a sub picture is chosen. The vertical oscillator output is amplified by IC5004 on the D deflection board to drive the DY deflection yoke. Vertical Pincushion Correction As the TV screen becomes larger, the yoke can not perfectly control the beam at the screen perimeter. An additional coil on the top and bottom of the CRT neck assembly is fed V Pin correction signal from IC201 and IC5514. The additional coil eliminates any minor inward/outward bow at the top and bottom of the picture.

H Pin Distortion

Sides bowed in (exaggerated)

TUNERS VIDEO 1-4 VIDEO 5-6

VID IC3048 SW 480i SYNC

IC3303/ IC3408 DRC/MID 480p SYNC 1080i

MAIN 9V IC3414 SW A BD. +200V (HOT) C BD. RGB IC9001-3 RGB OUT IK CRT CATHODES

B BD.

E/W

H DRIVE = 33.75kHz

CRT VPIN FILAMENT COIL ON V DRIVE 200V CRT Q5026-8, C BD. NECK Q5035-6, G2 Q5030 IC5514 V IC5004 H DRIVE V PIN DY FOCUS V OUT H OUTPUT OUT H HV 100V DY IC5511 DF/DQP IC5513, VTIM CY IC5002 COILS IC5515 IN PWM CONV. DY IC8002 +135V HV CONV. AFC 200V

IC201 Y/C CRT DRIVE

VTIM (IC5513) STANDBY

STBY 15V 7V 5V IC5501 NVM (D BD.) IC707 NVM

IC701 MAIN uCOM D6530 POWER ON

340VDC + 15V SECONDARY P.S PRE 15V

SET VOLTAGES PRIMARY P.S 9V 5V 3.3V A BD.

D BD.

MAIN VOLTAGES 12V,9V,5V,24V

OVERALL BLOCK

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13
Convergence of the Three Beams The good news is that the complex convergence signal is made in one IC5513 and the signal is amplified in the second IC5515. The output signal drives a convergence yoke inside the main horizontal and vertical deflection yoke. The convergence stage affects the beams at the perimeter of the screen. Dynamic Focus Correction As a beam is deflected, the points of focus form a curve. The focus points have to be moved to match the flat screen of the TV. A signal from DF IC5511 modulates the DC focus voltage to prevent poor focus at the left and right sides of the screen. Video Processing Standard Resolution Input A standard resolution NTSC signal can be selected from either tuner or any video input. However, this high resolution TV runs at a different horizontal frequency of 33.75kHz. To accept a standard NTSC signal (480i) that runs at 15,734 Hz, the video signal is improved and the horizontal sync more than doubled. The Digital Reality Creation Circuit (IC3303) analyzes each pixel of a line to add another line. Therefore the DRC circuit doubles the number of video lines of a standard NTSC signal. The DRC also doubles the horizontal sync frequency before passing the signal onto the MID circuit on the same board. The Multi Image Driver (MID) Circuit (IC3408) stores the lines and outputs the signal based on a new horizontal frequency that matches the TV. At the higher frequency, the picture finishes before the scan. Blank lines are added as filler by this MID stage before leaving the board. High Resolution Input - Video inputs 5 and 6 are for Y, Pr and Pb component signals only. They can be standard (480i) or high resolution (480p or 1080i). The 480p signal is already high resolution at double the H freq so it need not go through the DRC circuit. It is switched directly into the MID circuit. The high-resolution 1080i picture is at the same horizontal frequency as the TV set (33.75kHz), so it does not go into the DRC or the MID circuit. The 1080i signal is switched directly to the Y/C CRT Drive IC201 on the A board. Since the 1080i signal is a wide 16:9 ratio picture, it looks squeezed in on a 4:3 aspect ratio picture tube. To make the picture look correct, the vertical can be reduced using a 16:9 enhanced menu command. Vertical reduction can be automatically done if there is a code in the vertical blanking area of the input signal called ID-1. This signal identifies the aspect ratio of the picture.

TUNERS VIDEO 1-4 VIDEO 5-6

VID IC3048 SW 480i SYNC

IC3303/ IC3408 DRC/MID 480p SYNC 1080i

MAIN 9V IC3414 SW A BD. +200V (HOT) C BD. RGB IC9001-3 RGB OUT IK CRT CATHODES

B BD.

E/W

H DRIVE = 33.75kHz

CRT VPIN FILAMENT COIL ON V DRIVE 200V CRT Q5026-8, C BD. NECK Q5035-6, G2 Q5030 IC5514 V IC5004 H DRIVE V PIN DY FOCUS V OUT H OUTPUT OUT H HV 100V DY IC5511 DF/DQP IC5513, VTIM CY IC5002 COILS IC5515 IN PWM CONV. DY IC8002 +135V HV CONV. AFC 200V

IC201 Y/C CRT DRIVE

VTIM (IC5513) STANDBY

STBY 15V 7V 5V IC5501 NVM (D BD.) IC707 NVM

IC701 MAIN uCOM D6530 POWER ON

340VDC + 15V SECONDARY P.S PRE 15V

SET VOLTAGES PRIMARY P.S 9V 5V 3.3V A BD.

D BD.

MAIN VOLTAGES 12V,9V,5V,24V

OVERALL BLOCK

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SD to HD Conversion Concept
This TV has features designed to bridge the gap between the current analog sets and newer higher resolution digital TV sets. The KV32XBR400 TV is a high resolution set capable of receiving the current standard definition (SD) NTSC signal. The NTSC standard resolution of 480i lines is upgraded to a 960i (interlaced) or 480p (progressive) line picture, to be compatible with this TV. The user selects interlaced scan if there is motion in the picture or progressive scan if there is a still picture signal in order to stop interlace flicker. A higher resolution (480p or 1080i) signal that does not need to be upgraded can be input to video 5 or 6 for advanced placement in the video chain. Interlaced or Progressive Scan Most technical people do not know how many horizontal lines are present on the screen in a single scan from the top of the screen to the bottom. The confusion about the number of lines shown at one time relates to the different interlace/progressive scan modes. In the progressive scan mode the entire picture is presented in one scan of the picture tube (left to right, top to bottom). In an interlaced scan the entire picture consists of two fields so the picture is presented in two scans of the picture tube. The second field is displaced from the first so the lines fit in-between each other making the completed picture:

number of lines in the total picture. The i suffix identifies an interlaced picture. Since the picture is interlaced, there is only half the number of lines presented in a single scan. In this case, there are 240 lines displayed in a single scan. This is equivalent to a 240p picture that displays 240 lines in a single scan (480i is the same as 240p).
In a single scan 1 2 3 4 5 6 12i Interlaced scan picture is 6 lines per field = 6p Progressive scan picture

Similarly a 480p picture is like a 960i picture because both these pictures present 480 horizontal lines per scan. This is important to understand as the standard resolution NTSC picture is changed to a higher resolution in the DRC video processing stage of this TV.

Standard Definition Video Input


The Tuner and Video 1-4 inputs accept only the NTSC 480i-line standard definition signal identified by the 15.75kHz horizontal frequency. The 480i input signal is interlaced (i), consisting of two 240-line fields presented/ scanned one at a time that total the 480 lines. Therefore a 480i NTSC picture normally displays 240 lines each time the picture is scanned. The NTSC signal passes through the DRC and MID circuits. DRC Circuit In this model KV32XBR400 high resolution TV, a single scan must contain 540 lines, more than double of a NTSC signal. The DRC circuit almost bridges the gap between the 240 line input signal and the 540 line TV requirement. The DRC circuit doubles the number of horizontal lines by analyzing the pixel data to construct new lines. Therefore the DRC circuit brings the total line count from 240 to 480. The DRC circuit also doubles the horizontal frequency to 31.5kHz to support these lines.

Field 1

Field 2

"6i" Interlaced Picture consisting of alternating lines from fields 1 & 2

The resolution of the TV picture is measured in horizontal lines of a complete picture followed by the letter for the type of scan (i or p). For example, the NTSC signal contains 525 horizontal lines. The number of viewable lines is reduced to 480 because of the time required for V & H retrace, creating a blanking area above and below the picture. Therefore the standard resolution NTSC signal displays a 480i picture. 480 is the

B BD.

A BD.

TUNER/ VIDEO 480i 1-4 IC3048 STANDARD SW NTSC RESOLUTION

Y, Pb, Pr IC3303 DRC CIRCUIT

Yo -7 Cr-7 Cb-7

H+V

IC3408, IC3410 MID-XA CIRCUIT

C BD. IIC BUS DATA/ CLK IC201 Y/C CRT DRIVE IC9001-3 RGB OUTPUT

H+V SYNC

IIC BUS
VIDEO

DATA/CLK

CRT CATHODES

Y, Pb, Pr CONT

480i VIDEO 5 VIDEO 6 480i 480p 1080i

IC3603 ID-1 DECODE 480p 1080i

IC3414 YUV SWITCH

OSD

VERT OUTPUT IC5004 (D BD.)

SD TO HD CONVERSION CIRCUIT

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Progressive Scan - In this example of the progressive scan video processing, an NTSC still picture signal is input from a DVD player (in pause). The user chooses progressive scan from the menu to reduce picture flicker. Flicker occurs in an interlaced picture when the two fields are not exactly the same images. The flicker is more noticeable in the movement area(s) of the picture where the fields are different. In the progressive scan mode the DRC circuit doubles the number of lines from 480i (actually 240 lines) to 480p to make the NTSC signal compat480p ible with the TV.
Tuner Video 1-4 A/V Switches 480i DRC circuit MID circuit

The MID circuit centers the picture by adding 30 blank lines above and below the picture (60 lines total). This simple method permits the TV to keep the vertical frequency at 60Hz. Therefore the MID circuit increases the number of lines from 480p to 540p but these extra lines are blank. There are still only 480 active (picture) lines.
480 active lines 540p 540 lines Expand Vertical 480p + 60 = 540p lines 480p 480i DRC circuit 960i Interlaced 960i + 120 = 1080i lines 1080 lines 1080i Expand Vertical 960 active lines (2 fields) Progressive MID Circuit Adds 60 blank lines/scan

Interlace Scan - In a second example of the video processing, an NTSC signal with live pictures is input from an antenna. The user chooses the interlace scan mode from the menu because of the moving images. Each interlaced field displays a slightly different transitioning picture making movement seem smoother. In the interlaced scan mode the DRC circuit still must double the number of lines to meet the TVs 480-line/scan requirement. The resolution is changed from 480i (actually 240 lines) to 960i (actually 480 lines) by the DRC circuit. MID Circuit Fortunately, the model KV32XBR400 TVs horizontal deflection stage scans at a 33.75kHz rate to display high definition (1080i) video signals. However The horizontal frequency output the DRC circuit is double that of NTSC at 31.5kHz. This is slower than the KV32XBR400s 33.75kHz rate. Since the TV scans at a faster rate than what is input, the picture is finished faster, leaving blank lines at the bottom.
240/480 lines 480 lines

960i Progressive or interlaced output

Vertical Expansion To keep the 60 blank lines invisible, the vertical size is expanded slightly (picture overscaned) so the 480 lines fill the 4:3 aspect ratio screen. This is seen in the previous diagram where the 60 blank lines are shown (exaggerated) in black.

15.75kHz/31.5kHz

33.75kHz

B BD.

A BD.

TUNER/ VIDEO 480i 1-4 IC3048 STANDARD SW NTSC RESOLUTION

Y, Pb, Pr IC3303 DRC CIRCUIT

Yo -7 Cr-7 Cb-7

H+V

IC3408, IC3410 MID-XA CIRCUIT

C BD. IIC BUS DATA/ CLK IC201 Y/C CRT DRIVE IC9001-3 RGB OUTPUT

H+V SYNC

IIC BUS
VIDEO

DATA/CLK

CRT CATHODES

Y, Pb, Pr CONT

480i VIDEO 5 VIDEO 6 480i 480p 1080i

IC3603 ID-1 DECODE 480p 1080i

IC3414 YUV SWITCH

OSD

VERT OUTPUT IC5004 (D BD.)

SD TO HD CONVERSION CIRCUIT

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19 High Definition Video Input


The Video 5 and 6 inputs can be standard or high definition format signals. The MID circuit distinguishes the video format by their horizontal frequencies: Video 5 or Video 6 Input Formats Horizontal Frequency 480i 15.734kHz 480p (4:3 aspect ratio) 31.50kHz 480p (16:9 aspect ratio) 31.50kHz 1080i (16:9 aspect ratio) 33.75kHz 480p Picture Process A high-resolution 480p-video format is detected by its horizontal frequency and selected by the MID circuit for video processing. The resultant picture appearance will depend upon whether the video format of the input signal is a 4:3 or 16:9 aspect ratio. 4:3 aspect ratio - The MID circuit processes a 480p, 4:3 picture the same as the 4:3 NTSC picture. The MID circuit adds 60 blank lines to the signals. The picture is normally overscanned so the 60 blank lines are not 540p seen.
480p 4:3 pix MID Circuitry Adds 60 blank lines Vert size increased 480 lines

1080i Picture Process The 1080i-video format is a high-resolution picture with a 16:9 aspect ratio at a 33.75kHz horizontal frequency. The 1080i picture actually has 540 lines/scan (half 1080). Although 540 lines would fill this picture tube vertically, the picture tube is the wrong aspect ratio. The 16:9 picture is the correct width on the TV, but is too tall because it is displayed on a 4:3 picture tube. To compensate, the vertical size is automatically reduced when a 33.75kHz input signal is detected. The final 1080i picture is a letterbox on the KV32XBR400:
High Definition 1080i picture on the 4:3 aspect ratio KV32XBR400 TV 16 : 9 ENHANCED (VERT REDUCTION)

Aspect Ratio Detection The pictures aspect ratio is always 4:3 for a standard 480i input and 16:9 for a 1080I input. Unfortunately a 480p signal can be in either aspect ratio so the TV must be adjusted manually. The MID circuit monitors the horizontal frequency of the input signal when video 5 or 6 is selected. If the H. input frequency is 15.734kHz or 31.5kHz, blank lines are added and the picture is normally over-scanned vertically for a 4:3 picture. If the H. input frequency is 33.75kHz, IC201s (A board) vertical oscillator signal is amplitude reduced to maintain the correct aspect ratio for a 1080i, 16:9 picture on a 4:3 picture tube. Vertical reduction must be manually selected from the users setup menu when a 480p 16:9 signal is input.

16:9 aspect ratio - The MID circuit does have to add 60 lines to the 480p, 16:9 picture when the horizontal frequency is changed. When this 16:9 picture is placed on a 4:3 screen, the picture is too tall (screen width was reduced). To maintain the aspect ratio of the picture, the vertical size must be manually reduced so the picture looks normal on the TVs 4:3 screen.
480p 16:9 pix MID Circuitry 540p 540p

Picture Compensation using Horizontal Frequency Resolution Aspect Horiz Freq Vertical Lines Ratio Compensation added 480i 4:3 15.734kHz Normal Overscan Yes 480p 480p 1080i 4:3 16:9 16:9 31.50kHz 31.50kHz 33.75kHz Normal Overscan Yes Manual Reduction Yes Automatic Reduction No

4:3 Pix Tube

Vertical size reduced

B BD.

A BD.

TUNER/ VIDEO 480i 1-4 IC3048 STANDARD SW NTSC RESOLUTION

Y, Pb, Pr IC3303 DRC CIRCUIT

Yo -7 Cr-7 Cb-7

H+V

IC3408, IC3410 MID-XA CIRCUIT

C BD. IIC BUS DATA/ CLK IC201 Y/C CRT DRIVE IC9001-3 RGB OUTPUT

H+V SYNC

IIC BUS
VIDEO

DATA/CLK

CRT CATHODES

Y, Pb, Pr CONT

480i VIDEO 5 VIDEO 6 480i 480p 1080i

IC3603 ID-1 DECODE 480p 1080i

IC3414 YUV SWITCH

OSD

VERT OUTPUT IC5004 (D BD.)

SD TO HD CONVERSION CIRCUIT

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21

Video Block
This Video Block Diagram will show the video signal processing as it changes from an NTSC composite video signal to separate Y & C, component Y, Pb, Pr and finally to RGB for the CRT cathodes.
Channel 1 2 3 Name Input

3D Comb Filter - Color Bar input Location CN3201/pin 1 CN3201/pin 3 CN3201/pin 5 Comments 2Vp-p 2Vp-p 1.7Vp-p

Y Output C Output

Composite Signal Input (B Board)


The NTSC format video from one of the two tuners or video inputs 1-4 is selected by composite video switch IC3201. The user makes the selection from the remote to the Main uCom IC701 through the I2C bus into IC3201 (not shown). There are three outputs from IC3201: IC3201 Outputs
Name Main Sub Monitor Location CN3201/pin 1 IC3201/pin 56, 58 IC3201/pin Output Type Composite or Y (if S video input TV) Separate Y / C Composite Destination 3D Comb filter IC3501 Y/C Sub processor Rear panel output

Time base = 20usec/div

Component Video Conversion (B Board)


The separate Y & C main signal is matrixed into component Y, Pb, and Pr signals inside IC3048. This IC3048 can therefore act as a switch to choose between the component video input from Video 5, Video 6 or the main signal from the 3D Comb filter. An additional RGB signal from the closed caption / V Chip IC3602 can be matrixed into the signal path by IC3048 if these features are selected by the user. There are three outputs from IC3048: IC3048 Outputs

Name Main Signal H & V Sync Comp Video

Output Type Component 1Vp-p 1Vp-p

Destination Main/Sub selector Sync selector IC3004 CCD/V Chip IC3602, ID-1 IC3603

Y & C Separation (B Board)


The main composite signal enters the BC board that plugs into the larger B board. The 3D Comb filter separates the luminance from the chroma, pixel by pixel to output Y and C signals. The input and outputs of the Comb filter are accessible and shown as 2Vp-p signals with a DC component in this scope shot:
c h1 c h2 1

Comp Video / ID-1 Concept ID-1 Concept ID-1 is a relatively new concept. The ID-1 signal is hidden in the vertical blanking area of the picture. This ID-1 signal identifies the aspect ratio of the picture. IC3603 finds the signal and outputs data to the microprocessor. The micro can change the vertical or horizontal size to present the picture properly. Recently, an ID-2 signal containing the aspect ratio and copy guard information has been proposed. Main Signal Path The main component video and sync signals are sent to switches IC3002 (video) and IC3004 (sync). They switch between the main and sub pictures. The outputs go to the Digital Reality Creation IC3303.

c h3

C H 1 !2 .00 V ~ C H 2 !2 .0 0 V = STOP 3 C H 3 !2 .0 0 V = C H P M T B 2 0 .0 us line

c h 1p

CN3201/ CN3500 CN003/ CN3203


A10 A8 63 6 44 1

BC BOARD
76

B BD. SUB Y,Pb,Pr (IC3110) MAIN Y,Pb,Pr IC3002 YCT SEL DRC CD SEL/ SYNC-SEL MID-uCOM IC3090 HD, VD SUB TO DRC - MF IC3303

MAIN TUNER SUB TUNER A BD. VIDEO 1 - 4 480i FORMAT

COMPOSITE/ Y
47 15 96

IC3501 3D COMB FILTER


83 84

IC3003 SUB COMB

C IC3201 (S VIDEO) A/V SW - 1 Y C SUB OUT Y/C TO: YCT SUB (IC3110)

C
5 3

Y Y

CN3500/ CN3201 MAIN Y,Pb,Pr

C
48

46

A25

41

MONITOR OUT VIDEO 5-6 480i/ 480p/ 1080i U BD. Y,Pb, Pr

IC3048 YCT MAIN

SUB PIX COMPOSITE VIDEO IC3110 VID 5,6

MAIN HTIM,VTIM IC3004 RGB DRC IC3602 VIN SYN 1 CLOSE CAP SEL V CHIP VIN HTIM/VTIM SYNC IC3603 TO IC3413 ID - 1 DEC 2 I C/ BUS (TO MID DATA CLK uCOM IC3090) IC3001 COMP J - F

HD - S VD - S (IC3110)

COMPONENT VIDEO TO IC3414

VIDEO BLOCK 1/2

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Digital Reality Creation This 3rd generation device has three main purposes: To summarize the MID functions, 60 lines are added to the picture by the MID-XA main signal processor IC3408 when the horizontal frequency is not 33.75kHz. MID-uCom IC3090 instructs oscillator IC201 to reduce the vertical amplitude when the sync is 33.75kHz (High Definition signal). Signal and Sync Switches Using control signal from MID-uCom IC3090, switches IC3414 and IC3413 select final signal and sync for the Y/C CRT Drive IC201. The component video that leaves the B board is shown in the waveform:
P M 3 3 9 4 , F L U K E & P H IL IP S

Doubles the number of pixels on each scanning line after analyzing the pixels in the immediate area. Creates double the number of scanning lines by prediction.

Doubles the horizontal frequency to match the new image. The input is analog component video and the output is an 8 bit parallel port for each of the three component lines - Y, Pb and Pr. The digital output goes to the MID circuit IC3408. Multi Image Driver (MID) Circuit

ch1

The purpose of the MID circuit is to:

Displays two images on the same screen (Main and Sub or Main and High resolution). Add 60 blank lines to the picture. Change the input signals horizontal frequency from 31.5kHz to 33.75kHz. Instruct the related MID uCom IC3090 what the input horizontal frequency is so it can control the sync path and aspect ratio.
1 2 3

ch2

ch3

Component Video leaving the B board - Color Bar input Channel Name MID Y MID Cb MID Cr Location CN3203/pin B8 CN3203/pin B9 CN3203/pin B10 Comments 0.7Vp-p 0.7Vp-p 0.7Vp-p

Any input signal selected is present at the MID-XA signal processor IC3408, so it knows what the input horizontal frequency is. Using this information, the interconnected MID-uCom IC3090 can control the signal and sync routing as well as send information to the Y/C CRT Drive IC201 for vertical reduction. MID-uCom IC3090 Outputs

Time base = 10usec/div

Name DO, CO (data, clock) IIC data bus Sync Sel

Destination MID-XA IC3408 Y/C, CRT Drive Sync Sw IC3413

Purpose Add 60 blank lines Vertical Reduction Sync for IC201

The following waveforms show the horizontal sync compared to the Y signal. After the MID circuit, the frequency is 33.75lkHz.

MAIN Y,Pb,Pr FROM IC3002 (YCTSEL) HD,VD SYNC FROM IC3004 (DRC-SYNSEL) II C BUS

OSD,RGB FROM MAIN uCOM IC701 YO-7 CRO-7 IC3303 DRC - MF CBO-7 H+V IC3408 MID - XA YO-7 CRO7 IC3410 D/A H DRIVE V DRIVE C BD.

CBO-7 Y,Pb,Cr IC201 Y/C CN3203/ CRT CN003 VIDEO DRIVE B8


B9 B10

RGB TO CRT

MID-uCOM IC3090 CONT: TO IC3414 (YUV SW)

DO,CO DATA/ CLK Y,Pb,Pr

IC3402 64M SDRAM

CONT. MID-uCOM IC3090

Y MID CB CR IC3414 YUV SW. IC3413 SYNC SW.

CN202/ CN9001 R
1 3 5 8

G MID H B14
B15

COMPONENT VIDEO FROM IC3001 (AV-SW1) SYNC SEL

B IK
10

IC9001, IC9002 IC9003 RGB OUT G2 MUTE

HIGH DEFINITION VIDEO 5 OR 6

MAIN H, PROG VERT

MID V

SYNC II C BUS

B BD.

HTIM HD HORIZ. IC3048 (YCT MAIN) VTIM INTERLACE VERT IC3048,(YCT MAIN)

P MUTE POWER OFF MUTE FROM MAIN uCOM IC701/67, Q708,Q730

A BD.

VIDEO BLOCK 2/2

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25
Component Video leaving the B board - Color Bar input
c h1 c h2 1

c h3

(vertical blanking area of ch 1) is still at 3Vp-p (power On level). The normal green signal (ch 2) shows the IK signal is reduced to 1.8Vp-p because the IK loop is complete. The last waveform (ch 3) does not show the missing red IK signal because of sampling errors in the digital scope used. IK drive pulses

3 39

&

ch1

3 C H 1 ! 50 0 m V~ C H 2 ! 2 .0 0 V = C H 3 ! 2 .0 0 V = C H P M T B 1 0 .0 u s lin e ch1p
ch3 ch2 T

Channel 1 2 3

Name Mid Y Mid H Mid V

Location CN3203/pin B8 CN3203/pin B14 CN3203/pin B15

Comments 0.7Vp-p 3.8Vp-p 3.8Vp-p

C H 1 ! 2 .0 0 V = C H 2 ! 2 .0 0 V =

Vertical blanking
C H P M T B 5 0 0 u s - 1 .0 8 d v c h 1 -

Time base = 10usec/div

C H 3 ! 1 .0 0 V = 3

IK drive signal in the vertical interval - Color Bar input


RGB Drive / AKB Circuit The Y/C CRT Drive IC201 has several functions:

Channel 1 2 3

Name R Drive G Drive B Drive

Location (C board) CN9001/pin 1 CN9001/pin 3 CN9001/pin 8

Comments 4Vp-p (open circuited) 3Vp-p 1.4Vp-p

Automatic Cathode Balance (AKB) or IK (cathode current) The AKB circuit monitors the CRT cathode currents and adjusts the RBG drive levels to compensate for CRT aging. By adjusting RGB drive levels to simulate the same cathode currents, white balance can be maintained. To accomplish this task, at power ON three IK drive pulses (about 3Vp-p) from IC201 are sent to each CRT cathode (video is muted). The cathode currents from all three cathodes are returned to IC201 on the single IK line. The three pulses are used to adjust the RGB drive pulses (and RGB gain) to produce equal amplitude IK return pulse levels. When the AKB loop closes, the AKB drive pulse is reduced (1.8Vp-p - ch 2). Finally, the video signal is unmuted to display a picture. To see the full operation in the next scope shot, the red drive wire has been opened at CN9001/pin 1. The CN9001/pin 1 connector is shorted to ground to simulate a defect red cathode. Notice the red IK drive pulse

Amplifies the RGB signal and applies it to the CRT cathodes Mixes the main signal with the RGB On-Screen Display (OSD)

Time base = 0.5msec/div


Technical Note: If one or two cathodes falls below AKB adjustment range, the video will NOT blank as in other AKB circuits. However, if a cathode draws too much current, (Ik pulse gets large) the picture will blank, and the standby light will blink five times and repeat. In normal operation, if you increase the screen voltage, the IK return pulses (ch 3) will increase in amplitude because more cathode current is drawn. Because of the AKB closed loop, IC201s output IK drive pulses (ch 2) will decrease to lower the cathode current.

MAIN Y,Pb,Pr FROM IC3002 (YCTSEL) HD,VD SYNC FROM IC3004 (DRC-SYNSEL) II C BUS

OSD,RGB FROM MAIN uCOM IC701 YO-7 CRO-7 IC3303 DRC - MF CBO-7 H+V IC3408 MID - XA YO-7 CRO7 IC3410 D/A H DRIVE V DRIVE C BD.

CBO-7 Y,Pb,Cr IC201 Y/C CN3203/ CRT CN003 VIDEO DRIVE B8


B9 B10

RGB TO CRT

MID-uCOM IC3090 CONT: TO IC3414 (YUV SW)

DO,CO DATA/ CLK Y,Pb,Pr

IC3402 64M SDRAM

CONT. MID-uCOM IC3090

Y MID CB CR IC3414 YUV SW. IC3413 SYNC SW.

CN202/ CN9001 R
1 3 5 8

G MID H B14
B15

COMPONENT VIDEO FROM IC3001 (AV-SW1) SYNC SEL

B IK
10

IC9001, IC9002 IC9003 RGB OUT G2 MUTE

HIGH DEFINITION VIDEO 5 OR 6

MAIN H, PROG VERT

MID V

SYNC II C BUS

B BD.

HTIM HD HORIZ. IC3048 (YCT MAIN) VTIM INTERLACE VERT IC3048,(YCT MAIN)

P MUTE POWER OFF MUTE FROM MAIN uCOM IC701/67, Q708,Q730

A BD.

VIDEO BLOCK 2/2

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27

Picture with Picture


The picture with picture feature in the Sony model KV32XBR400 and 36XBR400 TVs displays two signals side by side. The picture-in-picture feature containing a small sub picture in one of the corners of the main picture is not used in this TV set. If the left or right picture is defective or missing, the signal path is required to localize the defect. There are two signal paths, one for each picture. In comparing the two diagrams, you will note that the main picture is on the
CN003/ CN3203
A10

left when both pictures are standard 480i video resolution. The confusing part is that when video 5 or 6 is selected and a 480p or 1080i signal is detected, the main picture moves to the right. There is no swap button to exchange pictures. Standard Resolution Input When only standard resolution signals are selected in the picture-withpicture mode, the left picture will pass through the DRC-MF circuit for detail improvements. The right picture will enter the MID-XA circuit directly to be reduced and merged with the main DRC picture on the same screen.
480i Y,Pb,Pr IC3303 DRC MF B BD.

MAIN TUNER SUB TUNER A BD. VIDEO 1 - 4 VIDEO 5 - 6 U BD.

MAIN TU - V
A6

MAIN A/V SWITCHES COMPOSITE TO COMPONENT MATRIX SUB

SUB TU - V

MAIN CN3203/ CN003 MAIN + SUB

A BD. IC201 CRT DRIVE

SUB

IC3408 MID XA

MAIN TUNER VIDEO 1 2 3 4 VIDEO 5 - 480i 6 - 480i

MAIN 480i PIX IN DRC PROCESS

SUB 480i PIX

SUB TUNER VIDEO 1 CRT 2 3 4

IC9001 - 3 VIDEO OUT C BD.

CN9001/ CN202

INPUTS ARE 480i

PICTURE WITH PICTURE - STANDARD RESOLUTION

High Resolution Input If video 5 or 6 inputs were selected, the MID circuit measures the signals horizontal frequency to identify the video signal. If the frequency is higher than 15.75kHz, the signal is either 480p or 1080i. The MID uCom toggles switches to set up the signal path shown in the diagram below. When a 480p or 1080i signal is detected, this picture will be placed on the left side of the screen.
CN003/ CN3203
A10

The right 480i main picture will come from the tuner or video 1-4 signals along the top 480i path through the DRC-MF IC3303. The right side picture in Twin View cannot select video 5 or 6 inputs (they are skipped during the selection).

MAIN TUNER A BD. VIDEO 1 - 4 VIDEO 5 - 6 U BD.

480i Y,Pb,Pr A/V SWITCHES COMPOSITE TO COMPONENT MATRIX IC3303 DRC MF

MAIN PIX IC3408 MID XA

MAIN

IC3001 COMP J-F B BD.

HD PIX

MAIN + HD

CN3203/ CN003

C BD. VIDEO 5,6 Y,Pb,Pr 1080i/480p 480i PIX IN DRC PROCESS TO CRT IC9001 - 3 VIDEO OUT

A BD. IC201 CRT DRIVE CN9001/ CN202

HIGHER RESOLUTION VIDEO 5 6

STANDARD RESOLUTION MAIN TUNER VIDEO 1 2 3 4

PICTURE WITH PICTURE - HIGH RESOLUTION INPUT

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29

Power ON Block
Power Supplies
There are four power supplies in the XBR400 TV:
KV32XBR400 Power Supplies Name Standby Primary Secondary Board A A D Start Plug in Power ON Primary Pre 15V, Main Relay Horiz Output AFC-PLS Purpose 5V for Main uCom 7V & 15V for power relay Unreg 11V, 7V, 5V become regulated 9V, 5V, 3.3V. +200V for HV stage, +135V for H. Output, +15V, +24V for Audio stage 31.5kV HV for CRT, Focus voltage.

Primary & Secondary Power Supplies


Before power ON can occur, the front panel master ON/OFF button (S01 on the HA board) must be pressed in. This latching switch behind the button supplies the AC relay (RY6501) with standby 7V. Pressing the switch again would unlatch the switch and the set would shut OFF. Power ON can be activated from the remote control or when the front panel button is latched in. The second half of front panel switch S01 (not shown) grounds out the power ON input to Main uCom IC701. IC701 powers ON the TV by turning on relay driver Q6527. Q6527 grounds one end of relay RY6501 and momentarily turns on Q710 via C724. Q710 supplies a higher +15V to AC relay RY6501 because a relay needs more voltage to close the contacts than to hold them closed.

Primary Power Supply


This power supply only needs 340Vdc from the bridge rectifier D6530 to start up and run. Three voltages with the prefix set are used on the A and plug in B and BC boards. The most important voltage is the Pri Pre 15V output that starts up the Secondary power supply on the D board.

HV Converter (not shown)

Except for the Standby power supply, the Primary, Secondary and HV Converter supplies are similar. The last three supplies use the same IC in a similar configuration. How they are turned on and the voltages they deliver is what makes them different. Each power supply is turned on in the order listed. The first power supply is operational when the TV is plugged into AC. When the TV is powered ON, the second and third supplies are turned ON one after the other. These supplies power the horizontal stages. Finally, the fourth power supply is turned ON after the horizontal output transformer develops scan, filament voltage and AFC pulses. The last power supply is not shown on this diagram, but knowing when the HV is powered on is important for troubleshooting.

Secondary Power Supply


The Secondary Power Supply needs three items to operate:

Three Items needed to run the Secondary Power Supply Item 340Vdc (B+) Pri Pre 15V voltage Main Relay (normally HIGH) From Primary Power Supply secondary Main uCom IC701 Purpose Starts the oscillator when more than 15.6Vdc. Enables IC6501 when HIGH Bridge Rectifier D6530 Powers the Driver/Output

Standby Power Supply


When the TV is plugged in, the standby power supply outputs three voltages: +15V, +7V, and +5V. A small transformer develops the +15V and +7V. The +7V is regulated down to +5V to power the Main uCom IC701.

This secondary power supply produces the remainder of the low voltages to power the TV. The +200V feeds the HV Converter power supply. The +135V powers the Horizontal stages. The +15V makes Main 12, Main 9 and Main 5V used throughout the D board. The +24V feeds the audio output stage.

STANDBY 5V F6001 6A STANDBY P.S. STANDBY 7V STANDBY 15V SOURCE IC6010 IC6007 IC6003 DEGAUSSING CIRCUIT STANDBY 7V D721 S 01 AC OUT CN6013/ 1 2 CN6502 FRONT PANEL POWER (HA BD.) CN7003/
1 3

SET 9V SET 5V SET 3.3V SOURCE

DCC COIL DGC COIL

UNREG. STANDBY 11V 7V 5V 5V

STANDBY 15V AC RELAY

D722

Q710

IC701 MAIN uCOM MAIN RELAY

IC6001 PRIMARY POWER SUPPLY PRI PRE 15V

C724 SET ON CN702/ 1 CN6504

POWER ON (HA BD.) CN6005/ 1 CN6501

R6006

A BD.

CN6503

Q6527 RY6501 AC D6530

Q6530, Q6532 PROT. LATCH

OVP OCP +135V

AC RECT +

D BD.

+200V IC6501 SECONDARY POWER SUPPLY +135V + 15V +24V AUDIO SOURCE

MAIN RELAY

R6526

POWER ON BLOCK

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Primary Power Supply


The primary power supply on the A board consists of three parts: 1. Oscillator 2. Output stage 3. Regulator Stage

into pin 14. Internal pulses from IC6001/pin 14 add to D6003s DC voltage, producing the boost voltage at Vb pin 14. This boost voltage is approximately +10V above the reference voltage at IC6001/pin 15 and used internally to serve as the B+ for the top internal drivers that amplify oscillator signal leaving IC6001/pin 16. Secondary Power Supply Starting The Pri Pre 15V output of D6009 is only approximately 10Vdc at start up when the oscillator frequency is high (normally about 18Vdc). When is reaches 15.6Vdc, it starts the Secondary Power Supply. Therefore, the Secondary Supply cannot start until the Primary Supply is running.

Start Up
The oscillator within IC6001 starts if the V Sense input voltage at pin 1 is above 1.3Vdc. Sample voltage from pin 18 is then used to run the internal oscillator. The initial frequency is approximately 200kHz. The low amplitude initial oscillator signal is output IC6001/pins 12 and 16 into the driver/output stage.

Regulation
Concept T6003s secondary output voltages are dependent upon the match between the output resonate circuit (T6003 = L, C6014 = C) and the oscillator frequency. When IC6001s oscillator frequency is the same as the resonate circuit frequency, there is maximum power transferred in T6003 producing maximum output voltage. By setting the oscillator frequency above resonance, T6003s output voltage can be regulated.
85kHz = Normal Operation 200kHz = Start Up

Driver / Output stage


The oscillator voltage output at pins 12 and 16 use drivers Q6007 and Q6008 to develop T6003 secondary voltages. IC6001s oscillator will shut down if the driver transistors current is excessive. To prevent premature shutdown, the timer capacitor C6064 delays the shutdown. VC1 Enables the Regulator Although the oscillator is running, at this initial frequency of 200kHz, there is insufficient current from T6003 to produce any unregulated 5, 7, or 11V voltage because of the load. There is little load on D6005 and D6009, producing about 15V each at the cathodes (normally about 18Vdc). The voltage from D6005 is returned to IC6001/pin 8 to serve as regulated B+ for the internal drivers that amplify the oscillator signal leaving pin 12. The VC1 voltage also enables the internal regulator circuit (responds to the error voltage input IC6001/pin 2) to change the oscillator frequency. B+ for IC6001s Internal Drivers At start up IC6001 uses current limited B+ from pin 18 to amplify the oscillator signal and get it out to pin 16 (internal drivers). When VC1 is present, the internal drivers switch to this stable regulated B+. The B+ for the internal drivers for IC6001/pin 16 comes from Vb at pin 14. D6003 and C6009, external to IC6001/pins 10 and 14 (Vb), complete an internal voltage boost circuit. This boost circuit starts with VC1 voltage (input pin 8) that is connected internally to VC2 pin 10 (less 0.6Vdc). This VC2 voltage is filtered by C6009 and passes through blocking diode D6003

T6003 Output Voltage

Output Voltage Control The regulating stage uses error detector IC6002 and optical isolator PH6001 to monitor the unregulated +7V output from T6003. If the unregulated +7V output is LOW as it is at initial start up, the voltage fed back to IC6001/pin 2 goes HIGH, decreasing the oscillator frequency. The decrease in frequency increases the output of the T6003 transformer, until +7Vdc is reached.
Regulation Feedback Voltages Unreg 7V Output (D6011) Low PH6001/pin 2 high IC6001/pin 2 high

D6012 A BD. T6003 UNREG. 5V SOURCE AC RECT.+ FROM D6530 (D BD.) R6606 0.47 OHMS 340VDC R6059
18

D6013 UNREG. 11V SOURCE Q6008 VGH 16 N CH 160V Q6007 VGL 12 N CH R6043 R6049 C6014 D6011 UNREG. 7V SOURCE R6002 R6010 PRI PRE 15V (D BD.) D6009 D6005

R6007 R6008 VD

R6009

V SENSE
1

VS 15 IC6001 DRIVER MCZ3001D

3V R6011

TIMER VC1 VC2


6 8 10

OCP VB
14

F/B
2

C6064

+
1

1.86V D6003 + C6009 PH6001 OPTICAL ISOLATOR

R6050 IC6002 ERROR DET. uPC1093C

R6022 R6029
1

18.4V

PRIMARY POWER SUPPLY

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In the following scope shot both drive outputs from IC6001/pins 12 and 16 are shown. The outputs are complementary, the duty cycle is 50% and the frequency has dropped down from 200kHz to about 85kHz.
ch1 pkpk= 3 5 V : 2 ch1 ch1 fre 84 kH : q= .8 z ch2

Hot ground is at CN6501/pin 6 (black wire).

Oscillator Output Operation


The details of how the oscillator develops output voltage in T6003 are explained here. When the oscillator in IC6001 starts up (V Sense = 3V, no feedback VC1 voltage yet), the signal is amplified using unregulated voltage input pin 18 and a 200kHz signal is output IC6001/pins 12 and 16. This is shown in the following waveform:
PM 3394, F LUKE & PH ILIPS ch1: pkpk= 34 V 9 ch1 ch1: freq= 209kH z

ch2
C 1! 1 0 V H 0 = C 2!5 0 V H .0 = M B .0 us- 1 8 ch1 T 2 0 .1 dv -

Primary PS Oscillator - Normal operation - 85kHz


T

Channel 1 2

Name Top Driver Output Bottom Driver Out

Location Q6008/gate Q6007/gate

Voltage 340Vp-p 12Vp-p (4.6Vdc)


2 C 1!79.9 V= H C 2!10.0 V= H M TB1.0 0us- 1.28dv ch1+ 1

Time base = 2usec/div.

Testing
Checks for Primary power supply operation Check Point 1. R6006 2. CN6005/ pin 5 3. IC6001/ pin 2 (Feedback voltage) Normal 340Vdc >+15.6Vdc 1.9Vdc P.S. Input voltage Pri-Pre 15V. Checks P.S. Output If step 2 voltage is low, measure IC6001/pin 2. If pin 2 is High (4V) problem is around IC6001. If pin 2 is Low (0-1V), problem is the feedback path IC6002, PH6001.

Primary PS Oscillator - Start Up = 209kHz Channel 1 2 Name Top Driver Output Bottom Driver Out Location IC6001/pin 16 IC6001/pin 12 Voltage 340Vp-p 12Vp-p (4.6Vdc)

Time base = 1usec/div.


The two signals applied to the Q6008 and Q6007 drivers are complementary. This means only one MOSFET is conducting at a time. A positive voltage applied to top MOSFET Q6008s gate turns it ON so its Drain to Source resistance drops, increasing the voltage to T6003s primary winding. This voltage passes through the primary winding of T6003 into C6014. As the increasing voltage charges C6014, a magnetic field is built up in the primary of T6003. This magnetic field induces voltage into the secondary windings that is rectified to supply low voltages to the TV set. The cycle continues when Q6008 turns OFF and Q6007 turns ON. The charged C6014 discharges through the primary of T6003 and Q6007 to ground. The cycle then repeats.

4. IC6001 voltages. See the next chart. IC6001 Voltages (Power ON, Video 1 input, Dark screen) 1. 3.0V 10. 10V 2. 1.8V 11. 0V 3. 2.2V 12. 4.5V 4. 2.5V 13. -0.2V 5. 0V 14. -28V 6. 0V 15. -32V 7. 4.5V 16. -32V 8. 18.4V 17. -0.3V 9. 0V 18. 313V

D6012 A BD. T6003 UNREG. 5V SOURCE AC RECT.+ FROM D6530 (D BD.) R6606 0.47 OHMS 340VDC R6059
18

D6013 UNREG. 11V SOURCE Q6008 VGH 16 N CH 160V Q6007 VGL 12 N CH R6043 R6049 C6014 D6011 UNREG. 7V SOURCE R6002 R6010 PRI PRE 15V (D BD.) D6009 D6005

R6007 R6008 VD

R6009

V SENSE
1

VS 15 IC6001 DRIVER MCZ3001D

3V R6011

TIMER VC1 VC2


6 8 10

OCP VB
14

F/B
2

C6064

+
1

1.86V D6003 + C6009 PH6001 OPTICAL ISOLATOR

R6050 IC6002 ERROR DET. uPC1093C

R6022 R6029
1

18.4V

PRIMARY POWER SUPPLY

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35

Secondary Power Supply


The Primary and Secondary power supplies are similar because they use the same IC and driver/output stage. They differ in start up and output voltages.

Regulation
The +135V line to the Horizontal Output stage is fed back to IC6501 for regulation of the secondary power supply. Error Control IC6503 and Optical Isolator PH6502 control regulation. If the +135V output rises, the voltage at IC6501/pin 2 lowers to correct. A reduced voltage increases the oscillator frequency and decreases the output voltages of T6501.

Start UP
Although IC6501 is identical to IC6001 in the Primary power supply, IC6501/ pin 18 in this supply is not connected to 340Vdc. This makes VC1 at pin 8 the primary source of power to start this IC after pin 1 senses voltage. The start up sequence is listed as follows: 1. 340Vdc (B+) is applied to this stage from bridge rectifier D6530. 2. Pri Pre 15V voltage from the Primary power supply is applied to IC6501/ pin 8. It must be at least 15.6Vdc to enable IC6501s internal oscillator. 3. Main Relay signal from Main uCom IC701/pin 72 (HIGH at CN6501/ pin 5) turns ON Q6531, PH6503 and Q6528. Q6528 turns OFF Q6503, enabling voltage to appear at IC6501/pin 1. 4. R6646 and R6513 deliver at least 1.3Vdc to IC6501/pin 1. 5. IC6501 turns ON using voltage from pin 8 to run the oscillator. 6. An internal diode connected between pin 8 and 10 supplies voltage to VC2. 7. Oscillator pulses from VC2 pass blocking diode D6502 to make a (pump up) voltage for the internal predriver amplifier stage. 8. Oscillator signal outputs IC6501/pins 12 and 16. In summary, these items are necessary to run the Secondary Supply:
Three Items needed to run the Secondary Power Supply Item 340Vdc (B+) (CN6501/pin 1) Pri Pre 15V voltage (CN6501/pin 5) Main Relay (normally HIGH at CN6504/pin 2) From Purpose Bridge Rectifier D6530 Powers the Driver/Output Primary Power Supply secondary Main uCom IC701 Starts the oscillator when more than 15.6Vdc. Enables IC6501 when HIGH

Testing
The typical error correction feedback voltage at IC6501/pin 2 is 2Vdc. By measuring the +135V B+ at R6598 and the feedback at IC6501/pin 2, you can determine if the problem is in the basic oscillator stage or the error regulator stage.
1. Measure B+ at R6598 (0.27 ohms at 1W) B+ is LOW or 0V 2. Measure IC6501/pin 2 Voltage Higher than 2V Lower than 2Vdc B+ is HIGH (shutdown Stby light blinks 3 times) IC Higher than 2V Lower than 2Vdc 3. Problem area

Oscillator stage IC6501 Error regulating stage IC6503/PH6502 Error regulating stage IC6503/PH6502 Oscillator/Driver Stage IC6501

V l (P ON Vid i D k ) IC6501 Voltages (Power ON, Video 1 input, Dark screen)

1. 2.5V 10. 10V

2. 1.8V 11. 0V

3. 2.2V 12. 4.7V

4. 2.5V 13. 0V

5. 0V 14. -15V

6. 0V 15. -19V

7. 4.0V 16. -19V

8. 18.3V 17. 0V

9. 0V 18. 1.5V

Hot ground is at CN6501/pin 6 (black wire).

AC

D6530

R6526 0.1 OHM R6646 DC


18

T6501 PIT

GND AU + 24 TO AUDIO D6516

AC PRIMARY POWER SUPPLY

NO CONNECTION D6515 Q6507 N CH R6533 VS


15

R6513
1

VD VGH 16 V SENSE

D6517 D6513

+200V SOURCE TO HV SOURCE R6598 135V SOURCE

Q6503 N R6504 R6552 OFF R6517 STANDBY 5V


1

Q6506 VGL 12 IC6501 DRIVER MCZ3001D OCP 9 V B 14 N CH R6535 R6501 R6556 D6502 VC2 10 F/B 2
8 4

Q6528 N

- 15V SOURCE + 15V SOURCE

PH6503 3 OPTICAL ON ISOLATOR


2

C6532

D6514
1 1

R6590

R6557

MAIN RELAY FROM MAIN uCOM IC701/72 (A BD.)

ON

Q6531 N

PH6502 OPTICAL ISOLATOR

IC6503 CONTROL 4 DM-58


5

VC1

PRI PRE 15V CN6005/6 (A BD.)

START D BD.

SECONDARY POWER SUPPLY

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Horizontal Drive / H Pincushion Correction / Filament Voltage


Overview
The purpose of the horizontal drive circuit is to manufacture a magnetic field that is used to sweep the CRTs electron beam from left to right on the screen. Within the basic horizontal drive circuit there is a PWM circuit that supplies the Horizontal Output transistor with voltage and provides horizontal pincushion correction. The horizontal drive circuit also makes the CRT filament voltage.

quency, but the MID circuit stored the video and output the signal at a new H freq. of 33.75kHz, independent of the source.
PM3394, FLUKE & PHILIPS ch1 1

ch2

ch3

ch4

CH1!2.00 V~ CH2!2.00 V~

Basic Horizontal Drive Circuit


This circuit is split between an oscillator on the A board and an output stage on the D board. The 33.75kHz horizontal oscillator is in the Y/C CRT Drive IC201. IC201 outputs a 2Vp-p rectangular waveform from pin 40 while there is B+ at pins 55 & 61 and the 2.7MHz X201 crystal is running. The horizontal drive waveform is buffered by Q211 and enters the D board. On the D board, an N channel MOSFET driver and an output transistor amplify the signal to provide sufficient current to drive the HOT T5001 and the H DY deflection yoke. At the output stage, the HOT T5001 has a secondary winding that provides filament voltage while its main winding provides +200V for the RGB video output ICs. While the H DY yoke provides horizontal beam deflection (sweep), a voltage divider consisting of capacitors C5058-C5060 tap off a sample of the H spike from the H Output Q5030/Collector to start the HV converter stage. This AFC-PLS is also used in the convergence and dynamic focus stages. The waveforms of the horizontal drive stage show typical signal shapes. The difference between this set and a conventional one is that the horizontal frequency is 33.75kHz (ch 2), not 15.75kHz (ch 1). When comparing the input sync (ch 1) to the horizontal oscillator (ch 2), notice that they are not in phase. This is because the DRC circuit doubled the H freChannel 1 2 3 4

CH3!10.0 V~ STOP 4 CH4! 125 V= ALT MTB5.00us L=2

ch2p

Horizontal Drive Signals Name 15.75kHz H signal Input 33.75kHz osc output H Driver input Horiz Output Location NTSC generator IC201/pin 40 Q5028/gate Q5030/Collector Voltage from the generator 2.2Vp-p 12Vp-p 1kVp-p

Time base = 5usec/div.

PWM Circuit
The PWM circuit has two functions. First it provides a regulated 102Vdc output for the H Output transistor. Second it compensates for horizontal pincushioning and keeps the picture straight at the sides.
No horiz pincushion correction Pix is bowed inward

MAIN 9V MID HS IC3413/4 SYNC SW. (B BD.) A BD. AFC-PLS Q5030/C H. PROT IC701/44 Y/C (A BC.)

X201
61 55 39 33

HD IC201 Y/C CRT 40 DRIVE Q211 CXA2150Q


47

CN203/ CN5505
2

Q5035, Q5036, Q5026-7 H DRIVE

MAIN 12V

RGB VIDEO OUTPUT (C BD.) Q5016 200V REG. D5013

37

CN201/ CN5503

E/W DRIVE

135V IC5002, Q5003, Q5011 PWM CIRCUIT 102V


1 2

CRT HEATER T5001 HOT R5096 D5015


8

Q5004 OCP

HOT C5035 100

+135V R5013 R5095


7 6

IC5006 6V REG. D5014

D5024

T5002 HDT R5142-4 N CH D BD.

Q5030 H OUT C5058 N

R5094

D5012 H DY

G2 TO C BD.

R5164 D5025

D5023 C5059 C5060 D5018 50V

Q5028 DRIVER

UNREG. 7V (A BD.) AFC-PLS TO: IC8001/8 HV CONV. IC5511/19 DQP CONT. IC5513/14 DY-CONV. IC201/39 Y/C CRT DRIVE
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HORIZONTAL DRIVE

38

39
Regulator The PWM circuit regulates +135Vdc from the secondary power supply down to 102Vdc. It is driven by H drive pulses from Drivers Q5026-7. These pulses are amplified and output to HOT T5001/pin 1. To control the output voltage, the output is sampled and used to change the pulse width of the H drive pulses. These changes regulate the output voltage to 102Vdc at T5001/pin 1. Pincushion correction If the PWM output voltage at T5001/pin 1 were changed, the horizontal picture size would vary accordingly. A vertical pincushion signal made by IC201/pin 47 is applied to this PWM stage to increase the picture width and compensate for pincushion distortion. The first waveform shows the input E/W (east/west) pin correction signal. The second waveform is the PWM output. The corresponding modulation (sum of E/W signal and horizontal drive) changes the width of the output pulses (ch2), but that is not easily seen at this scopes time base.
ch1

Filament Voltage
There are two sources of filament voltage. When the set is turned ON, unregulated 7V from the primary power supply (A board) is reduced by D5025 and D5024 to approximately (7V-1.2V =) 5.8Vdc. This is the first filament voltage source used warm up the CRT quickly at power ON. There is no danger from this unregulated 7V supply. Excessive voltage on the unregulated 7V-line causes Main uCom IC701 to shut down the TV set (protection circuit not shown here). Consequently, filament damage from an unregulated primary power supply is unlikely unless a technician bypasses the protection circuitry during troubleshooting. The second filament voltage is applied when the horizontal oscillator signal produces horizontal sweep. The horizontal output transformer T5001/ pin 8 outputs 7.7Vdc when running. This voltage is regulated to 6.1Vdc by IC5006 to become the main filament voltage.

1 ch2

CH1! 500mV~ CH2!50.0 V= MTB5.00ms ch1+

Horizontal Pincushion Correction Channel 1 2 Name E/W Drive PWM Output Location Cn5505/pin 7 T5001/pin 1 Voltage 0.7Vp-p 150Vp-p. 102Vdc

Time base = 5mesc/div.

MAIN 9V MID HS IC3413/4 SYNC SW. (B BD.) A BD. AFC-PLS Q5030/C H. PROT IC701/44 Y/C (A BC.)

X201
61 55 39 33

HD IC201 Y/C CRT 40 DRIVE Q211 CXA2150Q


47

CN203/ CN5505
2

Q5035, Q5036, Q5026-7 H DRIVE

MAIN 12V

RGB VIDEO OUTPUT (C BD.) Q5016 200V REG. D5013

37

CN201/ CN5503

E/W DRIVE

135V IC5002, Q5003, Q5011 PWM CIRCUIT 102V


1 2

CRT HEATER T5001 HOT R5096 D5015


8

Q5004 OCP

HOT C5035 100

+135V R5013 R5095


7 6

IC5006 6V REG. D5014

D5024

T5002 HDT R5142-4 N CH D BD.

Q5030 H OUT C5058 N

R5094

D5012 H DY

G2 TO C BD.

R5164 D5025

D5023 C5059 C5060 D5018 50V

Q5028 DRIVER

UNREG. 7V (A BD.) AFC-PLS TO: IC8001/8 HV CONV. IC5511/19 DQP CONT. IC5513/14 DY-CONV. IC201/39 Y/C CRT DRIVE
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HORIZONTAL DRIVE

40

41

G2 Circuit
RV9002 Position

G2 (RV9002) Voltage Range G2 Voltage 292.4Vdc 484Vdc 590Vdc is maximum before shutdown CCW Normal 2/3 CW

Operation
The G2 circuit controls the voltage to the screen grid of the CRT. The higher the voltage the more electrons are accelerated in the gun structure, resulting in a brighter picture. The source of the G2 voltage is approximately 1kV from the Horizontal Output Transformer (T5001) secondary winding. The G2 control circuit uses three transistors to shunt some of the G2 source voltage to ground. The remaining voltage is applied to the CRTs G2 grid. A simplified diagram of this voltage divider is shown below:
Approx. 1kV from the HOT T5001/6 CRT G2 voltage

Operating Voltages
Normal Operating Voltages Transistor Q9002 Q9008 Q9012 Q9014 Collector 10.9V 12.0V 10.4V 438.5V Base 0V 5.4V 5.4V 11.5V Emitter 0V 4.8V 4.8V 10.9V

Resistor string

Automatic Video Mute


Shunt Transistors Q9014, Q9012, Q9008

G2 HV Adj RV9002

At power OFF, the Main uCom IC701 outputs a HIGH that turns on Mute transistor Q9002. Q9002 lowers the G2 voltage, blanking the video when the TV is shut off. The HIGH remains present as long as the TV is plugged in (standby voltage is present).

Within the shunt circuit are three transistors. Q9008 is used as a reference while Q9012 and Q9014 set the resistance to ground. Rotating RV9002 varies the conduction of Q9012 and Q9014, and consequently the shunt resistance. A lower shunt resistance produces a lower G2 voltage. The G2 voltage range of the screen control is listed in the chart.

G2 VOLTAGE FROM HOT T5001/6 (D BD.) 12V

R9055

R9085

R9064

R9084

489VDC R9063 100k 1/2W N Q9014 G2-REF

R9062 100k

R9056 100k 484VDC CRT G2 GRID

907VDC

180k OHMS EACH D9013 G2-DUMP +

R9077 1k

C9032

C BD.

D9014 PROT

R9067

R9076 D9015 PROT D9003 R9004 D9001 + D9016 PROT D9017 PROT RV9002 100k G2 R9063 R9078 Q9008 G2-REF Q9012 G2-REF N N 10.4V

R9005 Q9002 MUTE N

FROM MAIN POWER uCOM OFF MUTE IC701/67 (A BD.) R9009 10k + C9038 4.7

C9036 10 R9010 10k

5.4V

R9079 +

R9081 C9037 2.2

C9047 0.01 CHIP

G2 CIRCUIT

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43

HV Converter Block
This HV Converter is similar to the two low voltage power supplies because they have the same MCZ3001D ICs. This power supply differs only in the start up, voltage output, and over voltage (OV) protection. The Flyback Output transformer of this power supply generates regulated 31.5kV and focus voltage for the CRT. Excessive current drawn by this stage will permit Q8009 to shut down the TV set, but there will be no Standby light blink indication.

Protection / Shutdown
There are two protection circuits for the HV stage. The first circuit shuts down the HV oscillator if the HV is excessive (without affecting the sound). The second circuit shuts down the entire TV set if the +200V current demand is excessive. Excessive HV Protection The HV oscillator in IC8002 is stopped if the HV sampled from the flyback is excessive. The oscillator stops when via Q8003 or Q8004 grounds IC8002/pin 1. Sample high voltage from the flyback transformer normally takes two paths to keep Q8003 and Q8004 turned OFF. The first path is from D8014 through 33V zener D8025. If the sample HV is excessive, zener D8025 conducts, turning ON Q8010. A LOW voltage outputs to IC8001/pin 7. The LOW input and output turns Q8003 ON, grounding IC8002/pin 1. This shuts down the HV Converter stage. The second shutdown path is from D8014 through R8078, and IC8001 to Q8004. An excessive voltage will similarly turn Q8004 ON, shutting down the HV Converter. RV8001 and RV8003 form a voltage divider along the feedback path to set the shutdown point. Excessive Current Protection Excessive current drawn by the +200V line into this HV Converter stage causes the TV to shut down. There is NO Standby light blink indication when this HV stage shuts down the TV. The +200 line feeds IC8002, the two converter transistors (not shown), and flyback transformer. Excessive HV will also cause the TV to shut down by drawing too much current through the flyback. In summary, shutdown without a Standby light indication indicates a problem in this HV stage.

Start Up
Three items are necessary to start this HV power supply:

HV Converter Inputs (Starting) Name 1. +200V 2. +15V 3. AFCPLS From D6515 & D6517 / cathode(D Bd) D6514 / cathode (D Bd) H Out Q5030/C (D Bd) (CN5501/pin 3 = 9Vp-p Destination IC8002/18 (199V) IC8002/8 (14.7V) IC8002/1 (1.6V)

The Start sequence is as follows: 1. The Primary power supply produces low voltages for the Horizontal stage (D board). 2. The Secondary power supply produces +135V for the Horizontal stage, along with +200V and +15V for this HV Converter stage. 3. The Horizontal Output stage is needed to develop AFC-PLS pulses (CN5501/pin 3 = 9Vp-p) for the HV Converter. 4. AFC-PLS pulses turn ON Q8001 and turn OFF Q8002. 5. IC8002/pin 1 rises. (1.3Vdc is the minimum to start IC8002). 6. IC8002s oscillator starts and drives the flyback transformer. 7. The voltage at IC8002/pin 2 decreases from 4V to 2Vdc as the HV climbs to 31.5kV. 8. Regulated HV and focus voltage output the Flyback transformer.

HV Adjustment
The adjustment procedure for these three controls is straightforward. First the shutdown controls are preset (ineffective). Then the RV8002 HV control is set to the shutdown trip point. The two shutdown controls are reset. Finally the HV control is set. A HV probe connected to a DVM is required for this adjustment procedure.

+200V (FROM SECONDARY POWER SUPPLY) AFC PLS (Q5030/C H OUT) START HV CONV.

Q8009 OCP

D8003

SHUTDOWN LATCH Q6530,Q6532 D BD.

R8053R8055 ON + OFF Q8002 R8056 OFF Q8004 OFF Q8003

V SENSE
1

Q8001

VD IC8002 HV DRIVER MCZ3001D


8

18

CONVERTER TRANSISTORS FLYBACK


2

HV TO PICTURE TUBE FOCUS VOLTAGE (PICTURE TUBE)

C8004 100

VC1

F/B

+15V (SEC P.S.) RV8002 HV

IC8003, IC8004 PH8001 ERROR DET

Q8022-3, Q8018 DYNAMIC FOCUS AMP D8025 33V

D8020
1

+ IC8001 OP AMPS NJM2901M

7 6

+ D8004 5.1V C8005 47 Q8010

DF DRIVE DQP CONTROL IC5511/11

4 5

R8078 R8042 RV8001 (COARSE)

D8014

RV8003 (FINE)

H.V. CONVERTER BLOCK

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45
The procedure is as follows: 1. 2. 3. 4. 5. 6. Replace RV8001, RV8002, and RV8003 (they are epoxyed). Turn RV8001 and RV8003 both CCW from the top of the D board. Turn the set ON with a black screen (HV unloaded). Adjust HV RV8002 for 35.5kV (shutdown threshold). Adjust RV8001 and RV8003 until the set just shuts down. Turn HV RV8002 CW to turn the set ON. Input a white signal. Bring the HV up to 35kV to make sure the set does not shut down. (This rechecks the RV8001 and RV8003 adjustments.) 7. Adjust HV RV8002 for 31.5kV. 8. Guard against premature shutdown by following bulletin 492 (appendix).
Pin Volts Pin Volts 1 1.63 10 10.3 0 2 1.75 11 Converter IC8002 Voltages 3 2.25 12 4.14 4 2.47 13 0 0 14 108 5 0 15 98.6 6 7 4.56 16 103 0 8 14.7 17 0 18 200 9

Additional Important Voltages related to IC8002/pin 1 Voltage Electrical Location IC8001/pin 1 IC8001/pin 2 C8004/ + lead Physical Location Voltage 14 pin Surface mounted IC under 0V RV8001/RV8003 0V Behind IC5515 s large heat sink 0.02V next to large 820uf, 250V C8023.

Testing
1. HV Check - Measuring the voltage at D8025/Cathode verifies HV. Normally D8025/Cathode = 31.6Vdc when there is HV, and 0V when HV is missing. D8025s Anode voltage should not be higher than 0.6Vdc in normal operation (measured). D8025 is located next to the potted (epoxy sealed) RV8001/RV8003 controls at the left edge of the D board.

D Bd

A Bd

3. HV may be starting, then shutting down - Monitor D8025/Cathode for 3.16V at start up. If it is 0V, there is no HV. Check the converter transistors and suspect IC8002 and the flyback to cause OCP shutdown (via Q8009). If the cathold voltage momentarily rises to beyond 31Vdc, there is HV but it may be excessive. Turn the RV8001 and RV8003 controls CCW and adjust the HV. Follow the HV adjustment procedure. If shutdown still occurs suspect D8025, C8005, and D8004.

D8025 Flyback KV32XBR400 rear

2. HV Converter Check - If no HV is output, look for +200V input at IC8002/pin 18 and more than 15.6V at IC8002/pin 8. Look for HV Conv start voltage at IC8002/pin 1 (normally 1.6Vdc but must be more than 1.3Vdc. to start).

+200V (FROM SECONDARY POWER SUPPLY) AFC PLS (Q5030/C H OUT) START HV CONV.

Q8009 OCP

D8003

SHUTDOWN LATCH Q6530,Q6532 D BD.

R8053R8055 ON + OFF Q8002 R8056 OFF Q8004 OFF Q8003

V SENSE
1

Q8001

VD IC8002 HV DRIVER MCZ3001D


8

18

CONVERTER TRANSISTORS FLYBACK


2

HV TO PICTURE TUBE FOCUS VOLTAGE (PICTURE TUBE)

C8004 100

VC1

F/B

+15V (SEC P.S.) RV8002 HV

IC8003, IC8004 PH8001 ERROR DET

Q8022-3, Q8018 DYNAMIC FOCUS AMP D8025 33V

D8020
1

+ IC8001 OP AMPS NJM2901M

7 6

+ D8004 5.1V C8005 47 Q8010

DF DRIVE DQP CONTROL IC5511/11

4 5

R8078 R8042 RV8001 (COARSE)

D8014

RV8003 (FINE)

H.V. CONVERTER BLOCK

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47

Communications
There are three communications networks used in this DX-1A TV chassis. All three consist of only clock and data lines running on a parallel connection with multiple ICs. Communications Networks
Network 0 (clock 0, data 0 lines) 1 (clock 1, data 1 lines) 2 Location IC701/pin 29, 30 IC701/pin 28, 31 B Bd. IC3090 to IC3089 & IC3408 Purpose Dedicated communications to the two NVM on the A & D boards (IC707 & IC5501. Main IIC bus to provide direction to most ICs on the A, B, & D boards Multi Image Driver (MID) uCom CI3090 communications link with driver IC3408 and NVM (memory) IC3089.

nected to both memories in parallel. The first group of communications goes to IC707. IC5501 is hard wired differently at pins 2 and 3 to accept the second communications group from IC701.
ch1

ch2 T 1 ch3

3 C H 1 !5 .0 0 V = C H 2 !5 .0 0 V = STOP

C H 3 !5 .0 0 V = C H P M T B 5 .0 0 m s - 2 .5 8 d v c h 1 -

Communications Network 0 & 1


Main uCom IC701 generates the clock signal for communications network 0 and 1. Network 0 is used by IC701 to read and write data to NVM IC707 (A board) and IC5501 (D board). Network 1 is used to send data to most of the ICs in the TV set. At power ON, the user data in IC707 and deflection data in IC5501 is retrieved by IC701 using network 0 and passed to the appropriate ICs using network 1. Once the ICs on network 1 receive this data to set their operating parameters, the TV can function. The Y/C CRT Drive IC201 on the A board and MID uCom IC3090 on the B board can provide return (reply) data to IC701. This data either updates the on-screen display menu (OSD is in IC701) or initiates a safety shutdown of the TV. The data at both network 0 and network 1 is always present as long as the TV is ON. The first scope shot shows the network 0 data being read from NVM IC707 and IC5501. The clock and data lines from IC701 are con-

Memory Communications - TV Channel 7 displayed Scope Channel 1 2 3 Name WP (read/write) Clock Data Location CN702/pin 8 CN703/pin 1 CN703/pin 2 Voltage 5Vdc 5Vp-p 5Vp-p

Time base = 5msec/div.

In this second scope shot, when the TILT rotation number is changed from the setup menu, the WP pulse (ch 1) goes LOW when the network 0 is communicating with IC707. This allows IC701 to write the new rotation number into NVM IC707.

STBY+5V
16 62 50

R834 Q717 RESET


8 1

A BD.

IC701 MAIN uCOM DAT 1


31 28

47 29

WP CLK 0 DAT 0

7 6 5

IC707 NVM

2 3 4

D BD.

CLK 1

30

CN702/ CN6504 WP CLK DATA

8 2 1

7 5 6 8

R829 STBY+5V R827 STBY+5V IIC BUS MAIN TUNER SUB TUNER IC201Y/C CRT DRIVE

IC5501 NVM

2 3 4

STBY+5V

CN703/ CN6506
5

IC7001 AUDIO PROC. DATA


8 7

IC5511 DQP CONT. IC5513 DY-CONV.

DAT.
1 2 A29 A30

CLK

CLK

CN706/ CN5501

CN7001/ CN4104 IC4103 AUDIO D/A S BD.

CN203/ CN3203 IC3001 COMP. I/F IC3090 MID uCOM IC3201 A/V SW. IC3408 MID-XA B BD. IC3202 AUDIO SW. IC3110 Y CT SUB IC3601 SUB CCD V CHIP IC3602 MAIN CCD V CHIP
9 10

BC BD. IC3501 3D COMB

IC3408 Y CT MAIN

IC3089 NVM

CN3201/ CN3500

COMMUNICATIONS BLOCK

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49
PM3394, FL UK E & PHILIPS c h1

Network 1 Communications - TV Channel 7 displayed Scope Channel Name Clock Data Location CN706/pin 7 CN706/pin 8 Voltage 5Vp-p 5Vp-p
T 1

c h2

1 2

c h3

Time base = 5msec/div.

Communications Network 2
3 CH1!5.00 V= CH2!5.00 V= CH3!5.00 V= CHP MTB5.00m s- 2.58d v c h 1-

Communications network 2 is only used between three ICs on the B board. MID uCom IC3090 communicates with MID IC3408 to retrieve processed data such as the input horizontal frequency and uses it to select video signal paths.

Memory Communications during picture Tilt Scope Channel 1 2 3 Name WP (read/write) Clock Data Location CN702/pin 8 CN703/pin 1 CN703/pin 2 Voltage 5Vp-p 5Vp-p 5Vp-p

MID uCom IC3090 also communicates with memory IC3089 and IC3408 to set up the twin picture (picture with picture) parameters. This data in memory IC3089 is accessed in the service mode using MID uCom IC3090 to interface to IC701. MID uCom IC3090 is connected to communications network 1 and 2.

Time base = 5msec/div.


Although not shown, network 0 data and clock are accessible at the 10pin rear panel service connector. Network 1 communications is also always present when the TV is ON. A scope shot of the two 5Vp-p signals is shown:

ch 1

ch 2 T 2 C 15 0V S O H .0 ~ T P C 25 0V M B .0 m 1 2 vHxx H .0 = T 5 0 s- .3 d

STBY+5V
16 62 50

R834 Q717 RESET


8 1

A BD.

IC701 MAIN uCOM DAT 1


31 28

47 29

WP CLK 0 DAT 0

7 6 5

IC707 NVM

2 3 4

D BD.

CLK 1

30

CN702/ CN6504 WP CLK DATA

8 2 1

7 5 6 8

R829 STBY+5V R827 STBY+5V IIC BUS MAIN TUNER SUB TUNER IC201Y/C CRT DRIVE

IC5501 NVM

2 3 4

STBY+5V

CN703/ CN6506
5

IC7001 AUDIO PROC. DATA


8 7

IC5511 DQP CONT. IC5513 DY-CONV.

DAT.
1 2 A29 A30

CLK

CLK

CN706/ CN5501

CN7001/ CN4104 IC4103 AUDIO D/A S BD.

CN203/ CN3203 IC3001 COMP. I/F IC3090 MID uCOM IC3201 A/V SW. IC3408 MID-XA B BD. IC3202 AUDIO SW. IC3110 Y CT SUB IC3601 SUB CCD V CHIP IC3602 MAIN CCD V CHIP
9 10

BC BD. IC3501 3D COMB

IC3408 Y CT MAIN

IC3089 NVM

CN3201/ CN3500

COMMUNICATIONS BLOCK

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50

51

Dynamic Focus Block


Static Focus Concept
An electron beam within the picture tube consists of many electrons that are slowed down by the focus electrode. After passing through the focus electrode, the accelerating electrode brings the beam to a fine point on the screen. This focus point is positioned by adjusting the voltage at the focus electrode relative to the accelerating voltage. The accelerating voltage is usually fixed at the HV potential from the flyback secondary.
CRT Electrodes: Focus Accelerating

This means the focus point must be moved up at the left and right sides to meet the flat picture tube screen.

Dynamic Focus Concept


The job of the dynamic focus circuit is to change the focus points to meet the flat picture tube screen. This is done by either increasing the static focus voltage when the beam is at the left and right sides of the screen or decreasing the static focus voltage when the beam is at the middle of the screen. Either method accomplishes the same effect. This dynamic focus correction voltage is shaped like a parabola to match the focus arc.
H D ynam ic focus voltage

Electron beam

Focus point

left

right

N o correction
HV to CRT

As the electron beam is moved from side to side (swept) by the magnetic field created by the external horizontal deflection yoke, the focus points form an arc as shown by the arrowheads. Early picture tube glass screens were made into a similar arc to maintain focus at the left and right sides of the screen.
Focus Arc Yoke Right side Flat CRT screen Left side Picture Tube - Top View

DF Transformer

Flyback

Focus V to CRT

Circuitry
The Dynamic focus circuitry is divided into two parts: Modulated power supply Both signals are fed to DFT T8002 to make the dynamic focus voltage. In the scope shot, the top waveform is the DF Drive and the second is the modulated power supply. The third waveform is the flyback signal that marks the left and right sides of the screen.
PM 3394, FLUKE & PHILIPS ch1 T ch3 1 ch4

DF Drive

Electron beam

CH 100 V~ 1! 4 CH3!50.0 V~

STOP ch1+

CH 4!10.0 V ALT M = TB5.00us

TV SCREEN

T8001 FLYBACK D BD. HV CONV


17

CRT HV CRT FOCUS VOLTAGE

IC5502 OP AMP 2/2 DF FOCUS CORRECTION C5509 AFC-PLS H OUT Q5030/C


19 2 11

13

Q5508, Q5509 DRIVERS

R8082 Q5501 Q8022, Q8023 DRIVERS C8058 Q8018 DF OUTPUT N L8005 D8017 Q8015 SW R8101 Q8016 SW +135V
6

T8002 DFT

3 1

DATA

CLK IIC BUS

IC5511 DAC1 DQP 11 5 CONTROL CXA202GAS


14 21

IC5502 OP AMP 1/2

91VDC P C8060 4.7 160V

SWO

C8051 10

Q8019, Q8020 DF PROT

VTIM CN5503/2 Y/C CRT DRIVE IC201/54

R8102 22k IC5502 = NJM2901M

SM CATEGORY 2026AS DF ON - 0=ON, 1=OFF DF - CHANGES FOCUS START


15DTV 1268 10/10/00

DYNAMIC FOCUS

52

53
Dynamic Focus Signals Channel 1 2 3 Name DF Drive signal Modulated power supply AFC-PLS (H fly pulses) Location T8002//pin 3 T8002//pin 1 IC5511/pin 19 Voltage 400Vp-p 140Vp-p 10Vp-p Channel 1 2 3 4 Name AFC-PLS Dynamic Drive Delayed DF Drive Final DF Drive Signal DF Drive Signals Location IC5511/pin 19 IC5511/pin 11 Q8018/Base Q8018/Collector Voltage 10Vp-p 0.3Vp-p 10Vp-p 400Vp-p

Time base = 5usec/div


By examining the channel 2 and 3 waveforms, the modulated power supply (ch 2) is turned off before and after the H sync pulse (ch 3). This means there is no dynamic focus correction to the left nor right sides of the screen. However focus correction is applied to the center of the picture as seen by the increasing voltage at the DF drive signal (ch1). The focus correction at the center brings the focus point to the same level as the sides.

Time Base = 5usec/div.

Modulated power supply


The modulated power supply signal is also made in IC5511 from horizontal and vertical timing pulses input pins 19 and 21. IC5511s output signal is AC coupled to switches Q8015 and Q8016 and finally applied to T8002/ pin 1. The modulated power supply signal passes through T8002 to power DF Output transistor Q8018 with modulated dynamic focus voltage. In the scope shot of the DF power supply, the channel 2 waveform shows two switching voltages in between the H sync pulses (channel 1). The two positive switching voltages in channel 2 result in low going B+ parts of channel 4s waveform. The reduction of B+ corresponds to no focus correction at the left and right sides of the picture. However, dynamic focus correction does take place at the center of the picture when there is B+ output Q8016/Collector.
PM3394, FLUKE & PHILIPS ch1

DF Drive
The DF drive signal is manufactured in IC5511 from horizontal and vertical timing pulse input at pins 19 and 21. The drive signal is output pin 11 and delayed in a chain of amps (IC5502 and Q5501). Driver transistors Q5508-9 and Q8022-23 buffer the signal as it travels from one part of the D board toward the other near the FBT. The final DF Output transistor Q8018 applies the signal to T8002/pin 3. In the following waveforms you can see the low going drive signal from IC5511/pin 11 (ch 2) become inverted and delayed (ch 3). The final drive signal (ch 4) goes low to reduce the focus voltage at the right side of the picture.
ch1 T 1 ch2 2

T 1

ch2 2 ch3

ch4

ch3

ch4

3 CH1!10.0 V~ CH2! 200mV~ 4 CH3! 200mV~ AVG ch1+

CH4! 100 V= ALT MTB5.00us

CH1!10.0 V~ CH2! 200mV~ 4 CH3!10.0 V~ CH4! 100 V= ALT MTB5.00us ch1+

TV SCREEN

T8001 FLYBACK D BD. HV CONV


17

CRT HV CRT FOCUS VOLTAGE

IC5502 OP AMP 2/2 DF FOCUS CORRECTION C5509 AFC-PLS H OUT Q5030/C


19 2 11

13

Q5508, Q5509 DRIVERS

R8082 Q5501 Q8022, Q8023 DRIVERS C8058 Q8018 DF OUTPUT N L8005 D8017 Q8015 SW R8101 Q8016 SW +135V
6

T8002 DFT

3 1

DATA

CLK IIC BUS

IC5511 DAC1 DQP 11 5 CONTROL CXA202GAS


14 21

IC5502 OP AMP 1/2

91VDC P C8060 4.7 160V

SWO

C8051 10

Q8019, Q8020 DF PROT

VTIM CN5503/2 Y/C CRT DRIVE IC201/54

R8102 22k IC5502 = NJM2901M

SM CATEGORY 2026AS DF ON - 0=ON, 1=OFF DF - CHANGES FOCUS START


15DTV 1268 10/10/00

DYNAMIC FOCUS

54

55
DF Switching Signals Channel 1 2 3 4 Name AFC-PLS SWO (Switch control) Switch Drive signal Final DF Drive Signal Location IC5511/pin 19 IC5511/pin 14 Q8016/Base Q8016/Collector Voltage 10Vp-p 0.3Vp-p (main) 0.1Vp-p (main) 140Vp-p
DFON data = 0 (DF is On) 1 (DF is Off)

Service mode item DFON turns OFF the switching voltage from IC5511/ pin 14. This can be seen in the following chart that contains the DC voltages of the output stage.
DF Output Stage Voltages Q8018/C -14Vdc 0.3Vdc T8002/pin 3 89Vdc 0Vdc T8002/pin 1 91Vdc 0Vdc

The purpose of DF Protect transistors Q8019 and Q8020 in the switching path is unknown as of this writing.

Adjustment
The manual focus adjustment is located on the flyback (the only control). Input a crosshatch and adjust the focus control until you can see the scanning lines in the picture. Dynamic focus can be turned ON/OFF and phase adjusted (start location) in the service mode. Data group #7 with the heading 2026 contains two items related to dynamic focus:

Service Mode Category 2026 Item Name DFON DF Purpose Data 0 = dynamic focus ON Data 1 = dynamic focus OFF Positions IC5511/pin 14 switching pulses to change the start of the dynamic focus points on the screen.

TV SCREEN

T8001 FLYBACK D BD. HV CONV


17

CRT HV CRT FOCUS VOLTAGE

IC5502 OP AMP 2/2 DF FOCUS CORRECTION C5509 AFC-PLS H OUT Q5030/C


19 2 11

13

Q5508, Q5509 DRIVERS

R8082 Q5501 Q8022, Q8023 DRIVERS C8058 Q8018 DF OUTPUT N L8005 D8017 Q8015 SW R8101 Q8016 SW +135V
6

T8002 DFT

3 1

DATA

CLK IIC BUS

IC5511 DAC1 DQP 11 5 CONTROL CXA202GAS


14 21

IC5502 OP AMP 1/2

91VDC P C8060 4.7 160V

SWO

C8051 10

Q8019, Q8020 DF PROT

VTIM CN5503/2 Y/C CRT DRIVE IC201/54

R8102 22k IC5502 = NJM2901M

SM CATEGORY 2026AS DF ON - 0=ON, 1=OFF DF - CHANGES FOCUS START


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DYNAMIC FOCUS

56

57

DQP Circuit Corner Focus Correction


Channel Name

DQP-- Signal Processing Location IC5511/pin 4 CN5509/pin 6 Voltage 0.4Vp-p 130Vp-p 1 2 DQP negative signal Amplified DQP- signal

Focus at the sides of a Wega flat screen picture tube was accomplished with the Dynamic Focus Circuitry. Focus at the corners is corrected using a Dynamic Quadrapole circuit. Although they are independent circuits, a failure in one will make it appear as if the other is also defective. Therefore, both the Dynamic Focus and DPQ circuits must be tested when there is poor focus on a portion of the screen. The DQP circuit is also used to correct for mis-convergence at the perimeter.

Time base = 10usec/div

The waveforms in the following scope shot are made by IC5511/pin 6 and applied to the QP coils at CN5509/pin 4.
c h1

Circuitry
IC5511 manufactures the corner focus correction signal that is amplified and applied to four coils placed at the neck of the CRT. There are two signals marked Para 1 and Para 2 that output IC5511/pins 4 and 6. They are amplified and applied to the four QP coils. At power ON, Q5008 and Q5505 use C5027 to momentary disable the DQP amplification in IC5504. This is so the beam will be unaffected by incorrect voltages at start up.

c h2

T 2

Q5502, Q5507 and IC5502 monitor the horizontal width (AFC-PLS from Q5030) and corrects for focus if the width changes momentarily. This is accomplished by changing the DC input voltage of IC5504/pin 2 proportional to the width of the picture. The waveforms in the following scope shot are made by IC5511/pin 4 and applied to the QP coils at CN5509/pin 6.
P 33 4 F KE& P ILIP M 9 , LU H S

C H 1 ! 20 0 m V~ CH 2 ! 10 0 V= M T B1 0 .0 us H xx

DQP-- Signal Processing Channel 1 2 Name DQP positive signal Amplified DQP + signal Location IC5511/pin 6 CN5509/pin 4 Voltage 0.4Vp-p 300Vp-p

ch1

ch2

Time base = 10usec/div


T 2

By comparing both output waveforms, we can see the resultant DQP correction signal (difference of the two waveforms) is not that complex.

C 1! 2 0 V H 0m ~ C 2 1 0V H! 0 = M B10 us T .0 Hxx

AFC-PLS Q5030/C VTIM CN5503/2 IC201/54

19 21

PARA 1 4 R5577 180k IC5511 DQP CONTROLLER CXA2026A

IC5506 DQP-AMP1 LA6500

R5588
4

L5505
6

QP-

C5548 0.47

MAIN +12V

R5056 C5027

POWER ON INHIBIT Q5008 Q5505

3.5 OHMS

IIC BUS FROM IC701/28,31

1 2

SDA SCL PARA 2 6 PWM


9 2 1

R5554 18k R5564 R5563 IC5502 AMP Q5502 Q5507

IC5504 DQP-AMP2 LA6500

L5504
4 4

CN5509 D5514 C5531 0.1

QP+

R5696

D5515 C5533

C5614 HORIZ. AFC-PLS Q5030/C

ADJUSTMENT SERVICE MODE: CATEGORY 2026AS DQP FOCUS CORRECTION ITEM 1 - DQP - PWM LEVEL ITEM 3 - DQPD - DC LEVEL ITEM 4 - QPDV - VERT. MOD ITEM 5 - DVS - TILT ITEM 7 - DQPA - AMPLITUDE

DQP FOCUS CORRECTION 58

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PM3394, FLUKE & PHILIPS ch1

ch2

T 2

CH1!50.0 V~ CH2! 100 V= MTB10.0us- 1.18dv L xx

DQP-- Signal Processing Channel 1 2 Name Amplified DQP - signal Amplified DQP + signal Location CN5509/pin 6 CN5509/pin 4 Voltage 130Vp-p 300Vp-p

Time base = 10usec/div

Adjustment
The waveforms from IC5511 can be changed from the service mode to affect the starting point of focus correction on the screen, the amount of focus, and convergence. These items are found in the service mode category 2026AS.

AFC-PLS Q5030/C VTIM CN5503/2 IC201/54

19 21

PARA 1 4 R5577 180k IC5511 DQP CONTROLLER CXA2026A

IC5506 DQP-AMP1 LA6500

R5588
4

L5505
6

QP-

C5548 0.47

MAIN +12V

R5056 C5027

POWER ON INHIBIT Q5008 Q5505

3.5 OHMS

IIC BUS FROM IC701/28,31

1 2

SDA SCL PARA 2 6 PWM


9 2 1

R5554 18k R5564 R5563 IC5502 AMP Q5502 Q5507

IC5504 DQP-AMP2 LA6500

L5504
4 4

CN5509 D5514 C5531 0.1

QP+

R5696

D5515 C5533

C5614 HORIZ. AFC-PLS Q5030/C

ADJUSTMENT SERVICE MODE: CATEGORY 2026AS DQP FOCUS CORRECTION ITEM 1 - DQP - PWM LEVEL ITEM 3 - DQPD - DC LEVEL ITEM 4 - QPDV - VERT. MOD ITEM 5 - DVS - TILT ITEM 7 - DQPA - AMPLITUDE

DQP FOCUS CORRECTION 60

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Convergence Circuit
1T

Concept
The purpose of the convergence circuit is to create a dynamic signal that is applied to the convergence (CY) winding within the main yoke. The convergence winding is positioned so the dynamic signal will move one or two electron beams more than the third. This is how an electronic signal can unite all three beams together on the screen. The convergence circuitry corrects at the four sides and right corners of the TV screen in this TV.
Correction areas Correction areas TV screen Convergence correction areas

CH1!1.00 V~ CH2!5.00 V~

STOP ENV MTB5.00ms ch1+

Convergence Output Channel 1. 2. Name VTIM (Vertical timing) input Convergence Output Location IC5513/pin 3 CN5510/pin 3 Voltage 1.8Vp-p 10Vp-p

Circuitry

At power ON, convergence data stored in the Non-Volatile Memory IC707 is retrieved by Main uCom IC701 (not shown) and sent to IC5513 via the I2C bus. Within ICI5513, this data shapes the vertical and horizontal signal input to pins 3 and 14 and produces two outputs. The H Stat output at IC5513/pin 8 corrects for left and right mis-convergence. The V Stat output at IC5513/pin 9 corrects for top and bottom misconvergence. The two signals are combined externally and amplified by IC5515 into a 10Vp-p waveform at the convergence yoke CN5510/pin 3. IC5513s input and output signals are listed in the chart:
IC5513 s Input / Output Signals Name VTIM AFC-PLS Ref H Stat V Stat IC5513/pin 3 14 5 8 9 Voltage 1.8Vp-p, 4.8Vdc 10Vp-p, 0.74Vdc 5Vdc 100 mV p-p 200 mV p-p Purpose Input Vert sawtooth ramp Input horiz pulse reference for IC5515 left/right conv. signal top/bottom conv. signal

Time Base = 5msec/div

Adjustment
The convergence yoke signal is adjusted in the service mode. Data group #6 with the heading D-Conv has nine adjustment parameters that correct for mis-convergence, mostly at the right side of the TV screen.

VTIM IC201/54 AFC-PLS Q5030/C

D BD.
3 14

IC5515 STK390-910 IC5513 DY-CONV CXA8070AP


5 8 9

5V REF. R5693 H STAT R5699 V STAT

+
3 3 1 8 4

CY PART OF MAIN YOKE

DATA CLOCK IIC BUS

16 17

CN5510 R5711 R5648

10

R5712 MAIN +12V SOURCE

+15V

-15V

+15V

IC5003 12V REG SERVICE MODE CATEGORY D - CONV 9 ADJUSTMENT ITEMS

CONVERGENCE CIRCUIT

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63

Picture Tilt Correction


When flat screen picture tubes were first manufactured, lines that were not straight were very noticeable. This meant additional pincushion and convergence circuitry was required to improve the picture quality. If the yoke were a little off center, the slight tilt of the picture would also be noticeable. A picture tilt circuit was added to Sony flat screen Wega TVs to correct for this tilt. The user can perform Tilt Correction from the setup menu. The coarse adjustment is performed in the service mode by changing the data in category 2150D, item 6 (NSCO). The circuit required a DC voltage to be applied to a N/S coil suspended about the perimeter of the yoke housing at the bell of the tube. Applying a voltage to this N/S coil produces a magnetic field. The field offsets the three beams as they emerged from the electron gun structure, rotating the picture. A sawtooth waveform is also added to this DC voltage for horizontal trapezoid correction. Therefore, there is a DC voltage and a sawtooth signal present at the coil. Both the DC level and sawtooth amplitude can be controlled in the service mode.

Horizontal Trapezoid Correction Circuit


The trapezoid correction signal takes the same path the tilt correction DC voltage did. This signal comes from IC201/pin 51 as a 60 Hz 0.3Vp-p sawtooth waveform. IC5510 brings the signal level up to 2Vp-p for the main sawtooth plus 4Vp-p for the low going spike.
ch1

ch2

1 2

CH1 2.00 V= CH2 2.00 V= MTB5.00ms- 1.32dv H xx

Horizontal Trapezoid Correction Waveform Channel 1 2 Name V Saw 1 N/S Coil Location CN201/pin 5 CN5509/pin 12 Voltage 0.3Vp-p 6Vp-p

Tilt Correction Circuit


The tilt correction DC voltage and the horizontal trapezoid correction sawtooth signal are created by IC201. The signal and DC voltage leave IC201/pin 51 and are amplified by IC5510 before being sent to the N/S coil. The voltages in normal operation and when the user has set the tilt to both extremes (+7) are shown in the chart.
Tilt correction Voltages Location CN201/pin 5 CN9102/pin 12 Name Output of IC201 N/S coil 0 rotation 4Vdc 0V -7 rotation 5Vdc -4.8Vdc +7 rotation 3Vdc 5Vdc

Time base = 5msec/div.

Adjustment
Tilt - The DC voltage from IC201/pin 51 can be adjusted in the service mode, as well as from the users setup menu. Access the coarse adjustment by locating category 2150D-1 in the service mode. Scroll down to item number 6 - NSCO to change the tilt from the service mode. H Trapezoid - The sawtooth amplitude from IC201/pin 51 can also be controlled from the service mode, independent of the DC voltage. In the same category as for tilt (2150D-1), scroll down to item 7 - HTPZ. Changing its data changes the signal amplitude and corrects for trapezoid distortion.

N/S COIL R5670 A BD R5669


5

MAIN +12V

PICTURE TUBE REAR

IC201 Y/C CRT DRIVE CXA2150Q 51


25 26

V SAW 1
5

R5678
2

+ -

LA6500
4

CN5509/ CN9102
12

0V
3

YOKE

CN201/ CN5503 4V

IIC BUS DATA


31 28

0.25V R5679 W BD. C5601 R5613 270


11

N/S COIL 38.2 OHMS

CLK1 -12V R5688 R5705 1

CLK O 29 IC701 IC707 MAIN uCOM NVM M306V2- 30 N24C8 DX1A DATA O

D BD.

ADJUSTMENTS SET UP MENU - TILT CORRECTION USER: SERVICE MODE: CATEGORY 2150D-1 ITEM 6 - NSCO - 0-15 ITEM 7 - HTPZ - HORIZ. TRAPEZOID

PICTURE TILT CORRECTION

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65

Vertical Pincushion Correction Circuit


Channel

Vertical Pincushion Correction Signal Name VSAWO Pincushion Output Location CN201/pin 6 CN5509/pin 2 Voltage 0.3Vp-p 0.5Vp-p = main waveform 3.5Vp-p including spike 1 2

Concept
The geometry on a flat screen picture tube is more critical than that on a curved picture tube. This new circuit applies an electronic signal to a coil at the CRT electron gun to straighten the top and bottom lines on a picture.
Straighten top & bottom lines using VPIN adjustment

Time base = 5msec/div.

The Vertical Pincushion coil resistance is 18.9 ohms between CN9102/ pins 1 and 2 without the plug connected.

Adjustment
The vertical pincushion signal is adjusted in the service mode with the aid of an external cross hatch generator. Data group #4 with the heading 2150D-1 contains the VPIN adjustment in its fifth item. The fourth item VCEN also changes the DC level of the VPIN signal. VPIN must be adjusted in all three deflection modes: 1. Full - (normal NTSC) 4:3 signal input. 2. V Comp1 - (480p) 16:9 video 5 or 6 input. 3. V Comp2 - (1080i) 16:9 video 5 or 6 input.

Circuitry
At power ON, data stored in the Non-Volatile Memory (NVM) IC707 is retrieved by Main uCom IC701. IC701 distributes the data to various ICs in the TV via the I2C bus. The Y/C CRT Drive IC201 is sent just the data that pertains to it. Within IC201, a correction signal is made consisting of mixed horizontal and vertical components. This signal is amplified by IC5514 and applied to the pincushion coil. The correction signals before and after amplifier IC5514 is shown in this scope shot.
PM3394, FLUKE & PHILIPS ch1

ch2 1

CH1! 200m V~ CH2!1.00 V~

STOP MTB5.00ms L=2 ch1p

R5698 A BD. R5697


5

MAIN 9V IC5514 V PIN OUT LA6500 CN5509/ CN9102


4 2

IC201 Y/C CRT DRIVE CXA2150Q 50


25 26

V SAW O
6

R5700
2

+ 3

V PIN +

0V

CN201/ CN5503

0.25V 4V R5615

IIC BUS DATA


31 28

W BD. C5616 R5710 270


1

CRT

CLK1 CLK O IC707 NVM N24C8 DATA O D BD. -12V SLIGHT BOW INWARDS

29 IC701 MAIN uCOM M306V2- 30 DX1A

V PIN R5704 1

TV SCREEN

NO CORRECTION

SM CATEGORY 2150D-1 5 ITEMS ADJ. IN ALL 3 MODES: 1. FULL (NORMAL) 2. V COMP1 - 480P 16:9 3. V COMP2 - 1080I/VERT ENHANCED

VERTICAL PINCUSHION CORRECTION CIRCUIT

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67

Vertical Process
The vertical sync source selection on the B board is new, but the oscillator and output stage is traditional.

The waveforms of this stage show the basic operation from sync input (ch1) through drive (ch 2) to feedback (ch 3 & 4).
c h 3 : d c = 2 6 .2 m V ch1 ch4 : dc = 16 3m V T ch2

Vertical Sync
The vertical frequency is 60Hz but the sync is selected by IC4313 from one of three sources: 1. MID circuit when Progressive scan is selected by the user (IC4313/ pin 13 input). 2. Main video input from input switch IC3048 when interlace scan is selected (IC4313/pin 1 input). 3. Sub video input from sub picture switch IC3001 when this picture is the only one selected (from the Twin mode). (IC4313/pin 2 input) Switch IC4313 selects one input that outputs pin 14. The selection is based upon control voltages from MID uCom IC3090 and the Main uCom IC701 input IC4313/pin 9-11.
ch3

ch4 2

C H 1 !2 .0 0 V = C H 2 !2 .0 0 V = 4 C H 3 !1 .0 0 V ~ C H 4 !2 .0 0 V = C H P M T B 5 .0 0 m s ch1 -

Vertical Stage Waveforms Channel 1 2 3 4 Name Mid VS (sync) V Drive + Protect signal Timing Location CN003/pin B15 CN5503/pin 4 CN5505/pin 7 CN5501/pin 1 Voltage 3Vp-p 1.8Vp-p 1Vp-p 0.8Vdc 3.5Vp-p Time base =5msec/div.

Vertical Oscillator
The vertical oscillator inside IC201 starts and outputs pins 52 and 53 when Main 9V is applied to IC201/pins 55 and 61. Data need not be present for vertical drive to output like other Y/C Jungle ICs.

Vertical Output
The vertical stage is traditional. The vertical oscillator signal is amplified in IC5004 and used to drive the vertical deflection yoke. To make sure the vertical stage is operational, a sample of the vertical signal is returned to IC201/pin 35. If IC201 detects a loss of vertical pulses, it blanks the picture. If the loss remains for two seconds, IC201 sends data to Main uCom IC701 to shut down the set and store the vertical failure code. Vertical pulses from IC5004/pin 3 are sent to the MID uCom IC3090/pin 35 to identify the end of the scan for interlace/progressive scan timing.

Vertical Compression / 16:9 Enhancement


When a 16:9 video signal is input from video 5 or 6, the aspect ratio is incorrect for this 4:3 TV screen and the picture will appear too tall. The vertical is compressed slightly to maintain the correct aspect ratio. The user chooses this compression from the menu. In the setup menu under 16:9 enhancement, he can choose AUTO or ON. In AUTO, the MID circuit on the D board detects the higher horizontal frequency associated with a 1080i 16:9 picture and reduces the vertical sweep. A 480p signal can be in either aspect ratio. Therefore the user must manually select ON for the vertical compression.

V SYNC PROGRESSIVE V SYNC FROM IC3408 VTIM (INTERLACE) FROM IC3048/15 YCT MAIN SEL V OUT(SUB PIX) FROM IC3001/23 COMP J-F SYNC SEL IC3090/10 MID uCOM TH CONT/X SW IC701/52(A BD.) Y/C CRT DRIVE

13

IC3413 SYNC SW SN74LV 4053A


14

V SYNC FOR OSD MAIN uCOM IC701/97 A BD. CN3205/ CN003


C15 B15 42 55 61

MAIN 9V

10 9 11

MID VS B BD.
4 53 52

IC201 Y/C CRT DRIVE CXA2150Q + V DRV PROT


35 3

D BD. CN201/ CN5503 R5029

VFB TO MID uCOM IC3090/35 (B BD.) FOR PROG./ INTER TIMING CN706/ CN5501
1

CN203/ CN5505

4Vp-p
7 1

TH5001

R5046 1.8

R5052 1.5

R5599 10k
6

V PROT YDY

1Vp-p TIMING +15V

-15V (D BD.)

IC5004 V OUT STR9379


1 6 3

CN5002
5

L5001

+15V (D BD.)

D5002

N R5023 D5001 5.1V Q5005 R5018

VERTICAL PROCESS

13DTV02 1269

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69
To keep the information in the vertical blanking area hidden in the vertical area above the picture, the vertical drive waveform from IC201 is altered. After the electron beam retraces to the top of the screen, normal downward scan begins. After the blanking interval, the beam drops down the screen before resuming sweep. The vertical ramps amplitude is also reduced. This can be seen when comparing the normal and compressed vertical waveform. Notice there is an irregularity at the beginning of the vertical ramp in the compressed vertical mode.
PM3394, FLUKE & PHILIPS ch2: pkpk= 1.78 V ch1 ch2: freq= 122 Hz T ch2 1

P M 3 3 9 4 , F L U K E & P H IL IP S c h 2 : p k p k = 1 .5 5 V ch1 c h 2 : fre q = 6 0 .0 H z T ch2 1

Ramp Irregularity
C H 1 !2 .0 0 V = C H 2! 500m V~ M T B 2 .0 0 m s - 0 .9 0 d v c h 1 +

Normal vertical ramp

Vertical Drive Signal - Reduced (16:9 Mode) Channel 1 Name MID VS (sync) V Drive (osc) Location CN3205/pin C15 CN5503/pin 4 Voltage 3.5Vp-p 1.3Vp-p

CH1!2.00 V= CH2! 500mV~ MTB2.00ms- 0.90dv ch1+

Vertical Drive Signal - Normal Channel 1 2 Name MID VS (sync) V Drive (osc) Location CN3205/pin C15 CN5503/pin 4 Voltage 3.5Vp-p 1.5Vp-p

Time base = 2msec/div.

Time base = 2msec/div.

V SYNC PROGRESSIVE V SYNC FROM IC3408 VTIM (INTERLACE) FROM IC3048/15 YCT MAIN SEL V OUT(SUB PIX) FROM IC3001/23 COMP J-F SYNC SEL IC3090/10 MID uCOM TH CONT/X SW IC701/52(A BD.) Y/C CRT DRIVE

13

IC3413 SYNC SW SN74LV 4053A


14

V SYNC FOR OSD MAIN uCOM IC701/97 A BD. CN3205/ CN003


C15 B15 42 55 61

MAIN 9V

10 9 11

MID VS B BD.
4 53 52

IC201 Y/C CRT DRIVE CXA2150Q + V DRV PROT


35 3

D BD. CN201/ CN5503 R5029

VFB TO MID uCOM IC3090/35 (B BD.) FOR PROG./ INTER TIMING CN706/ CN5501
1

CN203/ CN5505

4Vp-p
7 1

TH5001

R5046 1.8

R5052 1.5

R5599 10k
6

V PROT YDY

1Vp-p TIMING +15V

-15V (D BD.)

IC5004 V OUT STR9379


1 6 3

CN5002
5

L5001

+15V (D BD.)

D5002

N R5023 D5001 5.1V Q5005 R5018

VERTICAL PROCESS

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71

Audio Block Diagram


Features
The XBR400 audio section features: XBR400 Series Audio Section Features (Menu selection) Feature Steady Sound Description Reduces dynamic range to prevent drastic volume changes when switching channels or when a commercial comes on. Circuit location Audio Processor IC7001

The output of IC3201 is sent to IC3202. IC3202 is an analog switch that only handles audio. The input choices are:

Video 6 Selection of Main Vs Sub sound is used in the Twin mode. The outputs go to the rear monitor output jack and the S board for TruSurround Sound processing. S Board The L/R channel audio is applied to both TruSurround IC4101 and Switch IC4102. The TruSurround IC4101 outputs the L/R audio if the TruSurround mode is not selected. When TruSurround is selected, the second output from TruSurround IC4101 to D/A IC4103 is used. IC4103 converts the digital data to a control signal that instructs switch IC4102 to return L/R audio to a different part of IC4101 for TruSurround sound processing. The output of IC4101 is into the Audio Processor IC7001 on the A board. A Board

Main signal Sub signal Video 5

TruSurround Simulates a 3D sound using the Sound stereo signal and only the TV speakers Simulated Surround Separate Woofer and Tweeter 15Watts/ channel RMS Fixed or Variable audio Output Adds echo to a Mono signal to simulate a larger room. Tweeter is located at the bezel for better HF dispersion. IC packages. Power comes from fusible resistors on the D board. Output is present only when the speaker is switched OFF from the menu. The fixed or variable level can be chosen

IC4101, IC4103

Audio Processor IC7001

IC7002 & IC7005

IC7001

Signal Path
B Board IC3201 (CXA2069) is an analog switch that selects both audio and video. Using I2C data from the Main uCom IC701 (not shown), IC3201 can select between the following:

IC7001 handles the simulated and steady sound processing. It also adjusts the volume, treble, bass, and balance based upon the user commands. Its output is split into three paths. The speaker path is to a high and a low pass filter, then to the 15W power amplifiers IC7002 and IC7005. The third path is through buffer IC7007 to the TVs rear panel audio output jack. This path is muted (not shown) when the TV speaker is ON. If the user turns the speaker OFF from the menu, it is implied the user has an external amplifier or audio processor connected to the rear audio jack so this jack is unmuted (enabled). The user must then select a variable or fixed output level.

Main Tuner Sub Tuner Video 1 - 4

LINE OUT

W-L IC7007 BUFFER NJM4558 A BD. CN7008


7

SPEAKERS

MONITOR OUT INPUTS: MAIN SUB AUDIO 1 AUDIO 2 AUDIO 3 AUDIO 4 AUDIO 5 AUDIO 6 B BD. CN3205/CN003 U BD. THICKER LINES DENOTE L/R SIGNAL PAIR IC3203 BUFFER NJM4558

IC7002 POWER AMP TA8216 (HIGH PASS) IC7006 LOW PASS NJM4558 IC7001 AUDIO PROCESSOR BH3868
A14 A15 5 7 9 10 3

L H-L H-R R

IC3201 ANALOG SW (A/V) CXA2069

MAIN SUB MON IC3202 ANALOG SW AUDIO TEA6422

IC7005 POWER AMP TA8216 DATA/CLK IIC BUS CN7001 CN4101 S BD.

W-R

9 10

IC4101 TRUSURROUND NJM2180

IC4102 ANALOG SW NJU4066

IC4103 D/A CXA1315

IIC BUS

DX1A AUDIO BLOCK DIAGRAM

17DTV02 1270

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73

Self Diagnostic Block


The Self-Diagnostic circuit is a program of the Main uCom IC on the A board. This program monitors seven general faults that result in one or more of the following: TV shutdown (AC relay is turned off); TV Latched OFF** (AC relay is held off); or A dark picture (no RGB signal). As an indication of failure, the Main uCom blinks the Standby LED a number of times, pauses, then repeats.

OSD Diagnostics
In addition to the blinking Stby LED, the Main uCom records the number of times the failure occurred. This is useful when the user complains of an intermittent shutdown. Access the Diagnostic Mode To enter the test screen, first press these remote control buttons one at a time: Display, 5, Vol , Power On. The screen will list the circuit monitored and the number of times the failure has occurred. Clear the OSD Diagnostic numbers To clear the number of failures from the test screen press: Press 8, Enter.
Front of TV

Faults Monitored by Main uCom IC Stby LED Blinks 0X 2X 3X 3X 4X 5X Symptom Bd Monitored Circuit +200V OCP (HV) +135V OCP Unreg 7V OVP +135V OVP V Out Loss Test point (verification) Q8009/C CN6506/pin 8 D6017/C CN6506/pin 7 CN5505/pin 7 Normal Voltage 0.1Vdc 0V

Shutdown Shutdown Shutdown Shutdown Shutdown Blanking

D D A D D C/A /G2 adj A D

D6017 CN6506

0V 0.1V 0.78V
Q8009 10 FBT CN5505 8 IC6007

IK balance CN202/pin 8 3 pulses in vertical interval. Set 5V OCP H Out OCP IC6007/ Output CN5505/pin 8 5.0Vdc

6X 7X

Shutdown Shutdown

D Board

A Board
IC6007

0V

** TV latched OFF. Press power button twice to turn TV back on


I O G n/c

D BD.

UNREG. 3X 7V OVP

STANDBY LED

UNREG. 7V C BD. IC6007 5V REG. LOW B OCP 6X RGB TO CRT CN202/ CN9001
8

3X

+135V OVP D6018


7

D6017

SET 5V

2X

+135V OCP
8

0X Q8009 +200V OCP (HV)

0X POWER OFF LATCH D BOARD

CN6506/ CN703

IC701 MAIN uCOM

DATA/ CLK

IC201 Y/C CRT DRIVE

5X

IK SIGNAL WHITE BAL FAILURE V OUT LOSS H OUT OCP

4X
8

OSD RGB

CN203/ CN5505

7X

CN6504/ CN702 AC RELAY ON/OFF

D BD.

NUMBER OF TIMES THE STANDBY LIGHT BLINKS AFTER SHUTDOWN

SELF-DIAGNOSTIC BLOCK

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75

Self Diagnostic Circuit


When the TV shuts down and the standby LED blinks, the Main uCom IC701 knows which failure activated the shutdown. The number of times the Standby LED blinks indicates the problem board or section.

by monitoring CN6506/pin 8 as you power ON. If the voltage does not rise above 0v at power ON, the problem is not on the +135V line. If the voltage reaches 1.2V, disconnect the V board and try again. If the CN6506/ pin 8 voltage still rises to 1.2V, test the H Output and PWM transistors or replace the entire D board.

Shutdown - Standby light does not blink


Circuit - The current on the +200 volt line is monitored by R8043 and Q8009. This 200-volt line supplies the High Voltage Converter stage, which feeds the flyback. A short in the flyback or excessive high voltage will demand sufficient current to shut down the TV. Since there is no connection to the Main uCom IC701, the standby LED will not indicate this failure. Unstable standby voltage or a defect in the basic latch circuit (Q6530 and Q6532) will also cause the TV to shut down without the standby light blinking. This last problem is rare. Testing - To determine if the +200V line to the HV Converter stage is causing shutdown, monitor the voltage at Q8009/Collector at power ON. The voltage should not rise above 0.2Vdc at power ON. A higher voltage means the problem is on the D board in the Converter.

Shutdown - Standby light blinks three times


Circuit - There are two possible causes for this LED indication caused by excessive voltage. Two power supply voltages are monitored, +135V on the D board and Unreg. 7V on the A board. On the D board, the maximum voltage on the +135V line is +140V. This is monitored by IC6505 and Q6522. On the A board, the maximum voltage on the unregulated 7V line is 8.2V. This is monitored by D6014. Testing - The problem can be on either the A or the D board. Locate D6017/Cathode or D6014/Anode and monitor this voltage as you power the TV. If the voltage rises above 1V, the problem is in the A boards power supply (regulation). To test the power supply on the D board, monitor CN6506/pin 7. If this voltage rises above 0.6Vdc, the problem is on the D board.

Shutdown - Standby light blinks four times


Circuit - A vertical failure because of the output IC or power supply (both on the D board) will cause the Y/C, CRT Drive IC201 to send emergency data to Main uCom IC701. IC701 turns the TV by opening the AC relay (IC701/pin 69 goes LOW). Testing - Measure the +15v and -15V to the vertical output IC5004/pins 2 and 4 before you suspect the IC5004 itself.

Shutdown - Standby light blinks two times


There are two +135V OCP monitoring circuits. The first circuit will cause the Standby light to blink two times and the second will cause the light to blink seven times. Both sensing and output circuits are on the D board but the indicating circuit is on the A board. Circuit - R6598, R6591, Q6520, Q6521, and Q6524 monitor the current on the +135V line from the Secondary Power Supply. The +135 volt line supplies: Velocity modulation (V) board Horiz Output (Q5030) and PWM (Q5003) stage (D board) The HOT supplies +200V to the RGB Output ICs (C board). Testing - The blinking LED indicates the failure, but the problem could be in one of three locations: The H. Output/PWM stage, the sensing circuit on the D board, or the sensing circuit on this A board. Verify this problem

Blanking - Standby light blinks five times


Circuit - The Ik signals are measured by Y/C, CRT Drive IC201 and are used to adjust the RGB gain to maintain color balance. As the picture tube ages, the Ik signals may fall below the threshold for automatic balance and mute/blank the picture. Testing - Increase the G2 control on the CRTs C board. If that does not return cathode current to within operating range so the picture will appear, examine each filament to see if it is lit.

D BD. +135V (SEC P.S.) R6598 +135V SOURCE

A BD.

UNREG.7V R6015 1k UNREG.7V (PRI P.S.) D6014 7V R6019 D6017 4.7V


44

D6018 R6591 R6593 Q6520, Q6521 OCP STBY 5V Q6524 P R6612 R6602 IC701 MAIN uCOM CN6506/ CN703
8

IC6007 5V REG.

OCP

43

SET 5V SOURCE

+15V D6501 P

IC6506 OVP Q6522 D6537 +200V (SEC P.S.) R8043 1 OHM Q8009 OCP

48 7 45

STANDBY LED

OVP

OVP Q6530, Q6532 LATCH

OCP
30

DAT O TO/FROM YC/, CRT DRIVE IC201/26,27

D8003

CN6504/ CN702
1 69

29

CLK O

200V TO HV CONV. AC FROM F BD.

Q6527 Q6501 AC RELAY AC TO +200V/ +135V POWER SUPPLY

AC RELAY

SELF-DIAGNOSTIC CIRCUIT 1/2

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77
Then use your scope to examine the signal to the cathode. Go to CN9001/ pins 1, 3 and 5 to see if there is a signal coming into the C board. Next check the signal at the CRT cathodes. If they are present, check the IK signal from CN9001/pin 8 of the C board. You should see three pulses and be able to change the level of the signal with the G2 control. If you get about 1Vp-p pulses at pin 8, this is the normal output from the CRT/C board so the problem is on the A board about IC201. Q214 is turned on for five seconds at power ON to permit comparator IC5007 time to stabilize. Testing - If the Standby light blinks two or seven times, the problem is most likely on the D board where the sensing and Horizontal Output stages are. On the D board, if the Horizontal Output (Q5030), PWM (Q5003) transistors, and video output ICs (C board) are good, suspect the components in the sensing circuit (same board). The sensing parts are Q5004, IC5007 and Q5018. Verify that this circuit is causing the shutdown by disconnecting the H. Output Transistor Q5030 and monitor the voltage at CN5505/pin 8 as you power ON. If this voltage rises above 1 volt, this +135V OCP circuit is responsible. Suspect Q214 on the A board and the following main parts on the D board: R5013, Q5004, IC5007, delay cap C5006, Q5018.
Bridge Connectors 10 1 CN6006 1 8 CN6504 1 11 CN6506 1 10 D Board CN5503 1 10 CN5505 1 8 CN5501 1 Back of TV CN706 I O G n/c CN203 CN201 CN703 CN702 Hot Ground

Shutdown - Standby light blinks six times


Circuit - IC701/pin 43 monitors the Set 5V supply from the power supply on the A board. This voltage feeds almost all the boards. A short on the Set 5V line will cause IC701 to shut off the AC relay (IC701/pin 69 goes LOW). Testing - At power ON, measure the Set 5V at regulator IC6007/Output on the A board. The trip voltage is 3.7Vdc. If this voltage remains low at power ON, unplug the B board within the A board and power ON again.

Shutdown - Standby light blinks seven times


There are two +135V OCP monitoring circuits. The first circuit will cause the Standby light to blink two times and the second will cause the light to blink seven times. Both sensing and output circuits are on the D board, but the indicating circuit is on the A board. Circuit - The second OCP circuit monitors the current through the PWM Output (Q5001-3) that supplies B+ voltage to the H. Output transistor Q5030. When there is excessive current drawn by the Horizontal Output stage, Q5018 turns OFF, permitting IC201/pin 34 to rise to a threshold of 1.2Vdc. IC201 blanks the picture to prevent a CRT line burn and sends data to IC701/pin 30 to shut down the TV.
6 CN6501 1

CN6505

6 CN6005 IC 60 07 A Board IC6007

Normal Operating Voltages Location IC5007/pin 8 IC5007/pin 9 IC5007/pin 1 Q214/base 3V 2.6V 5V for 5 seconds At power ON 0.07V Operating 0V 3V 2.6V 0V

+12V A BD. CN202/ CN9001


58 8

+12V R9006 Q9001 P R9008 R9012 D9002 R9068

C BD.

R9036 R9041 R9042


IK FROM IC9001/5, IC9002/5, IC9003/5

C219 0.068 25V DATO FROM MAIN uCOM IC701 IC201 Y/C, CLKO CRT 26 DRIVE
25

R9065

IK
MAIN 9V R250
7

D BD. R5599 10k R5046 1.8 OHMS


8

R249
35

IC5004 V OUT

L5001
5 6

CN5002
5

OUT V YOKE

V CN203/ PROT CN5505


34

R5052 1.5 OHMS MAIN 12V Q5004 OCP

+135V R5013

R5104 Q5018 H PROT PROT MUTE MAIN uCOM IC701/54 Q214 N N R5125
1

IC5007 COMPARATOR + MAIN 9V


8 9

C5006 10 HDT T5001/1 R5108

Q5001 Q5002 Q5003 PWM OUT

R5108

H OUT Q5030

SELF-DIAGNOSTIC CIRCUIT 2/2

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78

APPENDIX

Service Mode Display


Service Mode Access (same as other Sony TVs):
Point the remote control at the TV and press the following buttons: Display, 5, Volume +, Power ON.

Service Group Service Item

Data

Service Video 5 480i

WLS = 0

Display
The service mode display has more information. WSL At the center of the service screen is a Weak Signal Level (WSL) number. This number is similar to the AGC level in older TV sets. The lower the WSL number the stronger the TV signal. 0 is a strong station and about 255 corresponds to snow. When a video input is selected, the WSL number is fixed at 0. 480i/480p/1080i Video Format When Video 5 or 6 is selected, the input format is shown at the right side of the display. The video format is detected by the MID circuit when measuring the horizontal frequency of the signal input. The default format is 480i when there is no video signal input.
F/A Flag: CBA Flag: 11110111 11111111

Memory Check In the service mode you can check the condition of two of three NVM ICs (memories). Press the #2 button repeatedly until the Service Group = ID. At the lower right, G = Good. NG = No good.
ID ID0 0 89 WSL=0 Service 480I

Input signal Standard NTSC 480i High Resolution 480p High Resolution 1080i
Bottom Flag numbers

Horizontal Frequency 15,734 Hz 31.5kHz 33.75kHz

Main uCom number Main uCom version NVM G G

A Board NVM D Board NVM

Geometry Adjustments
The geometry adjustments have three memory locations for each item in the service menu. 480i standard NTSC 480p 16:9 aspect ratio 1080i 16:9 aspect ratio After performing the adjustment in the 480i standard mode, change the user setup menu to 16:9 Enhanced Mode. Selecting ON reduces the vertical for the 1080i mode. Perform the adjustment again. The middle 480p 16x9 mode requires a generator to access.

These numbers are added in manufacturing to identify where the boards come from and when they were made. The information is used for quality control purposes.

12.2 - 12.7GHz

Video Decoder MPEG 2

S Video NTSC Encoder Composite Video video

DSS Dish Modulator Tuner 950-1450Hz Transport Demultiplexer audio video Interface IEEE 1394 (i-LINK) Ch 3/4 RF Output

audio SMART card (plug in) Audio Decoder Dolby AC-3 Analog Audio Optical Out (Digital) RJ11 phone jack Low speed data (9 pin D-sub)

Micro

access card

DIGITAL SATELLITE SYSTEM CONVERTER BOX

41DTV02

10/3/00

ii

iii

Antenna

Composite Video

VIDEO Decompression MPEG 2 or Tuner VSB Demodulator

S Video

Format Decoder / Down Conversion

Componet Video (Y, Pb, Pr)

Transport Packet Demultiplexer

Analog L&R

Cable signal feed Micro

AUDIO Decompression Dolby AC-3

Digital Optical Port

DTV SET TOP BOX

9/13/00

IEEE-1394
Overview
IEEE-1394 is high-speed digital interface that can be used by many types of products, including computers and consumer electronics. It uses transaction-based packet technology to communicate between devices. This standard was developed to help bridge the gap between PCs and consumer electronic products.

Peer to peer communications are possible. Any device should communicate with any other device without the need for a hub or a PC to be connected.
CAMCORDER CAMCORDER

PEER TO PEER CONNECTION

Advantages
The IEEE-1394 has been chosen as the standard interface for digital consumer products because of its many advantages. Listed below are several of these advantages: It is a hot pluggable and unpluggable system. Devices may be added or removed at any time and their presence or absence will be recognized by the system. It is a non-proprietary standard adapted by the Institute for Electrical and Electronic Engineers. There are no licensing problems at this time to stop companies from adapting this format. It allows for flexible hookups and easy connection. One thin cable between devices does it all. The system allows for daisy chaining up to 63 devices together at one time and also supports branching. It is Plug and Play and does not require ID jumpers or switches. There is no need for terminators.

The system uses scalable architecture that will allow older, slower devices to communicate with newer, faster devices at the slower rate. Different combinations of faster and slower devices can be used on the same bus.

Hardware
There is hardware currently available to support speeds of 100, 200 and 400 Mb/s (Megabits per second). These speeds are fine for digital video since it has a data rate of 30 Mb/s. Data rates of 800 and 1600 Mb/s are already scheduled for release. A data rate of 3200 Mb/s is in the planning stage. IEEE-1394 consists of three layers of hardware called the physical, link and transaction layers. These components may be found in a single IC or in several ICs. These layers will perform the same function regardless of how many ICs there are. A description of each layer is listed below: Physical Layer Provides the electrical and mechanical interface between a device and a connector. This layer also provides initialization and arbitration between devices. There is a built-in arbitration subroutine that will make one of the devices the bus master. This device will assign IDs to the nodes (devices connected) and control traffic. Link Layer The link layer handles all data packet transmissions and receptions. The data can be either asynchronous or isochronous.

PC

PRINTER

DIGITAL VCR

CAMCORDER

TYPICAL IEEE1394 HOOK-UP

iv

v
Transaction Layer Manages asynchronous data protocols. This layer is also responsible for communicating between a device that is using IEEE 1394, such as a digital camcorder or a capture card, and the link layer. This would be the system control IC in a camcorder and the PCI bus in a PC.
MODE DATA BUS TRANSACTION LAYER

IDs Cleared - All previous ID information is erased. Tree ID - The device, which is the bus master, assigns each node a specific address. This is called the Tree ID Process. Self-ID - After IDs have been assigned, the system allows time for each device to identify itself to the other nodes in the network.

Multi-Speed Transactions
The IEEE-1394 allows for data transmission speed to vary over the network. If necessary, a faster device will change its speed to communicate with a slower one. The paths taken between devices also limit data rates. In Example A below, the PC or scanner would have no trouble communicating with the camcorder at a rate of 100 Mb/s. However, the scanner could not communicate with the PC at its top data rate of 200 Mb/s because the path between the two contains a 100 Mb/s device (the camcorder). The maximum data rate that can be achieved through another device is limited to the speed of that device. In example B, the PC and the scanner would be able to communicate at the scanners top rate of 200 Mb/s. It is very important that when an IEEE-1394 network is set up that care is taken to properly place devices that need to communicate with each other at top speeds.

VIDEO AND AUDIO DATA

LINK LAYER

PHYSICAL LAYER

EXAMPLE: IEEE1394 INTERFACE IN CAMCORDER

Protocol
Data Transfer
There are two types of data transfer possible using IEEE-1394. They are as follows: Asynchronous This is a memory mapped system. Each packet of data is sent to a specific address to be stored and buffered by the recipient. An acknowledge signal is sent when the data is properly received. Isochronous - Isochronous data needs to be sent and received at a steady rate that is in close timing with the ability of the receiving device to process the data. For example, if a digital camcorder processes data at approximately 30 Mb/s, then the receiving device must be able to use this data at the same rate. Data is essentially broadcast at a predetermined rate and not checked for accuracy.

PC 400 Mb/s

CAMCORDER 100 Mb/s

SCANNER 200 Mb/s

BANDWIDTH LIMITED BY SLOWER DEVICE

PC 400 Mb/s

SCANNER 200 Mb/s

CAMCORDER 100 Mb/s

Dynamic Node Addressing


Each device, called a node, is assigned a specific address. This occurs when a bus reset occurs or a new device is added to the system. Three steps occur when these events occur:

BANDWIDTH NOT LIMITED BY SLOWER DEVICE

Cable Technology
Wire
A standard six-wire cable is used by the PC industry as an IEEE-1394 connection. There is also a four-wire connection used by Sony and other manufacturers on digital camcorders and similar devices. The six-wire cable contains B+, Gnd, and one differential pair for transmitting data and one differential pair for receiving data. The four-wire cable only contains the two differential pairs for data. There are adapters available if one device uses a four-wire cable and other uses a six-wire cable.

Trade Names
There are a few trade names associated with the IEEE-1394 standard. The most notable are Fire Wire, which is an Apple trademark and i.LINK, which is a Sony trademark.

Current Products
A brief list of products that use IEEE-1394 are: DV Camcorders D8mm Camcorders High-Resolution Digital Cameras HDTV HDTV Set-Top (Converter) Boxes DSS (Digital Satellite System) Boxes Hard Disks DVD-ROM Drives Printers Scanners

Future Developments
CABLES

Connector
The connectors are simple, sturdy and reliable. They are designed with the contacts inside the connector to reduce corrosion and the risk of shock. They are childproof, if there is such a thing, and are based on the Nintendo NES connector.

IEEE1394 seems poised to take its place as the home networking standard of the future. Its high speed and ease of use are part of the keys that may one day make it the bond between all the components in your home. Sony, along with other industry leaders, is working on a standard called HAVi. HAVi, which stands for Home Audio Video Interoperability, would be an open architecture system. This means that software, application programming interfaces and communication protocols will allow all digital electronic components to work together regardless of manufacturer. This might mean that you could control your DTV set top box, digital audio system and the temperature of your refrigerator all from one central location. The amount of products that may use this system is limitless. We are heading for a digital future and it seems that IEEE1394 will be a large part of it. Fire Wire is a trademark of Apple Computer Inc.

i.LINK is a trademark of Sony.


CONNECTORS

vi

vii

DX-1A CHASSIS ASSEMBLY

[C] ANT SW
MAIN SUB

CN9001

CN9002

TO DY FOCUS LEAD

HV LEAD

CN9102 CN9103(N/S) CN9101

[W]

[ BC ]

[U]

Put one loop in HV Lead and secure with purse lock 9

CN603 AC CORD CN607 DGC CN605

[B]
CN202 CN204 CN3204 CN201

BUSCONN

CN706 CN5501 CN5505 CN5003 to [C] (G-2) CN5503 DY CONN CN5002

CN203

CN703 CN6506

CN606

[S]
CN702 CN707 CL701 CN6006

[ D]
CN5510 to CY

CN6504

HV REG. BLOCK (Optional)

[A]
) CN7004 CN7003

CN6501 CN6505 CN 6503

CN701

CN6005

CN6502

CN5005 to [VM]

TO SPEAKERS 12mm Purse Lock (38mm height)

TO SPEAKERS CN4503 CN4301

[HB]

[HA]

Board Replacement
Board Removal
D Slide chassis assembly back away from the pix tube. Remove 7 screws securing the board. Slide the board toward the pix tube and tilt up to access the flyback. Unsolder the flyback.

Functions
Primary Power Supply (+200V, +135V) Protection latch circuit HV Regulator circuit Corner focus circuit Top/bottom pincushion circuit H Output / V Output

Possible Failure Symptoms


Shutdown Sides bowing in

After board replacement


Transplant memory IC5501 containing deflection parameters. Adj Focus (on FBT). Enter the service mode and perform touch up geometry adjustments to DConv/CXA8070 (group #6) and CXA2026AS data (group #7)*. Adjust HV RV8002 for 31.5kV. Adj HV shutdown RV8001 (coarse) and RV8003 (fine) according to safety related adj in the service manual.

A Remove 4 screws from the rear panel and fold it down. Pry the locks from connectors CN3202/3 while wiggling the B board away form the A board. Remove 6 screws securing the A board. Lift the right side of the A board out.

Standby Power Supply Degaussing circuit Secondary Power Supply (9V, 5V, 3.3V) H & V Oscillators/Jungle Both Tuners Main uCom IC701 Audio processing OSD (Menu)

Dead set (check front panel master switch).

Transplant memory IC707 containing system and user data. Enter the service mode and verify the TV ID (group #19), then perform touch up geometry adjustments to CXA2150D-1 data (group #4-1)*.

U Remove 4 screws from the rear panel and fold it down. Pry the locks from its connector and wiggle it

Rear panel input connectors Loss of video / audio 1-6 inputs. Tuner is unaffected.

None

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B Remove 4 screws from the rear panel and fold it down. Pry the locks from connectors CN3202/3 while wiggling the B board away form the A board. C Wiggle the C board off the CRT neck. Unsolder the CRT socket and install on the new board. W Velocity Modulation circuit to improve detail Video processing and audio switching. Closed caption/V Chip DRC for line doubling MID for twin pictures RGB CRT signal amplifiers Dark screen (adjust G2 first) Stby light blinks 5 times & repeats. Adj Screen control according to the service manual: Reduce vertical size to see IK line at the top. Blank pix in the service mode by changing CXA2150P-2/ALBLK data from 0 to 1. Adjust screen control so the IK line is just invisible in a dark room. W board clamp Pix tube Loss of video, Y or C. Loss of sync to main or sub pix. Transplant memory IC3089 containing Twin picture parameters.

Remove the C board. Mark the pix tube neck to reinstall the new W Top/bottom Pincushion & corner focus coils board assembly. Loosen the clamp and remove the assembly.

White outline along object.

G1

* Refer to the service manual s section 5 for the list of adjustments.


HA/HB boards - Front panel remote & buttons Dynamic Convergence

Secondary Power Supply

Primary Power Supply S Bd (audio)

HV Regulator

Horizontal Deflection

FBT Vertical

B board (video) Stby Circuit

Front of TV

Pry out CN3202

HA board D Board

HB board A Board

B board BC board

Pry out

CN3203

BC board U board

U board

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S
Sony Service Company National Technical Services A Division of Sony Electronics Inc. Park Ridge, New Jersey 07656

CONFIDENTIAL
Service Bulletin TV Products
KV-32XBR400, KV-36XBR400

csv-1

Model:

No.

492

Subject: Service Manual Correction: Safety Related Adjustments Symptom: (****)

Date: July 27, 2000

There is an error on page 23 of the preliminary service manual in the HV Service Flowchart.

Solution:

Change the incorrect text as follows: Incorrect: "Confirm +B, Vd, and check hold-down on D-board with black video with the following steps: 1. Confirm +B across C6544 to make sure it is 135.3 1 Vdc. 2. Confirm Vd at pin 2 CN6506 or at TP-Vd for 4.9 V < Vd < 5.1 Vdc. 3. Apply 5.5 + 0.5 VDC at pin 2 of CN6544, then confirm set holds down."

Correct: "Confirm +B, Vd, and check hold-down on D-board with black video with the following steps: 1. Confirm +B across C6544 to make sure it is 135.3 1 Vdc. 2. Confirm Vd at pin 2 CN5506 or at TP-Vd for 4.30 V = Vd = 4.65 V. 3. Apply 5.5 + 0.3 VDC at pin 2 of CN5506, then confirm set holds down."

S and i.LINK are trademarks of Sony Electronics Dolby Digital is a trademark of Dolby
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S
SEL Service Company A Division of Sony Electronics Inc. 1 Sony Drive Park Ridge, New Jersey 07656

DTV021000

Printed in U.S.A.