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Canadian Journal on Electrical and Electronics Engineering Vol. 2, No.

7, July 2011

A One-Memristor Cell Implementation of a Non-Volatile Memory System
Afsaneh Shadaram, Sattar Mirzakuchaki, and Farahnaz Zakerian
Abstract — A Memristor is a two terminal resistive memory. As the memristor retains its state when un-powered, it is considered a nonvolatile memory. This element has nanoscale size which results in an increase in the density of memory chips. In this research, we demonstrate reliable writing to and reading from a 4×4 crossbar memory array based on the memristor. We have also designed the corresponding demultiplexers, writing and reading circuits. One of the main drawbacks of memory arrays based on onememristor cells is the parasitic current that is presented while reading which causes logic degradation. Thus, the memory system in this paper has been designed in such a way that the parasitic current becomes minimum. The data string [1010] has been written to the first column of the memory array and then has been read from it successfully. The procedure of reading has been done in both ideal and real conditions. In the case of real condition, the resistance of the nanowires has been considered and in order to generate the reference voltage for comparison between ‘‘0’’ and ‘‘1’’, the reference cells are used in a memory array. To investigate the worst condition, other non-selected cells are put in "1" state (closed resistor), which thus contributes the most parasitic currents. In both read process cases, the output string [1010] has been retrieved successfully. Key Words — crossbar array, memory resistor, non-volatile memory .

In 1971, Leon Chua represented a two terminal circuit element named memristor (memory resistor) which was described by a relationship between flux and charge [2]. This element was introduced as the fourth basic circuit element after resistor, capacitor and inductor. In 1976, Chua showed that memristor poses an interesting non-linear characteristic that makes it a special member of the non-linear dynamical systems, called memristive systems[3]. After 37 years, in 2008, R.Stanely Williams and his research group in HP (Hewlett-Packard) laboratory constructed a memristor device based on the TiO2 film in the crossbar arrays and presented a physical model of memristor for the first time [4]. Consequently, some other models were presented for HP’s memristor [5]-[7]. The crossbar arrays based on one memristor cells have a simple structure and easy to fabricate. They can also be constructed as 3D stacked multilayer which can increase the memory density to as high as 100 [8]. The frequency response of the current-voltage curve in a memristor is hysteretic. So, its resistance depends on the amplitude, polarity and the duration of the applied voltage to it. When the power is off, memristor can retain its latest resistance till a voltage with a different value and polarity is applied. The ability of maintaining resistance values in the memristor for a long period of time shows that this device can be used as RRAM. II. THE PHYSICAL MODEL OF CONSTRUCTED MEMRISTOR IN HP LABORATORY The HP’s constructed memristor is in the crossbar array shape, made up of nanowires. There is a memristor at the point where two nanowires cross each other. These nanowires are fabricated from Platinum which are used as electrodes in the cross points. Between these two electrodes, there is a 3-10 nm thin film of TiO2. The film consists of two layers. In the bottom layer, the ratio of Oxygen to Titanium is 2:1, that acts as an insulator while in the upper layer, TiO2 has lost part of its Oxygen (TiO2-x). The oxygen vacancies in TiO2-x make this layer a conductor. In Fig. 1, the thickness of the thin film between two electrodes is represented by L. The total resistance of the device is a two variable resistance that is connected in series. The portion of the semiconductor film that has high concentration of dopants (positive ions) has a low resistance (RON), and the remaining region that has a lower concentration of dopants, has a higher resistance (ROFF).

I. INTRODUCTION According to the Moore’s law, transistors’ density on chips doubles every two years. Because of numerous limitations, this trend eventually comes to an end. In addition, the materials and technologies in the semiconductor industry are reaching their physical limitations. Therefore, in electronics design, it is necessary to shift to devices that are increasingly infinitesimal and efficient. It is essential to develop the nanoscale memory cells in non-volatile memories. In recent years, a variety of non-volatile memories such as Ferroelectric RAM (FeRAM), Magnetic RAM (MRAM) and Resistive RAM (RRAM) have emerged [1]. Among these memories, the RRAM plays an important role due to a low operational voltage, high speed, long retention time, simple structure and nano-scale size.
Afsaneh Shadaram and Farahnaz Zakerian are with the Department of Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran (email: A.shadaram@srbiau.ac.ir; F.zakerian@srbiau.ac.ir ) Sattar Mirzakuchaki is with the E. E. Department, Iran University of Science and Technology, Tehran, Iran (email: M_kuchaki@iust.ac.ir)

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III.Canadian Journal on Electrical and Electronics Engineering Vol. (4) Fig. and column and row demultiplexer circuits. IV. So. needs to be restricted. No. the amplitude of the applied voltage should be much lower than the threshold values in order for no switching to occur. . July 2011 duration of this pass through. 2 indicates that by applying a voltage equal to or higher than positive threshold value. . Thus. the boundary . The value RON is coded as “1” and the value ROFF is coded as “0”. v(t). VR is the amplitude of the read pulse and the tolerance level “γ” is the upper bound for w(t)/L for all times. where µ v is the average of the ions mobility. we obtain: = + 1− 3 Fig. 3. the boundary between the two regions . Additionally. the read pulse width. the total resistance of the device becomes RON. µ v is the average mobility of ions and Vwr is the amplitude of the applied voltage for writing. w(t) =0 or y = 0 can be obtained after a small delay. By applying a voltage much lower than the threshold value. The ideal hysteretic current-voltage (I-V) curve in memristor Because the ions need some time to reach the boundaries of the device in a memristor. Two variable resistor model for memristor By applying a voltage. THE IMPLEMENTATION OF MEMORY SYSTEM BASED ON ONE-MEMRISTOR CELLS In this work. L represents the length of the device. will move to 0 or L. As a result. . higher than the threshold values across the device. Block diagram of the designed memory system immediately after the voltage reaches a threshold value. 3 − (5) where. For the read operation. The obtained physical relationships are as follows [4]: = = + 1− 1 2 where.w. Tread. the resistance does not change and it keeps its latest value. applying a read voltage for a long duration of time may change the amount of the flux passing through the device and move the boundary w. The memory array is a 4×4 crossbar array based on the one-memristor cells. The 347 . OPERATION OF MEMRISTOR AS RRAM By replacing y= w (t)/L in (1). the charged dopants will drift. This restriction is obtained from [9]: ≤ . will remain in its latest state. 2. w(t) is the thickness of the conductor region and i(t) is the current flowing through the device. by applying a negative voltage equal to or higher than the absolute value of the negative threshold voltage. 2. switching does not occur Fig. Similarly. Therefore. For voltages between threshold values. Twr.w. Fig. we used the block diagram of the designed memory system shown in Fig. the total resistance becomes ROFF. 1. 3. This block consists of column and row multiplexer switches. based on the polarity of the applied voltage. w(t) becomes L (y becomes 1). after a small delay. 7. is calculated applying the following equation [9]: ≥ . .

6. As is shown in Fig. 5(c)). the current passing through the memristor can be measured. switch S3 will connect to the read voltage source. Since these memristors are hysteretic. To read from the selected memory cell. July 2011 For the write operation. For writing “0”. one side of each switch is connected to the ground and the other side is connected to the data inputs through 10 k resistors in writing procedure or read voltage source and comparator circuit in reading procedure. and switch S1 will connect to the sense amplifier. 5(b)). (c) reading from the selected memory cell. by applying half of the positive threshold voltage (or a higher voltage) to the positive terminal of the selected memristor and half of the threshold voltage (or a higher voltage) with negative polarity to the negative terminal. 348 . 6. and disconnect S1 and S3 switches from the sense amplifier circuit and read voltage source. the voltage across the device becomes equal to (or higher than) the negative threshold voltage and the total resistance of the memristor becomes high (ROFF) (Fig. 5. the total resistance of the memristor becomes low (RON) and “1” will be written to it (Fig. the positive terminal of memristor is connected to the vertical nanowire and the negative terminal is connected to the horizontal nanowire. the write/read voltage enable (VWR/RE) becomes high in order to connect S0 and S2 switches to the inputs. and (b) writing “0” to the selected memory cell. 7. 4. 4(a). the VWR/RE should become low. (a) The 4×4 crossbar memory array (b) One-memristor memory cell As can be seen in Fig. Multiplexer Switches Each vertical and horizontal nanowire ends with an nMOS switch. No. (c) Fig. B. respectively. Each vertical and horizontal nanowire ends with an nMOS switch as switch multiplexer. The reference cells are used to generate the reference voltage while reading from the memory array in real conditions. (a) (b) Fig. So. In each cross point there is a memristor acting as memory cell. In this way. its positive terminal must be connected to the read pulse voltage source (VR). For the read operation. VR.Canadian Journal on Electrical and Electronics Engineering Vol. the voltage across the device becomes equal to (or higher than) the positive threshold voltage. The 4×4 Crossbar Array The 4×4 crossbar memory array consists of four vertical nanowires crossing over four horizontal nanowires as shown in Fig. Fig. which is much lower than the threshold value and its negative terminal must be grounded through the sense resistor (RS) (Fig. 4(b). 2. (a) (b) A. 5(a)). the polarity of these voltages must be changed. In this way switches S0 and S2 will disconnect from input data. In this way. (a) writing “1”.

respectively.(2.(3.1) in an ideal condition is shown in Fig.1) in the first column of the memory array. VWR/RE must become low to connect the positive terminal of the targeted cell to the read pulse. 8. must be restricted according to (5) in order to avoid the movement of boundary ‘‘w’’. TABLE I ROW INPUT ADDRESSES a1a0 11 01 10 00 Row1 0 1 1 1 Row2 1 0 1 1 TABLE I I Row3 1 1 0 1 Row4 1 1 1 0 COLUMN INPUT ADDRESSES b1b0 11 01 10 00 Col1 0 1 1 1 Col 2 1 0 1 1 Col 3 1 1 0 1 Col 4 1 1 1 0 (a) D. the input voltages of each three resistors connected to them should be 0V. Here. only memory cell (i.5V. 2. As described before for writing. all other non-selected memristors have been put in RON state. The reason is that in this condition. The same string has been then read. we face the highest possible parasitic current in the array. which carries the memristor state information. Voltage divider resistors can be memristors which are not hysteretic and have been put in RON states permanently during manufacturing. one of the resistors connects to 0V and two of them connect to 1.Canadian Journal on Electrical and Electronics Engineering Vol. the voltage divider resistors play as three inputs wired NAND gate instead of an AND gate. 7. By doing this. this voltage will be compared to a reference voltage in the sense amplifier stage. RS. So. the selected row and column connect to the data inputs or read circuits. the current passing through the selected cell.[11] with some modification. C. July 2011 These switches operate as multiplexers in such a way that for writing or reading procedures.1. Tread. VWR/RE must become high in order to connect the selected memristor cell to the data inputs through S0 and S2 switches. the output of XOR gate and its inverter are interchanged. through S3 switch and to connect its negative terminal to the comparator circuit through S1 switch. Then. As can be seen. Demultiplexers Demultiplexer circuits in this research are the same as improved resistive demultiplexers that have been described in [10]. the output voltages of all non-selected rows and columns become 1V which cause the corresponding multiplexer switch to be turned on. the output voltage becomes 0V and turns the corresponding multiplexer switch off. only one memory cell will be selected in order to write to or read from it.1).1). In this way. 7. The gate control voltage of these switches comes from demultiplexer stages. Writing to and Reading from the Cells of Memory Array In this work the data string [1010] has been written to the cells (1. In all other non-selected rows and columns. the parasitic resistors of the nanowires are neglected.j) will be selected. by dividing voltages through these resistors. The sense resistor is the pull up resistors of the nonselected multiplexer switches in parallel.1) and (4. only one of the column switches and one of the row switches will become off. To consider the worst case while performing writing and reading operations. By choosing row i and column j. D. The width of these input pulses should be obtained from (4) to guarantee the switching event. The read pulse width. (b) 349 . while reading. Read operation in ideal conditions The Equivalent circuit while reading from the cell (1. The first row and the first column of the array are connected to ground through the sense resistor and the read voltage source. The input addresses of all rows and columns are presented in TableI and TableII respectively. No. Through this method. In this way. will be converted to a voltage signal across the sense resistor. these voltage divider resistors have been chosen to be 300k to neglect the resistors of the demultiplexer wires. VR. The latter forces the non-selected rows and columns in the memory array to be grounded. 7 shows the column and row demultiplexers. For reading. In order to select one row or column. Fig. (a) Row demultiplexer (b) column demultiplexer In this simulation. Fig. Consequently.

In real conditions. In order to have distinguishable states. Thus. μ = 3 × 10 .(1. since both terminals of the other memristors are connected to the ground directly. becomes high for write operation and then becomes low at 260 nsec for read procedure. for the sense amplifier becomes necessary. is selected and the corresponding current passes through the sense resistor. 9 illustrates the equivalent circuit while reading from cell (1. As is shown in Fig. No. July 2011 respectively.1) in real conditions. Equivalent circuit while reading from the cell (1. D. 8.Canadian Journal on Electrical and Electronics Engineering Vol. one in ‘on’ and the other in ‘off’ state. Fig. L = 3 nm and the threshold values are considered ±2 V. Read operation in real conditions Fig. Reference cells in the top row are in ‘‘on’’ and ‘‘off ’’ states alternately.3 and 4 are not grounded directly. The average of the voltages generated across the sense resistors of the two reference cells goes to the sense amplifier as reference voltage. as reference cells. only the cell of the first row. In an ideal condition. that at first. the reference cells are inserted in two rows. for each column there are two vertical adjacent reference cells. currents flow through them. no leakage current would flow in them. (a) 350 .2. both terminals of memristors of columns 2. The other rows and columns are grounded directly. The reference cells can be the memristors which are not hysteretic and have been put in ‘on’ and ‘off ’states permanently during manufacturing. SIMULATION RESULTS Simulation in this research is based on the following parameters: RON = 1M . Vref.1 mV in this circuit. So. VWR/RE. ROFF = 1G . 7. alternately. V. one on the top and the other at the bottom of the array. the parasitic resistors of the rows and columns nanowires have been considered and their values have been chosen to be 100k in this simulation.1) in ideal conditions. Among the memristors of the column 1. 9. Equivalent circuit while reading from the cell (1. 2. only across the memristors of the first column the voltage differences appear and consequently. Here. using reference cells to generate reference voltage.1). Fig. But. the reference voltage can be a voltage source with a constant value which has been selected to be 0. Due to the voltage dividing. leakage current occurs in these cells which may disturb determining selected memristor state. 10(a) demonstrates the write/read enable voltage. 9. and reference cells in the bottom row are in ‘‘off ’’ and ‘‘on’’ states. This scheme of generating reference voltage in crossbars has been presented in [12]. Fig.1) in real conditions.

the input voltage at node in+ is –1. VWR/RE . while reading the data from the cells in ideal condition.1) become "1". read voltage pulse (VR).1) and (3.1). V (RS) with the generated reference voltage (VREF) along with the reference cells and Vdata-out .the value of y does not change and remain in its initial value. The data input voltages at terminals in+ and in– of the selected memristors and their corresponding internal states ‘y’ are shown in Fig.1). once for write and once for read operations. Fig. 12 demonstrates the VWR/RE .y2. (a) Fig. So. respectively. As can be seen.2. consequently.1) . rows 1. "1" is written to the cell (3.2 V. By considering Vwr =2. the input voltage at node in+ is +1.1). the state of the cells (1.(3.4 V (higher than the threshold value +2 V).1). to guarantee the switching event. 10(b) shows the gate input voltages of row multiplexer switches that come from row demultiplexer circuit. As shown in Fig. the output data (Vdata-out ) represents the data string [1010] successfully.(3.1). the voltage presented across the sense resistor (V(RS)) and the output voltage of the sense amplifier circuit(V(data_out)) signals.1) becomes +2.4 V (higher than the absolute value of the threshold –2V). 2.3 and 4 are selected twice. July 2011 (b) Fig.1) respectively. Fig. the duration of these applied inputs must be Twr≥ 65 nsec based on (4).1) and (4.1.1) and (4. In this simulation. 13 illustrates the VWR/RE. the cells (1. 7. once for writing to them and once for reading from them. The latter causes the voltage difference across the selected cell (2. (b) gate input voltages of row multiplexer switches that are selected twice consequently. In both ideal and real conditions.1) and "0" is written to the cell (4.1). 10. (a) Write/read enable voltage (VWR/RE). As can be seen in these figures. (a) The data input voltages at terminals in+ and in– of the circuit.1).y3 and y4 signals that represent the state of memristors (1. respectively. is generated exactly between "0" and "1" values. To write "0" to cell (2. Fig."1" and "0" respectively. Therefore. the data [1010] is written to these memory cells. (b) y1.1) respectively."0". Thus.Canadian Journal on Electrical and Electronics Engineering Vol. while writing "1" to cells (1. Column 1 is in the selected state at all times. 351 . in comparison with the V(RS) signal. while reading the data from the cells in ideal condition. VR.(3.1) to become –2.(2. once for the write and once for the read operations.1) and (4. the voltage presented across the sense resistor (V(RS)). and the output voltage of the sense amplifier circuit (V(data_out).(2. The initial value of y has been considered "1". According to this method. Thus.4 V.(2.1). the voltage difference across the cell (1. In order to write "1" to cell (1. while reading the data from the cells in real condition. By choosing γ=0. (b) Fig. 12.2 V and at node in– is +1.6V (much lower than thresholds). Tread has been considered to be 12 nsec. The amplitude of the applied read pulse is 0. the duration of this pulse for each read process must be restricted to Tread ≤ 73 nsec based on (5) to avoid the changes of ‘y’ while reading from the cell. read voltage pulse (VR). the reference voltage that is shown by dots.2 V and at node in– is –1. 11. 11(b). No. 11.2 V. respectively.1) will be selected respectively.

2009. D. P. Seroussi. K. M.6: 687-691. one of the most common problems in one-memristor cell crossbars is the parasitic current that originates from other cells during the measurement of the targeted current.5: 507-519.106. Electronics Letters. 7. and S.33:917–978. has been investigated. devices and mechanisms’’. In an ideal condition.D.S. Farahnaz Zakerian received the B. degree in electrical engineering from the Islamic Azad University of Yazd in 2007. “Polymer electronic memories: Materials. 2. Snider. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.T.4 mV for "1" and 0 mV for "0".64.S. [5] S. Kuekes. “ Memristor .J. D. Dr. Tehran. Huang. IEEE Trans on nanotechnology. Kuekes. and the MS and PhD in Electrical Engineering from the University of Missouri-Columbia. 1976. Progress in Polymer Science.S. The VWR/RE.45(7): 377–379. IX.18(2):210-214. Nature. Chua. Since 2008.S. Mustafa. 13. REFERENCES [1] Q. Robinett.the missing circuit element”. April 2010. O. Radioengineering Journal. Shin. The data string [1010] has been written to the first column of the 4×4 crossbar memory array and then it has been read from the memory. VR. and also the corresponding generated reference voltage has been obtained 488. In real case.R. Kang. W.S. T. IOP Publishing Nanotechnology 16:1419-1432. E. VOL. R.2009. the voltage presented across the sense resistor has been retrieved as 1. [6] Z.B. IEEE Trans on circuit theory. respectively. O. the reference cells which are locally correlated in one column have been used in order to generate the reference voltage. BIOGRAPHIES Afsaneh Shadaram received the B.A. Fig. Since the memory cells are not separated from each other. pages 485-490. Strukov. In both read process experiments. S. “ Defect-tolerant demulti. [10] P.453: 80–83. 2008.Canadian Journal on Electrical and Electronics Engineering Vol. Her current research interests include characterization of semiconductor devices and nanotechnology. Wey. VOL.G. Williams. NO. The read operation is done in both ideal and real conditions. student in Department of Electrical Engineering at the Islamic Azad University. “ Four-Dimentional address topology for circuits with stacked multilayer crossbar arrays”. R. in 1991 and 1996. Benderli. Her current research interests include design of VLSI circuits. 2009. Science and Research Branch of Tehran.6 µV. Stewart.CT-18. Appl Phys.S. Waser. Strukov. which is almost between "0" and "1" values. In this research.2008. D. IEEE/CAM international conference on Computer-Aided Design Digest of Technical Papers. Williams. Biolek.NO. K. In addition. V(RS) with the generated reference voltage (VREF) by the reference cells and Vdata-out signals respectively while reading the data from the cells in real condition.plexers for nano-electronics constructed from error-correcting codes”. July 2011 [2] L. she is a M. we designed the system with its corresponding write and read circuits. [3] L.S. D.Letters. 2005. “the missing memristor found’’.VOL. Science Direct.NO.S.5 µV for "0" in a real condition. “ Improved voltage margins using linear error. Neoh. degree in electrical engineering from the Islamic Azad University. Chan. He has been a faculty member of the College of Electrical Engineering at the Iran University of Science and Technology. R. Liaw.VOL. Williams. [9] Y.J.48: 20155-20158. R. [4] D . that causes the decrement of margins between "0" and "1". G. 2009. G. This value has been retrieved as 825 µV for "1" and 33. Williams. Sattar Mirzakuchaki received the BS in Electrical Engineering from the University of Mississippi in 1989. PNAS. V. C. student in Department of Engineering at the Islamic Azad University. His current research interests include characterization of semiconductor devices and design of VLSI circuits. Kang. Li. [11] P. 1971.J. NO.S.S. Kang. Biolkov´a. Chua.B. 29(4):590 – 598. “ SPICE model of memristor with nonlinear dopant drift”. HO. the data [1010] has been retrieved in the output of the sense amplifier successfully.A 80:1161-1164. . Biolek. Proc IEEE.2005. she is a M. Mirzakuchaki is a member of IEEE and IET (formerly IEE) and a Chartered Engineer. since 1996. Thus. CONCLUSION In this paper we implemented and analyzed a memory system based on memristors.2: 209–223. Since 2008. “ Compact models for memristors based on charge-flux constitutive relationships”. [12] J. G. No. “ Memristive devices and systems’’.VOL. Zhu. Science and Research Branch of Tehran. Kim. W. the resistance of nanowires. “On SPICE macromodelling of TiO2 memristors”.2006. the write and read circuits have been designed in such a way that the parasitic current becomes minimum. “ A novel reference scheme for reading passive resistive crossbar memories”. R. 352 . [7] S.correcting codes in resistor-logic demultiplexers for nanoelectronics”.M. Ling. Central Branch of Tehran in 2006. Robinett. [8] D .5. “ Nonvolatile memristor memory: Devices characteristics and design implications”. VOL.