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The following is the path for opening S-Edit tool : Start  All Programs  Tanner EDA  Tanner V 15  S-Edit

V15.0 32 Bit

To do schematic entry , run S-Edit tool

To create a new design : File  New Design

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Enter the design name and give the path where it should be saved. Example : techlabs_designs is the design folder C:\Documents and Settings\phanendra\My Documents\Tanner_lab is the target location of design folder

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Add component libraries. The path for component libraries is given below. My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm Click add in S-Edit window for adding the libraries and follow the path of process folder.

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Double click all the component libraries under Generic_250nm and add all tanner database files (.tdb). To add Spice commands and Spice Elements for setting spic e simulation follow the path. My Documents\Tanner EDA\Tanner Tools v15.0\Process\Standard Libraries

Now , we need to create a new cell.

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Give a new name for cell 5 .

then Instance Cell pops up where a user can change the properties . 6 . Either press ESC button on keyboard or Done on Instance Cell window to stop placing of cells. Click on Generic_250nm_Devices folder on libraries To add any component either drag the component on to the design area (black region with grids) or click Instance . Keeping the icon on the design area . And to view entire design press home button on keyboard. components icon can be placed N number of times.Scroll mouse for Zoom In and Zoom Out.

To Zoom the design area scroll the mouse or press home button on keyboard.In the same way place PMOS component on the design area. 7 .

Now place Vdd and Gnd Instances from the Misc folder under Library. 8 . Now place a DC Voltage and Pulse Voltage source from the Spice Elements folder under Library.

9 . Click done only after placing the voltage source on design area. Click Spice Elements.To place a Voltage Source. Under Spice Elements Click Voltage Source and then Instance. change the interface to DC and edit the voltage value . To place a DC voltage source.

10 . change the interface to DC and edit the voltage value . Now place Input and Output ports. Place Vdd and Gnd even for the voltage sources as shown.To place a Pulse voltage source. Click done only after placing the voltage source on design area.

In port window pops up where we can edit the port name . Even the port orientation can be changed by pressing r button on key board.When an input port is placed. Now we have placed all the components on the design window. font size and orientation. And connections are made using the wire as shown below 11 .

12 .Now we need to set up simulation.

13 .lib After giving the path of Generic_250nm.lib file * TT : Typical model for NMOS & PMOS * SS : Slow NMOS Slow PMOS model * FF : Fast NMOS Fast PMOS model * SF : Slow NMOS Fast PMOS model Set Transient Analysis as shown below .lib. give the path of library file.Now . There are different types of Corner models in .lib TT TT is the corner model used . My Documents\Tanner EDA\Tanner Tools v15. My Documents\Tanner EDA\Tanner Tools v15.0\Process\Generic_250nm\ Generic_250nm_Tech \Generic_250nm.0\Process\Generic_250nm\ Generic_250nm_Tech \Generic_250nm. add TT as shown below.

Run Simulation. 14 .

15 .To view waveforms . place PrintVoltage from Spice Commands library. Run Simulation. Now .

Waveforms can be expanded by clicking Chart  Expand Traces on W-Edit window. 16 .Waveforms can be viewed on W-Edit tool once Simulation is Run again. To extract the spice netlist from schematic. go to S-Edit and click the T-Spice option.

0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm. analysis setup .ORDER == 0.The following spice netlist is extracted from the schematic which contains the information of the circuit connections across its nodes. Save the netlist as inverter_sch.General Section ********* .sp ********* Simulation Settings . voltages applied and type of library used for simulation.Devices With SPICE.lib "C:\Documents and Settings\phanendra\My Documents\Tanner EDA\Tanner Tools v15.0 -------***** Top Level ***** 17 .lib" TT *-------.

PRINT TRAN V(In) $ $x=2850 $y=4350 $w=1500 $h=300 $r=180 .end L-EDIT CMOS Inverter Structure: - 18 .0 -------VVoltageSource_2 Vdd Gnd DC 5 $ $x=1800 $y=3800 $w=400 $h=600 VVoltageSource_1 In Gnd PULSE(0 5 0 5n 5n 95n 200n) $ $x=3400 $y=3600 $w=400 $h=600 .Devices With SPICE.3u $ $x=4793 $y=4700 $w=414 $h=600 *-------.3u AD=1.3u AD=975f PD=4.PRINT TRAN V(Out) $ $x=6250 $y=4050 $w=1500 $h=300 ********* Simulation Settings .Analysis Section ********* .Additional SPICE Commands ********* .ORDER > 0.95p PS=7.tran 50n 1u start=0 ********* Simulation Settings .5u L=250n AS=975f PS=4.95p PD=7.3u $ $x=4793 $y=3700 $w=414 $h=600 MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.MNMOS_2_5v_1 Out In Gnd 0 NMOS25 W=1.

run L-Edit tool.0 32 Bit To do Layout . Go to File  New 19 . Follow window pops up.The following is the path for opening L-Edit tool : Start  All Programs  Tanner EDA  Tanner V 15  L-Edit V15.

Click Browse  My Documents\Tanner EDA\Tanner Tools v15. Go to Cell  New 20 .0 \Process \Generic_250nm \Generic_250nm_Tech and add Generic_250nm_TechSetup.tdb file and click ok.

Name the Cell Grids spacing can be minimized or maximized using – or + sign To change the technology Goto setup-> Design 21 .

Select Lambda or microns accordingly and click ok Before designing layout we need to remember following equations N Diffusion = N Implant and Active – (1) P Diffusion = P Implant and Active . First draw active 22 . We are Taking Example of CMOS Layout design Background of L-Edit is P-Substrate by default We need to design PMOS.(2) From layer palette. we can select layer then for drawing layer we need to switch at Drawing boxes as follows Now we can start layout designing.

Now draw P Implant over Active with keeping in mind Lambda based design rules Now draw poly over it accordingly 23 .

Now draw Contact for Active region Now draw metal1 around Contact 24 .

We have designed source. Now we have to design bulk by creating a N+ diffusion Now we need to put this in N-Well 25 . gate and drain.

We can perform DRC (Design Rule Check) at every stage If we are violating any Design rule then it will be shown in Error verification navigator 26 .

27 . the tool points to the error that occur on layout.By clicking on the error.

28 . We need to design Gate contact. And again run DRC check.By increasing the poly density area in the layout we can minimize that error.

go to (A) We can now find the port name added to gate . 29 .To define port.

CMOS layout looks like as follows.Similarly we do NMOS layout. 30 . After connecting NMOS and PMOS .

Now we can extract netlist by doing some settings 31 .

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lib "C:\Documents and Settings\phanendra\My Documents\Tanner EDA\Tanner Tools v15. An spice file will open as follows This netlist is saved as inverter_layout. Run Extraction.PRINT TRAN V(vin) .Click options in Setup Extract above.spc VVoltageSource_1 Vdd Gnd DC 5 VVoltageSource_2 vin Gnd PULSE(0 5 0 5n 5n 95n 200n) .lib" TT 33 .tran 1ns 500ns Final netlist .0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.PRINT TRAN V(vout) . and uncheck all Hiper Verify Options.

08e012 pd=9.2e-006 ps=8.1e-006 ps=8. W-Edit will invoked and we can check the response: 34 . we can simulate it.65 -272194 26.end After saving spice file.6 -272192) VVoltageSource_1 Vdd Gnd DC 5 VVoltageSource_2 Vin Gnd PULSE(0 5 0 5n 5n 95n 200n) .PRINT TRAN V(Vout) .3e-006 $(24.tran 1ns 500ns .95e-006 w=2.9525e-012 pd=9.65 -272199 26.55e-006 ad=5.6 -272197) M2 Vout Vin VDD VDD PMOS25 l=1.55e-006 ad=5.2e-006 $(24.95e-006 w=2.2275e-012 as=3.1e-012 as=4.PRINT TRAN V(Vin) .M1 Vout Vin GND GND_ NMOS25 l=1.

Now we can compare results by using LVS 35 .LVS (Layout Vs Schematic) We got two output files (one from S-Edit and second from L-Edit).

then ok We need to browse spice netlist files for layout netlist and Schematic netlist 36 .Double click on LVS. and file -> new & Select file type-> LVS setup.

Both netlists are equal. we need to run verification as follows & Results can be checked from Verification Window.After including these files. 37 .

or op-amp. A more realistic expression for the output of a differential amplifier thus includes a second term. Some kinds of differential amplifier usually include several simpler differential amplifiers. and a low output impedance. For example.Experiment No. The output of an ideal differential amplifier is given by: Where and are the input voltages and Ad is the differential gain. very high input impedances. bandwidth. Schematic Entry and SPICE simulation of MOS differential amplifier. Many electronic devices use differential amplifiers internally. Note that a differential amplifier is a more general form of amplifier than one with a single input. the output will not be zero. an instrumentation amplifier. An operational amplifier. however. In practice. the gain is not quite equal for the two inputs. The common-mode rejection ratio. is a differential amplifier with very high differential-mode gain. as it would be in the ideal case. output impedance and CMRR. 5: 5. that if and are equal. usually defined as the ratio between differentialmode gain and common-mode gain. a single-ended amplifier results. Theory : A differential amplifier is a type of electronic amplifier that multiplies the difference between two inputs by some constant factor (the differential gain). As differential amplifiers are often used when it is desired to null out noise or biasvoltages that appear at both inputs. for instance. by grounding one input of a differential amplifier. Ac is called the common-mode gain of the amplifier. a fully differential 38 . Common-mode rejection ratio (CMRR): In a perfectly symmetrical differential amplifier. indicates the ability of the amplifier to accurately cancel voltages that are common to both inputs. Determination of gain. a low common-mode gain is usually considered good. This means. Ac is zero and the CMRR is infinite.

as well as for signal amplification applications. or an isolation amplifier are often built from several op-amps. an instrument amplifier. where one input is used for the input signal. a common arrangement for implementing a differential amplifier is the long-tailed pair. the other for the feedback signal. Design : In S-Edit. draw the circuit as shown below. A differential amplifier is used as the input stage emitter coupled logic gates.amplifier. Differential amplifiers are found in many systems that utilise negative feedback. which is also usually found as the differential element in most op-amp integrated circuits. A common application is for the control ofmotors or servos. Convert the schematic to symbol 39 . In discrete electronics.

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create a symbol for op-amp as below. 41 .Using the lines for drawing. Make the connections accordingly.

Vpwr and Vpwr/2 are the instance name of the voltage souces. bandwidth. Now place the spice commands for finding out the gain. 42 .Again create a symbol for the above circuit and make the connections accordingly.

Simulation setup Then click run simulation 43 .

44 .Gain . Frequency and Bandwidth can be viewed from simulation window above. The following schematic shows 10 bit VCO. 7th Experiment is 10 Bit Number Controlled Oscillator. And waveforms can be viewed from w-Edit 6th Experiment is already shown in the Tanner working Flow. By changing the values of D0 – D9 the input pulse applied varies accordingly.