You are on page 1of 7


ASIC interv iew Question & Answer: ASIC Gate



Next Blog

Create Blog

Sign In

ASIC interview Question & Answer

A blog to collect the interview questions and answer for ASIC related positions

Verilog Simulation & Test

Verilog Simulator with automatic test bench generation.

Showing posts with label ASIC Gate. Show all posts Friday, January 29, 2010

ASIC Gate Interview Questions Part#3

1) What is antenna violation & ways to prevent it? Answer: During the process of plasma etching, charges accumulate along the metal strips. The longer the strips are, the more charges are accumulated. If a small transistor gate connected to these long metal strips, the gate oxide can be destroyed (large electric field over a very thin electric) , This is called as Antenna violation. The ways to prevent is , by making jogging the metal line, which is at least one metal above the layer to be protected. If we want to remove antenna violation in metal2 then need to jog it in metal3 not in metal1. The reason being while we are etching metal2, metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge to gate. When we laydown metal3, the remaining portion of metal got charge added to metal3. This is called accumulative antenna effect. Another way of preventing is adding reverse Diodes at the gates. It's true that the diode will 100% solve your "violation" but watch out that, in certain conditions, the leakage this diode will have could actually kill your circuit... Conclusion... As always, this is a trade of... additional interview-questions-and-answers

VLSI Design Courses

Find Top VLSI Institutes in India. Get Info on Courses,Admission,Fees.
www.Shik /VLSI-D

Bonds Investment
Enjoy Higher Returns with the help of our Insights & Research reports!
rse e liance Se curit

Confused by choice?
Stop Thinking. Start Investing. Invest in a basket of4 select funds
scripbox .com

Financial Advise
Learn how to increase your cash flow. Get to know your options
the financialadvice .wordpr

Posted by Roy Chan at 11:13 PM Labels: ASIC Gate

No comments:

ASIC Flow (1)


ASIC interv iew Question & Answer: ASIC Gate

ASIC Gate (3) ASIC Logic (4) ASIC SystemVerilog (10) ASIC timing (2) ASIC Verification (1) C++ (2) Design Complier (1) M emory Interface (1) Networking (2) perl (9) PLL (1) Previous Interview Questions (1) PrimeTime (1) SVA (2) Verilog Interview Questions (6)

vlsi design
Daily news, design technology Application notes & more, All Free

Wednesday, January 13, 2010

Blog Archive
2010 (49)
November (1) October (2) June (2) May (2) April (7) February (12) January (23) ASIC Gate Interview Questions Part#3 Asic Flow Prime Time Questions Design Constraints and Synthesis Questions CAM related Questions Network Questions & Answer Basic OPP questions, SystemVerilog Interview Quest... System Verilog Interview Questions 2 Clock Domain Crossing Timing Q&A Ethernet Questions Memory Interface Questions ASIC Timing Interview Questions ASIC Logic Interview Questions Part #4 ASIC Gate Interview Questions Part #2 ASIC Logic Interview Questions Part # 3 ASIC Logic Interview Questions Part # 2
asic-interv Gate

ASIC Gate Interview Questions Part #2

1) Deriving the vectors for the stuck at 0 and stuck at 1 faults.

A line l is stuck at a fixed logic value v (v {0,1}), denoted by l/v;

(we say also: a line has a fault stuck-at-1 (s-a-1) or stuck-at-0 (s-a-0); examples:

a short between ground (s-a-0) or power (s-a-1) and a signal line; an open on a unidirectional signal line; any internal fault in the component driving its output that it keeps a constant value;

The detectable error can be tested by applying different vectors to the circuit. The combination logic will pass the errors if there's any stack-at-1 or stack-at-0 errors.

Some errors could not be detectable because the error could not passed to the result logic. It need additional tests to catch this errors.

The testing based on stuck at fault model is aided by several things: 1) A test developed for a single stuck at fault often finds a large number


ASIC interv iew Question & Answer: ASIC Gate

ASIC Logic Interview Questions Part # 1 Verilog Interview Question Part # 5 Verilog Interview Questions Part #4 Verilog Interview Questions Part #3 Verilog Interview Questions Part #2 Verilog Interview Questions Part #1 ASIC Gate Interview Questions Part #1

of other stuck at faults. 2) A series of tests for stuck at faults will often, purely by serendipity, find a large number of other faults, like the stuck-open faults. This is sometimes called "windfall" fault coverage. 3) Another type of testing called IDDQ testing measures the way the power supply current of a CMOS integrated circuit changes, when a small number of slowly changing test vectors are applied. Since CMOS draws a very low current when its inputs are static, any increase in that current indicates a potential problem.

2) minimize a boolean expression:

Visitor's counter
Use Karnaugh Maps to minimize the logic.
Visitor Counter

For example:

About Me
Roy Chan Specialties in ASIC Design and Verification from front-end to backend activities, including RTL coding, verification (testbench development, testcase generation and test regression), logic synthesis, static timing analysis, Place and route, power analysis, ECO and final tapeout process. Currently, I am still looking for a new career. View my complete profile

3) What's the latchup effect? Latchup is a term used in the realm of integrated circuits (ICs) to describe a particular type of short circuit which can occur in an improperly designed circuit. More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part and possibly even leading to its destruction due to overcurrent. A power cycle is required to correct this situation.

There was an error in this gadget

asic-interv Gate


Preventing latchup Fab/Design Approaches 1. Reduce the gain product b1 x b1 move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces gain beta2 also > reduces circuit density buried n+ layer in well reduces gain of Q1 2. Reduce the well and substrate resistances, producing lower voltage drops higher substrate doping level reduces Rsub reduce Rwell by making low resistance contact to GND guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic resistances.

Systems Approaches 1. Make sure power supplies are off before plugging a board. A "hot

plug in" of an unpowered circuit board or module may cause signal pins to see surge voltages greater than 0.7 V higher than Vdd, which rises more slowly to is peak value. When the chip comes up to full power, sections of it could be latched. 2. Carefully protect electrostatic protection devices associated with I/O pads with guard rings. Electrostatic discharge can trigger latchup. ESD enters the circuit through an I/O pad, where it is clamped to one of the rails by the ESD protection circuit. Devices in the protection circuit can inject minority carriers in the substrate or well, potentially triggering latchup. 3. Radiation, including x-rays, cosmic, or alpha rays, can generate electron-hole pairs as they penetrate the chip. These carriers can contribute to well or substrate currents. 4. Sudden transients on the power or ground bus, which may occur if large numbers of transistors switch simultaneously, can drive the circuit into latchup. Whether this is possible should be checked through simulation.
Posted by Roy Chan at 11:26 PM Labels: ASIC Gate No comments:

Wednesday, January 6, 2010

ASIC Gate Interview Questions Part #1

Here are the basic interview questions and answer from my previous experience and other source. 1) What is the difference between a latch and a flip lop. For the same input, how would the output look for a latch and for a flip-flop. Latch is a level-sensitive "sequential" element. The output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes. It's faster than Flip-flop, it takes less gates to implemented ( less area). But it's sensitive to glitches on enable pin. It also can be clocked or clock less. Flip-flop is a edge sensitive "sequential" element. Flip flop will store the input only when there is a rising or falling edge of the clock. FF is immune to glitches. D-FF is built from two latches. They are in master slave configuration. 2) What's finite state machines? A finite state machine(FSM), is a model of behavior composed of a finite number of states, transitions between those states, and actions. It is similar to a "flow graph" where we can inspect the way in which the logic runs when certain conditions are met. They are two types of FSM. Mealy Machine and Moore Machine:


ASIC interv iew Question & Answer: ASIC Gate

Moore Machines uses only entry actions and output depends on the state. Mealy Machines uses only input actions and output depends on the input and the state. For more detail, please check this link

3) Explain the differences between "direct Mapped", "fully Associative" and "Set Associative" caches. Answer: If each block has only one place it can appear in the cache, the cache is said to be direct mapped. The mapping is usually (block-frame address) modulo (number of blocks in cache). If a block can be placed anywhere in the cache, the cache is said to be fully associative. If a block can be placed in a restricted set of places in the cache, the cache is said to be set associative. A set is a group of two or more blocks in the cache. A block is first mapped onto a set, and then the block can be placed anywhere within the set. The set is usually chosen by bit selection; that is, (block-frame address) modulo (number of sets in cache). If there are n blocks in a set, the cache placement is called n-way set associative.

4) Design a four-input NAND gate using only two-input NAND gates.

Answer: Tie the inputs of NAND gate together to get an inverter. The result is as following:

asic-interv Gate


Posted by Roy Chan at 9:24 AM Labels: ASIC Gate

1 comment:

Home Subscribe to: Posts (Atom)

Search This Blog