Basis steps to develop the VLSI Program

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Basis steps to develop the VLSI Program

Attribution Non-Commercial (BY-NC)

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Course 2IN35 Course: Kees van Berkel Rudolf Mak Lab: c.h.v.berkel@tue.nl r.h.mak@tue.nl

www:

http://www.win.tue.nl/~cberkel/2IN35/

Lecture 1

Introduction

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to acquire insight in the description, design, and optimization of fine-grained parallel computations; to acquire insight in the (future) capabilities of VLSI as an implementation medium of parallel computations; to acquire skills in the design of parallel computations and in their implementation on FPGAs.

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Contents

Massive parallelism is needed to exploit the huge and still increasing computational capabilities of Very Large Scale Integrated (VLSI) circuits: we focus on fine-grained parallelism (not on networks of computers); we assume that parallelism is by design (not by compilation); we draw inspiration from consumer applications, such as digital TV, 3D TV, image processing, mobile phones, etc.; we will use Field Programmable Arrays (FPGA) as finegrained abstraction of VLSI for practical implementation.

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FPGA

XC2VP30

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Notebook Exceed (can be obtained through the software distribution of the university) Access to UNIX server Dept. W&I (can be obtained through BCF, HG floor 8) Lab work is by teams of two students. Have FPGA tools (SW) installed on your machine by Feb 28

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date Feb 7 class | lab 2 | 0 hours 2 | 0 hours subject (provisional) introduction, DSP representations, bounds pipelining, retiming, transposition, J-slow, unfolding no lecture (carnaval) (have FPGA tools installed) 2 | 0 hours 1 | 3 hours 2 | 2 hours 1 | 3 hours 1 | 3 hours 1 | 3 hours unfolding (cntd), look-ahead, strength reduction Introductions FPGA, Verilog, Lab (A1) systolic computation (A1) folding; FPGAs: pipelining, retiming (A2) DSP processors; FPGAs: parallelism, strength reduc. (A3) FPGAs: sample-rate conversion (A4) 2x no lecture (examinations) 1 | 3 hours 1 | 3 hours FPGAs: video scaler (A5); hand-in report A3 FPGAs: video scaler (A5 cntd) deadline final report A4, A5

May 22

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Your course grade is based on:

the quality of your programs/designs your final report on the design and evaluation of these programs (guidelines will follow) a concluding discussion with you on the programs, the report and the lecture notes intermediate assignments

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First half of VLSI programming course is based on:

Keshab K. Parhi. VLSI Digital Signal Processing Systems, Design and Implementation. Wiley Inter-Science 1999. This book is recommended.

Mandatory reading: Keshab K. Parhi. High-Level Algorithm and Architecture Transformations for DSP Synthesis. Journal of VLSI Signal Processing, 9, 121-143 (1995), Kluwer Academic Publishers.

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Introduction

VLSI FPGAs

Machine Intellligence Bee, SKA, SETI Digital Signal Processing (Software Defined Radio)

Parhi, Chapters 1, 2

DSP Representation Methods Iteration bounds

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Power dissipation 130 W (107 W typical) 3 Levels of Cache: 16k + 16k, 256K, 6M CMOS technology: 130nm Clock frequency1.5 GHz 7,877 pins, 95 percent of the are for power 1,322 Specint base2000 for a single processor! Next generation: 1.7GHz and 9MByte cache!

Rusu et. al [Intel], Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache, IEEE Micro April 2004, vol. 24, Issue 2, pp. 10-18.

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Moores Law

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Every 2 generations of IC technology (6 years) device feature size chip size clock frequency number of i/o pins DRAM capacity logic-gate density 4 x 0.5 x 2x 2x 2x 16 x (no longer true)

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consensus on the best current estimate of the industrys research and development needs out to a 15-year horizon.

universities, governments, and other research providers/funders.

made at all levels and has helped channel research efforts to areas that most need research breakthroughs.

Involves over 1000 technical experts, world wide. a self-fulfilling prophecy? or wishful thinking?

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ST-Ericsson confidential

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ST-Ericsson confidential

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ST-Ericsson confidential

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1000

300x 20x

100

Virtex-II Pro

10 200x10x

Spartan-3

1 1x 1/91 1/92 1/93 1/94 1/95 1/96 1/97 1/98 1/99 1/00 1/01 1/02 1/03 1/04

Year

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500MHz clock

450MHz PowerPC

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brain power equivalent per $1000 of computer

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... the ultimate exploration tool ... and the ultimate software defined radio

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antenna surface: 1 km2 (sensitivity 50) large physical extent (3000+ km) wide frequency range: 70 MHz 30 GHz full design by 2010; phase 1: 2017;

phase 2: 2022

1000- 1500 dishes (15m) in the central 5 km (2000-3000 total) + dense and/or sparse aperture arrays connected to a massive data processor by an optical fibre network

Software Defined Radio Astronomy computational load (on-line) 1 exa MAC power budget = 30 MW 30 pJ/MAC allall-in

28 MPSoC -- 2010, June 30

(1018 MAC/s)

References

Chip fotos:

http://www-vlsi.stanford.edu/group/chips.html

ITRS Roadmap

http://www.itrs.net/Links/2005ITRS/ExecSum2005.pdf

http://www.jetpress.org/volume1/moravec.htm

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http://bwrc.eecs.berkeley.edu/Research/BEE/ http://seti.berkeley.edu/casper/papers/BEE2_ska2004_poster.pdf http://www.skatelescope.org/

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10G 1G

Sample rate

# instructions/sample

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speech (de-)coding speech recognition speech synthesis speaker identification Hi-fi audio en/decoding noise cancellation audio equalization ambient acoustic

emulation.

sound synthesis echo cancellation modem: (de-)modulation vision image (de-)compression image composition beam cancellation spectral estimation etc.

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by removing unwanted frequencies.

y (i ) = h(k ) x(i k ) = h(n) * x(n)

k =0 N 1

where

x is the input sequence y is the output sequence h is the impulse response (filter coefficients) N is the number of taps (coefficients) in the filter

response.

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y (i) =

M 1 k =1

k =0

N 1

response,as well as previous outputs

minimize the distance between the filter output and the desired signal.

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The Discrete Fourier Transform (DFT) supports frequency domain (spectral) analysis:

2 j =e N

y (k ) = WN nk x(n)

n =0

N 1

WN

j = 1

x is the input sequence in the time domain (real or complex) y is an output sequence in the frequency domain (complex)

The Inverse Discrete Fourier Transform (IDFT) is computed as

N 1 k =0

x ( n ) = WN

nk

y (k ), for n = 0, 1, ... , n - 1

The Fast Fourier Transform (FFT) and its inverse (IFFT) provide an efficient method for computing the DFT and IDFT.

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The Discrete Cosine Transform (DCT) and its inverse IDCT are frequently used in video (de-) compression (e.g., MPEG-2):

N 1

2 x ( n) = N

N 1 k =0

e(k ) cos[

where e(k) = 1/sqrt(2) if k = 0; otherwise e(k) = 1. A N-Point, 1D-DCT requires N2 MAC operations.

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recognition, motion estimation, and coding.

the input vector x is minimum.

N 1 i =0

1 d= N

N 1 i =0

| x(i) rk (i) |

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1 d= N

[ x(i ) rk (i )]2

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Matrix computations are typically used to estimate parameters in DSP systems.

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Computation Rates

the equation:

where

RC = RS N S

Rc is the computation rate Rs is the sampling rate Ns is the (average) number of operations per sample

and a 2-D FIR has NS = 2N2.

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Signal type Speech Music Frequency # taps 8 kHz 48 kHz N =128 N =256 Performance 20 MOPs 240 MOPs

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block diagram data flow graph signal flow graph LTI systems signal processing general

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Linear Systems

input x, output y: discrete system:

x(n)

results in

y(n)

c1 x1(n) + c2 x2(n)

c1 y1(n) + c2 y2(n)

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input x, output y:

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x(n)

LTI System A

f(n)

LTI System B

y(n)

is equivalent to

x(n)

LTI System B

g(n)

LTI System A

y(n)

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graph to a particular state

Example of a

multi-rate DFG:

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Iteration period

Iteration period = the time required for the execution of one iteration of the SFG

a

Example:

x(n)

Let

y(n-1)

Iteration period = Tm+Ta = 14 = minimum sample period Ts; that is: Ts Tm+Ta

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combinational functions 3 2 1 4

1 2 3

inputs

outputs

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DSP references

Keshab K. Parhi. VLSI Digital Signal Processing Systems, Design and Implementation. Wiley Inter-Science 1999.

Richard G. Lyons. Understanding Digital Signal Processing (2nd edition). Prentice Hall 2004.

John G. Proakis and Dimitris K Manolakis. Digital Signal Processing (4th edition), Prentice Hall, 2006.

Simon Haykin. Neural Networks, a Comprehensive Foundation (2nd edition). Prentice Hall 1999.

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Hennessy and Patterson, Computer Architecture, a Quantitative Approach. 3rd edition. Morgan Kaufmann, 2002.

Phil Lapsley, Jeff Bier, Amit Sholam, Edward Lee. DSP Processor Fundamentals, Berkeley Design Technology, Inc, 1994-199

Jennifer Eyre, Jeff Bier, The Evolution of DSP Processors, IEEE Signal Processing Magazine, 2000.

Kees van Berkel et al. Vector Processing as an Enabler for Software-Defined Radio in Handheld Devices, EURASIP Journal on Applied Signal Processing 2005:16, 2613-2625.

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Parhi, Chapters 2, 3

Representations of DSP algorithms Data flow graphs Loop bounds and iteration bounds Pipelining of digital filters Parallel processing Retiming techniques

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