Chng 7 T chc b x l

T chc b x l trung tm B thanh ghi ng i d liu (Datapath) T chc One-Bus T chc Two-Bus, Three-Bus Din tin thi hnh lnh m my B iu khin X l ngt (Interrupt Handling) K thut ng dn (Pipeline)

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7.1. T chc b x l trung tm

i hi bn trong CPU:
Tm np lnh (Fetch Instruction) Din gii lnh (Interpret Instruction) Tm np d liu (Fetch data) X l d liu (Process data) Ghi d liu (Write data)

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Cu trc bn trong ca CPU

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7.2. B thanh ghi

Thanh ghi mc ch chung Thanh ghi c mc ch c bit Chiu di ca thanh ghi S lng thanh ghi Thanh ghi truy cp b nh
Thanh ghi d liu b nh (memory data register - MDR) Thanh ghi a ch b nh (memory address regiater MAR)

Thanh ghi chuyn ti lnh

B m chng trnh (program counter PC) Thanh ghi lnh (instruction register IR)

Thanh ghi t trng thi ca chng trnh (program status word PSW).
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Cc thanh ghi h 80x86

8 thanh ghi mc ch chung: SI (source index), DI (destination index), SP (stack pointer) v BP (base pointer). Thanh ghi segment Thanh ghi m chng trnh PC, thanh ghi lnh IR v thanh ghi c trng thi

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7.3. ng i d liu (Datapath)

ng i d liu gm c
b logic-s hc (ALU: Arithmetic and Logic Unit), cc mch dch, cc thanh ghi cc ng ni kt cc b phn trn

Nhim v chnh ca phn ng i d liu

c cc ton hng t cc thanh ghi tng qut thc hin cc php tnh trn ton hng ny trong ALU lu tr kt qu trong cc thanh ghi tng qut

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T chc One-Bus

Mt BUS ch c th s dng mt d liu di chuyn trong mt chu k ng h => mt php ton c hai ton hng cn hai chu k ng h.

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T chc Two-Bus

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Three-Bus
T chc ng truyn d liu dng three-bus

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7.4. Din tin thi hnh lnh m my(CPU instruction cycle)

Vic thi hnh mt lnh m my c th chia thnh 5 giai on
c lnh (IF: Instruction Fetch) Gii m lnh (ID: Instruction Decode) Thi hnh lnh (EX: Execute) Thm nhp b nh trong hoc nhy (MEM: Memory access) Lu tr kt qu (RS: Result Storing).

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c lnh
c lnh (fetch instruction):
D liu trong PC c load vo MAR: MAR PC Gi tr trong thanh ghi PC tng ln 1: PC PC+1 Kt qu ca lnh c t b nh, d liu c load vo MDR: MDRM[MAR] D liu trong MDR c load vo IR: IR MDR

Th t thc hin lnh theo thi gian i vi loi one-bus:

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c lnh - Gii m lnh

Th t thc hin lnh theo thi gian i vi loi two-bus(a):
t0: MAR PC; A PC + 4 t1: MDR M[MAR] ; PC A t2: IR MDR

Gii m lnh v c cc thanh ghi ngun:

Opcode

Ri

Rj
Thanh ghi no? R1, R2 hay R8,

Lnh g? +, -, x, :, AND,
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Thi hnh mt lnh s hc n gin

V d: ADD R1,R2,R0 Cc bc thi hnh lnh:

Trong cu trc one-bus v two-bus

Cu trc three bus thc hin bao nhiu chu k

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Thi hnh mt lnh s hc n gin

V d lnh: ADD R0,X

i vi cu trc one-bus

Two-bus

Three-bus

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7.5. B iu khin
B iu khin mch in t
nguyn l hot ng nh mt mch tun t hay Automate (mch t ng ha) trng thi hu hn u im : ch c mt s hu hn cc trng thi ti u to ra ch nhanh cho tc v

B iu khin vi chng trnh

dng mt vi chng trnh lp sn nm trong b nh iu khin (control memory) khi ng dy vi tc v theo yu cu. dng rng ri trong cc b x l CISC

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B iu khin (tt)
s khi mt b iu khin mch in t c bn

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B iu khin in t
V d iu khin thc hin mt lnh: ADD R0,R1,R2
Cc bc thc hin

Ci t phn cng

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B iu khin in t (tt)
VD lnh ADD R0,R1,R2 vi cu trc one-bus databath

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B iu khin in t (tt)
Yu cu tm ra biu thc logic cho tn hiu iu khin VD: gi s b lnh c 3 lnh Inst-x, Inst-y, Inst-z v A,B,C,D,R,F,G,H l cc ng iu khin.

A = Inst-x * t1 + Inst-z * t1

B = Inst-x * t0 + Inst-y * t2
C = Inst-x * t2 + Inst-x * t2 + + Ints-y * t2 + Inst-z * t1

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B iu khin in t (tt)
S trng thi thc hin lnh

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B iu khin vi chng trnh

Vi lnh chiu ngang v chiu dc

VD: Trong cu trc ng truyn three-bus, gi s c 16 thanh ghi GPR

R0-R15, ALU c 8 php ton (add, sub, multiply, divide, AND,OR, shift left v shift right). Xt format cho vi lnh ADD R0,R1,R2 theo chiu ngang

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Vi lnh chiu ngang v chiu dc

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7.6. X l ngt (Interrupt Handling)

Ngt l mt s kin xy ra mt cch ngu nhin trong my tnh v lm ngng tnh tun t ca chng trnh (ngha l to ra mt lnh nhy) ngt qung c dng cho cc cng vic:
Ngoi vi i hi nhp hoc xut s liu. Ngi lp trnh mun dng dch v ca h iu hnh. Cho mt chng trnh chy tng lnh. Lm im dng ca mt chng trnh. Bo trn s liu trong tnh ton s hc. Trang b nh thc s khng c trong b nh. Bo vi phm vng cm ca b nh. Bo dng mt lnh khng c trong tp lnh. Bo phn cng my tnh b h. Bo in b ct.
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7.6. X l ngt (Interrupt Handling)

Khi mt ngt xy ra, b x l thi hnh cc bc:
1. Thc hin xong lnh ang lm. 2. Lu tr trng thi hin ti. 3. Nhy n chng trnh phc v ngt 4. Khi chng trnh phc v chm dt, b x l khi phc li trng thi c ca n v tip tc thc hin chng trnh m n ang thc hin khi b ngt.

Thc hin cc vi tc v khi ngt

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7.7. K thut ng dn (PIPELINE)

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7.7. K thut ng dn (PIPELINE)

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7.7. K thut ng dn (PIPELINE)(tt)

chu k xung nhp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Chui lnh

lnh i
lnh i + 1 lnh i + 2

IF ID EX MEM

RS
IF ID EX MEM RS IF ID EX MEM RS

lnh i + 3 lnh i + 4

IF

ID EX MEM

RS IF ID EX MEM RS

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7.7. K thut ng dn (PIPELINE)(tt)

Thc hin lnh trong k thut pipeline:

Mt s rng buc trong pipeline

Cn phi c mt mch in t thi hnh mi giai on ca lnh Phi c nhiu thanh ghi khc nhau dng cho cc tc v c v vit Cn phi gii m cc lnh mt cch n gin Cn phi c cc b lm tnh ALU hu hiu c th thi hnh lnh s hc di nht
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Nhng kh khn trong k thut ng dn

Kh khn do cu trc
Do thiu cc ti nguyn : ALU, PC, IR,

Kh khn do iu khin
Cc lnh khng thc thi 1 cch tun t lin quan n cc lnh nhy (nhy c iu kin, v nhy khng c iu kin).

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Nhng kh khn trong k thut ng dn

Kh khn do s liu
v d trng hp cc lnh lin tip sau: Lnh 1: ADD R1, R2, R3 Lnh 2: SUB R4, R1, R5 Lnh 3: AND R6, R1, R7 Lnh 4: OR R8, R1, R9

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Cch khc phc

Kh khn do cu trc
Gn thm cc thnh phn

Kh khn do iu khin
ng bng k thut ng dn ngng li lnh th i + 1, nu lnh i l lnh nhy. Lnh nhy khng iu kin chn 1 lnh sau lnh nhy. Lnh nhy c iu kin.

Kh khn do s liu
To mt b phn cng a d liu t ng ra ALU v trc tip cc thnh ghi ng vo.

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