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Verilog Language Concepts

Adapted from Z. Navabi


Portions Copyright Z. Navabi, 2006

CSE 467

Verilog Digital System Design

Verilog Language Concepts

Characterizing Hardware Languages


Timing Concurrency Timing and concurrency example

Module Basics

Code format Logic value system Wires and variables Modules Module ports Names Numbers

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Verilog Digital System Design

Verilog Language Concepts

Module Basics (cont.)


Arrays Verilog operators Verilog data types Array indexing

Verilog Simulation Model


Continuous assignments Procedural assignments

CSE 467

Verilog Digital System Design

Verilog Language Concepts

Compiler Directives

timescale default-nettype include define ifdef, else,endif ifdef, else, unconnected-drive celldefine, endcelldefine celldefine, resetall

CSE 467

Verilog Digital System Design

Verilog Language Concepts

System Tasks and Functions


Display tasks File I/O tasks Timescale tasks Simulation control tasks Timing check tasks PLA modeling tasks Conversion functions for reals Other tasks and functions

Summary

CSE 467

Verilog Digital System Design

Characterizing Hardware Languages


Timing and concurrency are the main characteristics of hardware description languages. Timing is associated with values that are assigned to hardware carriers. Concurrency refers to simultaneous operation of various hardware components.

CSE 467

Verilog Digital System Design

Characterizing Hardware Languages


Characterizing Hardware Languages Timing Concurrency

Timing & Concurrency Example


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Timing
Characterizing Hardware Languages Timing Timing Concurrency

Timing & Concurrency Example


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Timing
Transfer of data is done through wires or busses and some of delays are associated with transfer of data through wires. Variables in Verilog may be used for representation of wires and variable assignments can include timing specification.

CSE 467

Verilog Digital System Design

A more accurate assignment:

A sharp-sign An assign statement (#) followed on the drives the signal by a number specifies the left-hand side ofthe delay of the equal signInleft the the 6 ns with hand Because of side this simple assign #6 n = ~b; signal. boolean assignmentinverter in expression on delay of Glitches assign #3like this:a & b; m = The circuit can be written itsthat may appear on b right. path from second assign #3 p = n & c; to w a different w due to 6 ns glitch assign #2 w2 = m | p; delay appears on w.to paths from b assign w1 = a & b | c & ~b; ~b; w are not considered.
Td = 3ns

Timing

a b c
n

m
Td = 6 ns T d = 3ns

Td =2 ns

w p

An AND-OR Circuit
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Timing

When b changes from 1 to 0 the final value of w remains at 1. However, because of the inverter delay in forwarding a 1 to the output, a 6 ns glitch appears on w.

w1, which is the result w1, of the single assign Output Glitch statement, does not show the delay

w2 shows both propagation delays and glitches that may occur on the w output of circuit

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Concurrency
Characterizing Hardware Languages Timing Concurrency Concurrency

Timing & Concurrency Example


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Concurrency
Concurrency is an essential feature of any language for description of hardware. Functionality of a hardware system is described by concurrent subcomponents or by a program in a sequential manner. By using concurrent sub-components Verilog simulator makes us think that simulation of components is being done concurrently.

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Verilog Digital System Design

13

Concurrency
assign #6 assign assign assign n = ~b; #3 m = a & b; #3 p = n & c; #2 w2 = m | p;
Regarded gates are The as concurrent. The order in which these concurrently active. statements appear in a We cannot decide on a concurrent body of Verilog pre-determined order in is not important. which gates of this circuit perform their operations.

a b c
An AND-OR Circuit

Td = 3ns

m
Td = 6 ns Td = 3ns n

T d =2ns

w p

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Verilog Digital System Design

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Timing & Concurrency Example


Characterizing Hardware Languages Timing Concurrency

Timing & Concurrency Example


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Timing & Concurrency Example


Module header declares inputs and outputs of circuit.

`timescale 1ns/100ps

module FullAdder (input a, b, ci, output co, s); (input ci, assign #4 co = a & b | a & ci | b & ci; ci; assign #3 s = a ^ b ^ ci; ci; endmodule The two assign
Propagation Delay Full Adder Concurrent Description of Assignment

Because of the delay values, statements drive s if an input change causes (sum) and cos (carryboth outputs to change, out) outputs of changes before co does. circuit.

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Verilog Digital System Design

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Timing & Concurrency Example


`timescale 1ns/100ps Declaration and module FullAdderTester; FullAdderTester; initialization of reg a = 0, b = 0, ci = 0; variables, wires, wire co, s; and constants parameter tlimit = 500; FullAdder MUT (a, b, ci, co, s); ci, ................................ Instantiation statement to instantiate the full ................................ Fulladder Tester Procedural Description

adder that is the module under test

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on the outside, but has Timing &body. Concurrency Example a procedural Checks the simulation time and if it exceeds always begin tlimit it stops the if ($time >= tlimit) $stop; tlimit) $stop; simulation. else begin After a wait of 17ns input #17; a is complemented a = ~a; #13; ci = ~ci; ~ci; Applies test data to the ports of the #19; circuit being tested. b = ~b; end end endmodule

A concurrent structure

Fulladder Tester Procedural Description (Continued)


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Module Basics
Now we are going to see: How modules are developed How names, numbers and operators are used

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Module Basics
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

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Code Format
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

Code Format
Verilog code is free format. Spaces and new lines are served as separators. It is case sensitive. Language keywords use lowercase characters. A comment designator start with // makes the rest of line comment. The symbols /* */ bracket the section of code which is in between as a comment.

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Verilog Digital System Design

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11

Logic Value System


Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

Logic Value System


Bit type, or bits of vectors or arrays, of Verilog wires and variables take the 4-value logic value system. Values in this system are 0, 1, Z and X. 0, The values 0 and 1 have Three modes: Forcing, Resistive and Forcing, Capacitive. Capacitive. The Z value represents an undriven, high impedance value. undriven, The X value represent a conflict in multiple driving values, an unknown or value of a variable not initialized.

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12

Logic Value System


0: 1:
X or x : Z or z :
Logic Values and Examples
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0 1 X 0 1 0 z

x 0

Wires and Variables


Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

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Wires and Variables


Wires and Variables: net: represents a wire driven by a hardware structure or output of a net: gate. reg: represents a variable that can be assigned values in behavior reg: description of a component in a Verilog procedural block.

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Modules
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

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Modules
Module is the main structure of definition of hardware components and testbenchs. testbenchs. Begins with module keyword and end with endmodule. endmodule. Immediately following the module keyword, port list of the module appears enclosed in parenthesis.

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Modules
`timescale 1ns/100ps module FlipFlop (preset, reset, din, input preset, reset, din, clk; clk; output qout; qout; reg qout; qout; always @ (posedge clk) begin (posedge clk) if (reset) qout <= #7 0; else if (preset) qout <= #7 1; else qout <= #8 din; end endmodule Separate Port Declarations Statements
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clk, qout); clk, qout);


Ports are only listed in the port list and declared as separate input and output ports inside the body of the Flip-Flop module.

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Module Ports
Module Basics Code Format Wires and Variables Logic Value System Module Module Ports Ports

Modules

Names

Numbers

Arrays
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Verilog Data Types

Array Indexing
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Verilog Digital System Design

Module Ports
Inputs and outputs of a model must be declared as: input output inout By default, all declared ports are regarded as nets and the default net nets type is used for the ports. Ports declared as output may be declared as reg. reg. This way they can be assigned values in procedural blocks. An inout port can be used only as a net. To assign values to an inout net. port in procedural bodies, a reg corresponding to the port must be declared and used. For an output, a reg specification can follow the output keyword in the port list of the module.
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Names
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

Names
A stream of characters starting with a letter or an underscore forms a Verilog identifier. The $ character and underscore are allowed in an identifier. Verilog uses keywords that are all formed by streams of lowercase characters. characters. The names of system tasks and functions begin with a $ character. Compiler directive names are preceded by the ` (back single quote) character. Example: `timescale

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Names
The following are valid names for identifiers: a_name , name1 , _name , Name, Name$ , name55 , _55name , setup, _$name. The following are Verilog keywords or system tasks. $display, default, $setup, $display, default, $setup, begin, tri1, small. begin, tri1, small.

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Verilog Digital System Design

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Numbers
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

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Numbers
Constants in Verilog are integer or real. real. Specification of integers can include X and Z in addition to the standard 0 and 1 logic values. Integers may be Sized: Begins with the number of equivalent bits Unsized: Without the number of bits specification The general format for a sized integers is: number_of_bits base_identifier digits example: 6b101100 6 The base specifier is a single lower or uppercase character b, d, o or h which respectively stand for binary, decimal, octal and hexadecimal binary, decimal, bases.
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Numbers
Optionally, the base-identifier can be preceded by the single character s (or S) to indicate a signed quantity. S) A plus or minus operator can be used on the left of the number specification to change the sign of the number. The underscore character (_) can be used anywhere in a number for grouping its bits or digits for readability purposes.

Real constants in Verilog use the standard format as described by IEEE std 754-1985, the IEEE standard for double precision floatingpoint numbers. Examples: 1.9, 2.6E9, 0.1e-6, 315.96-12.

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Numbers
Number representation
4d5 4d5 8b101 number. 8b101 number. 12h5B_3 12h5B_3 -8b101 -8b101 10o752

Number Representation Examples Explanation

Binary Equivalent

101 101

101 Decimal 5 is interpreted as a Decimal 5 is interpreted as a 4-bit4-bit number. 101 Binary 101 is turned 8-bit Binary 101 is turned into an into an 8-bit number. 10110110011 10110110011 Binary equivalent of hex; underscore is ignored. Binary equivalent of hex;

This underscore is ignored. is the 11111011 11111011 This is the2s complement of the number in the 2scomplement of the above example. 0111101010 Thisnumber in the above example. is the octal 752 with a 0 padded This is the octal 752 with a 0 padded to its left to 10o752 111101010to itself to make it a 10-bit number. make it a 10-bit number. 8hF 8hF 00001111 1111 Hexadecimalis expanded to 8 bits byto Hexadecimal F F is expanded padding zeros to its 8 bits by padding zerosleft. its left. to 12hxA xxxxxxxx1010 HexadecimalXA is expanded to 12 bitsto Hexadecimal XA is expanded by 12hXA xxxxxxxx1010 extending the X. 12 bits by extendingthe leftleft x. 12shA6 Signed 111110100110 This isThis is an 8-bit number treated as a 2s an 8-bit number treated Signed 12shA6 111110100110 complement signed number. as -4shA Signed 0110 The 2s complement (because ofnumber. 2s complement signed theof the The 2s complement (because minus sign) -4shA Signed 0110 a 4-bit A is A is regarded as a minus sign) 4-bit regarded as a signed number. 596 1001010100 signed number. a a positive constant. ThisThis is positive constant. is 596 1001010100
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Numbers
`timescale 1ns/100ps Display Results

Variables a through l are displayb tasksinitialized. $ declared and display the binary values .

module NumberTest; NumberTest; reg [11:0] a = 8'shA6; initial $displayb ("a=", // a=111110100110 reg [11:0] b = 8'sh6A; initial $displayb ("b=", // b=000001101010 reg [11:0] c = 'shA6; initial $displayb ("c=", // c=000010100110 reg [11:0] d = 'sh6A; initial $displayb ("d=", // d=000001101010 reg [11:0] e = -8'shA6;initial $displayb ("e=", -8'shA6;initial // e=000001011010 .............................................. Integer Constants
CSE 467 Verilog Digital System Design

a); b); c); d); e);

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Numbers
................................................... reg [11:0] f = -'shA6; initial $displayb ("f=", f); // f=111101011010 reg [11:0] g = 9'shA6; initial $displayb ("g=", g); // g=000010100110 reg [11:0] h = 9'sh6A; initial $displayb ("h=", h); // h=000001101010 reg [11:0] i = -9'shA6;initial $displayb ("i=", i); -9'shA6;initial // i=111101011010 reg [11:0] j = -9'sh6A;initial $displayb ("j=", j); -9'sh6A;initial // j=111110010110 reg [11:0] k = 596; initial $displayb ("k=", k); // k=001001010100 reg [11:0] l = -596; initial $displayb ("l=", l); // l=110110101100 endmodule Integer Constants (Continued)
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Arrays
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

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Arrays
Verilog allows declaration and usage of multidimensional arrays for nets or regs. nets regs The following declares a_array as a two-dimensional array of 8-bit words: reg [7:0] a_array [0:1023][0:511]; In an array declaration, the address range of the elements of the array comes after the name of the array. Range specifications are enclosed in square brackets. brackets. The size and range specification of the elements of an array come after the net type (e.g., wire) or reg keyword. wire) In the absence of a range specification before the name of the array, an element size of one bit is assumed.

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Arrays
7 // An 8-bit vector reg [7:0] Areg; Areg 0

// A memory of 8 one -bit elements reg Amem [7:0];

Amem

Array Structures Structures


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Arrays
// A two-dimensional memory of one -bit elements reg Bmem [7:0] [0:3]; Bmem

0 7 // A memory of four 8-bit words reg [7:0] Cmem [0:3]; 0 Cmem 3


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Array Structures (Continued) Structures


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Arrays
// A two-dimensional memory of 3-bit elements reg [2:0] Dmem [0:3] [0:4]; 3 4

0 0 Dmem 3

Array Structures Structures


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Verilog Operators
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Verilog Operators Operators

Verilog Data Types

Array Indexing
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Verilog Digital System Design

Verilog Operators
Basic
Arithmetic OPERATION + - * / ** > > = < <= DESCRIPTION Basic arithmetic compare RESULT Multi -bit One-bit

Shift Basic
Equality
Relational

Relational

OPERATION OPERATION Equality


OPERATION !=

DESCRIPTION

DESCRIPTION DESCRIPTION
RESULT

RESULT RESULT

Arithmetic Logical Right

Logical

Case OPERATION !

+ - *>>n / **

Equality not including Z , X

Boolean
Logical

Logical Left Logical

Arithmetic Reduction { } Case Concatenation Right !==>>>n Shift Logical ! {{ Condition LogicalRight&& }} >>n OPERATION Replication Arithmetic Left Left ? : <<n <<<n Logical Conditional ~ & ^ ^~ Bit-wise Arithmetic Right >>>n ~^
^~ ~^

Concat Boolean

> >= < <= == && <<n !=


~&

Zero-fill One-bit Basic arithmetic Equality Shift n places One-bit DESCRIPTION including Z , X

OPERATION

Bit -wise OPERATION ~^ OPERATION^ === & ~& ~

^ ^~

OPERATION

RESULT Equality Zero-fill One-bit Simple logic One-bit Multi-bit not including Z, X Shift n places One-bit Vector logic operation DESCRIPTION RESULT DESCRIPTION RESULT Equality One-bit Perform operation on all bits One-bit Multi-bit Join bits Multi-bit including Z , X DESCRIPTION RESULT Simple logic One-bit Join & Replicate Zero-fill DESCRIPTION RESULT Multi-bit Multi -bit Shift n places Multi-bit Zero-fill If-then-else Multi -bit Multi-bit Shift n places One-bit Vector logic Multi operation -bit DESCRIPTION Multi -bit

compare

Multi-bit Multi-bit RESULT One-bit

Arithmetic Left

<<<n

Reduction

Concat&
Concatenation Replication

~&OPERATION ~ ^ ^~ ~^{ }
{{ }} OPERATION ? :

DESCRIPTION

Perform operation RESULT on all bits -bit Join bits Multi


Multi -bit RESULT Multi -bit

One-bit

Join & Replicate DESCRIPTION If -then-else

Condition
Conditional

Verilog Operations
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Verilog Operators
Verilog Operators Basic Operators Boolean Operators Concatenation Operators
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Equality Operators Shift Operators Conditional Operators


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Verilog Digital System Design

Basic Operators
Verilog Operators Basic Operators Boolean Operators Concatenation Operators
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Equality Operators Shift Operators Conditional Operators


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Verilog Digital System Design

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Basic Operators
Arithmetic Operations in Verilog take bit, vector, integer and real operands. Basic operators of Verilog are +, -, *, / and **. **. An X or a Z value in a bit of either of the operands of a multiplication causes the entire result of the multiply operation to become X. Unary plus (+) and minus () are allowed in Verilog. These operators () take precedence over other arithmetic operators. If any of the operands of a relational operator contain an X or a Z, then the result becomes X.

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Basic Operators
Example
25 * 8b6 25 + 8b7 25 / 8b6 22 % 7 8'b10110011 > 8b0011 4b1011 < 10 4b1Z10 < 4b1100 4b1x10 < 4b1100 4b1x10 <= 4b1x10

Results in
150 32 4 1 1 0 x x x

Examples of Basic Operations


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Equality Operators
Verilog Operators Basic Operators Boolean Operators Concatenation Operators
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Equality Equality Operators Shift Operators Conditional Operators


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Verilog Digital System Design

Equality Operators
Equality operators are categorized into two groups: Logical: Compare their operands for equality (==) or inequality (!=) Return a one-bit result, 0, 1, or Z 1, An X ambiguity arises when an X or a Z occurs in one of the operands. Case: Consider X and Z values in comparing their operands. The result is always 0 or 1.

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Equality Operators
Example
8b10110011 8b1011 4b1100 4b1100 8b1011 8b101X == == == != !== === 8b10110011 8b00001011 4b1Z10 8b100X 8b00001011 8b101X

Results in
1 1 0 1 0 1

Examples of Equality Operations

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Boolean Operators
Verilog Operators Basic Operators Boolean Boolean Operators Operators Concatenation Operators
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Equality Operators Shift Operators Conditional Operators


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Boolean Operators
If an X or a Z appears in an operand of a logical operator, an X will result. The complement operator ~ results in 1 and 0 for 0 and 1 inputs and X for X and Z inputs.

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Boolean Operators
If an X or a Z appears in an operand of a logical operator, an X will result. The complement operator ~ results in 1 and 0 for 0 and 1 inputs and X for X and Z inputs.
&

^~

0
0 0 0 1 0 x 0 1 0 1 1 0 x x x x 0 1 1 0 x x x x

1
1 0 1 1 1 x 1 x 0 x x x x x x x

X
x x 1 x x x x x 0 x x x x x x x

Z
x x 1 x x x x x

0 1 X Z

Bit-by-bit Bitwise and Reduction Operators


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Boolean Operators

Complement reduction operations (~&, ~|, and ~^) perform reduction (~&, ~|, ~^) first and then complement the result.
Example
8b01101110 && 4b0 8b01101110 || 4b0 8b01101110 && 8b10010001 ! (8b10010001) 8b01101110 & 8bxxzz1100 8b01101110 | 8bxxzz1100 ~& (4b0xz1) ~| (4b0xz1)

Results in
0 1 1 1 8b0xx01100 8'bx11x1110 1 0

Logical, Bit-wise, and Reduction


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Shift Operators
Verilog Operators Basic Operators Boolean Operators Concatenation Operators
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Equality Operators Shift Shift Operators Operators Conditional Operators


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Shift Operators

Logical shift operators (>> and << for shift right and left) fill the (>> vacated bit positions with zeros. Fill values for arithmetic shift operators depend on the type of their results being signed or unsigned .

Example
8b0110_0111 << 3 8b0110_0111 << 1bz Signed_LHS = 8b1100_0000>>>2

Results in
8b0011_1000 8bxxxx_xxxx 8b1111_0000

Shift Operators

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Concatenation Operators
Verilog Operators Basic Operators Boolean Operators Concatenation Operators
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Equality Operators Shift Operators Conditional Operators


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Concatenation Operators

The notation used for this operator is a pair of curly brackets ({...}) ({...}) enclosing all scalars and vectors that are being concatenated. If a is a 4-bit reg and aa is a 6-bit reg, the following assignment places 1101 in a and 001001 in aa: aa:
{a, aa} = 10b1101001001 aa} 10

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Concatenation Operators

If the a and aa registers have the values assigned to them above, and aaa is a 16-bit reg data type, then the assignment,
aaa = {aa, {2{a}}, 2b11} {aa, 2

puts 001001_1101_1101_11 in aaa. aaa.


{a, 2{b,c}, 3{d}} is equivalent to: {a, b, c, b, c, d, d, d} {2b00, 3{201}, 2b11} results in: 10b0001010111 {2 3{2 2 10

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Conditional Operators
Verilog Operators Basic Operators Boolean Operators Concatenation Operators
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Equality Operators Shift Operators Conditional Operators


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Conditional Operators

expression1 ? expression2 : expression3


If expression1 is true, then expression2 is selected as the result of the operation; otherwise expression3 is selected.

assign a = (b == c)? 1 : 0;

If expression1 is X or Z, both expressions 2 and 3 will be evaluated, and the result becomes the bit-by-bit combination of these two expressions.

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Conditional Operators
Example
1 ? 4b1100 : 4b|ZX0 0 ? 4b1100 : 4b1ZX0 X ? 4b1100 : 4b1ZX0
Conditional Operators

Results in
4b1100 4b1ZX0 4b1XX0

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Precedence of Operators
Highest + -!~ ** */% +<< >> <<< >>> < <= > >= == ! = === !== &~& ^ ^~ ~^ ~ &&

Operator Precedence
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?: Lowest
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Precedence of Operators

&

& &

B && C

+ +

&

&&

Precedence Examples

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Verilog Data Types


Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
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Verilog Operators

Verilog Data Types

Array Indexing
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Verilog Data Types


Verilog Data Types

Net Declarations

Reg Declarations

Signed Data
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Parameters

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Net Declarations
Verilog Data Types Net Declarations

Reg Declarations

Signed Data
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Parameters

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Net Declarations
Types wire and tri, wand and triand, and wor and trior are equivalent. tri, triand, Types supply0 and supply1 are used for declaring signal names for supply voltages. The trireg net type declares three-state capacitive signals.

Other net types (wire, wand and wor or their equivalents, tri, triand (wire, tri, and trior ) declare state signals that allow multiple driving sources.

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Net Declarations
This statement declares wires used between gates or Boolean expressions representing logic structures.
wire w, n, m, p;

By default, ports of a module are net of wire type. The Z value is the weakest and is overridden by non-Z values from other driving sources.

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Net Declarations
Driving a wire with multiple 0 and 1 conflicting values resolves in the X value for the wire. wire. The wand and wor type nets signify wired-and and wired-or functions, respectively. For wand type, a 0 value on a driving source overrides all other source values and value Z is treated as null and is overridden by any other value driving a wand net. In wor operation, logic value 1 on one source overrides all other source values. As in wand, the Z value is the weakest and is overridden by 0, 1 wand, and X values.
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Net Declarations
NET TYPES Supply
supply0 supply1 wire (tri)

PROPERTIES
Driven: 0 Driven: 1 Tri -state wired logic Wired-and logic Wired-or logic Hold old value

INITIAL
0 1 Driven: X Not Driven: Z Driven: X Not Driven: Z Driven: X Not Driven: Z X

Three-state

wand (triand) wor (trior)

Capacitive

trireg

net Types and Properties


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Net Declarations
s1 0 s2 0 1 X Z
0 X X 0

1
X 1 X 1

X
X X X X

Z
0 1 X Z

s1
wire value

s2

wire net type

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77

s1 0 s2 0 1 X Z
0 0 0 0

Net Declarations
1 X
0 1 X 1 0

Z
0

s1
wand value

X 1 X X X Z

s2

s1 0 s2 0 1 Z
0 1

1 X
1 1 1 1 X 1 X X

Z
0 1 X Z

s1
wor value

X X
0

s2

(a) wand net Types, (b) wor net Type


CSE 467 Verilog Digital System Design 78

39

Net Declarations
The trireg type net behaves as a capacitive wire and holds its old value when a new resolved value is to become Z. As long as there is at least one driver with 0, 1, or X value, trireg behaves the same as wire. When all drivers are turned off (Z), a trireg net retains its previous value. The amount of time a trireg net holds a value is specified by a delay parameter in its declaration. Delay parameters will be discussed next. Chapter 7 shows examples of using trireg for CMOS flip-flop modeling.

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Net Declarations

Three delay values for net switching to 1, to 0, and to Z are specified in a set of parenthesis that are followed by a # sign after the net type keyword. A simpler format contains a single delay value.
wire #3 w, n, m, p;

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40

Net Declarations
trireg net types may also be declared with three delay parameters. Unlike the case with other nets, in this case the third timing parameter is not delay for the Z transition. Instead, this specifies the time that a declared trireg net holds an old value when driven by Z. The initial value for all net types except supply0 and supply1 with at least one driver is X. A net with no driver assumes the Z value, except for trireg, which has the initial value X. trireg,

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81

Reg Declarations
Verilog Data Types Reg Declarations Declarations

Net Declarations

Signed Data
CSE 467

Parameters

Verilog Digital System Design

82

41

Reg Declarations
reg is a variable for holding intermediate signal values or nonhardware parameters and function values. The reg declaration shown below declares a, b and ci as reg types with 0 initial values.
reg a=0, b=0, ci=0; ci=0;

The default initial value of a declared reg is (X).

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Reg Declarations
Other reg types are integer and time. An integer declaration declares a signed 2s-complement number, and a time declaration declares an unsigned reg variable of at least 64 bits.

Verilog also allows declaration of real and realtime variables. These variables are similar in use to integer and time variables, but do not have direct bit-to-bit correspondence with reg type registers.

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42

Signed Data
Verilog Data Types

Net Declarations

Reg Declarations

Signed Data
CSE 467

Parameters

Verilog Digital System Design

85

Signed Data
Verilog net and reg types can be declared as signed. In below example areg is declared as a signed reg.
reg signed [15:0] areg; areg;

A signed reg that is shifted right by the >>> operator is sign filled, whereas an unsigned reg shifted by this operator is zero-filled.

If the right-hand side of an assignment is determined as signed, it is sign extended to the size of its left hand side and is placed on the left hand side reg or net.

CSE 467

Verilog Digital System Design

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43

Parameters
Verilog Data Types

Net Declarations

Reg Declarations

Signed Data
CSE 467

Parameters Parameters

Verilog Digital System Design

87

Parameters
Parameters in Verilog do not belong to either the variable or the net group. Parameters are constants and cannot be changed at runtime. Parameters can be declared as signed, real, integer, time or realtime.

Example
parameter parameter parameter parameter p1=5, p2=6; [4:0] p1=5, p2=6; integer p1=5; signed [4:0] p1=5;

Explanation
32 bit parameters 5 bit parameters 32 bit parameters 5 bit signed parameters

Parameter Examples

CSE 467

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44

Array Indexing
Module Basics Code Format Wires and Variables Logic Value System Module Ports

Modules

Names

Numbers

Arrays
CSE 467

Verilog Operators

Verilog Data Types

Array Array Indexing Indexing


89

Verilog Digital System Design

Array Indexing
Array Indexing

Bit Selection

Part Selection Multi Dimensional Memories


90

Standard Memory
CSE 467

Verilog Digital System Design

45

Bit Selection
Array Indexing

Bit Bit Selection Selection

Part Selection Multi Dimensional Memories


91

Standard Memory
CSE 467

Verilog Digital System Design

Bit Selection
Bit-select and part-select operators are used for extracting a bit or a group of bits from a declared array.
reg reg reg reg reg [7:0] Areg; Areg; Amem [7:0]; Dmem [7:0][0:3]; [7:0] Cmem [0:3]; [2:0] Dmem [0:3][0:4];

Bit-selection is done by using the addressed bit number in a set of square brackets. For example Areg[5] selects bit 5 of the Areg array.

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46

Part Selection
Array Indexing

Bit Selection

Part Part Selection Selection Multi Dimensional Memories


93

Standard Memory
CSE 467

Verilog Digital System Design

Part Selection
Verilog allows constant and indexed part-select. For example, Areg[7:3] selects the upper five bits of Areg. Areg.
Areg Areg Areg [5:3] [5-:4] [2+:4] //selects //selects //selects bits bits bits 5, 5, 5, 4 and 3 4, 3 and 2 4, 3 and 2

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47

Standard Memory
Array Indexing

Bit Selection Standard Standard Memory Memory


CSE 467

Part Selection Multi Dimensional Memories


95

Verilog Digital System Design

Standard Memory
Thememory with a 10 bit address standard format for declaring a memory in Verilog is to declare it as an array of a vector. (1024 address space)
(1024 address space) Emem as a byte-oriented

reg [7:0] Emem [0:1023]; addressed by Cmem [Areg[7:6]] Areg[7:6]] Areg[7:6] Extracts Emem word Emem [Emem[0]] Emem[0]] addressed by Emem [355][3:0] 4 LSBEmem[0] 355 of location 4 bits starting Emem [355][3-:4] from 3, down Emem [355:358]
Illegal; Does not address a 4-word block

extracts Cmem word

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48

Multi-Dimensional Memories
Array Indexing

Bit Selection

Part Selection Multi Multi Dimensional Dimensional Memories Memory


97

Standard Memory
CSE 467

Verilog Digital System Design

Multi-Dimensional Memories
For accessing such memories (e.g. Dmem declared before), simple indexing are allowed for specifying a word in the memory, and bitselect and part-select are allowed for accessing bit or bits of the addressed word.

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49

Multi-Dimensional Memories
// declaration Areg [7 :5] : reg [7 :0 ] Areg ; 7 Areg 0

// declaration : reg [7:0] Areg; Areg [7:5]


// declaration : reg Amem [ 7 :0 ]; Amem [3 ]

7
7

Areg
7
Amem

// declaration : reg Amem [ 7:0]; Amem [3]


// declaration : reg Bmem [7 :0][0 :3] Bmem [2 ] [1 ]

0 Amem 7
Bmem 7

0 0 3

// declaration : reg Bmem [7:0][0:3] Bmem [2] [1]


0 // declaration : reg [7:0] Cmem [0:3]
// declaration : reg [7:0 ] C mem [0 :3] C mem [1 ] [6 -: 4]

Bmem
7

0
0

Cmem [1] [6 -: : // declaration 4]reg [ 2:0] Dmem [0:3][0:4] Dmem [0] [2]
// declaration D mem [0 ] [2]

0 Dmem 3 3 : reg [ 2 :0 ] D mem [0 :3][0 :4]


D mem

Cmem

C mem

2
0
1 2 3

0 0 3

Array Addressing & Selection


CSE 467 Verilog Digital System Design

99

Verilog Simulation Model


Verilog Simulation Model

Continuous Assignments

Procedural Assignments

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Verilog Digital System Design

100

50

Continuous Assignments
Verilog Simulation Model

Continuous Continuous Assignments Assignment

Procedural Assignments

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101

Continuous Assignments
Continuous Assignments Simple Assignments Strength Specification Delay Specification Net Declaration Assignments

Multiple Drives
CSE 467 Verilog Digital System Design 102

51

Simple Assignments
Continuous Assignments Simple Simple Assignments Assignments Strength Specification Delay Specification Net Declaration Assignments

Multiple Drives
CSE 467 Verilog Digital System Design 103

Simple Assignments
A continuous assignment in Verilog is used only in concurrent Verilog bodies. This assignment represents a net driven by a gate output or a logic function. assign w = m | p;

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52

Delay Specification
Continuous Assignments Simple Assignments Strength Specification Delay Specification Net Declaration Assignments

Multiple Drives
CSE 467 Verilog Digital System Design 105

Delay Specification
assign #2 w = m | p; This assignment becomes active when m or p changes. At this time, the new value of the m | p expression is evaluated, and after a wait time of 2 time units, this new value is assigned to w.

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53

Delay Specification
`timescale 1ns/100ps module Mux2to1 (input a, b, c, output w); (input wire n, m, p; Regardless of position in the assign #3 m = a & b; code, each assignment waits for assign #3 p = n & c; a right-hand-side variable to assign #6 n = ~b; change for it to execute. assign #2 w = m | p; endmodule Concurrent Continuous Assignments

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The simulation the Delay Specificationin aofglitchpreviousa circuit results due to 1-hazard on w. The event driven simulation of concurrent statements makes this simulation to correspond to events in the actual circuit.

Simulation Run Showing a Glitch

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Verilog Digital System Design

108

54

Strength Specification
Continuous Assignments Simple Assignments Strength Specification Delay Specification Net Declaration Assignments

Multiple Drives
CSE 467 Verilog Digital System Design 109

Simple Assignments
Net strengths are specified by a pair of strength values bracketed by a set of parenthesis, as shown below. assign (strong0, strong1) w = m | p; (strong0, strong1) One strength value is for logic 1 and one is for logic 0, and the order in which the strength values appear in the set of parenthesis is not important. Strength value names for logic 1 end with a 1 (supply1, (supply1, strong1, pull1, weak1, ) and those for logic 0 end with a 0 (supply0, strong0, strong1, pull1, weak1, (supply0, strong0, pull0, weak0, ). pull0, weak0,

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Verilog Digital System Design

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55

Three strength values, large, medium, For wire and tri type nets, drive Default values for these nets and strength values are used, and for and strong1 forsmall, are used for trireg net types, are strong0 and the default is medium. storage nets charge strength is and logic 1 respectively. logic 0 used.

Strength Specification
Wires (tri) wand (triand), Wor ( trior), tri0, tri1 Strength value
Supply 0 Strong 0 Pull 0

trireg
Level
7 6 5 4 Large Medium (0) Small (0) 3 2 1 0 0 1 2 Small (1) Medium (1) Large (1)

Strength values

Strength 0

Weak 0

Highz 0 Highz 1

Weak values

Weak 1 Pull 1 Strong1 Supply 1

3 4 5 6 7

net Types and Their Strengths


CSE 467

Strength 1

Verilog Digital System Design

111

Net Declaration Assignments


Continuous Assignments Simple Assignments Strength Specification Delay Specification Net Declaration Assignments

Multiple Drives
CSE 467 Verilog Digital System Design 112

56

Net Declaration Assignments


`timescale 1ns/100ps module Mux2to1 (input a, b, c, output w); (input wire #3 m = a & b, p = n & c, In this code, all the continuous n = ~b, assignments of previous code are w = m | p; replaced by a list of net declaration endmodule assignments providing drivers for
w, n, m and p signals.

Using net_declaration_assignment

CSE 467

Verilog Digital System Design

113

Multiple Drives
Continuous Assignments Simple Assignments Strength Specification Delay Specification Net Declaration Assignments

Multiple Drives
CSE 467 Verilog Digital System Design 114

57

Multiple Drives
`timescale 1ns/100ps module Mux2to1 wire n; wor #2 w; assign #3 w assign #3 w assign #6 n endmodule (input a, b, c, output w); (input = a & b; = n & c; = ~b;
A value assigned to w is first delayed by continuous assignment delay. Before this value appears on w, it is further delayed by 2 ns specified in wor declaration.

A net with Multiple Drivers

CSE 467

Verilog Digital System Design

115

Multiple Drives

Simulation Run of Assignment Statements


CSE 467 Verilog Digital System Design 116

58

Procedural Assignments
Verilog Simulation Model

Continuous Assignment

Procedural Procedural Assignments Assignment

CSE 467

Verilog Digital System Design

117

Procedural Assignments
Procedural assignments in Verilog take place in the initial and always procedural constructs, which are regarded as procedural bodies.

CSE 467

Verilog Digital System Design

118

59

Procedural Assignments
Procedural Assignments Procedural Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force and Release


119

Verilog Digital System Design

Procedural Flow Control


Procedural Assignments Procedural Procedural Flow Control Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force and Release


120

Verilog Digital System Design

60

Procedural Flow Control


Statements in a procedural body are executed when program flow reaches them. Flow control statements are classified as delay control and event control. An event or delay control statement in a procedural body causes program flow to be put on hold temporarily.

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Procedural Flow Control


program flow stops when it Program flow resumes reaches the @ (reset) after the positive edgestatement and resumes when of Program flow resumes the value of reset changes. always clk the afteralwaysput on hold being . . for 10 time units.
always

. . . . .

@ (reset )

. . . . .

@ (posedge CLK)

. . . . . .

#10

end

end

end

Procedural Flow Control

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Verilog Digital System Design

122

61

Procedural Blocking Assignments


Procedural Assignments Procedural Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force and Release


123

Verilog Digital System Design

Procedural Blocking Assignments


A blocking assignment uses a reg data type on the left-hand side and an expression on the right-hand side of an equal sign.

The syntax of intra-assignment control constructs is similar to that of procedural flow control statements, but these constructs appear on the right-hand side of an equal sign in a procedural assignment.
. . .; #200 a = #100 b; The procedural assignment that is delayed by 200 time units by a delay control statement and by 100 time units by an intraassignment delay control.

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62

Procedural Blocking Assignments


initial begin : Blocking_Assignment_to_b b = 1; #100 b = #80 0; b = #120 1; #100 $display ("Initial Block with Blocking Assignment to b Ends at:", $time); $time); end The $display
statement displays 400

Blocking Procedural Assignments

CSE 467

Verilog Digital System Design

125

Procedural Non-blocking Assignments


Procedural Assignments Procedural Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force and Release


126

Verilog Digital System Design

63

Procedural Non-blocking Assignments


A non-blocking assignment uses the left arrow notation <= (left angular bracket followed by the equal sign) instead of the equal sign used in blocking assignments. When flow reaches a non-blocking assignment, the right-hand side of the assignment is evaluated and will be scheduled for the left-hand side reg to take place when the intra-assignment control is satisfied.

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Verilog Digital System Design

127

Procedural Non-blocking Assignments


initial begin : Non_blocking_Assignment_to_a a = 1; #100 a <= #80 0; a <= #120 1; #100 $display ("Initial Block with Non-blocking Assignment to a Ends at:", $time); $time); end
The $display statement displays 200

Non-blocking Procedural Assignments

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Verilog Digital System Design

128

64

Procedural Non-blocking Assignments

Comparing Blocking and Non-blocking Procedural Assignments

CSE 467

Verilog Digital System Design

129

Multiple Assignments
Procedural Assignments Procedural Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force and Release


130

Verilog Digital System Design

65

Multiple Assignments
If several assignments appear at the same real time in a procedural body, the last assignment overrides all others. If program flow in two procedural bodies reaches assignments to the same reg at exactly the same time, the outcome of the value assigned to the left-hand side of the assignment will not be known.

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Verilog Digital System Design

131

Multiple Assignments
initial begin clk = 0; end always begin clk = ~clk; ~clk; #17; end Multiple reg Assignments

This code works properly only if complementing of the clk is delayed until the clk is initialized to 0 in the initial block.

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66

Multiple Assignments
initial begin clk = 0; end always begin #0; clk = ~clk; ~clk; #17; end

One way to correct this problem is to delay complementing the clock by one simulation cycle. This can be done by inserting #0.

Multiple reg Assignments; Delay Used for Deterministic Results

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Verilog Digital System Design

133

Procedural Continuous Assignments


Procedural Assignments Procedural Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force and Release


134

Verilog Digital System Design

67

Procedural Continuous Assignments


Using a procedural continuous assignment construct, an assignment to a reg type variable can be made to stop all other assignments to this variable from taking place.
deassign qout <= 0; While qout is not deassigned, no other assignments to it affect its value.

Unlike assign and deassign, which apply to reg type variables, force deassign, and release constructs apply to net and reg types.

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Verilog Digital System Design

135

Procedural Continuous Assignments


`timescale 1ns/100ps module FlipflopAssign (input reset, din, clk, output (input clk, qout); qout); reg qout; qout; If reset is not active (it is 0), the always @(reset) begin flip-flop output qout is deassigned. if (reset) assign qout <= 0; Assignment takes place only when Only after qout is deassigned can else deassign qout; qout; reset is 0. While to assign is in other assignments an qout change end effect, another assign to the same its value. variable, deassigns the one that is always @(posedge clk) begin @(posedge clk) in effect and then assigns a new qout <= din; value to the variable. end endmodule Procedural Continuous Assignments
CSE 467 Verilog Digital System Design 136

68

Force and Release


Procedural Assignments Procedural Flow Control Procedural Non-blocking Assignments Procedural Continuous Assignments
CSE 467

Procedural Blocking Assignments Multiple Assignments Force And and Release


137

Verilog Digital System Design

Force and Release


Unlike assign and deassign, which apply to reg type variables, force, deassign, force, and release constructs apply to net and reg types. Forcing a value on a net overrides all values assigned to the net through continuous assignments or connected to it through gate outputs.

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Verilog Digital System Design

138

69

Compiler Directives
Compiler Directives

timescale

default-nettype default-nettype

include

define

ifdef, else, ifdef, endif

unconnected -drive

celldefine, celldefine, endcelldefine

resetall

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Verilog Digital System Design

139

`timescale
Compiler Directives

timescale timescale

default_nettype

include

define

ifdef, else, ifdef, endif

unconnected _drive

celldefine, celldefine, endcelldefine

resetall

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70

`timescale
Including the timescale 1ns/100 ps directive before a module header causes all time-related numbers to be interpreted as having a 1-ns time unit.

CSE 467

Verilog Digital System Design

141

`default-nettype
Compiler Directives

timescale

default-nettype default_nettype default-nettype

include

define

ifdef, else, ifdef, endif

unconnected _drive

celldefine, celldefine, endcelldefine

resetall

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71

`default-nettype
The default wire type can be changed by the default_nettype. For default_nettype. example,
default_nettype wor

at the beginning of a module causes undeclared nets in constructs such as the terminal list of a module instance to be assumed to be wor type nets.

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Verilog Digital System Design

143

`include
Compiler Directives

timescale

default_nettype

include

define

ifdef, else, ifdef, endif

unconnected _drive

celldefine, celldefine, endcelldefine

resetall

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72

`include
Because Verilog does not provide a common library of parts and utilities, a shared code must be explicitly inserted in modules that use the code.

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Verilog Digital System Design

145

`define
Compiler Directives

timescale

default_nettype

include

define

ifdef, else, ifdef, endif

unconnected _drive

celldefine, celldefine, endcelldefine

resetall

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73

`define
`define word_length 32 `define begin_fetch_state 3b101 3
if begin_fetch_state is used anywhere in a Verilog code, it is replaced by 3b101.

undef directive undefines a previously defined text macro

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147

`ifdef, `else, `endif


Compiler Directives

timescale

default_nettype

include

define

ifdef,, else, ifdef, else, ifdef, ifdef endif endif

unconnected _drive

celldefine, celldefine, endcelldefine

resetall

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74

`ifdef, `else, `endif


Because Verilog does not provide a common library of parts and utilities, a shared code must be explicitly inserted in modules that use the code.

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Verilog Digital System Design

149

`ifdef, `else, `endif


If the next macro has been defined, the group of lines bracketed between ifdef and else is compiled. If the text macro has not been defined, the group of lines bracketed between else and endif is compiled.

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150

75

`unconnected-drive
Compiler Directives

timescale

default_nettype

include

define

ifdef, else, ifdef, endif

unconnected unconnected -drive _drive

celldefine, celldefine, endcelldefine

resetall

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`unconnected-drive
Changes port value left open in the connection list of a module instantiation which is assumed to have the default net value. The only arguments allowed with this directive are pull0 or pull1 for unconnected values 0 and 1, respectively.

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76

`celldefine, `endcelldefine
Compiler Directives

timescale

default_nettype

include

define

ifdef, else, ifdef, endif

unconnected _drive

celldefine,, celldefine, celldefine, celldefine endcelldefine endcelldefine

resetall

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153

`celldefine, `endcelldefine
The celldefine and endcelldefine directives bracket modules that are to be considered as cells.

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Verilog Digital System Design

154

77

`resetall
Compiler Directives

timescale

default_nettype

include

define

ifdef, else, ifdef, endif

unconnected _drive

celldefine, celldefine, endcelldefine

resetall

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155

`resetall
Using this directive at the beginning of every module guarantees that no previous setting affects compilation of modules and that all defaults are set.

CSE 467

Verilog Digital System Design

156

78

System Tasks and Functions


The names of system tasks and functions begin with a dollar sign, $, followed by a task specifier

CSE 467

Verilog Digital System Design

157

System Tasks and Functions


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions
158

79

Display Tasks
System Tasks and Functions Display Tasks Display Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions
159

Display Tasks
Display tasks include those for monitoring and outputting variable values as they change (the $monitor group of tasks) and those for displaying variables at a selected time (the $display tasks). Display tasks can display in binary, hexadecimal, or octal formats. The character b, h, or o at the end of the task name specifies the data type a task handles.

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Verilog Digital System Design

160

80

File I/O Tasks


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions
161

File I/O Tasks


The $fopen function opens a file and assigns an integer file description. The file descriptor will be used as an argument for all file I/O tasks. There are string write tasks ($swrite) that write their formatted ($ swrite) outputs to a string. Verilog also provides tasks for inputting data from files or strings. Examples of these tasks are $fgetc, $fscanf, and $sscanf for getting fgetc, fscanf, character from file, reading formatted data from file, and reading formatted data from string, respectively.

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Verilog Digital System Design

162

81

File I/O Tasks


Other input tasks exist for reading memory data directly into a declared memory. Examples of such tasks are $fread and $ readmemh. readmemh. File positioning tasks, $fseek and $frewind are available for positioning file pointer for read or write.

CSE 467

Verilog Digital System Design

163

Timescale Tasks
System Tasks and Functions Display Tasks Timescale Tasks Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions
164

82

Timescale Tasks
The $printtimescale task displays the timescale and precision of the module whose hierarchical name is being passed to it as its argument. The $timeformat task formats time for display by file IO and display tasks.

CSE 467

Verilog Digital System Design

165

Simulation Control Tasks


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions
166

83

Simulation Control Tasks


The $finish task ends the simulation and exits. The $stop task suspends the simulation and does not exit the simulation environment.

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Verilog Digital System Design

167

Timing Check Tasks


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Timing Check Tasks Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions
168

84

Timing Check Tasks


In general, timing check tasks check the timing on one signal or the relative timing of several signals for certain conditions to hold. $nochange (posedge clock, d_input, 3, 5); (posedge d_input,
Uses the $nochange timing $nochange check task to report a violation if d_input changes in the period of 3 time units before and 5 time units after the positive edge of the clock. clock.

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Verilog Digital System Design

169

PLA Modeling Tasks


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

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PLA Modeling Tasks


The general format that we use for describing these tasks is: $sync_async: can be either sync or async sync_async: $and_or: can be and, or, nand, or nor and_or: nand, $array_plane: in place of array_plane, array or plane can be used. array_plane: array_plane, $async $nand $array $nand (mem8by4, {a1, a2, a3, a4, a5, a6, a7, a8}, {b1, b2, b3, b4}} An asynchronous PLA with a
nand logical function, a1 to a7 inputs, and b1 to b4 outputs. PLA nand-plane fuses are nand-plane determined by the contents of the mem8by4 declared memory
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b1 b2 b3 b4
0 1 0 0 0 1 0 1 1 0 0 0

= = = =

~(a3 ~(a1 ~(a5 ~(a2


1 0 0 1 0 1 1 0

& & & &


0 0 1 0

a4 & a8) a2 & a5) a6) a4)


0 0 0 0 1 0 0 0

PLA Output Equations

a1 a2 a3 a 4 a 5 a6 a7 a8 b1 b2 b3 b4

a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4

(a) Contents of mem8by4, (b) Corresponding PLA NAND Plane


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Conversion Functions for Reals


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Tasks Convention Functions Conversion For Reals for Reals
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Conversion Functions for Reals


Verilog provides four system functions for converting from real to integer or bit, and for converting between bit or integer and real. The functions are $bitstoreal, $realtobits, $itor, and $rtoi. $bitstoreal, realtobits, itor, rtoi.

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Other Functions and Tasks


System Tasks and Functions Display Tasks Timescale Tasks Timing Check Tasks Conversion Functions For Reals
CSE 467 Verilog Digital System Design

File I/O Tasks Simulation Control Tasks PLA Modeling Tasks Other Tasks and Functions and Functions
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Other Functions and Tasks


$random is a useful function for random data generation. There are three time functions, $realtime, $time, and $stime, that return realtime, $time, stime, the simulation time in various formats.

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Summary
This chapter presented: General timing and concurrency concepts that are particular to hardware description languages. Utilities found in Verilog for describing hardware and hardware test environments. General syntax of the language its operators, names, and data types. Simulation of hardware described in Verilog using language constructs and utilities of this language. Tasks and compiler directives, that are part of the language utilities for hardware and testbench modeling, but are secondary to those discussed in Section 3.2. Most of Verilog without presenting a lot of examples and specific applications of the language constructs.

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