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Each schedule is added to the current intermediate hash value. message schedule. non linear function and standard initial hash values of secure hash algorithm. and word operations to iteratively generate a series of hash values. The message digest uses the message schedule. and message digest calculation.3 General block diagram of SHA-1: Input message or data length is 64-bit data. where the initialization vectors determine the initial hash value. and setting initialization values used in the hash computation. In the message digest calculation are done by word computation (Wt). The final hash value generated by the hash computation is used to determine the message digest.2 Specifications: • • • • • Security Padding Parsing Message schedule Message digest 3. The output of preprocessor block . constants. this 64-bit data is generated by the preprocessor block. parsing the padded message into 512-bit blocks. along with functions.CHAPTER – 3 DESIGN 3. The secure hash algorithm (SHA-x) can be described in three stages: preprocessing. Preprocessing involves padding a message. The security is done by padding and message schedule process based hash algorithm. Each padded 512-bit block is then expanded to form the message schedule.1 Design of Secure hash algorithm: The main object of the secure hash algorithm (SHA-x) is to implement Security as well as digest of the given input data for the data integrity. 3.

Fig 3. This preprocessing consists of three steps: 1. Then 2560-bit and internal hash values (160-bit) are applied to Message digest (MD) block as input.1. Then message scheduler block expanding a 512-bit input message block into 2560-bit output block.1: GENERAL BLOCK DIAGRAM OF SHA-x 3. of length ‘l’ bits. M.4.4 Pre-Processing: Pre-processing means performed on raw data to prepare it for another processing procedure. For a message. 3. That 512-bit is applied to an input for message scheduler block.1 Padding the message: The purpose of padding is to ensure that the message is a multiple of the block size.produced 512-bits data. Padding the message 2. padding is carried out in the following manner. 3. Then message digest generated and produced an output of 160-bit fixed hash value which is shown in Fig 3. Setting the initial hash values. 512-bits before hash computation begin. Afterwards . First 3-bits are given as “abc” in ASCII format. Parsing the padding message into message blocks.

Fig 3.4. followed by ‘k’ zero bits.3: Padding the message as stream of bits 3.2: Padding the message block Fig 3.Then append the 64-bit block representing the size of the original message at last as shown in Fig 3.2 Parsing the padding message into message blocks: .2 and Fig 3. where k is the smallest.3. non-negative solution to the equation: l +1+k=512 mod 448.append the bit “1” to the end of the message.

M3 =00000000. the first 32-bits of message block is M1. M10=00000000 M11 =00000000. M1. Fig 3. M8 =00000000. it must be divided into N into M-bit blocks before the hash computation begin.4. M2=00000000..e.. M7 =00000000. M4 =00000000. M5 =00000000. M3 ……….M16. M2. M14 =00000000 M15=510a4571. M9 =00000000. The padded message is divided into N * M-bits equal to 512-bits block i.4: Parsing the message block . Since the 512 bits of the input block may be expressed as sixteen 32bit words. For example 512-bits are parsing into 16 * 32-bits as shown in Fig 3.After message is padded. so on up to last is M16. Input 512-bits:-61626310000000000000……. M16 =337890b2.0510a4571337890b2 M1=61626310. M13 =00000000. second is M2. M6 =00000000. M12 =00000000.

3.4. The size and number of words depends on the message digest size. These initial hash values are standard hash values developed by National Institute of Standards Hash Buffer H0 H1 H2 H3 H4 Hash Value X”67452301” X”EFCDAB89” X”98BADCFE’ X”10325476” X”C3D2E1F0” and Technology (NIST). The initial hash values are hexadecimal values as shown in below Table 1.3 Setting the initial hash values: Before hash computation begins for each of the secure hash algorithms. Table 1: Initial hash values. . the initial hash value must be set.

the message scheduler block diagram is design which is shown in Fig 3. After storing the data in registers the output is taken from 4 register (i. one xor gate and one rotate left module.e.……….e. that output is given to multiplexer . R16) and each resister is 32-bit. When multiplexer (MUX = ‘1’ )the data(i.R3. in each register it stores 32-bits data . R14. given to the input for xor gate.R2..R1. R8. The messagescheduling unit of the SHA-x algorithm consists of expanding a 512-bit message block into 2560-bit block. R3.3. second 32-bits data will be stored in R15 register and so on up to last 32-bits data will be stored in first R1 register.(R2 move to R3) then( R3 move to R4) then (R4 move to R5) so on . The multiplexer (MUX) is used for selection purpose of data. One 32-bit word. total 16 registers (i. (Wt) will be delivered to the message digest unit for digest in each of the 80 iterations.when multiplexer (MUX = ‘0’ ) the output of data will be stored in register R1. 512 -bits input) will stored in registers . The message schedule is prepared by expanding the divided 512-bit data block to a sequence of eighty 32-bit words.5 Developed Architecture of Message scheduler block: With the help of below equation. Mt Wt = ROTL1 (Wt-3 Wt-8 Wt-14 Wt-16) 0<t<15 16<t<79 Message scheduler block diagram consist of one multiplexer. The xor gate produced an output of 32-bits data. 16 registers. that 32-bits data is given an input for rotate left one bit module (ROTL1) here the rotate left module rotates one bit to most significant position.e. R16) it stores 512-bits data .the first 32-bits data will be stored in last R16 register. Before when (MUX = ‘1’ )in register (R1) there will be some other data that data will be move to register (R2).5.

This process will be continued up to another 64 iterations to find word computation (Wt) for message digest unit.up to (R15 move to R16) just like first in first out (FIFO) process . M e ssa g e W o rd Mt R0 R1 Wt R2 R3 R4 R5 R6 R7 R8 R9 R 10 R 11 R 12 R 13 R 14 R 15 R O X R O T 1L ’ .

5 Developed Architecture of Word computation block: Input to the word computation (Wt) is 32-bits which is taken from 16 words i.e. that output is stored in register (i.Fig 3.e 512-bits.6. Rotate left one bit module (ROTL 1) rotates one bit to most significant position.5: Message scheduler block diagram 3. 17th word).5 and generated then afterward xored. From the block of 16 words selecting 4 words with the of equation as shown in above fig 3. . The xored gate output is 32-bits which are given as input for rotate left block. This operation will be done for up to another 64-times as shown in fig 3.

each consisting of five 32-bit words. B. The words of the second 5word buffer are labeled working variables temporally A.6 Developed Architecture of Message digest single round: The message digest computation for single round is described using two buffers.Fig 3. the initial hash values are initialized as follows in hexadecimal. and E. C. The words of the first 5-word buffer are labeled A. . C. D. D. and E. Before processing any blocks.6: Word computation block diagram 3. B.

.A = 67452301 B = EFCDAB89 C = 98BADCFE D = 10325476 E = C3D2E1F0. are used to forming intermediate hash values.7. C.. which are standard values. K1…. and E as shown in Fig 3.e. . The output of single round message digest is 160-bits hash value which is stored in second 5-word buffer are labeled working variables temporally A. SHA-1 uses a sequence of eighty constant 32-bit words. B. D = C. constant (Kt). For t = 0 to 79 do TEMP = ROTL5 (A) + Ft (B. With the help of below equation. are standard initial hash values. The message digest sequentially processes each message schedule under a set of operations. word computation (Wt).e. The set of operation are rotate left module. D) + E + Wt + Kt. the message digest single round architecture is developed. C. is 32-bits and internal input is 160-bits i. C = ROTL30 (B). The constant values are in hexadecimal format. Here word computation (Wt) is an external input for message digest i. K0. E = D. D. A = TEMP. B = A. K79 and eighty non-linear functions which are shown in the table 2 and table 3. and non linear function (Ft).

Fig 3.7: Message digest single round diagram Constant Value X”5A827999” X”6ED9EBA1” X”8F1BBCDC” X”CA62C1D6” Step (0 -to -19) (20 -to -39) (40 -to -59) (60 -to -79) Table 2: SHA-x constants values .

linear functions .Fig 3.8: SHA-x non-linear functions Table 3: SHA-x non.

Fig 3.9. IV2. Functions and constants are basic operation of each round. 3.9: Message digest ‘N’ diagram. .7 Developed Architecture of Message digest ‘N’ round: The message digest ‘N’ round architecture is shown in Fig 3. Each round operates on five 32 bits hashing words (H0 to H4 which have A to E as their temporary versions. Finally the ‘N’ round output is added with initial hash values and produced hash output of 160-bits (H0. IV3 and IV4) this 160-bit data is generated by the first round and produced an output of 160-bits.10. Here the external input data length of message block size (Mi) is 512-bits and standard initial hash values (Hi) is 160-bits length is applied. That first round output of 160-bits is given as input for second round and produced an output of 160-bits and so on up to ‘N’ rounds. H2.SHA-x requires the operation of 80 rounds which can be grouped into 4 groups. H3. and H4). IV1.3.8 Developed VLSI Architecture of Secure hash algorithm (SHA-x): The VLSI architecture of secure hash algorithm (SHA-x)is shown in Fig 3. Input data length is 160-bit data given as initial hash value (IV 0. H1. 20 rounds each.

Fig 3. different constant value (Kt) and different word computation (Wt). each group it uses different function.Those constants are round constants (Kt) and message word computation (Wt). C.Total four groups. D and E) to get final output.The output of 80th round is added with initial hash value (A.10: VLSI architecture of secure hash algorithm (SHA-x): . B.

Table 4: Secure hash algorithm inputs-outputs .

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