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# Practical Design of an ASIC

7
Test

7.1 Introduction This chapter analyzes a practical IC and covers the top-level to bottom-level design of an ASIC (Application Specific Integrated Circuit). It uses the DIGCHIP design available with L-EDIT Version 5.00. 7.2 Requirements analysis

Requirements analysis

Requirements specification

Design

Implementation

The requirements analysis and specification is the first stage of the process and is typically the most difficult part. Any failure in analyzing the requirements can be very costly in future work. At this stage, decisions are made as to the nature and bounds of the project and how the problem is to be solved. These decisions involve: • stating how the problem is to be solved; • stating the requirements that define successful solution of the problem. If after this stage a requirement has been identified then a requirements specification is generated. This defines the technical requirements of the system and should state exactly how the system is intended to operate and all operational constraints. In this case the objective is to produce an ASIC which will control a set of traffic lights and a WALK/DONT WALK light. A layout of the traffic light junction is shown in Figure 7.1. There are two sets of traffic lights, from North to South (_NS) and from East to West (_EW). One complete sequence of a single traffic light is 64 seconds, made up of: • • • • 24 seconds GREEN. 8 seconds YELLOW. 32 seconds RED. then repeat.

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N

CROSS

W

C R O S S R Y G S

E

WALK DONT

Figure 7.1

Traffic light junction.

With two traffic lights, one traffic light should show steady RED until the other traffic light has finished its sequence. Table 7.1 outlines the basic sequence. When the East-West traffic light is showing RED then pedestrians can cross on the North-South junction and vice versa. Thus when the GREEN on the North-South junction is on then the North-South WALK light is on for 16 seconds. It will then flash for 8 seconds (16 flashes, that is on for 0.5 seconds and off for 0.5 seconds).
Table 7.1 Traffic light sequence.

Traffic light 1 GREEN YELLOW RED RED GREEN YELLOW RED RED and so on.

Traffic light 2 RED RED GREEN YELLOW RED RED GREEN YELLOW

Time (seconds) 24 8 24 8 24 8 24 8

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7.3 Requirements specification

Requirements analysis

Requirements specification

Design

Implementation

Test

The requirement specification defines all the system requirements and any constraints or limitations. All functions performed by the system will be specified and all error and warning conditions are documented. The requirements specification is extremely important and all parties involved in the system development must agree on its content before a full design takes place. 7.3.1 Input/output requirements The design requires the generation of a number of states which will be generated by a system clock. A reset input will also be required to start the system in a known state. These input signals will be named CLOCK and RESET. There are 12 outputs to the system for the traffic lights and walk/don’t walk signals. These will be named RED_EW (for RED light on the East/West junction), YELLOW_EW, GREEN_EW, RED_NS, YELLOW_NS, GREEN_NS, WALK_EW, DONT_EW, WALK_NS and DONT_NS. Figure 7.2 shows the input/output requirements and for the ASIC.
RED_NS YELLOW_NS GREEN_NS WALK_NS DONT_NS CLOCK RED_EW RESET YELLOW_EW GREEN_EW WALK_EW DONT_EW Traffic light controller

Figure 7.2

Connections to system.

7.3.2 Waveform diagram It can be shown that the system requires a total of 128 states. This will require a 7-bit counter. Figures 7.3 to 7.5 show the waveform diagram for the system. After this the waveform repeats. It can be seen that since that the system clock must operate at 8 cycles over 4 seconds, or 2 Hz.

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0 CLK

8

16

24

32

40

48

4 seconds RED_EW

YELLOW_EW

GREEN_EW

RED_NS

YELLOW_NS

GREEN_NS

WALK_EW

DONT_EW

WALK_NS

DONT_NS

Figure 7.3

Waveform from 0 to 48 clock pulses.
48 56 64 72 80 88 96

CLK

RED_EW

YELLOW_EW

GREEN_EW

RED_NS

YELLOW_NS

GREEN_NS

WALK_EW

DONT_EW

WALK_NS

DONT_NS

Figure 7.4

Waveform from 48 to 96 clock pulses.

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96 CLK

104

112

120

128

RED_EW

YELLOW_EW

GREEN_EW

RED_NS

YELLOW_NS

GREEN_NS

WALK_EW

DONT_EW

WALK_NS

DONT_NS

Figure 7.5

Waveform from 96 to 128 clock pulses.

7.3.3 State table From the waveform diagrams in Figures 7.3 to 7.5 a state table can be produced. An outline of one for this design is given in Table 7.2 (the completion of the complete table is left as an exercise). The period between each change of state is 0.5 seconds. The signals have been assigned shortened names, such as R_E (RED_EW) and D_E (for DONT_EW).
Table 7.2
State 0000000 0000001 ::: 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 ::: 1111110 1111111

Traffic light sequence.
R_E 0 0 ::: 0 0 0 0 0 0 0 0 ::: 1 1 Y_E 0 0 ::: 0 0 0 0 0 0 0 0 ::: 0 0 G_E 1 1 ::: 1 1 1 1 1 1 1 1 ::: 0 0 R_N 1 1 ::: 1 1 1 1 1 1 1 1 ::: 0 0 Y_N 0 0 ::: 0 0 0 0 0 0 0 0 ::: 1 1 G_N 0 0 ::: 0 0 0 0 0 0 0 0 ::: 0 0 W_E 1 1 ::: 0 0 0 0 0 0 0 0 ::: 0 0 D_E 0 0 ::: 0 1 0 1 0 1 0 1 ::: 1 1 W_N 0 0 ::: 0 0 0 0 0 0 0 0 ::: 0 0 D_S 1 1 ::: 1 1 1 1 1 1 1 1 ::: 1 1

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7.4 Design

Requirements analysis

Requirements specification

Design

Implementation

Test

Figure 7.6 shows a top-level representation of the traffic light controller. The 7bit counter produces an output 0000000 to 1111111 on the signal lines GFEDCBA. This output is then fed into combinational logic to produce the required logic levels. The K-map for the GREEN_EW signal is given in Table 7.3.
RED_EW YELLOW_EW GREEN_EW RED_NS YELLOW_EW GREEN_EW WALK_EW DONT_EW WALK_NS DONT_NS

CLK

7-bit counter

A (lsb) B C Combinational D E logic F G(msb)

Figure 7.6 Table 7.3

Top-level representation of the traffic light controller. K-map for GREEN_EW signal. CBA 000 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

GEFD 0000 0001 0011 0010 0110 0100 0100 0111 1111 1110 1101 1001 1000 1011 1010 1100

001 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

011 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

010 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

110 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

100 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

101 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

111 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0

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From the K-map it can be seen that the GREEN_EW signals will give: GREEN _ EW = G. F + G.F . E This can then be minimized to produce:

GREEN _ EW = G.( F + F . E )
which can be further minimized to give:

GREEN _ EW = G.( F + E )
The conversion of the state table to the resultant logic is left as an exercise. The resulting logic is: RED _ EW = G RED _ NS = G YELLOW _ EW = G. F . E YELLOW _ NS = G. F . E GREEN _ EW = G. F + G. E GREEN _ NS = G. F + G. E WALK _ EW = F . G DONT _ EW = G + A. F . E + G. F . E WALK _ NS = G. F DONT _ NS = G + A. F . E + G. F . E From these logic equations the resultant electronic design can be generated. A 7bit ripple counter will be used. Figure 7.7 shows the resultant schematic after some minimization of terms. 7.5 Simulation All designs must be simulated to prove that they are error-free. In this case it is assumed that the design is fault-free and the actual simulation of the circuit is left as a tutorial example. Appendix D contains a C program which simulates the sequence of operations. An ECAD package such as OrCAD, Cadence or Mentor Graphics can be used to simulate the hardware operation. The results should be check against the requirements specification.

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D S Q

D S Q CK R Q

D S Q CK R Q

D S Q CK R Q

D S Q CK R Q

D S Q CK R Q

D S Q CK R Q

RED_EW RED_NS

CLK RESET

CK R

Q

E F A

DONT_NS

DONT_EW

G

WALK_NS

G

WALK_EW

YELLOW_NS

E

YELLOW_EW

F

GREEN_NS

GREEN_EW

Figure 7.7

Traffic light controller schematic.

7.6 Implementation

Requirements analysis

Requirements specification

Design

Implementation

Test

This section analyzes the DIGCHIP ASIC. Figure 7.8 shows the connection to the core of the ASIC. These connections are bounded to the plastic package with gold wires. Other signals are also used that are not included in the schematic in Figure 7.7. These are TOP4 (D output on 7-bit counter), TOP5 (E output on 7bit counter), TOP6 (D output on 7-bit counter), and TST_PNT ( E output on 7bit counter), There are a total of 18 pins which would probably connect to a 18pin DIL package.

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RED_NS

TOP6 GREEN_EW RED_EW

RESET

YELLOW_NS

CLK

GREEN_NS

VDD

CORE

GND

TOP5

DONT_EW

TOP4

YELLOW_EW

TST_PNT WALK_NS

DONT_NS WALK_EW

Figure 7.8

Traffic light controller schematic.

7.6.1 Top-level Figure 7.9 shows the completed ASIC. The design uses two layers of metal. From the input pads the VDD and GND lines connections connect with one layer of metal and the other input/output signals connect from the core to the pads with the second layer of metal. Figure 7.10 shows how the power rails connect to the logic cells. The top of the cells connects to VDD and the bottom of the cells to GND. It can also be seen from Figure 7.10 that the other signal lines cross underneath the power supply lines. It can be seen from Figure 7.9 and Figure 7.11 that the logic cells are arranged in three rows. The signal connection from the pads to the rows are shown around the outside of the diagram. Connections between the logic cells are made in the channels between the rows (the interconnection highway). These are made with metal connections, horizontal with metal 1 (so as not to shortcircuit to the supply rails) and vertical for metal 2. The metal 1 layer is shaded darker than the metal 2. A via (represented as a black box) connects layer 1 to layer 2. The interconnection of the cells is illustrated in Figure 7.12.

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Power supply rail (VDD)

Power supply rail (GND)

Figure 7.9

Traffic light ASIC.
logic cells

metal (layer 1)

metal (layer 2)

VDD

GND

Figure 7.10

Power supply connections.

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TOP6 CLK

RED_NS

RED_EW

GREEN_EW

GREEN_NS

RESET

YELLOW_NS

TOP4

YELLOW_EW

TOP5 WALK_NS WALK_EW DONT_NS

DONT_EW

TST_PNT

Figure 7.11
VDD

Traffic light ASIC showing the three rows of cells.

GND

Connection channel

Figure 7.12

Connections between cells with metal 1 and metal 2.

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The arrangement of the logic cells is given in Figure 7.13. A 2AND represents a 2-input AND gates, DFF represent a D-type flip-flop, 2NOR represents a 2-input NOR gate, and so on.

2AND

DFF

DFF

DFF

2NOR

3OR

3AND

2NOR

2OR

2NOR

2AND

DFF

DFF

2NOR

DFF

DFF

Figure 7.13

Layout of logic cells.

7.6.2 Logic cell design This section discusses the design of the 2-input NOR gate. The analysis of the remaining cells will be left as an exercise. Figure 7.14 shows the design 2-input NOR gate. It differs in its shape from the cell designed in the previous chapter because it has been compacted to save space. The equivalent transistor circuit on the left-hand side shows that the gate equates to a 2-input NOR gate. Inputs to the circuit are A, B and the output is Out. These connect to the cell with the metal 2 layer. The white boxes show the connection from metal 1 to metal 2 and the black boxes show the connection between metal and diffusion (an active contact) or between metal and polysilicon (a polysilicon contact). The width of the polysilicon is 2λ, the total length of the cell is 70λ and its width is 26λ. Space is saved by connecting the metal of the supplies into the diffusion layer (rather than vice versa, in the previous chapter). The polysilicon line runs vertical through the cell and crosses the diffusion layer to create the required transistor layout.

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The best way to understand the circuit is to trace the current flow from VDD to GND. First the current travels along the metal 1 layer and makes contact to the first PMOS transistor on the upper left-hand side of cell (the PMOS transistor connected to A). The current then flows through the diffusion horizontally and encounters the first polysilicon crossing (which makes the PMOS transistor). If this line is a low level then the current will cross the transistor and encounter another polysilicon crossing (the PMOS transistor connected to the B input). Again if the B input is a low then it will cross the channel in the diffusion on the other side. Metal 1 then connects to the diffusion and the current then flows downward and to the left-hand side. Next it connects to metal 2 by a via. The metal 2 layer directs the current downwards where it connects to metal 1 again which then connects to the diffusion layer in the lower part of the cell. The current can then take two routes (if the A and B input are high). Metal connects the diffusion back to the GND rail. Figure 7.15 gives the equivalent stick diagram (which is easier than cell layout to trace the logical flow).

Polysilicon VDD VDD A B

n-well

p-type diffusion

A

B

n-type diffusion

GND

GND

Via between metal 1 and metal 2 Contact to active diffision or polysilicon

Figure 7.14

2-input NOR gate cell and equivalent transistor circuit.

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VDD

Out A B

GND

Figure 7.15

2-input NOR gate cell and equivalent stick diagram.

Figure 7.16 shows the layout and dimensions of the two layers of metal. Figure 7.17 shows the masks for diffusion and polysilicon layers. All vias and contacts are 2λ×2λ.
26λ 8λ 12λ 9λ 8λ 16λ 12λ

29λ 19λ

8λ 16λ Metal 1 Metal 2 Dimensions are 4λ unless shown (or implied)

Figure 7.16

Metal 1 and metal 2 masks for 2-input NOR gate.

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6λ 8λ

32λ

19λ

22λ

32λ

Polysilicon

Diffision

Dimension are 2λ unless shown (or implied)

Figure 7.17

Polysilicon and diffusion masks for 2-input NOR gate.

Figure 7.18 shows a cross-section of the cell taken in lower-half of the cell where there is a via and two contacts between metal 1 and the diffusion.

Figure 7.18

Cross section of 2-input NOR gate showing contacts between layers.

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7.7 Exercises 7.1 Explain how the power supply lines connect to individual logic cells and also explain how the signal lines connect from the pads to the core of the cell. Explain how the logic cells electrically interconnect. Complete the state table in Table 7.2 for all of the states. The complete set of Boolean equations for the traffic light design is given next. Derive each of them. RED _ EW = G RED _ NS = G YELLOW _ EW = G. F . E YELLOW _ NS = G. F . E GREEN _ EW = G. F + G. E GREEN _ NS = G. F + G. E WALK _ EW = F . G DONT _ EW = G + A. F . E + G. F . E WALK _ NS = G. F DONT _ NS = G + A. F . E + G. F . E 7.5 With reference to Figures 7.11 and 7.13 identify the location of each of the gates in the schematic in Figure 7.7. Figure 7.19 is a 2-input NOR gate with an inverted output. Out1 is the NOR output and Out2 is the OR output. Identify its operation and each of the layers. If possible, estimate the lengths and widths of each of the layers. Figure 7.20 is a 2-input NAND gate with an inverted output. Out1 is the NAND output and Out2 is the AND output. Identify its operation and each of the layers. If possible, estimate the lengths and widths of each of the layers.

7.2 7.3 7.4

7.6

7.7

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Figure 7.19

2-input NOR with inverter output.

Figure 7.20

2-input NAND with inverter output.

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7.8

Figure 7.21 is a 3-input NOR gate with an inverted output. Out1 is the NOR output and Out2 is the OR output. Identify its operation and each of the layers. If possible, estimate the lengths and widths of each of the layers.

Figure 7.21

3-input NOR with inverted output.

7.9

Investigate the D-type gate and draw its equivalent transistor schematic (if you have access to the design package). Investigate other designs for the traffic light controller, such as having a separate gated oscillator for the flashing and reducing the number of states on the counter.

7.10

7.8 Projects

7.8.1 Project 1: Traffic light controller 1 Design an ASIC for a road junction with a single traffic light. The sequence and timing of each of the individual lights is outlined in Table 7.4.

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A WALK light will be active after the traffic light has completed a full sequence. This should stay active for four seconds, followed by a flashing WALK light for another four seconds (on for one second and off for one second). When this goes OFF a DON’T WALK light should be ON.
Table 7.4 Traffic light timings. Sequence RED RED/YELLOW GREEN YELLOW RED RED/YELLOW and so on. Timing (seconds) 6 1 4 2 6 1

Sequence No. 1 2 3 4 1 2

7.8.2 Project 2: Traffic light controller 2 Design an ASIC for a road junction with two traffic lights. The sequence and timing of lights is outlined in Table 7.5. A WALK light will be active after the traffic light has completed a full sequence. This light activates when pedestrians are allowed to cross the road and should stay active for 4 seconds, followed by a flashing WALK light for another 4 seconds (on for 1 second and off for 1 second). When this goes OFF the DON’T WALK light should be ON. Note that the WALK/DONT WALK lights are common to both traffic lights.
Table 7.5 Traffic light timings. Sequence (traffic light 1) RED RED RED RED RED RED/YELLOW GREEN YELLOW RED RED and so on. Sequence (traffic light 2) RED RED/YELLOW GREEN YELLOW RED RED RED RED RED RED/YELLOW and so on. Timing (seconds) 6 1 4 2 6 1 4 2 6 1

Sequence No. 1 2 3 4 5 6 7 8 1 2

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