VLSI Design I

The MOSFET model
Wow ! Are device models as nice as Cindy ?

Overview The large signal MOSFET model and second order effects. MOSFET capacitances. Introduction in fet process technology Goal: You can use the large signal equivalent MOS device equation. You are familiar with second order effects like body effect, channel length modulation. You know the MOS capacitances. You know the basic steps in MOS fabrication.
MicroLab, VLSI-2 (1/24)
JMM v1.4

Let’s build a MOSFET
There are lots of different recipes to choose from. Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation hardness, reduced latch-up and substrate noise, … are all extra cost options. We’ll consider a general process: bulk CMOS with a p-type substrate:

Use <100> surface to minimize surface charge

500um slice of a silicon ingot that has been doped with an acceptor (typically boron) to increase the concentration of holes to 1014/cm3 - 1018 /cm3.

p-type Back is metallized to provide a good ground connection.

Good for n-channel fets, but p-channel fets will need a n-type “well” (or tub) to live in!
MicroLab, VLSI-2 (2/24)
JMM v1.4

the more oomph the fet will have (we’ll see why soon) but the harder it is to make it defect free.01um = 100 Å) layer of silicon dioxide. called gate oxide. on the surface by exposing the wafer to dry oxygen. is formed on the surface by oxidation in wet oxygen. p The gate oxide needs to be of high quality: uniform thickness.Next. called field oxide. VLSI-2 (3/24) JMM v1.4 . This is then etched to expose surface where we want to make a mosfet: p Now grow a “thin” (0. a “thick” (0.4um) layer of silicon dioxide. no defects! The thinner the gate oxide. MicroLab.

is deposited by CVD. called polysilicon or poly for short. MicroLab. This is great for memory structures that have lots of poly wiring. respectively. These have sheet resistances of 1.7um thick layer of polycrystalline silicon. VLSI-2 (4/24) JMM v1.4 . The poly layer is patterned and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and drain junctions will be formed: gate oxide (only under poly) poly wires field oxide exposed surface for source and drain junctions p Poly has a high sheet resistance (25 ohms/square) which can be reduced by adding a layer of a silicided refractory metal such titanium (TiSi2). 3 or 5 ohms per square. tantalum (TaSi2) or molybdenum (MoSi2).On top of the thin oxide a 0.

25 . diffusions are “self-aligned” with poly n+ n+ wires: 20-30 ohms/sq.4 .10 ohms) n. with phosphorus (an electron donor) which creates two n-type regions in the substrate. metal wires (0. VLSI-2 (5/24) JMM v1. patterned and etched. Holes are etched in the oxide (where contacts to poly/diff are wanted) and aluminum deposited.The entire surface is doped.08 ohms/square) ??? diff contact (0. either by diffusion or ion implantation.channel MOS field effect transistor! MicroLab. The phosphorus also penetrates the poly reducing its resistance and affecting the nfet’s threshold. n+ p Finally an intermediate oxide layer is grown and then reflowed to flatten its surface.

fixed negative ions B n+ depletion layer no mobile carriers. the other is labelled S so Ids >= 0. but mostly in p area) Other symbols: S mobile electrons.NFET Operation Picture shows configuration when Vgs < Vto S G D Ids = 0 n+ p mobile holes. fixed positive ions (n+ means heavily doped with donors. but fixed negative ions (slight intrusion into n+.4 almost always ground MicroLab. doesn’t imply positive charge!) Terminal with higher voltage is labelled D. D G B JMM v1. VLSI-2 (6/24) .

FET = field effect transistor The four terminals of a fet (gate. Expect Ids proportional to Vds*(W/L)? MicroLab. a horizontal field will cause a drift current from the drain to the source. CONDUCTION: If a channel exists. drain and bulk) connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on the relative voltages of each terminal. Picture shows configuration when Vgb > Vto gate inversion happens here Eh source Ev drain bulk INVERSION: A sufficiently strong vertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain.4 . VLSI-2 (7/24) JMM v1. source.

Threshold voltage for source-bulk voltage zero: VTO ? V t ? ms ? Vfb ?? ? ? ? ?? ? ? ? Q Q VTO ? 2 ? b ? b ? ? ms ? fc ? C C ox ox 0.7V for n-channel 2 kT ln? NA ? ? ? -0. VLSI-2 (8/24) JMM v1.4 .7V for p-channel q ? n i ? ? ? ? ox t ox kT ? NDN A ? ln? 2 ? q ? ni ? ? ? 2 ? si qN A 2 ? b MicroLab.Threshold voltage The gate voltage required to form the channel is called the threshold voltage. Many factors affect the gate-source voltage at which the channel becomes conductive.

JMM v1.Body effect (second order) As Vsb increases. exposing more of the fixed acceptor (i.4 Vsb>0 T1 Vt2> Vt1 Vsb=0 MicroLab. Thus the second term in the threshold voltage equation on the previous slide increases from to 2 ? siqNA 2 ? b b 2 ? siqNA ?Vsb ? 2 ? ? the threshold voltage of the n-channel transistor is now: Vtn ? Vtn0 ? ? ? Vsb ? 2 ? b ? 2 ? b ? T2 ?? 2? siqN A C ox As we’ll see.e. this effect comes into play in series-connected fets where only one of the fets will have Vsb = 0 and the other fets will have Vsb > 0 and a higher threshold voltage. negative) ions in the substrate. the depth of the depletion region increases. VLSI-2 (9/24) .

Basic DC equations MOS transistors have 3 regions of operation: ?cutoff region (subthreshold) ?linear region (triode region) ?saturated region (active region) polysilicon gate SiO2 source diffusion W L drain diffusion Cutoff or subthreshold region: Vgs <=Vt Ids = 0 There is still a small current described in the second order effects (weak inversion). VLSI-2 (10/24) JMM v1. Important to model for analog circuits: I ds ? Vds MicroLab.4 .

Vt = Vdsat 2 Vds ? ? 2 ? fet gain factor k=µCox W ? ? ox ? I ds ? ? Vgs ? V t Vds ? L t ox ? ? ? max value at Vds = Vdsat. VLSI-2 (11/24) . but then channel is pinched off (see next slide) JMM v1. otherwise parabolic MicroLab. Channel will pinch-off.4 only linear when Vds is small.“Linear” operating region Vs Vgs > Vt 0 < Vds < Vdsat Ids L Larger Vgs creates deeper channel which increases Ids channel length is almost always min allowable mobility (un > up) Larger Vds increases drift current but also reduces vertical field component which in turn makes channel less deep. when Vds = Vgs .

VLSI-2 (12/24) JMM v1.Saturated operating region Vs Vgs > Vt Vdsat < Vds Ids Voltage at channel end remains essentially constant at Vdsat so drift current also remains constant: device is in saturation .4 .Vdsat usually reaching the drift velocity limit. Electrons arriving from source are injected into drain depletion region and accelerated towards drain by field proportional to Vds . W ? ? ox I ds ?sat ? ? Vgs ? Vt 2 L t ox ? ? 2 this is just Ids from previous slide evaluated at Vds = Vdsat MicroLab.

Channel-length modulation (second order) Vs Vgs > Vt Vdsat < Vds Ids L’ = L . As Vds increases. dL get larger As Vds increases the effective channel length gets shorter so Ids(sat) increases.. VLSI-2 (13/24) JMM v1. Shorter L’ implies greater Ids.4 . dL is proportional to Vds ? Vdsat but most people approximate channel length modulation as a linear effect: W ? ? ox I ds ?sat ? ? Vgs ? Vt 2 L t ox ? ? ?1 ? ? V 2 ds ? MicroLab.dL dL This looks just like a fet with a channel length of L’ < L..

Vds when Vgs = 0V Ids vs. VLSI-2 (14/24) JMM v1. 4 and 5V Can you find the following in the plot? Ids vs. 3. 2. Vds for Vgs = 0 . Vds when Vgs = 5V value of Vt value of Vdsat evidence of body effect evidence of channel length modulation MicroLab.4 .NFET Ids curves “Put it together and what have you got?” plot of Ids vs.1.

. .5u AS=1p AD=1p PS=3u PD=3u .75 +. . . VLSI-2 (15/24) JMM v1. M1 4 3 5 0 nfet W=1u L=0. . .SPICE Models There are different models used in circuit simulators: ? level 1 is our simple model including the most important second order effects described ?level 2 model is based on device physics ?level 3 is a semi-empirical model allowing to match equations to the real circuit: example BSIM model from Berkeley models subthreshold characteristics ?summary of the main SPICE DC parameters used in all three models at the end of this chapter .4 .MODEL nfet NMOS +TOX=1E-8 +CGB0=345p CGS0=138p CGD0=138p +CJ=775u CJSW=344p MJ=0.26 PB=0. MicroLab.35 MJSW=0. .

MOSFET Capacitance Estimation the dynamic response of MOS systems strongly depends on the parasitic capacitances associated with the MOS device.4 drain Cdb substrate Csb gate Cgd tox drain Cdb . The total load capacitance on the output of a CMOS gate is the sum of: ?gate capacitance (of other inputs connected to out) ?diffusion capacitance (of drain/source regions) ?routing capacitances (output to other inputs) Cgd gate Cgs source Cgb Cgs source Csb Cgb channel depletion layer substrate MicroLab. VLSI-2 (16/24) JMM v1.

4 .MOSFET gate capacitances Cg = Cgd + Cgs + Cgb Oxide-related capacitances come in two forms: ? overlap capacitance (extrinsic) since gate slightly overhangs diffusions and bulk: for both Cgs and Cgd amount of overlap C(overlap) = W LD Cox C(overlap) = 2L CGB0 for Cgb for SPICE Cgs = W CGS0 Cgd = W CGD0 Cgb = 2L CGB0 ?channel-charge related capacitances (intrinsic): cut-off: Cgb = Cox W L Cgs = Cgd = 0 linear: shielded by channel Cgb = 0 Cgs = Cgd = 0.5 Cox W L equally shared between S and D note capacitive coupling of gate and drain/source saturation: Cgb = 0 channel pinched off Cgd = 0 channel shortened Cgs = 0.67 Cox W L MicroLab. VLSI-2 (17/24) JMM v1.

4 .MOSFET diffusion capacitances Junction capacitances Cdb and Csb are a function of the applied terminal voltages and diffusion dimensions: source/drain diffusion xj channel sidewall faces channel bottom junction faces p-type substrate sidewalls face p+ channel stop zero-bias C/unit length of sidewall junction perimeter of diffusion zero-bias C/unit area of bottom junction area of diffusion negative for reverse biased C diff ? CjA ? Vj ? ?1 ? ? ? V ? ? b ? Mj ? C jswP ? Vj ? ?1 ? ? ? V ? ? b ? Mjsw grading coeff. junction voltage built-in junction potential grading coeff. MicroLab. VLSI-2 (18/24) JMM v1.

Don’t forget well contacts! G Terminal with lower voltage is labelled D.4 . the other is labelled S D B n-well always connected to Vdd to keep pn junction back-biased MicroLab.P-channel MOSFETs S G D p+ p+ n p threshold voltage is negative since we need attract holes to form inversion layer Other symbols: B PFET is built inside its own “substrate”: a n-type well or tub diffused into p-type bulk substrate. Vds>Vgs-Vt sat: Vgs>Vt. Vds<Vgs-Vt JMM v1. VLSI-2 (19/24) S off: Vgs > Vt lin: Vgs>Vt.

it will conduct more current as Vgs increases. depletion fets are always on. One can build logic circuits with only n-channel devices (NMOS): enhancement fets for pulldowns and depletion fets as static pullups. Since NMOS logic dissipates DC power it’s been largely replaced by CMOS.e. i. This mosfet is always conducting but. MicroLab.Depletion-mode MOSFETs S G D n+ p B n+ channel doped with donors to give negative threshold voltage.4 .. VLSI-2 (20/24) JMM v1. like ordinary enhancement fets.

Next topic… Static characteristics of MOS inverters: input and output voltages. power dissipation.23 except 2.4 (capacitances) ? CBT: Study the chip fabrication text of the university of Manchester at the MicroLab VLSI course web link.2.3 through 4.2 (process technology) and ? 4.2.2. noise margins.4 . Readings for next time… Weste: sections 2 thru 2.2.2. ? 3 thru 3.4 ..2. VLSI-2 (21/24) JMM v1.Coming Up.7 (fet models).3.. MicroLab.

381E-23 1.9 ?0 11.45E10 units F/m F/m F/m mV C J/°K cm-3 description permittivity permittivity of SiO2 permittivity of silicon kT/q (@300°K) charge of electron Boltzmann‘s constant intrinsic carrier concentration MicroLab.8 1.6022E-19 1.8542E-12 3.4 .Useful Constants sym ?0 ?ox ?Si VT q k ni value 8. VLSI-2 (22/24) JMM v1.7 ?0 25.

61 V threshold voltage TOX 1E-8 1E-8 m thin oxide thickness NSUB 4E16 4E16 cm-3 substrate doping density U0 290 78 cm2/Vs charge mobility KP A/V2 fet gain factor GAMMA V0. PHI 0.38E-10 dito F/m overlapping cap per W 1.45E-10 dito F/m overlapping cap per 2L 1. COX F/m2 oxide capacitance ? /L V-1 channel length modulat.54E-10 F/m zero-bias cap per unit P 0.26 0.5 bulk threshold param.36 grading coeff for bottom 0. CGB0 CGS0 CGD0 CJ CJSW MJ MJSW 3.27 grading coeff sidewall MicroLab.5um Process Parameters sym Vt0 tox NA ? k ? Cox ? ? ?0 2? F Cgb0 Cgs0 Cgd0 Cj Cjsw Mj Mjsw JMM v1.Alcatel 0.4 param nmos pmos units description VTO 0.15E-4 F/m2 zero-bias cap / unit A 3. VLSI-2 (23/24) . PB 0.78469 V built in junction potent.38E-10 dito F/m overlapping cap per W 7.44E-10 3.35 0.75E-4 8.77 0.1e-8 2e-8 V-1m-1 channel length mod fact.77 V surface inversion pot.7556 0.61 -0.

5? m.1 (difficulty: easy): Calculate the missing parameters on the previous transparency like intrinsic transconductance k. Cdrain=Csource=1. W=1 ? m. L= 0.35fF. P=3? m (Alatel 0. W=1? m. A=1? m2. Cox=3.5V (Alcatel 0. 9 MicroLab.5. VLSI-2 (24/24) JMM v1.5? m process).5? m process? Result: kn=100? A/V2. ?=0.45E-7 F/cm2 (see Weste pp48ff) Ex vlsi2.10: Have a look at ex 8.282V (see Weste pp55) Ex vlsi2.5 ? m Result: ? n=200 ? ? ?V2 (see Weste pp53) Ex vlsi2. L=0.4 (difficulty: easy): Calculate the capacitances of an nfet with Vsb=Vdb=3V.334V0.Exercises: VLSI-2 Ex vlsi2.5? m process) Result: dVtn = 0.3 (difficulty: easy): Calculate the transconductance ? n of an nfet (Alatel 0.2 (difficulty: easy): Calculate the threshold voltage shift due to the body effect of an nfet at Vsb = 2.9? A/V2.5? m process) Result: Cgate=2. bulk threshold parameter ? and oxide capacitance Cox of an nfet (Alatel 0.2fF (see Weste pp183-191) Weste pp99: 2.4 . kp=24.

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