9/21/2011

Implementing MATLAB and Simulink Algorithms g on FPGAs

Stefano Olivieri Senior Application Engineer MathWorks Daniele Bagni DSP Specialist EMEA Xilinx

Marco Visintini Sales Account Manager MathWorks

© 2011 The MathWorks, Inc. 1

Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45

Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up

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Introducing The Speakers
Xilinx:  Daniele Bagni DSP Specialist EMEA MathWorks:  Stefano Olvieri Senior Application Engineer Signal Processing and Communication

Marco Visintini Sales Account Manager
3

MathWorks and Xilinx Goals

MathWorks: accelerate the pace of engineering and science by providing best in class Software for:
– De elopment and verification of algorithms and control logic Development erification – Embedded Systems implementation

Xilinx: providing best in class Silicon including FPGAs and embedded system hardware platforms :
– Offers FPGAs and Zynq – an Extensible Processing Platform – P t Partner with MathWorks to provide an integrated workflow ith M thW k t id i t t d kfl

Purpose of the joint seminar:
– to demonstrate a Model-Based Design workflow for FPGAs from first idea down to the Hardware.
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MathWorks at a Glance

Headquarters: Natick, Massachusetts US N ti k M h tt Other US Locations: California, Michigan, Texas, Washington DC Europe: France, Germany, Italy, Spain, the Netherlands, Sweden, Switzerland, UK Asia-Pacific: Australia, China, India, Japan, Korea Worldwide training and consulting Distributors in 25 countries
5 Earth’s topography on an equidistant cylindrical projection, created with MATLAB and Mapping Toolbox.

MathWorks Today
   

Revenues ~$600M in 2010 Privately held More than 2000 employees worldwide Worldwide revenue balance: 45% North America, 55% international More than 1 million users in 175+ countries

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Key Industries

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Aerospace and Defense Automotive Biotech and Pharmaceutical Communications Education Electronics and Semiconductors Energy Production Financial Services Industrial Automation and Machinery

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Who is Who???

Who is a System Engineer? Who is Wh i an FPGA designers ? d i Who is using MATLAB? Who is using Simulink?

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Your Expectations Beyond the Agenda...

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Corner Detection in Video Mosaicking (A Brief Example)

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Things to remember ….
DESIGN

Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time

Algorithm Development

MATLAB Simulink Stateflow

14

Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45

Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up

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9/21/2011

Why do we use FPGAs?

Customized interfaces to peripherals High-speed communication interfaces to other processors Finite state machines, digital logic, timing and memory control High speed, highly parallel DSP Algorithms or Control Algorithms
Analog I/O Memory Memory Memory

We are going to focus on this use case today

Bridge

FPGA
Digital I/O

ARM

DSP DSP Algorithms

16

Separate Views of DSP Implementation
System Designer FPGA Designer

Algorithm Design
Fixed-Point Timing / Control Logic Architecture Exploration Algorithms / IP

System Test Bench
Environment Models Analog Models Digital Models Algorithms / IP

RTL Design
IP Interfaces HW Architecture

Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation

Implement Design FPGA Requirements
Hardware Specification Test Stimulus Synthesis Map Place & Route

Back Annotation

FPGA Hardware

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9/21/2011

Where do you spend most of your time?
System Designer
 
Algorithm Design
Fixed-Point Timing / Control Logic Architecture Exploration Algorithms / IP

System Test Bench
Environment Models Analog Models Digital Models Algorithms / IP

  

FPGA Requirements
Hardware Specification Test Stimulus

Simulating designs? Creating designs and test benches? Analyzing and combining results from multiple tools? Exploring implementation ideas and architectures? Floating point to fixed-point? Writing HW specifications? Iterating over designs with the FPGA designer? Blaming the FPGA designer?

 

18

Where do you spend most of your time?
    

Simulating designs and validating against HW specs? Creating designs and writing test benches? Hardware architecture design? Writing interfaces to existing IP? Synthesis, Map, PAR cycles? Iterating over designs with the system designer? Blaming the system designer?

FPGA Designer

RTL Design
IP Interfaces Hardware Architecture

Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation

Implement Design

Back Annotation

 

Synthesis Map ap Place & Route

FPGA Hardware

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A Few Ways to Reduce Development Time
1. 2.

3.

4.

Increase simulation speed Simplify design entry, system test harness creation, and exploration Shorter iteration cycles required for RTL design & verification Integrate the separate workflows to facilitate collaboration, re-use, and prototyping

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Model-Based Design for Implementation
MATLAB® and Simulink® Algorithm and System Design
Algorithm Design
Fixed-Point Timing / Control Logic Architecture Exploration Algorithms / IP

System Test Bench
Environment Models Analog Models Digital Models Algorithms / IP

RTL Design
IP Interfaces Hardware Architecture

Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation

Implement Design FPGA Requirements
Hardware Specification Test Stimulus Synthesis Map Place & Route

Back Annotation

FPGA Hardware

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Model-Based Design for Implementation
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

RTL Design
IP Interfaces

Verification
Behavioral Simulation Functional Simulation Static Timing Analysis Timing Simulation

Automatic HDL Code Generation

Hardware Architecture

Implement Design
Synthesis Map Place & Route

Back Annotation

FPGA Hardware

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Model-Based Design for Implementation
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Verification
Behavioral Simulation

Automatic HDL Code Generation

Functional Simulation

HDL Co-Simulation Co-

Static Timing Analysis Timing Simulation

Behavioral Simulation

Implement Design
Synthesis Map Place & Route

Back Annotation

FPGA Hardware

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Model-Based Design for Implementation
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Verification

Automatic HDL Code Generation

Functional Simulation

HDL Co-Simulation Co-

Static Timing Analysis Timing Simulation

Behavioral Simulation

Implement Design
Back Annotation Synthesis Map

Back Annotation

Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation

Place & Route

FPGA Hardware

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Model-Based Design for Implementation
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Automatic HDL Code Generation

HDL Co-Simulation Co-

Behavioral Simulation

Back Annotation

Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation

FPGA Hardware

FPGA Hardware FPGA-in-theFPGA-in-the-Loop
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Why Model-Based Design?
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles Integrate FPGA development tools to reduce verification time 27

Automatic HDL Code Generation

HDL Co-Simulation Co-

Behavioral Simulation

Back Annotation


Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation


FPGA Hardware FPGA-in-theFPGA-in-the-Loop

AT4 wireless Increases Internal Test Coverage to Over 90% for LTE Physical Layer Test Equipment Designs
Ch ll Challenge
Develop test systems for LTE wireless equipment
AT4 wireless LTE layer 1 tester.

Solution
Use MATLAB and Simulink to design and simulate the LTE physical layer, verify the FPGA implementation, and analyze test results
“MATLAB is a universal language that makes it easy to exchange algorithms and test results across our team. Our physical layer model in MATLAB and Simulink enabled us to better understand the LTE specifications, and Model-Based Design enabled us to verify that our FPGA implementation conformed to those specifications.”
Francisco Javier Campos AT4 wireless
Link to user story

Results
 Internal test coverage increased to over 90%  Test harness reused throughout the project life cycle  Development effort reduced by 25–30%

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Semtech Speeds Development of Digital Receiver FPGAs and ASICs

Challenge g
Accelerate the development of optimized digital receiver chains for wireless RF devices
The Semtech SX1231 wireless transceiver.

Solution
Use MathWorks tools for Model-Based Design to generate production VHDL code for rapid FPGA and ASIC implementation
“Writing VHDL is tedious, and the handwritten code still needs to be verified. With Simulink and Simulink HDL Coder, once we have simulated the model we can generate VHDL directly and prototype an FPGA. It saves a lot of time, and the generated code contains some optimizations we hadn’t thought of.”
Frantz Prianon Semtech
Link to user story

Results
 Prototypes created 50% faster  Verification time reduced from weeks to days  Optimized, better-performing design delivered

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Case Study: Corner Detection Algorithm

© 2011 The MathWorks, Inc. 31

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Harris-Stephens’ Corner Detection

Corner detection is used in many Image Processing applications
– Image mosaicking – Tracking – Object recognition

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Harris-Stephens’ Corner Detection
Horizontal Gradient

Corner Metric Mc Vertical Gradient

Sobel Edge Filter

Calculate Corner Metrics

Threshold & Find Local Maxima
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From Algorithm to Synthesizable RTL
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Automatic HDL Code Generation

HDL Co-Simulation Co-

Behavioral Simulation

Back Annotation

Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation

FPGA Hardware FPGA-in-theFPGA-in-the-Loop
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Flexible Design Environment
Design, Simulation and Implementation

 

Choice of best modeling methods (Simulink, MATLAB and Stateflow) Integrate with MATLAB Algorithm Design
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Fixed Point Analysis
Corner Detection

Convert floating point to optimized fixed point models
– Automatic tracking of signal range (also intermediate quantities) – Word / Fraction lengths recommendation Automatically

Bit-true models in the same environment

identify and solve fixed point issues

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Automatic HDL Code Generation
Corner Detection

Automatically generate bit true, cycle accurate HDL code from Simulink, MATLAB and Stateflow

Full bi-directional traceability!!

Requirements

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9/21/2011

Simulink Library Support for HDL
HDL Supported Blocks

170 blocks supported Core Simulink Blocks
– Basic and Array Arithmetic, Look-Up Tables, Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs

Signal Processing Blocks
– NCOs, FFTs, Digital Filters (FIR, IIR, Multi, , g ( , , rate, Adaptive), Rate Changes (Up &Down Sample), Statistics (Min/Max)

Communications Blocks
– Psuedo-random Sequence Generators, Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders

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MATLAB & Stateflow for HDL
HDL Supported Blocks

MATLAB
– Relevant subset of the MATLAB language for modeling and generating HDL implementations – eml_hdl_design_patterns: Useful MATLAB Function Block Design Patterns for HDL

Stateflow
– Graphical tool for modeling Mealy and Moore Finite State Machines

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Integrating Legacy HDL Code
HDL Supported Blocks
Integrate legacy HDL code in Simulink using black boxes

Configure the interface to legacy HDL code

EDA Simulator Link is a special black box
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Summary: Modeling and Code Generation

Model-Based Design provides an integrated workflow
– Optimized design on a System Level

Speed up algorithm development with a unified design environment
– Collaborate with other engineers – Use Simulink blocks, Stateflow or MATLAB for modeling and implementation

Shorter iteration cycles
– Assisted Fixed-Point Conversion – Automatic HDL Code Generation
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9/21/2011

Break

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Things to remember ….
DESIGN

Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time

Algorithm Development

MATLAB Simulink Stateflow

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9/21/2011

What Wh t would you like to get ld lik t t from automatic code generation?

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Hardware Design Challenges:
Optimizing for Speed, Area or Power
DESIGN

Algorithm Development

MATLAB Simulink Stateflow

Optimize HDL code Verify optimized HDL Place & Route Analyze result

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IIR Low Pass Filter
Direct-Form II Transposed SOS

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From Algorithm to Optimized RTL
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Automatic HDL Code Generation

HDL Co-Simulation Co-

Behavioral Simulation

Back Annotation

Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation

FPGA Hardware FPGA-in-theFPGA-in-the-Loop
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9/21/2011

Hardware Design Challenges:
Speed Optimization

Finding the critical path in your model can be challenging

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Demo: HDL Workflow Advisor
>> Choose target workflow:
• • • FPGA-in-the-Loop FPGA Turnkey Design exploration: Generic ASIC/FPGA

Choose FPGA target

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Demo: HDL Workflow Advisor
Perform relevant checks for HDL code generation

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Demo: HDL Workflow Advisor
Set options and generate automatically HDL code

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Demo: HDL Workflow Advisor
Create FPGA project Run P&R -andAnnotate timing information

Automated workflow  from model to FPGA Analysis & Implementation
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Identifying the critical path
Speed Optimization

Critical Path highlighting:  Visual representation of critical path in your model  Easier to identify bottlenecks of your model
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9/21/2011

Balancing pipeline registers
Speed Optimization

parallel paths

critical path

 

Multiple parallel paths through your model High risk to have unmatched latencies
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Demo: Configuring Pipelining Options
Speed Optimization

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9/21/2011

Distributed Pipelining
Speed Optimization

  

Distributed pipelining (model retiming) Automatic balancing of pipeline registers (focus on critical path only) You are in full control of your pipelining strategy  Bottom-up and top-down
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Distributed Pipelining
Speed Optimization
Minimum period: 23.796ns Maximum Frequency: 42.024MHz 42 024MHz

Section 1

Section 3

Section 2

Device,package,speed: xc5vsx50t,ff1136,-1

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Distributed Pipelining
Speed Optimization
Minimum period: 9.379ns Maximum Frequency: 106.62MHz 106 62MHz

Section 3

Device,package,speed: xc5vsx50t,ff1136,-1

Section 2
58

Hardware Design Challenges:
Area Optimization

MUX

SCHEDULING

X X

X X
DEMUX

X X

X X

X X X X

X X X X

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IIR Low Pass Filter
Direct-Form II Transposed SOS

Challenges:  Data dependent resources to be shared  Feedback loops  Vectorized inputs
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Demo: Configuring Sharing Options
Area Optimization

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Resource Sharing and Streaming
Area Optimization
  

Easy to explore different sharing options Direct feedback through resource utilization report Prove correctness through validation models

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Hardware Design Challenges:
Power Optimization

Power Dissipation = Static Power + Dynamic Power
– Static Power = Due to transistor leakage current

Significant in smaller silicon geometries

– Dynamic Power = CV2f

Function of load capacitance, operating frequency, and voltage swing

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Better Algorithm Design
Power Optimization

Steps To Reduce Power
– – – – Smaller/Efficient Designs Reduce Clock Frequency Control Subsystem Execution (enabled/triggered subsystems) Low Power Design Libraries/FPGA Devices

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Multi-rate Models to Reduce Clock Frequency Power Optimization
 

Cycle accurate simulation and implementation Multiple or single clock implementation p g p

clk_enable clk

enb_1_2_1

clk_enable

Timing Controller
enb_1_2_0
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Control Subsystem Execution
Power Optimization
Enabled Subsystems

Modules can be enabled and disabled

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Control Subsystem Execution
Power Optimization
Triggered Subsystems

Modules can be triggered: rising / falling / either edge gg g g g

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Harris-Stephens’ Corner Detection

How do these techniques work with our Corner Detection algorithm??

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Summary: Corner Detection Demo

Multipliers Adders/Subtractors Registers RAMs Multiplexers

154 90 852 0 2

Multipliers Adders/Subtractors Registers RAMs Multiplexers

6 46 679 4 302

 

Easy approach to explore different implementations No costly mistakes
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Summary: Code Generation Optimizations

Shorter iteration cycles
– Automatic HDL code generation

Flexible automatic HDL Code generation
– – – – –

Speed Optimization Area Optimization Make the right design choices to save power Analyze implementation results, resource utilization report Validation models to prove that implementation is correct

71

Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45

Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up

72

33

9/21/2011

Things to remember ….
DESIGN

Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time

Algorithm Development

MATLAB Simulink Stateflow

73

HDL Verification

How do you do HDL verification today? y y

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Verification Challenges:
HDL Verification

  

Design the Test Bench twice

10 – to – 1 ratio of Test bench LOC – to – Design LOC

Many stimuli-files from MATLAB These are ideal references which require pre- and postprocessing How to analyze results?

75

Verification Challenges:
HDL Verification

Demo: Re-Use System Level Test Bench
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Digital Down Converter

 

DDC accepts p
– A high sample-rate passband signal (may be 50 to 100 Msps)

DDC produces
– A low sample-rate baseband signal ready for demodulation ~70 MSPS ~270 KSPS
Digital Down Converter

RF Section

A/D Conv

Demod

77

Integrated HDL Verification
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Automatic HDL Code Generation

HDL Co-Simulation Co-

Behavioral Simulation

Back Annotation

Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation

FPGA Hardware FPGA-in-theFPGA-in-the-Loop
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Verify Handwritten HDL Vector-Based
Digital Down Converter
What is the impact of these differences?

Difficult to analyze simulation results
79

Co-Simulation with HDL simulators
Digital Down Converter
Re-use system level test bench Flexible testbench creation in Simulink

Direct simulation link to HDL Simulators

Automatically generated HDL co-simulation models

Difference is small and in the stopband of the filter
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Additional Methods for Verification
HDL Verification Techniques

Co-simulation with MATLAB
– Test Bench – Component

Generate vector based test benches for standalone verification FPGA-in-the-Loop

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Integrate MATLAB Algorithm Development Co-Simulation with MATLAB
MATLAB

Test Bench

Verify HDL against high-level high level MATLAB design

HDL Simulator

Component

Replace a “Broken” or un-finished R l “B k ” fi i h d block in a full HDL test bench with a working high level component Test alternate algorithms for system trade-off without developing HDL
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Harris Accelerates Verification of Signal Processing FPGAs

Ch ll Challenge
Streamline a time-consuming manual process for testing signal processing FPGA implementation
Harris FPGA-based system.

Solution
Use EDA Simulator Link to verify the HDL design from within MATLAB
“EDA Simulator Link enabled us to greatly reduce functional verification development time by providing a direct cosimulation interface between our MATLAB model and our logic simulator. As a result, we verified our design earlier, identified problems faster, completed more tests, and compressed our entire development cycle.”
Jason Plew Harris Corporation
Link to user story

Results
 Functional verification time cut by more than 85%  100% of planned test cases completed  Design implemented defect-free

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Collaborate with Other Design Teams
Test Benches for Standalone Verification
Compile and simulation scripts are provided

Automatically generate self-checking test benches

Can be used in any HDL Simulator
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Challenges:
Testing algorithms on real hardware

  

Motivation: building confidence But …… interfaces with peripherals p p & rest of the system needed Difficult to construct testbenches in real hardware

Demo: Re-Use System Level test bench
86

FPGA-in-the-Loop verification
Digital Down Converter
Integration with FPGA development boards

Automatic creation of FPGA-in-the-Loop verification models

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FPGA-in-the-Loop verification
Digital Down Converter

Re-use system level test bench for FPGA verification Flexible testbench creation in Simulink

Building confidence that the design works on real hardware
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Summary: Verification

Integration of FPGA development tools enhances verification

Improved analysis, flexible testbench creation (multi domain, feedback loops) Integration with HDL verification Integration with FPGA verification

– –

Automation gives A tomation gi es shorter iteration c cles cycles
– Automatically generated verification models for:
 

HDL Co-Simulation FPGA-in-the-Loop

– Wizards for legacy HDL code
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From Algorithm to FPGA Implementation
MATLAB® and Simulink® Algorithm and System Design Model Refinement for Hardware

Simulink HDL Coder RTL Creation

EDA Simulator Link ModelSim HDL Co-Simulation Co-

Behavioral Simulation

Back Annotation

Implement Design
Synthesis Map Place & Route

Verification
Functional Simulation Static Timing Analysis Timing Simulation

EDA Simulator Link FPGA-in-theFPGA-in-the-Loop 90

Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45

Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up

91

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Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45

Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up

92

Agenda
9:45 10:00 11:00 11:15 12:00 13:15 14:15 15:45

Welcome Reduce FPGA Development Time with Model-Based Design p g Break Integrated HDL Verification Xilinx Target-optimized FPGA Design Using MATLAB and Simulink Lunch FPGA Design Optimization Techniques Q&A, Summary and Wrap-up

93

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9/21/2011

Things to remember ….
DESIGN

Use Model-Based Design to provide an integrated workflow Speed up algorithm development with a unified design environment Automate manual steps in FPGA implementation to enable shorter iteration cycles y Integrate FPGA development tools to reduce verification time

Algorithm Development

MATLAB Simulink Stateflow

94

ROI: Customer Adoption Of Model-Based Design
Time spent on FPGA/ASIC implementation
  

Shorter implementation time by 48% (total project 33%) Reduced FPGA prototype development schedule by 47% Shorter design iteration cycle by 80%
1st FPGA Prototype 2nd FPGA Prototype

1st FPGA Prototype

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How to adopt MathWorks technologies?

 

MathWorks tools provide a technology to speed up p gy p p development MathWorks services provide the support to roll out this technology in your organization

96

Example MathWorks Services

MathWorks Training
– Private training “Simulink HDL Coder” – Public training “Signal Processing with MATLAB/Simulink Signal MATLAB/Simulink” Fundamental trainings for uniform knowledge, quick ramp up

MathWorks Consulting
– Jumpstart service to get you up and running quickly with Simulink HDL Coder – Advisory service for ongoing expert advice during technology adoption – Based on industry experience, assistance with tailoring workflow – On site expert customization / optimization of your workflow

Technical Support
– Comprehensive, product-specific Web support resources – 70% cases solved within 24 hours – Included in Software Maintenance Service
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Were Your Expectations Met?

Please complete and return seminar survey forms Your comments and feedback are very important to us

99

Next Steps …

1.

2.

Visit www.mathworks.com/fpga pg for more information Visit www.xilinx.com/dsp for more information

3.

Watch our FPGA webinars: – www.mathworks.com/company/events/webinars th k / / t / bi Contact your local sales reps for a trial of our FPGA tools

4.

Questions?
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