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CS/JAN 2012/ITT430




INSTRUCTIONS TO CANDIDATES 1. The question paper consists of three (3) parts: PART A (25 Questions) PART B (25 Questions) PART C (6 Questions)

Answer i) ii) iii)

ALL questions from all three (3) parts. Answer Part A in the Objective Answer Sheet Answer Part B in the True / False Answer Sheet Answer Part C in the Answer Booklet. Start each answer on a new page.

Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) the Question Paper ii) an Answer Booklet - provided by the Faculty iii) a True / False Answer Sheet - provided by the Faculty iv) an Objective Answer Sheet - provided by the Faculty

This examination paper consists of 13 printed pages
© Hak Cipta Universiti Teknologi MARA CONFIDENTIAL

B. JUMP CALL INT RET 5. B. Determine the value of the word stored in memory starting at address 0A00BH and whether it is an aligned or misaligned word. 0012H CONFIDENTIAL © Hak Cipta Universiti Teknologi MARA . D. C. 12H" is A. and 4ie respectively. B. D. A. The size of the machine code for the assembly instruction "MOV CX. 0080H BX. The following operation will require the stack A. 3ie. register indirect addressing mode indexed addressing mode based addressing mode based-indexed addressing mode 4. 0082H BX. C. AND AND AND AND DX. OAOODie. choose ONE (1) suitable answer and mark the answer on the Objective Answer Sheet provided. 2 3 4 5 bytes bytes bytes bytes 2. and OAOOEieare lie. The contents of memory locations OAOOBie. D. 0042H DX. OAOOOe. 2ie. 1. C. Instruction MOV [BX][DI]+2H. B. 10203040ie and aligned word 10203040i6 and misaligned word 201 is and aligned word 20116 and misaligned word 3. D. C. The destination operand is accessed using A. C.CONFIDENTIAL 2 CS/JAN 2012/ITT430 PART A (25 MARKS) For each of the following questions. D. AH. B. The instruction that when executed will mask off all but bit 4 and bit 1 of the base register is A.

19H 29H 59H 69H 7. 0103 ROL DX. DX = DX = DX = DX = 091CH 91C0H 0C74H C740H The following statements are TRUE EXCEPT I II III DMA capability permits devices such as peripherals to perform high speed data transfer between memories or memory and I/O devices. D. D. DMA mode of operation is frequently used when blocks or packets of data are to be transferred. B. II and III None of the above A. D. 10 11 8.CONFIDENTIAL 3 CS/JAN 2012/ITT430 6. B. CL DEBUG trace is A. © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . The result after executing the following instructions in the MOV DX. 8123H MOV CX. the output on S4S3 when a fetch to the stack segment is in progress will be A. If the ASCII representation for character " I " is 49H. the ASCII representation for character "i" is A. C. The memory or I/O bus cycles initiated as part of a DMA transfer are not performed by the MPU. D. C. In a minimum-mode 8088 microcomputer. 00 01 C. I and II I and III I. B. B. 9. C.

B. D. PC. The status flags will be shown after executing the following instructions in the trace is MOV AL. 14. The following interrupt group is user defined EXCEPT A. . D. Assuming that (AX)=0123H and (BL)=02H. Hardware Interrupts Software Interrupts Internal Interrupts Nonmaskable Interrupts 13. B. B. C. AH = 01H AL = 01H AH = 91H AL = 91H 12.2 H DEBUG A. = 1 PC 2 =0 PC 3 =1 PC 4 =0 11. D. 12H ADD AH. 27H CMP AL. C. D. C. NV UP El NV UP El NV UP El NV UP El PL NZ NA PE NC PL NZ NA PE CY NG NZ NA PO CY PL NZ AC PE CY The content of AH register to invoke the interrupt 21H so that it display data to the screen is A. B. the remainder after executing the instruction " D I V B L " in the DEBUG trace is A. B.CONFIDENTIAL 10. (AH)=03H (AH)=05H (AH)=07H (AH)=09H © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . D. C. the port C affected by the operation is A. C. 4 CS/JAN 2012/ITT430 If the value 0416 is written to the control register of an 82C55A set for mode 2.

The key differences between NMI and the other external hardware initiated interrupts are I II III A. The duration of the bus cycle in the 8088-based microcomputer if the clock is 8 MHz and two wait states are inserted is A. B. B. Memory mapped I/O operation is generally faster than isolated I/O operation I II C. Port 0 Port 2 Port 4 None of the above 18. I and II I and III II and III I. The following statements are true EXCEPT I II III A. Ill I and III 16. C. C. B. 500 ns 625 ns 750 ns 875 ns In a sixty-four-line parallel output circuit for an 8088-based microcomputer.CONFIDENTIAL 5 CS/JAN 2012/ITT430 15. 17. II and III © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . B. if the address put on the bus during an output bus cycle is 800A16. NMI input is edge-triggered instead of level sensitive. Memory mapped I/O devices can reside anywhere in the 1 Mbyte memory address space of the 8088. D. D. NMI is masked out by IF NMI is initiated from the NMI input lead instead of from the INTR input. the output port that the data will be written to is A. memory read and write bus cycles are initiated instead of I/O bus cycles. During I/O operation in memory mapped I/O. C. D. D.

C. 88H 89H C8H C9H 22.CONFIDENTIAL 6 CS/JAN 2012/ITT430 19. D. read I/O port write I/O port halt instruction fetch 20. the bus activity that is taking place is A.. 2 0OH DEC CX NOP LOOP DLY DLY: NXT: A. Signals IO/M and DT/R are set to 1 and 0 logic levels respectively at the start of T-. B. Status bits S3 through S6 are output on the upper four address bus lines Ai 6 through A19 at the beginning of T2. D. Signal RD is switched to logic 1 at the later part of T2. II. B. If the bus status code SaSiSo equals 100. The value to be written to the control register of the 82C55A to configure the device such that port A and port B are configured as output ports and port C is set up as input port in mode 0 operation is A. I and II I and III II and III I. C. B. III. D. C. and III 21. 128 255 256 512 times times times times © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . A. D. The "NOP" instruction is executed for MOV CX. C. This program is referred as a delay program. II. B. The following statements are TRUE I.

DEBUG State the value of the flag register after executing the following instructions in the trace MOV A X . Determine the address of the vector specified by CS75:IP75. C. In a sixty-four-line parallel output circuit for an 8088-based microcomputer. SUB A X . NV UP El NG NZ NA PE NC NV UP El PL NZ AC PO NC NV UP El NG NZ NA PO NC NV UP El PL NZ AC PE NC 25. A. B. if the address put on the bus during an output bus cycle is 800A16. C. D. C. (CS) (CS) (CS) (CS) = 96H and (IP) = 98H = 75H and (IP) = 75H = 98H and (IP) = 96H = 12EHand(IP) = 12CH © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . B. B. ABCDH 1234H A. Port 1 Port 3 Port 5 Port 7 24. the output port that the data will be written to will be A.CONFIDENTIAL 7 CS/JAN 2012/ITT430 23. D. D.

framing. 7. the content of the DS register is initialized to 0000. 8. A USART has the ability to automatically check characters during data reception to detect automatically the occurrence of parity. the new contents of AX after executing the instruction "IMUL AL" is 0144H. The number of bus cycle required for writing a word at memory address 012AAie of an 8088-based microcomputer is two bus cycle. the effective address is obtained from the contents of either BX or BP registers. 2.CONFIDENTIAL 8 CS/JAN 2012/ITT430 PART B (25 MARKS) For each of the following questions. it initiates its internal initialization routine and flags are all cleared. The two separate internal processing units within the 8088/8086 microprocessor are Execution Unit (EU) and Bus Interface Unit (BIU). 1. answer either TRUE or FALSE and mark your answer on the TRUE/FALSE Answer Sheet provided. 11. Assuming that (AX) = FFF2H. 6. 10. In based addressing mode. © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . In maximum mode. and overrun errors. 5. As a result of this process. Pointer and index registers can be accessed either as a whole 16 bits for word data operations or as two 8-bit registers for byte-wide data operations. The control word to configure the 82C55A so that all ports are input ports arid are set up for mode 0 operation is 9AH. 9. 13. Executing the instruction "JMP BX" will not affect the flag register. Microprocessors operate with a crystal-controlled clock signal that is responsible for the timing. 14. When the MPU recognizes the RESET input. the empty bits are filled with the sign bit. the 8088 has an external bus controller for interfacing to memory and I/O devices. 4. 12. either the complete memory array or a large block of storage locations is erased. 3. When an erase operation is performed on a FLASH memory. as the bits of the destination are shifted to the right into CF. Each phase of the instruction cycle requires a given number of clock cycles. In RCR (rotate right through carry). The VF flag register bit is set as a result of the last arithmetic operation being negative.

19. If (SP)=44FCH. 17. The condition tested for JNE and JZ instructions is similar. then the output P4 will be activated. 25. when a byte of data is being written to I/O address 20001H. 23. 22. The 8288 Bus Controller is used to provide control signals for the 8088/8086 when it is operating in minimum mode. the logic level of A0 and BHE are 1 and 0 respectively. The IP and CS registers have their contents changed during an intrasegment jump. The trap flag (TF) is reset so that the address is automatically incremented for the subroutine operation. If the inputs to a 74F138 decoder are Gi=1. and CBA=110forthe I/O address decoding. © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . The maximum number of repeats that can be implemented with a loop instruction is 65535. The 82C37A has two priority schemes: fixed priority and rotating priority that can be selected under software control.0008016. 24. 21. G2A=0. 16.CONFIDENTIAL 9 CS/JAN 2012/ITT430 15. In an 8086-base microcomputer. The reserved memory which are saved for the storage of the pointers that are used for the 8088's user-defined interrupts are located at 00014 16 . the offset address of the first location of the stack that is available to push data into is 44FAH. 20. 18. G2B=0. Treating a peripheral device like a memory location is referred to as isolated memory mapping.

QUESTION 1 Encode (in hexadecimal) the following instructions using the information given in Table 1 and Table 2. MOV and LES operations are 001010.CONFIDENTIAL 10 CS/JAN 2012/ITT430 PART C (50 MARKS) Answer ALL questions. [ S I ] (2 marks) C) ADD [BP] +85H . Assume that the opcode for the SUB. address (BP)+D8 (BP)+D16 DI 111 (DX) (DX)+D8 (DX)+D16 Table 2: Register/Memory Encoding Field © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . AX (2 marks) REG 000 001 010 011 100 101 110 111 W=1 AL AX CL CX DL DX BL DX AH SP CH BP DH SI BH DI Table 1: Register Field Encoding w=o MOD=l 1 R/M w=o 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH EFFECTIVE ADDRESS CALCULATION W=l MOD=01 MOD=10 R/M MOD=00 (DX)+(SI)+D16 AX 000 (DX)+(SI)+D8 (DX)+(SI) CX 001 (DX)+(DI) (DX)+(DI)+D8 (DX)+(DI)+D16 DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16 DX 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16 SP 100 (SI) (SI)+D8 (SI) +D16 BP 101 (DI) (DI)+D8 (DI)+D16 SI 110 Dir. 12CDH (2 marks) b) XCHG BX. 100010 and 11000100 respectively. a) MOV WORD PTR [BX] [DI] + 4815.

a) POP AX (2 marks) b) PUSH AX (2 marks) c) POPF (2 marks) d) PUSHF (2 marks) QUESTION 3 a) Write an equivalent instruction sequence to replace the usage of string instruction for each of the following short program: i) CLD LODSB STOSB (4 marks) ii) MOV AX.CONFIDENTIAL 11 CS/JAN 2012/ITT430 QUESTION 2 Describe the operation performed by the following stack related instructions. (2 marks) Name the flag related to the instruction CLD and STD. AX STD CMPSW (4 marks) b) Name TWO(2) other string instructions of the 8088 instruction set beside found in a). DS MOV ES. (1 mark) c) © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL .

CL. i) Determine the physical address of the related memory location. (2 marks) b) MOV BX. a) RCL BYTE PTR [DI]+10H. F0F0H CLC MOV CL. MOV CL. STC SAR BX. CL i) Determine the output of the accumulator (2 marks) © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . 8A3BH 3 CL i) Determine the output of BX (2 marks) C) MOV AX.CONFIDENTIAL 12 CS/JAN 2012/ITT430 QUESTION 4 Assume that the contents of registers and memory are as follows (all in hex): AX = 0010 SI = 0100 IP = 010F (DS: :100) (DS: :200) :201) (DS: :210) (DS: (DS: :211) (DS: :220) (DS: :221) (DS: :400) :401) (DS: BX = 0220 CX = 0105 DX = 1234 DI = 0200 DS = 136A ES = 136A NV UP EI PL NZ NA PO NC = = = = = = = = = 0AH 33H 55H 66H BBH BBH 66H BBH 66H SP = FFEE BP = ABCD SS =136A CS =136A Observe the following instructions and answer accordingly. (1 mark) ii) Determine the output stored in the specified memory location. 5 RCR AX.

The content of all the 32. The address of port 3 is given as 8006H. (6 marks) Determine the number of bus cycle involved for the above transfer. (8 marks) Write an instruction sequence that inputs the byte contents of input port 3 to the memory location PORT_3.bit binary inputs are pointed by the source index register. the memory address spaces of the 8088 and 8086 based microcomputers are organized differently. a) Explain with respect to bus cycle. Therefore. (3 marks) b) END OF QUESTION PAPER © Hak Cipta Universiti Teknologi MARA CONFIDENTIAL . (1 mark) b) QUESTION 6 a) Write a program that performs a 32-bit binary addition.CONFIDENTIAL 13 CS/JAN 2012/ITT430 QUESTION 5 The 8088 and 8086 based microcomputer memory subsystems are implemented differently. Once the addition is performed. when a word of data is transferred to the storage location at 0ABC5H of the 8086 memory subsystem using diagram. the output of the 32-bit addition is stored at the memory location pointed by the destination index register.