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Common-Base Configuration (CB) The CB configuration having a low input and high output impedance and a current gain

less than 1, the voltage gain can be quite large, ro in MΩ so that ignored in parallel with RC

Fig6-22 CB configuration Zi

Fig6-23 re equivalent circuit

[6-54] Zo [6-55] Av

[6-56] Ai Assuming RE >> re

[6-57] Phase Relationship: the resulting equation for the Av is a positive reveals that the output Vo and input Vi are in phase for the common-base configuration Example 8: For the network in fig 6-24

Fig6-24 Ex 8 Solution: IE

114

re Zi

Zo Av

Ai

Collector Feedback Configuration (CE A feedback path from collector to base increased the stability of the system

Fig6-25 feedback configuration Zi

Fig6-26 re model into network of fig6-25

115

the effect of βre is removed and RF appears in parallel with RC [6-59] Av at node C of Fig 6-26 [6-60] Ai Applying KVL around the outside network loop 116 .[6-58] Zo to define Zo set Vi to zero .

Ignoring βre compared to RF and βRC gives us [6-61] βRC >> RF [6-62] Phase Relationship: the negative sign in the resulting equation for the Av reveals that a 180 º phase shift occurs between the output VO and input Vi Example 9: For the network of fig6-27 determine Fig6-27 Example 9: Solution: IB IE re Zi Zo Av Ai 117 .

Fig6-29 Collector dc feedback Zi Fig6-30 re equivalent circuit of the network [6-67] Zo [6-68] For ro ≥ 10RC 118 .For the configuration of Fig6-28. will determine the variables Fig6-28 Collector feedback configuration Zi [6-63] Zo [6-64] Av [6-65] Ai [6-66] Collector DC feedback Configuration (CE) The dc feedback resistor increased stability. C3 will shift portions of the feedback resistance to the input and output sections of the network in the ac domain.

[6-69] Av [6-70] For ro ≥ 10RC [6-71] Ai for the input side [6-72] [6-73] Or [6-74] Phase Relationship: the negative sign in the resulting equation for the Av reveals that a 180 º phase shift occurs between the output VO and input Vi 119 .

Example 10: For the network of fig6-31 determine: Fig6-31 Example 10 Solution: DC testing: IB IE re βre Zi F ig6-32 re equivalent Testing the condition ro ≥ 10RC we find It is satisfied So Zo 120 .

Approximate Hybrid Equivalent Circuit Fig6-33 Approximate CE hybrid circuit hie = βre hfe =β hoe= 1/ro hfb= -α hib =re Fixed-Bias Configuration (CE) Fig 6-34 Approximate CB hybrid circuit Fig 6-35fixed-bias configuration Zi Fig6-36 approximate hybrid equivalent circuit [6-75] Zo [6-76] Av [6-77] Ai Assuming that RB >> hie and 1/ hoe ≥10RC. then Ib ≈ Ii and IO = IC = hfe Ib = hfe Ii with [6-78] Example 11: For the network of fig6-37. determine 121 .

Fig6-37 Example 11: Solution: Voltage-Divider Configuration (CE bypassed) Fig6-38Voltage-dividerbiasconfiguration Zi RB=R' [6-79] Zo [6-80] Av [6-81] Ai [6-82] Unbypassed Emitter-Bias Configuration (CE) βre replaced by hie and βIb by hfeIb . The analysis will proceed in the manner 122 .

[6-92] Fig6-40Emitter-follower configuration Zi [6-93] 123 . the resulting equations will therefore be quite similar.Fig6-39 CE unbypassed emitter-bias configuration Zi: [6-83] [6-84] Zo [6-89] Av And Ai [6-90] [6-91] or Emitter-Follower Configuration (CE) βre = hie and β = hfe .

[6-94] Zo the output network will appear as shown in fig [6-95] Av [6-96] Ai [6-97] or Common-Base Configuration (CB) [6-98 ] Fig6-41 CB configuration Fig6-42 CB hybrid equivalent circuit Zi [6-99] Zo [6-100] 124 .

Av [6-101] Ai [6-102] Example 12: For the network of fig6-43. determine: Fig 6-43 Example 12 Solution. 125 .

Table6-1 Relative Levels for the Important Parameters of the CE. CB. and CC Transistor Amplifier 126 .

the input impedance can be very large. The voltage-divider bias configuration has a higher stability than the fixed-bias configuration. However. Due to the biasing resistors. The output impedance is usually close to Rc and the input impedance relatively close to that obtained with the basic common-emitter configuration. The approximate hybrid equivalent network is very similar in composition to that used with the re model. The CE emitter-bias configuration with an unbypassed emitter resistor has a larger input resistance than the bypassed configuration. One must be aware. 6. but it can have a significant voltage gain. The collector feedback configuration has input impedance that is sensitive to beta and that can be quite low depending on the parameters of the configuration. whereas for the re model they will be in terms of the network parameters and β . For the hybrid model the results will be in terms of the network parameters and the hybrid parameters. and output impedance. In fact. This parameter is normally not provided on a specification sheet. The common-base configuration has very low input impedance. Most specification sheets for BJT include a list of hybrid parameters to establish an ac model for the transistor. although hie of the normally provided hybrid parameters is equal to β re but only under specific operating conditions. 127 . However. The CE fixed-bias configuration can have a significant voltage gain characteristic. The approximate current gain is given by simply beta. Its output impedance is extremely low. 2. and the output impedance is simply Rc 8. the same methods of analysis can be applied to both models.SUMMARY Important Conclusions and Concepts 1. the output impedance is normally assumed to be simply Rc. The current gain is just less than 1. 5. For the unbypassed or by-passed situation. 7. but it has about the same voltage gain. The output impedance is most often simply the collector resistance Rc 9. however. The hybrid model for common-emitter. common-base. making it an excellent signal source for the second stage of a multistage amplifier. its input impedance may be lower than that of the fixed-bias configuration. 3. 10. that they are provided for a particular set of dc operating conditions. and the output impedance is normally assumed to be Rc. current gain. and common-collector configurations is the same. re and ro 11. the voltage gain can be significant and the current gain of some magnitude if the parameters are chosen properly. The collector dc feedback configuration utilizes the dc feedback to increase its stability and the changing state of a capacitor from dc to ac to establish a higher voltage gain than obtained with a straight feedback connection. The re model for a BJT in the ac domain is sensitive to the actual dc operating conditions of the network. The emitter-follower configuration will always have an output voltage slightly less than the input signal. making it very useful for situations where a high-input first stage is needed to "pick up "as much of the applied signal as possible. The only difference will be the magnitude of the parameters of the equivalent network. but it will have a much smaller voltage gain than the bypassed configuration. although its input impedance can be relatively low. 4.

for BJT amplifiers that fail to operate properly. the first step should to be checking the dc level and be sure that they support the dc operation of the design.12. 13. Always keep in mind that capacitors are typically open circuits for the dc analysis and operation and essentially short circuits for the ac response Equations CE fixed bias: CE Voltage-divider bias: CE emitter-bias: Emitter-follower: Common-base: 128 .

Collector feedback: Collector dc feedback: 129 .

Point B in Fig7-4b ID becomes constant. JFETs either n channel or p channel Fig7-1 basic structure of the two types of JFET Fig7-2Water analogy for the JFET control mechanism JFET Symbols Notice that the arrow on the gate points "in" for n-channel and "out" for-p channel. as VGS is set to increasingly more negative values by adjusting VGG. the reversebias voltage in VGD produces a depletion region large enough to offset the increase in VDS. Breakdown result damage to the device. FET is a three-terminal device containing one p-n junction built as either a Junction FET (JFET) or a Metal-Oxide Semiconductor FET (MOS-FET). that is IB controls IC. As VDS increases from point B to point C. this region is called the ohmic region because VDS and ID are related by Ohm's law. so JFETs are always operated below breakdown ( between B & C). The FET is a voltage-controlled device in which the voltage gate VG controls current through the device. Pinch-Off Voltage VP: is the value of VDS at which ID becomes constant and VGS = 0V. ID decreases. is defined by the condition VGS = 0V and VDS > |VP | Breakdown: occurs at point C when ID begins to increase very rapidly with any further increase in VDS . thus keeping ID relatively constant. 130 . Construction and Characteristics of JFETS JFET is a type of FET that operates with a reverse biased junction to control current in the channel. VGS Controls ID: Connect a bias voltage VGG. Fig7-3 JFET symbols (a) n-channel (b) p-channel JFET Characteristics First consider the case where the VGS = 0V fig7-4a as VDD (and thus VDS) is increased from 0V. ID will increase proportionally (Fig7-4b between points A and B). a continued increase in VDS above the VP voltage produces a constant drain current IDSS (Drain to Source current with gate sorted) IDSS: is the maximum drain current and is always specified on JFET data sheets.7-Felid Effect Transistor (FET) BJT is a current-controlled device.

Fig 7-4 the drain characteristic curve of a JFET for VGS = 0 V. (pinch-off) Fig7-5 pinch-off occurs at a lower VDS as VGS is increased to more negative values Cutoff Voltage VGS(off) : the value of VGS that makes ID approximately zero . ID = IDSS (b) cutoff (ID = 0A) VGS less than (more negative) VP (c) ID exists between 0A and IDSS for VGS less than or equal to 0V and greater than the VP Fig7-6 131 .JFET must be operated between VGS = 0V and VGS(off) . VGS(off) & VP are always equal in magnitude but opposite in sign (a) VGS = 0V. for this range of voltage ID will vary from a maximum ( IDSS ) to a minimum .

86V JFET Input Resistance The input resistance at the gate is very high. VDD=VDS+VRD=3. Determine the input resistance Solution: Voltage-Controlled Resistor In ohmic region JFET be employed as a variable resistor whose resistance is controlled by VGS [7-1] ro is the resistance with VGS = 0V. ID=IDSS=6mA VRD= (6mA) (560Ω) =3. Determine the minimum value of VDD required putting the device in the constant-current region of operation Solution: Since VGS(off)=-3. VDS=3.5V. VP=3. and rd the resistance at a particular level of VGS Fig7-7 n-JFET IDSS =8mA & VP=-4V Transistor Characteristic Derivation: For BJT the output current IC and input controlling current IB related to beta. [7-2] 132 .5V & IDSS =6mA.5. which was considered constant for the analysis A liner relationship exist between IC and IB .36V Applying KVL.5V.5V+3.36V=6.The basic operation of a p-channel JFET is the same as for an n-channel device expect that is requires a negative VDD and a positive VGS. JFET data sheets often specify the input resistance by giving a value for the gate reverse current IGSS at a certain VGS Example2: A certain JFET has an IGSS of 1nA for VGS = -20V. Example 1: JFET in fig VGS(off) = -3.

defining an other point on transfer curve. Applying Shockley's Equation: Eq[7-3]Substituting VGS = 0V gives [7-4] [7-5] if we substitute VGS = -1V.This liner relationship dose not exists between the output and input quantities of the JFET. The derivation is quite straightforward and will result in [7-6] Test Eq[7-6]by finding VGS that will result in a drain current of 4. ID = IDSS When VGS = VP = -4V.5mA in fig7-8 133 . the relationship between ID and VGS is defined by Shockley's equation: [7-3] The transfer characteristics defined by Shockley's equation are unaffected by the network in which the device is employed Fig7-8 obtaining transfer char When VGS = 0V. ID=0 mA.

3VP = 0.3(-6V) = -1.8V For p-channel Vp & VGS will be positive and the curve will be the mirror image of the transfer curve obtained with an n-channel and the same limiting values Example4: Sketch the transfer curve for a p-channel device with IDSS = 4mA and VP=3V Solution: At VGS =VP/2 =3V/2=1.5V.Shorthand Method We can have a shorthand method as following: if we specify VGS to be 1/2 VP the resulting level of ID will be the following. if we choose ID = IDSS /2 & substitute into Eq[7-6] [7-7] [7-8] Example 3: Sketch the transfer curve defined by IDSS = 12mA and VP = -6V Solution: At VGS=VP/2 =-6V/2=-3V then IDSS/4 = 12mA/4 = 3mA.9V transfer curve for the p-channel device of Ex 4: 134 . At ID=IDSS/2=12mA/2=6mA the VGS =0.3(3V) =0. as determine by Shockley's equation And ID for VGS =VP/2 = -4V/2 = -2V.3VP = 0. ID=IDSS/4 = 4mA/4 =1mA At ID= IDSS/2=4mA/2=2mA. VGS =0.

Depletion Mode Visualize the gate as one plate of a parallel plate capacitor and the channel as the other plate. the greater the depletion of n-channel electrons. leaving positive ions in their place. at a VGS(off) the channel is totally depleted and ID is zero.Important Relationships Fig7-9 (a) JFET (b) BJT MOSFET (metal-oxide-semiconductor-field-effect transistor) There is no direct electrical connection between the gate terminal and the channel of a MOSFET. With VGS negative voltage. The greater the negative voltage (VGS ). it is the insulating layer of SiO2 in the MOSFET construction that accounts for the very desirable high input impedance of the device. (a)Depletion mode VGS negative < VGS(off) (b) Enhancement: VGS positive Fig7-11n-channel DMOSFET 135 . Depletion MOSFET (D-MOSFET) The drain and source are diffused into the substrate material then connected by a narrow channel adjacent to the insulated gate. D-MOSFET operates in the Depletion mode when a VGS is negative. Fig7-10 D-MOSFETs The D-MOSFET called a depletion/enhancement MOSFET. the negative charges on the gate repel conduction electrons from the channel. The SiO2 insulating layer is the dielectric. Enhancement mode when VGS is a positive voltage. In depletion mode current between drain and source will result from a voltage connected across the drain-source. Thus decreasing the channel conductivity.

The D-MOSFET conducts for values of VGS above 0 V. Fig7-12 transfers char for n-channel DMOSFET D-MOSFET Symbols Fig7-13 D-MOSFET schematic symbols P-channel Depletion-Type MOSFET Fig7-14 p-channel DMOSFET with IDSS = 6mA & VP =+6V Example 3: Sketch the transfer characteristics for n-D-MOSFET with IDSS =10mA and VP= -4V Solution: 136 . the n-channel D-MOSFET conducts ID for VGS between VGS(off) and 0V.Like the n-channel JFET.

thus increasing (enhancing) the channel conductivity. there is no channel. Fig7-15E-MOSFET E-MOSFET symbols For n-channel device. Enhancement MOSFET (E-MOSFET) This type operates only in the enhancement mode and has no depletion mode. thus pulling more electrons into the channel. more conduction electrons are attracted into the channel. a positive VGS voltage above VGS(off) (threshold voltage)creating a thin layer of negative charges in the substrate region adjacent to the SiO2 layer. So that choice values to be substituted into Shockley's equation. the conductivity of the channel is enhanced by increasing the VGS voltage. ID = 0mA [7-13] 137 . In this case. we will try +1V as follows: n-DMOSFET IDSS = 6mA & VP = -4V Enhancement Mode With a positive VGS. [7-11] [7-12] For values of VGS less than the threshold level.ID increases very rapidly with increasing positive values of VGS. It has no structural channel. For any VGS voltage below the threshold value.

additional levels of VGS are chosen and the resulting levels of ID obtained. a horizontal line is drawn at ID =0mA from VGS =0V to VGS =4V as in fig 7-18a next.Fig7-16 n-EMOSFET VT=2V&k=0. 4. at VGS =6. as shown on the resulting plot of fig7-18 138 . a level of VGS grater than VT such as 5V is chosen and substituted into Eq. 7. and 8V.278x10-3 A/V2 [7-14] Fig7-17 transfer char. respectively. and 8mA. the level of ID is 2. In particular.for n-EMOSFET from the drain characteristics First.5.[7-13] to determine the resulting level of ID as follows: And a point on the plot is obtained as in fig7-18b. finally.

ID will be 1. 4.14V.the transfer characteristics Solution: For VGS =8.38mA respectively. determine the resulting value of k for MOSFET.5 x 10-3 A/V2 Example 4: VGS(TH)=3V. 12. 3.Fig7-18 Transfer char of n-EMOSFET with VT = 4V & k = 0. 7.5 x 10-3 A/V2 Fig7-19 p-EMOSFET with VT =24V & k = 0.525. 10.94. Solution to Example 4: 139 .

CMOS CMOS is a complementary MOSFET constructed by a p-channel and an n-channel MOSFET on the same substrate. P-channel on the left and the n-channel on the right Fig7-20 CMOS connections One very effective use of the CMOS is as an inverter as shown in Fig7-21 Fig7-21 CMOS inverter SUMMARY TABLE Fig7-22 resistance levels For Vi = 5 V (1-state) 140 .

A junction field-effect transistor (JFET) operates with a reverse-biased gate-to-source pn junction. JFETs have very high input resistance due to the reverse-biased gate-source junction. 14. a current controlled device is one in which a current defines the operating condition of the device. When VGS = VP/2. Metal-oxide semiconductor field-effect transistors (MOSFETs) differ from JFETs in that the gate of a MOSFET is insulated from the channel. 12. 7. The relationship between the drain current and the gate-to-source voltage of a JFET is nonlinear one defined by Shockley's equation. 4. 13. 141 . whereas a voltage-controlled device is one in which a particular voltage defines the operating conditions. The maximum current for any JFET is labeled IDSS and occurs when VGS =0V. As the current level approaches IDSS. drain. 3. 5. 6.SUMMARY 1. and gate. ID = IDSS /4. the sensitivity of ID to changes in VGS increases significantly 11. Transistors are used as either amplifying devices or switching devices. Maximum operating conditions are determined by the product of the drain-to-source voltage and the drain current. The JFET can actually be used as a voltage-controlled resistor because of a unique sensitivity of the drain-to-source impedance to the gate-to-source voltage. 10. The transfer characteristics (ID versus VGS) are characteristics of the device itself and not sensitive to the network in which the JFET is employed. VGS =0. 2. MOSFET is available in one of two types: depletion and enhancement. 8. The two types of JFETs are n-channel and p-channel. A field-effect transistor (FET) has three terminals: source. JFET current between the drain and the source is through a channel whose width is controlled by the amount of reverse bias on the gate-source junction. 9. 15. and at a point where ID = IDSS /2.3 V. The maximum current for a JFET occurs at pinch-off defined by VGS = VP .

A depletion/enhancement MOSFET (D-MOSFET) can operate with a positive. 22. An enhancement-only MOSFET (E-MOSFET) can operate only when the gate-to-source voltage exceeds a threshold value. 20. At this point the characteristics of a depletion-type MOSFET continue to levels above IDSS. 21. fast switching speeds. Or Zero gate-to-source voltage. negative. 19. EQUATIONS:FET MOSFET (enhancement): 142 . The D-MOSFET has a physical channel between the drain and the source. the threshold voltage. The resulting plot of ID versus VGS is one that rises exponentially with increasing values of VGS. all of which make it very useful in logic circuits. The transfer characteristics of an enhancement-type MOSFET are not defined by Shockley's equation but rather by a nonlinear equation controlled by the gate-to-source voltage. and a constant k defined by the device employed.16. 18. whereas those of a p-channel device will always point out of the center of the symbol. A CMOS (complementary MOSFET) device is one that employs a unique combination of a p-channel and an n-channel MOSFET with a single set of external leads. The depletion-type MOSFET has the same transfer characteristics as a JFET for drain current up to the IDSS level. The arrow in the symbol of n-channel JFET or MOSFET will always point in to the center of the symbol. and low operating power levels. It has the advantages of very high input impedance. The E-MOSFET has no physical channel. 23. whereas those of the JFET will end 17.