This action might not be possible to undo. Are you sure you want to continue?
Introduction to Altium Designer 6
The aim of this lab is to introduce the student to the Altium Designer 6 software. An overview and step-by-step instructions will be given to guide the student through creating an FPGA design. The lab outlines how to create a schematic and then compile, synthesize, build and download to program the Xilinx Spartan IIE chip on the daughterboard of the Altium NanoBoard. An AND gate implementation using schematic then VHDL will be used as an example. Intended Learning Outcomes By the end of this lab session students should be able to: • • • • Create an FPGA project using Altium Designer 6 Create a schematic source document and place and connect parts on it Add a VHDL file to an FPGA project Configure the FPGA on the NanoBoard
1. The Altium Designer Environment Altium Designer provides a unified electronic product development environment, catering for all aspects of the electronic development process, including: • System Design and Capture • Physical PCB Design • FPGA Hardware Design • Embedded Software Development • Mixed-Signal Circuit Simulation • Signal Integrity Analysis • PCB Manufacturing • FPGA system implementation and debugging (when working with a suitable FPGA development board, such as an Altium NanoBoard). All of these design areas are intrinsic parts of a single, cohesive system, built on Altium Designer's Design Explorer (DXP) integration platform. Underlying Altium Designer is the DXP integration platform which brings together Altium Designer's various editors and software engines, and provides a consistent user-interface across all the tools and editors.
FB/GP Version 1.0
Page 1 of 11
An Overview of the Design process Altium Designer’s integrated design environment allows you to design. a process that transforms it from the capture form into a low-level gate form.The Altium Designer environment is fully customizable. Once the hardware design is complete it is synthesized. embedded software and PCB design  FB/GP Version 1. Altium Designer  2. implement and debug a microprocessor-based digital design in an FPGA. Figure 1. ready for compilation and download onto the processor in your design. Design flow: hardware design.0 Page 2 of 11 . or using a mixture of schematic and HDL (VHDL or Verilog). More details about these elements can be found in . Figure 2. A consistent selection and editing paradigm across different editors allows you to easily and smoothly switch between various design tasks within the Altium Designer environment. The design is captured as a schematic. The embedded software is written in a coding-aware editor. Figure 1 summarizes some of the key elements of the Altium Designer environment. allowing you to set up the workspace to suit the way you work.
as well as an array of general purpose peripheral components. and the integrated debugger for the embedded software. Since debugging is performed live from within the same environment as the design is captured in. The software communicates directly with the NanoBoard via a port on the PC.After design synthesis. design iterations can be carried out quickly and software/hardware solutions rapidly explored. an implementation platform that includes an FPGA. Once the design has been implemented on the NanoBoard it can be debugged. To test and debug the design the system includes a NanoBoard. which automatically manages all project and file handling aspects required to generate an FPGA program file. a place and route is performed. using virtual instruments and boundary scan pin status technology to debug the hardware. This is a process where device-aware software implements the design in the target FPGA. Flow diagram of the design process  FB/GP Version 1. Figure 3. programming the FPGA and implementing your design. The Vendor-specific place and route software required to synthesize for the target architecture is operated by the Altium Designer environment.0 Page 3 of 11 .
Now. Generic FPGA library components can be used in any of the target FPGA devices that this system supports. This library is installed and available from the Libraries panel by default. 1. Place the component by clicking on the appropriate position on the schematic. for FPGA projects.IntLib). Select File » New » Schematic.2 Placing parts on the schematic The components we will need for this schematic can be found in a generic integrated library (FPGA Generic. Move the cursor into the schematic workspace if you don’t see it. 3. To create a single schematic document for the AND gate: 1.SchDoc extension) by selecting File » Save As. 2. You can mix both types of documents in a project with the use of sheet symbols. let’s start designing the schematic for our AND Gate. 4. Type the name And_Gate in the file name field and click on Save. Repeat the above steps to place these components as shown in Figure 4.PrjFPG extension) by selecting File » Save Project As.IntLib from the drop-down list in the Libraries panel. a schematic must be used for the top level document of your project. Select FPGA Generic.SchDoc in the File Name field and click on Save. Find the component AND2 in the Libraries panel. J8S_8B).1 Creating a Schematic source document An FPGA project supports two types of source documents – schematic and HDL.IntLib. However. You should notice that your cursor now has the component attached to it. We also need to use an 8-Bit input and output busses (J8B_8S. 3. We also require some ports that interface with the plug-ins on the NanoBoard. You can browse the Libraries panel by either navigating through the list or typing the name AND2 (or part of the name) in the Masks edit box below the library name. 3.3. Select File » New » Project » FPGA Project from the menu 2.0 Page 4 of 11 . Place FB/GP Version 1. A blank schematic sheet named Sheet1. These are located in the FPGA NanoBoard PortPlugin. Rename the new schematic file (with a . Select the component in the list and click the Place AND2 button or simply drag the selected Component Name onto the schematic sheet. 2. Creating an FPGA Project  To create a new project: 1.SchDoc displays in the design window. also a default library available from the Libraries panel. Type the name And_Gate. Rename the new project file (with a . 5.
or press ESC. Let’s place the wires first. 1.DIPSWITCH and LED from this library as shown in Figure 4 below. AND gate schematic with parts placed 6. To place a wire. 2. in the Wiring toolbar. Designators will be automatically added to all the components in this schematic. these parameters will be updated to display the pin numbers that these nets connect to on the target FPGA. select Place » Wire [shortcut P. to exit placement mode. Select Place » Power Port or click on the GND icon 2. Move the cursor to the next point you want your wire segment to connect to and click again. 3. FB/GP Version 1. 3. Our design will need both wires and buses. Wire up the schematic as shown in Figure 5.4 Creating connections We have placed all the components and ports. W] and click on the point on the schematic where you want to start placing (usually at a port or a component pin). Right-click. Note that these components have a visible parameter named ‘PinNumberDisplay’ that initially reads as ‘PXX’ for each pin. or press ESC. to exit wire placement mode. Finally. add designators to the design using Tools » Annotate Schematics Quietly or Tools » Force Annotate All Schematics. When the design is synthesised later.0 Page 5 of 11 .3 Adding Power Ports Place one GND power ports for ground. Figure 4. so now it is time to wire them all together. Continue wiring and right-click. 1. Continue until you have made a connection to another port or component pin.
Figure 5. Place the net label so that the bottom left of the net label (its ‘hotspot’) touches the wire you want to label.5 Naming the connections It is always a good idea to net label all your connections as it will make your design easier to understand and makes tracking down problems and referencing easier. Right-click or press ESC to exit net label placement mode.g. Type the net name in the Net field. The cursor will change to a red cross when the net label touches the wire. Figure 6. e. The AND gate schematic wired up 3. The diagram below gives an indication where the net labels should be placed. To net label your connections: 1. The AND gate schematic with net labels added FB/GP Version 1. Select Place » Net Label [shortcut P. LEFT. Label the other nets.0 Page 6 of 11 . To edit the net label before it is placed. 3. N]. A dotted box will appear floating on the cursor. press the TAB key to display the Net Label dialog. 4. They need not be named exactly as shown in Figure 6. 2. as long as they are unique. Click OK.
0 Page 7 of 11 . To connect the LED port to J8S_8B and the DIPSWITCH to J8B_8S: 1. Any Error or Fatal Error messages will automatically appear in the Messages panel. Warnings will also be listed in the Messages panel but you must manually display the panel by clicking on the System tab at the bottom of the design window and selecting Messages (or select View » Workspace Panels » System » Messages from the menus). Select Project » Compile FPGA Project [project_name]. Resolve any errors and re-compile the project to check. it is important to remember that you always need to net label any disjointed bus segment. FB/GP Version 1. using the same placement technique used when placing a wire. It is also useful to note that a connection from a bus to another object is always resolved from left to right and the bus size of both objects in a connection must be the same. 3. When using buses. Buses can be used to specify not just a group of signals but how each signal in the bus is mapped to its endpoints. Save the schematic and project file. 2.6 Using Buses Altium Designer supports the complex use of buses for FPGA designs.7 Checking the design Before we proceed. Figure 7.3. 4. 3. let’s check that the schematic is going to plan by compiling the project and running the electrical and graphical checks set in the Error Checking tab of the Options for FPGA Project dialog (Project » Project Options). Double-click on any error message in the Messages panel to display more information about the error in the Compile Errors dialog. The offending entity will be zoomed into and highlighted in the schematic. 1. Place a bus by selecting Place » Bus [shortcut P. Save the schematic and save the project. 2. Connecting the DIP switch port to J8B_8S using a bus. B] and place the bus.
the Xilinx Spartan IIE).Constraint in the Choose Constraint files to add to Project dialog. translate the EDIF files. and click OK. 3. The Constraint file will determine the pin numbering and the device name to be used by the FPGA chip on the NanoBoard. e. Select the configuration checkbox back in the Configuration Manager dialog and click OK. Select Project » Configuration Manager.8 Configuring your design Now we need to specify which FPGA chip we want to use in our design. run a Timing Analysis and then Make the Bit File that can then be used to program the FPGA) • Program FPGA (download the bit file to the daughter board’s FPGA chip. you can: • Compile the project (and check for errors) • Synthesize (create an EDIF netlist) • Build (e.g. e. e. 2. 3.3. Click on the Add button in the Configurations section of the dialog and type a configuration name in the New Configuration Name dialog. The Configuration Manager for project dialog appears. Configuration manager 4. NB_SpartanIIE.g. In this view. FB/GP Version 1. Configuration names should relate to the target implementation for easy identification. Place and Route the FPGA.0 Page 8 of 11 .9 Using the Devices view to program the FPGA The Devices view (View » Devices View) allows you to follow through the workflow (from left to right) required to send your program to the FPGA. 5. Figure 8. A folder named Settings is added to the project and shows the constraint file used in the Constraints Files folder. Save the project file. Click Open. 1.g. We will add a configuration and constraint files to do this.g. Add a Constraints file to your configuration by clicking on the Add button in the Constraints section and select NB1_6_XC2S300E-6PQ208. the Xilinx Spartan IIE XC2S300E-6PQ208C chip on the NanoBoard daughterboard. map the design to the FPGA. Constraint files are found in the Altium Designer 6\Library\FPGA\ NB1 Constraint Files\ Xilinx FPGA folder.
you will be able to run the program by flicking on and off the DIP switches SW1 and SW2 on the NanoBoard.0 Page 9 of 11 . click on the Live button and check that the Connected indicator is green. Double-click on an error in the Messages panel to see the fault in the source documents and intermediary VHDL. 6. Make sure your NanoBoard is properly connected and switched on. save the files and recompile. In the Devices view. you will be able to run the program by flicking on and off the DIP switches (SW1 and SW2) on the NanoBoard. suitable for vendor Place & Route tools. so go back to the source files to fix any problems. Click on Build. When the Program FPGA process is completed.Figure 9. The DIP switch is wired as an active low device. In the Devices view. You will see the buttons next to the various processes turn green as they are successfully completed. If the synthesis is completed successfully. This will step through several processes to ultimately make the Bit file that can be downloaded to the FPGA. 4. 2. correct any errors. During synthesis. The Build button will turn green when all necessary processes are completed and the Results Summary dialog appears. The red indicator will turn green when a successful compilation takes place. Programming the FPGA When this workflow is completed. Click on Program FPGA to download the bit file to the daughterboard’s Spartan chip.e. i. 3. To download your AND gate design to the FPGA: 1. VHDL and synthesis log file. If any error messages display in the Messages panel. go back to your schematics. the source documents are translated into intermediate VHDL files which are then synthesised into EDIF. 5. Click on Synthesize. click on Compile. when a switch is ON the signal produced is low: FB/GP Version 1. Errors detected during synthesis are based on errors in the intermediate files. a folder called Generated [config_name] is created which holds the generated EDIF.
Press TAB to display its Sheet Symbol properties dialog. 1. just underneath the AND gate.10 Adding a VHDL file to the project SW2 0 1 0 1 LED0 1 0 0 0 Now we will write a VHDL code to replace the AND gate in the schematic. FB/GP Version 1.0 Page 10 of 11 . Right-click on the FPGA project name and select Add New to Project » VHDL Document. Select and_gate.SchDoc schematic open. Check the syntax of the VHDL code by Selecting Project » Compile Document [VHDL_file_name]. Next we will create a sheet symbol from the new VHDL file to replace the And gate.VHD. The sheet symbol appears floating on the cursor. Any syntax error messages will automatically appear in the Messages panel.VHD. create a new sheet symbol by selecting Design » Create Sheet Symbol from Sheet or HDL.VHD from the Choose Document to Place dialog and click OK. Resolve any errors and re-compile the file to check. 2. Make sure the Visible option is selected and click OK.SW1 0 0 1 1 3. With the And_Gate. 4. and_gate. Click on the Parameters tab to check that the VHDLEntity parameter has been added. Figure 10. Save the VHDL file and project file. 3. type in the following code and save the document under the name and_gate. Click to place the sheet symbol on the And_Gate schematic.
“FPGA Designers Quickstart Guide”. Sheet symbol for the VHDL file If the VHDL file contains multiple entities.altium.0). June 19.com FB/GP Version 1. building and programming the FPGA chip.  Guide. www. GU0112 (v2. “Welcome to the Altium Designer Environment”. 7. November 2005. the VHDLENTITY parameter specifies which entity you want to instantiate. Save the schematic document. Altium Ltd.Figure 11. Make sure the wires connect properly. Finally. 5.0 Page 11 of 11 . 2006.VHD into its place on the schematic. synthesis.  Altium Designer Documentation Library. GU0101 (v1. Delete the AND gate and move the new sheet symbol for and_gate. you should be able to run the design using the switches as before. and_gate. References  Guide. If the FPGA is successfully programmed. to check that the design is working. go to the Devices view (View » Devices) and click on Program FPGA to run all the stages of compilation. Figure 4.VHD sheet symbol placed 6.2). “Altium Designer 6-An Introduction”.