You are on page 1of 5

SHORT PAPER International Journal of Recent Trends in Engineering ,Vol 1, No.

3, May 2009

VLSI Implementation of the Fourphase Pulse Compression Sequences
N. Balaji1 K. Subba Rao2 and M. Srinivasa Rao3
1V.N.R. V.J.I.E.T /ECE Department, Hyderabad, India Email: balajin@vnrvjiet.ac.in 2 O.U. College of Engineering/ ECE Department, Hyderabad, India 3 DRKCET/ ECE Department, Hyderabad, India Email: {kakarlasubbarao, srmudunuru}@yahoo.com

Abstract— Fourphase codes have been widely used in radar and communication areas, but the synthesis of Fourphase codes with good merit factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. However, there is no guarantee to get global optimum point. In this paper, a novel and efficient VLSI architecture is proposed to design Fourphase Pulse compression sequences with good Merit factor. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability. The implemented architecture overcomes the drawbacks of non guaranteed convergence of the earlier optimization algorithms.

⎧N - k -1 ∗ ⎪ ∑ s n s n+k ; 0 ≤ k ≤ N -1 ⎪ n =0 A( k) = ⎨N+ k -1 ⎪ s s∗ ; - N + 1 ≤ k ≤ 0 ⎪ n∑0 n n -k ⎩ =

(2)

II. MERIT FACTOR Golay [2] defined the merit factor (MF) as the ratio of mainlobe energy to sidelobes energy of Autocorrelation (AC) function of sequence S. The MF mathematically is defined as:

MF = 2

A(0) 2

Index Terms— Pulse compression, Binary sequence, VLSI architecture, Merit Factor, Sidelobe energy, FPGA

∑| A(k) |
k ≠0

N -1

(3)
2

I. INTRODUCTION Pulse compression codes with low autocorrelation sidelobe levels and high merit factor are useful for radar [1], channel estimation, and spread spectrum communication applications. Pulse compression can be defined as a technique that allows the radar to utilize a long pulse to achieve large radiated energy but simultaneously obtaining the rangeresolution of a short pulse. Theoretically, in pulse compression, the code is modulated onto the pulsed waveform during transmission. At the receiver, the code is used to combine the signal to achieve a high range resolution. Range-resolution is the ability of the radar receiver to identify near by targets. The main criterion of good pulse compression is the Merit factor and discrimination. Merit factor is used to measure whether coded signal is a good or poor. This means that a code with high Merit factor is a good code while a code with low Merit factor is a poor code. Let S = [x0 ,x1, x2, x3 …..xN-1 ] (1)

The denominator term represents the energy in the sidelobes. The merit factor MF must be as large as possible for good sequence.

III. NON BINARY PULSE COMPRESSION CODES A. Polyphase Code Waveforms consisting more than two phases are called polyphase codes. The phase of sub pulse alternate among multiple values rather than 00 and 180 0. The sequence can be written as

φn =

2πi (n − 1) p2

(4)

Where p is the number of phases, n= 0, 1, 2 …...p2-1 and i= n modulo p. B. Fourphase Code Fourphase Code is the code that can be used to represent information and data. However Fourphase code uses 4 digits for representation of data. Therefore Fourphase code may also be called as 4-alphabet code. This code consists of +1,-1, j and -j. 311

be a real sequence of length N. The aperiodic autocorrelation function (ACF) of sequence S of length N is given as,

© 2009 ACADEMY PUBLISHER

VI. No. placing and routing. +j and -j we need to interface a little additional hardware to FPGA.” for the merit factor calculation of a Fourphase sequence. Since Merit factor is the main criterion for good pulse compression sequences. PROPOSED ARCHITECTURE As the main lobe energy A (0) of a given Fourphase sequence of length N is N2 from “(3).1. The Hardware Implementation architectures for Pulse compression signal processing systems available in the literature have the capability of only the generation of pulse compression sequences [6-7]. This sequence is represented by +1. the sequence generator of Fig.1i has been used for performing mapping. The sequence generator is a synchronous counter of length N which generates 4N sequences with j’s and 1’s. Fourphase sequences of length N. Fourphase and Quinquenary sequences. 5 it is seen that Fourphase sequence based on the lowest sidelobe energy is 0011110110111011111010011011011010110011010111 11(+1-j-1-1+j-j+j+1+j+j+j-1+1+j-1-j). 4. identifies and holds the sequence with minimum sidelobe energy. we need to calculate the side lobe energy of a Fourphase sequence. There has been little work on Fourphase sequences for obtaining good Merit factor values. In order to reduce the computing time and complexity for larger sequences of length N. +j and -j. This architecture generates 4 N N 2 energy value of a Fourphase pulse compression sequence. The behavioral simulation waveforms for the good 13-bit Fourphase Pulse compression sequence are shown in Fig. Xilinx ISE Foundation 9. Combining these generation architectures [8-10] with the currently proposing identification architecture gives an efficient real time Hardware solution for the Fourphase Pulse compression sequences. The proposed VLSI architecture for identification of the good Fourphase pulse compression is shown in the Fig . The targeted device was Spartan-3 xa3s1500fgg676-4 with detailed specifications at [11].-1. Therefore merit factor of this sequence is 6.5. The remaining hardware blocks are useful for computing. Hence earlier the authors proposed an efficient VLSI architecture for the generation of the Pulse Compression sequences with FPGA clock rate [8-10]. NEED FOR THE PROPOSED ARCHITECTURE The problem of obtaining long sequences with peaky autocorrelation [3] has long been an important problem in the field of radar. VII.Vol 1. 1 has been authored in VHDL for 13-bit and 16-bit Fourphase Pulse compression sequences and its synthesis was done with Xilinx XST. 1 holds the good Fourphase pulse compression sequence. This work was based on global optimization techniques such as genetic algorithm. ‘+j’ to 101 and ‘-j’ to 111. The output register2 of Fig. To convert this representation of the sequence to pure Fourphase sequences of 1. the sign conversion unit converts the bit ‘+1’ to 001. As the Fourphase sequence consists of +1. The Synthesis tool was configured to optimize for area and high effort considerations. It is viewed as the problem of optimization [4-5]. identifying and holding the lowest side lobe 312 © 2009 ACADEMY PUBLISHER . ‘-1’ to 011. 3 respectively.SHORT PAPER International Journal of Recent Trends in Engineering . V.-1. May 2009 IV.0 has been used. Therefore merit factor of this sequence is 14. TECHNOLOGY AND TOOLS The architecture shown in Fig. For lower sequence length the proposed architecture generates all the 4N sequences. The good 13-bit and 16-bit Fourphase Pulse compression sequences implementation reports presented in Fig. From the device utilization Summary the same Spartan-3 FPGA is useful for the implementation of higher lengths of the Fourphase Pulse Compression Sequence. For all these 4 sequences it calculates the sidelobe energy values. The signal design problem for radar application is suggested by sequences like binary. therefore the Fourphase sequence having minimum sidelobe energy can be considered as the best Fourphase Pulse compression sequence. slow convergence rate and require large number of evaluations of the objective function. sonar and system identification. These generated sequences are modified with the help of the sign conversion unit to get the Fourphase Pulse Compression sequence elements. For Behavioral simulation and Place and route simulation Modelsim6.-1. 3. But all these optimization algorithms have serious drawbacks of non guaranteed convergence. 2 and Fig. In this paper all the synthesized results are single realizations obtained using Spartan-3 FPGA. The behavioral simulation waveforms for the good 16-bit Fourphase Pulse compression sequence are shown in Fig. 1 can be modified to generate k bits dynamically and remaining (N-k) bits will be the fixed bits which can be taken from an already identified best sequence of length (N-k). From Fig. 4 it can be seen that Fourphase sequence based on the lowest sidelobe energy is 001111011101 001101001101001101011111001(+1-j-1+j+1+j+1+j+1+j1-j+1). eugenic algorithm and SKH (Simon-Kronecker-Hamming) algorithm. +j and -j. From Fig. DESIGN RESULTS Fourphase sequences are designed using the proposed novel and efficient VLSI architecture. identifies and holds the best Fourphase sequence among the 4N sequences.

313 © 2009 ACADEMY PUBLISHER . 3. VLSI architecture for the identification of good Fourphase pulse compression sequence.SHORT PAPER International Journal of Recent Trends in Engineering . May 2009 Fourphase sequence generator for N bits Sign conversion unit (0 to N-1) stages S E Q U E N C E Multiplexer unit (0 to N-1) stages of N:1 Multiplier and adder unit (0 to N-1) stages Squaring unit (0 to N-1) stages Adder unit (0 to N-1) stages Temp register Comparator Temp register Output register Output register Min energy Load signal Best sequence Figure 1.Vol 1. Design Implementation summary of the good 13-bit length Fourphase Pulse Compression sequence. Figure 2. No.

SHORT PAPER International Journal of Recent Trends in Engineering . Behavioral simulation result of a good 13-bit Fourphase Pulse compression sequence. Behavioral simulation result of a good 16-bit Fourphase Pulse compression sequence. 3. Figure 4. Figure 5. Design Implementation summary of the good 16-bit length Fourphase Pulse Compression sequence. May 2009 Figure 3.Vol 1. 314 © 2009 ACADEMY PUBLISHER . No.

“A Pulse compression Radar Signal Processor”.33 5. “Generation of Quinquenary Pulse Compression Sequences using FPGA” in Proc. It was also observed that the proposed 315 © 2009 ACADEMY PUBLISHER .. Phys. This shows the superiority of the architecture.N. 5.957 6. J. The architecture implemented overcomes the drawbacks of non guaranteed convergence and slow convergence rate of the earlier optimization algorithmic based approaches for identifying the good Fourphase pulse compression sequences. Subba Rao. CONCLUSION In this paper we have proposed and implemented an efficient VLSI architecture for the identification of the good Fourphase Pulse Compression sequences based on Merit factor. “A real time digital signal processing solution for radar pulse compression”.062 5. Table I shows the Merit factors of synthesized sequences. The synthesized sequences have Merit factor better than the binary sequences reported in the literature [1].com/spartan3). 1953.00 9. In Communication theory (ed.M. Wurtz D. with good Merit Factors are presented. REFERENCES [1] Golay M J E. of the 8th WSEAS International conference on Multimedia Systems and Signal Processing (MUSP '08).E..N. MERIT FACTOR OF SYNTHESIZED FOURPHASE SEQUENCES Sequence Length 8 9 10 14 16 17 22 23 26 29 31 Merit Factor architecture is giving good merit factor values for higher lengths. 2008. O'Neill.H. Germon. “Generation of Non-binary pulse compression sequences using FPGA”. Comparison of Merit Factors of Synthesized and literature sequences.Vol 1. 1977 IT-23: 43-51.221 7.K and Srinivasa Rao . IT-28.557 6.279-285. R. [8] Balaji .M “Generation of Pulse compression sequences using FPGA”. Germon R.55 7. K and Srinivasa Rao. shows sequence length. 2008.N. R.. Hoffman K H. shows Merit Factor (MF). Proceedings of International conference on VLSI design and Embedded Systems (ICVLSI’08). No. [10] Balaji . pp 543-549.221-225. TABLE I.SHORT PAPER International Journal of Recent Trends in Engineering . Subba Rao . IEEE Trans. IEEE Trans. Theory. 1982. [4] Bernasconi J “Low autocorrelation binary sequences: statistical mechanics and configuration space analysis”.280-286. [3] Barker R H “Group synchronization of binary digital systems”.59 COMPARISON OF MF 18 16 14 MERIT FACTOR 12 10 8 6 4 2 0 8 9 10 14 16 17 22 23 26 29 31 SEQUENCE LENGTH four binary Figure 6. From the above results it is clear that this architecture is giving better merit factor values than the binary sequences. Fig. Inf. 2008. 1992. 3. [2] Golay. column 1. 48: 559-567.25 8.142 5. [11] Xilinx. 1998 6/1-6/5.K and Srinivasa Rao. 1997 4/1-4/5 [7] Day.. N and column 2. “Sieves for low autocorrelation binary sequences”. “Low Autocorrelation binary sequences: exact enumeration and optimization by evolutionary strategies” Optimization 23: 369-384.M . IEE Colloquim on DSP Chip's in Real Time Instrumentation and Display Systems. Spartan-3 Field Programmable Gate array data sheets (http://www. [5] De Groot C. May 2009 Some of the synthesized Fourphase sequences.) W Jackson (London: Butterworths). Proceedings of International conference on RF and Signal Processing Systems (RSPS-2008).J. on Inform. “The merit factor of long low autocorrelation binary sequences”. O'Neill B. B. IEE Colloquium on Digital Filters: An Enabling Technology. Theory.xilinx. [9] Balaji . pp.1512 8. 6 shows comparison of merit factors of synthesized Fourphase sequences and binary sequences reported in the literature [1]. [6] Day R. 1987. In table I. M. pp. pp. Subba Rao .C.