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International Journal of Advances in Computer Architecture Volume 1, Issue 1, 2011, pp-01-03 Available online at: http://www.bioinfo.in/contents.

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Design and Implementation of VLSI Architecture for Characteristic Identification of Binary Pulse Compression Sequence
M. Srinivasa Rao and N. Madhusudhana Reddy
Professor & HOD, Department of ECE, DRKCET, Hyderabad Department of ECE, VNR VJIET, Hyderabad. e-mail: srmudunuru@yahoo.com, madhu.nandha@gmail.com
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Abstract—This paper describes the VLSI implementation for identification for of characteristic parameter of the given binary pulse compression sequence. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameter of the binary pulse compression sequence. The hardware architecture reported in the literature till now has the capability of identification of only one characteristic parameter of the binary pulse compression sequence. In this paper an effort is made with proposing an efficient VLSI architecture for identification of the characteristic parameters i.e. merit factor and discrimination of the binary pulse compression sequence. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability.

There fore our goal is to minimize the sum of squares of all the autocorrelation coefficients of the sequence in order to maximize the Merit Factor. The Discrimination factor is defined as the ratio of energy in the main peak of the auto correlation to the absolute maximum amplitude in the side lobes.

D=

r ( 0) Max k ≠ 0 | r (k ) |

(2)

II. NEED FOR PROPOSED ARCHITECTURE Since the quality of the binary sequence design for specific applications (Radar, Sonar) is decided by Merit Factor or Discrimination. It was reported in the literature for identification of these factors using VLSI architectures []. But all these reported literature provide identification of either Merit Factor or Discrimination of the given Binary pulse compression Sequence. Since the quality of pulse compression sequence is identified by either Merit Factor or Discrimination. There fore it is appropriate to design an efficient architecture to calculate the both these parameters. In this paper an efficient VLSI architecture is proposed for calculating for both Merit Factor and Discrimination.
Given sequence length N Multiplexer units(0 to N-1) Multiplier units(0 to N-1) Adder accumulator units(0 to N-1) Controller unit
NOVEL ARCHITECTURE FOR

I.

INTRODUCTION

In many application areas such as communications, radar and system identification binary sequences either with having good merit factor or discrimination is required. The merit factor is a natural measure of energy efficiency of an binary sequence used to transmit information by modulating a carrier signal, which is of particular importance in spread spectrum communications. The larger the merit factor of the sequence, the more uniformly the signal energy is distributed over the frequency range. The merit factor is useful sequence design criteria for radar applications in which the target must be distinguished from a large number of comparable sized small objects. A problem of digital sequence design is to determine, those binary sequences whose a periodic autocorrelation are collectively small according some suitable measure. The merit factor is an important such measure. A merit factor which specifies the ratio of energy of autocorrelation function main lobes, to the energy of autocorrelation function side lobes .Mathematically it is defined as
MF = 2 A(0) 2

Square units(0 to N-1) Temp1 Reg Merit factor

comparison units(0 to N-1)

Temp2 Reg Discrimination factor

∑| A(k) |
k ≠0

N -1

(1)
2

Fig. 1: A Novel and Efficient VLSI Architecture for Merit and Discrimination Factors Calculation of Binary Pulse Compression Sequence.

International Journal of Advances in Computer Architecture Volume 1, Issue 1, 2011

1. Inf. TECHNOLOGY. for the Merit Factor calculation of a binary sequence.e represent an enable signal. the calculation of the amplitudes of all side lobes are same for merit and discrimination factor. m represents a total side lobe energy and d represents a maximum side lobe amplitude. 2011 .0 has been used. In emd. By using an controller we can get appropriate signal for calculation either Merit factor or a discrimination factor. The proposed VLSI architecture for identification of the chrematistic parameter of the binary pulse compression is shown in the Fig. The Synthesis tool was configured to optimize for area and high effort considerations. on Inform. “The merit factor of long low autocorrelation binary sequences”. By using the controller we can get merit. Theory IT-23: 43-51.” Radar Handbook. New York: McGraw-Hill. In this paper an efficient VLSI architecture is proposed to calculate the characteristic parameter of the binary pulse compression sequence of energy calculation and maximum sidelobe amplitude of binary Pulse Compression Sequence. For Behavioral simulation and Place and route simulation Modelsim6.International Journal of Advances in Computer Architecture Volume 1. Since Merit Factor is calculated from the given total side lobe energy. Second ed. IT-28. V. IEEE Trans.. for the Discrimination calculation of a binary sequence. [3] [4] International Journal of Advances in Computer Architecture Volume 1. REFERENCES E. throughout this paper -1 of the binary sequence element is represented as 0 and +1 of the binary sequence element is represented as 1. Depending on the controller signal we can capable of either or both terms at a time. Stevens. III.) W Jackson (London: Butterworths). Barker R H 1953 Group synchronization of binary digital systems. 4: Behavioral Simulation Result of Merit or Discrimination of 32-bit Binary Pulse Compression Sequence.E. The targeted device was Spartan-3 [1] [2] Fig. Golay. 3: Behavioral Simulation Result of Merit or Discrimination of 16-bit Binary Pulse Compression Sequence. 2: A Controller Design for Merit and Discrimination Factors Calculation of Binary Pulse Compression Sequence. TOOLS AND RESULTS The architecture shown in figure 1 has been authored in VHDL for 16-bit and 32-bit binary Pulse compression sequences and its synthesis was done with Xilinx XST. Theory. IV. placing and routing. As the main lobe amplitude r(0) of a given binary sequence of length N is N from equation 2. Farnett and G. C. Issue 1. IEEE Trans. From the device utilization summary the same Spartan-3 FPGA is useful for the implementation of higher lengths of the binary Pulse Compression sequences. VI. 2011. Issue 1. “Pulse compression radar. Xilinx ISE Foundation 10. discrimination or both at a time. In Communication theory (ed. None merit and not disc Fig.1i has been used for performing mapping. 1982. PROPOSED ARCHITECTURE As the main lobe energy r 2 (0) of a given binary sequence of length N is N 2 from equation 1. we need to calculate the total side lobe energy of a binary sequence. H.in/contents. With a little additional hardware interfaced to the FPGA it is possible to generating the best binary pulse compression sequences with the desired speed.J.php?id=97 Design and Implementation of VLSI Architecture for Characteristic Identification of Binary Pulse Compression Sequence ♦ CONTROLLER Both merit and disc Not merit and disc xa3s1500fgg1146-4 with detailed specifications at [25]. CONCLUSION In this paper we have proposed and implemented an efficient VLSI architecture for identification of characteristic parameter of the given binary pulse compression sequence. The 16-bit and 25-bit binary Pulse compression sequence total sidelobe enery and maximum sidelobe amplitude implementation reports presented in figure 3 and4 respectively.bioinfo. Since this proposed architecture is targeted to FPGA. 1990. Fig. pp-01-03 Available online at: http://www. we need to calculate the maximum side lobe side lobe of a binary sequence. pp 543-549. By observing equation 1 and equation 2. Golay M J E 1977 Sieves for low autocorrelation binary sequences. M.

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