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- Electronics Ch10
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It is a miniature, low cost electronic circuit consisting of active and passive components that are irreparably joined together on a single crystal chip of silicon. Classification: 1. Based on mode of operation a. Digital ICs b. Linear ICs Digital ICs: Digital ICs are complete functioning logic networks that are equivalents of basic transistor logic circuits. Ex:- gates ,counters, multiplexers, demultiplexers, shift registers. Linear ICs: Linear ICs are equivalents of discrete transistor networks, such as amplifiers, filters, frequency multipliers, and modulators that often require additional external components for satisfactory operation. Note: Of all presently available linear ICs, the majority are operational amplifiers. 2. Based on fabrication a. Monolithic ICs b. Hybrid ICs a. Monolithic ICs : In monolithic ICs all components (active and passive) are formed simultaneously by a diffusion process. Then a metallization process is used in interconnecting these components to form the desired circuit. b. Hybrid ICs: In hybrid ICs, passive components (such as resistors and capacitors) and the interconnections between them are formed on an insulating substrate. The substrate is used as a chassis for the integrated components. Active components such as transistors and diodes as well as monolithic integrated circuits, are then connected to form a complete circuit. 3. Based on number of components integrated on ICs a. SSI <10 components b. MSI <100 components c. LSI >100 components d. VLSI >1000 components Integrated circuit Package types: 1. The flat pack 2. The metal can or transistor pack 3. The dual in line package or DIP

THE OPERATIONAL AMPLIFIER: An operational amplifier is a direct-coupled high-gain amplifier usually consisting of one or more differential amplifiers and usually followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package. The operational amplifier is a versatile device that can be used to amplify dc as well as ac input signals and was originally designed for computing such mathematical functions as addition, subtraction, multiplication, and integration. Thus the name operational amplifier stems from its original use for these mathematical operations and is abbreviated to op-amp. With the addition of suitable external feedback components, the modern day op-amp can be used for a variety of applications, such as ac and dc signal amplification, active filters, oscillators, comparators, regulators, and others.

The basic amplifier used in Op-Amp is a differential amplifier. Characteristics of op-amps: a) High voltage gain,i.e few 100 to few 1000s b) High input impedance, i.e 1 to 2 M c) Small output impedance, app 100 d) Larger bandwidth e) Large CMRR,i.e 70-80db f) f) Large slew rate,i.e 0.5 V/s .

Differential amplifier Let us consider the emitter-biased circuit. Figure 1-1 shows two identical emitter biased circuits in that transistor Q1 has the same characteristics as transistor Q2, RE1= RE2, RC1 =RC2, and the magnitude of +VCC is equal to the magnitude of -VEE. Remember that the supply voltages + +VCC and -VEE are measured with respect to ground. To obtain a single circuit such as the one in Figure 1-2, we should reconnect these two circuits as follows: 1. Reconnect +VCC supply voltages of the two circuits since the voltages are of the same polarity and amplitude. Similarly, reconnect -VEE supply voltages. 2. Reconnect the emitter E1 of transistor Q1 to the emitter E2 of transistor Q2. (This reconnection places RE1 in parallel with RE2) 3. Show the input signal vin1 applied to the base B1 of transistor Q1 and vin2 applied to the base B2 of transistor Q2. 4. Label the voltage between the collectors C1 and C2 as v0. (The v0 is the output voltage.)

DIFFERENTIAL AMPLIFIER CIRCUIT CONFIGURATIONS The four differential amplifier configurations are the following: 1. Dual-input, balanced-output differential amplifier 2. Dual-input, unbalanced-output differential amplifier 3. Single-input, balanced-output differential amplifier. 4. Single-input, unbalanced-output differential amplifier DUAL-INPUT, BA LANCED-OUTPUT DIFFERENTIAL AMPLIFIER 1. DC Analysis

The dc equivalent circuit can be obtained simply by reducing the input signals vin1 and vin2 to zero. To determine the operating point values ICQ and VCEQ,

AC Analysis: To perform ac analysis to derive the expression for the voltage gain Ad and the input resistance Ri of the differential amplifier shown in Figure 1-2: 1. Set the dc voltages + Vcc and -VEE at zero. 2. Substitute the small-signal T-equivalent models for the transistors.

Figure 1-4(a) shows the resulting ac equivalent circuit of the dual-input, balanced- output differential amplifier.

(a) Voltage gain: The following should be noted about the circuit in Figure 1-4(a): 1. IE1 =IE2; therefore, re1 = re2. For this reason, the ac emitter resistance of transistor Q1 and Q2 is simply denoted by re. 2. The voltage across each collector resistor is shown out of phase by 1800 with respect to the input voltages vin1 and vin2. This polarity assignment is in accordance with the common-emitter configuration. 3. Note the assigned polarity of the output voltage v0. This polarity simply indicates that the voltage at collector C2 is assumed to be more positive with respect to that at collector C1, even though both of them are negative with respect to ground.

(b) Differential input resistance. Differential input resistance is defined as the equivalent resistance that would be measured at either input terminal with the other terminal grounded.

(c) Output resistance. Output resistance is defined as the equivalent resistance that would be measured at either output terminal with respect to ground. Therefore, the output resistance R01 measured between collector C1 and ground is equal to that of the collector resistor RC. Similarly, the output resistance R02 measured at collector C2 with respect to ground is equal to that of the collector resistor Rc. Thus R01= R02 = RC FET DIFFERENTIAL AMPLIFIERS In the differential amplifier configurations just discussed we have used BJTs. But if we require very high input resistance, we can use FETs instead. Fortunately, the voltage-gain equations derived for these configurations using BJTs can also be used for configurations using FETs, except for the following replacements:

For instance, the voltage gain of the JFET dual-input, balanced-output differential amplifier obtained from Equation (1-12) is

Inverting & Non inverting Inputs: In differential amplifier the output voltage vO is given by VO = Ad (v1 v2) When v2 = 0, vO = Ad v1 & when v1 = 0, vO = - Ad v2 Therefore the input voltage v1 is called the non inventing input because a positive voltage v1 acting alone produces a positive output voltage vO. Similarly, the positive voltage v2 acting alone produces a negative output voltage hence v2 is called inverting input. Consequently B1 is called noninverting input terminal and B2 is called inverting input terminal. Common mode Gain: A common mode signal is one that drives both inputs of a differential amplifier equally. The common mode signal is interference, static and other kinds of undesirable pickup etc. The connecting wires on the input bases act like small antennas. If a differential amplifier is operating in an environment with lot of electromagnetic interference, each base picks up an unwanted interference voltage. If both the transistors were matched in all respects then the balanced output would be theoretically zero. This is the important characteristic of a differential amplifier. It discriminates against common mode input signals. In other words, it refuses to amplify the common mode signals. The practical effectiveness of rejecting the common signal depends on the degree of matching between the two CE stages forming the differential amplifier. In other words, more closely are the currents in the input transistors, the better is the common mode signal rejection e.g. If v1 and v2 are the two input signals, then the output of a practical op-amp cannot be described by simply v0 = Ad (v1 v2 ) In practical differential amplifier, the output depends not only on difference signal but also upon the common mode signal (average). vd = (v1 vd ) and vC = (v1 + v2 ) The output voltage, therefore can be expressed as vO = A1 v1 + A2 v2 Where A1 & A2 are the voltage amplification from input 1(2) to output under the condition that input 2 (1) is grounded.

The voltage gain for the difference signal is Ad and for the common mode signal is AC. The ability of a differential amplifier to reject a common mode signal is expressed by its common mode rejection ratio (CMRR). It is the ratio of differential gain Ad to the common mode gain AC.

Date sheet always specify CMRR in decibels CMRR = 20 log CMRR. Therefore, the differential amplifier should be designed so that r is large compared with the ratio of the common mode signal to the difference signal. If r = 1000, vC = 1mV, vd = 1 m V, then

It is equal to first term. Hence for an amplifier with r = 1000, a 1m V difference of potential between two inputs gives the same output as 1mV signal applied with the same polarity to both inputs. Biasing of Differential Amplifiers Constant Current Bias: In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon the value of dc. To make operating point stable IE current should be constant irrespective value of dc. For constant IE, RE should be very large. This also increases the value of CMRR but if RE value is increased to very large value, IE (quiescent operating current) decreases. To maintain same value of IE, the emitter supply VEE must be increased. To get very high value of resistance RE and constant IE, current, current bias is used.

Constant Current Bias: In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon the value of dc. To make operating point stable IE current should be constant irrespective value of dc. For constant IE, RE should be very large. This also increases the value of CMRR but if RE value is increased to very large value, IE (quiescent operating current) decreases. To maintain same value of IE, the emitter supply VEE must be increased. To get very high value of resistance RE and constant IE, current, current bias is used.

Figure 5.1 Fig. 1, shows the dual input balanced output differential amplifier using a constant current bias. The resistance RE is replace by constant current transistor Q3. The dc collector current in Q3 is established by R1, R2, & RE. Applying the voltage divider rule, the voltage at the base of Q3 is

Because the two halves of the differential amplifiers are symmetrical, each has half of the current IC3.

The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the emitter or the base of Q3. Besides supplying constant emitter current, the constant current bias also provides a very high source resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all the performance equations obtained for differential amplifier using emitter bias are also valid. As seen in IE expressions, the current depends upon VBE3. If temperature changes, VBE changes and current IE also changes. To improve thermal stability, a diode is placed in series with resistance R1as shown in fig. 2.

Fig. 2 This helps to hold the current IE3 constant even though the temperature changes. Applying KVL to the base circuit of Q3.

Therefore, the current IE3 is constant and independent of temperature because of the added diode D. Without D the current would vary with temperature because VBE3 decreases approximately by 2mV/ C. The diode has same temperature dependence and hence the two variations cancel each other and IE3 does not vary appreciably with temperature. Since the cut in voltage VD of diode approximately the same value as the base to emitter voltage VBE3 of a transistor the above condition cannot be satisfied with one diode. Hence two diodes are used in series for VD. In this case the common mode gain reduces to zero.

Some times zener diode may be used in place of diodes and resistance as shown in fig. 3. Zeners are available over a wide range of voltages and can have matching temperature coefficient The voltage at the base of transistor QB is

Fig. 3 The value of R2 is selected so that I2 1.2 IZ(min) where IZ is the minimum current required to cause the zener diode to conduct in the reverse region, that is to block the rated voltage VZ.

Current Mirror: The circuit in which the output current is forced to equal the input current is said to be a current mirror circuit. Thus in a current mirror circuit, the output current is a mirror image of the input current. The current mirror circuit is shown in fig. 4.

Fig. 4 Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2. The current mirror is a special case of constant current bias and the current mirror bias requires of constant current bias and therefore can be used to set up currents in differential amplifier stages. The current mirror bias requires fewer components than constant current

bias circuits. Since Q3 and Q4 are identical transistors the current and voltage are approximately same

LEVEL TRANSLATOR: From the results of the cascaded differential amplifier, the following observations can be made: 1. Because of the direct coupling, the dc level at the emitters rises from stage to stage. This increase in dc level tends to shift the operating point of the succeeding stages and, therefore, limits the output voltage swing and may even distort the output signal.. Therefore, the final stage should be included to shift the output dc level at the second stagedown to about zero volts to ground. Such a stage is referred to as a level translator or

shifter.

The voltage at the junction will be zero by selecting proper values of R1 and R2. Better results are obtained by using an emitter follower either with a diode constant current bias or a current mirror instead of the voltage divider, as shown in Figure 1-20(b) and (c), respectively. The output stage is generally a push-pull or push-pull complementary-symmetry pair. SCHEMATIC SYMBOL The symbolic diagram of an OPAMP is shown in fig. 1.

THE IDEAL OP-AMP An ideal op-amp would exhibit the following electrical characteristics: 1. Infinite voltage gain A. 2. Infinite input resistance R, so that almost any signal source can drive it and there is no loading of the preceding stage. 3. Zero output resistance R, so that output can drive an infinite number of other devices. 4. Zero output voltage when input voltage is zero. 5. Infinite bandwidth so that any frequency signal from 0 to Hz can be amplified without attenuation. 6. Infinite common-mode rejection ratio so that the output common-mode noise voltage is zero. 7. Infinite slew rate so that output voltage changes occur simultaneously with input voltage changes. EQUIVALENT CIRCUIT OF AN OP-AMP The output voltage is

Where A = large-signal voltage gain vid= difference input voltage v1= voltage at the non-inverting input terminal with respect to ground v2= voltage at the inverting terminal with respect to ground

OPEN-LOOP OP-AMP CONFIGURATIONS 1. Differential amplifier 2. Inverting amplifier 3. Non-inverting amplifier The Differential Amplifier

Example - 1 The following specifications are given for the dual input, balanced-output differential amplifier of fig.1: RC = 2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50 , +VCC = 10V, -VEE = -10 V, dc =100 and VBE = 0.715V. Determine the operating points (ICQ and VCEQ) of the two transistors. Solution: The value of ICQ can be obtained from equation .

The values of ICQ and VCEQ are same for both the transistors. 2.The following specifications are given for the dual input, balanced-output differential amplifier: RC = 2.2 k, RB = 4.7 k, Rin 1 = Rin 2 = 50, +VCC= 10V, -VEE = -10 V, dc =100 and VBE = 0.715V. a. Determine the voltage gain. b. Determine the input resistance c. Determine the output resistance. Solution: (a). The parameters of the amplifiers are same as discussed in example-1 of lecture-1. The operating point of the two transistors obtained in lecture-1 are given below ICQ = 0.988 mA VCEQ=8.54V The ac emitter resistance

Therefore, substituting the known values in voltage gain equation (E-2), we obtain

b). The input resistance seen from each input source is given by (E-3) and (E-4):

(c) The output resistance seen looking back into the circuit from each of the two output terminals is given by (E-5) Ro1 = Ro2 = 2.2 k

Example - 2 For the dual input, balanced output differential amplifier of Example-1: a. Determine the output voltage (vo) if vin 1 = 50mV peak to peak (pp) at 1 kHz and vin 2 = 20 mV pp at 1 kHz. b. What is the maximum peal to peak output voltage without clipping? Solution: (a) In Example-1 we have determined the voltage gain of the dual input, balanced output differential amplifier. Substituting this voltage gain (Ad = 86.96) and given values of input voltages in (E-1), we get

(b) Note that in case of dual input, balanced output difference amplifier, the output voltage vo is measured across the collector. Therefore, to calculate the maximum peak to peak output voltage, we need to determine the voltage drop across each collector resistor:

This means that the maximum change in voltage across each collector resistor is 2.17 (ideally) or 4.34 VPP. In other words, the maximum peak to peak output voltage with out clipping is (2) (4.34) = 8.68 VPP.

Consider example-1 of lecture-2. The specifications are given again for the dual input, unbalanced-output differential amplifier: RC = 2.2 k, RB= 4.7 k, Rin1 = Rin2= 50, +VCC = 10V, -VEE= -10 V, dc =100 and VBE= 0.715V. Determine the voltage gain, input resistance and the output resistance. Solution: Since the component values remain unchanged and the biasing arrangement is same, the ICQ and VCEQ values as well as input and output resistance values for the dual input, unbalanced output configuration must be the same as those for the dual input, balanced output configuration. Thus, ICQ = 0.988 mA VCEQ = 8.54 V

Ri1 = Ri2 = 5.06 k Ro = 2.2 k The voltage gain of the dual input, unbalanced output differential amplifier is given by

Example-2 Repeat Example-1 for single input, balanced output differential amplifier. Solution: Because the same biasing arrangement and same component values are used in both configurations, the results obtained in Example-1 for the dual input, balanced output configuration are also valid for the single input, balanced output configuration. That is, ICQ= 0.988 mA VCEQ = 8.54 V Vd = 86.96 Ri = 5.06 k Ro1 = Ro2 = 2.2 k

1.Design a zener constant current bias circuit as shown in fig. 5 according to the following specifications. (a). Emitter current -IE = 5 mA (b). Zener diode with Vz = 4.7 V and Iz = 53 mA. (c). ac = dc = 100, VBE = 0.715V (d). Supply voltage - VEE = - 9 V. Solution: From fig. 6 using KVL we get

Fig. 5

Fig. 6

Design the dual-input balanced output differential amplifier using the diode constant current bias to meet the following specifications. 1. supply voltage = 12 V. 2. Emitter current IE in each differential amplifier transistor = 1.5 mA. 3. Voltage gain 60. Solution: The voltage at the base of transistor Q3 is

Assuming that the transistor Q3 has the same characteristics as diode D1 and D2 that is VD = VBE3, then

Fig. 7

To obtain the differential gain of 60, the required value of the collector resistor is

The following fig. 7 shows the dual input, balanced output differential amplifier with the designed component values as RC = 1K, RE = 240 , and R2 = 3.6K.

Assuming that the transistor Q3 has the same characteristics as diode D1 and D2 that is VD = VBE3, then

Fig. 7

To obtain the differential gain of 60, the required value of the collector resistor is

The following fig. 7 shows the dual input, balanced output differential amplifier with the designed component values as RC = 1K, RE = 240 , and R2 = 3.6K.

Operational amplifier:

The collector current and collector to emitter voltage for each transistor. The overall voltage gain. The input resistance. The output resistance.

Assume that for the transistors used hFE = 100 and VBE = 0.715V

Fig. 5 Solution: (a). To determine the collector current and collector to emitter voltage of transistors Q1 and Q2, we assume that the inverting and non-inverting inputs are grounded. The collector currents (IC IE) in Q1 and Q2 are obtained as below:

That is, IC1 = IC2 =0.988 mA. Now, we can calculate the voltage between collector and emitter for Q1 and Q2 using the collector current as follows: VC1 = VCC = -RC1 IC1 = 10 (2.2k) (0.988 mA) = 7.83 V = VC2 Since the voltage at the emitter of Q1 and Q2 is -0.715 V, VCE1 = VCE2 = VC1 -VE1 = 7.83 + 0715 = 8.545 V Next, we will determine the collector current in Q3 and Q4 by writing the Kirchhoff's voltage equation for the base emitter loop of the transistor Q3: VCC RC2 IC2 = VBE3 - R'E IC3 - RE2 (2 IE3) + VBE= 0 10 (2.2k) (0.988mA) - 0.715 - (100) (IE3) (30k) IE3 + 10=0 10 - 2.17 - 0.715 + 10 - (30.1k) IE3 = 0

Hence the voltage at the collector of Q3 and Q4 is VC3 = VC4= VCC RC3 IC3 = 10 (1.2k) (0.569 mA) = 9.32 V Therefore, VCE3 = VVCE4 = VC3 VE3 = 9.32 7.12 = 2.2 V Thus, for Q1 and Q2: ICQ = 0.988 mA VCEQ = 8.545 V and for Q3 and Q4: ICQ = 0.569 mA VCEQ = 2.2 V [Note that the output terminal (VC4) is at 9.32 V and not at zero volts.] (b). First, we calculate the ac emitter resistance r'e of each stage and then its voltage gain.

The first stage is a dual input, balanced output differential amplifier, therefore, its voltage gain is

The second stage is dual input, unbalanced output differential amplifier with swamping resistor R'E, the voltage gain of which is

Hence the overall voltage gain is Ad= (Ad1) (Ad2) = (80.78) (4.17) = 336.85

Thus we can obtain a higher voltage gain by cascading differential amplifier stages. (c).The input resistance of the cascaded differential amplifier is the same as the input resistance of the first stage, that is Ri = 2ac(re1) = (200) (25.3) = 5.06 k (d). The output resistance of the cascaded differential amplifier is the same as the output resistance of the last stage. Hence, RO = RC = 1.2 k Example-2: For the circuit show in fig. 6, it is given that =100, VBE =0715V. Determine

The dc conditions for each state The overall voltage gain The maximum peak to peak output voltage swing.

Fig. 6 Solution: (a). The base currents of transistors are neglected and VBE drops of all transistors are assumed same.

and

(c). The maximum peak to peak output votage swing = Vopp = 2 (VC7 - VE7) = 2 x (5.52 - 3.325) = 4.39 V

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