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L10: Major/Minor FSMs, Lab 3, and RAM/ROM Instantiation

Acknowledgements: Rex Min

L10: 6.111 Spring 2004

Introductory Digital Systems Laboratory

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but the next-state transitions are not..Toward FSM Modularity Consider the following abstract FSM: S0 S1 a1 b1 S2 d1 c1 S3 S4 a2 b2 S5 d2 c2 S6 a3 b3 S7 d3 c3 S8 S9 Suppose that each set of states ax.dx is a “sub-FSM” that produces exactly the same outputs.. This situation closely resembles a procedure call or function call in software. Can we simplify the FSM by removing equivalent states? No! The outputs may be the same...how can we apply this concept to FSMs? L10: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2 .

The Major/Minor FSM Abstraction STARTA BUSYA Minor FSM A RESET CLK Major FSM RESET CLK STARTB BUSYB Minor FSM B Subtasks are encapsulated in minor FSMs with common reset and clock Simple communication abstraction: START: tells the minor FSM to begin operation (the call) BUSY: tells the major FSM whether the minor is done (the return) The major/minor abstraction is great for. Modular designs (always a good thing) Tasks that occur often but in different contexts Tasks that require a variable/unknown period of time Event-driven systems L10: 6...111 Spring 2004 Introductory Digital Systems Laboratory 3 .

111 Spring 2004 Introductory Digital Systems Laboratory 4 . S1 1.. Trigger the minor FSM (and make sure it’s started) 3.Inside the Major FSM BUSY BUSY BUSY BUSY BUSY BUSY .. Wait until the minor FSM is ready START S2 S3 S4 2. Wait until the minor FSM is done Major FSM State START BUSY CLK S1 S2 S2 S3 S3 S3 S4 L10: 6.

Do some useful work Major FSM State START BUSY CLK Minor FSM State S1 S2 S2 S3 S3 S3 S4 can we speed this up? T1 T1 T2 T3 T4 T1 T1 L10: 6.Inside the Minor FSM 1.111 Spring 2004 Introductory Digital Systems Laboratory 5 . Wait for a trigger from the major FSM START T1 BUSY START BUSY T2 BUSY T3 BUSY T4 3. Signal to the major FSM that work is done 2.

Optimizing the Minor FSM Good idea: de-assert BUSY one cycle early START T1 BUSY START BUSY T2 BUSY T3 T4 BUSY Bad idea #1: T4 may not immediately return to T1 START Bad idea #2: BUSY never asserts! START T1 BUSY START BUSY T2 BUSY T3 T4 BUSY T1 BUSY START T2 BUSY L10: 6.111 Spring 2004 Introductory Digital Systems Laboratory 6 .

Otherwise. we loop forever! TICK BUSYA+BUSYB BUSYA+BUSYB IDLE STARTA STARTB STAB BUSYABUSYB WTAB BUSYABUSYB BUSYC WTC BUSYC L10: 6.111 Spring 2004 BUSYC STARTC STC BUSYC Introductory Digital Systems Laboratory 7 .A Four-FSM Example TICK STARTA BUSYA STARTB Minor FSM A Minor FSM B Minor FSM C Operating Scenario: Major FSM is triggered by TICK Minors A and B are started simultaneously Minor C is started once both A and B complete TICKs arriving before the completion of C are ignored Major FSM BUSYB STARTC BUSYC TICK Assume that BUSYA and BUSYB both rise before either minor FSM completes.

Four-FSM Sample Waveform TICK STARTA BUSYA Minor FSM A Minor FSM B Minor FSM C Major FSM STARTB BUSYB STARTC BUSYC state tick STARTA BUSYA STARTB BUSYB STARTC BUSYC L10: 6.111 Spring 2004 IDLE IDLE STAB STAB WTAB WTAB WTAB STC STC WTC WTC WTC IDLE IDLE STAB Introductory Digital Systems Laboratory 8 .

. Must choose a shared bus for the A/D and DA A/D output in twos complement and ROM in sign/magnitude Bypass LE_DAC L E_ADC 8 8 Bidirectional I/O 8 D A/D Reg LD Q RAM Control and A ddress ALU CONTROL RO M Control and Address Use on-chip SRAM and ROM Sample rate is fixed at 20kHz Must use a memory based approach to FIR..111 Spring 2004 Introductory Digital Systems Laboratory .e. CS) Q D/A Reg LD D LE_DAC SRAM Impulse Response ROM 8 D/A AD 558 CLK 8 2 Arithmetic Unit (MAC) 8 Switches SW L10: 6. registers) Must use Major/Minor FSM structure 9 8 SW control (CE. CS. not tapped delay line (i. R/W) MINOR FSM 1 MINOR FSM 2 ..Lab3 Block Diagram RESET status Synchronizer CONTROL UNIT MAJOR FSM A/D AD 670 control(CE.

. Do the FIR filter algorithm which is a convolution..111 Spring 2004 Sample Output Computed Sample to DAC Store A/D Sample Initiate A/D Convolve Introductory Digital Systems Laboratory 10 . Start the next A/D conversion. L10: 6. Wait Sample Output what was computed on the last sample. Go back for more.Control Flow for Lab3 Reset Initialize Wait for a fixed time interval. Store the previous A/D sample into memory.

You can choose ROM RAM dp .Dual Ported dq . outputs.Use LPM to Create ROM/RAM Click on File → MegaWizard Plug-In Manager This starts up a series of windows so that you can specify parameters of the LPM module. You can choose registered or unregistered inputs.Separate Inputs and Outputs io . L10: 6. and addresses. You should specify a file to set the values of the ROM.111 Spring 2004 Introductory Digital Systems Laboratory 11 .TriState Inputs and Outputs (like the 6264) You choose the number of address bits and the word size.

The default base is HEX but you can use binary or decimal if you include the following statement (before the numbers).dat file.dat <filename>.111’ type ‘man dat2ntl’ dat2ntl <filename>.111/www/s2004/software.ROM Contents Prepare a .dat file into Intel HEX for details. # SET_ADDRESS = 0. # BASE = BINARY.edu/6. 7 6 5 4 3 2 1 0 L10: 6. (specifies that data should start at address 0) Run dat2ntl on Athena to format your . etc.) This has numbers separated by white space. You can type this in.ntl rom8x8.mit. after ‘setup 6. write a computer program. get it from another application (speech or graphics. Insert.html for .111 Spring 2004 dat2ntl rom8x8.mif format (memory initialization format) Introductory Digital Systems Laboratory 12 .dat: # SET_ADDRESS = 0.ntl: :080000000706050403020100DC :00000001FF tool on athena 3 8 address ROM data See http://web.

lpm_widthad = 3. lpm_rom_component.lpm_address_control = "UNREGISTERED". .111 Spring 2004 Introductory Digital Systems Laboratory 13 .ntl".v // Megafunction Name(s): // lpm_rom //============================================= module rom8x8 ( address. q).lpm_file = “rom8x8. lpm_rom_component.address (address).v (generated automatically) //============================================= // File Name: rom8x8. lpm_rom_component. Example: 8 deep by 8 bits wide 3 8 Path to location of Rom data ROM delay L10: 6.lpm_outdata = "UNREGISTERED". wire [7:0] sub_wire0.q (sub_wire0)).lpm_width = 8. endmodule lpm_rom_component ( . lpm_rom defparam lpm_rom_component. input [2:0] address. lpm_rom_component. output [7:0] q. wire [7:0] q = sub_wire0[7:0].rom8x8.

lpm_width = 2. input input input output [1:0] address. we. .v // megafunction wizard: %LPM_RAM_DQ% module ram4x2 ( address.lpm_address_control = "UNREGISTERED".data (data).lpm_outdata = "UNREGISTERED". we. defparam lpm_ram_dq_component. lpm_ram_dqlpm_ram_dq_component ( . lpm_ram_dq_component.lpm_widthad = 2. lpm_ram_dq_component. wire [1:0] q = sub_wire0[1:0].lpm_indata = "UNREGISTERED". q). . lpm_ram_dq_component. [1:0] data. . address data we 2 2 RAM 2 q wire [1:0] sub_wire0.we (we). lpm_ram_dq_component.ram4x2. lpm_ram_dq_component. [1:0] q. endmodule L10: 6.111 Spring 2004 Introductory Digital Systems Laboratory 14 .q (sub_wire0)).lpm_hint = "USE_EAB=ON".address (address). data.

address data we 2 2 RAM 2 q Latch interface: Data must be setup and held around the falling edge of the clock. [1:0] data.111 Spring 2004 Introductory Digital Systems Laboratory 15 . data. we. Address must be setup before rising edge and held after falling edge L10: 6. we.Asynchronous RAM Simulation module ram4x2 ( address. [1:0] q. input input input output endmodule [1:0] address. q).

a read operation takes place L10: 6. a write operation takes place If we=0 on the rising edge.SRAM with Registered Address and Data (Synchronous) Register interface: Address. data and we should be setup and held on the rising edge of clock If we=1 on the rising edge.111 Spring 2004 Introductory Digital Systems Laboratory 16 .