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SRV COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

B.E. ECE
QUESTION PAPER
Sub.Code Sub.Name Staff Name : EC 1354 : VLSI DESIGN : Mr.A.P.PRABAKARAN M.E; Branch / Year / Sem : ECE / III / VI Batch:2010-2014 Academic Year: 2012-2013(EVEN)

ANNA UNIVERSITY B.E/B.Tech Degree Examination,November/December 2009 Seventh Semester (Common to B.E.(Part-Time) Sixth Semester Regulation 2005)(Regulation 2004)

Part A-(10*2=20 marks) 1.What are the different MOS layers? 2.What are the two types of layout design rules? 3.Define rise time and fall time. 4.What is a pull down device? 5.What are the difference between task and function? 6.What is CBIC ? 7.Draw an assert high switch condition if input = 0 and input =1. 8.What do you mean by DFT? 9.Draw the boundary scan input logic diagram. Part B - (5*16=80 marks) 11.a) Discuss the steps involved in IC fabrication process.(16) (Or) b) Describe n-well process in detail.(16) 12.a)i)Explain the DC characteristics of CMOS inverter with neat sketch.(8) ii)Explain channel length modulation and body effect.(8) (Or) b)i)Explain the different regions of operation in a MOS transistor.(10) ii)Write a note on MOS models.(6)

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SRV COLLEGE 13.a)Explain in detail any five operators used in HDL .(16) (Or) b)i)Write the verilog code for 4 bit ripple carry full adder.(10) ii)Give the structural description for priority encoder using verilog.(6) 14.a)Explain in detail the sequence of steps to design an ASIC.(16) (Or) b)Describe in detail the chip with programmable logic structures.(16) 15.a)Explain in detail Scan Based Test Techniques.(16) (Or) b)Discuss the three main design strategies for testability.(16)

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SRV COLLEGE

EC 1354 VLSI Design (As per Trichy Anna University syllabus) Part-A:

1. Design a NOR gate using basic CMOS technology. 2. Write a note on channel-length modulation. 3. How do the problem of latch up prevented? 4. Write a brief note on transmission gates. 5. What is the link between the shapes and resistance? 6. When the MOS characteristics is in the stage of accumulation, depletion and inversion,draw the capacitance effect? 7. Write a brief note on two phase clocking. 8. Design a simple half adder circuit. 9. What is the function of assert statement? 10. What is meant by overloading?

Part-B:

11. a) (i) Discuss in detail the behavior of NMOS devices under the influence of different terminal voltages? (8) (ii) Derive an expression for Threshold voltage. (8)

(Or)

b) (i) Give a brief note on 1. Body effect 2. Mobility variation 3. Fowler Nordhum Tunneling 4. Impact Ionization (ii) Derive and draw the necessary equations for a small signal model of an MOS transistor. (6)

12. a) Discuss in detail the characteristics of CMOS INVERTER circuit. Also draw the layout diagram and stick diagram for an inverter. (16)

(Or)

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SRV COLLEGE b) Write a detailed note on the following (i) Pseudo NMOS Inverter (ii) Saturated load Inverter (iii) Cascade inverter (iv) TTL interface inverter (5 + 5 + 3 + 3 ) 13. a) With equation and necessary diagram explain in detail the capacitance estimation of MOS Device. (16)

(Or)

b) For a CMOS inverter, draw the equivalent circuit and obtain. (16) (i) Fall delay (ii) Rise delay (iii) Delay delay (iv) Gate delay (v) Switch level RC model. 14. a) Design the following circuits using VLSI design. (i)Multiplexers (ii) Multiplier (iii) Full adder.

(Or)

b) Draw a neat layout, circuit diagram and explain with necessary equations for the following circuit. (i) Bit serial adder (ii) Carry save adder (iii) Transmission gate adder (iv) Carry look ahead adder. 15. a) Discuss elaborately the various data types with examples. (8)

(Or)

b) Explain in detail the various levels of modeling with suitable example. (8)

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SRV COLLEGE B.E Electronics and Communication EC1401-VLSI DESIGN Question paper 2008 Anna University PART A-(10*2=20 marks)

1. How do you prevent latch up problem? 2. List any two types of layout design rules. 3. Define rise time and fall time. 4. Write an expression for power dissipation in CMOS inverter. 5. Differentiate between conditional and procedural assignment. 6. Why do you require sensitivity list? 7. Draw 2:1 Mux using Transmission gate. 8. What are the different types of programming structure available in PAL? 9. What are the different types of CMOS testing? 10. List any two faults that occur during manufacturing.

PART B-(5*16=80 marks)

11. (a) Explain with neat diagram the SOI process and mention its advantages.

(OR) (b) (i) How are the circuit elements implemented in ICs? (ii) Explain about CMOS interconnects with diagram.

12. (a)(i) Derive the expression for DC characteristics of CMOS inverter. (ii) Explain the small signal AC characteristics of MOS transistor.

(OR)

(b) (i) Derive the equation for threshold voltage of a MOS transistor and threshold voltage in terms of flat band voltage. (10) (ii) Calculate the threshold voltage for a transistor at 300K for a process with a SiO2 gate oxide with thickness 200A.Assume ?ms =-0.9V;Qfc=0. (6)

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SRV COLLEGE 13. (a) (i) write a Verilog program for 3 to 8 decoder in gate level description. (12) (ii) What are the differences between behavioral and RTL modeling? (4)

(OR)

(b) Write a Verilog program for 8 bits full adder using one bit full adder. The one bit full adder should be written in behavioral modeling.

14. (a) (i) Explain neatly the ASIC design flow. (ii) Briefly discuss about different types of ASIC.

(OR)

(b) (i) Implement the following functions using CMOS f(A,B,C)=ABC+ABC+ABC. (ii)Explain the programmable logic structure available in PAL.

15. (a) Briefly explain the system level test technique with neat diagram.

(OR)

(b) Explain with diagram the design strategies for testing the CMOS devices.

EC 1354 VLSI Design (As per Trichy Anna University syllabus)


May/June 2012 Question paper :< /H2>

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SRV COLLEGE Part-A: 1. Design a NOR gate using basic CMOS technology. 2. Write a note on channel-length modulation. 3. How do the problem of latch up prevented? 4. Write a brief note on transmission gates. 5. What is the link between the shapes and resistance? 6. When the MOS characteristics is in the stage of accumulation, depletion and inversion,draw the capacitance effect? 7. Write a brief note on two phase clocking. 8. Design a simple half adder circuit. 9. What is the function of assert statement? 10. What is meant by overloading?

Part-B: 11. a) (i) Discuss in detail the behavior of NMOS devices under the influence of different terminal voltages? (8) (ii) Derive an expression for Threshold voltage. (8) (or) b) (i) Give a brief note on 1. Body effect 2. Mobility variation 3. Fowler Nordhum Tunneling 4. Impact Ionization (ii) Derive and draw the necessary equations for a small signal model of an MOS transistor. (6) 12. a) Discuss in detail the characteristics of CMOS INVERTER circuit. Also draw the layout diagram and stick diagram for an inverter. (16) (Or) b) Write a detailed note on the following (i) Pseudo NMOS Inverter (ii) Saturated load Inverter (iii) Cascade inverter (iv) TTL interface inverter (5 + 5 + 3 + 3 ) 13. a) With equation and necessary diagram explain in detail the capacitance estimation of MOS Device. (16) (or) b) For a CMOS inverter, draw the equivalent circuit and obtain. (16) (i) Fall delay
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SRV COLLEGE (ii) Rise delay (iii) Delay delay (iv) Gate delay (v) Switch level RC model. 14. a) Design the following circuits using VLSI design. (i)Multiplexers (ii) Multiplier (iii) Full adder. (or) b) Draw a neat layout, circuit diagram and explain with necessary equations for the following circuit. (i) Bit serial adder (ii) Carry save adder (iii) Transmission gate adder (iv) Carry look ahead adder. 15. a) Discuss elaborately the various data types with examples. (8) (or) b) Explain in detail the various levels of modeling with suitable example. (8)

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