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Relion® 670 series

Generator protection REG670


Technical reference manual
Document ID: 1MRK 502 027-UEN
Issued: September 2011
Revision: A
Product version: 1.2

© Copyright 2011 ABB. All rights reserved


Copyright
This document and parts thereof must not be reproduced or copied without written
permission from ABB, and the contents thereof must not be imparted to a third
party, nor used for any unauthorized purpose.

The software or hardware described in this document is furnished under a license


and may be used or disclosed only in accordance with the terms of such license.

Trademarks
ABB and Relion are registered trademarks of ABB Group. All other brand or
product names mentioned in this document may be trademarks or registered
trademarks of their respective holders.

Warranty
Please inquire about the terms of warranty from your nearest ABB representative.

ABB AB
Substation Automation Products
SE-721 59 Västerås
Sweden
Telephone: +46 (0) 21 32 50 00
Facsimile: +46 (0) 21 14 69 18
http://www.abb.com/substationautomation
Disclaimer
The data, examples and diagrams in this manual are included solely for the concept
or product description and are not to be deemed as a statement of guaranteed
properties. All persons responsible for applying the equipment addressed in this
manual must satisfy themselves that each intended application is suitable and
acceptable, including that any applicable safety or other operational requirements
are complied with. In particular, any risks in applications where a system failure and/
or product failure would create a risk for harm to property or persons (including but
not limited to personal injuries or death) shall be the sole responsibility of the
person or entity applying the equipment, and those so responsible are hereby
requested to ensure that all measures are taken to exclude or mitigate such risks.

This document has been carefully checked by ABB but deviations cannot be
completely ruled out. In case any errors are detected, the reader is kindly requested
to notify the manufacturer. Other than under explicit contractual commitments, in
no event shall ABB be responsible or liable for any loss or damage resulting from
the use of this manual or the application of the equipment.
Conformity
This product complies with the directive of the Council of the European
Communities on the approximation of the laws of the Member States relating to
electromagnetic compatibility (EMC Directive 2004/108/EC) and concerning
electrical equipment for use within specified voltage limits (Low-voltage directive
2006/95/EC). This conformity is the result of tests conducted by ABB in
accordance with the product standards EN 50263 and EN 60255-26 for the EMC
directive, and with the product standards EN 60255-1 and EN 60255-27 for the low
voltage directive. The IED is designed in accordance with the international
standards of the IEC 60255 series.
Table of contents

Table of contents

Section 1 Introduction.....................................................................25
Introduction to the technical reference manual.................................25
About the complete set of manuals for an IED............................25
About the technical reference manual.........................................26
This manual.................................................................................27
Introduction.............................................................................27
Principle of operation..............................................................27
Input and output signals.........................................................30
Function block........................................................................30
Setting parameters.................................................................30
Technical data........................................................................31
Intended audience.......................................................................31
Related documents......................................................................31
Revision notes.............................................................................32

Section 2 Analog inputs..................................................................33


Introduction.......................................................................................33
Operation principle...........................................................................33
Function block..................................................................................34
Setting parameters...........................................................................34

Section 3 Local HMI.......................................................................41


Human machine interface ................................................................41
Small size HMI..................................................................................43
Small............................................................................................43
Design.........................................................................................43
Medium size graphic HMI.................................................................45
Medium........................................................................................45
Design.........................................................................................45
Keypad.............................................................................................47
LED...................................................................................................48
Introduction..................................................................................48
Status indication LEDs................................................................48
Indication LEDs...........................................................................48
Local HMI related functions..............................................................49
Introduction..................................................................................49
General setting parameters.........................................................50
Status LEDs.................................................................................50
Design....................................................................................50
Function block........................................................................50

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Input and output signals.........................................................50


Indication LEDs...........................................................................51
Introduction.............................................................................51
Design....................................................................................51
Function block........................................................................58
Input and output signals.........................................................58
Setting parameters.................................................................58

Section 4 Basic IED functions........................................................61


Authorization.....................................................................................61
Principle of operation...................................................................61
Authorization handling in the IED...........................................62
Self supervision with internal event list.............................................63
Introduction..................................................................................63
Principle of operation...................................................................63
Internal signals.......................................................................65
Run-time model......................................................................67
Function block.............................................................................68
Output signals..............................................................................68
Setting parameters......................................................................68
Technical data.............................................................................69
Time synchronization........................................................................69
Introduction..................................................................................69
Principle of operation...................................................................69
General concepts...................................................................69
Real-time clock (RTC) operation............................................72
Synchronization alternatives..................................................73
Function block.............................................................................76
Output signals..............................................................................76
Setting parameters......................................................................76
Technical data.............................................................................79
Parameter setting groups.................................................................79
Introduction..................................................................................79
Principle of operation...................................................................79
Function block.............................................................................81
Input and output signals..............................................................81
Setting parameters......................................................................82
ChangeLock function CHNGLCK.....................................................82
Introduction..................................................................................82
Principle of operation...................................................................82
Function block.............................................................................83
Input and output signals..............................................................83
Setting parameters......................................................................83
Test mode functionality TEST..........................................................83

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Introduction..................................................................................83
Principle of operation...................................................................84
Function block.............................................................................85
Input and output signals..............................................................86
Setting parameters......................................................................86
IED identifiers...................................................................................86
Introduction..................................................................................86
Setting parameters......................................................................87
Product information..........................................................................87
Introduction..................................................................................87
Setting parameters......................................................................87
Factory defined settings..............................................................87
Signal matrix for binary inputs SMBI................................................88
Introduction..................................................................................88
Principle of operation...................................................................88
Function block.............................................................................89
Input and output signals..............................................................89
Signal matrix for binary outputs SMBO ...........................................90
Introduction..................................................................................90
Principle of operation...................................................................90
Function block.............................................................................90
Input and output signals..............................................................91
Signal matrix for mA inputs SMMI....................................................91
Introduction..................................................................................91
Principle of operation...................................................................91
Function block.............................................................................92
Input and output signals..............................................................92
Signal matrix for analog inputs SMAI...............................................92
Introduction..................................................................................92
Principle of operation...................................................................93
Frequency values........................................................................93
Function block.............................................................................94
Input and output signals..............................................................94
Setting parameters......................................................................96
Summation block 3 phase 3PHSUM................................................97
Introduction..................................................................................97
Principle of operation...................................................................97
Function block.............................................................................98
Input and output signals..............................................................98
Setting parameters......................................................................98
Authority status ATHSTAT...............................................................99
Introduction..................................................................................99
Principle of operation...................................................................99

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Function block.............................................................................99
Output signals..............................................................................99
Setting parameters....................................................................100
Denial of service DOS....................................................................100
Introduction................................................................................100
Principle of operation.................................................................100
Function blocks..........................................................................100
Signals.......................................................................................101
Settings......................................................................................101

Section 5 Differential protection...................................................103


Generator differential protection GENPDIF ...................................103
Introduction................................................................................103
Principle of operation.................................................................104
Function calculation principles.............................................105
Fundamental frequency differential currents........................105
Supplementary criteria.........................................................109
Harmonic restrain.................................................................112
Cross-block logic scheme....................................................112
Function block...........................................................................116
Input and output signals............................................................116
Setting parameters....................................................................117
Technical data...........................................................................118
Transformer differential protection T2WPDIF and T3WPDIF ........119
Introduction ...............................................................................119
Principle of operation.................................................................121
Function calculation principles.............................................122
Logic diagram.......................................................................144
Function block...........................................................................150
Input and output signals............................................................151
Setting parameters....................................................................154
Technical data...........................................................................159
Restricted earth fault protection, low impedance REFPDIF ..........160
Introduction................................................................................160
Principle of operation.................................................................161
Fundamental principles of the restricted earthfault
protection..............................................................................161
Restricted earth-fault protection, low impedance as a
differential protection............................................................164
Calculation of differential current and bias current...............165
Detection of external earth faults..........................................167
Algorithm of the restricted earth fault protection...................168
Function block...........................................................................169
Input and output signals............................................................170

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Setting parameters....................................................................170
Technical data...........................................................................171
1Ph High impedance differential protection HZPDIF .....................171
Identification..............................................................................171
Introduction................................................................................171
Principle of operation.................................................................172
Logic diagram.......................................................................172
Function block...........................................................................172
Input and output signals............................................................173
Setting parameters....................................................................173
Technical data...........................................................................173

Section 6 Impedance protection ..................................................175


Full-scheme distance measuring, Mho characteristic
ZMHPDIS ......................................................................................175
Introduction................................................................................175
Principle of operation.................................................................175
Full scheme measurement...................................................175
Impedance characteristic.....................................................176
Basic operation characteristics.............................................177
Theory of operation..............................................................178
Simplified logic diagrams......................................................187
Function block...........................................................................190
Input and output signals............................................................191
Setting parameters....................................................................192
Technical data...........................................................................193
Directional impedance element for mho characteristic
ZDMRDIR.......................................................................................193
Introduction................................................................................194
Principle of operation.................................................................194
Directional impedance element for mho characteristic
ZDMRDIR.............................................................................194
Function block...........................................................................197
Input and output signals............................................................197
Setting parameters....................................................................197
Pole slip protection PSPPPAM ......................................................198
Introduction................................................................................198
Principle of operation.................................................................199
Function block...........................................................................203
Input and output signals............................................................203
Setting parameters....................................................................204
Technical data...........................................................................204
Loss of excitation LEXPDIS............................................................205
Introduction................................................................................205

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Principle of operation.................................................................205
Function block...........................................................................210
Input and output signals............................................................210
Setting parameters....................................................................211
Technical data...........................................................................212
Sensitive rotor earth fault protection, injection based
ROTIPHIZ ......................................................................................212
Introduction................................................................................212
Principle of operation.................................................................212
The injection unit REX060....................................................214
Rotor Earth Fault Protection function...................................215
General measurement of earth fault impedance..................216
Simplified logic diagram.......................................................218
Commissioning tool ICT.......................................................220
Description of input signals........................................................223
Description of output signals.....................................................223
Function block...........................................................................225
Input and output signals............................................................225
Setting parameters....................................................................226
Technical data...........................................................................227
100% stator earth fault protection, injection based STTIPHIZ .......227
Introduction................................................................................228
Principle of operation.................................................................228
Configuration principle..........................................................229
Generator system earthing methods....................................231
100% Stator earth fault protection function..........................235
General measurement of earth fault impedance..................239
Measuring reference impedance..........................................241
Simplified logic diagram.......................................................246
The commissioning tool ICT.................................................247
Description of input signals........................................................249
Description of output signals.....................................................250
Function block...........................................................................251
Input and Output signals............................................................252
Setting parameters....................................................................252
Technical data...........................................................................254

Section 7 Current protection.........................................................255


Instantaneous phase overcurrent protection PHPIOC ..................255
Introduction................................................................................255
Principle of operation.................................................................255
Function block...........................................................................256
Input and output signals............................................................256
Setting parameters....................................................................256

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Technical data...........................................................................257
Four step phase overcurrent protection OC4PTOC ......................257
Introduction................................................................................257
Principle of operation.................................................................257
Function block...........................................................................262
Input and output signals............................................................262
Setting parameters....................................................................264
Technical data...........................................................................269
Instantaneous residual overcurrent protection EFPIOC ................270
Introduction................................................................................270
Principle of operation.................................................................270
Function block...........................................................................271
Input and output signals............................................................271
Setting parameters....................................................................271
Technical data...........................................................................272
Four step residual overcurrent protection EF4PTOC ....................272
Introduction................................................................................272
Principle of operation.................................................................273
Operating quantity within the function..................................273
Internal polarizing.................................................................274
External polarizing for earth-fault function............................276
Base quantities within the protection....................................276
Internal earth-fault protection structure................................276
Four residual overcurrent steps............................................277
Directional supervision element with integrated
directional comparison function............................................278
Second harmonic blocking element.....................................280
Switch on to fault feature......................................................282
Function block...........................................................................284
Input and output signals............................................................285
Setting parameters....................................................................286
Technical data...........................................................................291
Four step directional negative phase sequence overcurrent
protection NS4PTOC .....................................................................291
Introduction................................................................................292
Principle of operation.................................................................292
Operating quantity within the function..................................292
Internal polarizing facility of the function..............................293
External polarizing for negative sequence function..............294
Base quantities within the function.......................................294
Internal negative sequence protection structure..................295
Four negative sequence overcurrent stages........................295
Directional supervision element with integrated
directional comparison function............................................296

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Function block...........................................................................299
Input and output signals............................................................299
Setting parameters....................................................................300
Technical data...........................................................................305
Sensitive directional residual overcurrent and power protection
SDEPSDE .....................................................................................305
Introduction................................................................................305
Principle of operation.................................................................307
Function inputs.....................................................................307
Function block...........................................................................313
Input and output signals............................................................314
Setting parameters....................................................................315
Technical data...........................................................................317
Thermal overload protection, two time constants TRPTTR ...........318
Introduction................................................................................318
Principle of operation.................................................................318
Function block...........................................................................322
Input and output signals............................................................322
Setting parameters....................................................................322
Technical data...........................................................................324
Breaker failure protection CCRBRF ..............................................324
Introduction................................................................................324
Principle of operation.................................................................325
Function block...........................................................................327
Input and output signals............................................................328
Setting parameters....................................................................328
Technical data...........................................................................329
Pole discordance protection CCRPLD ..........................................330
Introduction................................................................................330
Principle of operation.................................................................330
Pole discordance signaling from circuit breaker...................333
Unsymmetrical current detection..........................................333
Function block...........................................................................333
Input and output signals............................................................334
Setting parameters....................................................................334
Technical data...........................................................................335
Directional underpower protection GUPPDUP...............................335
Introduction................................................................................335
Principle of operation.................................................................336
Low pass filtering..................................................................338
Calibration of analog inputs..................................................338
Function block...........................................................................339
Input and output signals............................................................340

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Setting parameters....................................................................340
Technical data...........................................................................341
Directional overpower protection GOPPDOP ................................342
Introduction................................................................................342
Principle of operation.................................................................343
Low pass filtering..................................................................345
Calibration of analog inputs..................................................345
Function block...........................................................................346
Input and output signals............................................................347
Setting parameters....................................................................347
Technical data...........................................................................349
Negativ sequence time overcurrent protection for machines
NS2PTOC ......................................................................................349
Introduction................................................................................349
Principle of operation.................................................................350
Start sensitivity.....................................................................352
Alarm function......................................................................352
Logic diagram.......................................................................352
Function block...........................................................................353
Input and output signals............................................................353
Setting parameters....................................................................354
Technical data...........................................................................355
Accidental energizing protection for synchronous generator
AEGGAPC......................................................................................355
Introduction ...............................................................................355
Principle of operation.................................................................356
Function block...........................................................................357
Input and output signals............................................................357
Setting parameters....................................................................357
Technical data...........................................................................358

Section 8 Voltage protection........................................................359


Two step undervoltage protection UV2PTUV ................................359
Introduction................................................................................359
Principle of operation.................................................................359
Measurement principle.........................................................360
Time delay............................................................................360
Blocking................................................................................365
Design..................................................................................366
Function block...........................................................................368
Input and output signals............................................................368
Setting parameters....................................................................369
Technical data...........................................................................371
Two step overvoltage protection OV2PTOV ..................................372

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Introduction................................................................................372
Principle of operation.................................................................372
Measurement principle.........................................................373
Time delay............................................................................373
Blocking................................................................................379
Design..................................................................................379
Function block...........................................................................381
Input and output signals............................................................381
Setting parameters....................................................................382
Technical data...........................................................................384
Two step residual overvoltage protection ROV2PTOV .................384
Introduction................................................................................384
Principle of operation.................................................................385
Measurement principle.........................................................385
Time delay............................................................................385
Blocking................................................................................390
Design..................................................................................390
Function block...........................................................................391
Input and output signals............................................................392
Setting parameters....................................................................392
Technical data...........................................................................394
Overexcitation protection OEXPVPH ............................................394
Introduction................................................................................394
Principle of operation.................................................................395
Measured voltage.................................................................397
Operate time of the overexcitation protection.......................398
Cooling.................................................................................402
Overexcitation protection function measurands...................402
Overexcitation alarm............................................................403
Logic diagram.......................................................................403
Function block...........................................................................404
Input and output signals............................................................404
Setting parameters....................................................................404
Technical data...........................................................................406
Voltage differential protection VDCPTOV ......................................406
Introduction................................................................................406
Principle of operation.................................................................406
Function block...........................................................................408
Input and output signals............................................................408
Setting parameters....................................................................408
Technical data...........................................................................409
100% Stator earth fault protection, 3rd harmonic based
STEFPHIZ......................................................................................409

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Introduction................................................................................410
Principle of operation.................................................................411
Function block...........................................................................416
Input and output signals............................................................417
Setting parameters....................................................................418
Technical data...........................................................................418

Section 9 Frequency protection....................................................419


Underfrequency protection SAPTUF .............................................419
Introduction................................................................................419
Principle of operation.................................................................419
Measurement principle.........................................................420
Time delay............................................................................420
Voltage dependent time delay..............................................420
Blocking................................................................................422
Design..................................................................................422
Function block...........................................................................423
Input and output signals............................................................423
Setting parameters....................................................................423
Technical data...........................................................................424
Overfrequency protection SAPTOF ...............................................424
Introduction................................................................................425
Principle of operation.................................................................425
Measurement principle.........................................................425
Time delay............................................................................425
Blocking................................................................................426
Design..................................................................................426
Function block...........................................................................427
Input and output signals............................................................427
Setting parameters....................................................................427
Technical data...........................................................................428
Rate-of-change frequency protection SAPFRC .............................428
Introduction................................................................................428
Principle of operation.................................................................428
Measurement principle.........................................................429
Time delay............................................................................429
Blocking................................................................................429
Design..................................................................................430
Function block...........................................................................431
Input and output signals............................................................431
Setting parameters....................................................................431
Technical data...........................................................................432

Section 10 Multipurpose protection................................................433

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General current and voltage protection CVGAPC..........................433


Introduction................................................................................433
Inadvertent generator energization......................................434
Principle of operation.................................................................434
Measured quantities within CVGAPC...................................434
Base quantities for CVGAPC function..................................436
Built-in overcurrent protection steps.....................................437
Built-in undercurrent protection steps...................................442
Built-in overvoltage protection steps....................................443
Built-in undervoltage protection steps..................................443
Inadvertent generator energizing.........................................443
Logic diagram.......................................................................445
Function block...........................................................................450
Input and output signals............................................................451
Setting parameters....................................................................452
Technical data...........................................................................460
Rotor earth fault protection.............................................................461
Introduction................................................................................461
Principle of operation.................................................................462
Rotor earth fault....................................................................462
Technical data...........................................................................465

Section 11 Secondary system supervision.....................................467


Current circuit supervision CCSRDIF ............................................467
Introduction................................................................................467
Principle of operation.................................................................467
Function block...........................................................................469
Input and output signals............................................................469
Setting parameters....................................................................470
Technical data...........................................................................470
Fuse failure supervision SDDRFUF...............................................470
Introduction................................................................................470
Principle of operation.................................................................471
Zero and negative sequence detection................................471
Delta current and delta voltage detection.............................475
Dead line detection...............................................................477
Main logic.............................................................................477
Function block...........................................................................481
Input and output signals............................................................481
Setting parameters....................................................................481
Technical data...........................................................................482

Section 12 Control..........................................................................485

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Synchrocheck, energizing check, and synchronizing


SESRSYN......................................................................................485
Introduction................................................................................485
Principle of operation.................................................................486
Basic functionality.................................................................486
Logic diagrams.....................................................................486
Function block...........................................................................495
Input and output signals............................................................495
Setting parameters....................................................................498
Technical data...........................................................................501
Apparatus control APC...................................................................501
Introduction................................................................................501
Error handling............................................................................502
Bay control QCBAY...................................................................503
Introduction...........................................................................503
Function block......................................................................503
Input and output signals.......................................................504
Setting parameters...............................................................504
Local/Remote switch.................................................................504
Introduction...........................................................................504
Principle of operation............................................................504
Function block......................................................................506
Input and output signals.......................................................506
Setting parameters...............................................................507
Switch controller SCSWI...........................................................507
Introduction...........................................................................508
Principle of operation............................................................508
Function block......................................................................513
Input and output signals.......................................................513
Setting parameters...............................................................514
Circuit breaker SXCBR..............................................................514
Introduction...........................................................................515
Principle of operation............................................................515
Function block......................................................................519
Input and output signals.......................................................519
Setting parameters...............................................................520
Circuit switch SXSWI.................................................................520
Introduction...........................................................................520
Principle of operation............................................................520
Function block......................................................................524
Input and output signals.......................................................524
Setting parameters...............................................................525
Bay reserve QCRSV..................................................................525

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Introduction...........................................................................526
Principle of operation............................................................526
Function block......................................................................528
Input and output signals.......................................................529
Setting parameters...............................................................530
Reservation input RESIN...........................................................530
Introduction...........................................................................530
Principle of operation............................................................530
Function block......................................................................532
Input and output signals.......................................................533
Setting parameters...............................................................534
Interlocking ....................................................................................534
Introduction................................................................................534
Principle of operation.................................................................534
Logical node for interlocking SCILO .........................................537
Introduction...........................................................................537
Logic diagram.......................................................................537
Function block......................................................................538
Input and output signals.......................................................538
Interlocking for busbar earthing switch BB_ES .........................538
Introduction...........................................................................539
Function block......................................................................539
Logic diagram.......................................................................539
Input and output signals.......................................................539
Interlocking for bus-section breaker A1A2_BS..........................540
Introduction...........................................................................540
Function block......................................................................541
Logic diagram.......................................................................542
Input and output signals.......................................................543
Interlocking for bus-section disconnector A1A2_DC ................544
Introduction...........................................................................545
Function block......................................................................545
Logic diagram.......................................................................546
Input and output signals.......................................................546
Interlocking for bus-coupler bay ABC_BC ................................547
Introduction...........................................................................547
Function block......................................................................548
Logic diagram.......................................................................549
Input and output signals.......................................................551
Interlocking for 1 1/2 CB BH .....................................................554
Introduction...........................................................................554
Function blocks....................................................................555
Logic diagrams.....................................................................557

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Input and output signals.......................................................562


Interlocking for double CB bay DB ...........................................566
Introduction...........................................................................566
Function block......................................................................567
Logic diagrams.....................................................................569
Input and output signals ......................................................572
Interlocking for line bay ABC_LINE ..........................................575
Introduction...........................................................................575
Function block......................................................................576
Logic diagram.......................................................................577
Input and output signals.......................................................582
Interlocking for transformer bay AB_TRAFO ............................584
Introduction...........................................................................585
Function block......................................................................586
Logic diagram.......................................................................587
Input and output signals.......................................................588
Position evaluation POS_EVAL.................................................590
Introduction...........................................................................590
Logic diagram.......................................................................590
Function block......................................................................591
Input and output signals.......................................................591
Logic rotating switch for function selection and LHMI
presentation SLGGIO.....................................................................591
Introduction................................................................................591
Principle of operation.................................................................591
Functionality and behaviour ................................................593
Graphical display..................................................................593
Function block...........................................................................595
Input and output signals............................................................595
Setting parameters....................................................................596
Selector mini switch VSGGIO.........................................................597
Introduction................................................................................597
Principle of operation.................................................................597
Function block...........................................................................598
Input and output signals............................................................598
Setting parameters....................................................................599
Generic double point function block DPGGIO................................599
Introduction................................................................................599
Principle of operation.................................................................599
Function block...........................................................................600
Input and output signals............................................................600
Settings......................................................................................600
Single point generic control 8 signals SPC8GGIO.........................600

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Introduction................................................................................600
Principle of operation.................................................................601
Function block...........................................................................601
Input and output signals............................................................601
Setting parameters....................................................................602
AutomationBits, command function for DNP3.0 AUTOBITS..........602
Introduction................................................................................603
Principle of operation.................................................................603
Function block...........................................................................604
Input and output signals............................................................604
Setting parameters....................................................................605
Single command, 16 signals SINGLECMD....................................619
Introduction................................................................................619
Principle of operation.................................................................619
Function block...........................................................................620
Input and output signals............................................................620
Setting parameters....................................................................621

Section 13 Logic.............................................................................623
Tripping logic SMPPTRC ...............................................................623
Introduction................................................................................623
Principle of operation.................................................................623
Logic diagram.......................................................................625
Function block...........................................................................628
Input and output signals............................................................628
Setting parameters....................................................................629
Technical data...........................................................................630
Trip matrix logic TMAGGIO............................................................630
Introduction................................................................................630
Principle of operation.................................................................630
Function block...........................................................................632
Input and output signals............................................................632
Setting parameters....................................................................633
Configurable logic blocks................................................................634
Introduction................................................................................634
Inverter function block INV........................................................634
OR function block OR................................................................635
AND function block AND...........................................................636
Timer function block TIMER......................................................636
Pulse timer function block PULSETIMER..................................637
Exclusive OR function block XOR.............................................637
Loop delay function block LOOPDELAY...................................638
Set-reset with memory function block SRMEMORY.................638
Reset-set with memory function block RSMEMORY.................639

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Controllable gate function block GATE......................................640


Settable timer function block TIMERSET..................................641
Technical data...........................................................................642
Fixed signal function block FXDSIGN............................................642
Principle of operation.................................................................642
Function block...........................................................................643
Input and output signals............................................................643
Setting parameters....................................................................643
Boolean 16 to Integer conversion B16I..........................................644
Introduction................................................................................644
Principle of operation.................................................................644
Function block...........................................................................644
Input and output signals............................................................644
Setting parameters....................................................................645
Boolean 16 to Integer conversion with logic node
representation B16IFCVI................................................................645
Introduction................................................................................645
Principle of operation.................................................................646
Function block...........................................................................646
Input and output signals............................................................646
Setting parameters....................................................................647
Integer to Boolean 16 conversion IB16..........................................647
Introduction................................................................................647
Principle of operation.................................................................647
Function block...........................................................................648
Input and output signals............................................................648
Setting parameters....................................................................649
Integer to Boolean 16 conversion with logic node
representation IB16FCVB...............................................................649
Introduction................................................................................649
Principle of operation.................................................................649
Function block...........................................................................650
Input and output signals............................................................650
Setting parameters....................................................................651

Section 14 Monitoring.....................................................................653
Measurements................................................................................653
Introduction................................................................................654
Principle of operation.................................................................655
Measurement supervision....................................................655
Measurements CVMMXN.....................................................659
Phase current measurement CMMXU.................................664
Phase-phase and phase-neutral voltage measurements
VMMXU, VNMMXU..............................................................665

17
Technical reference manual
Table of contents

Voltage and current sequence measurements VMSQI,


CMSQI..................................................................................665
Function block...........................................................................665
Input and output signals............................................................667
Setting parameters....................................................................670
Technical data...........................................................................683
Event counter CNTGGIO................................................................683
Identification..............................................................................683
Introduction................................................................................683
Principle of operation.................................................................684
Reporting..............................................................................684
Design..................................................................................684
Function block...........................................................................685
Input signals..............................................................................685
Setting parameters....................................................................685
Technical data...........................................................................686
Event function EVENT....................................................................686
Introduction................................................................................686
Principle of operation.................................................................686
Function block...........................................................................688
Input and output signals............................................................688
Setting parameters....................................................................689
Logical signal status report BINSTATREP.....................................691
Introduction................................................................................691
Principle of operation.................................................................691
Function block...........................................................................692
Input and output signals............................................................692
Setting parameters....................................................................693
Measured value expander block RANGE_XP................................693
Introduction................................................................................694
Principle of operation.................................................................694
Function block...........................................................................694
Input and output signals............................................................694
Disturbance report DRPRDRE.......................................................695
Introduction................................................................................695
Principle of operation.................................................................696
Function block...........................................................................703
Input and output signals............................................................705
Setting parameters....................................................................706
Technical data...........................................................................716
Event list.........................................................................................716
Introduction................................................................................716
Principle of operation.................................................................716

18
Technical reference manual
Table of contents

Function block...........................................................................717
Input signals..............................................................................717
Technical data...........................................................................717
Indications......................................................................................717
Introduction................................................................................717
Principle of operation.................................................................718
Function block...........................................................................719
Input signals..............................................................................719
Technical data...........................................................................719
Event recorder ...............................................................................719
Introduction................................................................................719
Principle of operation.................................................................719
Function block...........................................................................720
Input signals..............................................................................720
Technical data...........................................................................720
Trip value recorder.........................................................................720
Introduction................................................................................720
Principle of operation.................................................................721
Function block...........................................................................721
Input signals..............................................................................721
Technical data...........................................................................722
Disturbance recorder......................................................................722
Introduction................................................................................722
Principle of operation.................................................................722
Memory and storage............................................................723
IEC 60870-5-103..................................................................724
Function block...........................................................................725
Input and output signals............................................................725
Setting parameters....................................................................725
Technical data...........................................................................725

Section 15 Metering.......................................................................727
Pulse-counter logic PCGGIO..........................................................727
Introduction................................................................................727
Principle of operation.................................................................727
Function block...........................................................................729
Input and output signals............................................................730
Setting parameters....................................................................730
Technical data...........................................................................731
Function for energy calculation and demand handling
ETPMMTR......................................................................................731
Introduction................................................................................731
Principle of operation.................................................................731
Function block...........................................................................732

19
Technical reference manual
Table of contents

Input and output signals............................................................732


Setting parameters....................................................................733

Section 16 Station communication.................................................735


Overview.........................................................................................735
IEC 61850-8-1 communication protocol.........................................735
Setting parameters....................................................................735
Technical data...........................................................................736
IEC 61850 generic communication I/O functions SPGGIO,
SP16GGIO................................................................................736
Introduction...........................................................................736
Principle of operation............................................................736
Function block......................................................................736
Input and output signals.......................................................737
Setting parameters...............................................................738
IEC 61850 generic communication I/O functions MVGGIO.......738
Principle of operation............................................................738
Function block......................................................................738
Input and output signals.......................................................738
Setting parameters...............................................................739
IEC 61850-8-1 redundant station bus communication..............739
Introduction...........................................................................739
Principle of operation............................................................739
Function block......................................................................741
Output signals......................................................................741
Setting parameters...............................................................741
LON communication protocol.........................................................741
Introduction................................................................................741
Principle of operation.................................................................742
Setting parameters....................................................................760
Technical data...........................................................................760
SPA communication protocol.........................................................760
Introduction................................................................................760
Principle of operation.................................................................761
Communication ports...........................................................768
Design.......................................................................................768
Setting parameters....................................................................769
Technical data...........................................................................769
IEC 60870-5-103 communication protocol.....................................769
Introduction................................................................................769
Principle of operation.................................................................769
General.................................................................................769
Communication ports...........................................................779
Function block...........................................................................779

20
Technical reference manual
Table of contents

Input and output signals............................................................782


Setting parameters....................................................................787
Technical data...........................................................................790
Horizontal communication via GOOSE for interlocking
GOOSEINTLKRCV.........................................................................790
Function block...........................................................................790
Input and output signals............................................................791
Setting parameters....................................................................792
Goose binary receive GOOSEBINRCV..........................................793
Function block...........................................................................793
Input and output signals............................................................793
Setting parameters....................................................................794
Multiple command and transmit MULTICMDRCV,
MULTICMDSND.............................................................................794
Introduction................................................................................795
Principle of operation.................................................................795
Design.......................................................................................795
General.................................................................................795
Function block...........................................................................796
Input and output signals............................................................797
Setting parameters....................................................................798

Section 17 Remote communication................................................799


Binary signal transfer......................................................................799
Introduction................................................................................799
Principle of operation.................................................................799
Setting parameters....................................................................800
Transmission of analog data from LDCM LDCMTransmit..............803
Function block...........................................................................803
Input and output signals............................................................803

Section 18 IED hardware...............................................................805


Overview.........................................................................................805
Variants of case and local HMI display size..............................805
Case from the rear side.............................................................808
Hardware modules.........................................................................812
Overview....................................................................................812
Combined backplane module (CBM).........................................813
Introduction...........................................................................813
Functionality.........................................................................813
Design..................................................................................814
Universal backplane module (UBM)..........................................816
Introduction...........................................................................816
Functionality.........................................................................816

21
Technical reference manual
Table of contents

Design..................................................................................816
Numeric processing module (NUM)..........................................818
Introduction...........................................................................818
Functionality.........................................................................818
Block diagram.......................................................................819
Power supply module (PSM).....................................................820
Introduction...........................................................................820
Design..................................................................................820
Technical data......................................................................820
Local human-machine interface (Local HMI).............................821
Transformer input module (TRM)..............................................821
Introduction...........................................................................821
Design..................................................................................821
Technical data......................................................................822
Analog digital conversion module, with time
synchronization (ADM) .............................................................823
Introduction...........................................................................823
Design..................................................................................823
Binary input module (BIM).........................................................825
Introduction...........................................................................825
Design..................................................................................825
Technical data......................................................................829
Binary output modules (BOM)...................................................829
Introduction...........................................................................829
Design..................................................................................829
Technical data......................................................................831
Binary input/output module (IOM)..............................................832
Introduction...........................................................................832
Design..................................................................................832
Technical data......................................................................834
mA input module (MIM).............................................................835
Introduction...........................................................................835
Design..................................................................................835
Technical data......................................................................837
Serial and LON communication module (SLM) ........................837
Introduction...........................................................................837
Design..................................................................................837
Technical data......................................................................839
Optical ethernet module (OEM).................................................839
Introduction...........................................................................839
Functionality.........................................................................839
Design..................................................................................840
Technical data......................................................................840

22
Technical reference manual
Table of contents

Line data communication module (LDCM)................................841


Introduction...........................................................................841
Design..................................................................................841
Technical data......................................................................842
GPS antenna.............................................................................843
Introduction...........................................................................843
Design..................................................................................843
Technical data......................................................................845
IRIG-B time synchronization module IRIG-B.............................846
Introduction...........................................................................846
Design..................................................................................846
Technical data......................................................................847
Dimensions.....................................................................................848
Case without rear cover.............................................................848
Case with rear cover..................................................................850
Flush mounting dimensions.......................................................852
Side-by-side flush mounting dimensions...................................853
Wall mounting dimensions.........................................................854
External resistor unit for high impedance differential
protection...................................................................................854
External current transformer unit...............................................855
Mounting alternatives.....................................................................856
Flush mounting..........................................................................856
Overview..............................................................................856
Mounting procedure for flush mounting................................857
19” panel rack mounting............................................................858
Overview..............................................................................858
Mounting procedure for 19” panel rack mounting.................859
Wall mounting............................................................................859
Overview..............................................................................859
Mounting procedure for wall mounting.................................860
How to reach the rear side of the IED..................................861
Side-by-side 19” rack mounting.................................................861
Overview..............................................................................861
Mounting procedure for side-by-side rack mounting............862
IED in the 670 series mounted with a RHGS6 case.............862
Side-by-side flush mounting......................................................863
Overview..............................................................................863
Mounting procedure for side-by-side flush mounting...........864
Technical data................................................................................864
Enclosure...................................................................................864
Connection system....................................................................865
Influencing factors.....................................................................865

23
Technical reference manual
Table of contents

Type tests according to standard..............................................866

Section 19 Injection equipment hardware......................................869


Overview.........................................................................................869
Front view of injection unit, coupling capacitor and shunt
resitor unit..................................................................................869
REX060 Injection unit...........................................................869
REX060 Front panel controls...............................................870
Coupling capacitor unit REX061..........................................871
Shunt resistor unit REX062..................................................872
Injection unit REX060 from rear side.........................................873
Injection unit REX060...........................................................873
Injection unit REX060.....................................................................874
Introduction................................................................................874
Design.......................................................................................874
Coupling capacitor unit REX061.....................................................877
Introduction................................................................................877
Design.......................................................................................877
Shunt resistor unit REX062............................................................878
Introduction................................................................................878
Design.......................................................................................878
Technical data................................................................................880
Hardware...................................................................................880
Type tests according to standards.............................................881
Influencing factors.....................................................................883

Section 20 Labels...........................................................................885
Labels on IED.................................................................................885
Labels on injection equipment........................................................888

Section 21 Connection diagrams...................................................893


Injection equipment........................................................................909

Section 22 Inverse time characteristics..........................................935


Application......................................................................................935
Principle of operation......................................................................938
Mode of operation......................................................................938
Inverse characteristics....................................................................943

Section 23 Glossary.......................................................................969

24
Technical reference manual
1MRK 502 027-UEN A Section 1
Introduction

Section 1 Introduction

About this chapter


This chapter explains concepts and conventions used in this manual and provides
information necessary to understand the contents of the manual.

1.1 Introduction to the technical reference manual

1.1.1 About the complete set of manuals for an IED


The user’s manual (UM) is a complete set of five different manuals:

deinstalling & disposal


Planning & purchase

Decommissioning
Commissioning

Maintenance
Engineering

Operation
Installing

Engineeringmanual
Installation and
Commissioning manual

Operator’s manual

Application manual

Technical reference
manual
IEC09000744-1-en.vsd
IEC09000744 V1 EN

The Application Manual (AM) contains application descriptions, setting


guidelines and setting parameters sorted per function. The application manual
should be used to find out when and for what purpose a typical protection function
could be used. The manual should also be used when calculating settings.

The Technical Reference Manual (TRM) contains application and functionality


descriptions and it lists function blocks, logic diagrams, input and output signals,
setting parameters and technical data sorted per function. The technical reference

25
Technical reference manual
Section 1 1MRK 502 027-UEN A
Introduction

manual should be used as a technical reference during the engineering phase,


installation and commissioning phase, and during normal service.

The Installation and Commissioning Manual (ICM) contains instructions on


how to install and commission the protection IED. The manual can also be used as
a reference during periodic testing. The manual covers procedures for mechanical
and electrical installation, energizing and checking of external circuitry, setting and
configuration as well as verifying settings and performing directional tests. The
chapters are organized in the chronological order (indicated by chapter/section
numbers) in which the protection IED should be installed and commissioned.

The Operator’s Manual (OM) contains instructions on how to operate the


protection IED during normal service once it has been commissioned. The
operator’s manual can be used to find out how to handle disturbances or how to
view calculated and measured network data in order to determine the cause of a fault.

The Engineering Manual (EM) contains instructions on how to engineer the IEDs
using the different tools in PCM600. The manual provides instructions on how to
set up a PCM600 project and insert IEDs to the project structure. The manual also
recommends a sequence for engineering of protection and control functions, LHMI
functions as well as communication engineering for IEC 61850 and DNP3.

1.1.2 About the technical reference manual


The following chapters are included in the technical reference manual.

• Local HMI describes the control panel on the IED and explains display
characteristics, control keys and various local HMI features.
• Basic IED functions presents functions for all protection types that are
included in all IEDs, for example, time synchronization, self supervision with
event list, test mode and other general functions.
• Current protection describes functions, for example, over current protection,
breaker failure protection and pole discordance.
• Voltage protection describes functions for under voltage and over voltage
protection and residual over voltage protection.
• Frequency protection describes functions for over frequency, under frequency
and rate of change of frequency protection.
• Multipurpose protection describes the general protection function for current
and voltage.
• Secondary system supervision describes current based functions for current
circuit supervision and fuse failure supervision.
• Control describes control functions, for example, synchronization and
energizing check and other product specific functions.
• Logic describes trip logic and related functions.
• Monitoring describes measurement related functions that are used to provide
data regarding relevant quantities, events and faults, for example.
• Station communication describes Ethernet based communication in general,
including the use of IEC 61850 and horizontal communication via GOOSE.
• Remote communication describes binary and analog signal transfer, and the
associated hardware.

26
Technical reference manual
1MRK 502 027-UEN A Section 1
Introduction

• Hardware describes the IED and its components.


• Connection diagrams provides terminal wiring diagrams and information
regarding connections to and from the IED.
• Inverse time characteristics describes and explains inverse time delay, inverse
time curves and their effects.
• Glossary is a list of terms, acronyms and abbreviations used in ABB technical
documentation.

1.1.3 This manual


The description of each IED related function follows the same structure (where
applicable). The different sections are outlined below.

1.1.3.1 Introduction

Outlines the implementation of a particular protection function.

1.1.3.2 Principle of operation

Describes how the function works, presents a general background to algorithms


and measurement techniques. Logic diagrams are used to illustrate functionality.

Logic diagrams
Logic diagrams describe the signal logic inside the function block and are bordered
by dashed lines.

Signal names
Input and output logic signals consist of two groups of letters separated by two
dashes. The first group consists of up to four letters and presents the abbreviated
name for the corresponding function. The second group presents the functionality
of the particular signal. According to this explanation, the meaning of the signal
BLKTR in figure 4 is as follows:

• BLKTR informs the user that the signal will BLOCK the TRIP command from
the under-voltage function, when its value is a logical one (1).

Input signals are always on the left hand side, and output signals on the right hand
side. Settings are not displayed.

Input and output signals


In a logic diagram, input and output signal paths are shown as a lines that touch the
outer border of the diagram.

Input and output signals can be configured using the ACT tool. They can be
connected to the inputs and outputs of other functions and to binary inputs and
outputs. Examples of input signals are BLKTR, BLOCK and VTSU. Examples
output signals are TRIP, START, STL1, STL2, STL3.

27
Technical reference manual
Section 1 1MRK 502 027-UEN A
Introduction

Setting parameters
Signals in frames with a shaded area on their right hand side represent setting
parameter signals. These parameters can only be set via the PST or LHMI. Their
values are high (1) only when the corresponding setting parameter is set to the
symbolic value specified within the frame. Example is the signal Block TUV=Yes.
Their logical values correspond automatically to the selected setting value.

Internal signals
Internal signals are illustrated graphically and end approximately 2 mm from the
frame edge. If an internal signal path cannot be drawn with a continuous line, the
suffix -int is added to the signal name to indicate where the signal starts and
continues, see figure 1.

BLKTR

TEST

TEST
&
Block TUV=Yes BLOCK-int.
>1

BLOCK

VTSU
BLOCK-int.
&
STUL1N
BLOCK-int.
& >1 & TRIP
t
STUL2N
BLOCK-int.
START
&
STUL3N
STL1

STL2

STL3

xx04000375.vsd
IEC04000375 V1 EN

Figure 1: Logic diagram example with -int signals

External signals
Signal paths that extend beyond the logic diagram and continue in another diagram
have the suffix “-cont.”, see figure 2 and figure 3.

28
Technical reference manual
1MRK 502 027-UEN A Section 1
Introduction

STZMPP-cont.
>1
STCND

& STNDL1L2-cont.
1L1L2
STNDL2L3-cont.
&
1L2L3

& STNDL3L1-cont.
1L3L1

& STNDL1N-cont.
1L1N

& STNDL2N-cont.
1L2N
STNDL3N-cont.
&
1L3N

>1 STNDPE-cont.

>1
1--VTSZ 1--STND
>1 &
1--BLOCK
BLK-cont.

xx04000376.vsd
IEC04000376 V1 EN

Figure 2: Logic diagram example with an outgoing -cont signal

STNDL1N-cont.
>1
STNDL2N-cont. 15 ms
& t STL1
STNDL3N-cont.
STNDL1L2-cont. >1 15 ms
& t STL2
STNDL2L3-cont.
15 ms
STNDL3L1-cont. & t STL3
>1
15 ms
& t START
>1

BLK-cont.

xx04000377.vsd
IEC04000377 V1 EN

Figure 3: Logic diagram example with an incoming -cont signal

29
Technical reference manual
Section 1 1MRK 502 027-UEN A
Introduction

1.1.3.3 Input and output signals

Input and output signals are presented in two separate tables. Each table consists of
two columns. The first column contains the name of the signal and the second
column contains the description of the signal.

1.1.3.4 Function block

Each function block is illustrated graphically.

Input signals are always on the left hand side and output signals on the right hand
side. Settings are not displayed. Special kinds of settings are sometimes available.
These are supposed to be connected to constants in the configuration scheme and
are therefore depicted as inputs. Such signals will be found in the signal list but
described in the settings table.

• The ^ character in front of an input or output signal name in the function block
symbol given for a function, indicates that the user can set a signal name of
their own in PCM600.
• The * character after an input or output signal name in the function block
symbol given for a function, indicates that the signal must be connected to
another function block in the application configuration to achieve a valid
application configuration.

IEC 61850 - 8 -1
Logical Node Mandatory
signal (*)

Inputs Outputs
PCGGIO
BLOCK INVALID
READ_VAL RESTART
BI_PULSE* BLOCKED
RS_CNT NEW_VAL
^SCAL_VAL

en05000511-1-en.vsd
User defined
name (^)

Diagram
Number
IEC05000511 V2 EN

Figure 4: Example of a function block

1.1.3.5 Setting parameters

These are presented in tables and include all parameters associated with the
function in question.

30
Technical reference manual
1MRK 502 027-UEN A Section 1
Introduction

1.1.3.6 Technical data

The technical data section provides specific technical information about the
function or hardware described.

1.1.4 Intended audience


General
This manual addresses system engineers, installation and commissioning
personnel, who use technical data during engineering, installation and
commissioning, and in normal service.

Requirements
The system engineer must have a thorough knowledge of protection systems,
protection equipment, protection functions and the configured functional logics in
the protective devices. The installation and commissioning personnel must have a
basic knowledge in the handling electronic equipment.

1.1.5 Related documents


Documents related to REG670 Identity number
Operator’s manual 1MRK 502 028-UEN
Installation and commissioning manual 1MRK 502 029-UEN
Technical reference manual 1MRK 502 027-UEN
Application manual 1MRK 502 030-UEN
Product guide customized 1MRK 502 031-BEN
Product guide pre-configured 1MRK 502 032-BEN
Rotor Earth Fault Protection with Injection Unit RXTTE4 and REG670 1MRG001910

Connection and Installation components 1MRK 513 003-BEN


Test system, COMBITEST 1MRK 512 001-BEN
Accessories for 670 series IEDs 1MRK 514 012-BEN
670 series SPA and signal list 1MRK 500 092-WEN
IEC 61850 Data objects list for 670 series 1MRK 500 091-WEN
Engineering manual 670 series 1MRK 511 240-UEN
Buyer’s guide REG 216 1MRB520004-BEN
Communication set-up for Relion 670 series 1MRK 505 260-UEN

More information can be found on www.abb.com/substationautomation.

31
Technical reference manual
Section 1 1MRK 502 027-UEN A
Introduction

1.1.6 Revision notes


Revision Description
- First issue for 670 series version 1.2.
A Minor corrections made

32
Technical reference manual
1MRK 502 027-UEN A Section 2
Analog inputs

Section 2 Analog inputs

2.1 Introduction

Analog input channels must be configured and set properly to get correct
measurement results and correct protection operations. For power measuring and
all directional and differential functions the directions of the input currents must be
defined properly. Measuring and protection algorithms in the IED use primary
system quantities. Set values are done in primary quantities as well and it is
important to set the data about the connected current and voltage transformers
properly.

A reference PhaseAngleRef can be defined to facilitate service values reading. This


analog channels phase angle will always be fixed to zero degree and all other angle
information will be shown in relation to this analog input. During testing and
commissioning of the IED the reference channel can be changed to facilitate testing
and service values reading.

The availability of VT inputs depends on the ordered transformer


input module (TRM) type.

2.2 Operation principle

The direction of a current to the IED depends on the connection of the CT. The
main CTs are typically star connected and can be connected with the star point to
the object or from the object. This information must be set to the IED.

Directional conventions for current or power, for example

• Positive value of current or power means quantity direction into the object.
• Negative value of current or power means quantity direction out from the object.

Directional conventions for directional functions (see figure 5)

• Forward means direction into the object.


• Reverse means direction out from the object.

33
Technical reference manual
Section 2 1MRK 502 027-UEN A
Analog inputs

Definition of direction Definition of direction


for directional functions for directional functions
Reverse Forward Forward Reverse
Protected Object
Line, transformer, etc
e.g. P, Q, I e.g. P, Q, I
Measured quantity is Measured quantity is
positive when flowing positive when flowing
towards the object towards the object

Set parameter Set parameter


CTStarPoint CTStarPoint
Correct Setting is Correct Setting is
"ToObject" "FromObject"

en05000456.vsd
IEC05000456 V1 EN

Figure 5: Internal convention of the directionality in the IED

The correct setting of the primary CT direction

• CTStarPoint is set to FromObject or ToObject.


• Positive quantities flow towards the object.
• Direction is defined as Forward and looks towards the object.

The ratios of the main CTs and VTs must be known to use primary system
quantities for settings and calculation in the IED, The user has to set the rated
secondary and primary currents and voltages of the CTs and VTs to provide the
IED with this information.

The CT and VT ratio and the name on respective channel is done under Main
menu/Hardware/Analog modules in the Parameter Settings tool.

2.3 Function block

The function blocks are not represented in the configuration tool.


The signals appear only in the SMT tool when a TRM is included in
the configuration with the function selector tool. In the SMT tool
they can be mapped to the desired virtual input (SMAI) of the IED
and used internally in the configuration.

2.4 Setting parameters

Dependent on ordered IED type.

34
Technical reference manual
1MRK 502 027-UEN A Section 2
Analog inputs

Table 1: AISVBAS Non group settings (basic)


Name Values (Range) Unit Step Default Description
PhaseAngleRef TRM40-Ch1 - - TRM40-Ch1 Reference channel for phase angle
TRM40-Ch2 presentation
TRM40-Ch3
TRM40-Ch4
TRM40-Ch5
TRM40-Ch6
TRM40-Ch7
TRM40-Ch8
TRM40-Ch9
TRM40-Ch10
TRM40-Ch11
TRM40-Ch12
TRM41-Ch1
TRM41-Ch2
TRM41-Ch3
TRM41-Ch4
TRM41-Ch5
TRM41-Ch6
TRM41-Ch7
TRM41-Ch8
TRM41-Ch9
TRM41-Ch10
TRM41-Ch11
TRM41-Ch12
MU1-L1I
MU1-L2I
MU1-L3I
MU1-L4I
MU1-L1U
MU1-L2U
MU1-L3U
MU1-L4U
MU2-L1I
MU2-L2I
MU2-L3I
MU2-L4I
MU2-L1U
MU2-L2U
MU2-L3U
MU2-L4U
MU3-L1I
MU3-L2I
MU3-L3I
MU3-L4I
MU3-L1U
MU3-L2U
MU3-L3U
MU3-L4U

Table 2: TRM_12I Non group settings (basic)


Name Values (Range) Unit Step Default Description
CTStarPoint1 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec1 1 - 10 A 1 1 Rated CT secondary current
CTprim1 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint2 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
Table continues on next page

35
Technical reference manual
Section 2 1MRK 502 027-UEN A
Analog inputs

Name Values (Range) Unit Step Default Description


CTsec2 1 - 10 A 1 1 Rated CT secondary current
CTprim2 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint3 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec3 1 - 10 A 1 1 Rated CT secondary current
CTprim3 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint4 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec4 1 - 10 A 1 1 Rated CT secondary current
CTprim4 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint5 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec5 1 - 10 A 1 1 Rated CT secondary current
CTprim5 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint6 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec6 1 - 10 A 1 1 Rated CT secondary current
CTprim6 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint7 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec7 1 - 10 A 1 1 Rated CT secondary current
CTprim7 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint8 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec8 1 - 10 A 1 1 Rated CT secondary current
CTprim8 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint9 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec9 1 - 10 A 1 1 Rated CT secondary current
CTprim9 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint10 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec10 1 - 10 A 1 1 Rated CT secondary current
CTprim10 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint11 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec11 1 - 10 A 1 1 Rated CT secondary current
CTprim11 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint12 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec12 1 - 10 A 1 1 Rated CT secondary current
CTprim12 1 - 99999 A 1 3000 Rated CT primary current

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Technical reference manual
1MRK 502 027-UEN A Section 2
Analog inputs

Table 3: TRM_6I_6U Non group settings (basic)


Name Values (Range) Unit Step Default Description
CTStarPoint1 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec1 1 - 10 A 1 1 Rated CT secondary current
CTprim1 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint2 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec2 1 - 10 A 1 1 Rated CT secondary current
CTprim2 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint3 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec3 1 - 10 A 1 1 Rated CT secondary current
CTprim3 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint4 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec4 1 - 10 A 1 1 Rated CT secondary current
CTprim4 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint5 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec5 1 - 10 A 1 1 Rated CT secondary current
CTprim5 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint6 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec6 1 - 10 A 1 1 Rated CT secondary current
CTprim6 1 - 99999 A 1 3000 Rated CT primary current
VTsec7 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim7 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec8 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim8 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec9 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim9 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec10 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim10 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec11 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim11 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec12 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim12 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage

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Technical reference manual
Section 2 1MRK 502 027-UEN A
Analog inputs

Table 4: TRM_6I Non group settings (basic)


Name Values (Range) Unit Step Default Description
CTStarPoint1 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec1 1 - 10 A 1 1 Rated CT secondary current
CTprim1 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint2 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec2 1 - 10 A 1 1 Rated CT secondary current
CTprim2 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint3 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec3 1 - 10 A 1 1 Rated CT secondary current
CTprim3 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint4 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec4 1 - 10 A 1 1 Rated CT secondary current
CTprim4 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint5 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec5 1 - 10 A 1 1 Rated CT secondary current
CTprim5 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint6 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec6 1 - 10 A 1 1 Rated CT secondary current
CTprim6 1 - 99999 A 1 3000 Rated CT primary current

Table 5: TRM_7I_5U Non group settings (basic)


Name Values (Range) Unit Step Default Description
CTStarPoint1 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec1 1 - 10 A 1 1 Rated CT secondary current
CTprim1 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint2 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec2 1 - 10 A 1 1 Rated CT secondary current
CTprim2 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint3 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec3 1 - 10 A 1 1 Rated CT secondary current
CTprim3 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint4 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec4 1 - 10 A 1 1 Rated CT secondary current
Table continues on next page

38
Technical reference manual
1MRK 502 027-UEN A Section 2
Analog inputs

Name Values (Range) Unit Step Default Description


CTprim4 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint5 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec5 1 - 10 A 1 1 Rated CT secondary current
CTprim5 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint6 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec6 1 - 10 A 1 1 Rated CT secondary current
CTprim6 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint7 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec7 1 - 10 A 1 1 Rated CT secondary current
CTprim7 1 - 99999 A 1 3000 Rated CT primary current
VTsec8 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim8 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec9 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim9 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec10 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim10 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec11 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim11 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec12 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim12 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage

Table 6: TRM_9I_3U Non group settings (basic)


Name Values (Range) Unit Step Default Description
CTStarPoint1 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec1 1 - 10 A 1 1 Rated CT secondary current
CTprim1 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint2 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec2 1 - 10 A 1 1 Rated CT secondary current
CTprim2 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint3 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec3 1 - 10 A 1 1 Rated CT secondary current
CTprim3 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint4 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec4 1 - 10 A 1 1 Rated CT secondary current
CTprim4 1 - 99999 A 1 3000 Rated CT primary current
Table continues on next page

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Technical reference manual
Section 2 1MRK 502 027-UEN A
Analog inputs

Name Values (Range) Unit Step Default Description


CTStarPoint5 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec5 1 - 10 A 1 1 Rated CT secondary current
CTprim5 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint6 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec6 1 - 10 A 1 1 Rated CT secondary current
CTprim6 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint7 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec7 1 - 10 A 1 1 Rated CT secondary current
CTprim7 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint8 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec8 1 - 10 A 1 1 Rated CT secondary current
CTprim8 1 - 99999 A 1 3000 Rated CT primary current
CTStarPoint9 FromObject - - ToObject ToObject= towards protected object,
ToObject FromObject= the opposite
CTsec9 1 - 10 A 1 1 Rated CT secondary current
CTprim9 1 - 99999 A 1 3000 Rated CT primary current
VTsec10 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim10 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec11 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim11 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage
VTsec12 0.001 - 999.999 V 0.001 110.000 Rated VT secondary voltage
VTprim12 0.05 - 2000.00 kV 0.05 400.00 Rated VT primary voltage

40
Technical reference manual
1MRK 502 027-UEN A Section 3
Local HMI

Section 3 Local HMI

About this chapter


This chapter describes the structure and use of local HMI, which is the control
panel at the IED.

3.1 Human machine interface

The local human machine interface is available in a small and a medium sized
model. The difference between the two models is the size of the LCD. The small
size LCD can display seven lines of text and the medium size LCD can display the
single line diagram with up to 15 objects on each page. Up to 12 single line
diagram pages can be defined, depending on the product capability.

The local HMI is divided into zones with different functionality.

• Status indication LEDs.


• Alarm indication LEDs, which consist of 15 LEDs (6 red and 9 yellow) with
user printable label. All LEDs are configurable from PCM600.
• Liquid crystal display (LCD).
• Keypad with push buttons for control and navigation purposes, switch for
selection between local and remote control and reset.
• Isolated RJ45 communication port.

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Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

IEC05000055-LITEN V1 EN

Figure 6: Small, alpha numeric HMI

IEC05000056-LITEN V1 EN

Figure 7: Example of medium graphic HMI

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Technical reference manual
1MRK 502 027-UEN A Section 3
Local HMI

3.2 Small size HMI

3.2.1 Small
The small sized HMI is available for 1/2, 3/4 and 1/1 x 19” case. The LCD on the
small HMI measures 32 x 90 mm and displays 7 lines with up to 40 characters per
line. The first line displays the product name and the last line displays date and
time. The remaining 5 lines are dynamic. This LCD has no graphic display potential.

3.2.2 Design
The local HMI is identical for both the 1/2, 3/4 and 1/1 cases. The different parts of
the small local HMI are shown in figure 8

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Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

1 2 3

en05000055.eps
8 7
IEC05000055-CALLOUT V1 EN

Figure 8: Small graphic HMI

1 Status indication LEDs


2 LCD
3 Indication LEDs
4 Label
5 Local/Remote LEDs
6 RJ45 port
7 Communication indication LED
8 Keypad

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Technical reference manual
1MRK 502 027-UEN A Section 3
Local HMI

3.3 Medium size graphic HMI

3.3.1 Medium
The following case sizes can be equipped with the medium size LCD:

• 1/2 x 19”
• 3/4 x 19”
• 1/1 x 19”

This is a fully graphical monochrome LCD which measures 120 x 90 mm. It has 28
lines with up to 40 characters per line. To display the single line diagram, this LCD
is required.

3.3.2 Design
The different parts of the medium size local HMI are shown in figure 9. The local
HMI exists in an IEC version and in an ANSI version. The difference is on the
keypad operation buttons and the yellow LED designation.

45
Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

1 2 3

en05000056.eps
8 7
IEC05000056-CALLOUT V1 EN

Figure 9: Medium size graphic HMI

1 Status indication LEDs


2 LCD
3 Indication LEDs
4 Label
5 Local/Remote LEDs
6 RJ45 port
7 Communication indication LED
8 Keypad

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Technical reference manual
1MRK 502 027-UEN A Section 3
Local HMI

3.4 Keypad

The keypad is used to monitor and operate the IED. The keypad has the same look
and feel in all IEDs. LCD screens and other details may differ but the way the keys
function is identical.

IEC05000153 V1 EN

Figure 10: The HMI keypad.

Table 7 describes the HMI keys that are used to operate the IED.

Table 7: HMI keys on the front of the IED


Key Function

Press to close or energize a breaker or disconnector.


IEC05000101 V1 EN

Press to open a breaker or disconnector.


IEC05000102 V1 EN

Press to open two sub menus: Key operation and IED information.
IEC05000103 V1 EN

Press to clear entries, cancel commands or edit.


IEC05000104 V1 EN

Press to open the main menu and to move to the default screen.
IEC05000105 V1 EN

Press to set the IED in local or remote control mode.


IEC05000106 V1 EN

Press to open the reset screen.


IEC05000107 V1 EN

Press to start the editing mode and confirm setting changes, when in editing mode.
IEC05000108 V1 EN

Table continues on next page

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Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

Key Function

Press to navigate forward between screens and move right in editing mode.
IEC05000109 V1 EN

Press to navigate backwards between screens and move left in editing mode.
IEC05000110 V1 EN

Press to move up in the single line diagram and in the menu tree.
IEC05000111 V1 EN

Press to move down in the single line diagram and in the menu tree.
IEC05000112 V1 EN

3.5 LED

3.5.1 Introduction
The LED module is a unidirectional means of communicating. This means that
events may occur that activate a LED in order to draw the operators attention to
something that has occurred and needs some sort of action.

3.5.2 Status indication LEDs


The three LEDs above the LCD provide information as shown in the table below.
LED Indication Information
Green:
Steady In service
Flashing Internal failure
Dark No power supply
Yellow:
Steady Dist. rep. triggered
Flashing Terminal in test mode
Red:
Steady Trip command issued

3.5.3 Indication LEDs


The LED indication module comprising 15 LEDs is standard in 670 series. Its main
purpose is to present an immediate visual information for protection indications or
alarm signals.

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1MRK 502 027-UEN A Section 3
Local HMI

Alarm indication LEDs and hardware associated LEDs are located on the right
hand side of the front panel. Alarm LEDs are located on the right of the LCD
screen and show steady or flashing light.

• Steady light indicates normal operation.


• Flashing light indicates alarm.

Alarm LEDs can be configured in PCM600 and depend on the binary logic.
Therefore they can not be configured on the local HMI.

Typical examples of alarm LEDs

• Bay controller failure


• CB close blocked
• Interlocking bypassed
• Differential protection trip
• SF6 Gas refill
• Position error
• CB spring charge alarm
• Oil temperature alarm
• Thermal overload trip
• Bucholtz trip

The RJ45 port has a yellow LED indicating that communication has been
established between the IED and a computer.

The Local/Remote key on the front panel has two LEDs indicating whether local or
remote control of the IED is active.

3.6 Local HMI related functions

3.6.1 Introduction
The local HMI can be adapted to the application configuration and to user preferences.

• Function block LocalHMI


• Function block LEDGEN
• Setting parameters

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Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

3.6.2 General setting parameters


Table 8: SCREEN Non group settings (basic)
Name Values (Range) Unit Step Default Description
Language English - - English Local HMI language
OptionalLanguage
DisplayTimeout 10 - 120 Min 10 60 Local HMI display timeout
AutoRepeat Off - - On Activation of auto-repeat (On) or not (Off)
On
ContrastLevel -10 - 20 % 1 0 Contrast level for display
DefaultScreen 0-0 - 1 0 Default screen
EvListSrtOrder Latest on top - - Latest on top Sort order of event list
Oldest on top
SymbolFont IEC - - IEC Symbol font for Single Line Diagram
ANSI

3.6.3 Status LEDs

3.6.3.1 Design

The function block LocalHMI controls and supplies information about the status of
the status indication LEDs. The input and output signals of local HMI are
configured with PCM600.

The function block can be used if any of the signals are required in a configuration
logic.

See section "Status indication LEDs" for information about the LEDs.

3.6.3.2 Function block


LocalHMI
CLRLEDS HMI-ON
RED-S
YELLOW-S
YELLOW-F
CLRPULSE
LEDSCLRD

IEC05000773-2-en.vsd
IEC05000773 V2 EN

Figure 11: LocalHMI function block

3.6.3.3 Input and output signals


Table 9: LocalHMI Input signals
Name Type Default Description
CLRLEDS BOOLEAN 0 Input to clear the LCD-HMI LEDs

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1MRK 502 027-UEN A Section 3
Local HMI

Table 10: LocalHMI Output signals


Name Type Description
HMI-ON BOOLEAN Backlight of the LCD display is active
RED-S BOOLEAN Red LED on the LCD-HMI is steady
YELLOW-S BOOLEAN Yellow LED on the LCD-HMI is steady
YELLOW-F BOOLEAN Yellow LED on the LCD-HMI is flashing
CLRPULSE BOOLEAN A pulse is provided when the LEDs on the LCD-
HMI are cleared
LEDSCLRD BOOLEAN Active when the LEDs on the LCD-HMI are not
active

3.6.4 Indication LEDs

3.6.4.1 Introduction

The function block LEDGEN controls and supplies information about the status of
the indication LEDs. The input and output signals of LEDGEN are configured with
PCM600. The input signal for each LED is selected individually with the Signal
Matrix Tool in PCM600.

• LEDs (number 1–6) for trip indications are red.


• LEDs (number 7–15) for start indications are yellow.

Each indication LED on the local HMI can be set individually to operate in six
different sequences

• Two sequences operate as follow type.


• Four sequences operate as latch type.
• Two of the latching sequence types are intended to be used as a
protection indication system, either in collecting or restarting mode, with
reset functionality.
• Two of the latching sequence types are intended to be used as signaling
system in collecting (coll) mode with an acknowledgment functionality.

The light from the LEDs can be steady (-S) or flashing (-F). See the technical
reference manual for more information.

3.6.4.2 Design

The information on the LEDs is stored at loss of the auxiliary power to the IED in
some of the modes of LEDGEN. The latest LED picture appears immediately after
the IED is successfully restarted.

Operating modes
• Collecting mode

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Section 3 1MRK 502 027-UEN A
Local HMI

• LEDs which are used in collecting mode of operation are accumulated


continuously until the unit is acknowledged manually. This mode is
suitable when the LEDs are used as a simplified alarm system.

• Re-starting mode
• In the re-starting mode of operation each new start resets all previous
active LEDs and activates only those which appear during one
disturbance. Only LEDs defined for re-starting mode with the latched
sequence type 6 (LatchedReset-S) will initiate a reset and a restart at a
new disturbance. A disturbance is defined to end a settable time after the
reset of the activated input signals or when the maximum time limit has
elapsed.

Acknowledgment/reset
• From local HMI
• Active indications can be acknowledged or reset manually. Manual
acknowledgment and manual reset have the same meaning and is a
common signal for all the operating sequences and LEDs. The function
is positive edge triggered, not level triggered. The acknowledged or reset
is performed via the reset button and menus on the local HMI. See the
operator's manual for more information.

• From function input


• Active indications can also be acknowledged or reset from an input,
RESET, to the function. This input can, for example, be configured to a
binary input operated from an external push button. The function is
positive edge triggered, not level triggered. This means that even if the
button is continuously pressed, the acknowledgment or reset only affects
indications active at the moment when the button is first pressed.

• Automatic reset
• Automatic reset can only be performed for indications defined for re-
starting mode with the latched sequence type 6 (LatchedReset-S). When
automatic reset of the LEDs has been performed, still persisting
indications will be indicated with a steady light.

Operating sequences
The operating sequences can be of type Follow or Latched.

• For the Follow type the LED follows the input signal completely.
• For the Latched type each LED latches to the corresponding input signal until
it is reset.

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1MRK 502 027-UEN A Section 3
Local HMI

Figure 12 show the function of available sequences that are selectable for each
LED separately.

• The acknowledgment or reset function is not applicable for sequence 1 and 2


(Follow type).
• Sequence 3 and 4 (Latched type with acknowledgement) are only working in
collecting mode.
• Sequence 5 is working according to Latched type and collecting mode.
• Sequence 6 is working according to Latched type and re-starting mode.

The letters S and F in the sequence names have the meaning S = Steady and F =
Flashing.

At the activation of the input signal, the indication operates according to the
selected sequence diagrams.

In the sequence diagrams the LEDs have the characteristics as shown in figure 12.

= No indication = Steady light = Flash

en05000506.vsd
IEC05000506 V1 EN

Figure 12: Symbols used in the sequence diagrams

Sequence 1 (Follow-S)
This sequence follows all the time, with a steady light, the corresponding input
signals. It does not react on acknowledgment or reset. Every LED is independent of
the other LEDs in its operation.

Activating
signal

LED

IEC01000228_2_en.vsd
IEC01000228 V2 EN

Figure 13: Operating sequence 1 (Follow-S)

Sequence 2 (Follow-F)
This sequence is the same as sequence 1, Follow-S, but the LEDs are flashing
instead of showing steady light.

Sequence 3 (LatchedAck-F-S)
This sequence has a latched function and works in collecting mode. Every LED is
independent of the other LEDs in its operation. At the activation of the input signal,
the indication starts flashing. After acknowledgment the indication disappears if

53
Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

the signal is not present any more. If the signal is still present after
acknowledgment it gets a steady light.

Activating
signal

LED

Acknow.
en01000231.vsd
IEC01000231 V1 EN

Figure 14: Operating sequence 3 (LatchedAck-F-S)

Sequence 4 (LatchedAck-S-F)
This sequence has the same functionality as sequence 3, but steady and flashing
light have been alternated.

Sequence 5 (LatchedColl-S)
This sequence has a latched function and works in collecting mode. At the
activation of the input signal, the indication will light up with a steady light. The
difference to sequence 3 and 4 is that indications that are still activated will not be
affected by the reset that is, immediately after the positive edge of the reset has
been executed a new reading and storing of active signals is performed. Every LED
is independent of the other LEDs in its operation.

Activating
signal

LED

Reset

IEC01000235_2_en.vsd
IEC01000235 V2 EN

Figure 15: Operating sequence 5 (LatchedColl-S)

Sequence 6 (LatchedReset-S)
In this mode all activated LEDs, which are set to sequence 6 (LatchedReset-S), are
automatically reset at a new disturbance when activating any input signal for other
LEDs set to sequence 6 (LatchedReset-S). Also in this case indications that are still
activated will not be affected by manual reset, that is, immediately after the
positive edge of that the manual reset has been executed a new reading and storing

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1MRK 502 027-UEN A Section 3
Local HMI

of active signals is performed. LEDs set for sequence 6 are completely independent
in its operation of LEDs set for other sequences.

Definition of a disturbance
A disturbance is defined to last from the first LED set as LatchedReset-S is
activated until a settable time, tRestart, has elapsed after that all activating signals
for the LEDs set as LatchedReset-S have reset. However if all activating signals
have reset and some signal again becomes active before tRestart has elapsed, the
tRestart timer does not restart the timing sequence. A new disturbance start will be
issued first when all signals have reset after tRestart has elapsed. A diagram of this
functionality is shown in figure 16.

From
disturbance
length control ³1 New
per LED ³1 disturbance
set to
sequence 6
tRestart
& t

&
³1

³1
&

en01000237.vsd
IEC01000237 V1 EN

Figure 16: Activation of new disturbance

In order not to have a lock-up of the indications in the case of a persisting signal
each LED is provided with a timer, tMax, after which time the influence on the
definition of a disturbance of that specific LED is inhibited. This functionality is
shown i diagram in figure 17.

Activating signal
To LED

To disturbance
AND
tMax length control
t
en05000507.vsd
IEC05000507 V1 EN

Figure 17: Length control of activating signals

Timing diagram for sequence 6


Figure 18 shows the timing diagram for two indications within one disturbance.

55
Technical reference manual
Section 3 1MRK 502 027-UEN A
Local HMI

Disturbance
tRestart

Activating
signal 1

Activating
signal 2

LED 1

LED 2

Automatic
reset

Manual
reset
IEC01000239_2-en.vsd
IEC01000239 V2 EN

Figure 18: Operating sequence 6 (LatchedReset-S), two indications within


same disturbance

Figure 19 shows the timing diagram for a new indication after tRestart time has
elapsed.

Disturbance Disturbance

tRestart tRestart

Activating
signal 1

Activating
signal 2

LED 1

LED 2

Automatic
reset

Manual
reset
IEC01000240_2_en.vsd
IEC01000240 V2 EN

Figure 19: Operating sequence 6 (LatchedReset-S), two different disturbances

56
Technical reference manual
1MRK 502 027-UEN A Section 3
Local HMI

Figure 20 shows the timing diagram when a new indication appears after the first
one has reset but before tRestart has elapsed.

Disturbance

tRestart

Activating
signal 1

Activating
signal 2

LED 1

LED 2

Automatic
reset

Manual
reset
IEC01000241_2_en.vsd
IEC01000241 V2 EN

Figure 20: Operating sequence 6 (LatchedReset-S), two indications within


same disturbance but with reset of activating signal between

Figure 21 shows the timing diagram for manual reset.

Disturbance

tRestart

Activating
signal 1

Activating
signal 2

LED 1

LED 2

Automatic
reset

Manual
reset
IEC01000242_2_en.vsd
IEC01000242 V2 EN

Figure 21: Operating sequence 6 (LatchedReset-S), manual reset

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3.6.4.3 Function block


LEDGEN
BLOCK NEWIND
RESET ACK
LEDTEST

IEC05000508_2_en.vsd
IEC05000508 V2 EN

Figure 22: LEDGEN function block

3.6.4.4 Input and output signals


Table 11: LEDGEN Input signals
Name Type Default Description
BLOCK BOOLEAN 0 Input to block the operation of the LED-unit
RESET BOOLEAN 0 Input to acknowledge/reset the indications of the
LED-unit
LEDTEST BOOLEAN 0 Input for external LED test

Table 12: LEDGEN Output signals


Name Type Description
NEWIND BOOLEAN A new signal on any of the indication inputs occurs
ACK BOOLEAN A pulse is provided when the LEDs are
acknowledged

3.6.4.5 Setting parameters


Table 13: LEDGEN Non group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation mode for the LED function
On
tRestart 0.0 - 100.0 s 0.1 0.0 Defines the disturbance length
tMax 0.0 - 100.0 s 0.1 0.0 Maximum time for the definition of a
disturbance
SeqTypeLED1 Follow-S - - Follow-S Sequence type for LED 1
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED2 Follow-S - - Follow-S Sequence type for LED 2
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Table continues on next page

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Local HMI

Name Values (Range) Unit Step Default Description


SeqTypeLED3 Follow-S - - Follow-S Sequence type for LED 3
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED4 Follow-S - - Follow-S Sequence type for LED 4
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED5 Follow-S - - Follow-S Sequence type for LED 5
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED6 Follow-S - - Follow-S Sequence type for LED 6
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED7 Follow-S - - Follow-S Sequence type for LED 7
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED8 Follow-S - - Follow-S sequence type for LED 8
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED9 Follow-S - - Follow-S Sequence type for LED 9
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED10 Follow-S - - Follow-S Sequence type for LED 10
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED11 Follow-S - - Follow-S Sequence type for LED 11
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
Table continues on next page

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Name Values (Range) Unit Step Default Description


SeqTypeLED12 Follow-S - - Follow-S Sequence type for LED 12
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED13 Follow-S - - Follow-S Sequence type for LED 13
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED14 Follow-S - - Follow-S Sequence type for LED 14
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S
SeqTypeLED15 Follow-S - - Follow-S Sequence type for LED 15
Follow-F
LatchedAck-F-S
LatchedAck-S-F
LatchedColl-S
LatchedReset-S

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1MRK 502 027-UEN A Section 4
Basic IED functions

Section 4 Basic IED functions

About this chapter


This chapter presents functions that are basic to all 670 series IEDs. Typical
functions in this category are time synchronization, self supervision and test mode.

4.1 Authorization

To safeguard the interests of our customers, both the IED and the tools that are
accessing the IED are protected, by means of authorization handling. The
authorization handling of the IED and the PCM600 is implemented at both access
points to the IED:

• local, through the local HMI


• remote, through the communication ports

4.1.1 Principle of operation


There are different levels (or types) of users that can access or operate different
areas of the IED and tools functionality. The pre-defined user types are given in
Table 14.

Be sure that the user logged on to the IED has the access required
when writing particular data to the IED from PCM600.

The meaning of the legends used in the table:


• R= Read
• W= Write
• - = No access rights

Table 14: Pre-defined user types


Access rights System Protection Design User
Guest Super User SPA Guest
Operator Engineer Engineer Administrator
Basic setting possibilities (change R R/W R R/W R/W R/W R
setting group, control settings,
limit supervision)
Advanced setting possibilities (for R R/W R R R/W R/W R
example protection settings)
Basic control possibilities (process R R/W R/W R/W R/W R/W R
control, no bypass)
Table continues on next page

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Basic IED functions

Access rights System Protection Design User


Guest Super User SPA Guest
Operator Engineer Engineer Administrator
Advanced control possibilities R R/W R/W R/W R/W R/W R
(process control including interlock
trigg)
Basic command handling (for R R/W R R/W R/W R/W R
example clear LEDs, manual trigg)
Advanced command handling (for R R/W R R R/W R/W R/W
example clear disturbance record)
Basic configuration possibilities (I/ R R/W R R R R/W R/W
O-configuration in SMT)
Advanced configuration R R/W R R R R/W R/W
possibilities (application
configuration including SMT, GDE
and CMT)
File loading (database loading - R/W - - - R/W R/W
from XML-file)
File dumping (database dumping - R/W - - - R/W R/W
to XML-file)
File transfer (FTP file transfer) - R/W - R/W R/W R/W R/W
File transfer (limited) (FTP file R R/W R R/W R/W R/W R/W
transfer)
File Transfer (SPA File Transfer) - R/W - - - R/W -
Database access for normal user R R/W R R/W R/W R/W R/W
User administration (user R R/W R R R R R/W
management – FTP File Transfer)
User administration (user - R/W - - - - -
management – SPA File Transfer)

The IED users can be created, deleted and edited only with the User Management
Tool (UMT) within PCM600. The user can only LogOn or LogOff on the local
HMI on the IED, there are no users, groups or functions that can be defined on
local HMI.

Only characters A - Z, a - z and 0 - 9 should be used in user names


and passwords.

At least one user must be included in the UserAdministrator group


to be able to write users, created in PCM600, to IED.

4.1.1.1 Authorization handling in the IED

At delivery the default user is the SuperUser. No Log on is required to operate the
IED until a user has been created with the User Management Tool.

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Once a user is created and downloaded to the IED, that user can perform a Log on,
introducing the password assigned in the tool.

If there is no user created, an attempt to log on will display a message box: “No
user defined!”

If one user leaves the IED without logging off, then after the timeout (set in Main
menu/Settings/General Settings/HMI/Screen/Display Timeout) elapses, the IED
returns to Guest state, when only reading is possible. The display time out is set to
60 minutes at delivery.

If there are one or more users created with the User Management Tool and
downloaded into the IED, then, when a user intentionally attempts a Log on or
when the user attempts to perform an operation that is password protected, the Log
on window will appear.

The cursor is focused on the User identity field, so upon pressing the “E” key, the
user can change the user name, by browsing the list of users, with the “up” and
“down” arrows. After choosing the right user name, the user must press the “E”
key again. When it comes to password, upon pressing the “E” key, the following
character will show up: “$”. The user must scroll for every letter in the password.
After all the letters are introduced (passwords are case sensitive) choose OK and
press the “E” key again.

If everything is alright at a voluntary Log on, the local HMI returns to the
Authorization screen. If the Log on is OK, when required to change for example a
password protected setting, the local HMI returns to the actual setting folder. If the
Log on has failed, then the Log on window opens again, until either the user makes
it right or presses “Cancel”.

4.2 Self supervision with internal event list

4.2.1 Introduction
Self supervision with internal event list function listens and reacts to internal
system events, generated by the different built-in self-supervision elements. The
internal events are saved in an internal event list.

4.2.2 Principle of operation


The self-supervision operates continuously and includes:

• Normal micro-processor watchdog function.


• Checking of digitized measuring signals.
• Other alarms, for example hardware and time synchronization.

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The self-supervision function status can be monitored from the local HMI, from the
Event Viewer in PCM600 or from a SMS/SCS system.

Under the Diagnostics menu in the local HMI the present information from the self-
supervision function can be reviewed. The information can be found under Main
menu/Diagnostics/Internal events or Main menu/Diagnostics/IED status/
General. The information from the self-supervision function is also available in the
Event Viewer in PCM600.

A self-supervision summary can be obtained by means of the potential free alarm


contact (INTERNAL FAIL) located on the power supply module. The function of
this output relay is an OR-function between the INT-FAIL signal see figure 24 and
a couple of more severe faults that can occur in the IED, see figure 23

IEC04000520 V1 EN

Figure 23: Hardware self-supervision, potential-free alarm contact

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IO fail
OR Set e.g. BIM 1 Error
IO stopped
Reset
IO started
e.g. IOM2 Error OR
e.g. IO (n) Error Internal
OR FAIL
LON ERROR

FTF fatal error


OR
Watchdog NUMFAIL
RTE fatal error
Internal
Set WARN
RTE Appl-fail
OR
RTE OK Reset

IEC61850 not ready NUMWARNING


OR
RTCERROR Set RTCERROR
RTC OK Reset

TIMESYNCHERROR
OR TIMESYNCHERROR
Time reset Set

SYNCH OK Reset
SETCHGD
Settings changed
1 second pulse

en04000519-1.vsd
IEC04000519 V2 EN

Figure 24: Software self-supervision, IES (IntErrorSign) function block

Some signals are available from the INTERRSIG function block. The signals from
this function block are sent as events to the station level of the control system. The
signals from the INTERRSIG function block can also be connected to binary
outputs for signalization via output relays or they can be used as conditions for
other functions if required/desired.

Individual error signals from I/O modules can be obtained from respective module
in the Signal Matrix tool. Error signals from time synchronization can be obtained
from the time synchronization block TIME.

4.2.2.1 Internal signals

Self supervision provides several status signals, that tells about the condition of the
IED. As they provide information about the internal status of the IED, they are also
called internal signals. The internal signals can be divided into two groups.

• Standard signals are always presented in the IED, see Table 15.
• Hardware dependent internal signals are collected depending on the hardware
configuration, see Table 16.

Explanations of internal signals are listed in Table 17.

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Table 15: Self-supervision's standard internal signals


Name of signal Description
FAIL Internal Fail status
WARNING Internal Warning status
NUMFAIL CPU module Fail status
NUMWARNING CPU module Warning status
RTCERROR Real Time Clock status
TIMESYNCHERROR Time Synchronization status
RTEERROR Runtime Execution Error status
IEC61850ERROR IEC 61850 Error status
WATCHDOG SW Watchdog Error status
LMDERROR LON/Mip Device Error status
APPERROR Runtime Application Error status
SETCHGD Settings changed
SETGRPCHGD Setting groups changed
FTFERROR Fault Tolerant Filesystem status

Table 16: Self-supervision's hardware dependent internal signals


Card Name of signal Description
PSM PSM-Error Power Supply Module Error status
ADOne ADOne-Error Analog In Module Error status
BIM BIM-Error Binary In Module Error status
BOM BOM-Error Binary Out Module Error status
IOM IOM-Error In/Out Module Error status
MIM MIM-Error Millampere Input Module Error status
LDCM LDCM-Error Line Differential Communication Error status

Table 17: Explanations of internal signals


Name of signal Reasons for activation
FAIL This signal will be active if one or more of the following internal
signals are active; NUMFAIL, LMDERROR, WATCHDOG,
APPERROR, RTEERROR, FTFERROR, or any of the HW
dependent signals
WARNING This signal will be active if one or more of the following internal
signals are active; RTCERROR, IEC61850ERROR,
TIMESYNCHERROR
NUMFAIL This signal will be active if one or more of the following internal
signals are active; WATCHDOG, APPERROR, RTEERROR,
FTFERROR
NUMWARNING This signal will be active if one or more of the following internal
signals are active; RTCERROR, IEC61850ERROR
RTCERROR This signal will be active when there is a hardware error with the
real time clock.
Table continues on next page

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Name of signal Reasons for activation


TIMESYNCHERROR This signal will be active when the source of the time
synchronization is lost, or when the time system has to make a
time reset.
RTEERROR This signal will be active if the Runtime Engine failed to do some
actions with the application threads. The actions can be loading
of settings or parameters for components, changing of setting
groups, loading or unloading of application threads.
IEC61850ERROR This signal will be active if the IEC 61850 stack did not succeed
in some actions like reading IEC 61850 configuration, startup,
for example
WATCHDOG This signal will be activated when the terminal has been under
too heavy load for at least 5 minutes. The operating systems
background task is used for the measurements.
LMDERROR LON network interface, MIP/DPS, is in an unrecoverable error
state.
APPERROR This signal will be active if one or more of the application threads
are not in the state that Runtime Engine expects. The states can
be CREATED, INITIALIZED, RUNNING, for example
SETCHGD This signal will generate an Internal Event to the Internal Event
list if any settings are changed.
SETGRPCHGD This signal will generate an Internal Event to the Internal Event
list if any setting groups are changed.
FTFERROR This signal will be active if both the working file and the backup
file are corrupted and can not be recovered.

4.2.2.2 Run-time model

The analog signals to the A/D converter is internally distributed into two different
converters, one with low amplification and one with high amplification, see Figure
25.

ADx
Adx_Low
x1

u1

x2

Adx
Adx_High Controller
x1

u1

x2

en05000296-2-en.vsd
IEC05000296 V2 EN

Figure 25: Simplified drawing of A/D converter for the IED.

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The technique to split the analog input signal into two A/D converters with
different amplification makes it possible to supervise the incoming signals under
normal conditions where the signals from the two converters should be identical.
An alarm is given if the signals are out of the boundaries. Another benefit is that it
improves the dynamic performance of the A/D conversion.

The self-supervision of the A/D conversion is controlled by the ADx_Controller


function. One of the tasks for the controller is to perform a validation of the input
signals. This is done in a validation filter which has mainly two objects: First is the
validation part that checks that the A/D conversion seems to work as expected.
Secondly, the filter chooses which of the two signals that shall be sent to the CPU,
that is the signal that has the most suitable level, the ADx_LO or the 16 times
higherADx_HI.

When the signal is within measurable limits on both channels, a direct comparison
of the two channels can be performed. If the validation fails, the CPU will be
informed and an alarm will be given.

The ADx_Controller also supervise other parts of the A/D converter.

4.2.3 Function block

IEC09000787 V1 EN

Figure 26: INTERRSIG function block

4.2.4 Output signals


Table 18: INTERRSIG Output signals
Name Type Description
FAIL BOOLEAN Internal fail
WARNING BOOLEAN Internal warning
CPUFAIL BOOLEAN CPU fail
CPUWARN BOOLEAN CPU warning

4.2.5 Setting parameters


The function does not have any parameters available in the local HMI or PCM600.

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4.2.6 Technical data


Table 19: Self supervision with internal event list
Data Value
Recording manner Continuous, event controlled
List size 1000 events, first in-first out

4.3 Time synchronization

4.3.1 Introduction
The time synchronization source selector is used to select a common source of
absolute time for the IED when it is a part of a protection system. This makes it
possible to compare event- and disturbance data between all IEDs in a station
automation system possible.

Micro SCADA OPC server should not be used as a time


synchronization source.

4.3.2 Principle of operation

4.3.2.1 General concepts

Time definitions
The error of a clock is the difference between the actual time of the clock, and the
time the clock is intended to have. The rate accuracy of a clock is normally called
the clock accuracy and means how much the error increases, that is how much the
clock gains or loses time. A disciplined (trained) clock knows its own faults and
tries to compensate for them.

Design of the time system (clock synchronization)


The time system is based on a software clock, which can be adjusted from external
time sources and a hardware clock. The protection and control modules will be
timed from a hardware clock, which runs independently from the software clock.
See figure 27.

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External
Synchronization
sources Time tagging and general synchronisation

Off
Comm- Protection
LON Events
Time- unication and control
SPA Regulator functions
Min. pulse
(Setting,
GPS see
SW-time
technical
SNTP
reference
DNP manual) Connected when GPS-time is
IRIG-B used for differential protection

PPS

Synchronization for differential protection


(ECHO-mode or GPS)
Off Time-
GPS Regulator HW-time
(fast or slow)
IRIG-B
PPS Diff.-
A/D Trans-
converter comm- ducers*
unication

*IEC 61850-9-2

IEC08000287-2-en.vsd
IEC08000287 V2 EN

Figure 27: Design of time system (clock synchronization)

All time tagging is performed by the software clock. When for example a status
signal is changed in the protection system with the function based on free running
hardware clock, the event is time tagged by the software clock when it reaches the
event recorder. Thus the hardware clock can run independently.

The echo mode for the differential protection is based on the hardware clock. Thus,
there is no need to synchronize the hardware clock and the software clock.

The synchronization of the hardware clock and the software clock is necessary only
when GPS or IRIG B 00X with optical fibre, IEEE 1344 is used for differential
protection. The two clock systems are synchronized by a special clock
synchronization unit with two modes, fast and slow. A special feature, an
automatic fast clock time regulator is used. The automatic fast mode makes the
synchronization time as short as possible during start-up or at interruptions/
disturbances in the GPS timing. The setting fast or slow is also available on the
local HMI.

If a GPS clock is used for other 670 series IEDs than line differential RED670, the
hardware and software clocks are not synchronized

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Fast clock synchronization mode


At startup and after interruptions in the GPS or IRIG B time signal, the clock
deviation between the GPS time and the internal differential time system can be
substantial. A new startup is also required after for example maintenance of the
auxiliary voltage system.

When the time difference is >16us, the differential function is blocked and the time
regulator for the hardware clock is automatically using a fast mode to synchronize
the clock systems. The time adjustment is made with an exponential function, i.e.
big time adjustment steps in the beginning, then smaller steps until a time deviation
between the GPS time and the differential time system of >16us has been reached.
Then the differential function is enabled and the synchronization remains in fast
mode or switches to slow mode, depending on the setting.

Slow clock synchronization mode


During normal service, a setting with slow synchronization mode is normally used,
which prevents the hardware clock to make too big time steps, >16µs, emanating
from the differential protection requirement of correct timing.

Synchronization principle
From a general point of view synchronization can be seen as a hierarchical
structure. A function is synchronized from a higher level and provides
synchronization to lower levels.

Synchronization from
a higher level

Function

Optional synchronization of
modules at a lower level

IEC09000342-1-en.vsd
IEC09000342 V1 EN

Figure 28: Synchronization principle

A function is said to be synchronized when it periodically receives synchronization


messages from a higher level. As the level decreases, the accuracy of the
synchronization decreases as well. A function can have several potential sources of
synchronization, with different maximum errors, which give the function the
possibility to choose the source with the best quality, and to adjust its internal clock
after this source. The maximum error of a clock can be defined as:

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• The maximum error of the last used synchronization message


• The time since the last used synchronization message
• The rate accuracy of the internal clock in the function.

4.3.2.2 Real-time clock (RTC) operation

The IED has a built-in real-time clock (RTC) with a resolution of one second. The
clock has a built-in calendar that handles leap years through 2038.

Real-time clock at power off


During power off, the system time in the IED is kept by a capacitor-backed real-
time clock that will provide 35 ppm accuracy for 5 days. This means that if the
power is off, the time in the IED may drift with 3 seconds per day, during 5 days,
and after this time the time will be lost completely.

Real-time clock at startup

Time synchronization startup procedure


The first message that contains the full time (as for instance LON, SNTP and GPS)
gives an accurate time to the IED. After the initial setting of the clock, one of three
things happens with each of the coming synchronization messages configured as
“fine”:

• If the synchronization message, which is similar to the other messages, has an


offset compared to the internal time in the IED, the message is used directly
for synchronization, that is, for adjusting the internal clock to obtain zero
offset at the next coming time message.
• If the synchronization message has an offset that is large compared to the other
messages, a spike-filter in the IED removes this time-message.
• If the synchronization message has an offset that is large, and the following
message also has a large offset, the spike filter does not act and the offset in
the synchronization message is compared to a threshold that defaults to 100
milliseconds. If the offset is more than the threshold, the IED is brought into a
safe state and the clock is set to the correct time. If the offset is lower than the
threshold, the clock is adjusted with 1000 ppm until the offset is removed.
With an adjustment of 1000 ppm, it takes 100 seconds or 1.7 minutes to
remove an offset of 100 milliseconds.

Synchronization messages configured as coarse are only used for initial setting of
the time. After this has been done, the messages are checked against the internal
time and only an offset of more than 10 seconds resets the time.

Rate accuracy
In the IED, the rate accuracy at cold start is 100 ppm but if the IED is synchronized
for a while, the rate accuracy is approximately 1 ppm if the surrounding
temperature is constant. Normally, it takes 20 minutes to reach full accuracy.

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Time-out on synchronization sources


All synchronization interfaces has a time-out and a configured interface must
receive time-messages regularly in order not to give an error signal (TSYNCERR).
Normally, the time-out is set so that one message can be lost without getting a
TSYNCERR, but if more than one message is lost, a TSYNCERR is given.

4.3.2.3 Synchronization alternatives

Three main alternatives of external time synchronization are available. Either the
synchronization message is applied via any of the communication ports of the IED
as a telegram message including date and time or as a minute pulse, connected to a
binary input, or via GPS. The minute pulse is used to fine tune already existing
time in the IEDs.

Synchronization via SNTP


SNTP provides a ping-pong method of synchronization. A message is sent from an
IED to an SNTP server, and the SNTP server returns the message after filling in a
reception time and a transmission time. SNTP operates via the normal Ethernet
network that connects IEDs together in an IEC 61850 network. For SNTP to
operate properly, there must be an SNTP-server present, preferably in the same
station. The SNTP synchronization provides an accuracy that gives 1 ms accuracy
for binary inputs. The IED itself can be set as an SNTP-time server.

SNTP server requirements


The SNTP server to be used is connected to the local network, that is not more than
4-5 switches or routers away from the IED. The SNTP server is dedicated for its
task, or at least equipped with a real-time operating system, that is not a PC with
SNTP server software. The SNTP server should be stable, that is, either
synchronized from a stable source like GPS, or local without synchronization.
Using a local SNTP server without synchronization as primary or secondary server
in a redundant configuration is not recommended.

Synchronization via Serial Communication Module (SLM)


On the serial buses (both LON and SPA) two types of synchronization messages
are sent.

• Coarse message is sent every minute and comprises complete date and time,
that is, year, month, day, hours, minutes, seconds and milliseconds.
• Fine message is sent every second and comprises only seconds and milliseconds.

IEC60870-5-103 is not used to synchronize the IED, but instead the offset between
the local time in the IED and the time received from 103 is added to all times (in
events and so on) sent via 103. In this way the IED acts as it is synchronized from
various 103 sessions at the same time. Actually, there is a “local” time for each 103
session.

The SLM module is located on the AD conversion Module (ADM).

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Synchronization via binary input


The IED accepts minute pulses to a binary input. These minute pulses can be
generated from, for example station master clock. If the station master clock is not
synchronized from a world wide source, time will be a relative time valid for the
substation. Both positive and negative edge on the signal can be accepted. This
signal is also considered as a fine time synchronization signal.

The minute pulse is connected to any channel on any Binary Input Module in the
IED. The electrical characteristic is thereby the same as for any other binary input.

If the objective of synchronization is to achieve a relative time within the


substation and if no station master clock with minute pulse output is available, a
simple minute pulse generator can be designed and used for synchronization of the
IEDs. The minute pulse generator can be created using the logical elements and
timers available in the IED.

The definition of a minute pulse is that it occurs one minute after the last pulse. As
only the flanks are detected, the flank of the minute pulse shall occur one minute
after the last flank.

Binary minute pulses are checked with reference to frequency.

Pulse data:

• Period time (a) should be 60 seconds.


• Pulse length (b):
• Minimum pulse length should be >50 ms.
• Maximum pulse length is optional.
• Amplitude (c) - please refer to section "Binary input module (BIM)".

Deviations in the period time larger than 50 ms will cause TSYNCERR.

en05000251.vsd
IEC05000251 V1 EN

Figure 29: Binary minute pulses

The default time-out-time for a minute pulse is two minutes, and if no valid minute
pulse is received within two minutes a SYNCERR will be given.

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If contact bounces occurs, only the first pulse will be detected as a minute pulse.
The next minute pulse will be registered first 60 s - 50 ms after the last contact bounce.

If the minute pulses are perfect, for example, it is exactly 60 seconds between the
pulses, contact bounces might occur 49 ms after the actual minute pulse without
effecting the system. If contact bounces occurs more than 50 ms, for example, it is
less than 59950 ms between the two most adjacent positive (or negative) flanks, the
minute pulse will not be accepted.

Binary synchronization example


An IED is configured to use only binary input, and a valid binary input is applied
to a binary input card. The HMI is used to tell the IED the approximate time and
the minute pulse is used to synchronize the IED thereafter. The definition of a
minute pulse is that it occurs one minute after the previous minute pulse, so the
first minute pulse is not used at all. The second minute pulse will probably be
rejected due to the spike filter. The third pulse will give the IED a good time and
will reset the time so that the fourth minute pulse will occur on a minute border.
After the first three minutes, the time in the IED will be good if the coarse time is
set properly via the HMI or the RTC backup still keeps the time since last up-time.
If the minute pulse is removed for instance for an hour, the internal time will drift
by maximum the error rate in the internal clock. If the minute pulse is returned, the
first pulse automatically is rejected. The second pulse will possibly be rejected due
to the spike filter. The third pulse will either synchronize the time, if the time offset
is more than 100 ms, or adjust the time, if the time offset is small enough. If the
time is set, the application will be brought to a safe state before the time is set. If
the time is adjusted, the time will reach its destination within 1.7 minutes.

Synchronization via IRIG-B


IRIG-B is a protocol used only for time synchronization. A clock can provide local
time of the year in this format. The “B” in IRIG-B states that 100 bits per second
are transmitted, and the message is sent every second. After IRIG-B there numbers
stating if and how the signal is modulated and the information transmitted.

To receive IRIG-B there are two connectors in the IRIG-B module, one galvanic
BNC connector and one optical ST connector. IRIG-B 12x messages can be
supplied via the galvanic interface, and IRIG-B 00x messages can be supplied via
either the galvanic interface or the optical interface, where x (in 00x or 12x) means
a number in the range of 1-7.

“00” means that a base band is used, and the information can be fed into the IRIG-
B module via the BNC contact or an optical fiber. “12” means that a 1 kHz
modulation is used. In this case the information must go into the module via the
BNC connector.

If the x in 00x or 12x is 4, 5, 6 or 7, the time message from IRIG-B contains


information of the year. If x is 0, 1, 2 or 3, the information contains only the time
within the year, and year information has to come from PCM600 or local HMI.

The IRIG-B module also takes care of IEEE1344 messages that are sent by IRIG-B
clocks, as IRIG-B previously did not have any year information. IEEE1344 is

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compatible with IRIG-B and contains year information and information of the time-
zone.

It is recommended to use IEEE 1344 for supplying time information to the IRIG-B
module. In this case, send also the local time in the messages, as this local time
plus the TZ Offset supplied in the message equals UTC at all times.

4.3.3 Function block


TIMEERR
TSYNCERR
RTCERR

IEC05000425-2-en.vsd
IEC05000425 V2 EN

Figure 30: TIMEERR function block

4.3.4 Output signals


Table 20: TIMEERR Output signals
Name Type Description
TSYNCERR BOOLEAN Time synchronization error
RTCERR BOOLEAN Real time clock error

4.3.5 Setting parameters


Path in the local HMI is located under Main menu/Setting/Time

Path in PCM600 is located under Main menu/Settings/Time/Synchronization

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Table 21: TIMESYNCHGEN Non group settings (basic)


Name Values (Range) Unit Step Default Description
CoarseSyncSrc Off - - Off Coarse time synchronization source
SPA
LON
SNTP
DNP
FineSyncSource Off - - Off Fine time synchronization source
SPA
LON
BIN
GPS
GPS+SPA
GPS+LON
GPS+BIN
SNTP
GPS+SNTP
IRIG-B
GPS+IRIG-B
PPS
SyncMaster Off - - Off Activate IED as synchronization master
SNTP-Server
TimeAdjustRate Slow - - Fast Adjust rate for time synchronization
Fast
HWSyncSrc Off - - Off Hardware time synchronization source
GPS
IRIG-B
PPS
AppSynch NoSynch - - NoSynch Time synchronization mode for
Synch application
SyncAccLevel Class T5 (1us) - - Unspecified Wanted time synchronization accuracy
Class T4 (4us)
Unspecified

Table 22: SYNCHBIN Non group settings (basic)


Name Values (Range) Unit Step Default Description
ModulePosition 3 - 16 - 1 3 Hardware position of IO module for time
synchronization
BinaryInput 1 - 16 - 1 1 Binary input number for time
synchronization
BinDetection PositiveEdge - - PositiveEdge Positive or negative edge detection
NegativeEdge

Table 23: SYNCHSNTP Non group settings (basic)


Name Values (Range) Unit Step Default Description
ServerIP-Add 0 - 18 IP 1 0.0.0.0 Server IP-address
Address
RedServIP-Add 0 - 18 IP 1 0.0.0.0 Redundant server IP-address
Address

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Table 24: DSTBEGIN Non group settings (basic)


Name Values (Range) Unit Step Default Description
MonthInYear January - - March Month in year when daylight time starts
February
March
April
May
June
July
August
September
October
November
December
DayInWeek Sunday - - Sunday Day in week when daylight time starts
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
WeekInMonth Last - - Last Week in month when daylight time starts
First
Second
Third
Fourth
UTCTimeOfDay 0 - 172800 s 1 3600 UTC Time of day in seconds when
daylight time starts

Table 25: DSTEND Non group settings (basic)


Name Values (Range) Unit Step Default Description
MonthInYear January - - October Month in year when daylight time ends
February
March
April
May
June
July
August
September
October
November
December
DayInWeek Sunday - - Sunday Day in week when daylight time ends
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
WeekInMonth Last - - Last Week in month when daylight time ends
First
Second
Third
Fourth
UTCTimeOfDay 0 - 172800 s 1 3600 UTC Time of day in seconds when
daylight time ends

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Table 26: TIMEZONE Non group settings (basic)


Name Values (Range) Unit Step Default Description
NoHalfHourUTC -24 - 24 - 1 0 Number of half-hours from UTC

Table 27: SYNCHIRIG-B Non group settings (basic)


Name Values (Range) Unit Step Default Description
SynchType BNC - - Opto Type of synchronization
Opto
TimeDomain LocalTime - - LocalTime Time domain
UTC
Encoding IRIG-B - - IRIG-B Type of encoding
1344
1344TZ
TimeZoneAs1344 MinusTZ - - PlusTZ Time zone as in 1344 standard
PlusTZ

4.3.6 Technical data


Table 28: Time synchronization, time tagging
Function Value
Time tagging resolution, events and sampled measurement values 1 ms
Time tagging error with synchronization once/min (minute pulse ± 1.0 ms typically
synchronization), events and sampled measurement values
Time tagging error with SNTP synchronization, sampled ± 1.0 ms typically
measurement values

4.4 Parameter setting groups

4.4.1 Introduction
Use the six sets of settings to optimize the IED operation for different system
conditions. Creating and switching between fine-tuned setting sets, either from the
local HMI or configurable binary inputs, results in a highly adaptable IED that can
cope with a variety of system scenarios.

4.4.2 Principle of operation


Parameter setting groups ActiveGroup function has six functional inputs, each
corresponding to one of the setting groups stored in the IED. Activation of any of
these inputs changes the active setting group. Seven functional output signals are
available for configuration purposes, so that up to date information on the active
setting group is always available.

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A setting group is selected by using the local HMI, from a front connected personal
computer, remotely from the station control or station monitoring system or by
activating the corresponding input to the ActiveGroup function block.

Each input of the function block can be configured to connect to any of the binary
inputs in the IED. To do this PCM600 must be used.

The external control signals are used for activating a suitable setting group when
adaptive functionality is necessary. Input signals that should activate setting groups
must be either permanent or a pulse exceeding 400 ms.

More than one input may be activated at the same time. In such cases the lower
order setting group has priority. This means that if for example both group four and
group two are set to activate, group two will be the one activated.

Every time the active group is changed, the output signal SETCHGD is sending a
pulse.

The parameter MAXSETGR defines the maximum number of setting groups in use
to switch between.

ACTIVATE GROUP 6
ACTIVATE GROUP 5
ACTIVATE GROUP 4
ACTIVATE GROUP 3
ACTIVATE GROUP 2
+RL2 ACTIVATE GROUP 1

IOx-Bly1 ActiveGroup
Æ ACTGRP1 GRP1
IOx-Bly2
Æ ACTGRP2 GRP2
IOx-Bly3
Æ ACTGRP3 GRP3
IOx-Bly4
Æ ACTGRP4 GRP4
IOx-Bly5
Æ ACTGRP5 GRP5
IOx-Bly6 ACTGRP6
Æ GRP6
SETCHGD

en05000119.vsd
IEC05000119 V2 EN

Figure 31: Connection of the function to external circuits

The above example also includes seven output signals, for confirmation of which
group that is active.

SETGRPS function block has an input where the number of setting groups used is
defined. Switching can only be done within that number of groups. The number of
setting groups selected to be used will be filtered so only the setting groups used
will be shown on the Parameter Setting Tool.

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4.4.3 Function block


ActiveGroup
ACTGRP1 GRP1
ACTGRP2 GRP2
ACTGRP3 GRP3
ACTGRP4 GRP4
ACTGRP5 GRP5
ACTGRP6 GRP6
SETCHGD

IEC05000433_2_en.vsd
IEC05000433 V2 EN

Figure 32: ActiveGroup function block

SETGRPS
MAXSETGR

IEC05000716_2_en.vsd
IEC05000716 V2 EN

Figure 33: SETGRPS function block

4.4.4 Input and output signals


Table 29: ActiveGroup Input signals
Name Type Default Description
ACTGRP1 BOOLEAN 0 Selects setting group 1 as active
ACTGRP2 BOOLEAN 0 Selects setting group 2 as active
ACTGRP3 BOOLEAN 0 Selects setting group 3 as active
ACTGRP4 BOOLEAN 0 Selects setting group 4 as active
ACTGRP5 BOOLEAN 0 Selects setting group 5 as active
ACTGRP6 BOOLEAN 0 Selects setting group 6 as active

Table 30: ActiveGroup Output signals


Name Type Description
GRP1 BOOLEAN Setting group 1 is active
GRP2 BOOLEAN Setting group 2 is active
GRP3 BOOLEAN Setting group 3 is active
GRP4 BOOLEAN Setting group 4 is active
GRP5 BOOLEAN Setting group 5 is active
GRP6 BOOLEAN Setting group 6 is active
SETCHGD BOOLEAN Pulse when setting changed

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4.4.5 Setting parameters


Table 31: ActiveGroup Non group settings (basic)
Name Values (Range) Unit Step Default Description
t 0.0 - 10.0 s 0.1 1.0 Pulse length of pulse when setting
changed

Table 32: SETGRPS Non group settings (basic)


Name Values (Range) Unit Step Default Description
ActiveSetGrp SettingGroup1 - - SettingGroup1 ActiveSettingGroup
SettingGroup2
SettingGroup3
SettingGroup4
SettingGroup5
SettingGroup6
MAXSETGR 1-6 No 1 1 Max number of setting groups 1-6

4.5 ChangeLock function CHNGLCK

4.5.1 Introduction
Change lock function (CHNGLCK) is used to block further changes to the IED
configuration and settings once the commissioning is complete. The purpose is to
block inadvertent IED configuration changes beyond a certain point in time.

4.5.2 Principle of operation


The Change lock function (CHNGLCK) is configured using ACT.

The function, when activated, will still allow the following changes of the IED
state that does not involve reconfiguring of the IED:
• Monitoring
• Reading events
• Resetting events
• Reading disturbance data
• Clear disturbances
• Reset LEDs
• Reset counters and other runtime component states
• Control operations
• Set system time
• Enter and exit from test mode
• Change of active setting group

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The binary input signal LOCK controlling the function is defined in ACT or SMT:
Binary input Function
1 Activated
0 Deactivated

4.5.3 Function block


CHNGLCK
LOCK

IEC09000946-1-en.vsd
IEC09000946 V1 EN

Figure 34: CHNGLCK function block

4.5.4 Input and output signals


Table 33: CHNGLCK Input signals
Name Type Default Description
LOCK BOOLEAN 0 Parameter change lock

4.5.5 Setting parameters


Table 34: CHNGLCK Non group settings (basic)
Name Values (Range) Unit Step Default Description
Operation LockHMI and Com - - LockHMI and Com Operation mode of change lock
LockHMI,
EnableCom
EnableHMI,
LockCom

4.6 Test mode functionality TEST

4.6.1 Introduction
When the Test mode functionality TESTMODE function is activated, protection
functions in the IED are automatically blocked. It is then possible to unblock the
protection functions individually from the local HMI or the Parameter Setting tool
to perform required tests.

When leaving TESTMODE, all blockings are removed and the IED resumes
normal operation. However, if during TESTMODE operation, power is removed
and later restored, the IED will remain in TESTMODE with the same protection

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functions blocked or unblocked as before the power was removed. All testing will
be done with actually set and configured values within the IED. No settings will be
changed, thus mistakes are avoided.

4.6.2 Principle of operation


Put the IED into test mode to test functions in the IED. Set the IED in test mode by

• configuration, activating the input signal of the function block TESTMODE.


• setting TestMode to On in the local HMI, under Main menu/TEST/IED test
mode.

While the IED is in test mode, the ACTIVE output of the function block
TESTMODE is activated. The other outputs of the function block TESTMODE
shows the generator of the “Test mode: On” state — input from configuration
(OUTPUT output is activated) or setting from local HMI (SETTING output is
activated).

While the IED is in test mode, the yellow START LED will flash and all functions
are blocked. Any function can be unblocked individually regarding functionality
and event signalling.

Most of the functions in the IED can individually be blocked by means of settings
from the local HMI. To enable these blockings the IED must be set in test mode
(output ACTIVE is activated), see example in figure 35. When leaving the test
mode, that is entering normal mode, these blockings are disabled and everything is
set to normal operation. All testing will be done with actually set and configured
values within the IED. No settings will be changed, thus no mistakes are possible.

The blocked functions will still be blocked next time entering the test mode, if the
blockings were not reset.

The blocking of a function concerns all output signals from the actual function, so
no outputs will be activated.

When a binary input is used to set the IED in test mode and a
parameter, that requires restart of the application, is changed, the
IED will re-enter test mode and all functions will be blocked, also
functions that were unblocked before the change. During the re-
entering to test mode, all functions will be temporarily unblocked
for a short time, which might lead to unwanted operations. This is
only valid if the IED is put in TEST mode by a binary input, not by
local HMI.

The TESTMODE function block might be used to automatically block functions


when a test handle is inserted in a test switch. A contact in the test switch (RTXP24
contact 29-30) can supply a binary input which in turn is configured to the
TESTMODE function block.

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Each of the protection functions includes the blocking from the TESTMODE
function block. A typical example from the undervoltage function is shown in
figure 35.

The functions can also be blocked from sending events over IEC 61850 station bus
to prevent filling station and SCADA databases with test events, for example
during a maintenance test.

U Disconnection

Normal voltage

U1<

U2<

tBlkUV1 <
t1,t1Min
IntBlkStVal1
tBlkUV2 <
t2,t2Min
IntBlkStVal2

Time

Block step 1

Block step 2
en05000466.vsd
IEC05000466 V1 EN

Figure 35: Example of blocking the time delayed undervoltage protection


function.

4.6.3 Function block


TESTMODE
INPUT ACTIVE
OUTPUT
SETTING
NOEVENT

IEC09000219-1.vsd
IEC09000219 V1 EN

Figure 36: TESTMODE function block

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4.6.4 Input and output signals


Table 35: TESTMODE Input signals
Name Type Default Description
INPUT BOOLEAN 0 Sets terminal in test mode when active

Table 36: TESTMODE Output signals


Name Type Description
ACTIVE BOOLEAN Terminal in test mode when active
OUTPUT BOOLEAN Test input is active
SETTING BOOLEAN Test mode setting is (On) or not (Off)
NOEVENT BOOLEAN Event disabled during testmode

4.6.5 Setting parameters


Table 37: TESTMODE Non group settings (basic)
Name Values (Range) Unit Step Default Description
TestMode Off - - Off Test mode in operation (On) or not (Off)
On
EventDisable Off - - Off Event disable during testmode
On
CmdTestBit Off - - Off Command bit for test required or not
On during testmode

4.7 IED identifiers

4.7.1 Introduction
IED identifiers (TERMINALID) function allows the user to identify the individual
IED in the system, not only in the substation, but in a whole region or a country.

Use only characters A-Z, a-z and 0-9 in station, object and unit names.

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4.7.2 Setting parameters


Table 38: TERMINALID Non group settings (basic)
Name Values (Range) Unit Step Default Description
StationName 0 - 18 - 1 Station name Station name
StationNumber 0 - 99999 - 1 0 Station number
ObjectName 0 - 18 - 1 Object name Object name
ObjectNumber 0 - 99999 - 1 0 Object number
UnitName 0 - 18 - 1 Unit name Unit name
UnitNumber 0 - 99999 - 1 0 Unit number

4.8 Product information

4.8.1 Introduction
The Product identifiers function identifies the IED. The function has seven pre-set,
settings that are unchangeable but nevertheless very important:

• IEDProdType
• ProductDef
• FirmwareVer
• SerialNo
• OrderingNo
• ProductionDate

The settings are visible on the local HMI , under Main menu/Diagnostics/IED
status/Product identifiers

They are very helpful in case of support process (such as repair or maintenance).

4.8.2 Setting parameters


The function does not have any parameters available in the local HMI or PCM600.

4.8.3 Factory defined settings


The factory defined settings are very useful for identifying a specific version and
very helpful in the case of maintenance, repair, interchanging IEDs between
different Substation Automation Systems and upgrading. The factory made settings
can not be changed by the customer. They can only be viewed. The settings are
found in the local HMI under Main menu/Diagnostics/IED status/Product
identifiers

The following identifiers are available:

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• IEDProdType
• Describes the type of the IED (like REL, REC or RET). Example: REL670
• ProductDef
• Describes the release number, from the production. Example: 1.2.2.0
• FirmwareVer
• Describes the firmware version. Example: 1.4.51
• Firmware versions numbers are “running” independently from the
release production numbers. For every release numbers (like 1.5.0.17)
there can be one or more firmware versions, depending on the small
issues corrected in between releases.
• IEDMainFunType
• Main function type code according to IEC 60870-5-103. Example: 128
(meaning line protection).
• SerialNo
• OrderingNo
• ProductionDate

4.9 Signal matrix for binary inputs SMBI

4.9.1 Introduction
The Signal matrix for binary inputs (SMBI) function is used within the Application
Configuration Tool (ACT) in direct relation with the Signal Matrix Tool (SMT),
see the application manual to get information about how binary inputs are brought
in for one IED configuration.

4.9.2 Principle of operation


The Signal matrix for binary inputs (SMBI) function , see figure 37, receives its
inputs from the real (hardware) binary inputs via the Signal Matrix Tool (SMT),
and makes them available to the rest of the configuration via its outputs, BI1 to
BI10. The inputs and outputs, as well as the whole block, can be given a user
defined name. These names will be represented in SMT as information which
signals shall be connected between physical IO and SMBI function. The input/
output user defined name will also appear on the respective output/input signal.

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4.9.3 Function block


SMBI
^VIN1 ^BI1
^VIN2 ^BI2
^VIN3 ^BI3
^VIN4 ^BI4
^VIN5 ^BI5
^VIN6 ^BI6
^VIN7 ^BI7
^VIN8 ^BI8
^VIN9 ^BI9
^VIN10 ^BI10

IEC05000434-2-en.vsd
IEC05000434 V2 EN

Figure 37: SMBI function block

4.9.4 Input and output signals


Table 39: SMBI Input signals
Name Type Default Description
VIn1 BOOLEAN 0 SMT Connect input
VIn2 BOOLEAN 0 SMT Connect input
VIn3 BOOLEAN 0 SMT Connect input
VIn4 BOOLEAN 0 SMT Connect input
VIn5 BOOLEAN 0 SMT Connect input
VIn6 BOOLEAN 0 SMT Connect input
VIn7 BOOLEAN 0 SMT Connect input
VIn8 BOOLEAN 0 SMT Connect input
VIn9 BOOLEAN 0 SMT Connect input
VIn10 BOOLEAN 0 SMT Connect input

Table 40: SMBI Output signals


Name Type Description
BI1 BOOLEAN Binary input 1
BI2 BOOLEAN Binary input 2
BI3 BOOLEAN Binary input 3
BI4 BOOLEAN Binary input 4
BI5 BOOLEAN Binary input 5
BI6 BOOLEAN Binary input 6
BI7 BOOLEAN Binary input 7
BI8 BOOLEAN Binary input 8
BI9 BOOLEAN Binary input 9
BI10 BOOLEAN Binary input 10

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4.10 Signal matrix for binary outputs SMBO

4.10.1 Introduction
The Signal matrix for binary outputs (SMBO) function is used within the
Application Configuration Tool (ACT) in direct relation with the Signal Matrix
Tool (SMT), see the application manual to get information about how binary inputs
are sent from one IED configuration.

4.10.2 Principle of operation


The Signal matrix for binary outputs (SMBO) function , see figure 38, receives
logical signal from the IED configuration, which is transferring to the real
(hardware) outputs, via the Signal Matrix Tool (SMT). The inputs in SMBO are
BO1 to BO10 and they, as well as the whole function block, can be tag-named. The
name tags will appear in SMT as information which signals shall be connected
between physical IO and the SMBO.

It is important that SMBO inputs are connected when SMBOs


are connected to physical outputs through the Signal Matrix
Tool. If SMBOs are connected (in SMT) but their inputs not, all
the physical outputs will be set by default. This might cause
malfunction of primary equipment and/or injury to personnel.

4.10.3 Function block


SMBO
BO1 ^BO1
BO2 ^BO2
BO3 ^BO3
BO4 ^BO4
BO5 ^BO5
BO6 ^BO6
BO7 ^BO7
BO8 ^BO8
BO9 ^BO9
BO10 ^BO10

IEC05000439-2-en.vsd
IEC05000439 V2 EN

Figure 38: SMBO function block

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4.10.4 Input and output signals


Table 41: SMBO Input signals
Name Type Default Description
BO1 BOOLEAN 1 Signal name for BO1 in Signal Matrix Tool
BO2 BOOLEAN 1 Signal name for BO2 in Signal Matrix Tool
BO3 BOOLEAN 1 Signal name for BO3 in Signal Matrix Tool
BO4 BOOLEAN 1 Signal name for BO4 in Signal Matrix Tool
BO5 BOOLEAN 1 Signal name for BO5 in Signal Matrix Tool
BO6 BOOLEAN 1 Signal name for BO6 in Signal Matrix Tool
BO7 BOOLEAN 1 Signal name for BO7 in Signal Matrix Tool
BO8 BOOLEAN 1 Signal name for BO8 in Signal Matrix Tool
BO9 BOOLEAN 1 Signal name for BO9 in Signal Matrix Tool
BO10 BOOLEAN 1 Signal name for BO10 in Signal Matrix Tool

4.11 Signal matrix for mA inputs SMMI

4.11.1 Introduction
The Signal matrix for mA inputs (SMMI) function is used within the Application
Configuration Tool (ACT) in direct relation with the Signal Matrix Tool (SMT),
see the application manual to get information about how milliamp (mA) inputs are
brought in for one IED configuration.

4.11.2 Principle of operation


The Signal matrix for mA inputs (SMMI) function, see figure 39, receives its
inputs from the real (hardware) mA inputs via the Signal Matrix Tool (SMT), and
makes them available to the rest of the configuration via its analog outputs, named
AI1 to AI6. The inputs, as well as the whole block, can be tag-named. These tags
will be represented in SMT.

The outputs on SMMI are normally connected to the IEC61850 generic


communication I/O functions (MVGGIO) function for further use of the mA signals.

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4.11.3 Function block


SMMI
^VIN1 AI1
^VIN2 AI2
^VIN3 AI3
^VIN4 AI4
^VIN5 AI5
^VIN6 AI6

IEC05000440-2-en.vsd
IEC05000440 V2 EN

Figure 39: SMMI function block

4.11.4 Input and output signals


Table 42: SMMI Input signals
Name Type Default Description
VIn1 REAL 0 SMT connected milliampere input
VIn2 REAL 0 SMT connected milliampere input
VIn3 REAL 0 SMT connected milliampere input
VIn4 REAL 0 SMT connected milliampere input
VIn5 REAL 0 SMT connected milliampere input
VIn6 REAL 0 SMT connected milliampere input

Table 43: SMMI Output signals


Name Type Description
AI1 REAL Analog milliampere input 1
AI2 REAL Analog milliampere input 2
AI3 REAL Analog milliampere input 3
AI4 REAL Analog milliampere input 4
AI5 REAL Analog milliampere input 5
AI6 REAL Analog milliampere input 6

4.12 Signal matrix for analog inputs SMAI

4.12.1 Introduction
Signal matrix for analog inputs function SMAI (or the pre-processing function) is
used within PCM600 in direct relation with the Signal Matrix tool or the
Application Configuration tool. Signal Matrix tool represents the way analog
inputs are brought in for one IED configuration.

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4.12.2 Principle of operation


Every Signal matrix for analog inputs function (SMAI) can receive four analog
signals (three phases and one neutral value), either voltage or current, see figure 41
and figure 42. SMAI outputs give information about every aspect of the 3ph analog
signals acquired (phase angle, RMS value, frequency and frequency derivates etc. –
244 values in total). The BLOCK input will reset all outputs to 0.

The output signal AI1 to AI4 are direct output of the, in SMT, connected input to
GRPxL1, GRPxL2, GRPxL3 and GRPxN, x=1-12. AIN is always the neutral
current, calculated residual sum or the signal connected to GRPxN. Note that
function block will always calculate the residual sum of current/voltage if the input
is not connected in SMT. Applications with a few exceptions shall always be
connected to AI3P.

4.12.3 Frequency values


The frequency functions includes a functionality based on level of positive
sequence voltage, IntBlockLevel, to validate if the frequency measurement is valid
or not. If positive sequence voltage is lower than IntBlockLevel the function is
blocked. IntBlockLevel, is set in % of UBase/√3

If SMAI setting ConnectionType is Ph-Ph at least two of the inputs GRPxL1,


GRPxL2 and GRPxL3 must be connected in order to calculate positive sequence
voltage. If SMAI setting ConnectionType is Ph-N, all three inputs GRPxL1,
GRPxL2 and GRPxL3 must be connected in order to calculate positive sequence
voltage.

If only one phase-phase voltage is available and SMAI setting ConnectionType is


Ph-Ph the user is advised to connect two (not three) of the inputs GRPxL1,
GRPxL2 and GRPxL3 to the same voltage input as shown in figure 40 to make
SMAI calculating a positive sequence voltage (that is input voltage/√3).

IEC10000060-1-en.vsd
IEC10000060 V1 EN

Figure 40: Connection example

The above described scenario does not work if SMAI setting


ConnectionType is Ph-N. If only one phase-earth voltage is
available, the same type of connection can be used but the SMAI
ConnectionType setting must still be Ph-Ph and this has to be
accounted for when setting IntBlockLevel. If SMAI setting

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ConnectionType is Ph-N and the same voltage is connected to all


three SMAI inputs, the positive sequence voltage will be zero and
the frequency functions will not work properly.

The outputs from the above configured SMAI block shall only be
used for Overfrequency protection (SAPTOF), Underfrequency
protection (SAPTUF) and Rate-of-change frequency protection
(SAPFRC) due to that all other information except frequency and
positive sequence voltage might be wrongly calculated.

The same phase-phase voltage connection principle shall be used for frequency
tracking master SMAI block in pump-storage power plant applications when
swapping of positive and negative sequence voltages happens during generator/
motor mode of operation.

4.12.4 Function block


SMAI1
BLOCK SPFCOUT
DFTSPFC AI3P
^GRP1L1 AI1
^GRP1L2 AI2
^GRP1L3 AI3
^GRP1N AI4
TYPE AIN

IEC05000705-2-en.vsd
IEC05000705 V2 EN

Figure 41: SMAI1 function block

SMAI2
BLOCK AI3P
^GRP2L1 AI1
^GRP2L2 AI2
^GRP2L3 AI3
^GRP2N AI4
TYPE AIN

IEC07000130-2-en.vsd
IEC07000130 V2 EN

Figure 42: SMAI2 function block

4.12.5 Input and output signals


Table 44: SMAI1 Input signals
Name Type Default Description
BLOCK BOOLEAN 0 Block group 1
DFTSPFC REAL 20.0 Number of samples per fundamental cycle used
for DFT calculation
GRP1L1 STRING - Sample input to be used for group 1 phase L1
calculations
Table continues on next page

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Name Type Default Description


GRP1L2 STRING - Sample input to be used for group 1 phase L2
calculations
GRP1L3 STRING - Sample input to be used for group 1 phase L3
calculations
GRP1N STRING - Sample input to be used for group 1 residual
calculations

Table 45: SMAI1 Output signals


Name Type Description
SPFCOUT REAL Number of samples per fundamental cycle from
internal DFT reference function
AI3P GROUP SIGNAL Group 1 analog input 3-phase group
AI1 GROUP SIGNAL Group 1 analog input 1
AI2 GROUP SIGNAL Group 1 analog input 2
AI3 GROUP SIGNAL Group 1 analog input 3
AI4 GROUP SIGNAL Group 1 analog input 4
AIN GROUP SIGNAL Group 1 analog input residual for disturbance
recorder

Table 46: SMAI2 Input signals


Name Type Default Description
BLOCK BOOLEAN 0 Block group 2
GRP2L1 STRING - Sample input to be used for group 2 phase L1
calculations
GRP2L2 STRING - Sample input to be used for group 2 phase L2
calculations
GRP2L3 STRING - Sample input to be used for group 2 phase L3
calculations
GRP2N STRING - Sample input to be used for group 2 residual
calculations

Table 47: SMAI2 Output signals


Name Type Description
AI3P GROUP SIGNAL Group 2 analog input 3-phase group
AI1 GROUP SIGNAL Group 2 analog input 1
AI2 GROUP SIGNAL Group 2 analog input 2
AI3 GROUP SIGNAL Group 2 analog input 3
AI4 GROUP SIGNAL Group 2 analog input 4
AIN GROUP SIGNAL Group 2 analog input residual for disturbance
recorder

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4.12.6 Setting parameters

Settings DFTRefExtOut and DFTReference shall be set to default


value InternalDFTRef if no VT inputs are available. Internal
nominal frequency DFT reference is then the reference.

Table 48: SMAI1 Non group settings (basic)


Name Values (Range) Unit Step Default Description
DFTRefExtOut InternalDFTRef - - InternalDFTRef DFT reference for external output
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
DFTReference InternalDFTRef - - InternalDFTRef DFT reference
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
ConnectionType Ph-N - - Ph-N Input connection type
Ph-Ph
TYPE 1-2 Ch 1 1 1=Voltage, 2=Current

Table 49: SMAI1 Non group settings (advanced)


Name Values (Range) Unit Step Default Description
Negation Off - - Off Negation
NegateN
Negate3Ph
Negate3Ph+N
MinValFreqMeas 5 - 200 % 1 10 Limit for frequency calculation in % of
UBase
UBase 0.05 - 2000.00 kV 0.05 400.00 Base voltage

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Table 50: SMAI2 Non group settings (basic)


Name Values (Range) Unit Step Default Description
DFTReference InternalDFTRef - - InternalDFTRef DFT reference
AdDFTRefCh1
AdDFTRefCh2
AdDFTRefCh3
AdDFTRefCh4
AdDFTRefCh5
AdDFTRefCh6
AdDFTRefCh7
AdDFTRefCh8
AdDFTRefCh9
AdDFTRefCh10
AdDFTRefCh11
AdDFTRefCh12
External DFT ref
ConnectionType Ph-N - - Ph-N Input connection type
Ph-Ph
TYPE 1-2 Ch 1 1 1=Voltage, 2=Current

Table 51: SMAI2 Non group settings (advanced)


Name Values (Range) Unit Step Default Description
Negation Off - - Off Negation
NegateN
Negate3Ph
Negate3Ph+N
MinValFreqMeas 5 - 200 % 1 10 Limit for frequency calculation in % of
UBase
UBase 0.05 - 2000.00 kV 0.05 400.00 Base voltage

4.13 Summation block 3 phase 3PHSUM

4.13.1 Introduction
Summation block 3 phase function 3PHSUM is used to get the sum of two sets of
three-phase analog signals (of the same type) for those IED functions that might
need it.

4.13.2 Principle of operation


Summation block 3 phase 3PHSUM receives the three-phase signals from Signal
matrix for analog inputs function (SMAI). In the same way, the BLOCK input will
reset all the outputs of the function to 0.

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4.13.3 Function block


3PHSUM
BLOCK AI3P
DFTSPFC AI1
G1AI3P* AI2
G2AI3P* AI3
AI4

IEC05000441-2-en.vsd
IEC05000441 V2 EN

Figure 43: 3PHSUM function block

4.13.4 Input and output signals


Table 52: 3PHSUM Input signals
Name Type Default Description
BLOCK BOOLEAN 0 Block
DFTSPFC REAL 0 Number of samples per fundamental cycle used
for DFT calculation
G1AI3P GROUP - Group 1 analog input 3-phase group
SIGNAL
G2AI3P GROUP - Group 2 analog input 3-phase group
SIGNAL

Table 53: 3PHSUM Output signals


Name Type Description
AI3P GROUP SIGNAL Group analog input 3-phase group
AI1 GROUP SIGNAL Group 1 analog input
AI2 GROUP SIGNAL Group 2 analog input
AI3 GROUP SIGNAL Group 3 analog input
AI4 GROUP SIGNAL Group 4 analog input

4.13.5 Setting parameters

Settings DFTRefExtOut and DFTReference shall be set to default


value InternalDFTRef if no VT inputs are available.

Table 54: 3PHSUM Non group settings (basic)


Name Values (Range) Unit Step Default Description
SummationType Group1+Group2 - - Group1+Group2 Summation type
Group1-Group2
Group2-Group1
-(Group1+Group2)
DFTReference InternalDFTRef - - InternalDFTRef DFT reference
AdDFTRefCh1
External DFT ref

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Table 55: 3PHSUM Non group settings (advanced)


Name Values (Range) Unit Step Default Description
FreqMeasMinVal 5 - 200 % 1 10 Amplitude limit for frequency calculation
in % of Ubase
UBase 0.05 - 2000.00 kV 0.05 400.00 Base voltage

4.14 Authority status ATHSTAT

4.14.1 Introduction
Authority status (ATHSTAT) function is an indication function block for user log-
on activity.

4.14.2 Principle of operation


Authority status (ATHSTAT) function informs about two events related to the IED
and the user authorization:
• the fact that at least one user has tried to log on wrongly into the IED and it
was blocked (the output USRBLKED)
• the fact that at least one user is logged on (the output LOGGEDON)

Whenever one of the two events occurs, the corresponding output (USRBLKED or
LOGGEDON) is activated. The output can for example, be connected on Event
(EVENT) function block for LON/SPA.The signals are also available on IEC
61850 station bus.

4.14.3 Function block


ATHSTAT
USRBLKED
LOGGEDON

IEC06000503-2-en.vsd
IEC06000503 V2 EN

Figure 44: ATHSTAT function block

4.14.4 Output signals


Table 56: ATHSTAT Output signals
Name Type Description
USRBLKED BOOLEAN At least one user is blocked by invalid password
LOGGEDON BOOLEAN At least one user is logged on

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4.14.5 Setting parameters


The function does not have any parameters available in the local HMI or PCM600.

4.15 Denial of service DOS

4.15.1 Introduction
The Denial of service functions (DOSFRNT, DOSOEMAB and DOSOEMCD) are
designed to limit overload on the IED produced by heavy Ethernet network traffic.
The communication facilities must not be allowed to compromise the primary
functionality of the device. All inbound network traffic will be quota controlled so
that too heavy network loads can be controlled. Heavy network load might for
instance be the result of malfunctioning equipment connected to the network.

4.15.2 Principle of operation


The Denial of service functions (DOSFRNT, DOSOEMAB and DOSOEMCD)
measures the IED load from communication and, if necessary, limit it for not
jeopardizing the IEDs control and protection functionality due to high CPU load.
The function has the following outputs:
• LINKUP indicates the Ethernet link status
• WARNING indicates that communication (frame rate) is higher than normal
• ALARM indicates that the IED limits communication

4.15.3 Function blocks


DOSFRNT
LINKUP
WARNING
ALARM

IEC09000749-1-en.vsd
IEC09000749 V1 EN

Figure 45: DOSFRNT function block

DOSOEMAB
LINKUP
WARNING
ALARM
IEC09000750-1-en.vsd
IEC09000750 V1 EN

Figure 46: DOSOEMAB function block

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DOSOEMCD
LINKUP
WARNING
ALARM

IEC09000751-1-en.vsd
IEC09000751 V1 EN

Figure 47: DOSOEMCD function block

4.15.4 Signals
Table 57: DOSFRNT Output signals
Name Type Description
LINKUP BOOLEAN Ethernet link status
WARNING BOOLEAN Frame rate is higher than normal state
ALARM BOOLEAN Frame rate is higher than throttle state

Table 58: DOSOEMAB Output signals


Name Type Description
LINKUP BOOLEAN Ethernet link status
WARNING BOOLEAN Frame rate is higher than normal state
ALARM BOOLEAN Frame rate is higher than throttle state

Table 59: DOSOEMCD Output signals


Name Type Description
LINKUP BOOLEAN Ethernet link status
WARNING BOOLEAN Frame rate is higher than normal state
ALARM BOOLEAN Frame rate is higher than throttle state

4.15.5 Settings
The function does not have any parameters available in the local HMI or PCM600.

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1MRK 502 027-UEN A Section 5
Differential protection

Section 5 Differential protection

About this chapter


This chapter describes the measuring principles, functions and parameters used in
differential protection.

5.1 Generator differential protection GENPDIF

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Generator differential protection GENPDIF 87G
Id>
SYMBOL-NN V1 EN

5.1.1 Introduction
Short circuit between the phases of the stator windings causes normally very large
fault currents. The short circuit gives risk of damages on insulation, windings and
stator iron core. The large short circuit currents cause large forces, which can cause
damage even to other components in the power plant, such as turbine and generator-
turbine shaft.

To limit the damage due to stator winding short circuits, the fault clearance must be
as fast as possible (instantaneous). If the generator block is connected to the power
system close to other generating blocks, the fast fault clearance is essential to
maintain the transient stability of the non-faulted generators.

Normally, the short circuit fault current is very large, that is, significantly larger
than the generator rated current. There is a risk that a short circuit can occur
between phases close to the neutral point of the generator, thus causing a relatively
small fault current. The fault current can also be limited due to low excitation of
the generator. Therefore, it is desired that the detection of generator phase-to-phase
short circuits shall be relatively sensitive, detecting small fault currents.

It is also of great importance that the generator differential protection does not trip
for external faults, with large fault currents flowing from the generator.

To combine fast fault clearance, as well as sensitivity and selectivity, the generator
differential protection is normally the best choice for phase-to-phase generator
short circuits.

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Generator differential protection GENPDIF is also well suited to generate fast,


sensitive and selective fault clearance, if used to protect shunt reactors or small
busbars.

5.1.2 Principle of operation


The task of Generator differential protection GENPDIF is to determine whether a
fault is within the protected zone, or outside the protected zone. The protected zone
is delimited by the position of current transformers, as shown in figure 48.

IEC06000430-2-en.vsd

IEC06000430 V2 EN

Figure 48: Position of current transformers; the recommended (default)


orientation

If the fault is internal, the faulty generator must be quickly tripped, that is,
disconnected from the network, the field breaker tripped and the power to the
prime mover interrupted.

GENPDIF function always uses reference (default) directions of CTs towards the
protected generator as shown in figure 48. Thus, it always measures the currents on
the two sides of the generator with the same reference direction towards the
generator windings. With the orientation of CTs as in figure 48, the difference of
currents flowing in, and out, of a separate stator winding phase is simply obtained
by summation of the two currents fed to the differential protection function.

Numerical IEDs have brought a large number of advantages and new functionality
to the protective relaying. One of the benefits is the simplicity and accuracy of
calculating symmetrical components from individual phase quantities. Within the
firmware of a numerical IED, it is no more difficult to calculate negative-sequence
components than it is to calculate zero-sequence components. Diversity of
operation principles integrated in the same protection function enhances the overall
performance without a significant increase in cost.

A novelty in GENPDIF, namely the negative-sequence-current-based internal-


external fault discriminator, is used with advantage in order to determine whether a
fault is internal or external. Indeed, the internal-external fault discriminator not
only positively discriminates between internal and external faults, but can
independently detect minor faults which may not be felt (until they develop into
more serious faults) by the "usual" differential protection based on operate-restrain
characteristic.

GENPDIF is using fundamental frequency phase current phasors and negative


sequence current phasors. These quantities are derived outside the differential
protection function block, in the general pre-processing blocks. GENPDIF is also
using with advantage the DC component of the instantaneous differential current

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Differential protection

and the 2nd and 5th harmonic components of the instantaneous differential currents.
The instantaneous differential currents are calculated from the input samples of the
instantaneous values of the currents measured at both ends of the stator winding.
The DC and the 2nd and 5th harmonic components of each separate instantaneous
differential current are extracted inside the differential protection.

5.1.2.1 Function calculation principles

To make a differential protection as sensitive and stable as possible, the restrained


differential characteristic is used. The protection must be provided with a
proportional bias, which makes the protection operate for a certain percentage
differential current related to the current through the generator stator winding. This
stabilizes the protection under through fault conditions while still permitting the
system to have good basic sensitivity. The following chapters explain how these
quantities are calculated.

The fundamental frequency phasors of the phase currents from both sides of the
generator (the neutral side and the terminal side) are delivered to the differential
protection function by the pre-processing module of the IED.

5.1.2.2 Fundamental frequency differential currents

The fundamental frequency RMS differential current is a vectorial sum (that is,
sum of fundamental frequency phasors) of the individual phase currents from the
two sides of the protected generator. The magnitude of the fundamental frequency
RMS differential current, in phase L1, is as calculated in equation 1:

Idiff _ L1 = [(Re( IL1n + IL1t ))2 + (Im( IL1n + IL1t )) 2 ]


EQUATION2316 V2 EN (Equation 1)

One common fundamental frequency bias current is used. The bias current is the
magnitude of the highest measured current in the protected circuit. The bias current
is not allowed to drop instantaneously, instead, it decays exponentially with a
predefined time constant. These principles make the differential IED more secure,
with less risk to operate for external faults. The “maximum” principle brings as
well more meaning to the breakpoint settings of the operate-restrain characteristic.

Ibias = max( IL1n, IL 2 n, IL3n, IL1t , IL 2t , IL 3t )


EQUATION1666 V1 EN (Equation 2)

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Differential protection

IL1n IL1t

IL1t Idiff

IL1n
IEC07000018_3_en.vsd
IEC07000018 V3 EN

Figure 49: Internal fault

IL1n IL1t

External fault: IL1n = - IL1t

IL1t IL1n

Idiff = 0 en07000019-2.vsd
IEC07000019 V2 EN

Figure 50: External fault

Generator differential protection GENPDIF function uses two mutually


independent characteristics to which magnitudes of the three fundamental
frequency RMS differential currents are compared at each execution of the
differential protection function. These two characteristics divide, each of them
independently, the operate current – restrain current plane into two regions: the
operate (trip) region and the restrain (block) region, as shown in figure 52. Two
kinds of protection are obtained:

• the non-stabilized (instantaneous unrestrained) differential protection


• the stabilized differential protection

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The non-stabilized (instantaneous) differential protection is used for very high


differential currents, where it must be beyond any doubt, that the fault is internal.
This limit, (defined by the setting UnrestrainedLimit), is a constant, not
proportional the bias (restrain) current. No harmonic or any other restrain is applied
to this limit, which is, therefore, called the unrestrained limit. The reset ratio of the
unrestrained characteristic is equal to 0.95.

The stabilized differential protection applies a differential (operate) current, and the
common bias (restrain) current, on the operate-restrain characteristic, as shown in
figure 52. Here, the actual limit, where the protection can operate, is dependent on
the bias (restrain) current. The operate value, is stabilized by the bias current. This
operate – restrain characteristic is represented by a double-slope, double-breakpoint
characteristic. The restrained characteristic is determined by the following 5 settings:

• IdMin (Sensitivity in section 1, set as multiple of generator rated current)


• EndSection1 (End of section 1, set as multiple of generator rated current)
• EndSection2 (End of section 2, set as multiple of generator rated current)
• SlopeSection2 (Slope in section 2 of the characteristic, set in percent)
• SlopeSection3 (Slope in section 3 of the characteristic, set in percent)

slope = D Ioperate × 100%


D Irestrain
EQUATION1246 V1 EN (Equation 3)

Note that both slopes are calculated from the characteristics break
points.

The operate-restrain characteristic is tailor-made, in other words, it can be


constructed by the user. A default operate-restrain characteristic is suggested which
gives acceptably good results in a majority of applications. The operate-restrain
characteristic has in principle three sections with a section-wise proportionality of
the operate value to the common restrain (bias) current. The reset ratio is in all
parts of the characteristic equal to 0.95.

Section 1 is the most sensitive part on the characteristic. In section 1, normal


currents flow through the protected circuit and its current transformers, and risk for
higher false differential currents is low. With generators the only cause of small
false differential currents in this section can be tolerances of the current
transformers used on both sides of the protected generator. Slope in section 1 is
always zero percent. Normally, with the protected machine at rated load, the
restrain, bias current will be around 1 p.u., that is, equal to the machine rated current.

In section 2, a certain minor slope is introduced which is supposed to cope with


false differential currents proportional to higher than normal currents through the
current transformers.

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The more pronounced slope in section 3 is designed to result in a higher tolerance


to substantial current transformer saturation at high through-fault currents, which
can be expected in this section.

Note that both slopes are calculated from the characteristics break
points.

Temporarily decreased sensitivity of differential protection is activated if the


binary input DESENSIT is (temporarily) set to 1 (TRUE). In this case, a new,
separate limit is superposed the otherwise unchanged operate-bias characteristic.
This limit is called TempIdMin and is a setting. The value of the setting TempIdMin
must be given as a multiple of the setting IdMin. In this case no trip command can
be issued if all fundamental frequency differential currents are below the value of
the setting TempIdMin.

AddTripDelay: If the input DESENSIT is activated also the operation time of the
protection function can be increased by using the setting AddTripDelay.

operate current
[ times IBase ]
Operate
5
unconditionally

UnrestrainedLimit
4

Operate
3
conditionally

2
Section 1 Section 2 Section 3

SlopeSection3
1
TempIdMin
IdMin
SlopeSection2 Restrain
0
0 1 2 3 4 5

EndSection1 restrain current


EndSection2 [ times IBase ]

en06000637.vsd
IEC06000637 V2 EN

Figure 52: Operate-restrain characteristic

GENPDIF can also be temporarily ‘desensitized’ if the Boolean setting


OperDCBiasing is set to 1 (TRUE). In this case, the DC component is extracted on-
line from the instantaneous differential currents. The highest DC component is

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taken as a kind of bias in the sense that the highest sensitivity of the differential
protection is inversely proportional to the ratio of this DC component to the
maximum fundamental frequency differential current. Similar to the
‘desensitization’ described above, a separate (temporary) additional limit is
activated. The value of this limit is limited to either the generator rated current, or 3
times IdMin, whichever is smaller. This temporary extra limit decays exponentially
from its maximum value with a time constant equal to T = 1 second. This feature
must be used when unmatched CTs are used on the generator or shut reactor,
especially where a long DC time constant can be expected. The new limit is
superposed the otherwise unchanged operate-bias characteristic, and temporarily
determines the highest sensitivity of the differential protection. This temporary
sensitivity must be lower than the sensitivity in section 1 of the operate-bias
characteristic.

This DC desensitization is not active, if a disturbance has been


detected and characterized as internal fault.

5.1.2.3 Supplementary criteria

To relieve the burden of constructing an exact optimal operate-restrain


characteristic, two special features supplement the basic stabilized differential
protection function, making Generator differential protection GENPDIF a very
reliable one.

The supplementary criteria are:

• Internal/external fault discriminator (enhances, or blocks, the trip command)


• Harmonic restrain (blocks only)

The internal/external fault discriminator is a very reliable supplementary criterion.


It discriminates with a high speed between internal and external faults. The
discriminator is the main part of what is here called the negative-sequence-current-
based differential protections. It is recommended that this feature is always used
(that is, enabled, OpNegSeqDiff = On).

If a fault is classified as internal, then any eventual block signals by the harmonic
criterion are ignored, and the differential protection can operate very quickly
without any further delay.

If a fault (disturbance) is classified as external, then generally, but not


unconditionally, a trip command is prevented. If a fault is classified as external,
harmonic analysis of the fault conditions is initiated.

If all the differential currents which caused their respective start signals to be set,
are free of harmonic pollution, that is, if no harmonic block signal has been set,
then a (minor) internal fault, simultaneous with a predominant external fault, can
be suspected. This conclusion can be drawn because at external faults, major false

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Differential protection

differential currents can only exist when one or more current transformers saturate
transiently. In this case, the false instantaneous differential currents are highly
polluted by higher harmonic components, the 2nd, and the 5th.

The existence of relatively high negative-sequence currents is in itself an indication


of a disturbance, as the negative-sequence currents are superimposed, pure-fault
quantities. The negative-sequence currents are measurable indications of abnormal
conditions. The negative sequence currents are particularly suitable for directional
tests. The negative sequence internal or external fault discriminator works
satisfactorily even in case of three-phase faults. Because of the fundamental
frequency components (50/60 Hz) of the decaying DC offset of the fault currents,
the system is not fully symmetrical immediately after the fault. Due to the transient
existence of the negative sequence system, faults can be distinguished as internal or
external, even for three-phase faults.

The internal or external fault discriminator responds to the relative phase angles of
the negative sequence fault currents at both ends of the stator winding. Observe
that the source of the negative sequence currents at unsymmetrical faults is at the
fault point.

• If the two negative sequence currents, as seen by the differential relay, flow in
the same direction (that is with the CTs oriented as in figure 48), the fault is
internal. If the two negative sequence currents flow in opposite directions, the
fault is external.
• Under external fault condition, the relative angle is theoretically equal to 180°.
Under internal fault condition, the angle is ideally 0°, but due to possible
different negative-sequence impedance angles on both sides of the internal
fault, it may differ somewhat from 0°.

The setting NegSeqROA, as shown in figure 53, represents the so called Relay
Operate Angle, which determines the boundary between the internal and external
fault regions. It can be selected in the range ±30° to ±90°, with a step of 1°. The
default value is ±60°. The default setting, ±60°, favors somewhat security in
comparison to dependability.

Magnitudes of both negative-sequence currents which are to be compared as to


their phase positions in the complex plane must be high enough so that one can be
sure that they are due to a fault. The limit value IMinNegSeq is settable in the range
[0.02 – 0.20] of the protected generator rated current. Adaptability is introduced if
the bias current is higher than 150 % rated current. Adaptability is introduced 10
ms after this limit of 150 % rated current has been crossed so that the internal/
external discriminator is given the time to detect correctly a fault before an
eventual CT saturation sets in. The threshold IMinNegSeq is dynamically increased
by 4 % of the bias current, in case of internal faults, and by 8 % of the bias current
in case of external faults. Only if magnitudes of both currents are above the limit
IMinNegSeq, the angle between the two currents is calculated. If any of the two
currents is too small, no decision is taken regarding the relative position of the
fault, and this feature then remains inactive rather than to produce a wrong
decision. The relative angle is then assigned the value of 120° (2.094 radians). If

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Technical reference manual
1MRK 502 027-UEN A Section 5
Differential protection

this value persists, then this is an indication that no directional comparison has
been made. Neither internal, nor external fault (disturbance) is declared in this case.

90 deg
120 deg

NegSeqROA
Angle could not be (Relay Operate Angle)
measured. One or both
currents too small

Internal fault
region

180 deg 0 deg

IminNegSeq
External fault
region

Internal /
external fault
boundary.
Default ± 60 deg
The characteristic is defined by the
settings:
IMinNegSeq and NegSeqROA

270 deg
en06000433-2.vsd
IEC06000433 V2 EN

Figure 53: NegSeqROA determines the boundary between the internal and
external fault regions

Unrestrained negative sequence differential protection


If one or more start signals have been set by the restrained differential protection
algorithm, because one or more of the fundamental frequency differential currents
entered the “operate” region of the restrained differential protection, then the internal/
external fault discriminator can enhance the final, common, trip command by the
differential protection. If a fault is classified as internal, then any eventual block
signals by the harmonic criterion are ignored, and the differential protection
operates immediately without any further delay. This makes the overall generator
differential protection very fast. Operation of this protection is signaled on the
output of GENPDIF as TRNSUNRE.

Sensitive negative sequence differential protection


The difference from the unrestrained negative sequence differential protection,
described above, is that the sensitive one does not require any start signal to be set.
It is enough that both of the negative sequence currents, contributions to the total
negative sequence differential current, which should be compared, are above the
setting IMinNegSeq. Thus, this protection can be made very sensitive. Further, an
intentional delay of one cycle is added in order not to inadvertently operate for
some eventual transients. Further, the sensitive negative sequence differential
protection is automatically disabled when the bias current exceeds 1.5 times the

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Technical reference manual
Section 5 1MRK 502 027-UEN A
Differential protection

rated current of the protected generator. Operation of this protection is signaled on


the output of the function as TRNSENS.

5.1.2.4 Harmonic restrain

Harmonic restrain is the classical restrain method traditionally used with power
transformer differential protections. The goal there was to prevent an unwanted trip
command due to magnetizing inrush currents at switching operations, due to
magnetizing currents at over-voltages, or external faults. Harmonic restrain is just
as useful with Generator differential protection GENPDIF. The harmonic analysis
is only executed in those phases, where start signals have been set.

There is no magnetizing inrush to a generator, but there may be some in case of


shunt reactors. The false initial differential currents of a shunt reactor have an
appreciable amount of higher harmonic currents.

At external faults dangerous false differential currents can arise for different
reasons, mainly due to saturation of one or more current transformers. The false
differential currents display in this case a considerable amount of higher
harmonics, which can, therefore, be used to prevent an unwanted trip of a healthy
generator or shunt reactor.

If a fault is recognized as external by the internal/external fault discriminator, but


nevertheless one or more start signals have been set, the harmonic analysis is
initiated in the phases with start signal, as previously described. If all of the
instantaneous differential currents, where trip signals have been set, are free of
higher harmonics (that is the cross-block principle is imposed temporarily), a
(minor) internal fault is assumed to have happened simultaneously with a
predominant external one. A trip command is then allowed.

5.1.2.5 Cross-block logic scheme

The cross-block logic says that in order to issue a common trip command, the
harmonic contents in all phases with a start signal set (start = TRUE) must be
below the limit defined with the setting HarmDistLimit. In the opposite case, no
trip command will be issued.

The cross-block logic is active if the setting OpCrossBlock = Yes. By always using
the cross-block logic, the false trips can be prevented for external faults in cases
where the internal or external fault discriminator should for some reason fail to
declare an external fault. For internal faults, the higher frequency components of an
instantaneous differential current are most often relatively low, compared to the
fundamental frequency component. While for an external (heavy) fault, they can be
relatively high. For external faults with moderate fault currents, there can be little
or no current transformer saturation and only small false differential currents.

The principle design of the Generator differential protection GENPDIF is shown in


figure 54.

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1MRK 502 027-UEN A Section 5
Differential protection

TRIP
Signals
Start
Phasors IL1N, IL2N,IL3N Magnitude phase
Calculation Idiff and Ibias Diff.prot. selective
Idiff and Ibias characteristic
Phasors IL1T, IL2T,IL3T
START
Signals

BLOCK
Signals

Samples IL1N, IL2N,IL3N Harm.


Calculation Samples Idiff Hamonic Block Start and INTFAULT
instantaneous analysis: DC, trip logic EXTFAULT
Samples IAT, IBT,ICT Idiff 2nd and 5th OPENCT
OPENCTAL

The sensitive protection is deactivated


above bias current > 150 % rated
current.

Internal/ Intern/ Analog


Phasor IL1N (neg.seq.) External Fault extern Outputs
Calculation
Discriminator Fault
negative
sequence and Sensitive
Phasor IL1T (neg.seq.) Idiff differential
protection

en06000434-2.vsd
IEC06000434 V3 EN

Figure 54: Simplified principle design of the Generator differential protection GENPDIF

Simplified logic diagrams of the function are shown in figures 55, 56, 57 and 58.

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Section 5 1MRK 502 027-UEN A
Differential protection

BLKUNRES

IdUnre a TRIPUNREL1
b>a AND
b
IDL1MAG

IBIAS STL1
AND
BLOCK
BLKRES

INTFAULT TRIPRESL1
AND
OR 1

IDL1 2nd and BLKHL1


5th
Harmonic

Cross Block
Cross Block to L2 or L3
from L2 or L3 AND
AND
OpCrossBlock=On

en07000020.vsd
IEC07000020 V2 EN

Figure 55: Generator differential logic diagram 1

Internal/ EXTFAULT
Neg.Seq. Diff External INTFAULT
Current Fault
Contributions discrimin
ator TRNSSENS

AND
OpNegSeqDiff=On

IBIAS
a
b>a
b
Constant
BLKNSSEN
BLKNSUNR
BLOCK
TRNSUNR
STL1 AND
STL2
OR
STL3

en07000021.vsd
IEC07000021 V2 EN

Figure 56: Generator differential logic diagram 2

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1MRK 502 027-UEN A Section 5
Differential protection

STL1
STL2 START
OR
STL3

BLKHL1
BLKHL2 BLKH
OR
BLKHL3

en07000022.vsd
IEC07000022 V1 EN

Figure 57: Generator differential logic diagram 3

TRIPRESL1
TRIPRESL2 TRIPRES
OR
TRIPRESL3

TRIPUNREL1
TRIPUNREL2 TRIPUNRE
OR
TRIPUNREL3

TRIP
TRNSSENS OR
TRNSUNR

en07000023.vsd
IEC07000023 V1 EN

Figure 58: Generator differential logic diagram 4

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Section 5 1MRK 502 027-UEN A
Differential protection

5.1.3 Function block


GENPDIF
I3PNCT1* TRIP
I3PNCT2* TRIPRES
I3PTCT1* TRIPUNRE
I3PTCT2* TRNSUNR
BLOCK TRNSSENS
BLKRES START
BLKUNRES STL1
BLKNSUNR STL2
BLKNSSEN STL3
DESENSIT BLKH
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDNSMAG
IBIAS

IEC11000212-1-en.vsd
IEC11000212 V1 EN

Figure 59: GENPDIF function block

5.1.4 Input and output signals


Table 60: GENPDIF Input signals
Name Type Default Description
I3PNCT1 GROUP - Neutral side input1
SIGNAL
I3PNCT2 GROUP - Neutral side input2
SIGNAL
I3PTCT1 GROUP - Terminal side input1
SIGNAL
I3PTCT2 GROUP - Terminal side input2
SIGNAL
BLOCK BOOLEAN 0 Block of function
BLKRES BOOLEAN 0 Block of trip command by the restrained diff.
protection
BLKUNRES BOOLEAN 0 Block of trip by unrestrained "instantaneous" diff.
prot.
BLKNSUNR BOOLEAN 0 Block of trip for unrestr. neg. seq. differential
feature
BLKNSSEN BOOLEAN 0 Block of trip for sensitive neg. seq. differential
feature
DESENSIT BOOLEAN 0 Raise pick up: function temporarily desensitized

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1MRK 502 027-UEN A Section 5
Differential protection

Table 61: GENPDIF Output signals


Name Type Description
TRIP BOOLEAN General, common trip signal
TRIPRES BOOLEAN Trip signal from restrained differential protection
TRIPUNRE BOOLEAN Trip signal from unrestrained differential protection
TRNSUNR BOOLEAN Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS BOOLEAN Trip signal from sensitive neg. seq. diff. protection
START BOOLEAN Common start signal from any phase
STL1 BOOLEAN Start signal from phase L1
STL2 BOOLEAN Start signal from phase L2
STL3 BOOLEAN Start signal from phase L3
BLKH BOOLEAN Common harmonic block signal
OPENCT BOOLEAN An open CT was detected
OPENCTAL BOOLEAN Open CT Alarm output signal. Issued after a
delay ...
IDL1 REAL Instantaneous differential current L1; in primary
Amperes
IDL2 REAL Instantaneous differential current L2; in primary
Amperes
IDL3 REAL Instantaneous differential current L3; in primary
Amperes
IDNSMAG REAL Negative Sequence Differential current; in
primary Amperes
IBIAS REAL Magnitude of the common Bias current; in
primary Amperes

5.1.5 Setting parameters


Table 62: GENPDIF Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation Off / On
On
IdMin 0.05 - 1.00 IB 0.01 0.25 Section 1 sensitivity, multiple of
generator rated current
IdUnre 1.00 - 50.00 IB 0.01 10.00 Unrestr. prot. limit, multiple of generator
rated current
OpNegSeqDiff No - - Yes Negative Sequence Differential Enable
Yes Off/On
IMinNegSeq 0.02 - 0.20 IB 0.01 0.04 Neg. sequence curr. limit, as multiple of
gen. rated curr.

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Section 5 1MRK 502 027-UEN A
Differential protection

Table 63: GENPDIF Group settings (advanced)


Name Values (Range) Unit Step Default Description
EndSection1 0.20 - 1.50 IB 0.01 1.25 End of section 1, multiple of generator
rated current
EndSection2 1.00 - 10.00 IB 0.01 3.00 End of section 2, multiple of generator
rated current
SlopeSection2 10.0 - 50.0 % 0.1 40.0 Slope in section 2 of operate-restrain
characteristic, in %
SlopeSection3 30.0 - 100.0 % 0.1 80.0 Slope in section 3 of operate-restrain
characteristic, in %
OpCrossBlock No - - Yes Operation On / Off for cross-block logic
Yes between phases
NegSeqROA 30.0 - 120.0 Deg 0.1 60.0 Operate Angle of int/ext neg. seq. fault
discriminator, deg
HarmDistLimit 5.0 - 100.0 % 0.1 10.0 (Total) relative harmonic distorsion limit,
percent
TempIdMin 1.0 - 5.0 IdMin 0.1 2.0 Temp. Id pickup when input
raisePickUp=1, multiple of IdMin
AddTripDelay 0.000 - 60.000 s 0.001 0.100 Additional trip delay, when input
raisePickUp=1
OperDCBiasing Off - - Off Operation DC biasing On / Off
On
OpenCTEnable Off - - Off Open CT detection feature Off/On
On
tOCTAlarmDelay 0.100 - 10.000 s 0.001 1.000 Open CT: time to alarm if an open CT is
detected, in sec
tOCTResetDelay 0.100 - 10.000 s 0.001 0.250 Reset delay in s. After delay, diff.
function is activated
tOCTUnrstDelay 0.100 - 100.000 s 0.001 10.000 Unrestrained diff. protection blocked
after this delay, in s

Table 64: GENPDIF Non group settings (basic)


Name Values (Range) Unit Step Default Description
IBase 100.0 - 100000.0 A 0.1 5000.0 Rated current of protected generator,
Amperes
InvertCT2Curr No - - No Invert CT 2 curr., yes (1) or no (0).
Yes Default is no (0).

5.1.6 Technical data


Table 65: GENPDIF technical data
Function Range or value Accuracy
Reset ratio > 95% -
Unrestrained differential current limit (1-50)p.u. of IBase ± 2.0% of set value
Base sensitivity function (0.05–1.00)p.u. of ± 2.0% of Ir
IBase
Table continues on next page

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1MRK 502 027-UEN A Section 5
Differential protection

Function Range or value Accuracy


Negative sequence current level (0.02–0.2)p.u. of IBase ± 1.0% of Ir

Operate time, restrained function 25 ms typically at 0 to -


2 x set level
Reset time, restrained function 20 ms typically at 2 to -
0 x set level
Operate time, unrestrained function 12 ms typically at 0 to -
5 x set level
Reset time, unrestrained function 25 ms typically at 5 to -
0 x set level
Operate time, negative sequence 15 ms typically at 0 to -
unrestrained function 5 x set level
Critical impulse time, unrestrained function 2 ms typically at 0 to 5 -
x set level

5.2 Transformer differential protection T2WPDIF and


T3WPDIF

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Transformer differential protection, two- T2WPDIF 87T
winding
3Id/I

SYMBOL-BB V1 EN

Transformer differential protection, T3WPDIF 87T


three-winding
3Id/I

SYMBOL-BB V1 EN

5.2.1 Introduction
The Transformer differential protection, two-winding (T2WPDIF) and Transformer
differential protection, three-winding (T3WPDIF) are provided with internal CT
ratio matching and vector group compensation and settable zero sequence current
elimination.

The function can be provided with up to three-phase sets of current inputs. All
current inputs are provided with percentage bias restraint features, making the IED
suitable for two- or three-winding transformer in multi-breaker station arrangements.

119
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Section 5 1MRK 502 027-UEN A
Differential protection

Two-winding applications
two-winding power
transformer
xx05000048.vsd
IEC05000048 V1 EN

two-winding power
transformer with
unconnected delta
xx05000049.vsd tertiary winding
IEC05000049 V1 EN

two-winding power
transformer with two
circuit breakers on
xx05000050.vsd one side
IEC05000050 V1 EN

two-winding power
transformer with two
circuit breakers and
two CT-sets on both
sides

xx05000051.vsd
IEC05000051 V1 EN

Three-winding applications
three-winding power
transformer with all
three windings
connected

xx05000052.vsd
IEC05000052 V1 EN

three-winding power
transformer with two
circuit breakers and
two CT-sets on one
side

xx05000053.vsd
IEC05000053 V1 EN

Autotransformer with
two circuit breakers
and two CT-sets on
two out of three sides

xx05000057.vsd
IEC05000057 V1 EN

Figure 60: CT group


arrangement for
differential protection
and other protections

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1MRK 502 027-UEN A Section 5
Differential protection

The setting facilities cover the applications of the differential protection to all types
of power transformers and auto-transformers with or without load tap changer as
well as for shunt reactors or and local feeders within the station. An adaptive
stabilizing feature is included for heavy through-faults.By introducing the load tap
changer position, the differential protection pick-up can be set to optimum
sensitivity thus covering internal faults with low fault level.

Stabilization is included for inrush currents as well as for overexcitation conditions.


Adaptive stabilization is also included for system recovery inrush and CT
saturation for external faults. A high set unrestrained differential current protection
is included for a very high speed tripping at a high internal fault currents.

An innovative sensitive differential protection feature, based on the theory of


symmetrical components, offers the best possible coverage for power transformer
winding turn-to-turn faults.

5.2.2 Principle of operation


The task of the power transformer differential protection is to determine whether a
fault is within the protected zone, or outside the protected zone. The protected zone
is delimited by the position of current transformers (see figure 61), and in principle
can include more objects than just transformer. If the fault is found to be internal,
the faulty power transformer must be quickly disconnected.

The main CTs are normally supposed to be star connected. The main CTs can be
earthed in anyway (that is, either "ToObject" or "FromObject"). However
internally the differential function will always use reference directions towards the
protected transformer as shown in figure 61. Thus the IED will always internally
measure the currents on all sides of the power transformer with the same reference
direction towards the power transformer windings as shown in figure 61.For more
information see the Application manual

IW1 IW2

Z1S1 Z1S2
E1S1 E1S2

IW1 IW2

IED

en05000186.vsd
IEC05000186 V1 EN

Figure 61: Typical CT location and definition of positive current direction

Even in a healthy power transformer, the currents are generally not equal when
they flow through the power transformer, due to the ratio of the number of turns of
the windings and the connection group of the protected transformer. Therefore the

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Section 5 1MRK 502 027-UEN A
Differential protection

differential protection must first correlate all currents to each other before any
calculation can be performed.

In numerical differential protections this correlation and comparison is performed


mathematically. First, compensation for the protected transformer transformation
ratio and connection group is made, and only then the currents are compared phase-
wise. This makes the external auxiliary (that is, interposing) current transformers
unnecessary. Conversion of all currents to the common reference side of the power
transformer is performed by pre-programmed coefficient matrices, which depends
on the protected power transformer transformation ratio and connection group.
Once the power transformer vector group, rated currents and voltages has been
entered by the user, the differential protection is capable to calculate off-line matrix
coefficients required in order to perform the on-line current comparison by means
of a fixed equation.

Numerical IEDs have brought a large number of well-known advantages and new
functionality to the protective relaying. One of the benefits is the simplicity and
accuracy of calculating symmetrical components from individual phase quantities.
Within the firmware of a numerical IED, it is no more difficult to calculate negative-
sequence components than it is to calculate zero-sequence components. Diversity
of operation principles integrated in the same protection function enhances the
overall performance without a significant increase in cost.

A novelty in power transformer differential protection, namely the negative-


sequence-current-based internal-external fault discriminator, is used with
advantage in order to determine whether a fault is internal or external. Indeed, the
internal-external fault discriminator not only positively discriminates between
internal and external faults, but can as well independently detect minor faults
which may not be felt by the "usual" differential protection based on operate-
restrain characteristic.

5.2.2.1 Function calculation principles

To make a differential IED as sensitive and stable as possible, restrained


differential characteristic have been developed and are now adopted as the general
practice in the protection of power transformers. The protection should be provided
with a proportional bias, which makes the protection operate for a certain
percentage differential current related to the current through the transformer. This
stabilizes the protection under through fault conditions while still permitting the
system to have good basic sensitivity. The following chapters explain how these
quantities are calculated.

Fundamental frequency differential currents


The fundamental frequency differential current is a vectorial sum (sum of
fundamental frequency phasors) of the individual phase currents from different side
of the protected power transformer.

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1MRK 502 027-UEN A Section 5
Differential protection

Before any differential current can be calculated, the power transformer phase
shift, and its transformation ratio, must be allowed for. Conversion of all currents
to a common reference is performed in two steps:

• all current phasors are phase-shifted to (referred to) the phase-reference side,
(whenever possible a first winding with star connection)
• all currents magnitudes are always referred to the first winding of the power
transformer (typically transformer high-voltage side)

The two steps of conversion are made simultaneously on-line by the pre-
programmed coefficient matrices, as shown in equation 5 for a two-winding power
transformer, and in equation 6 for a three-winding power transformer.

These are internal compensation within the differential function.


The protected power transformer data are always entered as they
are given on the nameplate. Differential function will by it self
correlate nameplate data and select proper reference windings.

é IDL1 ù é IL1_ W 1 ù é IL1_ W 2 ù


ê IDL 2 ú = A × ê IL 2 _ W 1ú + Un _ W 2 × B × ê IL 2 _ W 2 ú
ê ú ê ú Un _ W 1 ê ú
êë IDL3 úû êë IL3 _ W 1úû êë IL3 _ W 2 úû

1 2 3
EQUATION1880 V1 EN (Equation 5)

where:
1. is Differential Currents
2. is Differential current contribution from W1 side
3. is Differential current contribution from W2 side

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Section 5 1MRK 502 027-UEN A
Differential protection

é IDL1 ù é IL1_ W 1 ù é IL1_ W 2 ù é IL1_ W 3 ù


ê IDL 2 ú = A × ê IL 2 _ W 1ú + Un _ W 2 × B × ê IL 2 _ W 2 ú + Un _ W 3 × C × ê IL 2 _ W 3ú
ê ú ê ú Un _ W 1 ê ú Un _ W 1 ê ú
êë IDL3 úû êë IL3 _ W 1úû êë IL3 _ W 2 úû êë IL3 _ W 3 úû

1 2 3 4
EQUATION1556 V2 EN (Equation 6)

where:
1. is Differential Currents
2. is Differential current contribution from W1 side
3. is Differential current contribution from W2 side
4. is Differential current contribution from W3 side

and where, for equation 5 and equation 6:


IDL1 is the fundamental frequency differential current in phase L1 (in W1 side primary amperes)
IDL2 is the fundamental frequency differential current in phase L2 (in W1 side primary amperes)
IDL3 is the fundamental frequency differential current in phase L3C (in W1 side primary
amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on W1 side
IL2_W1 is the fundamental frequency phase current in phase L2 on W1 side
IL3_W1 is the fundamental frequency phase current in phase L3 on W1 side
IL1_W2 is the fundamental frequency phase current in phase L1 on W2 side
IL2_W2 is the fundamental frequency phase current in phase L2 on W2 side
IL3_W2 is the fundamental frequency phase current in phase L3
IL1_W3 is the fundamental frequency phase current in phase L1 on W3 side
IL2_W3 is the fundamental frequency phase current in phase L2 on W3 side
IL3_W3 is the fundamental frequency phase current in phase L3 on W3 side
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side (setting parameter)
Ur_W3 is transformer rated phase-to-phase voltage on W3 side (setting parameter)
A, B & C are three by three matrices with numerical coefficients

Values of the matrix A, B & C coefficients depend on:

1. Power transformer winding connection type, such as star (Y/y) or delta (D/d)
2. Transformer vector group such as Yd1, Dy11, YNautod5, Yy0d5 and so on,
which introduce phase displacement between individual windings currents in
multiples of 30°.
3. Settings for elimination of zero sequence currents for individual windings.

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Differential protection

When the end user enters all these parameters, transformer differential function
automatically calculates off-line the matrix coefficients. During this calculations
the following rules are used:

For the phase reference, the first winding with set star (Y) connection is always
used. For example, if the power transformer is a Yd1 power transformer, the HV
winding (Y) is taken as the phase reference winding. If the power transformer is a
Dy1, then the LV winding (y) is taken for the phase reference. If there is no star
connected winding, such as in Dd0 type of power transformers, then the HV delta
winding (D) is automatically chosen as the phase reference winding.

The fundamental frequency differential currents are in general composed of


currents of all sequences, that is, the positive-, the negative-, and the zero-sequence
currents. If the zero-sequence currents are eliminated (see section "Optional
Elimination of zero sequence currents"), then the differential currents can consist
only of the positive-, and the negative-sequence currents. When the zero-sequence
current is subtracted on one power transformer side, then it is subtracted from each
individual phase current.

As it can be seen from equation 5 and equation 6 the first entered winding (W1) is
always taken for ampere level reference (current magnitudes from all other sides
are always transferred to W1 side). In other words, within the differential
protection function, all differential currents and bias current are always expressed
in HV side primary Amperes.

It can be shown that the values of the matrix A, B & C coefficients (see equation 5
and equation 6) can be in advanced pre-calculated depending on the relative phase
shift between the reference winding and other power transformer windings.

Table 66 summarizes the values of the matrices for all standard phase shifts
between windings.

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Section 5 1MRK 502 027-UEN A
Differential protection

Table 66: Matrices for differential current calculation


Matrix with Zero Sequence Matrix with Zero Sequence
Reduction set to On Reduction set to Off
Matrix for Reference Winding
é 2 -1 -1ù é1 0 0 ù
1 ê
× -1 2 -1ú ê0 1 0 ú
3 ê ú ê ú
ëê -1 -1 2 ûú ëê0 0 1 úû
EQUATION1227 V1 EN (Equation 7) EQUATION1228 V1 EN (Equation 8)
Matrix for winding with 30° Not applicable. Matrix on the
lagging é 1 -1 0 ù left used.
1
× ê 0 1 -1ú
3 ê ú
ëê -1 0 1 úû
EQUATION1229 V1 EN (Equation 9)
Matrix for winding with 60°
é1 -2 1ù é 0 -1 0 ù
lagging 1 ê
× 1 1 -2 ú ê 0 0 -1ú
3 ê ú ê ú
êë -2 1 1 úû ëê -1 0 0 úû
EQUATION1230 V1 EN (Equation 10) EQUATION1231 V1 EN (Equation 11)
Matrix for winding with 90° Not applicable. Matrix on the
lagging é 0 -1 1 ù left used.
1
× ê 1 0 -1ú
3 ê ú
êë -1 1 0 úû
EQUATION1232 V1 EN (Equation 12)
Matrix for winding with 120°
lagging é -1 -1 2 ù é0 0 1 ù
1 ê
× 2 -1 -1ú ê1 0 0 ú
3 ê ú ê ú
êë -1 2 -1úû êë0 1 0 úû
EQUATION1233 V1 EN (Equation 13) EQUATION1234 V1 EN (Equation 14)
Matrix for winding with 150° Not applicable. Matrix on the
lagging é-1 0 1 ù left used.
1
× ê 1 -1 0 ú
3 ê ú
êë 0 1 -1úû
EQUATION1235 V1 EN (Equation 15)
Matrix for winding which is in
opposite phase é -2 1 1ù é -1 0 0 ù
1 ê
× 1 -2 1 ú ê 0 -1 0 ú
3 ê ú ê ú
ëê 1 1 -2 ûú êë 0 0 -1úû
EQUATION1236 V1 EN (Equation 16) EQUATION1237 V1 EN (Equation 17)
Matrix for winding with 150° Not applicable. Matrix on the
leading é-1 1 0 ù left used.
1
× ê 0 -1 1 ú
3 ê ú
ëê 1 0 -1ûú
EQUATION1238 V1 EN (Equation 18)
Table continues on next page

126
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1MRK 502 027-UEN A Section 5
Differential protection

Matrix with Zero Sequence Matrix with Zero Sequence


Reduction set to On Reduction set to Off
Matrix for winding with 120°
leading é -1 2 -1ù é0 1 0 ù
1 ê
× -1 -1 2 ú ê0 0 1 ú
3 ê ú ê ú
êë 2 -1 -1úû êë1 0 0 úû
EQUATION1239 V1 EN (Equation 19) EQUATION1240 V1 EN (Equation 20)

Matrix for winding with 90° Not applicable. Matrix on the


leading é 0 1 -1ù left used.
1
× ê -1 0 1 ú
3 ê ú
êë 1 -1 0 úû
EQUATION1241 V1 EN (Equation 21)
Matrix for winding with 60°
é1 1 -2 ù é 0 0 -1ù
leading 1 ê
× -2 1 1ú ê -1 0 0 ú
3 ê ú ê ú
êë 1 -2 1 úû êë 0 -1 0 úû
EQUATION1242 V1 EN (Equation 22) EQUATION1243 V1 EN (Equation 23)
Matrix for winding with 30° Not applicable. Matrix on the
leading é 1 0 -1ù left used.
1 ê
× -1 1 0 ú
3 ê ú
êë 0 -1 1 úû
EQUATION1244 V1 EN (Equation 24)

By using this table complete equation for calculation of fundamental frequency


differential currents for two winding power transformer with YNd5 vector group
and enabled zero sequence current reduction on HV side will be derived. From the
given power transformer vector group the following is possible to be concluded:

1. HV winding will be used as reference winding and zero sequence currents


shall be subtracted on that side
2. LV winding is lagging for 150°

With help of table 66, the following matrix equation can be written for this power
transformer:

é IDL1ù é 2 -1 -1ù é IL1_ W1ù é-1 0 1 ù é IL1_ W 2 ù


ê IDL2ú = 1 × ê-1 2 -1ú × ê IL2 _ W1ú + Ur _ W 2 × 1 × ê 1 -1 0 ú × ê IL2 _ W 2ú
ê ú 3 ê ú ê ú Ur _ W1 3 ê ú ê ú
êë IDL3úû êë-1 -1 2 úû êë IL3_ W1úû êë 0 1 -1úû êë IL3_ W 2 úû
EQUATION2015 V1 EN (Equation 25)

where:
IDL1 is the fundamental frequency differential current in phase L1 (in W1 side primary amperes)
IDL2 is the fundamental frequency differential current in phase L2 (in W1 side primary amperes)
IDL3 is the fundamental frequency differential current in phase L3 (in W1 side primary amperes)
IL1_W1 is the fundamental frequency phase current in phase L1 on W1 side
Table continues on next page

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Differential protection

IL2_W1 is the fundamental frequency phase current in phase L2 on W1 side


IL3_W1 is the fundamental frequency phase current in phase L3 on W1 side
IL1_W2 is the fundamental frequency phase current in phase L1 on W2 side
IL2_W2 is the fundamental frequency phase current in phase L2 on W2 side
IL3_W2 is the fundamental frequency phase current in phase L3 on W2 side
Ur_W1 is transformer rated phase-to-phase voltage on W1 side (setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side (setting parameter)

As marked in equation 5 and equation 6, the first term on the right hand side of the
equation, represents the total contribution from the individual phase currents from
W1 side to the fundamental frequency differential currents compensated for
eventual power transformer phase shift. The second term on the right hand side of
the equation, represents the total contribution from the individual phase currents
from W2 side to the fundamental frequency differential currents compensated for
eventual power transformer phase shift and transferred to the power transformer
W1 side. The third term on the right hand side of the equation, represents the total
contribution from the individual phase currents from W3 side to the fundamental
frequency differential currents compensated for eventual power transformer phase
shift and transferred to the power transformer W1 side. These current contributions
are important, because they are used for calculation of common bias current.

The fundamental frequency differential currents are the "usual" differential


currents, the magnitudes of which are applied in a phase-wise manner to the
operate - restrain characteristic of the differential protection. The magnitudes of the
differential currents can be read as service values from the function and they are
available as outputs IDL1MAG, IDL2MAG, IDL3MAG from the differential
protection function block. Thus they can be connected to the disturbance recorder
and automatically recorded during any external or internal fault condition.

On-line compensation for load tap changer movement


A load tap changer is a mechanical device, which is used to step-wise change
number of turns within one power transformer winding. Consequently the power
transformer overall turns ratio is changed. Typically the load tap changer is located
within the HV winding (that is, winding 1, W1) of the power transformer. By
operating load tap changer, it is possible to step-wise regulate voltage on the LV
side of the power transformer. However at the same time the differential protection
for power transformer becomes unbalanced. Differential function in the IED has built-
in feature to continuously monitor the load tap changer position and dynamically
compensate on-line for changes in power transformer turns ratio.

Differential currents are calculated as shown in equation 5and equation 6. If by


setting parameters is defined on which winding load tap changer is located and
what is the no-load voltage change for each step the differential function will make
no load voltage on that power transformer side dependent on actual load tap
changer position. Thus, if for example the load tap changer is located within
winding 1 the no-load voltage Vn_W1 will be treated as function of actual load tap
changer position in equation 5and equation 6. Thus for every load tap changer

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position corresponding value for Ur_W1 will be calculated and used in above-
mentioned equations. By doing this complete on-line compensation for load tap
changer movement is achieved. Differential protection will be ideally balanced for
every load tap changer position and no false differential current will appear
irrespective on actual load tap changer position.

Typically the minimum differential protection pickup for power transformer with
load tap changer is set between 30% to 40%. However with this load tap changer
compensation feature it is possible to set differential protection in the IED more
sensitive pickup value of 15% to 20%.

Load tap changer position is measured within the IED by Tap changer control and
supervision, (TCLYLTC). Within this function block the load tap changer position
value is continuously monitored to insure its integrity.

When any error with load tap changer position is detected the alarm is given which
shall be connected to the OLTCxAL input into the differential function block.
While OLTCxAL input has logical value one the differential protection minimum
pickup, originally defined by setting parameter IdMin, will be increased by the set
range of the load tap changer. Alternatively the differential current alarm feature
can be used to alarm for any problems in the whole load tap changer compensation
chain.

It shall be noted that:

• two-winding differential protection in the IED can on-line compensate for one
load tap changer within protected power transformer
• three-winding differential protection in the IED can on-line compensate for up
to two load tap changers within protected power transformer

Differential current alarm


Fundamental frequency differential current level is monitored all the time within
the differential function. As soon as all three fundamental frequency differential
currents are set, a threshold defined by setting parameter IDiffAlarm a delay on
pickup timer is started. When the pre-set time, defined by setting parameter
tAlarmDelay, has expired the differential current alarm is generated and output
signal IDALARM is set to logical value one. This feature can be effectively used to
provide alarm when load tap changer position compensation is used and something
in the whole compensation chain goes wrong. This alarm can be as well used with
some additional IED configuration logic to desensitize the differential function.

Bias current
The bias current is calculated as the highest current amongst individual winding
current contributions to the total fundamental frequency differential currents, as
shown in equation 5 and equation 6. All individual winding current contributions
are already referred to the power transformer winding one side (power transformer
HV winding) and therefore they can be compared regarding their magnitudes.
There are six (or nine in case of three-winding transformer) contributions to the
total fundamental differential currents, which are the candidates for the common

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Differential protection

bias current. The highest individual current contribution is taken as a common bias
(restrain) current for all three phases. This "maximum principle" makes the
differential protection more secure, with less risk to operate for external faults and
in the same time brings more meaning to the breakpoint settings of the operate -
restrain characteristic.

It shall be noted that if the zero-sequence currents are subtracted from the separate
contributions to the total differential current, then the zero-sequence component is
automatically eliminated from the bias current as well. This ensures that for
secondary injection from just one power transformer side the bias current is always
equal to the highest differential current regardless of the fault type. During normal
through-load operation of the power transformer, the bias current is equal to the
maximum load current from two (three) -power transformer windings.

The magnitudes of the common bias (restrain) current expressed in the HV side
Amperes can be read as service values from the function. At the same time it is
available as outputs IBIAS from the differential protection function block. Thus, it
can be connected to the disturbance recorder and automatically recorded during
any external or internal fault condition.

For application with so called "T" configuration, that is, two restraint CT inputs
from one side of the protected power transformer, such as in the case of breaker-and-
a-half scheme the primary CT ratings can be much higher then the rating of the
protected power transformer. In order to determine the bias current for such T
configuration, the two separate currents flowing on the T-side are scaled down to
the protected power transform level by means of additional setting. This is done in
order to prevent unwanted de-sensitizing of the overall differential protection. In
addition to that, the resultant currents (the sum of two currents) into the protected
power transformer winding, which is not directly measured is calculated, and
included as well in the common bias calculation. The rest of the bias calculation
procedure is the same as in protection schemes without breaker-and-a-half scheme.

Optional Elimination of zero sequence currents


To avoid unwanted trips for external earth-faults, the zero sequence currents should
be subtracted on the side of the protected power transformer, where the zero
sequence currents can flow at external earth-faults.

The zero sequence currents can be explicitly eliminated from the differential
currents and common bias current calculation by special, dedicated parameter
settings, which are available for every individual winding.

Elimination of the zero sequence component of current is necessary whenever:

• the protected power transformer cannot transform the zero sequence currents
to the other side, for any reason.
• the zero sequence currents can only flow on one side of the protected power
transformer.

In most cases, power transformers do not properly transform the zero sequence
current to the other side. A typical example is a power transformer of the star-delta

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type, for example YNd1. Transformers of this type do not transform the zero
sequence quantities, but zero sequence currents can flow in the earthed star-
connected winding. In such cases, an external earth-fault on the star-side causes the
zero sequence currents to flow on the star-side of the power transformer, but not on
the other side. This results in false differential currents - consisting exclusively of
the zero sequence currents. If high enough, these false differential currents can
cause an unwanted disconnection of the healthy power transformer. They must
therefore be subtracted from the fundamental frequency differential currents if an
unwanted trip is to be avoided.

For delta windings this feature shall be enabled only if an earthing transformer
exist within differential zone on the delta side of the protected power transformer.

Removing the zero sequence current from the differential currents decreases to
some extent sensitivity of the differential protection for internal earth-faults. In
order to counteract this effect to some degree, the zero sequence currents are
subtracted not only from the three fundamental frequency differential currents, but
automatically from the bias current as well.

Restrained, and unrestrained limits of the differential protection


Power transformer differential protection function uses two limits, to which actual
magnitudes of the three fundamental frequency differential currents are compared
at each execution of the function.

The unrestrained (that is, non-stabilized, "instantaneous") part of the differential


protection is used for very high differential currents, where it should be beyond any
doubt, that the fault is internal. This settable limit is constant (that is, not
proportional to the bias current). Neither harmonic, nor any other restrain is applied
to this limit, which is therefore allowed to trip power transformer instantaneously.

The restrained (that is, stabilized) part of the differential protection compares the
calculated fundamental differential (that is, operating) currents, and the bias (that
is, restrain) current, by applying them to the operate - restrain characteristic.
Practically, the magnitudes of the individual fundamental frequency differential
currents are compared with an adaptive limit. This limit is adaptive because it is
dependent on the bias (that is, restrain) current magnitude. This limit is called the
operate - restrain characteristic. It is represented by a double-slope, double-
breakpoint characteristic, as shown in figure 62. The restrained characteristic is
determined by the following 5 settings:

1. IdMin (Sensitivity in section 1, multiple of trans. HV side rated current set


under the parameter RatedCurrentW1)
2. EndSection1 (End of section 1, as multiple of transformer HV side rated
current set under the parameter RatedCurrentW1)
3. EndSection2 (End of section 2, as multiple of transformer HV side rated
current set under the parameter RatedCurrentW1)
4. SlopeSection2 (Slope in section 2, as multiple of transformer HV side rated
current set under the parameter RatedCurrentW1)
5. SlopeSection3 (Slope in section 2, as multiple of transformer HV side rated
current set under the parameter RatedCurrentW1)

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The restrained characteristic in figure 62 is defined by the settings:

1. IdMin
2. EndSection1
3. EndSection2
4. SlopeSection2
5. SlopeSection3

operate current
[ times IBase ]
Operate
5
unconditionally

UnrestrainedLimit
4

Operate
3
conditionally

2
Section 1 Section 2 Section 3

SlopeSection3
1
IdMin
SlopeSection2 Restrain
0
0 1 2 3 4 5

EndSection1 restrain current


EndSection2 [ times IBase ]

en05000187-2.vsd
IEC05000187 V2 EN

Figure 62: Description of the restrained, and the unrestrained operate


characteristics

where:

slope = D Ioperate × 100%


D Irestrain
EQUATION1246 V1 EN

The operate - restrain characteristic is tailor-made and can be designed freely by


the user after his needs. The default characteristic is recommended to be used. It
gives good results in a majority of applications. The operate - restrain characteristic
has in principle three sections with a section-wise proportionality of the operate

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Differential protection

value to the bias (restrain) current. The reset ratio is in all parts of the characteristic
is equal to 0.95.

Section 1: This is the most sensitive part on the characteristic. In section 1, normal
currents flow through the protected circuit and its current transformers, and risk for
higher false differential currents is relatively low. Un-compensated on-load tap-
changer is a typical reason for existence of the false differential currents in this
section. Slope in section 1 is always zero percent.

Section 2: In section 2, a certain minor slope is introduced which is supposed to


cope with false differential currents proportional to higher than normal currents
through the current transformers.

Section 3: The more pronounced slope in section 3 is designed to result in a higher


tolerance to substantial current transformer saturation at high through-fault
currents, which may be expected in this section.

The operate - restrain characteristic should be designed so that it can be expected that:

• for internal faults, the operate (differential) currents are always safely, that is,
with a good margin, above the operate - restrain characteristic
• for external faults, the false (spurious) operate currents are safely, that is, with
a good margin, below the operate - restrain characteristic

Fundamental frequency negative sequence differential currents


Existence of relatively high negative sequence currents is in itself a proof of a
disturbance on the power system, possibly a fault in the protected power
transformer. The negative-sequence currents are measurable indications of
abnormal conditions, similar to the zero sequence currents. One of the several
advantages of the negative sequence currents compared to the zero sequence
currents is however that they provide coverage for phase-to-phase and power
transformer turn-to-turn faults as well, not only for earth-faults. Theoretically the
negative sequence currents do not exist during symmetrical three-phase faults,
however they do appear during initial stage of such faults for long enough time (in
most cases) for the IED to make proper decision. Further, the negative sequence
currents are not stopped at a power transformer of the Yd, or Dy connection. The
negative sequence currents are always properly transformed to the other side of any
power transformer for any external disturbance. Finally, the negative sequence
currents are not affected by symmetrical through-load currents.

For power transformer differential protection application, the negative sequence


based differential currents are calculated by using exactly the same matrix
equations, which are used to calculate the traditional phase-wise fundamental
frequency differential currents. However, the same equation shall be fed by the
negative sequence currents from the two power transformer sides instead of
individual phase currents, as shown in matrix equation 27 for a case of two-
winding, YNd5 power transformer.

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Differential protection

é IDL1 _ NS ù é2 -1 -1ù é INS _ W 1 ù é -1 0 1 ù é INS _ W 2 ù


ê IDL 2 _ NS ú = 1 × ê -1 2 -1 × ê a × INS _ W 1 ú +
ú Ur _ W 2
×
1
×ê1 -1 0 ú × ê a × INS _ W 2 ú
ê ú 3 ê ú ê 2 ú Ur _ W 1 3 ê ú ê 2 ú
ëê IDL3 _ NS ûú ëê -1 -1 2ûú ëê a × INS _ W 1ûú ëê 0 1 ú ëê a × INS _ W 2 ûú
-1û

1 2 3

EQUATION1247 V1 EN (Equation 27)

where:
1. is Negative Sequence Differential Currents
2. is Negative Sequence current contribution from W1 side
3. is Negative Sequence current contribution from W2 side

and where:
IDL1_NS is the negative sequence differential current in phase L1 (in
W1 side primary amperes)
IDL2_NS is the negative sequence differential current in phase L2 (in
W1 side primary amperes)
IDL3_NS is the negative sequence differential current in phase L3 (in
W1 side primary amperes)
INS_W1 is negative sequence current on W1 side in primary
amperes (phase L1 reference)
INS_W2 is negative sequence current on W1 side in primary
amperes (phase L1 reference)
Ur_W1 is transformer rated phase-to-phase voltage on W1 side
(setting parameter)
Ur_W2 is transformer rated phase-to-phase voltage on W2 side
(setting parameter)

a is the complex operator for sequence quantities, for example,

j ×120
o 1 3
a=e =- + j×
2 2
EQUATION1248 V1 EN (Equation 28)

Because the negative sequence currents always form the symmetrical three phase
current system on each transformer side (that is, negative sequence currents in
every phase will always have the same magnitude and be phase displaced for 120
electrical degrees from each other), it is only necessary to calculate the first
negative sequence differential current that is, IDL1_NS.

As marked in equation 27, the first term on the right hand side of the equation,
represents the total contribution of the negative sequence current from W1 side
compensated for eventual power transformer phase shift. The second term on the
right hand side of the equation, represents the total contribution of the negative
sequence current from W2 side compensated for eventual power transformer phase

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shift and transferred to the power transformer W1 side. These negative sequence
current contributions are phasors, which are further used in directional
comparisons, made in order to characterize a fault as internal or external. See
section "Internal/external fault discriminator" for more information.

The magnitudes of the negative sequence differential current expressed in the HV


side A can be read as service values from the function. In the same time it is
available as outputs IDNSMAG from the differential protection function block.
Thus, it can be connected to the disturbance recorder and automatically recorded
during any external or internal fault condition.

Internal/external fault discriminator


The internal/external fault discriminator is a very powerful and reliable
supplementary criterion to the traditional differential protection. It is recommended
that this feature shall be always used (that is, On) when protecting three-phase
power transformers. The internal/external fault discriminator detects even minor
faults, with a high sensitivity and at high speed, and at the same time discriminates
with a high degree of dependability between internal and external faults.

The algorithm of the internal/external fault discriminator is based on the theory of


symmetrical components. Already in 1933, Wagner and Evans in their famous
book "Symmetrical Components" have stated that:

Source of the negative-sequence currents is at the point of fault,


1.
E NS = - I NS × Z NS

EQUATION1254 V1 EN (Equation 29)


2. Negative-sequence currents distribute through the negative-sequence
network
3. Negative-sequence currents obey the first Kirchhoff"s law

The internal/external fault discriminator responds to magnitudes and the relative


phase angles of the negative-sequence fault currents at different windings (that is,
sides) of the protected power transformer. The negative sequence fault currents
must of course first be referred to the same phase reference side, and put to the
same magnitude reference. This is done by the matrix expression (see equation 27).

Operation of the internal/external fault discriminator is based on the relative


position of the two phasors representing winding one (W1) and winding two (W2)
negative sequence current contributions, respectively, defined by expression shown
in equation 27. It performs a directional comparison between these two phasors.
First, the LV side phasor is referred to the HV side (W1 side): both the magnitude,
and the phase position are referred to the HV (W1 side). Then the relative phase
displacement between the two negative sequence current phasors is calculated. In
case of three-winding power transformers, a little more complex algorithm is
applied, with two directional tests. The overall directional characteristic of the
internal/external fault discriminator is shown in figure 63, where the directional
characteristic is defined by two setting parameters:

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Differential protection

1. IMinNegSeq
2. NegSeqROA

90 deg
120 deg
If one or the Internal/external
other of fault boundary
currents is too
low, then no
measurement
NegSeqROA
is done, and (Relay
120 degrees
Operate
is mapped Angle)

180 deg 0 deg

IMinNegSeq

External Internal
fault fault
region region

270 deg
en05000188-2-en.vsd
IEC05000188 V2 EN

Figure 63: Operating characteristic of the internal/external fault discriminator

In order to perform directional comparison of the two phasors their magnitudes


must be high enough so that one can be sure that they are due to a fault. On the
other hand, in order to guarantee a good sensitivity of the internal/external fault
discriminator, the value of this minimum limit must not be too high. Therefore this
limit value, called IminNegSeq, is settable in the range of 0.02 to 0.20 times the
IBase of the power transformer winding one. The default value is 0.04. Note that,
in order to enhance stability at higher fault currents, the relatively very low
threshold value IminNegSeq is dynamically increased at currents higher than
normal currents: if the bias current is higher than 110% IBase current, than 10% of
the bias current is added to the IminNegSeq.Only if magnitudes of both negative
sequence current contributions are above the actual limit, the relative position
between these two phasors is checked. If either of the negative sequence current
contributions, which should be compared, is too small (less than the set value for
IminNegSeq), no directional comparison is made in order to avoid the possibility to
produce a wrong decision. This magnitude check, as well guarantee stability of the
algorithm, when power transformer is energized. The setting NegSeqROA
represents the Relay Operate Angle, which determines the boundary between the
internal and external fault regions. It can be selected in the range from ±30 degrees
to ±90 degrees, with a step of 0.1 degree. The default value is ±60 degrees. The
default setting ±60 degree favours somewhat security in comparison to dependability.

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If the above condition concerning magnitudes is fulfilled, the internal/external fault


discriminator compares the relative phase angle between the negative sequence
current contributions from the W1 and W2 sides of the power transformer using the
following two rules:

• If the negative sequence currents contributions from W1 and W2 sides are in


phase, the fault is internal (that is, both phasors are within protected zone)
• If the negative sequence currents contributions from W1 and W2 sides are 180
degrees out of phase, the fault is external (that is, W1 phasors is outside
protected zone)

For example, for any unsymmetrical external fault, ideally the respective negative
sequence current contributions from the W1 and W2 power transformer sides will
be exactly 180 degrees apart and equal in magnitude, regardless the power
transformer turns ratio and phase displacement. One such example is shown in
figure 64, which shows trajectories of the two separate phasors representing the
negative sequence current contributions from HV and LV sides of an Yd5 power
transformer (for example, after the compensation of the transformer turns ratio and
phase displacement by using equation 27) for an unsymmetrical external fault.
Observe that the relative phase angle between these two phasors is 180 electrical
degrees at any point in time. No current transformer saturation was assumed for
this case.

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Differential protection

"steady state"
for HV side 90
neg. seq. phasor
60

150 30

10
ms

180 0
0.1 kA
0.2 kA
0.3 kA
10 0.4 kA
ms
210 330

"steady state"
240 for LV side
270 neg. seq. phasor

Contribution to neg. seq. differential current from HV side


Contribution to neg. seq. differential current from LV side

en05000189.vsd
IEC05000189 V1 EN

Figure 64: Trajectories of Negative Sequence Current Contributions from HV


and LV sides of Yd5 power transformer during external fault

Therefore, under all external fault condition, the relative angle is theoretically
equal to 180 degrees. During internal fault, the angle shall ideally be 0 degrees, but
due to possible different negative sequence source impedance angles on W1 and
W2 sides of the protected power transformer, it may differ somewhat from the
ideal zero value. However, during heavy faults, CT saturation might cause the
measured phase angle to differ from 180 degrees for external, and from about 0
degrees for internal fault. See figure 65 for an example of a heavy internal fault
with transient CT saturation.

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Differential protection

Dire ctiona l Compa ris on Crite rion: Inte rna l fa ult a s s e e n from the HV s ide
90
e xcurs ion
120 60
from 0 de gre e s
35 ms due to CT
s a tura tion
150 30
de finite ly
a n inte rna l
fa ult

180 0
trip c o mmand
in 12 ms
e xte rna l
fa ult Inte rna l fa ult
0.5 kA de cla re d 7 ms
re gion
210 330 a fte r inte rna l
fa ult occure d
1.0 kA

240 300
1.5 kA
270
HV s ide contribution to the tota l ne ga tive s e que nce diffe re ntia l curre nt in kA
Dire ctiona l limit (within the re gion de limite d by ± 60 de gre e s is inte rna l fa ult)

en05000190.vsd

IEC05000190 V1 EN

Figure 65: Operation of the internal/external fault discriminator for internal


fault with CT saturation

However, it shall be noted that additional security measures are implemented in the
internal/external fault discriminator algorithm in order to guaranty proper operation
with heavily saturated current transformers. The trustworthy information on
whether a fault is internal or external is typically obtained in about 10ms after the
fault inception, depending on the setting IminNegSeq, and the magnitudes of the
fault currents. At heavy faults, approximately 5ms time to full saturation of the
main CT is sufficient in order to produce a correct discrimination between internal
and external faults.

Unrestrained, and sensitive negative sequence protections


Two sub functions, which are based on the internal/external fault discriminator
with the ability to trip a faulty power transformer, are parts to the traditional power
transformer differential protection.

The unrestrained negative sequence differential protection


If one or more start signals have been set by the traditional differential protection
algorithm, because one or more of the fundamental frequency differential currents
entered the operate region on the operate - restrain characteristic then the
unrestrained negative sequence protection is activated. So, this protection is not
independent of the traditional restrained differential protection - it is activated after
the first start signal has been placed.

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If the same fault has been positively recognized as internal, then the unrestrained
negative sequence differential protection places its own trip request.

Any block signals by the harmonic and/or waveform criteria, which can block the
traditional differential protection are overridden, and the differential protection
operates quickly without any further delay.

This logic guarantees a fast disconnection of a faulty power transformer for any
heavier internal faults.

If the same fault has been classified as external, then generally, but not
unconditionally, a trip command is prevented. If a fault is classified as external, the
further analysis of the fault conditions is initiated. If all the instantaneous
differential currents in phases where start signals have been issued are free of
harmonic pollution, then a (minor) internal fault, simultaneous with a predominant
external fault can be suspected. This conclusion can be drawn because at external
faults, major false differential currents can only exist when one or more current
transformers saturate. In this case, the false instantaneous differential currents are
polluted by higher harmonic components, the 2nd, the 5th etc.

Sensitive negative sequence based turn-to-turn fault protection


The sensitive, negative sequence current based turn-to-turn fault protection detects
the low level faults, which are not detected by the traditional differential protection
until they develop into more severe faults, including power transformer iron core.
The sensitive protection is independent from the traditional differential protection
and is a very good complement to it. The essential part of this sensitive protection
is the internal/external fault discriminator. In order to be activated, the sensitive
protection requires no start signal from the traditional power transformer biased
differential protection. If magnitudes of HV and LV negative sequence current
contributions are above the set limit for IminNegSeq, then their relative positions
are determined. If the disturbance is characterized as an internal fault, then a
separate trip request will be placed. Any decision on the way to the final trip
request must be confirmed several times in succession in order to cope with
eventual CT transients. This causes a short additional operating time delay due to
this security count. For very low level turn-to-turn faults the overall response time
of this protection is about 30ms.

Instantaneous differential currents


The instantaneous differential currents are calculated from the instantaneous values
of the input currents in order to perform the harmonic analysis and waveform
analysis upon each one of them (see section "Harmonic and waveform block
criteria" for more information).

The instantaneous differential currents are calculated using the same matrix
expression as shown in equation 5 and equation 6. The same matrices A, B and C
are used for these calculations as well. The only difference is that the matrix
algorithm is fed by instantaneous values of currents, that is, samples.

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Harmonic and waveform block criteria


The two block criteria are the harmonic restrain and the waveform restrain. These
two criteria have the power to block (that is, to prevent) a trip command by the
traditional differential protection, which produces start signals by applying the
differential currents, and the bias current, to the operate - restrain characteristic.

Harmonic restrain
The harmonic restrain is the classical restrain method traditionally used with power
transformer differential protections. The goal is to prevent an unwanted trip
command due to magnetizing inrush currents at switching operations, or due to
magnetizing currents at over-voltages.

The magnetizing currents of a power transformer flow only on one side of the
power transformer (one or the other) and are therefore always the cause of false
differential currents. The harmonic analysis (the 2nd and the 5th harmonic) is
applied to instantaneous differential currents. Typically instantaneous differential
currents during power transformer energizing are shown in figure 66. The
harmonic analysis is only applied in those phases, where start signals have been
set. For example, if the content of the 2nd harmonic in the instantaneous differential
current of phase L1 is above the setting I2/I1Ratio, then a block signal is set for
that phase, which can be read as BLK2HL1 output of the differential protection.

Waveform restrain
The waveform restrain criterion is a good complement to the harmonic analysis.
The waveform restrain is a pattern recognition algorithm, which looks for intervals
within each fundamental power system cycle with low instantaneous differential
current. This interval is often called current gap in protection literature. However,
within differential function this criterion actually searches for long-lasting intervals
with low rate-of-change in instantaneous differential current, which are typical for
the power transformer inrush currents. Block signals BLKWAVLx are set in those
phases where such behavior is detected. The algorithm do not requires any end user
settings. The waveform algorithm is automatically adapted dependent only on the
power transformer rated data.

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Differential protection

IEC05000343 V1 EN

Figure 66: Inrush currents to a transformer as seen by a protective IED.


Typical is a high amount of the 2nd harmonic, and intervals of low
current, and low rate-of-change of current within each period.

Cross-blocking between phases


Basic definition of the cross-blocking is that one of the three phases can block
operation (that is,tripping) of the other two phases due to the harmonic pollution of
the differential current in that phase (that is, waveform, 2nd or 5th harmonic
content). In differential algorithm the user can control the cross-blocking between
the phases via the setting parameter CrossBlockEn=On.

When parameter CrossBlockEn=On cross blocking between phases is introduced.


There is no time settings involved, but the phase with the operating point above the
set bias characteristic (in the operate region) will be able to cross-block other two
phases if it is itself blocked by any of the previously explained restrained criteria.
As soon as the operating point for this phase is below the set bias characteristic
(that is, in the restrain region) cross blocking from that phase will be inhibited. In
this way cross-blocking of the temporary nature is achieved. It should be noted that
this is the default (recommended) setting value for this parameter.

When parameter CrossBlockEn=Off, any cross blocking between phases will be


disabled. It is recommended to use the value Off with caution in order to avoid the
unwanted tripping during initial energizing of the power transformer.

Switch onto fault feature


Transformer differential function in the IED has a built-in, advanced switch onto
fault feature. This feature can be enabled or disabled by a setting parameter
SOTFMode. When enabled this feature ensures quick differential protection
tripping in cases where a transformer is energized with an internal fault (for
example, forgotten earthing on transformer LV side). Operation of this feature is
based on the fact that a current gap (term current gap is explained under waveblock
feature above) will exist within the first power system cycle when healthy power
transformer is energized. If this is not the case the waveblock criterion will reset

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quickly. A quick reset of the waveblock criterion will temporarily disable the
second harmonic blocking feature within the differential function. This
consequently ensures fast operation of the transformer differential function for a
switch onto a fault condition. It shall be noted that this feature is only active during
initial power transformer energizing, more exactly, under the first 50 ms. When the
switch onto fault feature is disabled by the setting parameter SOTFMode, the
waveblock and second harmonic blocking features work in parallel and are
completely independent from each other.

Open CT detection feature


differential protection has a built-in, advanced open CT detection feature.

The open CT circuit condition creates unexpected operations for differential


protection under the normal load conditions. It is also possible to damage
secondary equipment due to high voltage produced from open CT circuit outputs.
Therefore, it is always a requirement from security and reliability points of view to
have open CT detection function to block differential protection function in case of
open CT conditions and at the same time, produce the alarm signal to the
operational personal to make quick remedy actions to correct the open CT condition.

The built-in open CT feature can be enabled or disabled by a setting parameter


OpenCTEnable (Off/On). When enabled, this feature prevents mal-operation when
a loaded main CT connected to differential protection is by mistake open circuited
on the secondary side. Note that this feature can only detect interruption of one CT
phase current at the time. If two or even all three-phase currents of one set of CT
are accidentally interrupted at the same time this feature cannot operate and
differential protection generates trip signal, if the false differential current is
sufficiently high. To ensure blocking of the differential protection for open CT
condition this algorithm must operate within 10 ms in order to be able to prevent
unwanted operation of differential protection under all loading conditions.

The principle applied to detect an open CT is a simple pattern recognition method,


similar to the waveform check which has been with advantage used by the Power
Transformer Differential Protection in order to detect the magnetizing inrush
condition. The open CT detection principle is based on the fact, that for an open
CT, the current in the phase with the open CT suddenly drops (at least
theoretically) to zero (that is, as seen by the protection), while the currents of the
other two phases continue as before.

The open CT function is supposed to detect an open CT under normal conditions,


that is, with the protected multi-terminal circuit under normal load. If the load
currents are very low or zero, the open CT condition cannot be detected. The open
CT algorithm only detects an open CT if the load on the power transformer is from
10% to 110% of the rated load. Outside this range an open CT condition is not
even looked for. The search for an open CT starts after 60 seconds (50 seconds in
60 Hz systems) since the bias current enters the 10–110% range. The Open CT
detection feature can also be explicitly deactivated by setting: OpenCTEnable = 0
(Off).

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If an open CT is detected and the output OPENCT set to 1, then all the differential
functions are blocked, except of the unrestrained (instantaneous) differential. An
alarm signal is also produced after a settable delay (tOCTAlarmDelay) to report to
operational personal for quick remedy actions once the open CT is detected. When
the open CT condition is removed (that is, the previously open CT reconnected),
the functions remain blocked for a specified interval of time, which is also a setting
(tOCTResetDelay). The task of this measure is to prevent an eventual mal-
operation after the reconnection of the previously open CT secondary circuit.

The open CT feature works only during normal loading condition. Thus, the open
CT feature must be automatically disabled for all external faults, big overloads and
inrush conditions.

The open CT algorithm provides detailed information about the location of the
defective CT secondary circuit. The algorithm clearly indicates IED side, CT input
and phase in which open CT condition has been detected. These indications are
provided via the following outputs from Line differential protection function:

1. Output OPENCT provides instant information to indicate that open CT circuit


has been detected
2. Output OPENCTAL provides time delayed alarm that the open CT circuit has
been detected. Time delay is defined by setting parameter tOCTAlarmDelay.
3. Integer output OPENCTIN provides information on the local HMI regarding
which open CT circuit has been detected (1=CT input No 1; 2=CT input No 2)
4. Integer output OPENCTPH provides information on the local HMI regarding
in which phase open CT circuit has been detected (1=Phase L1; 2= Phase L2;
3= Phase L3)

Once the open CT condition is declared, the algorithm stops to search for further
open CT circuits. It waits until the first open CT circuit has been corrected. Note
that once the open CT condition has been detected, it can be automatically reset
within the differential function. It is not possible to externally reset open CT
condition. To reset the open CT circuit alarm automatically, the following
conditions must be fulfilled:

• Bias current is for at least one minute smaller than 110%


• Open CT condition in defective CT circuit has been rectified (for example,
current asymmetry disappears)
• Above two conditions are fulfilled for longer time than defined by the setting
parameter tOCTResetDelay

After the reset, the open CT detection algorithm starts again to search for any other
open CT circuit within the protected zone.

5.2.2.2 Logic diagram

The simplified internal logics, for transformer differential protection are shown in
the following figures.

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Differential protection

ADM Differential function


Trafo
Data
A/D conversion scaling with CT

Phasor calculation of individual

Open CT logic on W1 side


Instantaneous (sample based) IDL1

Phasors & samples


phase current
Differential current, phase L1
ratio

IDL2

Derive equation to calculate differential currents


Instantaneous (sample based)
Differential current, phase L2

Instantaneous (sample based) IDL3


Differential current, phase L3

Negative sequence diff current IDNSMAG


& NS current contribution from
A/D conversion scaling with CT

Phasor calculation of individual

individual windings
Open CT logic on W2 side
phase current

IDL1MAG
Fundamental frequency (phasor
based) Diff current, phase L1 &
ratio

phase current contributions from


individual windings
Phasors & samples

IDL2MAG
Fundamental frequency (phasor
based) Diff current, phase L2 &
phase current contributions from
individual windings
IDL3MAG
Fundamental frequency (phasor
based) Diff current, phase L3 &
phase current contributions from
individual windings
MAX IBIAS

Settings for Zer. Seq.


Current Reduction

en06000554-3-en.vsd

IEC06000544 V3 EN

Figure 67: Treatment of measured currents within IED for transformer differential function

Figure 67 shows how internal treatment of measured currents is done in case of two-
winding transformer.

The following currents are inputs to the power transformer differential protection
function. They must all be expressed in true power system (primary) A, that is, as
measured.

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Section 5 1MRK 502 027-UEN A
Differential protection

1. Instantaneous values of currents (samples) from HV, and LV sides for two-
winding power transformers, and from the HV, the first LV, and the second
LV sides for three-winding power transformers.
2. Currents from all power transformer sides expressed as fundamental frequency
phasors, with their real, and imaginary parts. These currents are calculated
within the protection function by the fundamental frequency Fourier filters.
3. Negative sequence currents from all power transformer sides expressed as
phasors. These currents are calculated within the protection function by the
symmetrical components module.

The power transformer differential protection:

1. Calculates three fundamental frequency differential currents, and one common


bias current. The zero-sequence component can optionally be eliminated from
each of the three fundamental frequency differential currents, and at the same
time from the common bias current.
2. Calculates three instantaneous differential currents. They are used for
harmonic, and waveform analysis. Instantaneous differential currents are
useful for post-fault analysis using disturbance recording
3. Calculates negative-sequence differential current. Contributions to it from both
(all three) power transformer sides are used by the internal/external fault
discriminator to detect and classify a fault as internal or external.

BLKUNRES

IdUnre a TRIPUNREL1
b>a AND
b
IDL1MAG

IBIAS STL1
AND
BLOCK
BLKRES

TRIPRESL1
AND
OR 1

IDL1
to fault logic

2nd BLK2HL1
Switch on

Harmonic

Wave BLKWAVL1
block

5th BLK5HL1
Harmonic
Cross Block
Cross Block to L2 or L3
from L2 or L3 AND
OR
AND
OpCrossBlock=On

en06000545.vsd
IEC06000545 V1 EN

Figure 68: Transformer differential protection simplified logic diagram for


Phase L1

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1MRK 502 027-UEN A Section 5
Differential protection

IEC05000167-TIFF V1 EN

Figure 69: Transformer differential protection simplified logic diagram for


external/internal fault discriminator

TRIPRESL1
TRIPRESL2 TRIPRES
OR
TRIPRESL3

TRIPUNREL1
TRIPUNREL2 TRIPUNRE
OR
TRIPUNREL3

TRIP
TRNSSENS OR
TRNSUNR

en05000278.vsd
IEC05000278 V1 EN

Figure 70: Transformer differential protection internal grouping of tripping


signals

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Section 5 1MRK 502 027-UEN A
Differential protection

IEC05000279-TIFF V1 EN

Figure 71: Transformer differential protection internal grouping of logical signals

Logic in figures 68, 69, 70 and 71 can be summarized as follows:

1. The three fundamental frequency differential currents are applied in a phase-


wise manner to two limits. The first limit is the operate-restrain characteristic,
while the other is the high-set unrestrained limit. If the first limit is exceeded, a
start signal START is set. If the unrestrained limit is exceeded, an immediate
unrestrained trip TRIPUNRE and common trip TRIP are issued.
2. If a start signal is issued in a phase, then the harmonic-, and the waveform
block signals are checked. Only a start signal, which is free of all of its
respective block signals, can result in a trip command. If the cross-block logic
scheme is applied, then only if all phases with set start signal are free of their
respective block signals, a restrained trip TRIPRES and common trip TRIP are
issued
3. If a start signal is issued in a phase, and the fault has been classified as
internal, then any eventual block signals are overridden and a unrestrained
negative-sequence trip TRNSUNR and common trip TRIP are issued without
any further delay. This feature is called the unrestrained negative-sequence
protection.
4. The sensitive negative sequence differential protection is independent of any
start signals. It is meant to detect smaller internal faults, such as turn-to-turn
faults, which are often not detected by the traditional differential protection.
The sensitive negative sequence differential protection starts whenever both
contributions to the total negative sequence differential current (that must be
compared by the internal/external fault discriminator) are higher than the value
of the setting IMinNegSeq. If a fault is positively recognized as internal, and
the condition is stable with no interruption for at least one fundamental
frequency cycle the sensitive negative sequence differential protection
TRNSSENS and common trip TRIP are issued. This feature is called the
sensitive negative sequence differential protection.
5. If a start signal is issued in a phase (see signal STL1), even if the fault has
been classified as an external fault, then the instantaneous differential current

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of that phase (see signal IDL1) is analyzed for the 2nd and the 5th harmonic
contents (see the blocks with the text inside: 2nd Harmonic; Wave block and
5th Harmonic). If there is less harmonic pollution, than allowed by the settings
I2/I1Ratio, and I5/I1Ratio, (then the outputs from the blocks 2nd harmonic and
5th harmonic is 0) then it is assumed that a minor simultaneous internal fault
must have occurred. Only under these conditions a trip command is allowed
(the signal TRIPRESL1 is = 1). The cross-block logic scheme is automatically
applied under such circumstances. (This means that the cross block signals
from the other two phases L2 and L3 is not activated to obtain a trip on the
TRIPRESL1 output signal in figure 68)
6. All start and blocking conditions are available as phase segregated as well as
common (that is three-phase) signals.

IDL1 MAG
a
a>b
I Diff Alarm b

IDL2 MAG tAlarm Delay


a
& IDALARM
a>b t
I Diff Alarm b

IDL3 MAG
a
a>b
I Diff Alarm b

en06000546.vsd
IEC06000546 V1 EN

Figure 72: Differential current alarm logic

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Differential protection

5.2.3 Function block


T2WPDIF
I3PW1CT1* TRIP
I3PW1CT2* TRIPRES
I3PW2CT1* TRIPUNRE
I3PW2CT2* TRNSUNR
TAPOLTC1 TRNSSENS
OLTC1AL START
BLOCK STL1
BLKRES STL2
BLKUNRES STL3
BLKNSUNR BLK2H
BLKNSSEN BLK2HL1
BLK2HL2
BLK2HL3
BLK5H
BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG

IEC06000249_2_en.vsd
IEC06000249 V2 EN

Figure 73: T2WPDIF function block

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1MRK 502 027-UEN A Section 5
Differential protection

T3WPDIF
I3PW1CT1* TRIP
I3PW1CT2* TRIPRES
I3PW2CT1* TRIPUNRE
I3PW2CT2* TRNSUNR
I3PW3CT1* TRNSSENS
I3PW3CT2* START
TAPOLTC1 STL1
TAPOLTC2 STL2
OLTC1AL STL3
OLTC2AL BLK2H
BLOCK BLK2HL1
BLKRES BLK2HL2
BLKUNRES BLK2HL3
BLKNSUNR BLK5H
BLKNSSEN BLK5HL1
BLK5HL2
BLK5HL3
BLKWAV
BLKWAVL1
BLKWAVL2
BLKWAVL3
IDALARM
OPENCT
OPENCTAL
IDL1
IDL2
IDL3
IDL1MAG
IDL2MAG
IDL3MAG
IBIAS
IDNSMAG

IEC06000250_2_en.vsd
IEC06000250 V2 EN

Figure 74: T3WPDIF function block

5.2.4 Input and output signals


Table 67: T2WPDIF Input signals
Name Type Default Description
I3PW1CT1 GROUP - Three phase winding primary CT1
SIGNAL
I3PW1CT2 GROUP - Three phase winding primary CT2
SIGNAL
I3PW2CT1 GROUP - Three phase winding secondary CT1
SIGNAL
I3PW2CT2 GROUP - Three phase winding secondary CT2
SIGNAL
TAPOLTC1 INTEGER 1 Most recent tap position reading on OLTC 1
OLTC1AL BOOLEAN 0 OLTC1 alarm
BLOCK BOOLEAN 0 Block of function
BLKRES BOOLEAN 0 Block of trip for restrained differential feature
BLKUNRES BOOLEAN 0 Block of trip for unrestrained differential feature
BLKNSUNR BOOLEAN 0 Block of trip for unrestr. neg. seq. differential
feature
BLKNSSEN BOOLEAN 0 Block of trip for sensitive neg. seq. differential
feature

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Table 68: T2WPDIF Output signals


Name Type Description
TRIP BOOLEAN General, common trip signal
TRIPRES BOOLEAN Trip signal from restrained differential protection
TRIPUNRE BOOLEAN Trip signal from unrestrained differential protection
TRNSUNR BOOLEAN Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS BOOLEAN Trip signal from sensitive neg. seq. diff. protection
START BOOLEAN Common start signal from any phase
STL1 BOOLEAN Start signal from phase L1
STL2 BOOLEAN Start signal from phase L2
STL3 BOOLEAN Start signal from phase L3
BLK2H BOOLEAN Common second harmonic block signal from any
phase
BLK2HL1 BOOLEAN Second harmonic block signal, phase L1
BLK2HL2 BOOLEAN Second harmonic block signal, phase L2
BLK2HL3 BOOLEAN Second harmonic block signal, phase L3
BLK5H BOOLEAN Common fifth harmonic block signal from any
phase
BLK5HL1 BOOLEAN Fifth harmonic block signal, phase L1
BLK5HL2 BOOLEAN Fifth harmonic block signal, phase L2
BLK5HL3 BOOLEAN Fifth harmonic block signal, phase L3
BLKWAV BOOLEAN Common block signal, waveform criterion, from
any phase
BLKWAVL1 BOOLEAN Block signal, waveform criterion, phase L1
BLKWAVL2 BOOLEAN Block signal, waveform criterion, phase L2
BLKWAVL3 BOOLEAN Block signal, waveform criterion, phase L3
IDALARM BOOLEAN Alarm for sustained diff currents in all three phases
OPENCT BOOLEAN An open CT was detected
OPENCTAL BOOLEAN Open CT Alarm output signal. Issued after a
delay ...
IDL1 REAL Value of the instantaneous differential current,
phase L1
IDL2 REAL Value of the instantaneous differential current,
phase L2
IDL3 REAL Value of the instantaneous differential current,
phase L3
IDL1MAG REAL Magnitude of fundamental freq. diff. current,
phase L1
IDL2MAG REAL Magnitude of fundamental freq. diff. current,
phase L2
IDL3MAG REAL Magnitude of fundamental freq. diff. current,
phase L3
IBIAS REAL Magnitude of the bias current, which is common
to all phases
IDNSMAG REAL Magnitude of the negative sequence differential
current

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Table 69: T3WPDIF Input signals


Name Type Default Description
I3PW1CT1 GROUP - Three phase winding primary CT1
SIGNAL
I3PW1CT2 GROUP - Three phase winding primary CT2
SIGNAL
I3PW2CT1 GROUP - Three phase winding secondary CT1
SIGNAL
I3PW2CT2 GROUP - Three phase winding secondary CT2
SIGNAL
I3PW3CT1 GROUP - Three phase winding tertiary CT1
SIGNAL
I3PW3CT2 GROUP - Three phase winding tertiary CT2
SIGNAL
TAPOLTC1 INTEGER 1 Most recent tap position reading on OLTC 1
TAPOLTC2 INTEGER 1 Most recent tap position reading on OLTC 2
OLTC1AL BOOLEAN 0 OLTC1 alarm
OLTC2AL BOOLEAN 0 OLTC2 alarm
BLOCK BOOLEAN 0 Block of function
BLKRES BOOLEAN 0 Block of trip for restrained differential feature
BLKUNRES BOOLEAN 0 Block of trip for unrestrained differential feature
BLKNSUNR BOOLEAN 0 Block of trip for unrestr. neg. seq. differential
feature
BLKNSSEN BOOLEAN 0 Block of trip for sensitive neg. seq. differential
feature

Table 70: T3WPDIF Output signals


Name Type Description
TRIP BOOLEAN General, common trip signal
TRIPRES BOOLEAN Trip signal from restrained differential protection
TRIPUNRE BOOLEAN Trip signal from unrestrained differential protection
TRNSUNR BOOLEAN Trip signal from unrestr. neg. seq. diff. protection
TRNSSENS BOOLEAN Trip signal from sensitive neg. seq. diff. protection
START BOOLEAN Common start signal from any phase
STL1 BOOLEAN Start signal from phase L1
STL2 BOOLEAN Start signal from phase L2
STL3 BOOLEAN Start signal from phase L3
BLK2H BOOLEAN Common second harmonic block signal from any
phase
BLK2HL1 BOOLEAN Second harmonic block signal, phase L1
BLK2HL2 BOOLEAN Second harmonic block signal, phase L2
BLK2HL3 BOOLEAN Second harmonic block signal, phase L3
BLK5H BOOLEAN Common fifth harmonic block signal from any
phase
Table continues on next page

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Differential protection

Name Type Description


BLK5HL1 BOOLEAN Fifth harmonic block signal, phase L1
BLK5HL2 BOOLEAN Fifth harmonic block signal, phase L2
BLK5HL3 BOOLEAN Fifth harmonic block signal, phase L3
BLKWAV BOOLEAN Common block signal, waveform criterion, from
any phase
BLKWAVL1 BOOLEAN Block signal, waveform criterion, phase L1
BLKWAVL2 BOOLEAN Block signal, waveform criterion, phase L2
BLKWAVL3 BOOLEAN Block signal, waveform criterion, phase L3
IDALARM BOOLEAN Alarm for sustained diff currents in all three phases
OPENCT BOOLEAN An open CT was detected
OPENCTAL BOOLEAN Open CT Alarm output signal. Issued after a
delay ...
IDL1 REAL Value of the instantaneous differential current,
phase L1
IDL2 REAL Value of the instantaneous differential current,
phase L2
IDL3 REAL Value of the instantaneous differential current,
phase L3
IDL1MAG REAL Magnitude of fundamental freq. diff. current,
phase L1
IDL2MAG REAL Magnitude of fundamental freq. diff. current,
phase L2
IDL3MAG REAL Magnitude of fundamental freq. diff. current,
phase L3
IBIAS REAL Magnitude of the bias current, which is common
to all phases
IDNSMAG REAL Magnitude of the negative sequence differential
current

5.2.5 Setting parameters


Table 71: T2WPDIF Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation Off / On
On
SOTFMode Off - - On Operation mode for switch onto fault
On
tAlarmDelay 0.000 - 60.000 s 0.001 10.000 Time delay for diff currents alarm level
IDiffAlarm 0.05 - 1.00 IB 0.01 0.20 Dif. cur. alarm, multiple of base curr,
usually W1 curr.
IdMin 0.05 - 0.60 IB 0.01 0.30 Section1 sensitivity, multi. of base curr,
usually W1 curr.
IdUnre 1.00 - 50.00 IB 0.01 10.00 Unrestr. prot. limit, multiple of Winding 1
rated current
Table continues on next page

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Differential protection

Name Values (Range) Unit Step Default Description


CrossBlockEn Off - - On Operation Off/On for cross-block logic
On between phases
NegSeqDiffEn Off - - On Operation Off/On for neg. seq.
On differential protections
IMinNegSeq 0.02 - 0.20 IB 0.01 0.04 Neg. seq. curr. must be higher than this
level to be used
NegSeqROA 30.0 - 120.0 Deg 0.1 60.0 Operate Angle for int. / ext. neg. seq.
fault discriminator

Table 72: T2WPDIF Group settings (advanced)


Name Values (Range) Unit Step Default Description
EndSection1 0.20 - 1.50 IB 0.01 1.25 End of section 1, multiple of Winding 1
rated current
EndSection2 1.00 - 10.00 IB 0.01 3.00 End of section 2, multiple of Winding 1
rated current
SlopeSection2 10.0 - 50.0 % 0.1 40.0 Slope in section 2 of operate-restrain
characteristic, in %
SlopeSection3 30.0 - 100.0 % 0.1 80.0 Slope in section 3 of operate-restrain
characteristic, in %
I2/I1Ratio 5.0 - 100.0 % 0.1 15.0 Max. ratio of 2nd harm. to fundamental
harm dif. curr. in %
I5/I1Ratio 5.0 - 100.0 % 0.1 25.0 Max. ratio of 5th harm. to fundamental
harm dif. curr. in %
OpenCTEnable Off - - Off Open CT detection feature. Open
On CTEnable Off/On
tOCTAlarmDelay 0.100 - 10.000 s 0.001 3.000 Open CT: time in s to alarm after an
open CT is detected
tOCTResetDelay 0.100 - 10.000 s 0.001 0.250 Reset delay in s. After delay, diff.
function is activated
tOCTUnrstDelay 0.10 - 6000.00 s 0.01 10.00 Unrestrained diff. protection blocked
after this delay, in s

Table 73: T2WPDIF Non group settings (basic)


Name Values (Range) Unit Step Default Description
RatedVoltageW1 0.05 - 2000.00 kV 0.05 400.00 Rated voltage of transformer winding 1
(HV winding) in kV
RatedVoltageW2 0.05 - 2000.00 kV 0.05 231.00 Rated voltage of transformer winding 2
in kV
RatedCurrentW1 1 - 99999 A 1 577 Rated current of transformer winding 1
(HV winding) in A
RatedCurrentW2 1 - 99999 A 1 1000 Rated current of transformer winding 2 in
A
ConnectTypeW1 WYE (Y) - - WYE (Y) Connection type of winding 1: Y-wye or D-
Delta (D) delta
ConnectTypeW2 WYE (Y) - - WYE (Y) Connection type of winding 2: Y-wye or D-
Delta (D) delta
Table continues on next page

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Differential protection

Name Values (Range) Unit Step Default Description


ClockNumberW2 0 [0 deg] - - 0 [0 deg] Phase displacement between W2 &
1 [30 deg lag] W1=HV winding, hour notation
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ZSCurrSubtrW1 Off - - On Enable zer. seq. current subtraction for
On W1 side, On / Off
ZSCurrSubtrW2 Off - - On Enable zer. seq. current subtraction for
On W2 side, On / Off
TconfigForW1 No - - No Two CT inputs (T-config.) for winding 1,
Yes YES / NO
CT1RatingW1 1 - 99999 A 1 3000 CT primary rating in A, T-branch 1, on
transf. W1 side
CT2RatingW1 1 - 99999 A 1 3000 CT primary in A, T-branch 2, on transf.
W1 side
TconfigForW2 No - - No Two CT inputs (T-config.) for winding 2,
Yes YES / NO
CT1RatingW2 1 - 99999 A 1 3000 CT primary rating in A, T-branch 1, on
transf. W2 side
CT2RatingW2 1 - 99999 A 1 3000 CT primary rating in A, T-branch 2, on
transf. W2 side
LocationOLTC1 Not Used - - Not Used Transformer winding where OLTC1 is
Winding 1 (W1) located
Winding 2 (W2)
LowTapPosOLTC1 0 - 10 - 1 1 OLTC1 lowest tap position designation
(e.g. 1)
RatedTapOLTC1 1 - 100 - 1 6 OLTC1 rated tap/mid-tap position
designation (e.g. 6)
HighTapPsOLTC1 1 - 100 - 1 11 OLTC1 highest tap position designation
(e.g. 11)
TapHighVoltTC1 1 - 100 - 1 1 OLTC1 end-tap position with winding
highest no-load voltage
StepSizeOLTC1 0.01 - 30.00 % 0.01 1.00 Voltage change per OLTC1 step in
percent of rated voltage

Table 74: T3WPDIF Group settings (basic)


Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation Off / On
On
SOTFMode Off - - On Operation mode for switch onto fault
On feature
tAlarmDelay 0.000 - 60.000 s 0.001 10.000 Time delay for diff currents alarm level
Table continues on next page

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Differential protection

Name Values (Range) Unit Step Default Description


IDiffAlarm 0.05 - 1.00 IB 0.01 0.20 Dif. cur. alarm, multiple of base curr,
usually W1 curr.
IdMin 0.05 - 0.60 IB 0.01 0.30 Section1 sensitivity, multi. of base curr,
usually W1 curr.
IdUnre 1.00 - 50.00 IB 0.01 10.00 Unrestr. prot. limit, multi. of base curr.
usually W1 curr.
CrossBlockEn Off - - On Operation Off/On for cross-block logic
On between phases
NegSeqDiffEn Off - - On Operation Off/On for neg. seq.
On differential protections
IMinNegSeq 0.02 - 0.20 IB 0.01 0.04 Neg. seq. curr. limit, mult. of base curr,
usually W1 curr.
NegSeqROA 30.0 - 120.0 Deg 0.1 60.0 Operate Angle for int. / ext. neg. seq.
fault discriminator

Table 75: T3WPDIF Group settings (advanced)


Name Values (Range) Unit Step Default Description
EndSection1 0.20 - 1.50 IB 0.01 1.25 End of section 1, multi. of base current,
usually W1 curr.
EndSection2 1.00 - 10.00 IB 0.01 3.00 End of section 2, multi. of base current,
usually W1 curr.
SlopeSection2 10.0 - 50.0 % 0.1 40.0 Slope in section 2 of operate-restrain
characteristic, in %
SlopeSection3 30.0 - 100.0 % 0.1 80.0 Slope in section 3 of operate-restrain
characteristic, in %
I2/I1Ratio 5.0 - 100.0 % 0.1 15.0 Max. ratio of 2nd harm. to fundamental
harm dif. curr. in %
I5/I1Ratio 5.0 - 100.0 % 0.1 25.0 Max. ratio of 5th harm. to fundamental
harm dif. curr. in %
OpenCTEnable Off - - Off Open CT detection feature. Open
On CTEnable Off/On
tOCTAlarmDelay 0.100 - 10.000 s 0.001 3.000 Open CT: time in s to alarm after an
open CT is detected
tOCTResetDelay 0.100 - 10.000 s 0.001 0.250 Reset delay in s. After delay, diff.
function is activated
tOCTUnrstDelay 0.10 - 6000.00 s 0.01 10.00 Unrestrained diff. protection blocked
after this delay, in s

Table 76: T3WPDIF Non group settings (basic)


Name Values (Range) Unit Step Default Description
RatedVoltageW1 0.05 - 2000.00 kV 0.05 400.00 Rated voltage of transformer winding 1
(HV winding) in kV
RatedVoltageW2 0.05 - 2000.00 kV 0.05 231.00 Rated voltage of transformer winding 2
in kV
RatedVoltageW3 0.05 - 2000.00 kV 0.05 10.50 Rated voltage of transformer winding 3
in kV
Table continues on next page

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Differential protection

Name Values (Range) Unit Step Default Description


RatedCurrentW1 1 - 99999 A 1 577 Rated current of transformer winding 1
(HV winding) in A
RatedCurrentW2 1 - 99999 A 1 1000 Rated current of transformer winding 2 in
A
RatedCurrentW3 1 - 99999 A 1 7173 Rated current of transformer winding 3 in
A
ConnectTypeW1 WYE (Y) - - WYE (Y) Connection type of winding 1: Y-wye or D-
Delta (D) delta
ConnectTypeW2 WYE (Y) - - WYE (Y) Connection type of winding 2: Y-wye or D-
Delta (D) delta
ConnectTypeW3 WYE (Y) - - Delta (D) Connection type of winding 3: Y-wye or D-
Delta (D) delta
ClockNumberW2 0 [0 deg] - - 0 [0 deg] Phase displacement between W2 &
1 [30 deg lag] W1=HV winding, hour notation
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ClockNumberW3 0 [0 deg] - - 5 [150 deg lag] Phase displacement between W3 &
1 [30 deg lag] W1=HV winding, hour notation
2 [60 deg lag]
3 [90 deg lag]
4 [120 deg lag]
5 [150 deg lag]
6 [180 deg]
7 [150 deg lead]
8 [120 deg lead]
9 [90 deg lead]
10 [60 deg lead]
11 [30 deg lead]
ZSCurrSubtrW1 Off - - On Enable zer. seq. current subtraction for
On W1 side, On / Off
ZSCurrSubtrW2 Off - - On Enable zer. seq. current subtraction for
On W2 side, On / Off
ZSCurrSubtrW3 Off - - On Enable zer. seq. current subtraction for
On W3 side, On / Off
TconfigForW1 No - - No Two CT inputs (T-config.) for winding 1,
Yes YES / NO
CT1RatingW1 1 - 99999 A 1 3000 CT primary rating in A, T-branch 1, on
transf. W1 side
CT2RatingW1 1 - 99999 A 1 3000 CT primary in A, T-branch 2, on transf.
W1 side
TconfigForW2 No - - No Two CT inputs (T-config.) for winding 2,
Yes YES / NO
CT1RatingW2 1 - 99999 A 1 3000 CT primary rating in A, T-branch 1, on
transf. W2 side
CT2RatingW2 1 - 99999 A 1 3000 CT primary rating in A, T-branch 2, on
transf. W2 side
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Name Values (Range) Unit Step Default Description


TconfigForW3 No - - No Two CT inputs (T-config.) for winding 3,
Yes YES / NO
CT1RatingW3 1 - 99999 A 1 3000 CT primary rating in A, T-branch 1, on
transf. W3 side
CT2RatingW3 1 - 99999 A 1 3000 CT primary rating in A, T-branch 2, on
transf. W3 side
LocationOLTC1 Not Used - - Not Used Transformer winding where OLTC1 is
Winding 1 (W1) located
Winding 2 (W2)
Winding 3 (W3)
LowTapPosOLTC1 0 - 10 - 1 1 OLTC1 lowest tap position designation
(e.g. 1)
RatedTapOLTC1 1 - 100 - 1 6 OLTC1 rated tap/mid-tap position
designation (e.g. 6)
HighTapPsOLTC1 1 - 100 - 1 11 OLTC1 highest tap position designation
(e.g. 11)
TapHighVoltTC1 1 - 100 - 1 1 OLTC1 end-tap position with winding
highest no-load voltage
StepSizeOLTC1 0.01 - 30.00 % 0.01 1.00 Voltage change per OLTC1 step in
percent of rated voltage
LocationOLTC2 Not Used - - Not Used Transformer winding where OLTC2 is
Winding 1 (W1) located
Winding 2 (W2)
Winding 3 (W3)
LowTapPosOLTC2 0 - 10 - 1 1 OLTC2 lowest tap position designation
(e.g. 1)
RatedTapOLTC2 1 - 100 - 1 6 OLTC2 rated tap/mid-tap position
designation (e.g. 6)
HighTapPsOLTC2 1 - 100 - 1 11 OLTC2 highest tap position designation
(e.g. 11)
TapHighVoltTC2 1 - 100 - 1 1 OLTC2 end-tap position with winding
highest no-load voltage
StepSizeOLTC2 0.01 - 30.00 % 0.01 1.00 Voltage change per OLTC2 step in
percent of rated voltage

5.2.6 Technical data


Table 77: T2WPDIF, T3WPDIF technical data
Function Range or value Accuracy
Operating characteristic Adaptable ± 1.0% of Ir for I < Ir
± 1.0% of Ir for I > Ir
Reset ratio >95% -
Unrestrained differential current limit (100-5000)% ofIBase ± 1.0% of set value
on high voltage winding
Base sensitivity function (10-60)% of IBase ± 1.0% of Ir
Second harmonic blocking (5.0-100.0)% of ± 2.0% of Ir
fundamental differential
current
Table continues on next page

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Differential protection

Function Range or value Accuracy


Fifth harmonic blocking (5.0-100.0)% of ± 5.0% of Ir
fundamental differential
current
Connection type for each of the windings Y or D -
Phase displacement between high voltage 0–11 -
winding, W1 and each of the windings, W2
and W3. Hour notation
Operate time, restrained function 25 ms typically at 0 to -
2 x Ib
Reset time, restrained function 20 ms typically at 2 to -
0 x Ib
Operate time, unrestrained function 12 ms typically at 0 to -
5 x Ib
Reset time, unrestrained function 25 ms typically at 5 to -
0 x Ib
Critical impulse time 2 ms typically at 0 to 5 -
x Ib

5.3 Restricted earth fault protection, low impedance


REFPDIF

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Restricted earth fault protection, low REFPDIF 87N
impedance
IdN/I

SYMBOL-AA V1 EN

5.3.1 Introduction
Restricted earth-fault protection, low-impedance function (REFPDIF) can be used
on all directly or low-impedance earthed windings. The REFPDIF function
provides high sensitivity (down to 5%) and high speed tripping as it measures each
winding individually and thus does not need inrush stabilization.

The low-impedance function is a percentage biased function with an additional


zero sequence current directional comparison criterion. This gives excellent
sensitivity and stability during through faults. The function allows the use of
different CT ratios and magnetizing characteristics on the phase and neutral CT
cores and mixing with other functions and protection IEDs on the same cores.

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5.3.2 Principle of operation

5.3.2.1 Fundamental principles of the restricted earthfault protection

Restricted earth-fault protection, low impedance function (REFPDIF) must detect


earth faults on earthed power transformer windings. REFPDIF is a unit protection
of differential type. Since REFPDIF is based on the zero sequence currents, which
theoretically only exist in case of an earth-fault, the REFPDIF can be made very
sensitive; regardless of normal load currents. It is the fastest protection a power
transformer winding can have. It must be borne in mind, however, that the high
sensitivity, and the high speed, tend to make such a protection instable, and special
measures must be taken to make it insensitive to conditions, for which it should not
operate, for example heavy through faults of phase-to-phase type, or heavy external
earth faults.

REFPDIF is of “low impedance” type. All three phase power transformer terminal
currents, and the power transformer neutral point current, must be fed separately to
REFPDIF . These input currents are then conditioned within REFPDIF by
mathematical tools.

Fundamental frequency components of all currents are extracted from all input
currents, while other eventual zero sequence components (for example, the 3rd
harmonic currents) are fully suppressed. Then the residual current phasor is
constructed from the three line current phasors. This zero sequence current phasor
is then vectorially added to the neutral current, in order to obtain differential current.

The following facts may be observed from the figure 75 and the figure 76 (where
the three-phase line CTs are lumped into a single 3Io current, for the sake of
simplicity).

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zone of protection

s Izs1 Ia = 0
o L1 L1
u Izs1 Ib = 0
L2 L2
r
c Izs1 Ic = 0
L3 L3
e
Uzs Current in the neutral (IN)
3Io=3I zs1 IN = -3Izs1 IN serves as a directional
reference because it has
the same direction for both
internal and external faults.

Uzs voltage is max. REFPDIF is a current polarized


at the earth-fault For external fault function
ROA RCA (Relay Characteristic Angle)
RCA = 0 deg.
3I0
REFPDIF is permanently set to
MTA
IN operate for internal earth-faults.
Reference is
ROA REFPDIF should never operate
neutral current
for any faults external to
the protected zone.
Restrain for Operate for Currents 3Io and IN are theoretically
external fault internal fault 180o out of phase for any external
earth-fault.

IEC09000107-1-en.vsd
IEC09000107 V1 EN

Figure 75: Currents at an external earth-fault

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power system
contribution to
fault current zone of protection

s Izs2 Izs1 Ia = 0
o L1 L1
u Izs2 Izs1
L2 Ib = 0 L2
r
c Izs2 Izs1 Ic = 0
e L3 L3

Ifault Current in the neutral (IN)


Uz serves as a directional
3Io = -3Izs2 IN
s reference because it has
the same direction for both
IN = - 3Izs1 internal and external faults.

Return path for 3Izs2 Return path for 3Izs1

currents 3Io and IN are approximately


For internal fault in phase for an internal earth-fault.
ROA 3I0

MTA
IN
Reference is
ROA
neutral current

Restrain for Operate for


external fault internal fault
IEC09000108-1-en.vsd
IEC09000108 V1 EN

Figure 76: Currents at an internal earth fault

1. For an external earth fault, (figure 75) the residual current 3Io and the neutral
conductor current IN have equal magnitude, but they are 180 degree out-of-
phase due to internal CT reference directions used in the IED. This is easy to
understand, as both CTs ideally measure exactly the same component of the
earth fault current.
2. For an internal fault, the total earth-fault current is composed generally of two
zero sequence components. One zero sequence component (that is, 3IZS1)
flows towards the power transformer neutral point and into the earth, while the
other zero sequence component (that is, 3IZS2) flows out into the connected
power system. These two primary currents can be expected to be of
approximately opposite directions (about the same zero sequence impedance
angle is assumed on both sides of the earth-fault). However, on the secondary
CT sides they will be approximately in phase due to internal CT reference
directions used in the IED. The magnitudes of the two components may be
different, dependent on the magnitudes of zero sequence impedances of both
sides. No current can flow towards the power system, if the only point where
the system is earthed, is at the protected power transformer. Likewise, no
current can flow into the power system, if the winding is not connected to the

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power system (circuit breaker open and power transformer energized from the
other side).
3. For both internal and external earth faults, the current in the neutral connection
IN has always the same direction, that is, towards the earth.
4. The two measured zero sequence current are 3Io and IN. The vectorial sum
between them is the REFPDIF differential current, which is equal to Idiff = IN
+3Io.

Since REFPDIF is a differential protection where the line zero sequence (residual)
current is constructed from 3 line (terminal) currents, a bias quantity must give
stability against false operations due to high through fault currents. An operate -
bias characteristic (only one) has been devised to the purpose.

It is not only external earth faults that REFPDIF should be stable against, but also
heavy phase-to-phase faults, not including earth. These faults may also give rise to
false zero sequence currents due to saturated line CTs. Such faults, however,
produce no neutral current, and can thus be eliminated as a source of danger, at
least during the fault.

As an additional measure against unwanted operation, a directional check is made


in agreement with the above points 1, and 2. An operation is only allowed if
currents 3Io and IN (as shown in figure 75 and the figure 76) are both within the
operating region. By taking a smaller ROA, REFPDIF can be made more stable
under heavy external fault conditions, as well as under the complex conditions,
when external faults are cleared by other protections.

5.3.2.2 Restricted earth-fault protection, low impedance as a differential


protection

Restricted earth-fault protection, low impedance (REFPDIF) is a protection of


differential type, a unit protection, whose settings are independent of any other
protection. Compared to the transformer differential protection it has some
advantages. It is simpler, as no current phase correction and magnitude correction
are needed, not even in the case of an eventual On-Load Tap-Changer (OLTC).
REFPDIF is not sensitive to inrush and overexcitation currents. The only danger
left is an eventual current transformer saturation.

REFPDIF has only one operate-bias characteristic, which is described in the table
78, and shown in the figure 77.

Table 78: Data of the operate - bias characteristic of REFPDIF


Default sensitivity Max. base Min. base sensitivity End of zone First slope Second
Idmin (zone 1) sensitivity Idmin Idmin (zone 1) 1 slope
(zone 1)
% IBase % IBase % IBase % IBase % %
30 4 100 125 70 100

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As a differential protection, REFPDIF calculates a differential current and a bias


current. In case of internal earth-faults, the differential current is theoretically equal
to the total earth-fault current. The bias current is supposed to give stability to
REFPDIF . The bias current is a measure of how high the currents are, or better, a
measure of how difficult the conditions are under which the CTs operate. The
higher the bias, the more difficult conditions can be suspected, and the more likely
that the calculated differential current has a component of a false current, primarily
due to CT saturation. This “law” is formulated by the operate-bias characteristic.
This characteristic divides the Idiff - Ibias plane into two parts. The part above the
operate - bias characteristic is the so called operate area, while that below is the
block area, see the figure 77.

operate current in pu

4 operate

Base Sensitivity Idmin


3
*************************************
Range : 5 % to 50 % rated current
Step : 1 % transformer rated current
2
zone 1 zone 2 second slope

1
minimum base sensitivity 50 %
default base sensitivity 30 % first slope block
maximum base sensitivity 5 %
0 1 2 3 4 5 6

1.25 pu bias current in per unit

IEC98000017-2-en.vsd

IEC98000017 V3 EN

Figure 77: Operate - bias characteristic of the Restricted earth-fault


protection, low impedance REFPDIF

5.3.2.3 Calculation of differential current and bias current

The differential current, (= operate current), as a fundamental frequency phasor, is


calculated as (with designations as in the figure 75 and the figure 76)

Idiff = IN + 3 Io
EQUATION1533 V1 EN (Equation 30)

where:
IN current in the power transformer neutral as a fundamental frequency phasor,

3Io residual current of the power transformer line (terminal) currents as a phasor.

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If there are two three-phase CT inputs on the HV winding side for REFPDIF (such
as in breaker-and-a-half configurations), then their respective residual currents are
added within REFPDIF function so that:

I3PW1 = I3PW1CT1 + I3PW1CT2

where the signals are defined in the input and output signal tables for REFPDIF.

The bias current is a measure (expressed as a current in Amperes) of how difficult


the conditions are under which the instrument current transformers operate.
Dependent on the magnitude of the bias current, the corresponding zone (section)
of the operate - bias characteristic is applied, when deciding whether “to trip, or
“not to trip”. In general, the higher the bias current, the higher the differential
current required to produce a trip.

As the bias current the highest current of all separate input currents to REFPDIF,
that is, of current in phase L1, phase L2, phase L3, and the current in the neutral
point (designated as IN in the figure 75 and in the figure 76).

If there are 2 feeders included in the zone of protection of REFPDIF, then the
respective bias current is found as the relatively highest of the following currents:

1
current[1] = max (I3PW1CT1) ×
CTFactorPri1
EQUATION1526 V1 EN (Equation 31)

1
current[2] = max (I3PW1CT2) ×
CTFactorPri2
EQUATION1527 V1 EN (Equation 32)

1
current[3] = max (I3PW2CT1) ×
CTFactorSec1
EQUATION1528 V1 EN (Equation 33)

1
current[4] = max (I3PW2CT2) ×
CTFactorSec2
EQUATION1529 V1 EN (Equation 34)

current[5] = IN
EQUATION1530 V1 EN (Equation 35)

The bias current is thus generally equal to none of the input currents. If all primary
ratings of the CTs were equal to IBase, then the bias current would be equal to the
highest current in Amperes. IBase shall be set equal to the rated current of the
protected winding where REFPDIF function is applied.

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5.3.2.4 Detection of external earth faults

External faults are more common than internal earth faults for which the restricted
earth fault protection should operate. It is important that the restricted earth fault
protection remains stable during heavy external earth and phase-to-phase faults,
and also when such a heavy external fault is cleared by some other protection such
as overcurrent, or earth-fault protection, and so on. The conditions during a heavy
external fault, and particularly immediately after the clearing of such a fault may be
complex. The circuit breaker’s poles may not open exactly at the same moment,
some of the CTs may still be highly saturated, and so on.

The detection of external earth faults is based on the fact that for such a fault a high
neutral current appears first, while a false differential current only appears if and
when one, or more, current transformers saturate.

An external earth fault is thus assumed to have occurred when a high neutral
current suddenly appears, while at the same time the differential current Idiff
remains low, at least for a while. This condition must be detected before a trip
request is placed within REFPDIF. Any search for external fault is aborted if a trip
request has been placed. A condition for a successful detection is that it takes not
less than 4ms for the first CT to saturate.

For an internal earth fault, a true differential current develops immediately, while
for an external fault it only develops if a CT saturates. If a trip request comes first,
before an external fault could be positively established, then it must be an internal
fault.

If an external earth fault has been detected, then the REFPDIF is temporarily
desensitized.

Directional criterion
The directional criterion is applied in order to positively distinguish between
internal- and external earth faults. This check is an additional criterion, which
should prevent malfunctions at heavy external earth faults, and during the
disconnection of such faults by other protections. Earth faults on lines connecting
the power transformer occur much more often than earth faults on a power
transformer winding. It is important therefore that the Restricted earth faults
protection, low impedance (REFPDIF,) must remain secure during an external
fault, and immediately after the fault has been cleared by some other protection.

For an external earth faults with no CT saturation, the residual current in the lines
(3Io) and the neutral current (IN in the figure 75) are theoretically equal in
magnitude and are 180 degree out-of-phase. It is the current in the neutral (IN)
which serves as a directional reference because it flows for all earth faults, and it
has the same direction for all earth faults, both external and internal. The
directional criterion in REFPDIF protection makes it a current-polarized IED.

If one or more CTs saturate, then the measured currents 3Io and IN may no more be
equal, nor will their positions in the complex plane be exactly 180 degree apart.
There is a risk that the resulting false differential current Idiff enters the operate

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area when clearing the external fault. If this happens, a directional test may prevent
a malfunction.

A directional check is only executed if:

1. a trip request signal has been issued, REFPDIF function START signal set to 1)
2. if the residual current in lines (3Io) is at least 3% of the IBase current.

If a directional check is either unreliable or not possible to do, due to too small
currents, then the direction is cancelled as a condition for an eventual trip.

If a directional check is executed, the REFPDIF protection operation is only


allowed if currents 3Io and IN (as seen in figure 75 and figure 76) are both within
the operating region.

RCA = 0 degrees = constant; where RCA stands for Relay Characteristic Angle
ROA = 60 to 90 degrees; where ROA stands for Relay Operate Angle.

RCA determines a direction MTA (“Maximum Torque Angle”) where the line
residual current 3Io must lie for an internal earth fault, while ROA sets a tolerance
margin.

Second harmonic analysis


At energizing of a reactor a false differential current may appear in Restricted earth-
fault protection, low impedance function (REFPDIF,) even though it does not exist
in the primary net. The phase CT’s may saturate due to a high dc-component with
long duration where as the current through the neutral CT does not have either the
same dc-component or the same amplitude and the risk for saturation in this CT is
not as high. The appearing differential current as a result of the saturation may be
so high that it reaches the operate characteristic. A calculation of the content of 2nd
harmonic in the neutral current is made when neutral current, residual current and
bias current are within some windows and some timing criteria are fulfilled. If the
ratio between second and fundamental harmonic exceeds 60%, REFPDIF must be
blocked.

5.3.2.5 Algorithm of the restricted earth fault protection

1. Check if current in the neutral Ineutral (IN) is less than 50% of the base
sensitivity Idmin. If yes, only service values are calculated, then REFPDIF
algorithm is exited.
2. If current in the Ineutral (IN) is more than 50% of Idmin, then determine the
bias current Ibias.
3. Determine the differential (operate) current Idiff as a phasor, and calculate its
magnitude.
4. Check if the point P(Ibias, Idiff) is above the operate - bias characteristic. If
yes, increment the trip request counter by 1. If the point P(Ibias, Idiff) is found
to be below the operate - bias characteristic, then the trip request counter is
reset to 0.

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5. If the trip request counter is still 0, search for an eventual heavy external earth
fault. The search is only made if the neutral current is at least 50% of the IBase
current. If an external earth fault has been detected, a flag is set which remains
set until the external fault has been cleared. The external fault flag is reset to 0
when Ineutral falls below 50% of the base sensitivity Idmin. Any search for
external fault is aborted if trip request counter is more than 0.
6. For as long as the external fault persists an additional temporary trip condition
is introduced. That means that REFPDIF is temporarily desensitized.
7. If point P(Ibias, Idiff) is found to be above the operate - bias characteristic), so
that trip request counter is becomes more than 0, a directional check can be
made. The directional check is made only if Iresidual (3Io) is more than 3% of
the IBase current. If the result of the check means “external fault”, then the
internal trip request is reset. If the directional check cannot be executed, then
direction is no longer a condition for a trip.
8. When neutral current, residual current and bias current are within some
windows and some timing criteria are fulfilled, the ratio of 2nd to fundamental
tone is calculated. If it is found to be above 60% the trip request counter is
reset and TRIP remains zero.
9. Finally, a check is made if the trip request counter is equal to, or higher than 2.
If it is, and that at the same instance of time tREFtrip, the actual bias current at
this instance of time tREFtrip is at least 50% of the highest bias current Ibiasmax
(Ibiasmax is the highest recording of any of the three phase currents measured
during the disturbance) then REFPDIF sets output TRIP to 1. If the counter is
less than 2, TRIP signal remains 0.

5.3.3 Function block


REFPDIF
I3P* TRIP
I3PW1CT1* START
I3PW1CT2* DIROK
I3PW2CT1* BLK2H
I3PW2CT2* IRES
BLOCK IN
IBIAS
IDIFF
ANGLE
I2RATIO

IEC06000251_2_en.vsd
IEC06000251 V2 EN

Figure 78: REFPDIF function block

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Differential protection

5.3.4 Input and output signals


Table 79: REFPDIF Input signals
Name Type Default Description
I3P GROUP - Group signal for neutral current input
SIGNAL
I3PW1CT1 GROUP - Group signal for primary CT1 current input
SIGNAL
I3PW1CT2 GROUP - Group signal for primary CT2 current input
SIGNAL
I3PW2CT1 GROUP - Group signal for secondary CT1 current input
SIGNAL
I3PW2CT2 GROUP - Group signal for secondary CT2 current input
SIGNAL
BLOCK BOOLEAN 0 Block of function

Table 80: REFPDIF Output signals


Name Type Description
TRIP BOOLEAN Trip by restricted earth fault protection function
START BOOLEAN Start by restricted earth fault protection function
DIROK BOOLEAN Directional Criteria has operated for internal fault
BLK2H BOOLEAN Block due to 2-nd harmonic
IRES REAL Magnitude of fund. freq. residual current
IN REAL Magnitude of fund. freq. neutral current
IBIAS REAL Magnitude of the bias current
IDIFF REAL Magnitude of fund. freq. differential current
ANGLE REAL Direction angle from zerosequence feature
I2RATIO REAL Second harmonic ratio

5.3.5 Setting parameters


Table 81: REFPDIF Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation Off / On
On
IBase 1 - 99999 A 1 3000 Base current
IdMin 4.0 - 100.0 %IB 0.1 10.0 Maximum sensitivity in % of Ibase
CTFactorPri1 1.0 - 10.0 - 0.1 1.0 CT factor for HV side CT1 (CT1rated/
HVrated current)
CTFactorPri2 1.0 - 10.0 - 0.1 1.0 CT factor for HV side CT2 (CT2rated/
HVrated current)
CTFactorSec1 1.0 - 10.0 - 0.1 1.0 CT factor for MV side CT1 (CT1rated/
MVrated current)
CTFactorSec2 1.0 - 10.0 - 0.1 1.0 CT factor for MV side CT2 (CT2rated/
MVrated current)

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Table 82: REFPDIF Group settings (advanced)


Name Values (Range) Unit Step Default Description
ROA 60 - 90 Deg 1 60 Relay operate angle for zero sequence
directional feature

5.3.6 Technical data


Table 83: REFPDIF technical data
Function Range or value Accuracy
Operate characteristic Adaptable ± 1.0% of Ir for I < IBase
± 1.0% of I for I > IBase
Reset ratio >95% -
Base sensitivity function (4.0-100.0)% of IBase ± 1.0% of Ir

Directional characteristic Fixed 180 degrees or ± 60 to ± ± 2.0 degree


90 degrees
Operate time, trip function 20 ms typically at 0 to 10 x IdMin -
Reset time, trip function 25 ms typically at 10 to 0 x IdMin -
Second harmonic blocking (5.0-100.0)% of fundamental ± 2.0% of IrBase

5.4 1Ph High impedance differential protection HZPDIF

5.4.1 Identification
IEC 61850 IEC 60617 ANSI/IEEE C37.2
Function description
identification identification device number

1Ph High impedance differential Id


HZPDIF 87
protection

SYMBOL-CC V2 EN

5.4.2 Introduction
The 1Ph High impedance differential protection (HZPDIF) function can be used
when the involved CT cores have the same turns ratio and similar magnetizing
characteristics. It utilizes an external CT current summation by wiring, a series
resistor, and a voltage dependent resistor which are mounted externally connected
to the IED.

HZPDIF can be used to protect generator stator windings, tee-feeders or busbars.


Six single phase function blocks are available to allow application for two three-
phase zones busbar protection.

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Differential protection

5.4.3 Principle of operation


The 1Ph High impedance differential protection (HZPDIF) function is based on
one current input with external stabilizing resistors and voltage dependent resistors.
Three functions can be used to provide a three phase differential protection
function. The stabilizing resistor value is calculated from the IED function
operating value UR calculated to achieve through fault stability. The supplied
stabilizing resistor has a link to allow setting of the correct resistance value .

See the application manual for operating voltage and sensitivity calculation.

5.4.3.1 Logic diagram

The logic diagram shows the operation principles for the 1Ph High impedance
differential protection function HZPDIF, see figure 79. It is a simple one step IED
function with an additional lower alarm level. By activating inputs, the HZPDIF
function can either be blocked completely, or only the trip output.

IEC05000301 V1 EN

Figure 79: Logic diagram for 1Ph High impedance differential protection
HZPDIF

5.4.4 Function block


HZPDIF
ISI* TRIP
BLOCK ALARM
BLKTR MEASVOLT

IEC05000363-2-en.vsd
IEC05000363 V2 EN

Figure 80: HZPDIF function block

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Differential protection

5.4.5 Input and output signals


Table 84: HZPDIF Input signals
Name Type Default Description
ISI GROUP - Group signal for current input
SIGNAL
BLOCK BOOLEAN 0 Block of function
BLKTR BOOLEAN 0 Block of trip

Table 85: HZPDIF Output signals


Name Type Description
TRIP BOOLEAN Trip signal
ALARM BOOLEAN Alarm signal
MEASVOLT REAL Measured RMS voltage on CT secondary side

5.4.6 Setting parameters


Table 86: HZPDIF Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation Off / On
On
U>Alarm 2 - 500 V 1 10 Alarm voltage level in volts on CT
secondary side
tAlarm 0.000 - 60.000 s 0.001 5.000 Time delay to activate alarm
U>Trip 5 - 900 V 1 100 Operate voltage level in volts on CT
secondary side
SeriesResistor 10 - 20000 ohm 1 250 Value of series resistor in Ohms

5.4.7 Technical data


Table 87: HZPDIF technical data
Function Range or value Accuracy
Operate voltage (20-400) V ± 1.0% of Ir
I=U/R
Reset ratio >95% -
Maximum U>Trip2/series resistor ≤200 W -
continuous voltage
Operate time 10 ms typically at 0 to 10 x Ud -

Reset time 90 ms typically at 10 to 0 x Ud -

Critical impulse time 2 ms typically at 0 to 10 x Ud -

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1MRK 502 027-UEN A Section 6
Impedance protection

Section 6 Impedance protection

About this chapter


This chapter describes distance protection and associated functions. It includes
function blocks, logic diagrams and data tables with information about distance
protection, automatic switch onto fault, weak end in-feed and other associated
functions.

6.1 Full-scheme distance measuring, Mho


characteristic ZMHPDIS

Function description IEC 61850 IEC 60617 identification ANSI/IEEE


identification C37.2 device
number
Full-scheme distance protection, mho ZMHPDIS 21
characteristic

S00346 V1 EN

6.1.1 Introduction
The numerical mho line distance protection is a, up to four zone full scheme
protection for back-up detection of short circuit and earth faults. The four zones
have fully independent measuring and settings, which gives high flexibility for all
types of lines.

The function can be used as under impedance back-up protection for transformers
and generators.

6.1.2 Principle of operation

6.1.2.1 Full scheme measurement

The execution of the different fault loops within the IED are of full scheme type,
which means that each fault loop for phase-to-earth faults and phase-to-phase faults
are executed in parallel.

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The use of full scheme technique gives faster operation time compared to switched
schemes which mostly uses a start element to select correct voltages and current
depending on fault type. So each distance protection zone performs like one
independent distance protection function with six measuring elements.

6.1.2.2 Impedance characteristic

The distance function consists of four instances. Each instance can be selected to
be either forward or reverse with positive sequence polarized mho characteristic
alternatively self polarized offset mho characteristics with reverse offset. The
operating characteristic is in accordance to figure 81.

jx

Mho, zone4

Mho, zone3
Zs=0
Mho, zone2

R
Mho, zone1

Zs=Z1

R Zs=2Z1

IEC11000223-1-en.vsd
IEC11000223 V1 EN

Figure 81: Mho characteristic and the source impedance influence on the mho characteristic

The mho characteristic has a dynamic expansion due to the source impedance.
Instead of crossing the origin as for the mho to the left of figure 81, which is only
valid where the source impedance is zero, the crossing point is moved to the
coordinates of the negative source impedance given an expansion of the circle
shown to the right of figure 81.

The polarization quantities used for the mho circle are 100% memorized positive
sequence voltages. This will give a somewhat less dynamic expansion of the mho
circle during faults. However, if the source impedance is high, the dynamic
expansion of the mho circle might lower the security of the function too much with
high loading and mild power swing conditions.

The mho distance element has a load encroachment function which cuts off a
section of the characteristic when enabled. The function is enabled by setting the

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Impedance protection

setting parameter LoadEnchMode to On. Enabling of the load encroachment


function increases the possibility to detect high resistive faults without interfering
with the load impedance. The algorithm for the load encroachment is located in the
Faulty phase identification with load encroachment for mho function FMPSPDIS,
where also the relevant settings can be found. Information about the load
encroachment from FMPSPDIS to the zone measurement is given in binary format
to the input signal LDCND.

6.1.2.3 Basic operation characteristics

Each impedance zone can be switched On and Off by the setting parameter
Operation.

Each zone can also be set to Non-directional, Forward or Reverse by setting the
parameter DirMode.

The operation for phase-to-earth and phase-to-phase fault can be individually


switched On and Off by the setting parameter OpModePE and OpModePP.

For critical applications such as for lines with high SIRs as well as CVTs, it is
possible to improve the security by setting the parameter ReachMode to
Underreach. In this mode the reach for faults close to the zone reach is reduced by
20% and the filtering is also introduced to increase the accuracy in the measuring.
If the ReachMode is set to Overreach no reduction of the reach is introduced and
no extra filtering introduced. The latter setting is recommended for overreaching
pilot zone, zone 2 or zone 3 elements and reverse zone where overreaching on
transients is not a major issue either because of less likelihood of overreach with
higher settings or the fact that these elements do not initiate tripping unconditionally.

The offset mho characteristic can be set in Non-directional, Forward or Reverse by


the setting parameter OffsetMhoDir. When Forward or Reverse is selected a
directional line is introduced. Information about the directional line is given from
the directional element and given to the measuring element as binary coded signal
to the input DIRCND.

The zone reach for phase-to-earth fault and phase-to-phase fault is set individually
in polar coordinates.

The impedance is set by the parameters ZPE and ZPP and the corresponding
arguments by the parameters ZAngPE and ZAngPP.

Compensation for earth-return path for faults involving earth is done by setting the
parameter KNMag and KNAng where KNMag is the magnitude of the earth-return
path and KNAng is the difference of angles between KNMag and ZPE.

Z0-Z1
KNMag =
3 × Z1
EQUATION1579 V1 EN (Equation 36)

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Impedance protection

KNAng = arg
( Z 0 - Z1

3 × Z1
)
EQUATION1580 V1 EN (Equation 37)

where
Z0 is the complex zero sequence impedance of the line in Ω/phase
Z1 is the complex positive sequence impedance of the line in Ω/phase

The phase-to-earth and phase-to-phase measuring loops can be time delayed


individually by setting the parameter tPE and tPP respectively. To release the time
delay, the operation mode for the timers, OpModetPE and OpModetPP, has to be
set to On. This is also the case for instantaneous operation.

The function can be blocked in the following ways:

• activating of input BLOCK blocks the whole function


• activating of the input BLKZ (fuse failure) blocks all output signals
• activating of the input BLKZMTD blocks the delta based algorithm
• activating of the input BLKHSIR blocks the instantaneous part of the
algorithm for high SIR values
• activating of the input BLKTRIP blocks all output signals
• activating the input BLKPE blocks the phase-to-earth fault loop outputs
• activating the input BLKPP blocks the phase-to-phase fault loop outputs

The activation of input signal BLKZ can be made by external fuse failure function
or from the loss of voltage check in the Mho supervision logic (ZSMGAPC). In
both cases the output BLKZ in the Mho supervision logic shall be connected to the
input BLKZ in the Mho distance function block (ZMHPDIS)

The input signal BLKZMTD is activated during some ms after fault has been
detected by ZSMGAPC to avoid unwanted operations due to transients. It shall be
connected to the BLKZMTD output signal of ZSMGAPC function.

At SIR values >10, the use of electronic CVT might cause overreach due to the built-
in resonance circuit in the CVT, which reduce the secondary voltage for a while.
The input BLKHSIR shall be connected to the output signal HSIR on ZSMGAPC
for increasing of the filtering and high SIR values. This is valid only when
permissive underreach scheme is selected by setting ReachMode=Underreach.

6.1.2.4 Theory of operation

The mho algorithm is based on the phase comparison of a operating phasor and a
polarizing phasor. When the operating phasor leads the reference polarizing phasor
by more than 90 degrees, the function operates and gives a trip output.

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Phase-to-phase fault

Mho
The plain mho circle has the characteristic as in figure 82. The condition for
deriving the angle β is according to equation 38.

b = arg(U L1 L 2 - I L1 L 2 × ZPP ) - arg(U pol )


EQUATION1789 V1 EN (Equation 38)

where

U L1L2 is the voltage vector difference between phases L1 and L2


EQUATION1790 V2
EN

I L1L2 is the current vector difference between phases L1 and L2


EQUATION1791 V2
EN

ZPP is the positive sequence impedance setting for phase-to-phase fault


Upol is the polarizing voltage

The polarized voltage consists of 100% memorized positive sequence voltage


(UL1L2 for phase L1 to L2 fault). The memorized voltage will prevent collapse of
the mho circle for close in faults.

Operation occurs if 90≤β≤270

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Impedance protection

IL1L2·X
Ucomp = UL1L2 - IL1L2 • ZPP

IL1L2 • ZPP
ß
Upol
UL1L2

IL1L2·R

en07000109.vsd
IEC07000109 V1 EN

Figure 82: Simplified mho characteristic and vector diagram for phase L1-to-
L2 fault

Offset Mho
The characteristic for offset mho is a circle where two points on the circle are the
setting parameters ZPP and ZRevPP. The vector ZPP in the impedance plane has
the settable angle AngZPP and the angle for ZRevPP is AngZPP+180°.

The condition for operation at phase-to-phase fault is that the angle β between the
two compensated voltages Ucomp1 and Ucomp2 is greater than or equal to 90°
(figure 83). The angle will be 90° for fault location on the boundary of the circle.

The angle β for L1-to-L2 fault can be defined according to equation 39.

æ U -IL1L2 × ZPP ö
b = arg ç ÷
è U-(-IL1L2 × ZRevPP) ø
EQUATION1792 V1 EN (Equation 39)

where

U is the UL1L2 voltage


EQUATION1800 V1 EN

ZRevPP is the positive sequence impedance setting for phase-to-phase fault in reverse direction

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Impedance protection

IL1L2jX

Ucomp1 = UL1L2 - IL1L2 • ZPP


IL1L2 • ZPP

U
Ucomp2 = U = IF•ZF=UL1L2
IL1L2R

- IL1L2 • Z RevPP
en07000110.vsd
IEC07000110 V1 EN

Figure 83: Simplified offset mho characteristic and voltage vectors for phase
L1-to-L2 fault.

Operation occurs if 90≤β≤270.

Offset mho, forward direction


When forward direction has been selected for the offset mho, an extra criteria
beside the one for offset mho (90<β<270) is introduced, that is the angle φ between
the voltage and the current must lie between the blinders in second quadrant and
fourth quadrant. See figure 84. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.

where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR.
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR.
β is calculated according to equation 39

The directional information is brought to the mho distance measurement from the
mho directional element as binary coded information to the input DIRCND. See
Directional impedance element for mho characteristic (ZDMRDIR) for information
about the mho directional element.

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IL1L2jX

ZPP

UL1L2

ArgNegRes f

IL1L2
ArgDir

en07000111.vsd
IEC07000111 V1 EN

Figure 84: Simplified offset mho characteristic in forward direction for phase
L1-to-L2 fault

Offset mho, reverse direction


The operation area for offset mho in reverse direction is according to figure 85.
The operation area in second quadrant is ArgNegRes+180°.

Operation occurs if 90≤β≤270 and 180° - ArgDir ≤φ ≤ ArgNegRes + 180°

The β is derived according to equation 39 for the mho circle and φ is the angle
between the voltage and current.

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Impedance protection

ZPP

ArgNegRes
ϕ

IL1L2

ArgDir R

UL1L2

ZRevPP

en06000469.eps
IEC06000469 V1 EN

Figure 85: Operation characteristic for reverse phase L1-to-L2 fault

Phase-to-earth fault

Mho
The measuring of earth faults uses earth-return compensation applied in a
conventional way. The compensation voltage is derived by considering the
influence from the earth-return path.

For an earth fault in phase L1, the compensation voltage Ucomp can be derived, as
shown in figure 86.

Ucomp = U pol - I L1 × Z loop


EQUATION1793 V1 EN (Equation 40)

where
Upol is the polarizing voltage (memorized UL1 for Phase L1-to- earth fault)

Zloop is the loop impedance, which in general terms can be expressed as

Z1+ZN = Z 1 × 1 + KN ( )
EQUATION1799 V1 EN (Equation 41)
Table continues on next page

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Impedance protection

where
Z1 is the positive sequence impedance of the line (Ohm/phase)

KN is the zero-sequence compensator factor

The angle β between the Ucomp and the polarize voltage Upol for a L1-to-earth
fault is

b = arg [UL1 -(IL1 +3I0 · KN ) · ZPE ] - arg( Upol)


GUID-A9492CDF-D3B7-4DC5-8E06-6638BEE2540B V1 EN (Equation 42)

where
UL1 is the phase voltage in faulty phase L1

IL1 is the phase current in faulty phase L1

IA is the phase current in faulty phase A

3I0 is the zero-sequence current in faulty phase L1

KN Z0-Z1
EQUATION1593 V1 EN
3 × Z1
EQUATION1594 V1 EN

the setting parameter for the zero sequence compensation consisting of the
magnitude KN and the angle KNAng.
Upol is the 100% of positive sequence memorized voltage UL1

Vpol is the 100% of positive sequence memorized voltage VA

IL1·X

IL1·ZN
Ucomp

IL1 • Zloop
IL1·ZPE
Upol

f
IL1 (Ref) IL1·R

en06000472_2.vsd
IEC06000472 V2 EN

Figure 86: Simplified offset mho characteristic and vector diagram for phase
L1-to-earth fault

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Impedance protection

Operation occurs if 90≤β≤270.

Offset mho
The characteristic for offset mho at earth fault is a circle containing the two vectors
from the origin ZPE and ZRevPE where ZPE and ZrevPE are the setting reach for
the positive sequence impedance in forward respective reverse direction. The
vector ZPE in the impedance plane has the settable angle AngZPE and the angle for
ZRevPP is AngZPE+180°.

The condition for operation at phase-to-earth fault is that the angle β between the
two compensated voltages Ucomp1 and Ucomp2 is greater or equal to 90° see
figure 87. The angle will be 90° for fault location on the boundary of the circle.

The angle β for L1-to-earth fault can be defined as

æ UL1- IL1L × ZPE ö


b = arg ç ÷
è UL1-(- IL1 × Z Re vPE ) ø
EQUATION1802 V1 EN (Equation 45)

is the phase L1 voltage


U L1
EQUATION1
805 V1 EN

IL1L 2 • jX

U comp1 = UL1 - I L1• ZPE


IL1 • ZPE

UL1
U comp2 = UL1 - (-IL1 • ZRevPE)
IL1L2 • R

- I L1 • Z Re vPe

en 06000465.vsd
IEC06000465 V1 EN

Figure 87: Simplified offset mho characteristic and voltage vector for phase L1-
to-L2 fault

Operation occurs if 90≤β≤270.

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Impedance protection

Offset mho, forward direction


In the same way as for phase-to-phase fault, selection of forward direction of offset
mho will introduce an extra criterion for operation. Beside the basic criteria for
offset mho according to equation 45 and 90≤β≤270, also the criteria that the angle
φ between the voltage and the current must lie between the blinders in second and
fourth quadrant. See figure 88. Operation occurs if 90≤β≤270 and
ArgDir≤φ≤ArgNegRes.

where
ArgDir is the setting parameter for directional line in fourth quadrant in the directional element,
ZDMRDIR.
ArgNegRes is the setting parameter for directional line in second quadrant in the directional element,
ZDMRDIR.
β is calculated according to equation 45

IL1 jX

UL1

ArgNegRes f

IL1 IL1·R

ArgDir

en 06000466.vsd
IEC06000466 V1 EN

Figure 88: Simplified characteristic for offset mho in forward direction for L1-to-
earth fault

Offset mho, reverse direction


In the same way as for offset in forward direction, the selection of offset mho in
reverse direction will introduce an extra criterion for operation compare to the
normal offset mho. The extra is that the angle between the fault voltage and the
fault current shall lie between the blinders in second and fourth quadrant. The
operation area in second quadrant is limited by the blinder defined as 180° -ArgDir
and in fourth quadrant ArgNegRes+180°, see figure 89.

The conditions for operation of offset mho in reverse direction for L1-to-earth fault
is 90≤β≤270 and 180°-Argdir≤φ≤ArgNegRes+180°.

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The β is derived according to equation 45 for the offset mho circle and φ is the
angle between the voltage and current.

ZPE

ArgNegRes
ϕ

IL
1
ArgDir R

UL1
ZRevPE

en06000470.eps
IEC06000470 V1 EN

Figure 89: Simplified characteristic for offset mho in reverse direction for L1-to-
earth fault

6.1.2.5 Simplified logic diagrams

Distance protection zones


The design of the distance protection zones are presented for all measuring loops:
phase-to-earth as well as phase-to-phase.

Phase-to-earth related signals are designated by L1N, L2N and L3N. The phase-to-
phase signals are designated by L1L2, L2L3, and L3L1.

Fulfillment of two different measuring conditions is necessary to obtain the one


logical signal for each separate measuring loop:

• Zone measuring condition, which follows the operating equations described


above.
• Group functional input signal (STCND), as presented in figure 90.

One type of function block, ZMHPDIS are used in the IED for zone 1 - 5.

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Impedance protection

The STCND input signal represents a connection of six different integer values
from Phase selection with load encroachment, quadrilateral characteristic function
FMPSPDIS within the IED, which are converted within the zone measuring
function into corresponding boolean expressions for each condition separately.
Input signal STCND is connected to FMPSPDIS function output signal
STCNDPHS.

The input signal DIRCND is used to give condition for directionality for the
distance measuring zones. The signal contains binary coded information for both
forward and reverse direction. The zone measurement function filters out the
relevant signals depending on the setting of the parameter DirMode. Input signal
DIRCND must be configured to the STDIRCND output signal on ZDMRDIR
function.

OffsetMhoDir=
Non-directional
AND AND
DirMode=Offset

STCND T
AND F

AND
LoadEnchMode=
On/Off
LDCND
T
True F
AND Release

DIRCND

OffsetMhoDir=
Forward/Reverse
AND
DirMode=
Forward/Reverse

BLKZ
BLOCK OR

IEC11000216-1-en.vsd
IEC11000216 V1 EN

Figure 90: Simplified logic for release start signal

When load encroachment mode is switched on (LoadEnchMode=On) then start


signal STCND is also checked against LDCND signal.

Results of the directional measurement enter the logic circuits, when the zone
operates in directional (forward or reverse) mode, as shown in figure 90.

Composition of the phase start signals is presented in figure 91.

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Impedance protection

Release STPE
OR

AND
STL1N STL1
OR

AND
STL2N

AND
STL3N
STL2
OR
AND
STL1L2

AND
STL2L3
STL3
OR
AND
STL3L1

START
OR

STPP
OR

IEC11000217-1-en.vsd
IEC11000217 V1 EN

Figure 91: Composition of starting signals

Tripping conditions for the distance protection zone one are symbolically presented
in figure 92.

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Impedance protection

Timer tPP=On tPP


AND t
STPP
OR
Timer tPE=On tPE
AND t
STPE

15ms
AND TRIP
BLKTRIP t

STL1 AND TRL1

AND TRL2
STL2

STL3 AND TRL3

IEC11000218-1-en.vsd
IEC11000218 V1 EN

Figure 92: Tripping logic for the distance protection zone

6.1.3 Function block


ZMHPDIS
I3P* TRIP
U3P* TRL1
CURR_INP* TRL2
VOLT_INP* TRL3
POL_VOLT* TRPE
BLOCK TRPP
BLKZ START
BLKZMTD STL1
BLKHSIR STL2
BLKTRIP STL3
BLKPE STPE
BLKPP STPP
DIRCND
STCND
LDCND

IEC06000423_2_en.vsd
IEC06000423 V2 EN

Figure 93: ZMHPDIS function block

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6.1.4 Input and output signals


Table 88: ZMHPDIS Input signals
Name Type Default Description
I3P GROUP - Connection for current sample signals
SIGNAL
U3P GROUP - Connection for voltage sample signals
SIGNAL
CURR_INP GROUP - Connection for current signals
SIGNAL
VOLT_INP GROUP - Connection for voltage signals
SIGNAL
POL_VOLT GROUP - Connection for polarizing voltage
SIGNAL
BLOCK BOOLEAN 0 Block of function
BLKZ BOOLEAN 0 Block due to fuse failure
BLKZMTD BOOLEAN 0 Block signal for blocking of time domaine function
BLKHSIR BOOLEAN 0 Blocks time domain function at high SIR
BLKTRIP BOOLEAN 0 Blocks all operate output signals
BLKPE BOOLEAN 0 Blocks phase-to-earth operation
BLKPP BOOLEAN 0 Blocks phase-to-phase operation
DIRCND INTEGER 0 External directional condition
STCND INTEGER 0 External start condition (loop enabler)
LDCND INTEGER 0 External load condition (loop enabler)

Table 89: ZMHPDIS Output signals


Name Type Description
TRIP BOOLEAN Trip General
TRL1 BOOLEAN Trip phase L1
TRL2 BOOLEAN Trip phase L2
TRL3 BOOLEAN Trip phase L3
TRPE BOOLEAN Trip phase-to-earth
TRPP BOOLEAN Trip phase-to-phase
START BOOLEAN Start General
STL1 BOOLEAN Start phase L1
STL2 BOOLEAN Start phase L2
STL3 BOOLEAN Start phase L3
STPE BOOLEAN Start phase-to-earth
STPP BOOLEAN Start phase-to-phase

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6.1.5 Setting parameters


Table 90: ZMHPDIS Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - On Operation Off/On
On
IBase 1 - 99999 A 1 3000 Base current
UBase 0.05 - 2000.00 kV 0.05 400.00 Base voltage
DirMode Off - - Forward Direction mode
Offset
Forward
Reverse
LoadEncMode Off - - Off Load encroachment mode Off/On
On
ReachMode Overreach - - Overreach Reach mode Over/Underreach
Underreach
OpModePE Off - - On Operation mode Off / On of Phase-Earth
On loops
ZPE 0.005 - 3000.000 ohm/p 0.001 30.000 Positive sequence impedance setting for
Phase-Earth loop
ZAngPE 10 - 90 Deg 1 80 Angle for positive sequence line
impedance for Phase-Earth loop
KN 0.00 - 3.00 - 0.01 0.80 Magnitud of earth return compensation
factor KN
KNAng -180 - 180 Deg 1 -15 Angle for earth return compensation
factor KN
ZRevPE 0.005 - 3000.000 ohm/p 0.001 30.000 Reverse reach of the phase to earth
loop(magnitude)
tPE 0.000 - 60.000 s 0.001 0.000 Delay time for operation of phase to
earth elements
IMinOpPE 10 - 30 %IB 1 20 Minimum operation phase to earth current
OpModePP Off - - On Operation mode Off / On of Phase-
On Phase loops
ZPP 0.005 - 3000.000 ohm/p 0.001 30.000 Impedance setting reach for phase to
phase elements
ZAngPP 10 - 90 Deg 1 85 Angle for positive sequence line
impedance for Phase-Phase elements
ZRevPP 0.005 - 3000.000 ohm/p 0.001 30.000 Reverse reach of the phase to phase
loop(magnitude)
tPP 0.000 - 60.000 s 0.001 0.000 Delay time for operation of phase to phase
IMinOpPP 10 - 30 %IB 1 20 Minimum operation phase to phase
current

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Table 91: ZMHPDIS Group settings (advanced)


Name Values (Range) Unit Step Default Description
OffsetMhoDir Non-directional - - Non-directional Direction mode for offset mho
Forward
Reverse
OpModetPE Off - - On Operation mode Off / On of Zone timer,
On Ph-E
OpModetPP Off - - On Operation mode Off / On of Zone timer,
On Ph-ph

6.1.6 Technical data


Table 92: ZMHPDIS technical data
Function Range or value Accuracy
Number of zones with selectable Max 4 with selectable direction -
directions
Minimum operate current (10–30)% of IBase -

Positive sequence impedance, (0.005–3000.000) W/phase ± 2.0% static accuracy


phase-to-earth loop Conditions:
Voltage range: (0.1-1.1) x Ur
Positive sequence impedance (10–90) degrees
Current range: (0.5-30) x Ir
angle, phase-to-earth loop
Angle: at 0 degrees and 85
Reverse reach, phase-to-earth (0.005–3000.000) Ω/phase degrees
loop (Magnitude)
Magnitude of earth return (0.00–3.00)
compensation factor KN
Angle for earth compensation (-180–180) degrees
factor KN
Dynamic overreach <5% at 85 degrees measured -
with CVT’s and 0.5<SIR<30
Timers (0.000-60.000) s ± 0.5% ± 10 ms
Operate time 20 ms typically (with static -
outputs)
Reset ratio 105% typically -
Reset time 30 ms typically -

6.2 Directional impedance element for mho


characteristic ZDMRDIR

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Directional impedance element for mho ZDMRDIR 21D
characteristic

S00346 V1 EN

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6.2.1 Introduction
The phase-to-earth impedance elements can be optionally supervised by a phase
unselective directional function based on symmetrical components.

6.2.2 Principle of operation

6.2.2.1 Directional impedance element for mho characteristic ZDMRDIR

The evaluation of the directionality takes place in Directional impedance element


for mho characteristic (ZDMRDIR). Equation 46 and equation 47 are used to
classify that the fault is in the forward direction for phase-to-earth fault and phase-
to-phase fault respectively.

0.85 × U1L1 + 0.15 × U1L1M


- ArgDir < arg < ArgNeg Re s
I L1
EQUATION1617 V1 EN (Equation 46)

0.85 × U1L1L 2 + 0.15 × U1L1L 2 M


- ArgDir < arg < ArgNeg Re s
I L1L 2
EQUATION1619 V1 EN (Equation 47)

Where:
ArgDir Setting for the lower boundary of the forward directional characteristic, by default set to
15 (= -15 degrees)
ArgNegRes Setting for the upper boundary of the forward directional characteristic, by default set to
115 degrees, see figure 94 for mho characteristics.
U1L1 Positive sequence phase voltage in phase L1

U1L1M Positive sequence memorized phase voltage in phase L1

IL1 Phase current in phase L1

U1L1L2 Voltage difference between phase L1 and L2 (L2 lagging L1)

U1L1L2M Memorized voltage difference between phase L1 and L2 (L2 lagging L1)

IL1L2 Current difference between phase L1 and L2 (L2 lagging L1)

The default settings for ArgDir and ArgNegRes are 15 (= -15) and 115 degrees
respectively (see figure 94) and they should not be changed unless system studies
show the necessity.

If one sets DirEvalType to Comparator (which is recommended when using the


mho characteristic) then the directional lines are computed by means of a comparator-
type calculation, meaning that the directional lines are based on mho-circles (of
infinite radius). The default setting value Impedance otherwise means that the

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directional lines are implemented based on an impedance calculation equivalent to


the one used for the quadrilateral impedance characteristics.

When Directional impedance element for mho characteristic


(ZDMRDIR) is used together with Fullscheme distance protection,
mho characteristic (ZMHPDIS) the following settings for
parameter DirEvalType is vital:
• alternative Comparator is strongly recommended
• alternative Imp/Comp should generally not be used
• alternative Impedance should not be used. This altenative is
intended for use together with Distance protection zone,
quadrilateral characteristic (ZMQPDIS)

X
Zset reach point

ArgNegRes

-ArgDir R

-Zs
en06000416.vsd

IEC06000416 V1 EN

Figure 94: Setting angles for discrimination of forward fault

The reverse directional characteristic is equal to the forward characteristic rotated


by 180 degrees.

The polarizing voltage is available as long as the positive-sequence voltage


exceeds 5% of the set base voltage UBase. So the directional element can use it for
all unsymmetrical faults including close-in faults.

For close-in three-phase faults, the U1L1M memory voltage, based on the same
positive sequence voltage, ensures correct directional discrimination.

The memory voltage is used for 100ms or until the positive sequence voltage is
restored. After 100ms, the following occurs:

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• If the current is still above the set value of the minimum operating current the
condition seals in.
• If the fault has caused tripping, the trip endures.
• If the fault was detected in the reverse direction, the measuring element
in the reverse direction remains in operation.
• If the current decreases below the minimum operating value, no directional
indications will be given until the positive sequence voltage exceeds 10% of
its rated value.

The Directional impedance element for mho characteristic (ZDMRDIR) function


has the following output signals:

The STDIRCND output provides an integer signal that depends on the evaluation
and is derived from a binary coded signal as follows:

bit 11 bit 10 bit 9 bit 8 bit 7 bit 6


(2048) (1024) (512) (256) (128) (64)
STRVL3L1= STRVL2L3= STRVL1L2= STRVL3N=1 STRVL2N=1 STRVL1N=1
1 1 1
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(32) (16) (8) (4) (2) (1)
STFWL3L1= STFWL2L3= STFWL1L2= STFWL3N=1 STFWL2N=1 STFWL1N=1
1 1 1

The STFW output is a logical signal with value 1 or 0. It is made up as an OR-


function of all the forward starting conditions, that is, STFWL1N, STFWL2N,
STFWL3N, STFWL1L2, STFWL2L3 and STFWL3L1. The STRV output is
similar to the STFW output, the only difference being that it is made up as an OR-
function of all the reverse starting conditions, that is, STRVL1N, STRVL2N,
STRVL3N, STRVL1L2, STRVL2L3 and STRVL3L1.

Values for the following parameters are calculated, and may be viewed as service
values:

• resistance phase L1
• reactance phase L1
• resistance phase L2
• reactance phase L2
• resistance phase L3
• reactance phase L3
• direction phase L1
• direction phase L2
• direction phase L3

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6.2.3 Function block


ZDMRDIR
I3P* DIR_CURR
U3P* DIR_VOLT
DIR_POL
STFW
STRV
STDIRCND

IEC06000422_2_en.vsd
IEC06000422 V2 EN

Figure 95: ZDMRDIR function block

6.2.4 Input and output signals


Table 93: ZDMRDIR Input signals
Name Type Default Description
I3P GROUP - group connection for current abs 1
SIGNAL
U3P GROUP - group connection for voltage abs 1
SIGNAL

Table 94: ZDMRDIR Output signals


Name Type Description
DIR_CURR GROUP SIGNAL Group connection
DIR_VOLT GROUP SIGNAL Group connection
DIR_POL GROUP SIGNAL Group connection
STFW BOOLEAN Start in forward direction
STRV BOOLEAN Start in reverse direction
STDIRCND INTEGER Binary coded directional information per
measuring loop

6.2.5 Setting parameters


Table 95: ZDMRDIR Group settings (basic)
Name Values (Range) Unit Step Default Description
IBase 1 - 99999 - 1 3000 Base setting for current level
UBase 0.05 - 2000.00 - 0.05 400.00 Base setting for voltage level
DirEvalType Impedance - - Comparator Directional evaluation mode Impedance /
Comparator Comparator
Imp/Comp
ArgNegRes 90 - 175 Deg 1 115 Angle of blinder in second quadrant for
forward direction
Table continues on next page

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Name Values (Range) Unit Step Default Description


ArgDir 5 - 45 Deg 1 15 Angle of blinder in fourth quadrant for
forward direction
IMinOpPE 5 - 30 %IB 1 5 Minimum operate phase current for
Phase-Earth loops
IMinOpPP 5 - 30 %IB 1 10 Minimum operate delta current for Phase-
Phase loops

6.3 Pole slip protection PSPPPAM

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Pole slip protection PSPPPAM Ucos 78

6.3.1 Introduction
The phenomenon pole slip, also named out of step conditions, occurs when there is
phase opposition between different parts of a power system. This is often shown in
a simplified way as two equivalent generators connected to each other via an
equivalent transmission line and the phase difference between the equivalent
generators is 180°.

Angle = 90° Angle = -90°

Centre of Pole Slip


en07000003.vsd
IEC07000003 V1 EN

Figure 96: The centre of pole slip

The centre of the pole slip can occur in the generator itself or somewhere in the
power system. When a pole slip occurs within the generator it is essential to trip the
generator. If the centre of pole slip occurs outside any generator the power system

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should be split into two different parts that could have the ability to get stable
operating conditions.

Pole slip protection (PSPPPAM) function in the IED can be used both for generator
protection application as well as, line protection applications.

The situation with pole slip of a generator can be caused by different reasons.

A short circuit may occur in the external power grid, close to the generator. If the
fault clearing time is too long, the generator will accelerate so much, that the
synchronism cannot be maintained.

Un-damped oscillations occur in the power system, where generator groups at


different locations, oscillate against each other. If the connection between the
generators is too weak the magnitude of the oscillations will increase until the
angular stability is lost.

The operation of a generator having pole slip will give risk of damages to the
generator, shaft and turbine.

• At each pole slip there will be significant torque impact on the generator-
turbine shaft.
• In asynchronous operation there will be induction of currents in parts of the
generator normally not carrying current, thus resulting in increased heating.
The consequence can be damages on insulation and stator/rotor iron.

The Pole slip protection (PSPPPAM) function shall detect pole slip conditions and
trip the generator as fast as possible if the locus of the measured impedance is
inside the generator-transformer block. If the centre of pole slip is outside in the
power grid, the first action should be to split the network into two parts, after line
protection action. If this fails there should be operation of the generator PSPPPAM
in zone 2, to prevent further damages to the generator, shaft and turbine.

6.3.2 Principle of operation


If the generator is faster than the power system, the rotor movement in the
impedance and voltage diagram is from right to left and generating is signalled. If
the generator is slower than the power system, the rotor movement is from left to
right and motoring is signalled (the power system drives the generator as if it were
a motor).

The movements in the impedance plain can be seen in figure 97. The transient
behaviour is described by the transient EMF's EA and EB, and by X'd, XT and the
transient system impedance ZS.

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Zone 1 Zone 2

EB X’d XT XS EA

IED
B A

jX

XS

Pole slip
impedance XT
d Apparent generator
movement impedance R

X’d

IEC06000437_2_en.vsd
IEC06000437 V2 EN

Figure 97: Movements in the impedance plain

where:
X'd = transient reactance of the generator

XT = short-circuit reactance of the step-up transformer

ZS = impedance of the power system A

The detection of rotor angle is enabled when:

• the minimum current exceeds 0.10 IN (IN is IBase parameter set under general
setting).
• the maximum voltage falls below 0.92 UBase
• the voltage Ucosφ (the voltage in phase with the generator current) has an
angular velocity of 0.2...8 Hz and
• the corresponding direction is not blocked.

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en07000004.vsd
IEC07000004 V1 EN

Figure 98: Different generator quantities as function of the angle between the
equivalent generators

An alarm is given when movement of the rotor is detected and the rotor angle
exceeds the angle set for 'WarnAngle'.

Slipping is detected when:

• a change of rotor angle of min. 50 ms is recognized


• the slip line is crossed between ZA and ZB.

When the impedance crosses the slip line between ZB and ZC it counts as being in
zone 1 and between ZC and ZA in zone 2. The entire distance ZA-ZB becomes zone
1 when signal EXTZONE1 is high (external device detects the direction of the
centre of slipping).

After the first slip, the signals ZONE1 or ZONE2 and – depending on the direction
of slip - either GEN or MOTOR are issued.

Every time pole slipping is detected, the impedance of the point where the slip line
is crossed and the instantaneous slip frequency are displayed as measurements.

Further slips are only detected, if they are in the same direction and if the rate of
rotor movement has reduced in relation to the preceding slip or the slip line is
crossed in the opposite direction outside ZA-ZB. A further slip in the opposite
direction within ZA-ZB resets all the signals and is then signalled itself as a first slip.

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The TRIP1 tripping command and signal are generated after N1 slips in zone 1,
providing the rotor angle is less than TripAngle. The TRIP2 signal is generated
after N2 slips in zone 2, providing the rotor angle is less than TripAngle.

All signals are reset if:

• the direction of movement reverses


• the rotor angle detector resets without a slip being counted or
• no rotor relative movement was detected during the time ResetTime.

Imin > 0.10 IBase

Ucosj < 0.92 UBase AND

START
AND
0.2 £ Slip.Freq. £ 8 Hz

d ³ startAngle

ZONE1
AND
Z cross line ZA - ZC

ZONE2
AND
Z cross line ZC - ZB

Counter
a
a³b
N1Limit b TRIP1
AND

d £ tripAngle TRIP
OR

Counter
a
N2Limit b a³b TRIP2
AND

en07000005.vsd

IEC07000005 V1 EN

Figure 99: Simplified logic diagram for pole slip protection PSPPPAM

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6.3.3 Function block


PSPPPAM
I3P* TRIP
U3P* TRIP1
BLOCK TRIP2
BLKGEN START
BLKMOTOR ZONE1
EXTZONE1 ZONE2
GEN
MOTOR
SFREQ
SLIPZOHM
SLIPZPER
UCOS
UCOSPER

IEC10000045-1-en.vsd
IEC10000045 V1 EN

Figure 100: PSPPPAM function block

6.3.4 Input and output signals


Table 96: PSPPPAM Input signals
Name Type Default Description
I3P GROUP - Current group connection
SIGNAL
U3P GROUP - Voltage group connection
SIGNAL
BLOCK BOOLEAN 0 Block of function
BLKGEN BOOLEAN 0 Block operation in generating direction
BLKMOTOR BOOLEAN 0 Block operation in motor direction
EXTZONE1 BOOLEAN 0 Extension of zone1 with zone2 region

Table 97: PSPPPAM Output signals


Name Type Description
TRIP BOOLEAN Common trip signal
TRIP1 BOOLEAN Trip1 after the N1Limit slip in zone1
TRIP2 BOOLEAN Trip2 after the N2Limit slip in zone2
START BOOLEAN Common start signal
ZONE1 BOOLEAN First slip in zone1 region
ZONE2 BOOLEAN First slip in zone2 region
GEN BOOLEAN Generator is faster than the system
MOTOR BOOLEAN Generator is slower than the system
SFREQ REAL Slip frequency
SLIPZOHM REAL Slip impedance in ohms
SLIPZPER REAL Slip impedance in percent of ZBase
UCOS REAL UCosPhi voltage
UCOSPER REAL UCosPhi voltage in percent of UBase

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6.3.5 Setting parameters


Table 98: PSPPPAM Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation On / Off
On
OperationZ1 Off - - On Operation Zone1 On / Off
On
OperationZ2 Off - - On Operation Zone2 On / Off
On
ImpedanceZA 0.00 - 1000.00 % 0.01 10.00 Forward impedance in % of Zbase
ImpedanceZB 0.00 - 1000.00 % 0.01 10.00 Reverse impedance in % of Zbase
ImpedanceZC 0.00 - 1000.00 % 0.01 10.00 Impedance of zone1 limit in % of Zbase
AnglePhi 72.00 - 90.00 Deg 0.01 85.00 Angle of the slip impedance line
StartAngle 0.0 - 180.0 Deg 0.1 110.0 Rotor angle for the start signal
TripAngle 0.0 - 180.0 Deg 0.1 90.0 Rotor angle for the trip1 and trip2 signals
N1Limit 1 - 20 - 1 1 Count limit for the trip1 signal
N2Limit 1 - 20 - 1 3 Count limit for the trip2 signal

Table 99: PSPPPAM Group settings (advanced)


Name Values (Range) Unit Step Default Description
ResetTime 0.000 - 60.000 s 0.001 5.000 Time without slip to reset all signals

Table 100: PSPPPAM Non group settings (basic)


Name Values (Range) Unit Step Default Description
IBase 0.1 - 99999.9 A 0.1 3000.0 Base Current (primary phase current in
Amperes)
UBase 0.1 - 9999.9 kV 0.1 20.0 Base Voltage (primary phase-to-phase
voltage in kV)
MeasureMode PosSeq - - PosSeq Measuring mode (PosSeq, L1L2, L2L3,
L1L2 L3L1)
L2L3
L3L1
InvertCTcurr No - - No Invert current direction
Yes

6.3.6 Technical data


Table 101: PSPPPAM technical data
Function Range or value Accuracy
Impedance reach (0.00–1000.00)% of Zbase ± 2.0% of Ur/Ir
Characteristic angle (72.00–90.00) degrees ± 5.0 degrees
Start and trip angles (0.0–180.0) degrees ± 5.0 degrees
Zone 1 and Zone 2 trip counters (1-20) -

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6.4 Loss of excitation LEXPDIS

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Loss of excitation LEXPDIS 40

<
SYMBOL-MM V1 EN

6.4.1 Introduction
There are limits for the under-excited operation of a synchronous machine. A
reduction of the excitation current weakens the coupling between the rotor and the
stator. The machine may lose the synchronism and start to operate like an induction
machine. Then, the reactive power consumption will increase. Even if the machine
does not loose synchronism it may not be acceptable to operate in this state for a
long time. Reduction of excitation increases the generation of heat in the end
region of the synchronous machine. The local heating may damage the insulation
of the stator winding and the iron core.

To prevent damages to the generator it should be tripped when excitation is lost.

6.4.2 Principle of operation


The Loss of excitation (LEXPDIS) protection in the IED measures the apparent
impedance seen out from the generator.The measurement loop of apparent
impedance can be chosen as the positive sequence loop or any one of the three phase-
to-phase loops depending on the available current and voltage signals. It is
recommended to use positive sequence quantities for function operation.

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Measured mode Measured apparent impedance

Zposseq U posseq
=
I posseq
EQUATION1771 V1 EN (Equation 48)

ZL1L2 U L1 - U L 2
=
I L1 - I L 2
EQUATION1772 V1 EN (Equation 49)

ZL2L3 U L 2 - U L3
=
I L 2 - I L3
EQUATION1773 V1 EN (Equation 50)

ZL3L1 U L 3 - U L1
=
I L 3 - I L1
EQUATION1774 V1 EN (Equation 51)

There are three characteristics in LEXPDIS protection as shown in figure 101.

Naimly:
• Offset mho circle for Z1
• Offset mho circle for Z2
• Directional blinder

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UnderexitationProtection
Underexcitation protection
Restrainarea
Restrain area

R
Directional
blinder

Z1, Fast zone

Z2, Slow zone

IEC06000455-2-en.vsd
IEC06000455 V2 EN

Figure 101: Three characteristics in LEXPDIS protection

When the apparent impedance reaches the zone Z1 this zone will operate, normally
with a short delay. The zone is related to the dynamic stability of the generator.

When the apparent impedance reaches the zone Z2 this zone will operate, normally
with a longer delay. The zone is related to the static stability of the generator.

LEXPDIS protection also has a directional blinder (supervision). See figure 101.

In LEXPDIS function the zone measurement is done as shown in figure 102.

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Offset

R
XoffsetZ1
Z (apparent impedance)

Z1 = Z - (XoffsetZ1 +
Z1diameter Z1diameter/2)

Z1 or Z2

en06000456-2.vsd
IEC06000456 V2 EN

Figure 102: Zone measurement in LEXPDIS protection function

The impedance Z1 is constructed out from the measured apparent impedance Z and
the impedance corresponding to the centre point of the impedance characteristic
(Z1 or Z2). If the amplitude of this impedance is less than the radius (diameter/2)
of the characteristic, this part of the protection will operate.

If the directional restrain is set off the impedance zone operation will start the
appropriate timer and LEXPDIS will trip after the set delay (tZ1 or tZ2).

If the directional restrain is set On the directional release function must also
operate to enable operation. A new impedance is constructed as XoffsetDirLine. If
the phase angle of this impedance is less than the set DirAngle LEXPDIS function
will be released, see figure 103.

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Underexcitation Protection
Restrain area

R
XoffsetDirLine
DirAngle

Z (apparent impedance)

en06000457.vsd
IEC06000457 V1 EN

Figure 103: Impedance constructed as XoffsetDirLine in LEXPDIS protection

LEXPDIS function is schematically described in figure 104.

Positive tZ1
sequence Z in startZ1 t TripZ1
&
current Z1 char.
phasor

Positive Apparent tZ2


Z Z in
sequence startZ2 t TripZ2
impedance &
voltage Z2 char.
calculation
phasor

Dir.
Restrain
Dir.Restrain ON ³1

en06000458-2.vsd

IEC06000458 V3 EN

Figure 104: Simplified logic diagram of LEXPDIS protection

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6.4.3 Function block


LEXPDIS
I3P* TRIP
U3P* TRZ1
BLOCK TRZ2
BLKTRZ1 START
BLKTRZ2 STZ1
STZ2
XOHM
XPERCENT
ROHM
RPERCENT

IEC07000031_2_en.vsd
IEC07000031 V2 EN

Figure 105: LEXPDIS function block

6.4.4 Input and output signals


Table 102: LEXPDIS Input signals
Name Type Default Description
I3P GROUP - Current group connection
SIGNAL
U3P GROUP - Voltage group connection
SIGNAL
BLOCK BOOLEAN 0 Block of function
BLKTRZ1 BOOLEAN 0 Block trip of zone Z1
BLKTRZ2 BOOLEAN 0 Block trip of zone Z2

Table 103: LEXPDIS Output signals


Name Type Description
TRIP BOOLEAN Common trip signal
TRZ1 BOOLEAN Trip signal from impedance zone Z1
TRZ2 BOOLEAN Trip signal from impedance zone Z2
START BOOLEAN Common start signal
STZ1 BOOLEAN Start signal from impedance zone Z1
STZ2 BOOLEAN Start signal from impedance zone Z2
XOHM REAL Reactance in Primary Ohms
XPERCENT REAL Reactance in percent of Zbase
ROHM REAL Resistance in Primary Ohms
RPERCENT REAL Resistance in percent of Zbase

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Impedance protection

6.4.5 Setting parameters


Table 104: LEXPDIS Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation Off / On
On
OperationZ1 Off - - On Operation Off/On zone Z1
On
XoffsetZ1 -1000.00 - 1000.00 % 0.01 -10.00 Offset of Z1 circle top point along X axis
in % of Zbase
Z1diameter 0.01 - 3000.00 % 0.01 100.00 Diameter of imedance circle for Z1 in %
of Zbase
tZ1 0.00 - 6000.00 s 0.01 0.01 Trip time delay for Z1
OperationZ2 Off - - On Operation Off/On zone Z2
On
XoffsetZ2 -1000.00 - 1000.00 % 0.01 -10.00 Offset of Z2 circle top point along X axis
in % of Zbase
Z2diameter 0.01 - 3000.00 % 0.01 200.00 Diameter of imedance circle for Z2 in %
of Zbase
tZ2 0.00 - 6000.00 s 0.01 1.00 Trip time delay for Z2

Table 105: LEXPDIS Group settings (advanced)


Name Values (Range) Unit Step Default Description
DirSuperv Off - - Off Operation Off/On for additional
On directional criterion
XoffsetDirLine -1000.00 - 3000.00 % 0.01 0.00 Offset of directional line along X axis in
% of Zbase
DirAngle -180.0 - 180.0 Deg 0.1 -13.0 Angle between directional line and R-
axis in degrees

Table 106: LEXPDIS Non group settings (basic)


Name Values (Range) Unit Step Default Description
IBase 0.1 - 99999.9 A 0.1 3000 Base Current (primary phase current in
Amperes)
UBase 0.1 - 9999.9 kV 0.1 20 Base Voltage (primary phase-to-phase
voltage in kV)
MeasureMode PosSeq - - PosSeq Measuring mode (PosSeq, L1L2, L2L3,
L1L2 L3L1)
L2L3
L3L1

Table 107: LEXPDIS Non group settings (advanced)


Name Values (Range) Unit Step Default Description
InvertCTcurr No - - No Invert CT current
Yes

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Impedance protection

6.4.6 Technical data


Table 108: LEXPDIS technical data
Function Range or value Accuracy
X offset of Mho top point (–1000.00–1000.00)% of ZBase ± 2.0% of Ur/Ir

Diameter of Mho circle (0.00–3000.00)% of ZBase ± 2.0% of Ur/Ir

Timers (0.00–6000.00) s ± 0.5% ± 10 ms

6.5 Sensitive rotor earth fault protection, injection based


ROTIPHIZ

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
Sensitive rotor earth fault protection, ROTIPHIZ Rre< 64R
injection based

6.5.1 Introduction
The sensitive rotor earth fault protection (ROTIPHIZ) is used to detect earth faults
in the rotor windings of generators. ROTIPHIZ is applicable for all types of
synchronous generators.

To implement the above concept, a separate injection box is required. The injection
box generates a square wave voltage signal at a certain preset frequency which is
fed into the rotor winding.

The magnitude of the injected voltage signal and the resulting injected current is
measured through a resistive shunt located within the injection box. These two
measured values are fed to the IED. Based on these two measured quantities, the
protection IED determines the rotor winding resistance to ground. The resistance
value is then compared with the preset fault resistance alarm and trip levels.

The protection function can detect earth faults in the entire rotor winding and
associated connections.

Requires injection unit REX060 and a coupling capacitor unit REX061 for correct
operation.

6.5.2 Principle of operation


The protection principle is based on injection of voltage to the exciter point of the
field circuit.

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1MRK 502 027-UEN A Section 6
Impedance protection

4 Step-up
Transformer

U> 3
Uinj 1

Rshunt
7 R C

~ Generator
5

6
REX061 2

ROTOR EF
I
RN

REX060/RIM module

REG670
IEC11000014-4-en.vsd
Generator Protection Panel
IEC11000014 V1 EN

Figure 106: Example installation for rotor injection

1 Generator unit consisting of a synchronous generator and a step-up transformer


2 Generator field winding
3 Capacitor coupling unit which is used to provide insulation barrier between rotor circuit and
injection equipment
4 Cable used to inject the square-wave signal into the rotor circuit
5 Connection for measurement of injected current. This signal is amplified in REX060 before it is
passed on to IED for evaluation.
6 Connection for measurement of injected voltage. This signal is amplified in REX060 before it is
passed on to IED for evaluation.
7 Two VT inputs into IED which are used to measure injected current and voltage
8 Protection for excessive over-voltages posed by generator. REX060 can withstand without
damage maximum voltage of 120V and when used together with REX062 up to 240V.

The injection signals are generated in a separate unit, REX060. The signals have
square wave form and are injected to the generator via the coupling capacitor unit
REX061 to the excitation circuit.

In the REX060 unit the injection voltage and current signals are amplified to a
level adapted to the analogue voltage inputs of IED. In IED the measured signals
evaluated to detect rotor earth faults.

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Section 6 1MRK 502 027-UEN A
Impedance protection

6.5.2.1 The injection unit REX060

IED and
Injection Top view Power Back view Front view
connectors connector Keylock
LED

X11 X61 X81


1 1 1

Injection Stator
Injection Rotor

18 18
X62 X82

PSM
1 1

5 5

Power

Stator

Rotor
Backplane

Front-plate Injection LED Injection switch


HMI with logic

IEC11000015-1-en.vsd
IEC11000015 V1 EN

Figure 107: Injection unit REX060

The REX060 unit is a common unit that can be configured for either rotor or stator
earth fault protection, or for both. The REX060 have separate modules for rotor
and stator protection. The REX060 generate square wave signals, where one is
used for injection to the stator neutral point and the other to the field winding
circuit (rotor circuit), if configured for both stator and rotor protection. The injected
voltage and currents are measured by the unit and amplified, resulting in voltage
signals both for the injected voltage and current, and adapted to the analogue inputs
of IED. The injection unit REX060 shall be located close to the IED, preferably in
the same cubicle.

For the Sensitive rotor earth fault protection, there are some settings necessary for
REX060:

• System frequency: 50/60 Hz


• Injected frequency for rotor circuit injection is settable in 1 Hz steps 75 – 250
Hz.
• Gain factor in four steps

REX060 will also continuously check the measured signal for detection of
saturation which could cause error in the evaluation in IED. If saturation level is
reached a binary signal, connected to IED, is activated. Also other errors in the
injection circuit will initiate a binary signal to IED for blocking of the function.

Rotor injection output is protected against high voltages by a relay blocking the
injection circuit. This blocking remains blocked by stored status in non-volatile
memory.

The output is also protected by a fuse. If this fuse is blown, it is caused by external
voltage source, since the injection unit cannot provide enough energy to blow this
fuse.

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1MRK 502 027-UEN A Section 6
Impedance protection

Refer to the Hardware section in this manual for a detailed description of REX060.

6.5.2.2 Rotor Earth Fault Protection function

The injection to the rotor is schematically shown in figure 108.

Iinj

+
DC
Crot
Rf Crot Uinj
AC
REX061 -
Rf Iinj
+
Rotor Reference
U inj
Im pedance
-

IEC11000065-1-en.vsd

IEC11000065 V1 EN

Figure 108: Equivalent diagram for Sensitive rotor earth fault protection principle

The impedance ZMeasured is equal to the capacitive reactance between the rotor
winding and earth (1/ωCrot) and the earth fault resistance (Rf). The series resistance
in the injection circuit is eliminated. Rf is very large in the non-faulted case and the
measured impedance, called the rotor reference impedance and can be calculated as :

1
Z ref = - j
wCrot
EQUATION2510 V1 EN

alternative

1
= jwCrot
Z ref
EQUATION2511 V1 EN

Where

w = 2p × finj
EQUATION2512 V1 EN

The injected frequency finj of the square wave, is a set value, deviating from the
fundamental frequency (50 or 60 Hz). The injected frequency can be set within the
range 75 – 250 Hz with the recommended value 113 Hz in 50 Hz systems and 137
Hz in 60 Hz systems.

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Section 6 1MRK 502 027-UEN A
Impedance protection

Rseries is a resistance in the REX061 unit used to protect against overvoltage to the
injection unit. Such overvoltages can occur if the unit is fed from static excitation
system.

The injection unit REX060 is connected to the generator and to IED as shown in
figure 106.

6.5.2.3 General measurement of earth fault impedance

From the REX060 the injected voltage and current are delivered as AC voltages to
IED. The injected voltage and current is measured and analyzed in the protection
function software within IED. The measured injected voltage and current are first
processed by means of special filtering so that the signals are referred to the
injected frequency only.

The bare complex impedance is, see fig 109:

U Inj
Z bare =
I Inj
EQUATION2500 V1 EN

An equivalent circuit for the measured impedance is shown in figure 109.

ZMeasured ZBare

Z series Iinj

Rf Z shunt Uinj

IEC11000003-2-en.vsd
IEC11000003 V1 EN

Figure 109: Equivalent of the impedance measurement

In non-faulted operation Rf is very large. A “healthy” impedance is calculated as:

Z Measured = k1 × Z bare + k 2
EQUATION2501 V1 EN

For definition of k1 and k2, see figure 110

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Impedance protection

The factors k1 and k2 [Ω] are derived from measurements during commissioning,
where calibration to known fault resistance will be used to convert the
measurement to true primary impedance. The factor k1 will compensate for
transformer ratio and other factors to achieve impedance values related to the
primary system. The factor k2 [Ω] will compensate for the series impedance Zseries

The healthy impedance measured at non-faulted conditions is referred to as the


reference impedance in further text.

In IED the measured impedance is compared to the reference impedance. In case of


an earth fault, the fault impedance is estimated and compared to the set values
RAlarm and RTrip.

The measured values are transferred to the primary impedance values by taking the
actual impedance value through the complex transformation given by the equation.

Ztrue = k1 × Z measured + k2
GUID-20ADF3F6-6A89-4B5F-B0DA-9740C4FD5482 V1 EN

The factors k1 and k2 [Ω] are derived during the calibration measurements under
commissioning. As support for the calibration, the Injection Commissioning tool
must be used. This tool is an integrated part of the PCM600 tool.

In connection to this calibration, the reference impedance is also derived. In case of


a rotor earth fault with fault impedance Zf, the measured admittance is:

1 1 1
= +
Z Z ref Z f
=
1 1 1
= -
Zf Z Z ref
EQUATION2405 V1 EN

The real part gives the fault conductance.

1 æ1 1 ö
= Re ç - ÷
Rf ç ÷
è Z Z ref ø
EQUATION2421 V1 EN

RAlarm and RTrip are the two resistance levels given in the settings. The values of
RAlarm and RTrip are given in Ω.

An alarm signal ALARM is given after a set delay tAlarm if Rf < RAlarm

A start signal START is given if Rf < RTrip

See figure 112

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Section 6 1MRK 502 027-UEN A
Impedance protection

6.5.2.4 Simplified logic diagram

ROTIPHIZ
Uinj
Rshunt
2
1
3
4
6 5

I Inj u_i_ref

Z Measured
Z Bare
¸ I
Rf X
Compare & S U Inj u_u_ref
Evaluate
7
K2
K1
U
ZRef1
ZRef2 REX060

REG670
IEC10000327-2-en.vsd

IEC10000327 V1 EN

Figure 110: Simplified logic diagram for sensitive rotor earth fault protection,
injection based ROTIPHIZ

1 The sensitive rotor earth fault protection function receives amplified injected voltage and
current via the REX060 unit as two voltages signals. (Voltage inputs in the IED)
2 The phasor of injected voltage UInj and phasor of injected current IInj is calculated by using
special filter from raw samples. Observe that phasors are calculated for the injected
frequency.
3 The complex bare impedance is calculated from Uinj / Iinj.

4, 5 The complex measured impedance is derived as ZMeasured = Zbare*k1 + k2 [Ω].

6 The fault resistance (Rf) is calculated from the complex measured impedance and a
selected complex reference.
7 Selection of one (out of maximum 2) ZRef.

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1MRK 502 027-UEN A Section 6
Impedance protection

Rf tAlarm
a
a<b t ALARM
b OR

RAlarm

a TRIP
a<b
b

RTrip

IEC10000326-2-en.vsd
IEC10000326 V1 EN

Figure 111: ROTIPHIZ Alarm and trip logic

If the fault resistance Rf is smaller than RAlarm and longer than alarm delay (using
delay-on), output ALARM is set. If the fault resistance Rf is smaller than RTrip,
using internal trip time characteristic, output signal TRIP is set after the calculated
time. For trip time delay, see fig 112

When 1s filter length is used and the fault resistance is equal to the set value RTrip,
the trip time is about 10 s. If the fault resistance is estimated to be 0 Ω, the trip
delay is 2 s. For values in between, the delay follows the linear interpolation
describing the fault resistance time characteristic.

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Section 6 1MRK 502 027-UEN A
Impedance protection

Trip time

10 × FilterLength

2 × FilterLength

Fault resistance
RTrip RAlarm
IEC11000002-1-en.vsd
IEC11000002 V1 EN

Figure 112: Trip time characteristic as function of fault resistance

A third high level step for the detection of excitation system earth faults on the AC
side of the excitation rectifier is available. This step uses the network frequency (50
or 60 Hz) for the evaluation. If an earth fault occurs at the AC side of the excitation
system rectifier, there is a fundamental frequency component at the measured
voltage and current injection points.

The third high level step is not applicable if mixed signals are used, that is when
the REX060 is used for both rotor and stator earth fault protection and only two,
instead of four, analog inputs on the IED are used.

6.5.2.5 Commissioning tool ICT

The sensitive rotor earth fault protection function in IED require a number of
settings. The settings k1, k2 and the reference impedance require measurements on
the generator performed by the ICT (injection commissioning tool). The factors are
derived in connection to the calibration measurements during commissioning. ICT
is an integrated part of the PCM600 tool.

Furthermore, ICT also assists the commissioning engineer to perform a successful


installation because of its structure and validating capabilities. During installation,
commissioning and calibration, ICT performs various tests to verify that the
installation is acceptable and the calibration successful. Besides carrying out the
actual tests, ICT also provides the commissioning engineer with tips if needed
during the commissioning.

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Impedance protection

When ICT is started, rotor earth fault protection is chosen.

There are five different parts of the ICT tool to be performed at commissioning and
operation:
1. Installing
2. Calibrating
3. Commissioning
4. Monitoring
5. Auditing

Before proceeding make sure that all necessary connections are in place.

Installing
When the injection is started, check that the injected voltage and current are within
the permissible limits. If not, adjust the settings in the injection unit REX060. The
ICT tool will check automatically for slight differences between actual injected and
set injection frequency (for example, due to accuracy of the REX060 hardware).
Set manually the actual frequency value measured by ICT in the IED via PST.

The high accuracy of this frequency is essential for proper operation of the
protection under different operating conditions.

Calibrating
The calibration is based on three measurement steps:

1. The injection is made to the faultless generator and the measured complex
impedance is stored.
2. A known resistance is connected between one rotor pole (see Figure 113) and
earth. The injection is made to the generator and the measured complex
impedance is stored.
3. The one rotor pole (see Figure 113) is directly short-circuited to the earth. The
injection is made to the generator and the measured complex impedance is stored.

The sequence of the commissioning calibration measurements is shown in the


figure below.

Step 1 Step 2 Step 3

DC DC DC
Crot C rot Crot

AC AC AC

REX061 REX061 REX061


I inj I inj Iinj
RTest

IEC11000205-1-en.vsd
IEC11000205 V1 EN

Figure 113: Different steps at calibration measurements

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Impedance protection

The sequence of the calibration session follows a scheme shown in the tool.

• Calibration sequence 1: The injection must be activated and the rotor must be
left with no impedance connected. The ICT now makes consecutive
measurements until the statistical error reaches an acceptable value. This is
graphically shown in a diagram. The user stops the sequence by acceptance of
the measurement. The result is stored for later calculations.
• Calibration sequence 2: A known resistor is connected between the rotor
winding and earth. The value of the resistance is the input to ICT. The ICT
now makes consecutive measurements until the statistical error reaches an
acceptable value. This is graphically shown in a diagram. The user stops the
sequence by acceptance of the measurement. The result is stored for later
calculations.
• Calibration sequence 3: The generator rotor winding is now directly connected
to earth. The ICT now makes consecutive measurements until the statistical
error reaches an acceptable value. This is graphically shown in a diagram. The
user stops the sequence by acceptance of the measurement. The result is stored
for later calculations.

After the three measurements ICT calculates the complex factors k1 and k2. The
reference impedance RefR1 + jRefX1 is also calculated. After this the values are
downloaded to the parameter setting in PCM600. From PCM600 the settings are
downloaded to IED.

During the three measurements described above a check is made that there are
sufficient changes in the measured impedance in order to guarantee that there is no
primary fault from the beginning or other problems due to the installation or
calibration procedure.

Now the reference impedance is derived for one operational state. It might be
necessary to make measurements to derive reference impedance for other
operational cases. For information on this, see Commissioning below.

Commissioning
There is a possibility to have two different reference impedances. The need to
change the reference impedance is due to different operating conditions of the
machine.

In the commissioning part of ICT this can be done. For each operation state of
interest a measurement is performed. If the reference impedance differs from the
first one, calculated under the calibration session, the new reference impedance is
stored by the command; Submit toParameter Setting.

If more than one reference impedance are to be used, there must be a logic
configured to detect such changes in the operation states that requires a change of
reference impedance.

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Monitoring
In the monitoring part the calibration can be checked by applying the known fault
resistance and compare it with the actual function measurement. It is also possible
to identify operational states where change of reference impedance is required.

Auditing
In the auditing part calibration and commissioning reports are made.

6.5.3 Description of input signals


The inputs to the sensitive rotor earth-fault protection function block are as shown
in table 109.

Table 109: Description of various inputs


Input signal Description
USU The measured injection voltage. This signal is taken from a pre-processor block, the AI
output. The analog voltage input AI1 is linked to the phase L1 in the pre-processor
block in the Signal Matrix tool.
USI The measured injection current. This signal is taken from a pre-processor block, the AI
output. In the pre-configured version, the analog voltage input AI2 is linked to the
phase L2 in the pre-processor block in the Signal Matrix tool.
BLOCK Input to block the function
ZREFSEL The selection of any of the predefined reference impedances. There is a possibility to
change from one set reference impedance to another. Two different reference
impedances are available.

6.5.4 Description of output signals


The outputs of the sensitive rotor earth-fault protection function block are as shown
in table 110.

Table 110: Description of various outputs


Output signal Description
TRIP Common trip command signal
TRIPDC is the trip command signal at DC-side earth fault
TRIPAC is the trip command signal at AC-side earth fault
START is a common signal for both AC and DC side of exciter
STARTDC is the start signal at DC-side earth fault
STARTAC is the start signal at AC-side earth fault
ALARM Signal activated after a set time delay, if the calculated fault resistance gets lower
than the set alarm level
ERROR Error signal which is boolean with values 0 and 1
ERRSTAT Status coded signal giving type of error. See table 111
Table continues on next page

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Section 6 1MRK 502 027-UEN A
Impedance protection

Output signal Description


RAVE Measured resistance to earth in Ω at an injected frequency (real part of the complex
impedance)
XAVE Measured reactance to earth in Ω at the injected frequency (imaginary part of the
complex impedance)
FREQU Measured frequency of the injected voltage
RFAULT Estimated fault resistance in Ω
ZREF Selected reference impedance number
ZREFRE The real part (resistance) of the used reference impedance
ZREFIM The imaginary part (reactance) of the used reference impedance
URMSSTAT This signal is set true, if the measured RMS voltage is larger than the set limit
ULimRMS

ERRSTAT output signal

Convert the integer output signal to binary and see table below for interpretation of
individual bits:

Table 111: Definition of errors


ERRSTAT output integer
Priority 3 Priority 2 Priority 3 Priority 1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Interfer- Under- Under- Over- Over- Frequ- No No
ence current voltage current voltage ency current voltage
detected difference

The ERRSTAT description will be shown in clear text in ICT.

The priority of the signals is set that the group priority 1 overrides the group
priority 2 and 3, and priority 2 overrides priority 3. Note that the ERRSTAT signal
can enable several error cases at the same time.

Following errors is detected and derived in the Error block:

• B0 = Injected voltage signal not found


• B1 = Injected current signal not found
• B2 = Voltage and current signal frequency differs
• B3 = Measured total RMS voltage too high
• B4 = Measured total RMS current too high
• B5 = Injected voltage signal too low
• B6 = Injected current signal too low
• B7 = External interference voltage detected

ERRSTAT = BitToInt[B7,…,B1,B0] The priority of the error conditions that will


be flagged out:

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• Prio1 = B0, B1
• Prio2 = B3, B4, B5, B6
• Prio3 = B2, B7

6.5.5 Function block


ROTIPHIZ
USU* TRIP
USI* TRIPDC
BLOCK TRIPAC
ZREFSEL START
STARTDC
STARTAC
ALARM
ERROR
ERRSTAT
RAVE
XAVE
FREQU
RFAULT
ZREF
ZREFRE
ZREFIM
URMSSTAT

IEC10000297-2-en.vsd
IEC10000297 V1 EN

Figure 114: ROTIPHIZ function block

6.5.6 Input and output signals


Table 112: ROTIPHIZ Input signals
Name Type Default Description
USU GROUP - Injected voltage signal
SIGNAL
USI GROUP - Injected current signal (voltage over shunt)
SIGNAL
BLOCK BOOLEAN 0 Block of function
ZREFSEL INTEGER 1 Reference impedance selection

Table 113: ROTIPHIZ Output signals


Name Type Description
TRIP BOOLEAN Trip (common AC and DC side of exciter)
TRIPDC BOOLEAN Trip for DC side of exciter
TRIPAC BOOLEAN Trip for AC side of exciter
START BOOLEAN Start (common AC and DC side of exciter)
STARTDC BOOLEAN Start for DC side of exciter
STARTAC BOOLEAN Start for AC side of exciter
ALARM BOOLEAN Alarm
Table continues on next page

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Section 6 1MRK 502 027-UEN A
Impedance protection

Name Type Description


ERROR BOOLEAN Error
ERRSTAT INTEGER b7=Interf,b6=I<,b5=U<,b4=IR>,b3=UR>,b2=F
Diff,b1=NoI,b0=NoU
RAVE REAL Measured resistance to earth in Ohm at inj freq
XAVE REAL Measured reactance to earth in Ohm at inj freq
FREQU REAL Measured frequency of injected voltage into rotor
RFAULT REAL Estimated fault resistance in Ohm
ZREF INTEGER Selected reference impedance number
ZREFRE REAL Used reference impedance real part in Ohm
ZREFIM REAL Used reference impedance imaginary part in Ohm
URMSSTAT BOOLEAN RMS voltage status, TRUE when > ULimRMS

6.5.7 Setting parameters


Table 114: ROTIPHIZ Group settings (basic)
Name Values (Range) Unit Step Default Description
Operation Off - - Off Operation (On / Off) of function
On
RTrip 100 - 100000 ohm 1 1000 Trip limit of fault resistance in Ohm
RAlarm 100 - 1000000 ohm 1 10000 Alarm limit of fault resistance in Ohm
tAlarm 0.00 - 600.00 s 1.00 30.00 Alarm time delay
FactACLim 0.01 - 2.00 - 0.01 0.25 Scale factor for rotor earth fault on AC
side of exciter
tTripAC 0.000 - 60.000 s 1.000 10.000 Time delay for trip on AC side of exciter
ULimRMS 1 - 1000 V 1 100 RMS voltage level

Table 115: ROTIPHIZ Group settings (advanced)


Name Values (Range) Unit Step Default Description
FreqInjected 75.000 - 250.000 Hz 0.001 113.000 Injected frequency

Table 116: ROTIPHIZ Non group settings (basic)


Name Values (Range) Unit Step Default Description
k1Real -10000000000.000 - 0.001 10000.000 Multiplication factor k1 for calibration,
- 10000000000.000 real part
k1Imag -10000000000.000 - 0.001 0.000 Multiplication factor k1 for calibration,
- 10000000000.000 imaginary part
k2Real -10000000000.000 ohm 0.001 0.000 Addition factor k2 for calibration, real
- 10000000000.000 part in Ohm
k2Imag -10000000000.000 ohm 0.001 0.000 Addition factor k2 for calibration,
- 10000000000.000 imaginary part in Ohm
Table continues on next page

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Impedance protection

Name Values (Range) Unit Step Default Description


RefR1 0.001 - ohm 0.001 1000000.000 Reference resistance R1 in ohm
1000000000.000
RefX1 -1000000.000 - ohm 0.001 2000.000 Reference reactance X1 in ohm
1000000.000
RefR2 0.001 - ohm 0.001 1000000.000 Reference resistance R2 in ohm
1000000000.000
RefX2 -1000000.000 - ohm 0.001 2000.000 Reference reactance X2 in ohm
1000000.000

Table 117: ROTIPHIZ Non group settings (advanced)


Name Values (Range) Unit Step Default Description
FilterLength 1s - - 1s Length of filter buffer
2s

6.5.8 Technical data


Table 118: ROTIPHIZ technical data
Function Range or value Accuracy
Fault resistance sensitivity Can be reached 500 kΩ
Typically 50 kΩ
Injection frequency (75.000 - 250.000) Hz ±0.1 Hz
Trip limit of fault resistance (100 - 100000)Ω 5% of 1 kΩ at Rf ≤ 1 kΩ
5% of set value at 1 kΩ < Rf ≤ 20 kΩ
10% of set value at Rf > 20 kΩ

Alarm limit of fault resistance (100 - 1000000)Ω 5% of 1 kΩ at Rf ≤ 1 kΩ


5% of 10 kΩ at 1 kΩ < Rf ≤ 20 kΩ
10% of set value at 20 kΩ < Rf ≤ 200 kΩ

Operate time, start 1.00 s typically -


Operate time, trip 2.00 s typically -
Alarm time delay (0.00 - 600.00) s ±0.5% ±10 ms

6.6 100% stator earth fault protection, injection based


STTIPHIZ

Function description IEC 61850 IEC 60617 ANSI/IEEE C37.2


identification identification device number
100% stator earth fault protection, STTIPHIZ Rse< 64S
injection based

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Impedance protection

6.6.1 Introduction
The 100% stator earth-fault protection STTIPHIZ is used to detect earth faults in
the stator windings of generators and motors. STTIPHIZ is applicable for
generators connected to the power system through a unit transformer in a block
connection. An independent signal with a certain frequency different from the
generator rated frequency is injected into the stator circuit. The responce of this
injected signal is used to detect stator earth faults.

To implement the above concept, a separate injection box is required. The injection
box generates a square wave voltage signal which for example can be fed into the
secondary winding of the generator neutral point voltage transformer or grounding
transformer. This signal propagates through this transformer into the stator circuit.

The magnitude of the injected voltage signal is measured on the secondary side of
the neutral point voltage transformer or grounding transformer. In addition, the
resulting injected current is measured through a resistive shunt located within the
injection box. These two measured values are fed to the IED. Based on these two
measured quantities, the IED determines the stator winding resistance to ground.
The resistance value is then compared with the preset fault resistance alarm and
trip levels.

The protection function can not only detect the earth fault at the generator star
point, but also along the stator windings and at the generator terminals, including
the connected components such as voltage transformers, circuit breakers, excitation
transformer and so on. The measuring principle used is not influenced by the
generator operating mode and is fully functional even with the generator at
standstill. It is still required to have a standard 95% stator earth-fault protection,
based on the neutral point fundamental frequency displacement voltage, operating
in parallel with the 100% stator earth-fault protection function.

Requires injection unit REX060 and optional shunt resistor unit REX062 for
correct operation.

6.6.2 Principle of operation


The protection function is based on signal injection into a stator winding. These
square wave signals are generated in a separate injection unit REX060.

The injection signals are connected to the stator winding via:


• secondary winding of a voltage transformer (VT) located at the stator neutral
point
• open delta winding of a three-phase VT set located at generator terminals
• secondary winding of a distribution transformer (DT) located at the stator
neutral point; note that REX062 is typically required for such arrangement
• open delta winding of a three-phase grounding transformer (GT) located at
generator terminals; note that REX062 is typically required for such arrangement

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Impedance protection

In the REX060 unit the injection voltage and current signals are amplified to a
level adapted to the analogue voltage inputs of IED. In IED the measured signals
are processed and evaluation will give detection of stator faults.

6.6.2.1 Configuration principle

Figure 115 shows a typical installation for stator injection.

10

4 Step-up
Transformer

U>

Uinj 1

Rshunt
7 5

~ Generator

6
100% SEF

I
RN

U
2
9 REX060/SIM module 8

95 % SEF

REG670 IEC11000067-2-en.vsd
Generator Protection Panel
IEC11000067 V1 EN

Figure 115: Example installation for stator injection

1 Generator unit consisting of a synchronous generator and a step-up transformer


2 Grounding resistor for the stator winding
3 Neutral point VT which is used as injection point and also to provide galvanic separation
between primary circuit and injection equipment
4 Cable used to inject the square-wave signal into the stator circuit
5 Connection for measurement of injected current. This signal is amplified in REX060 before it is
given to REG670 for evaluation.
6 Cable for measurement of injected voltage at the injection point. This signal is amplified in
REX060 before it is given to REG670 for evaluation.
7 Two VT inputs into REG670 which are used to measure injected current and voltage
8 Cable for 95% stator earth-fault protection
9 Separate VT input in REG670 used for 95% stator earth-fault protection
10 Protection for excessive over-voltages posed by generator. REX060 can withstand without
damage maximum voltage of 120V and when used together with REX062 up to 240V.

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Section 6 1MRK 502 027-UEN A
Impedance protection

The injection unit REX060


IED and
Injection Top view Power Back view Front view
connectors connector Keylock
LED

X11 X61 X81


1 1 1

Injection Stator
Injection Rotor
18 18
X62 X82

PSM
1 1

5 5

Power

Stator

Rotor
Backplane

Front-plate Injection LED Injection switch


HMI with logic

IEC11000015-1-en.vsd
IEC11000015 V1 EN

Figure 116: Injection unit REX060

The REX060 unit is a common unit that can be equipped for either rotor or stator
earth fault protection, or for both. The REX060 has specific injection modules for
rotor and stator protection. The REX060 generates square wave signals, where one
is used for injection to the stator neutral point and the other to the field winding
circuit (rotor circuit), if configured for both stator and rotor protection. The injected
voltages and currents are measured by the unit and amplified, giving voltage
signals both for the injected voltage and current, and adapted to the analogue inputs
of IED. The injection unit REX060 shall be located close to the IED.

For the stator earth fault protection, there are some settings necessary for REX060:

• System frequency: 50/60 Hz


• Injected frequency for stator neutral point is settable in 1 Hz steps 50 – 250 Hz.
• VT/DT maximum fundamental frequency voltage during earth fault in the
stator winding

REX060 will also continuously check the measured signal for detection of
saturation which could cause error in the evaluation in IED. If saturation level is
reached, a binary output contact is activated, which is connected to IED. Also other
errors in injection will activate another output contact to IED for blocking the
function.

Stator injection output is protected against voltages exceeding maximum operating


range (10% of rated VT/DT) by a relay blocking the injection circuit. This blocking
remains blocked by stored status in non-volatile memory. Note REX060 is
designed to cope with such voltages of up to 120V. When optional REX062
resistor unit is used, REX060 can cope with voltages of up to 240V at injection point.

The output is also protected by a fuse. If this fuse is blown, it is caused by external
voltage source, since the injection unit cannot provide enough energy to blow this
fuse.

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Refer to the Hardware section in this manual for a detailed description of REX060.

6.6.2.2 Generator system earthing methods

There are several principles for system earthing of synchronous generators. The
choice of earthing method depends on different factors:

• Limitation of earth fault current at stator earth fault


• Damping of transient overvoltages in the generator system
• Required insulation level to withstand overvoltage in “healthy” phases at
single phase earth fault
• Δ or Y coupled stator windings
• Connection of a single generator via a step up transformer or connection of
more than one generator via a common step up transformer

Normally the generator system has some kind of high resistance earthing, giving
earth fault current within the range 5 – 20 A, thus preventing serious damages in
case of stator earth faults. Direct earthing will give too high earth fault current
level. Isolated generator system will give risk of transient overvoltages.

Below some alternatives for generator system earthing are shown;

A B C
IEC110000066-1-en.vsd
IEC11000066 V1 EN

Figure 117: Generator earthing alternatives

A High-resistance earthing with a neutral point resistor


B Effective high-resistance earthing via a distribution transformer
C High-resistance earthing via a delta, grounded-wye transformer

These earthing alternatives are characterized by the following properties:

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Impedance protection

A: High-resistance earthing with a neutral point resistor

This earthing method utilizes a high resistance in the primary circuit by inserting
resistor RN between the generator neutral and the ground. The actual resistance
value of RN is generally in order of kΩ. Such high resistance is required in order to
limit the primary earth fault current to a quite small value (i.e. always < 20A and
quite often < 10A primary). Actual primary earth fault current can be calculated as
follows:

U G _ Ph - Ph
I =
3 × RN
EF_Max

EQUATION2515 V1 EN

where:
RN is the ohmic value of the primary resistor

UG_Ph-Ph is the protected generator rated phase-to-phase voltage

Typically a VT is connected in parallel with this resistor in order to measure


voltage in the stator neutral point. This VT typically has rating around 100VA and
rated secondary winding voltage of up to 120V. Note that maximum voltage on the
secondary side of this VT for an earth fault at generator terminals can be calculated
as follows:

U G _ Ph - Ph U2
U EF_Max = ×
3 U1
EQUATION2516 V1 EN

where:
U2/U1 is the turn (i.e. rated voltage) ratio of the VT
UG_Ph-Ph is the protected generator rated phase to phase voltage

B: Effective high-resistance earthing via a distribution transformer

This earthing method utilizes a distribution transformer that provides high


resistance in the primary circuit by utilizing a small resistor RN connected to the
secondary winding of the distribution transformer. The primary winding of the
distribution transformer is connected between the generator neutral and ground.
The actual resistance value RN is generally extremely small (i.e. typically < 1Ω);
however, the imposed ohmic value to the primary circuit becomes quite high (i.e.
in the order of kΩ). The equivalent resistance in the primary circuit can be
calculated as follows:

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Impedance protection

2
æ U1 ö
REq = ç ÷ × RN
èU2 ø
EQUATION2517 V1 EN

where:
U1/U2 is the turn (i.e. rated voltage) ratio of the distribution transformer
RN is the ohmic value of the resistor connected to the secondary winding

The distribution transformer typically has rating of several kVA (e.g. 33kVA) and
rated secondary winding voltage of up to 240V. Note that maximum voltage on the
secondary side of the distribution transformer for an earth fault at generator
terminals can be calculated as follows:

U G _ Ph - Ph U2
U EF_Max = ×
3 U1
EQUATION2516 V1 EN

where:
U2/U1 is the turn (i.e. rated voltage) ratio of the distribution transformer
UG_Ph-Ph is the protected generator rated phase to phase voltage

Note that in case of an earth fault in the stator, the secondary current through the
RN resistor will be often in order of couple of hundred amperes. This maximum
secondary current can be calculated as follows:

U EF _ Max
I EF _ Sec =
RN
EQUATION2518 V1 EN

C: High-resistance earthing via a delta, grounded-wye transformer

This earthing method utilizes a specially constructed three-phase, five-limb power


transformer that provides high resistance in the primary circuit by utilizing a
relatively small resistor RN connected to the secondary open-delta connected
windings. The primary windings of this transformer is star (i.e. wye) connected and
this neutral point is directly connected to ground. The actual resistance value RN is
relatively small (i.e. typically < 5Ω); however, the imposed ohmic value to the
primary circuit becomes quite high (i.e. in the order of kΩ). The equivalent
resistance in the primary circuit can be calculated as follows:

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Section 6 1MRK 502 027-UEN A
Impedance protection

2
æ U1 ö
REq = ç ÷ × RN
è 3 ×U 2 ø
EQUATION2519 V1 EN

where:
U1/U2 is the turn (i.e. rated voltage) ratio of one phase of the power transformer, e.g.

8 kV
3
500V
3
EQUATION2521 V1 EN

RN is the ohmic value of a resistor connected to the secondary open-delta windings

The three-phase power transformer typically has rating of several tens of kVA (e.g.
129kVA) and rated secondary winding voltage of up to 550V. Note that maximum
voltage across secondary resistor RN for an earth fault at generator terminals can
be calculated as follows:

U2
U EF_Max = 3 ×U G _ Ph - Ph ×
U1
EQUATION2520 V1 EN

where:
U2/U1 is the turn (i.e. rated voltage) ratio of one phase of the power transformer, e.g.

500V
3
8 kV
3
EQUATION2522 V1 EN

UG_Ph-Ph is the protected generator rated phase to phase voltage

Note that in case of an earth fault in the stator, the secondary current through the
RN resistor will be often in order of couple of hundred amperes. This maximum
secondary current can be calculated as follows:

U EF _ Max
I EF _ Sec =
RN
EQUATION2518 V1 EN

For all the alternatives the 100% stator earth fault protection can be applied.

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Impedance protection

6.6.2.3 100% Stator earth fault protection function

The injection to the stator is schematically shown in figure 118. It should be


observed that in this figure injection equivalent circuit is also shown with all
impedances and injection generator related to the primary side of the neutral point
voltage transformer. Points a & b indicate connection terminals for the injection
equipment. Similar equivalent circuit can be drawn for all other types of generator
stator earthing shown in latter figures.

Z Bare

Z Measured
Z series Iinj
Cstat
a +
R fault
Û UN
Rf Cstat RN ZmT Uinj

-
b
Iinj
Stator Reference
+ a Impedance ZRef

RN Uinj

- b
IEC11000008-4-en.vsd

IEC11000008 V1 EN

Figure 118: High-resistance generator earthing with a neutral point resistor

There are some alternatives for connection of the neutral point resistor as shown in
figure 119 (low voltage neutral point resistor connected via a DT).

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Section 6 1MRK 502 027-UEN A
Impedance protection

Cstat

Iinj
a
+

RN Uinj

-
b

IEC11000009-2-en.vsd

IEC11000009 V1 EN

Figure 119: Effective high-resistance generator earthing via a distribution


transformer

Another alternative is shown in figure 120 (High-resistance earthing via a delta,


grounded-wye transformer). In this case the transformer must withstand the large
secondary current caused by primary earth fault. The resistor typically has to be
divided as shown in figure 120 to limit the voltage to the injection equipment in
case of earth fault at the generator terminal. This voltage is often in the range 400 –
500 V. As the open delta connection gives three times the zero sequence phase
voltage this gives too high voltage at the injection point if the resistance is not
divided as shown in the figure 120 . By dividing the resistor in two parts it shall be
ensured that maximum voltage imposed back on injection equipment is equal to or
less than 240V.

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1MRK 502 027-UEN A Section 6
Impedance protection

I inj
a
+
RN
C stat U inj
-
b

IEC11000010-3-en.vsd
IEC11000010 V1 EN

Figure 120: High-resistance generator earthing via a delta, grounded-wye


transformer

It is also possible to make the injection via VT open delta connection, as shown in
figure 121.

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Section 6 1MRK 502 027-UEN A
Impedance protection

U1 / U2
Y
Y
Y
I inj
a
+
Rd U inj

-
C stat b

2
æU ö
R d >>çç 1 ÷÷ × R N
èU2 ø

RN

IEC11000011-3-en.vsd

IEC11000011 V1 EN

Figure 121: Injection via open delta VT connection

It must be observed that the resistor Rd is normally applied for ferro-resonance


damping. The resistance Rd is will have very little contribution to the earth fault
current as it has high resistance. This injection principle can be used for
applications with various generator system earthing methods. It is therefore

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1MRK 502 027-UEN A Section 6
Impedance protection

recommended to make the injection via the open delta VT on the terminal side in
most applications.

Accuracy for STTIPHIZ is installation dependent and it mainly depends on the


characteristic of grounding or voltage transformer used to inject signal into the
stator. Note that large variation of the ambient temperature and variation of stator
capacitance and conductance to ground between standstill and fully loaded
machine will also limit the possible setting level for the alarm stage. As a
consequence 10 kΩ sensitivity can be typically reached without problem.
Depending on particular installation alarm sensitivity of up to 50 kΩ may be
reached at steady state operating condition of the machine.

Note that it is possible to connect two REG670 in parallel to the REX060 injection
unit in order to obtain redundant measurement in two separate IEDs. However, at
commissioning both REG670 IEDs must be connected during calibration procedure.

6.6.2.4 General measurement of earth fault impedance

From the REX060 the injected voltage and current are delivered as AC voltages to
IED. The injected voltage and current is measured and analyzed in the protection
function software within IED. The measured injected voltage and current are first
processed by means of special filtering so that the signals are referred to the
injected frequency only.

The bare complex impedance is, see fig 118:

U Inj
Z bare =
I Inj
EQUATION2500 V1 EN

An equivalent circuit for the measured impedance is shown in figure 109.

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Section 6 1MRK 502 027-UEN A
Impedance protection

ZMeasured ZBare

Z series Iinj

Rf Z shunt Uinj

IEC11000003-2-en.vsd
IEC11000003 V1 EN

Figure 122: Equivalent of the impedance measurement

In non-faulted operation Rf is very large. A “healthy” impedance is calculated as:

Z Measured = k1 × Z bare + k 2
EQUATION2501 V1 EN

For definition of k1 and k2, see figure 110

The factors k1 and k2 [Ω] are derived from measurements during commissioning,
where calibration to known fault resistance will be used to convert the
measurement to true primary impedance. The factor k1 will compensate for
transformer ratio and other factors to achieve impedance values related to the
primary system. The factor k2 [Ω] will compensate for the series impedance Zseries

The healthy impedance measured at non-faulted conditions is referred to as the


reference impedance in further text.

In IED the measured impedance is compared to the reference impedance. In case of


an earth fault, the fault impedance is estimated and compared to the set values
RAlarm and RTrip.

If the measured impedance is larger than the setting openCircuitLimit, the output
OPCIRC is set TRUE. If OPCIRC is set, it means there is a strong likelihood that
the generator neutral resistor is not anymore connected to ground, since only the
capacitive part in the circuit is left. The open circuit is only applied on the stator
winding protection. To make the open circuit limit more stable a hysteresis is
added. If OPCIRC is TRUE, the measured fault impedance must drop below open
circuit limit * (1 - OpenCircLim) to reset. The hysteresis is hidden and set to a
default value of 10% of open Circuit limit for the stator.

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Impedance protection

Open- circuit
characteristics
no open- circuit open- circuit

Open Circuit
Hysteresis

{Z } re
0 Measured

openCircuitLimit

IEC11000073-1-en.vsd
IEC11000073 V1 EN

Figure 123: Open circuit characteristics

Blocking: The output OPCIRC is blocked during an error occurring and during
initialization of function.

Detailed Set: If the total measured real part of the impedance is greater than the
setting OpenCircLim the output OPCIRC is TRUE, see figure 109.

6.6.2.5 Measuring reference impedance

The healthy impedance is equal to the parallel connection of the neutral point
resistor (RN), the capacitive reactance between the stator windings and earth (1/
ωCstat), the transformer magnetization impedance (ZmT) and the earth fault
resistance (Rf). The series resistance in the injection circuit is eliminated by k2. Rf
is very large in the non-faulted case and the measured impedance is equal to the
stator reference impedance:

1 1 1
= + jw C stat +
Z ref RN Z mT
EQUATION2502 V1 EN

Where

w = 2p × finj
EQUATION2503 V1 EN

The injected frequency finj of the square wave, is a set value, deviating from the
fundamental frequency (50 or 60 Hz). The injected frequency can be set within the
range 50 – 250 Hz with recommend value 87 Hz in 50 Hz systems and 103 Hz in
60 Hz systems.

The reference impedance can vary depending on the operational state. The reason
for this can be the following:

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Impedance protection

• The influence from the impedance ZmT will be different when the generator is
stand-still and when it is in operation
• The capacitance to earth will vary if the generator breaker is open or closed
• The capacitance will vary if the generator is energized or not depending on
stator end winding corona protection
• Non-linearity of used injection transformer, different properties at low and
high total voltage and temperature changes
• Impedance to ground is affected by auxiliary loads connected between
generator and unit transformer. If these loads vary, the estimated earth fault
resistance will be affected.

The difference from the first reference impedance is identified by monitoring


impedance (RAVE + jXRAVE) during different operation modes. This impedance is
available as a service value from the stator function both on built-in HMI and in
ICT tool. If the difference is significant more than one reference impedance is
required. In the ICT up to five different sets of reference impedances can be
derived during commissioning for different states of operation and downloaded to
the protection function as different values of the reference impedance; RefRn and
RefXn where n = 1, 2, and up to 5. Switching of reference impedance can be made
automatically.

During commissioning ICT also makes “cross-calculations” between acquired


references, giving basically the calculated fault resistance between each existing
reference combination. This would be the fault resistance measured by the function
when the reference change occurs from one reference to another if the real
generator impedance stays the same, in other words a worst case scenario.

RMS voltage (rmsVolt) value at the injection point can be used for detecting when
a reference needs to be changed and logical outputs can be set to reflect whether
the RMS voltage is higher or lower than a prescribed value. There is one such
output for the voltage signal and one for the current signal. It is advantageous to
use RMS to determine a change of machine condition because the RMS makes a
distinction between the measured values and the total amplitude of the signal. The
standstill condition only contains the injected frequency, while the full load
condition and full speed condition contains other frequencies, which amplitudes
may change under varying machine conditions.

In case of a stator earth fault with fault impedance Zf the measured admittance will
be:

1 1 1
= +
Z Z ref Zf
EQUATION2513 V1 EN

and this gives:

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1MRK 502 027-UEN A Section 6
Impedance protection

1 1 1
= -
Zf Z Z ref
EQUATION2514 V1 EN

and the real part gives the fault conductance:

1 æ1 1 ö
= Re ç - ÷
Rf ç ÷
è Z Z ref ø
EQUATION2421 V1 EN

In the settings there are given two resistance levels:

• RAlarm given in Ω. If

R f < RAlarm
EQUATION2524 V1 EN

an alarm signal ALARM is given after a set delay tAlarm.


• RTrip given in Ω. If

R f < RTrip
EQUATION2523 V1 EN

a start signal START is given.

If the fault resistance is slightly below the set value RTrip the trip time will be
about 10 s with default filter length of 1 s. If the fault resistance is estimated to 0 Ω
the trip delay will be 2 s with default filter length of 1 s. For values in between the
delay will follow linear interpolation describing the fault resistance time relation,
as shown in figure 124.

Note that actual tripping time is dependent on the set parameter FilterLength which
has default value of 1s.

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Section 6 1MRK 502 027-UEN A
Impedance protection

Trip time

10 × FilterLength

2 × FilterLength

Fault resistance
RTrip RAlarm
IEC11000002-1-en.vsd
IEC11000002 V1 EN

Figure 124: Trip time characteristic as function of fault resistance

During run-up and shut down of the generator, i.e. when the rotational speed of the
generator changes, there will occur harmonic voltages with varying frequency at
the injection equipment connection point (for example see voltage generator Un in
Figure 118). If such frequencies interfere with the injected frequency this might
create an error in the fault resistance estimation. Such situations are identified in
the function and the function is automatically stabilized to prevent unwanted
operation of the protection.

In connection with this calibration the reference impedance is also derived.

It is possible to have up to five different reference impedances. The need to change


reference impedance is due to different operating conditions for the generator, for
instance:
1. Generator stand still
2. Generator running, not synchronized to the power network
3. Generator in normal operation, synchronized to the power network

The following automatic choice for the actual reference impedance can for
example be made:

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1MRK 502 027-UEN A Section 6
Impedance protection

• Generator voltage < set value and generator circuit breaker open: Reference
impedance 1
• Generator voltage > set value and generator circuit breaker open: Reference
impedance 2
• Generator voltage > set value and generator circuit breaker closed: Reference
impedance 3

The monitoring, enabled in ICT, will give indication if several reference


impedance values are needed.

From the measured impedance the stator earth fault resistance can be estimated
since the reference impedance is known. An alarm level (Ω) is set at a higher value
and the ALARM signal is activated after a set alarm delay time. A trip level (Ω) is
also set at a lower value. When the trip level is reached a TRIP signal is activated
as shown in figure 124.

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Section 6 1MRK 502 027-UEN A
Impedance protection

6.6.2.6 Simplified logic diagram

STTIPHIZ
Uinj
Rshunt
2
1
3
4
6 5

I Inj u_i_sef

Rf Z Measured
Z Bare I
X
Compare & S U Inj u_u_sef
Evaluate
K2 K1
U
ZRef1
7 ZRef2
ZRef3 REX060
ZRef4
SELECT REFERENCE
ZRef5

tON=0.5s UN un
95% Trip a U
t a>b
b

UN> = 5% 8
9
95% Stator earth fault protection
REG670
IEC10000325-2-en.vsd

IEC10000325 V1 EN

Figure 125: Simplified logic diagram for 100% stator earth fault protection
STTIPHIZ

1 The 100% stator earth fault protection function receives amplified injected voltage and
current via the REX060 unit as two voltage signals. (Voltage inputs in the REG670).
2 The phasor of injected voltage UInj and phasor of injected current IInj is calculated by using
special filter from raw samples. Observe that phasors are calculated for the injected