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This article explains the architecture and operation of pipelined analog-to-digital converters (ADCs). It discusses key performance characteristics such as architecture, latency, digital error correction, component accuracy, and digital calibration. The article also briefly compares pipelines ADCs to other data converter architectures. The pipelined analog-to-digital converter (ADC) has become the most popular ADC architecture for sampling rates from a few megasamples per second (Msps) up to 100Msps+. Resolutions range from eight bits at the faster sample rates up to 16 bits at the lower rates. These resolutions and sampling rates cover a wide range of applications, including CCD imaging, ultrasonic medical imaging, digital receivers, base stations, digital video (for example, HDTV), xDSL, cable modems, and fast Ethernet. Applications with lower sampling rates are still the domain of the successive approximation register (SAR) and integrating architectures, and more recently, oversampling/sigma-delta ADCs. The highest sampling rates (a few hundred Msps or higher) are still obtained using flash ADCs. Nonetheless, pipelined ADCs of various forms have improved greatly in speed, resolution, dynamic performance, and low power in recent years. Analog-to-digital converters (ADCs) are key design blocks in modern microelectronic digital communication systems. With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, lowvoltage ADCs that can be realized in a mainstream deep-submicron CMOS technology. Intended for embedded communication applications, specifications of these converters emphasize high dynamic range and low spurious spectral performance. For example, the worst-case blocking specs of some wireless standards, such as GSM, dictate a conversion linearity of 14-16 bits to avoid losing a weak received signal due to distortion artifacts. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons.

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1.1 PIPELINED ADC ARCHITECTURE

FIGURE 1.1 PIPELINED ADC WITH FOUR 3-BIT STAGES In this schematic, the analog input, VIN, is first sampled and held steady by a sample-and-hold (S&H), while the flash ADC in stage one quantizes it to three bits. The 3-bit output is then fed to a 3-bit DAC (accurate to about 12 bits), and the analog output is subtracted from the input. This "residue" is then gained up by a factor of four and fed to the next stage (Stage 2). This gained-up residue continues through the pipeline, providing three bits per stage until it reaches the 4-bit flash ADC, which resolves the last 4LSB bits. Because the bits from each stage are determined at different points in time, all the bits corresponding to the same sample are time-aligned with shift registers before being fed to the digital-error-correction logic. Note when a stage finishes processing a sample, determining the bits, and passing the residue to the next stage, it can then start processing the next sample received from the sample-and-hold embedded within each stage. This pipelining action is the reason for the high throughput.

1.2 DIGITAL ERROR CORRECTION Most modern pipelined ADCs employ a technique called "digital error correction" to greatly reduce the accuracy requirement of the flash ADCs (and thus the individual comparators). In Figure 1, notice that the 3-bit residue at the summation-node output has

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when there is no error in the first 3-bit conversion in Stage 1). the extra bits are also discarded to give either 14 bits or 16 bits overall.a dynamic range one-eighth that of the original Stage 1 input (VIN). As long as this gained-up residue does not over range the subsequent 3-bit ADC. it can be proven that the LSB code generated by the remaining pipeline (when added to the incorrect 3-bit MSB code) will give the correct ADC output code.3 DIGITAL CALIBRATION The MAX1200 (16-bit. the input to Stage 2 occupies only half the range of the 3-bit ADC in Stage 2 (that is. 1. If one of the comparators in the first 3-bit flash ADC has a significant offset when an analog input close to the trip point of this comparator is applied. Each device is a CMOS pipelined ADC with four 4-bit stages (with 1-bit overlap) and a 5-bit flash ADC at the end. The extra one to three bits are required by the digital calibration to quantize the error terms to greater accuracy than the ADC itself. each stage (Stages 1 to 4) effectively resolves only two bits. because the interstage gain is only 4. MAX1201 (14-bit 2Msps). The implication is that none of the flash ADCs in Figure 1 has to be as accurate as the entire ADC. as mentioned above. 1Msps) family¹ of ADCs employs digital calibration to ensure excellent accuracy and dynamic performance. Although each stage generates three raw bits in the Figure 1 example. The extra bit is simply to reduce the size of the residue by one half. allowing extra range in the next 3-bit ADC for digital error correction. thus producing a different residue. 1Msps). Thus the final stage only needs to be more than 4. then an incorrect 3-bit code and thus an incorrect 3-bit DAC output would result. This process is called "1-bit overlap" between adjacent stages. The effective number of bits of the entire ADC is therefore 2 + 2 + 2 + 2 + 4 = 12 bits. Any error made at that conversion is suppressed by the large (44) cumulative gain preceding the 4-bit flash. the 3-bit flash ADCs in Stages 1 through 4 require only about four bits of accuracy. yet the subsequent gain is only 4. The digital error correction will not correct for errors made in the final 4-bit flash conversion. In fact. giving a total of 3 + 3 + 3 + 3 + 5 = 17 raw bits (see Figure 3). and MAX1205 (14bit. Therefore. 3 .bits accurate.

once the second and third MDAC are calibrated. During normal conversions. those error terms are recalled from the RAM and used to adjust the outputs from the digitalerror-correction logic. they are used to calibrate the first MDAC. FIGURE 1. During normal conversions. The third-stage output is digitized by the remaining pipelined ADC. The third-stage output is digitized by the remaining pipelined ADC.Calibration starts from the MDAC in the third stage. beyond the third stage the MDAC error terms are small enough that calibration is not needed. 4 . Likewise. Averaging is used (especially in the first and second MDAC) to ensure that the calibration is noise-free. those error terms are recalled from the RAM and used to adjust the outputs from the digital-error-correction logic. Averaging is used (especially in the first and second MDAC) to ensure that the calibration is noise-free. Once the third MDAC is calibrated. Once the third MDAC is calibrated.2 MAX1200 PIPELINED ADC ARCHITECTURE. it can be used to calibrate the second MDAC in a similar fashion. it can be used to calibrate the second MDAC in a similar fashion. Likewise. once the second and third MDAC are calibrated. they are used to calibrate the first MDAC. and the error terms are stored in on-chip RAM. and the error terms are stored in on-chip RAM.

This is simply because in a flash ADC the number of comparators increases by a factor of 2 for every extra bit of resolution. As a result.1. must provide gains that do not need to be linear or accurate. only the comparators' trip points must be accurate. A pipelined ADC. however. A purely flash ADC.2 LITERATURE SURVEY 2. and still slower for very high resolutions (14 to 16 bits). has a large bank of comparators. from the MSB down to the LSB. In contrast. this comparator must be fast (clocked at approximately the number of bits x the sample rate) and as accurate as the ADC itself.2 VERSUS FLASH Despite the inherent parallelism. whose output is updated by previously decided bits and successively approximates the analog input. The preamps. however. high-accuracy comparator bit by bit. each comparator must be twice as accurate. a pipelined ADC cannot match the speed of a well-designed flash ADC.1 VERSUS SAR In a successive approximation register (SAR) ADC. Although there is only one comparator in a SAR. and thus significant linear settling time. 2. the bits are decided by a single high-speed. low-gain preamps followed by a latch. the MAX104/MAX106/MAX108). It is much harder to find a 10-bit flash. each consisting of wideband. Extremely fast 8-bit flash ADCs (or their folding/interpolation variants) do exist with sampling rates as high as 1. while 12-bit (or above) flash ADCs are not commercially viable products. employs a parallel structure in which each stage works on 1 to a few bits (of successive samples) concurrently. This serial nature of SAR limits its operating speed to no more than a few Msps. none of the comparators inside a pipelined ADC needs this degree of speed or accuracy.5Gsps (for example.1. a pipelined ADC still requires accurate analog amplification in DACs and interstage gain amplifiers. In a 5 .1 PIPELINED ADC VERSUS OTHER ADCS 2. simultaneously. The SAR ADC compares the analog input with a DAC. unlike those amplifiers in a pipelined ADC.

Comparator metastability in a flash can lead to spark le-code errors. The fastest. fourth or even higher) incorporating a multi-bit ADC and multi-bit feedback DAC. a condition in which the ADC provides unpredictable. to a first order the complexity only increases linearly. high-resolution sigma-deltatype converters are not expected to have more than a few MHz of bandwidth in the near future.4 ONE-STAGE PIPELINE A pipeline ADC is a type of switched-capacitor circuit that divides the quantization of an input signal into multiple steps. The need to sample many times (for example. Sigma-delta converters trade speed for resolution. and consumes a lot of silicon area.pipeline. The digital decimation filter is also nontrivial to design. a pipelined device usually has much lower power consumption than a flash.3 VERSUS THE SIGMA-DELTA CONVERTER Traditionally.1. These specifications indicate very high-order sigma-delta modulators (for example. oversampling/sigma-delta-type converters commonly used in digital audio have a limited bandwidth of about 22 kHz. At sampling rates obtainable by both pipeline and flash converters. at least 16 times. with the resolution. but often much higher) to produce one final sample causes the internal analog components in the sigma-delta modulator to operate much faster than the final data rate. even for 16 to 18 bits of resolution. The oversampling nature of the sigma-delta converter also tends to "average out" any system noise at the analog inputs. Like pipelined ADCs. A pipeline ADC is typically less susceptible to comparator metastability. The backend digital filters take care of that task. A sigma-delta converter needs no special trimming/calibration. erratic conversion results. not exponentially. 2. however.1. Recently some high-bandwidth sigma-delta converters reached a bandwidth of 1MHz to 2MHz with 12 to 16 bits of resolution. It does this by distributing the 6 . because the sampling rate is much higher than the effective bandwidth. 2. sigma-delta converters also have latency. Their main applications are in ADSL. They also require no steep rolling-off anti-alias filter at the analog inputs.

1.1. Starting from the first 7 . T/H1 and T/H2 sample the input. like a flash ADC. The process in the analog domain is very similar to that of the one-stage pipeline. Pipeline ADCs are more power efficient than ADCs that quantize in only one step. Figure 2. the ADC is in phase 2.conversion over multiple stages so that each stage converts only a subset of the total number of bits. Within the pipeline stage. At the end of the half cycle. Figure 2. In the first half cycle (T/2). The sub-ADC takes the input and quantizes it create the upper N/2 bits. 2. The MSBs are immediately converted back into an analog signal via the Digital to Analog Converter (DAC). The upper N/2 bits are referred to as the Most Significant Bit (MSB)s. N. The flash-ADC inside the pipeline stage is called a sub-ADC as not to get mixedup with the final flash-ADC. the pipeline stages function in a two-step or two-phase cycle. In the second half cycle. and Track and Hold (T/H) T/H1 and T/H2 track the analog input.5 shows a 10-bit pipeline ADC that resolves 1-bit per stage.1 ONE-STAGE PIPELINE ADC digital output of the pipeline stage. which gets subtracted from the original analog input in the summer block to produce the quantization error for the conversion. and T/H1 and T/H2 output the voltages they sampled for the sub-ADC and summer block. which is the FIGURE 2. T/H1 and T/H2 are integrated into the summer and sub-ADC respectively. Typically. To demonstrate this.1 shows a basic one-stage N-bit pipeline ADC. _2. _1. the ADC is in phase 1.5 1-BIT/STAGE PIPELINE The procedure in can be extended to multiple pipeline stages.

2TEN-STAGE PIPELINE ADC THAT RESOLVES 1-BIT/STAGE 8 . the accuracy requirement in every subsequent stage decreases by one bit. it is added to MSBi generated previously. FIGURE 2. however. the sub-ADC generates a 1-bit output. As a single bit is generated by each subsequent stage every T/2.stage. which produces the residue output for the next stage. in the end. the input signal is sampled by the sub-ADC and the summer. It immediately gets converted back into an analog voltage so it can be subtracted from the input sample to generate the quantization error. This process ensures that. Digital circuitry in the digital domain processes the digital bits as it is outputted from each pipeline stage. The next stage and every stage afterwards repeat the cycle until all 10-bits are generated. each bit has the correct magnitude weighting and all 10 bits corresponding to a specific input sample are aligned in time. The quantization error is then amplified by the stage gain (Gi = 2) to bring it back to the input range. The sum is delayed by T/2 and the delayed sum gets scaled by the stage gain of the corresponding pipeline stage to generate the next MSBi+1. The accuracy requirement in the first pipeline stage is the same as in the one-stage pipeline. Next.

Thus. the bits from each adjacent pipeline stage overlap by half a bit and form the expected 10-bit output. After the first digital output is generated. a total of 18-bits are generated from a single input sample. In the end. To apply DEC.3: A 10-BIT 1.5-BIT/STAGE PIPELINE DEC is a very popular technique because it significantly reduces the accuracy requirements of the sub-ADC. 8 pipeline stages.5 bits. 2. is limited by the delay through a single pipeline stage. a new output is generated every clock cycle. fS = 1/T. This is demonstrated in Figure 2.7 shows a more practical version of the pipeline ADC in Figure 2.5-BIT/STAGE PIPELINE ADC WITH DIGITAL ERROR CORRECTION The pipeline ADC applies DEC and consists of a front-end S/H.6 1.2.1. FIGURE 2. T.1. which is represented by a 2-bit output. Figure 2. Each pipeline stage resolves 1.6. the conversion rate or sampling speed of a pipeline ADC. and a 2-bit flash ADC at the end. each stage contributes T/2 of latency to the pipeline ADC. 9 .Because the first input sample must propagate through the pipeline before the first 10-bit output is generated.

the loop gain of the closed-loop circuit.loop circuit where the closed-loop gain is equal to the stage gain. must be: (3. In Section 3. The settling accuracy refers to how close the residue output settles to it’s intended value and therefore.1. sets the settling accuracy. This is because a higher open-loop gain results in a more accurate stage gain and in turn. the accuracy of the stage gain determines the settling accuracy of the residue signal.2. It’s configured in a closed. The three opamp design parameters that are discussed next are gain. 3.2.3. it can limit the accuracy of the ADC. opamp design considerations will be presented. 10 . Finally.1) where β is the feedback factor of the closed-loop circuit and 1 LSB = 1/2N. Aβ. an example design of a N-bit pipeline ADC is described in Section 3. To ensure the residue settles to within Δ LSB. the opamp’s open-loop gain. bandwidth.3 SYSTEM DEVELOPMENT PIPELINE ADC BUILDING BLOCKS AND DESIGN METHODOLOGY This section shows how to design a pipeline ADC for a specific operating speed and (thermal noise and settling) accuracy. as the name suggests.1 GAIN As discussed in Section 2. The loop gain.1 OPAMP DESIGN The opamp is used in the MDAC to implement the stage gain. Then in Section 3. and output swing.1. three major pipeline building blocks are characterized. ’A’. 3.1. Assuming the opamp has sufficient time to settle to it’s final value. the residue output follows a more accurate transfer function. is the gain around the opamp closed-loop circuit.

which determines how fast the residue output settles to a final value.3 OUTPUT VOLTAGE SWING Clearly. (3.5/fS.2) 3. f3dB. [8].3 sets the bandwidth of the opamp closed-loop circuit. Equation 3. 11 .2 BANDWIDTH Assuming the opamp has sufficient gain to accurately settle to it’s final value.boosting (Figure 3.2. a reasonable choice is _ = 0.1. 0. sets the settling accuracy. [1] have typically used single-stage opamps with gain.Considering there are other sources of error (e. the bandwidth of the opamp closed-loop circuit is the product of the opamp’s Gain Bandwidth (GBW) product and β: f3dB = GBW*β (3.3) Like with loop gain. the front-end S/H and first pipeline stage in a 10-bit pipeline ADC requires a loop gain of: (3.1) or two-stage Miller-compensated opamps (Figure 3.1.25 LSB. thermal noise). VCMFB is a signal generated by a CommonMode Feedback (CMFB) circuit to control the Common-Mode (CM) output voltage.2) to achieve these gains. In Figures 3. For instance.g. so that the residue settles to within 0. high opamp gain is needed at the front-end to achieve the desired settling accuracy. the opamp speed.1 and 3.5 LSB in half a sampling period. Previous publications ( [6]. The bandwidth must be high enough for the opamp to settle to a sufficiently accurate value within the required time of half a sampling period.4) 3.

of at least one overdrive voltage.2 Vpp (3. VDS.2 V and a Veff of 150 mV.3 is limited to: 2 (1.FIGURE 3.2 BUILDING BLOCKS In this section.5-bit sub-ADC and choice of comparator are presented. and its threshold. VGS. A transistor’s Veff is the difference between its gate-to-source voltage. the 1. otherwise.2 − 4Veff ) = 1.1 SINGLE-STAGE OPAMP WITH GAIN-BOOSTING The two-stage opamp has more output swing than the single-stage opamp because the output transistors in the two-stage opamp are cascoded. Vt.5) 3.1. The front. Veff .5-bit MDAC blocks are then analyzed to show that their thermal noise level sets the dynamic range of the pipeline ADC. Each transistors must have a drain-to-source voltage.end S/H and two 1. At a supply voltage of 1. the transistors drop out of saturation and the gain dramatically decreases. 12 . the differential output swing in Figure 3.

FIGURE 3. digitizes it to a sub-resolution equal to the number of bits resolved per stage. a 1.3.7.6) The total input capacitance of the sub-ADC during 1 is CiT.5-bit MDAC in Figure 2.5-bit sub-ADC is composed of two comparators and digital logic as shown in Figure 3.1.3. the sampling capacitors Cin and Cref can be made small without worrying about thermal accuracy. then from Equation 3.subADC. the sub-ADC samples the input voltage in 1 and then in 2.2. In this work.5-bit sub-ADC have thresholds at Vthres = ±Vref/4 as shown in the transfer function of the 1.4.2 THREE-LEVEL SUB-ADC The comparator used in this work is the the Charge-Distribution comparator [15] shown in Figure 3.5. The comparators in a 1.5-bit sub-ADC is used in each pipeline stage. In fact.3. If only flip-around MDACs [16] are used and only Vref is made available for the MDAC. sub ADC loads the opamp in the previous stage. The threshold of this comparator is set by: (3. which is equal to 2Cin. A 1. the smallest value Cin and Cref can be is most likely limited by the fabrication technology. The bits are used by the MDAC in _2 to calculate the residue for the next stage. 13 .1 SUB-ADC As described in Section 2. It is desirable to make Cin small because CiT. Since the sub-ADC only needs to be accurate to 2 bits.

making a fraction of Vref available on-chip reduces CiT. then Cin/Cref can be reduced to 2 and hence. Figure 3. Therefore.subADC. sub ADC. CiT. which is the total parasitic capacitance 14 . Cn2.Cin/Cref = 4. the feedback factor S/H is. and of the MDAC. in the next stage does load the S/H opamp.2 SAMPLE AND HOLD The S/H located at the front of the pipeline performs the first step of sampling the external input signal.5 shows a commonly used S/H.MDAC. sub ADC = 8Cref . 3. The opamp is also loaded by an additional capacitance.2. Cin = 4Cref and CiT. However. CiT. Cin = 2Cref and CiT. the total input sampling capacitance of the sub-ADC. In ɸ2.7) However. if an integrator MDAC [16] is used and Vref/2 is made available. Thus. The total input sampling capacitance the external source must drive in ɸ1 is CiT.3 A COMMONLY USED S/H As a result. The capacitor C S does not load the opamp because it’s top plate has no path to ground. (3.S/H = CS. sub ADC = 4Cref . FIGURE 3. the S/H opamp drives a load capacitance to hold the sampled voltage for the first pipeline stage. Phase 1 and 2 are indicated on the clock waveform in Figure 3.6.

connected to node 2 in Figure 3.2. The opamp is not used and therefore. nf . The noise from the second stage is negligible because. It consists of the drain capacitance of M11 and M13. However.nextstageMDAC + Cn2 As you can see. the second term in Equation 3. the dominate source of noise is from the opamp’s first stage in Figure 3. In _2.10 is the noise contribution from transistors generated during _1.10 accounts for the noise contributed by transistors M3/M4 and M9/M10 in Figure 3. Therefore. it is greatly reduced by the gain of the opamp. thermal noise from the transistors is sampled across CS. the total output load on the S/H opamp is: CL. both the opamp and transistors contribute thermal noise. once input-referred. the dynamic range of the pipeline ADC.subADC + CiT. Therefore. the size of the sampling and compensation capacitors set the thermal noise level and hence. Because a differential configuration is used. The noise fraction.10 is the noise contribution from the opamp’s first stage generated during _2. and the wire capacitance of the metal used to connect voutp/voutn. the term becomes 2kT/CS. 15 . as the input signal is being sampled in 1. Specifically looking at the S/H. The first term in Equation 3. is defined in Equation 3.S/H = CiT. does not contribute any noise.2.2.11 and it’s presence in Equation 3.

the thesis compares two 20 MS/s 10-bit 1.5bit/stage pipeline ADC designs: • A regular design that uses the popular flip-around MDAC in the first stage as shown in Figure 4.1: REGULAR PIPELINE ADC WITH A FLIP-AROUND MDAC IN THE FIRST STAGE • A novel design that applies front-end capacitor-sharing between the S/H and first stage MDAC as shown in Figure 4.2: PIPELINE ADC WITH CAPACITOR-SHARING FRONT-END 16 .2 FIGURE 4.2 REGULAR VERSUS CAPSHARE ADC To demonstrate the power savings.1 FIGURE 4.4 PERFORMANCE ANALYSIS 4. 4.1POWER COMPARISON This section demonstrates the power savings of the front-end capacitor-sharing technique by comparing a pipeline ADC that applies the technique to a regular pipeline ADC that does not.

13 μm technology.MDAC = CS = 120fF. The final seven stages. As indicated by Equation 3. Set the Veff of M1/M2 and M11/M12 to be 150 mV. 17 . only the opamp power will be considered.26 will be used to check that CC is within the recommended range. which is the smallest MIM capacitor allowed.25. The opamp parasitic capacitance at node 1 and 2 in Figure 3.5-bit sub-ADC. will be identical in each design to reduce the design complexity. Since most of the power is consumed in the opamps. Hence. stages 2 to 8. a reasonable Veff for M1/M2 in Figure 3.subADC. Initially set CC = CS. CiT. To minimize CiT. set Cref = 60 fF. Cn1 = Cn2 = 150 fF). Each pipeline stage use the same 1.2 is approximately 150 fF (i. Equation 3. They will use a flip-around MDAC with 60 fF sampling capacitors. Referring to Section 3. 4.1. an analysis is done to estimate and compare the power consumptions of the two designs. 4. which is the minimum size Metal Insulator Metal (MIM) capacitors in IBM 0. Later. several initial assumptions are presented: Vref = 0.2 is required to ensure that the opamp is not slew limited. An over-design factor of 1.8 V meaning the full-scale range is 1. Therefore.3 and uses the target specifications in. subADC = 4Cref . the following analysis assumes Vref/2 is available on-chip. The analysis follows the example design performed in Section 3.This thesis will concentrate on the design of the front-end S/H and first stage. allowing CiT.5x is used. the final pipeline stages have a CiT.3 ANALYSIS Next.6 Vpp.2.subADC = 240fF.4 INITIAL ASSUMPTIONS Before starting the analysis.e.

stages 2 to 8) for the capshare ADC.1) After applying an over-design factor of 1. to compute the opamp power in the front-end S/H.1 applies the capacitor values calculated above. The opamp power for stages 2 to 8 are the same as in the capshare ADC so only the steps for the S/H and first stage are presented.1: POWER OF CAPSHARE PIPELINE ADC Next. As you can see from comparing Step H in Tables 4. each opamp targets f3dB = 72. 18 . CS = CC = 300 fF.5.5 TWO-STAGE OPAMP DESIGN This section designs the opamp within each pipeline stage.5 LSB at a sampling frequency of 20 MS/s.5% power savings in the front-end S/H. the capshare ADC has a 42. From Equation 3. to compute the opamp power in the front-end S/H and first stage for the regular ADC. The corresponding opamps in the capshare and regular ADC should have the same bandwidth so that the power consumption between the capshare and regular ADC can be fairly compared. Table 4.8 MHz.4.1 and 4. TABLE 4.2 applies the capacitor values calculated above. CS = CC = 420 fF. the power for each stage is computed and compared.2. and final stages (i.e. the f3dB of the closed-loop system should be: (4. in order for the residue signal to settle within 0. Table 4.3. first stage.

7. it can be concluded that CC = 300fF for the capshare ADC and CC = 420fF for the regular ADC are acceptable choices. the assumption CC = CS was made. Since 2Cn1 = 300 fF.7) TABLE 4.26 can be rewritten as: 300 fF < Cc < CL/2 (4.1 and 4. 19 . Equation 3.Earlier in this section.2: POWER OF REGULAR PIPELINE ADC By plugging the values of CL in Tables 4.2 into Equation 4.

Table 5. Since the pipeline ADC in [1] is adaptable over a range of sampling frequencies.2 and to two other comparable designs. the capshare ADC is no longer thermally noise limited. Because the SNR is below the thermal noise level of 59. Table 5.4 MHz and a FOM as low as 0.7 mW of power and achieves a ENOB of 8.5 dB once the entire design is extracted and the post-layout parasitic capacitors are introduced.68 pJ/step.6 pJ/step when sub-sampling at fin = 13. 20 .53 MHz and fS = 20 MHz.67 bits at fS = 0.3. however. Table 5. the capshare ADC has experimentally shown that it can function at the targeted specifications in Section 4.1 DYNAMIC RANGE DEGRADATION This section debugs the capacitor-only post-layout capshare ADC to discover why the dynamic range decreases when capacitor layout parasitics are introduced. This section debugs the capacitor-only post-layout capshare ADC to discover why the dynamic range decreases when capacitor layout parasitics are introduced.4 dB to 55.7. the SNR drops from 61. a lower FOM could be achieved.6 MHz and fS = 20 MHz.4 shows the SNDR/SNR when portions of the post-layout design are extracted and simulated with.1 compares the capacitor-sharing front-end pipeline ADC in this work to the regular pipeline ADC that was designed in Section 4. the DUT consumes 4. The DUT can achieve an ENOB as high as 8.5 bits and a FOM of 0. As you can see from comparing Simulation 1 to 2. because stages 2 to 8 were not optimized. as shown in Table 4. the back-end consumes significantly more power than it should. 5.1 shows the SNDR/SNR when portions of the post-layout design are extracted and simulated with thermal noise deactivated. If the backend was scaled for optimum power consumption. The FOM is slightly higher than the targeted 0.5 CONCLUSION In conclusion.3 dB.5 pJ/step. At fin = 9. only the performance at a single fS is presented in the table.

1: SNDR AND SNR AT fin = 61/128. based on the previously sampled input. as shown in Figure 5. vout MDAC. charge from the input sampling is coupling into the capacitors used to generate the residue. creating an error in vout MDAC. there is parasitic capacitance between the two ping-pong paths. indicating that the coupling 21 .FS AFTER POST-LAYOUT EXTRACTION When there is parasitic capacitance across the sampling capacitors. In _1. If the gain constants (G1 to G9) in the digital domain.1.1. As a result. This error cannot be calibrated out because the amount of charge coupling varies based on the input voltage level sampled.TABLE 5.1: MDAC GAIN ERROR CAUSED BY PARASITICS ACROSS SAMPLING CAPACITOR Because the layout of the capshare stage is very compact. it produces a constant gain error in the MDAC’s stage gain. the ADC’s linearity suffers and the dynamic range decreases. phase A (B) is sampling the next input at the same time phase B (A) is generating the residue. Simulation 6 shows that the dynamic range improves to near the 10-bit level when the ping-ponging is turned off. The coupling should stop if one of the ping-pong phases (A or B) is shut down as that would cause the sampling of the input and generation of vout MDAC to occur on opposite clock cycles. are corrected to reflect the new MDAC stage gains. as shown in Figure 2. FIGURE 5. Consequently.

22 . This would effectively reduce the power consumption in the front-end S/H as it is loaded by only the sub-ADC and it’s opamp parasitic capacitance. The spectral plots in how the spectrum when ping-ponging is turned on and when it turned off. the opamp power consumption in every stage could be decreased by making the sub-ADC sampling capacitors Cin smaller than • 60 fF. • Because the sampling capacitance of the sub-ADC makes up a large portion of the load capacitance for each opamp. there was cross coupling between the two paths. If the design could be revised. 5. the sampling capacitors in the sub-ADC would be implemented by multiple 60 fF minimum-sized MIM capacitors placed in series to create a smaller effective capacitor. the layout of each parallel ping-pong phase would be separated so that the layout of the front-end S/H and the first stage are divided into two separate blocks.within the capshare stage was the source of the problem. which limited the dynamic range to below the thermal noise level.2 FUTURE WORK If the capshare ADC in this work could be redesigned. the following changes would be made to improve the front-end performance: • Because the two ping-pong paths within the capshare stage were layed out compactly. If the design could be revised.

In Solid-State Circuits Conference. Ahmed and D. Solid-State Circuits. K. [8] O.H. Ahmed. Johns. Wang. [2] D. Balasubramaniam and K. 2005.5mw 1.A. 2011 10th International Symposium on. 1. [4] S. Analog integrated circuit design. A 3.W. 43(7):1638 –1647.5v 10-bit pipeline adc for dvbh systems in 0. In Circuits and Systems. 30 2011-july 1 2011. 1997. 2006. D. 23 . Proceedings of the 32nd European. A pipelined 5-msample/s 9-bit analog-to-digital converter. Johns. pages 278 –279 Vol. [7] Young-Deuk Jeon. Martin. IEEE Journal of. 2006.3 mw 12 ms/s 10b pipelined adc in 90 nm digital cmos. and G. [5] H. Analog Circuits and Signal Processing. John Wiley & Sons.6 REFERENCES [1] I. feb 2005. Jongdae Kim. Burra.and Dongsoo Park. Adeniran and A. 2010. Johns and K. Springer. Jong-Kee Kwon. Martin. pages 1 – 4. page 4 pp. Demosthenous. Pipelined ADC Design and Enhancement Techniques. A 5-mw 0. 2005 IEEE International. ISCAS 2006. In Solid-State Circuits Conference. Digest of Technical Papers. [3] S.26-mm2 10-bit 20-ms/s pipelined cmos adc with multi-stage amplifier sharing technique. ISSCC. A 10 bit. [6] R. dec 1987. 1. A 19. Gray.I. Hofmann. may 2006. pages 544 –547. 22(6):954 – 961. Circuits and Systems (ISSCS). sept 2006. Seung-Chul Lee.A. Kwi-Dong Kim. A high bandwidth power scalable sub-sampling 10-bit pipelined adc with embedded sample and hold.R. 2006 IEEE International Symposium on. Solid-State Circuits.. Lewis and P. IEEE Journal of.35 /spl mu/m cmos. ESSCIRC 2006. july 2008.5b/stage pipeline adc using a fully differential current conveyor with foreground calibration. Proceedings. In Signals.

In Mixed Design of Integrated Circuits and Systems (MIXDES). and J. pages 456 –615. Paulino. A 4. Goes. Pacheco. Design of a 10-bit 40 ms/s pipelined adc using 1. N.32mm2 10b 30ms/s pipelined adc without a front-end s/h in 90nm cmos. 24 . pages 299 –302. Seung-Chul Lee. 2011 Proceedings of the 18th International Conference. 2007. In Solid-State Circuits Conference. feb 2007. Jong-Kee Kwon. ISSCC 2007. Digest of Technical Papers.[9] Young-Deuk Jeon. Figueiredo. june 2011. Kwi-Dong Kim. [10] J. M. and Jongdae Kim.7mw 0.5-bit with current-mode reference shifting. IEEE International.

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