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Tutorial on CMCs Digital IC Design Flow

Instructions for Taking a Sample Design through the Digital Flow


(0.35-micron and 0.18-micron CMOS Technologies with Black-Box Libraries)

Document ICI-096, Part of Tutorial Release V1.3 Developed by Canadian Microelectronics Corporation

May 7, 2001

Copyright 2001 Canadian Microelectronics Corporation This document may be copied by eligible universities for use by licensed individuals. This tutorial involves the use of documentation, software and technology database files. Ensure you understand the conditions governing the use of all licensed material.

LICENSE
You must be licensed to use the materials in this tutorial. Your acceptance or use of the licensed material shall constitute your acceptance of the terms of the licensing. Read the LICENSE file for more information. Note that use of this tutorial can require use of licensed software such as that from Cadence and Synopsys. Similarly, the fabrication technology is proprietary to the manufacturer. Make sure you understand the licensing conditions governing the use of the tools and technology. In general, all of the materials in this tutorial and the CAD tools are governed by non-commercial use conditions. By prior arrangement, commercial use may be possible. Contact CMC about the possibility of such an arrangement.

TRADEMARKS
Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc.; Design Analyzer, dont_touch, and dont_use are trademarks of Synopsys, Inc.
Cadence, the Cadence logo, Design Framework II, Diva, GDSII, Pearl, SKILL, Spectre, Verilog-XL, Virtuoso, and Verilog are registered trademarks of Cadence Design Systems, Inc.; Envisia Physical Design Planner and Silicon Ensemble are trademarks of Cadence Design Systems, Inc. FrameMaker is a trademark of Adobe Systems Incorporated. Star-Hspice is a trademark of Avant! Corporation. UNIX is a registered trademark of The Open Group in the United States and other countries

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TABLE OF CONTENTS

TABLE OF CONTENTS
TABLE OF CONTENTS ............................................................................................................................ iii LIST OF FIGURES .............................................................................................................................. vi INTRODUCTION ................................................................................................................................ 1 A TUTORIAL PURPOSE ...................................................................................................... 1 B CHECKLIST ...................................................................................................................... 3 C SETTING UP YOUR ENVIRONMENT ........................................................................... 4 D THE DESIGN EXAMPLE ............................................................................................... 11 E UP-FRONT ISSUES ........................................................................................................ 12 F REGISTERING YOUR TUTORIAL DESIGN WITH CMC .......................................... 17 MODULE 1: 1.1 1.2 1.3 1.4 MODULE 2: 2.1 2.2 2.3 MODULE 3: 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 MODULE 4: 4.1 4.2 MODULE 5: 5.1 5.2 5.3 5.4 SIMULATING THE RTL CODE .................................................................................... 18 Become familiar with the mult16chip design and test bench ........................................... 18 Simulate the RTL code with Verilog-XL ......................................................................... 19 View the simulator results ................................................................................................ 20 Save the waveform configuration ..................................................................................... 21 IMPORTING THE RTL CODE INTO SYNOPSYS ....................................................... 22 Start Synopsys Design Analyzer ...................................................................................... 22 Analyze and elaborate the RTL code ............................................................................... 23 Explore the Synopsys environment .................................................................................. 24 CONSTRAINING THE DESIGN .................................................................................... 26 Specify the I/O pads ......................................................................................................... 26 Define the scan style ......................................................................................................... 27 Define the output load ...................................................................................................... 28 Set maximum net transition (net slew) ............................................................................. 29 Define the clock................................................................................................................ 29 Set general compile directives .......................................................................................... 30 Propagate top-level constraints down to mult16bist module for synthesis ...................... 30 Save the constrained design .............................................................................................. 30 COMPILING THE DESIGN ........................................................................................... 32 Perform the initial compile ............................................................................................... 32 Perform an incremental compile ...................................................................................... 34 INSERTING SCAN ......................................................................................................... 37 Perform pre-insertion checks and check testability design rules ...................................... 38 Estimate fault coverage .................................................................................................... 38 Insert scan circuitry .......................................................................................................... 39 Perform final check and save the design as a gate-level Verilog netlist .......................... 39

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5.5 5.6 MODULE 6: 6.1 6.2 6.3 6.4 MODULE 7: 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 MODULE 8: 8.1 8.2 8.3 MODULE 9: 9.1 9.2 9.3 9.4 9.5 MODULE 10: 10.1 10.2 10.3 10.4 MODULE 11: 11.1 11.2 11.3 11.4 11.5 11.9

Write timing constraints 40 Create the physical test vectors ........................................................................................ 41 GATE-LEVEL SIMULATION ........................................................................................ 42 Modify or get your gate-level testbench ........................................................................... 42 Prepare the Verilog files ................................................................................................... 43 Run the simulations .......................................................................................................... 44 Insert and detect a fault ..................................................................................................... 45 FLOORPLANNNING ...................................................................................................... 47 Import the gate-level list ................................................................................................... 47 Add power pads to the design .......................................................................................... 48 Initialize the floorplan ...................................................................................................... 50 Create the ring of I/O cells ............................................................................................... 51 Define and place groups ................................................................................................... 54 Create placement sites ...................................................................................................... 56 Define special nets............................................................................................................ 57 Add power stripes (power planning) ................................................................................ 58 TIMING-DRIVEN PLACEMENT OF STANDARD CELLS ........................................ 60 Use the QPlace sequencer ................................................................................................ 60 View placement congestion .............................................................................................. 62 Perform timing analysis based on initial placement ......................................................... 62 CREATING A CLOCK TREE ........................................................................................ 65 Define the clock tree ......................................................................................................... 65 View the clock tree ........................................................................................................... 67 Write out the "golden netlist" ........................................................................................... 68 Add a power ring around the core .................................................................................... 69 Export the placed design .................................................................................................. 70 IMPORTING THE PLACED DESIGN ........................................................................... 72 Simulate the golden Verilog netlist .................................................................................. 72 Start Silicon Ensemble ..................................................................................................... 73 Import the results from Design Planner (PDP) into Silicon Ensemble ............................ 73 Import design-specific constraints .................................................................................... 74 ROUTING ........................................................................................................................ 76 Route power ...................................................................................................................... 76 Route the clock nets .......................................................................................................... 77 Perform timing-driven routing ......................................................................................... 78 Verify timing .................................................................................................................... 80 Export the routed design ................................................................................................... 81 Fix crosstalk problems identified in crosstalk error file ................................................... 87

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MODULE 12: 12.1 12.2 12.3 12.4 MODULE 13: 13.1 13.2 13.3 MODULE 14: 14.1 14.2 14.3 MODULE 15: 15.1 15.2 15.3 MODULE 16: 16.1 16.2 16.3 16.4 MODULE 17: 17.1 17.2 17.3

PERFORMING LVS VERIFICATION .......................................................................... 91 Start DFII with the appropriate technology ...................................................................... 91 Open your schematic ........................................................................................................ 94 Import the DEF view from Silicon Ensemble ................................................................. 96 Run LVS ........................................................................................................................... 97 FIXING MINOR DRC PROBLEMS .............................................................................. 99 Perform initial DRC ......................................................................................................... 99 Clean up the layout ......................................................................................................... 100 Fix "metal maxSize is 35.0um x 35.0um" errors ............................................................ 101 ADDING A LOGO ........................................................................................................ 110 Add a logo ...................................................................................................................... 110 Remove the PR boundary ............................................................................................... 111 Ensure edits have not introduced new errors .................................................................. 112 INITIAL SUBMISSION TO CMCS DRC SERVICE .................................................. 113 Create a copy of your design with the new name ........................................................... 113 Convert your design into a GDSII (stream) format ........................................................ 114 Submit the design to CMC for DRC checking ............................................................... 115 FIXING ANTENNA RULE VIOLATIONS .................................................................. 118 Save antenna rule error messages ................................................................................... 118 Fix the nets associated with the flagged antenna rule violations .................................... 118 View the DRC results on your design ............................................................................ 119 Locate the DRC problem nets ........................................................................................ 120 PREPARING YOUR DESIGN FOR FABRICATION ................................................. 124 Add fill ............................................................................................................................ 124 Perform final LVS .......................................................................................................... 126 Perform final DRC ......................................................................................................... 127

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LIST OF FIGURES

LIST OF FIGURES
Figure 1: Figure 2: Figure 4.1: Figure 7.1: Figure 13.1: Figure 13.2: Figure 13.3: Figure 13.4: Figure 13.5: Figure 13.6: Figure 16.1: Digital IC Design Flow ....................................................................................................... 1 cmc_digflow Directory Structure ....................................................................................... 6 Schematic view of mult16chip ......................................................................................... 35 Floorplanned design ......................................................................................................... 54 Via Array Instance Before Edits (error marker not shown) ........................................... 101 Flattened Via Array (result of step 13.3.3) ..................................................................... 103 Vias Selected for Deletion (step 13.3.7) ......................................................................... 105 Vias Deleted ................................................................................................................... 106 Area Selected to be Chopped (steps 13.3.11-13.3.13) ................................................... 108 Slots After Chopping (result of step 13.3.14) ................................................................. 109 Diode Placement ............................................................................................................. 121

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INTRODUCTIONREADME.FIRST

INTRODUCTIONREADME.FIRST A TUTORIAL PURPOSE


RTL Simulation Synthesis

The purpose of this tutorial is to introduce designersprimarily graduate students and faculty at Canadian universitiesto the digital IC design flow supported by CMC, and to the syntax used by the Synopsys and Cadence tools. To help you focus on the flow and the design environment, the tutorial package includes a sample design (described in part D of this Introduction). Using this design example, the steps outlined in Modules 1 to 17 will take you through a design process, starting with a register transfer level (RTL) model of the design all the way through to physical verification including stream file creation (see Figure 1). When you have completed all the design and verification steps, you will have a stream file to describe the mask layer information for your circuit. In the last steps, you can submit this file to CMC for Design Rule Checking (DRC) and will then correct the DRC errors. This guided process will help reduce initial difficulties in learning how to use CAD tools for synthesis (Synopsys) and physical design (Cadence). However, if you are relatively new to the IC design process, please note that the tutorial assumes you have some knowledge of the concepts behind the steps. To make the best use of the tutorial, you should be supported by a supervised educational environment and in-depth study of digital design theory and practice. Although this tutorial has been written to describe the specific steps required to complete a sample design using the TSMC 0.35-micron CMOS technology (CMOSP35) available through CMC, the steps will be applicable in some cases to digital design targeting other technologies. Similarly, you can transfer the lessons you have learned working with the tutorial sample design to your own design. This tutorial will help you work with a design that is flattened and without buses so that when you do a hierarchical design with buses you can focus on problems related to those features. You should be aware that you will need to do many more iterations with your own design than in the flow you will follow in this tutorial.

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Scan Insertion

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

Figure 1: Digital IC Design Flow

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CMOSP18 Throughout the tutorial, you will find boxes like this that highlight specific changes and additional steps that are required to use the tutorial with the 0.18micron CMOS technology (CMOSP18). You must be registered with CMC and have signed a Confidential Disclosure Agreement to get access to the 0.18-micron CMOS technology, including the design kit required to complete this tutorial (the design kit includes the design example for the tutorial). You can get information and forms about registration and completing the CDA at: http://www.cmc.ca/Assistance/legal.html Completing the tutorial can take approximately three days, depending on your experience with the tools. To help you pace yourself, we have marked two types of break points:

The hourglass icon will tell you when you will have a pause of at least a couple of minutes for computing.

The coffee cup icon will tell you when you have finished a set of tasks and/or exited a tool, and can take a break if you wish.

If you need help, e-mail support@cmc.ca

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CHECKLIST

CHECKLIST
ITEM # 1 2 ACTIVITY
You should have good problem-solving skills and be willing to provide feedback to CMC You must be registered with CMC, and your university must be licensed to use the TSMC 0.35-micron CMOS (CMOSP35) or you individually must be licensed to use the TSMC 0.18-micron CMOS (CMOSP18) technology, and you must understand and accept the associated licensing stipulations. You should be familiar with: a) Unix commands. b) Synopsys synthesis tools: If you are not familiar with Synopsys, there are tutorials located in the Synopsy on-line documentation. d) Cadence tools for Verilog simulation, floorplanning, place and route, DRC, and layout editing: If necessary, please contact CMC to request information on Cadence training materials and courses. d) CMCs CMOSP35 or CMOSP18 design kit If you are not familiar with the material mentioned above, then you might have difficulty with this tutorial. Stop now, and review the relevant training materials for the software you are not familiar with. Page ii

SEE

CHECK OFF

CMC

4 5 6 7

Ensure that the cmc_digflow or cmc_digflow18 directory has been created in your account. Ensure that your account has been set up properly to run both Synopsys and Cadence. Ensure that the required software and kit versions have been installed on your system To complete the entire tutorial you will require approximately 700 MB of disk space to store your design files and approximately 512 MB of RAM; however, you only need about 150 MB of disk space for Modules 1-16 with Module 17 requiring the additional space for tasks such as metal filling. You should now be ready to proceed through the tutorial. CONVENTIONS: In this document, ASCII text is shown in Courier font and executable commands and utilities are in bold Courier font.Icons, cells, objects, menu picks etc. are shown in bold Times font. CMC provides support for this tutorial and for the Synopsys/Cadence tools. If you have difficulty with any of these, you may contact CMC Engineering Support Services, support@cmc.ca or 613-530-4666.

C1 C2 C3 C4

7 NOTE #1 NOTE #2

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SETTING UP YOUR ENVIRONMENT

Before starting the steps of this tutorial, you must ensure that both your sites configuration and your own account configuration are properly set up to use the current versions of CMC-supported tools and design kit material. Since the CMC-supported design environment is constantly changing, this printed document may already be out of date. To ensure you have the latest information on using the material in this tutorial, you should check the CMC digital flow support page at: http://www.cmc.ca/Support/cmc_digflow/ The material on the linked pages will be kept current to reflect changes in the environment, flow, common problem areas, and feedback from other users. That Web address should be your first resource to overcome any difficulties you encounter while working on this tutorial. C.1 Obtaining the tutorial In order to go through this tutorial, you will need an initial working directory, the design and test bench files, and some technology-specific set-up files. The directory structure and initial files are available in a Unix .tar file from CMCs training material Web page: http://www.cmc.ca/Training/training.html (Note: You must be registered with CMC to obtain this filesee section F.) In order to install and complete the tutorial you will require 700 megabytes of disk space. Assuming you have access to that amount of space, obtain the compressed .tar file from the Web page by following the instructions listed there. Once you have the cmc_digflow35.1.2.tar.Z file, follow the steps listed below to create a cmc_digflow directory where you will complete the tutorial steps. 1. Move the cmc_digflow35.1.2.tar.Z file into the parent directory where you would like the new cmc_digflow directory to be created. Note that expanding the .tar file will create and place files in a new directory called cmc_digflow. You should not have a directory by that name in your account before proceeding. Uncompress the file with the following Unix command: uncompress cmc_digflow35.1.2.tar.Z 3. Extract the directory structure: tar xvf cmc_digflow35.1.2.tar

2.

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4.

Remove the original.tar file (you can obtain a copy from CMC if you need this again at a later time). rm cmc_digflow35.1.2.tar

5.

To meet your licensing requirements and protect your design environment, use the following Unix command to change the file access mode on your design environment so only you have read access to the files. chmod -R go-rwx cmc_digflow

The cmc_digflow directory should now be created with the appropriate files and links required to complete the tutorial. CMOSP18 - Obtaining the directory structure that is compatible with CMOSP18 The directory structure for the CMOSP18 design example is called cmc_digflow18 (in place of cmc_digflow) and is created by obtaining cmc_digflow18.1.0.tar.Z from the Web and installing that file in your account with the following commands: uncompress cmc_digflow18.1.0.tar.Z tar xf cmc_digflow18.1.0.tar rm cmc_digflow18.1.0.tar Design Name You should use the same design name as with CMOSP35, except change the technology code from CD to CF. For example if your assigned design name was TCDICABC, you would use the name TCFICABC for the CMOSP18 design created using this tutorial. The basic directory structure used in this tutorial is shown below. Note that, in most cases, directories are tool-dependent. This same directory structure can be used for your own designs, once you are familiar with the design flow procedure. Throughout the tutorial documentation, an effort has been made to specify where particular files come from, and whether they are design-specific or general to most designs using this technology. This should help you adapt this training material for your own design.

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dfII

dp

HDLs

samples

se

Synopsys

run

tech

design

dbs

Work

Figure 2: cmc_digflow Directory Structure

The use of each directory should become more apparent through the tutorial, but a brief description of each directory and its major contents and function is provided here. dfII - Cadence Design Framework II directory. This is used for the final design verification steps, once your layout is complete. dp - Cadence Design Planner (also called Physical Design Planner or PDP). Most of the physical design (layout) is done with this tool from within its run directory. The design directory is used to store intermediate design databases, and the tech directory is a link to CMOSP35-specific technology files within the CMOSP35 design kit. Design Planner is used to floorplan your I/O and core, as well as run a constraint-driven placement engine (Q-Place) and a clock tree generation tool (CT-Gen). HDLs - This is a design-specific directory that contains the Hardware Description Language (HDL) description of your design, and of the design test bench. This is also where functional simulation of the design takes place to ensure both the original designer-created Register Transfer Level (RTL) code, and the computer-generated gate-level netlists meet your functional specifications. samples - Some files are stored here that a designer would typically create for use in the design process. These files are included as examples, and also to reduce the time required to complete the tutorial and to ensure consistent results during this training exercise. se - Silicon Ensemble directory. Silicon Ensemble is a powerful set of tools, many of which can also be called from the Design Planner tool. For the purpose of this flow, the Silicon Ensemble tool is used for constraint-based routing of your design, and for running the Pearl static timing analyzer to ensure your routed design meets your timing constraints.

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Synopsys - This directory is used for synthesis to convert your design from RTL code into gatelevel code, generate timing constraints to be met by the placement and routing tools, and to create scan-based test and test vectors. It contains a .synopsys_dc.setup file which points to technology-specific standard cell libraries (the black-box libraries) and a Work sub-directory that contains working views of your design. C.2 Ensuring your account is set up to use the environment Next you should ensure your account is set up to properly use the CMC-supported tools and flow. Since each university is different, CMC cannot document the exact steps required to set up your account. The following are some general pointers: 1. 2. You should read the LICENSE file included in this release and follow its conditions. Your account should be set up to use the CMC-supported versions of Cadence and Synopsys CAD tools. Sample C-shell script files which may be used to set up your account are listed on the CMC Support page: http://www.cmc.ca/Support If you are not sure if your account is properly set up, or if you run into problems later on, the best source of knowledge is usually another person at your university who has already completed the tutorial. Your sites Unix system administrator and lab instructors are also usually a good place to turn for help in setting up your environment. Although CMC suggests your account should be set up to configure the Cadence and Synopsys tools from your .cshrc file, some sites have configuration scripts that the user calls from a shell before running the CAD tool. These scripts can cause trouble if the tool spawns a new Unix shell itself since that new auto-generated shell has not been properly configured. Fortunately, system administrators who create the setup scripts are usually knowledgeable enough to debug other effects. 3. In addition to the variables set in the provided tool setup scripts, it is assumed that your account already sets other required variables such as a valid LD_LIBRARY_PATH variable, and that you do not get warnings or errors such as "Ridiculously long path truncated" when you source your .cshrc. It is well worth your time to debug any .cshrc file problems before attempting to complete the tutorial steps. 4. You will require approximately 700 megabytes of disk space to store your design files. However, it only requires about 150 megabytes to complete Modules 1-16. The tasks in the final Module 17 require much more disk space because they involve adding the metal fill and saving the file in GDSII format (the uncompressed version of the final GDSII (stream)

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file for example is over 100 megabytes alone). 5. You will require access to a computer with sufficient RAM, SWAP and CPU to use the tools. CMC recommends 512 Mbytes RAM, but this also depends on other loads, etc.

You may need to consult your faculty supervisor or system administrator if you do not have sufficient computing resources to complete this tutorial. C.3 Ensuring your site is properly configured In order to successfully complete the training material, you will need to ensure the CAD tools and design kits you are using are the proper versions. The current set is listed below, and an updated set of required tools and kits can be found on the Web at: http://www.cmc.ca/Support/ If you find your site is not properly configured for this tutorial, you will need help from your faculty supervisor and/or system administrator. 1. Design kit. This training material uses the TSMC 0.35-micron CMOS technology (called CMOSP35 by CMC). You should be using V4.2 or higher of that design kit. To see which version is installed at your site, in a Unix shell issue the command: more /CMC/kits/cmosp35/README The top of the file you get should list the version as being 4.2 or higher. For documentation on this design kit, check out the HTML pages included in the kit by entering the following in a Web browser: file:/CMC/kits/cmosp35/doc/cmosp35_docs.html. The page that comes up should also list the kit version as being 4.2 or higher. This page contains documentation on various aspects of the CMOSP35 design kit including data sheets on the standard cell library being used, and general instructions on using the digital design flow. CMOSP18 - Design Kit Version This training material uses the TSMC 0.18-micron CMOS technology (called CMOSP18 by CMC). You should be using V3.0 or higher of that design kit. To see which version is installed at your site, in a Unix shell issue the command: more /CMC/kits/cmosp18/README The top of the file you get should list the version as being 3.0 or higher. For documentation on this design kit, check out the HTML pages included in the kit by entering the following in a Web browser: file:/CMC/kits/cmosp18/cmosp18_docs.html.

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2.

CMCs local environment for Cadence. This environment is used to bind the CMOSP35 design kit into the Design Framework II tools from Cadence. Your site should be at V1.10 or higher. Cadence tools. This tutorial is intended for use with a patched version of what CMC calls Cadence.2000a. If your site has that tool, you should have the IC stream IC.445.000508 with QSR (Quarterly Software Roll-up) 1. Check the following path appears: /CMC/tools/cadence.2000a/IC.445.qsr1 and the DSMSE stream should have been patched with the Pearl patch (pearl04.30s080sun4v). If you enter the command pearl -version, you should get the following: Pearl 4.3-s080 Also, you should be able to start the Pearl timing analysis tool from the Unix command line with the following command: pearl -gui If that command successfully spawns a user-interface, you can exit from that interface, and it is likely that the IC stream of your Cadence environment is properly set up. If you can not run pearl -gui, you should consult with your system administrator for suggested work arounds at your site. A second test of your Cadence install is to start the DFII environment with the command: startCds -t cmosp35 This should launch the Cadence Command Interpretor Window (CIW) where you can check your current version of the Cadence icfb tools and the version of design kit being used. You can use the command icfb -W from the Unix prompt to find your sub-version, or if you expand your CIW, near the top you should be able to find a line that lists the sub-version of the tool you are using. If your Cadence install has had a QSR applied, you should have a sub-version equal to or larger than: Sub version: sub-version 4.4.5.100.28 You should also be able to find a line similar to the following in your CIW which should give you confidence that Cadence is using the proper version of the CMOSP35 design kit: This is the CMC CMOSP35 Design Kit V4.2 for Synopsys and Cadence There are two other Cadence streams (DSMSE and DSMDP) that must be compatible for this tutorial. Your system administrator is responsible for that, but you can check the most recent instructions on CMCs Web Support page. Online documentation for most Cadence tools is found by entering "openbook" from your Unix command line. In order to access all the streams of Cadence online documentation, users should review the "Cadence Online Documentation" item linked from the http://

3.

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www.cmc.ca/Support page. That page also gives some information on accessing documentation on Design Planner (another Cadence tool) from your Web browser. 4. Synopsys tools The exact version of the tool being used is less critical with Synopsys than with the other tools. To determine if Synopsys is working, and which tool you are using, at the Unix prompt issue the command: design_analyzer & A version message something like: Version 2000.05 -- Apr 10, 2000 Copyright (c) 2000 by Synopsys, Inc. ALL RIGHTS RESERVED should appear in your Unix window, and a Synopsys Design Analyzer window should appear. The Synopsys version should be 1998.02 or higher. You can exit from the Design Analyzer window by clicking on File -> Quit Online documentation for Synopsys depends on the version of Synopsys you are using. If youve used the CMC-provided setup script, documentation for version 1998.08 and newer is in PDF format, and can be started by entering "sold" (Synopsys On Line Documentation) or "synview" from the Unix command line. Versions of Synopsys prior to 1998.08 used the command "iview" from the Unix prompt. You are strongly encouraged to read as much as possible of the online documentation for the tools you are using. If you encounter problems using the tools, check the following sources of information: 1. 2. 3. 4. 5. 6. The http://www.cmc.ca/Support Web pages, including the Digital Flow page linked from there The tools on-line documentation Other users at your site Your sites system administrator Users at other sites (using the cad@cmc.ca mailing reflector) support@cmc.ca

NOTE: Users must NOT contact the CAD tool providers (Synopsys or Cadence) directly.

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THE DESIGN EXAMPLE

D.1 Understanding the design example The particular example selected for this training material is a basic 16-bit multiplier (16-bit x 16bit producing 32-bit output). BIST: In an attempt to illustrate good design technique, a Built-In Self-Test (BIST) feature is included. Although not documented in this tutorial, self-test (BIST) is a feature that allows a device to test itself for functional problems once manufactured. Self-test is growing in use as more complex designs are being created, and as block-based and system-on-chip design is becoming more common. Please note that this design includes only a basic attempt at BISTthe algorithm is flawed, and should NOT be used for your own design. There is a wide range of resource material on BIST design, including various BIST algorithms which can be used for your own designs. Scan: A second form of test included in this design example is scan-based Design For Testability (DFT). This scan-based DFT allows the chip to be easily tested after manufacture to ensure there were no manufacturing errors, or subsequent problems (bonding problems for example) with the chip. Scan-based DFT is intended to test the chip before it is placed in its final application, to ensure the part you are using is working. BIST is used once the chip is in its final application to ensure the part continues to operate as expected. Scan-based DFT is also not covered in this material, since there are books that can be found which cover the subject (the Synopsys On-line documentation also has some information on scan-based DFT). For the purpose of this design, DFT means building the design so all sequential elements (flip-flops) can be replaced with multiplexed equivalents, which are connected into a shift register. When in "scan mode" this long shift register (or scan chain) is used to pre-load and sample values of internal nodes of the circuit. When scan-based testing is not used, the multiplexed FFs are placed in non-scan mode, and the circuit operates normally. In order to use scan-based test, scan in, scan enable, scan clock, and scan out pins are required on your design. For this example, the scan clock is the same pin as the regular clock, and scan out is also used as the designs BIST out pin. Neither BIST nor scan-based DFT are designed to ensure the original design is functionally (or logically) correct. Nor do they ensure your design will meet your timing goals. To ensure your design is functionally and logically correct, you should use sound design practices while designing your chip, and make use of a complete set of test patterns to simulate your chip before synthesis and throughout the design process.

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INTRODUCTIONREADME.FIRST

This design example has five separate Verilog modules: mult16chip is the top-level module, and is also called an "I/O wrapper", since it is port-compatible with the next lower mult16bist module, but includes instantiated I/O pads. It is common practice to have the wrapper module as a separate file. This module does not affect the logical function of the design, and is the only technology-specific portion of this design. To port this same design to another technology, only the wrapper module needs to be modified (to instantiate I/O from the new technology instead of from the CMOSP35 technology libraries). mult16bist has the same port list as the top-level mult16chip, and would have been used as the top-level of this design during development stages. mult16bist just contains calls to the three sub-modules. mult16 is the simplest in terms of RTL code, and simply has the form of: product = A x B. bist contains a crude BIST algorithm which you can look into, but which should NOT be used in your own designs. glue is logic which ties the other two sub-level modules together. It is critical that you understand all of the interfacing and functional aspects of your own design. However, for this tutorial example it is not important to fully understand the logic within the design itself, if you accept that the test bench properly exercises the design example.

UP-FRONT ISSUES

A designer must undertake a lot of evaluation up-front in order to create a chip. Although much of the up-front evaluation can be ignored when doing a training exercise (since this chip is not going to be fabricated anyway), you still should be aware of the up-front issues you MUST consider before attempting to fabricate your own chip. Architecture exploration: What function is meant to be accomplished, and what is the most efficient way of completing it? This is a very complex consideration, and will include your motivation/need for creating an IC. For this design example, a 16 by 16-bit multiplier, the designer should consider using an FPGA to create the design, or using an existing microprocessor or microcontroller to accomplish the task. In industry, factors such as per-unit cost, development cost, time to market, and performance requirements will often play a part in the decision. The academic world is often driven by quite different factors.

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INTRODUCTIONREADME.FIRST

Interfaces and top-level floorplan: If you are creating a chip, to what and how will it interface? How many input/output and power pins will be required? What speed will it need to run at? Fabrication technology and cell library selection: When starting a design project, one of the factors a designer must consider is which design technologies are available, which are most appropriate, and what other issues are related to the selected technology. After studying this design example, a good case could be made to use an FPGA as the fabrication technology, rather than an ASIC (Application Specific Integrated Circuit). However, the whole purpose of this tutorial is to take the user through a Digital IC Design Flow (which is a form of an ASIC flow) and it was therefore decided to use the 0.35-micron CMOS (CMOSP35) IC fabrication technology that is available through CMC (more information on this technology is available on the Web at http://www.cmc.ca/Fabrication). Having selected a technology, the designer needs to select a standard cell library (set of basic gates such as AND, OR, INVERT, FFs, etc.). The CMOSP35 design kit provided by CMC includes two standard cell libraries. The library selected for this tutorial is from the technology foundry (TSMC or Taiwan Semiconductor Manufacturing Company) and the cells are often referred to as "Black Box", "BBox", "B-cells", or sometimes phantom cells. This is a fairly elaborate set of standard cells of professional quality, and in order to protect TSMCs intellectual property the layout information of these cells is not provided in the CMOSP35 design kit. Instead, the designer creates a design based on abstract (information reduced) views of the cells. The physical layout detail is only added to the design after it is submitted to CMC for design rule check (DRC) or fabrication services. Since this library does not have layout or extracted views, it is not possible to run "analog" simulations such as Spectre or Hspice on your design. This is not a problem in the case of this design, since it is a pure digital design, and logical Verilog simulations coupled with static timing analysis are sufficient to verify the design will work without conducting transistor level simulations of the circuit. Many aspects of the techology and standard cell selection will affect how the designer proceeds at various steps. For example, a technology with more layers of metal can usually have its standard cells compressed together more tightly. Also, the size of the standard cells will affect the spacing of rows and cells within the design, and the optimum metal routing pitch which can be used to route the design. Most of these items are not under the control of the designer since the designer is stuck with the choices made by the cell library developer, who was stuck with limits placed by the technology fabrication facility. It will take a while to learn what parameters you should or can modify as a designer, and which ones you should use as set out in this tutorial. It is hoped that completing this tutorial example will help you develop the design experience needed to make such choices. Packaging: Packaging is related to the top-level floorplan. Before you can design the chip, you need to determine what package (for example a 20-pin DIP) your chip will end up in. In order

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INTRODUCTIONREADME.FIRST

to select a package, you will need to consider what packages are available, and if your chip can be bonded to them. What pin-count do you need, what are your speed requirements, what is your die area going to be, will bonding (attaching your IC die to the package) be a problem, etc.? All designers should review the CMC Web page on packaging page: http://www.cmc.ca/Packaging/ before proceeding with their own design, and contact fab@cmc.ca if you have any questions. Design size and power: Well before you create your design, you will need to have a good idea about its final size, shape and power requirements. Experience, both your own and that of other designers, is the best aid in up-front planning of your design. The following is a list of up-front issues that were considered for this design example. You MUST consider these and more when planning your own design. 1. Will this design be I/O bound, or core bound? That is, will there be any free space within the I/O ring? Designs that are I/O bound (have free space within the core) are wasting expensive design area, and would seldom be fabricated in industry. To get an initial estimate of the size of this design example, a very short Verilog RTL file was created which only contained the 16-bit multiplier. That module was similar to the mult16 module in the present design. That one module was synthesized without constraints using Synopsys. The area, timing, and power values are used as a starting point: In this case, the total area was reported as 143,000 square microns. A target clock speed (50 MHz) was applied and the critical path and a basic power estimate were generated: 33 mW and 26 ns critical path time were reported. It is anticipated that the multiply function will account for over one-half of the core area, almost all of the timing delay, and less than one-half of the power requirement (since the glue and BIST logic will add FFs and clock gating is not being used to reduce power consumed by those components). Given these data, it is estimated that the design will have a core area of 300,000 square microns if 100% core utilization was used, i.e. if all standard cells were packed together with no space between them. Power consumption should be well under 100 mW, and the 50 MHz (20 ns period) clock may be tight, but is not totally unreasonable. 2. I/O Pins. Next the number of required I/O pins is considered. The basic design has two 16bit input vectors, a 32-bit output, an input clock, reset, scan enable, scan input, and bist mode pins, as well as a combined scan/BIST output pin. This adds up to 70 I/O pins. In

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addition VDD and VSS pins will be required to power the chip. Browsing the I/O datasheets for the TSMC library provided with the design kit shows three types of power cells are available. 1. Core power pads which provide power to the core of the chip. Core and ring power are often separate to reduce the off-chip noise associated with high-current drive from affecting the core power. (PVDD1 and PVSS1) 1. Ring power pads which are used to provide power to the other I/O cells, and drive signals off-chip. (PVDD2 and PVSS2) 3. Combination core/ring pads exist. These pads power both the ring and the core from the same pin. (PVDD3 and PVSS3) It is decided that this design will have 6 pairs of ring power pads based on a rule-of thumb of one pair for every 4-6 output pins (this is very dependent on output toggle rate! For a fabricated design, simulation and detailed calculation are strongly encouraged.) For core power, four pairs of pads will be used. This allows for distributed power connections to the core, and using the rule of thumb of 1 mA per micron of metal width and assuming 60-micron wide power connections are going to be made, this should allow for an average flow of 240 mA of current to the core, which at 3.3 Volts gives a margin of almost 8x the estimated maximum core requirement of 100 mW. If your design is power intensive, or has portions which may be, heating effects or "hot spots" might cause problems. Adding 20 power pads (6 pair for ring power, 4 pair for core) brings the design pin count up to 90. 3. Die Size. Before determining if a suitable packaging option exists, the total die size should be estimated. From viewing the layout of the I/O pads it is determined that the standard I/O size is 84 by 365 microns. The CMC Web page on fabrication issues suggests that the "easiest" bonding pitch is 150 microns. This implies that without having special bonding considerations, the I/O pads need to be spaced apart an extra 66 microns. To accomplish this, four 20-micron wide "feeder" cells are added between every I/O pad within the I/O ring. So in effect, each I/O connection takes up 84 + 80 = 164 microns of the I/O ring. In addition to this, four 365-by-365 micron corner cells need to be added. If the 90 I/O pads could be evenly spaced around the design there would be 22.5 per side (that is an impractical number, but since this is just a rough calculation, we will use it for this example). Each side would be 22.5 times 164 plus two 365 corner cell lengths, plus an extra set of 80 micron feeder cells per side (to space the corner cells out). This makes a total length of 4500 microns, or 4.5 mm. Assuming this is a square chip, the usable core area is this number minus the space taken up by the I/O ring (2 times 365) squared or 14,212,900 square microns. Or over 108 times the 100% core utilization area number!!

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It is not practical to manufacture a chip with so much wasted area. Some steps which could be done to reduce the area requirement for this I/O ring are: 1. Reduce the pin count. This can be done by multiplexing signals, or transferring data in a serial fashion, instead of parallel busses. 2. If possible, reduce the I/O pitch. In the case of this design, the designer should contact fab@cmc.ca to discuss the possibility of bonding the chip if no I/O feeder cells are used. 3. Modify the aspect ratio. Assuming the chip perimeter is fixed based on the number of required I/O and power pads, the internal area is maximized as the shape becomes square. The internal (and total) area is minimized, as the aspect ratio is increased or decreased and the chip takes the form of a long or flat rectangle. Modifying the shape in this way can cause other problems such as bonding issues, and increased trace lengths within the die. Also, the shape/size of your die should be discussed with CMC before floorplanning the I/O to ensure your die will fit on the wafer along with designs from other designers. If your chip is core bound, the area used by your core (you will not be able to realize 100% utilization) is larger than the bound area of the chip. You will likely use a square shape to maximize internal area, and will need to add feeder cells around the I/O ring to ensure all I/Os are connected by abutment. A final note on the I/O ring is that in this flow the ring is connected by abutting I/O pads, feeder cells and corner cells to form a solid I/O ring. For this reason, the designer needs to consider and place every I/O and power pad on his/her design. This should be considered up front, along with external interfacing issues, and you need to be aware that core power routing is difficult if core power is placed in the corners of the die. In the example I/O floorplan used in this tutorial, the core power pairs are intentionally placed in the centre of each side of the die. Although this design example is severely I/O bound, since it is not going to be fabricated and is only used as a training example, we will continue with these numbers. The design will be given a flat aspect ratio which reduces the core area. If you plan on fabricating your own design, you must fully resolve packaging, bonding, test fixturing, and physical test issues BEFORE creating your design. All of these issues are interrelated, and affect decisions such as the number of I/O ports you can have on your design.

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CMC has developed a digital design checklist which will help ensure the designer considers necessary aspects of the design before getting too far on in the design process. Check http://www.cmc.ca/Design_Flows/ for more details. When possible, designers should review their design plans with supervisors, or other experienced designers, to avoid potential problems later in the design/test cycle.

REGISTERING YOUR TUTORIAL DESIGN WITH CMC

Before beginning the tutorial, you should obtain a design name for use in the later steps of the tutorial. For you own designs, you typically pick a three letter code, and append it to the technology code, and your university code, as described on CMCs Web pages on Fabrication (www.cmc.ca/Fabrication). For this tutorial, CMC will assign a special "tutorial" code for use with the CMOSP35 technology. To obtain your design name, go to the Web page: http://www.cmc.ca/Training/Digital_Flow/cmc_digflow_getting_started.html

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MODULE 1: SIMULATING THE RTL CODE

MODULE 1: SIMULATING THE RTL CODE


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 1: To verify the functionality of the Register Transfer Level (RTL) code describing the design example
Background: The back-end of the DSM flow uses Verilog to transfer the design from Synopsys to Cadence, but the design itself can be in either Verilog or VHDL. Using Verilog for the RTL code offers the advantage of needing only one test bench for the entire design cycle. If you wish to write your RTL code in VHDL, you will need a VHDL test bench for initial code verification, and then an equivalent Verilog test bench for final simulations. To avoid these problems, Verilog was selected for the RTL code.

Synthesis

Scan Insertion

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

1.1

Become familiar with the mult16chip design and test bench

The design is a 16-by-16 integer multiplier with a built-in self test (BIST) feature. It is hoped that the design will operate with a 50 MHz clock, and have over 98% fault coverage using a multiplexed flip-flop scan-based test system. Power consumption should be less than 100 mW. For the final stages of this design exercise, you must have an assigned design name which you will use to submit the design example to the CMC Design Rule Check (DRC) service. In preparation for those stages, you should now register for an individual design name by going to the Web page: http://www.cmc.ca/Training/Digital_Flow/cmc_digflow_getting_started.html Updates on the digital design flow and environment can also be found at the same Web page.

Routing & Timing Verification

Physical Verification

CMOSP18 Remember the directory for your design files is: cmc_digflow18 1.1.1 To view the design files, from the Unix prompt: cd cmc_digflow/HDLs more mult16chip_rtl.v more mult16tb_rtl.v

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MODULE 1: SIMULATING THE RTL CODE

Normally the designer would be quite familiar with the code and test bench. Take a while to look through the code. Understand the mult16chip design, and the test bench. Notice that the actual a x b = prod. multiplication is only a very small portion of the RTL code. Most of the code is dedicated to the BIST. It is not important to understand the BIST itself, as this is a very poor example of a BIST algorithm. Note that a simple design style was used. The design is fully synchronous off the rising edge of one clock signal. No latches or three-state devices were used. The reset input will place the entire design in a known state. These simple points will help make the design easier to test, and to ensure the synthesized results behave as expected. When writing the RTL code it is important to not only ensure the code will function properly, but the designer should also have a fairly good idea of the resources which will be created by the code. For example, how many flip-flops would be used by this design? The test bench provides the system clock and reset signals, and also initially invokes the circuits selftest, and monitors the output. Once two complete self-test cycles are finished, the chip is placed in its functional mode, and test vectors (with input values and expected results) are fed into the circuit. In this test bench, the functional vectors were generated by the included C program. Arbitrarily 1000 random vectors were generated, with expected results. Then some of the vectors were changed to exercise specific corner conditions (anticipated trouble areas for the multiplier circuit) and finally, one of the expected results was altered so the test bench would flag an error. The erroneous expected result serves two purposes. First, it reassures the designer that the test bench is working, and can tell when an error occurs, and secondly, because the vector with the error is near the end of the 1000 test vectors, it ensures that all of the vectors are being read in by the test bench.

1.2

Simulate the RTL code with Verilog-XL

The bbox_ver.setup file used in the Verilog simulation command contains technology library information used by Synopsys. This is needed since the RTL netlist does contain some gate-level I/O instances, so it is really a technology-dependent netlist. 1.2.1 At the Unix prompt, ensure you are in the HDLs directory: cd cmc_digflow/HDLs and issue the following command: verilog -f bbox_ver.setup mult16chip_rtl.v mult16tb_rtl.v This should cause Verilog to compile and simulate the specified files. Here is a sample output for a working design:

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MODULE 1: SIMULATING THE RTL CODE

...
Compiling source file mult16chip_rtl.v Compiling source file mult16tb_rtl.v Scanning library file /CMC/hits/cmosp35/models/verilog/nwb/bcells.v Highest level modules: tb Bist_out went low at time: 0 Bist_out went high at time: 170 Bist_out went low at time: 230 Bist_out went high at time: 2450 Bist_out went low at time: 2510 Functional test error: Vector 995, Actual product was: 177356088 L68 mult16tb_rtl.v: $finish at simulation time 2600000 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.2 secs to compile + 0.0 secs to link + 0.7 secs in simulation End of VERILOG-XL 2.5.15 Oct 9, 1998 22:11:34

Note that the error at vector 995 was intentionally inserted in the mult16tb.stim file. For initial simulations, or times when the results are not as expected, the designer will likely want to view waveforms of internal signals.

1.3

View the simulator results

In the test bench file a number of signals were written to a database. These signals can now be viewed. The name of the database and the signals written to it are defined in the mult16tb_rtl.v file by the two commands: $shm_open(file_name); and $shm_probe(signals, to, be, saved); 1.3.1 To start the waveform viewer tool, enter the following at your Unix prompt: signalscan mult16tb_rtl.db Once the signalscan tool starts up, select: File -> Open Simulation File In the pop-up window, select: cmc_digflow/HDLs/mult16tb_rtl.db Click: OK 1.3.3 Click the Desbrows:1 button, then the DAI Signalscan Design Browse:1 window will pop up. In Instance in Current Context, select tb. It will display chip at once, and in Nodes/Variables in Current Context, all inputs and outputs of chip will display.

1.3.2

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MODULE 1: SIMULATING THE RTL CODE

1.3.4 1.3.5

Select all of the signals by clicking the GetAllVars button. To add or remove a signal from the selected set: To add a signal, just click the signal in the Nodes/Variables in Current Context. To remove a signal, select the signal from the selected set and click on the Delete button.

1.3.6 1.3.7

To have these selected dignals added to the display window click on the AddtoWave button. You can ascend the hierarchy instances by clicking on an instance in Instance in Current Context. For example, with this design: Click on chip then mult16bist will display. All the input and output signals of mult16bist will display under Nodes/Variables in Current Context. Once you have all the desired signals displayed in the DAI Signalscan Waveform:1 window, you can adjust the order of the signals and the way they are displayed, zoom in, zoom out, etc. If you have the display you want, it is a good practice to save the setup, so that you don't need to go through this process every time you call up the Signalscan tool.

1.4
1.4.1 1.4.2 1.4.3

Save the waveform configuration


To save the setup, click on: File -> Save do-File In the pop-up window, put in the name of save do-file, and click OK. To show this set of waveforms next time, from the main Signalscan window select: File -> Execute do-File Select the do-File name in the pop-up window and click OK.

1.4.4

Once you are happy with the simulation results, close the Signalscan tool: File -> Exit

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MODULE 2: IMPORTING THE RTL CODE INTO SYNOPSYS

MODULE 2: IMPORTING THE RTL CODE INTO SYNOPSYS


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 2: To import the design example into a Synopsys database

Synthesis

2.1
2.1.1

Start Synopsys Design Analyzer


Change into the Synopsys directory: cd ../Synopsys Ensure you have an appropriate .synopsys_dc.setup file: more .synopsys_dc.setup

Scan Insertion

Gate-Level Simulation

Floorplanning

2.1.2

Placement

The .synopsys_dc.setup file sets the environment for the Design Compiler family of Synopsys tools. This file sets the search path for all libraries which will be used, and tells Synopsys what the target technology will be. It sets some other default values (bus naming style, etc.), and in this case, includes some scripts of common functions. Note that the .synopsys_dc.setup file in this tutorial is similar to the one that is used in your sites design environment and is included in the /CMC/ kits/cmosp35/synopsys/dotfiles directory. One difference is the addition of the following line: define_design_lib work -path Work This line is needed to tell synopsys to use Work as the working directory. It is needed since a .synopsys_vss.setup file is not used (the .synopsys_vss.setup file often includes the path to a working directory). 2.1.3 Start up the Design Analyzer tool by entering at the Unix prompt: design_analyzer Design Analyzer is a graphical interface to Design Compiler. 2.1.4 Open the Command Window by selecting: Setup -> Command Window... The Command Window echoes text versions of all functions performed, and allows the designer to enter Design Compiler commands as if they were using dc_shell (the Design Compiler text-based interface).

Clock Tree Generation

Routing & Timing Verification

Physical Verification

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MODULE 2: IMPORTING THE RTL CODE INTO SYNOPSYS

A log of the Command Window is automatically created in the view_command.log file. This is useful to review previous steps/results, especially after a long compile. HDL code (Verilog or VHDL) should be read into Design Analyzer with the Analyze and Elaborate steps. This is especially important when reading a file in for the first time.

2.2
2.2.1 2.2.2

Analyze and elaborate the RTL code


In the Synopsys Design Analyzer window, select: File -> Analyze... In the Analyze File window double left-click on: ../HDLs/mult16chip_rtl.v There should be no errors with this design, but this step is usually part of the code debug cycle. Just because you can simulate your code does not mean it can be synthesized!! Now elaborate the top-level design into the default library: File -> Elaborate... In the Elaborate Design form: Left-click on DEFAULT Left-click on mult16chip(verilog) which is the top-level module of this design. Click: OK

2.2.3 2.2.4

The results of elaboration will appear in both the Elaborate window, and the Command Window. This is a good place to look for problems with your design. Designs should have no warnings or errors at the elaborate stage. Also, instantiated sequential components (e.g. FFs) should be as expected. All modules in your design should now be present in the Synopsys Design Analyzer window (bist, glue, mult16, mult16bist and mult16chip in this case). You can Cancel the Elaborate window, or leave it there. Synopsys will use that window to report results from other steps. Note that the top-level designs are shown as a gate, where the other modules are shown as text code. This is because the mult16bist and mult16chip modules contain only "gate level" Verilog, where the other modules contain "RTL" code.

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MODULE 2: IMPORTING THE RTL CODE INTO SYNOPSYS

2.3
2.3.1

Explore the Synopsys environment


Left-click on the top level of your design (mult16chip). Have Synopsys check your design for problems: Analysis -> Check Design... OK the Check Design form. This design should only have warnings about connection class differences on the I/O pads, and test_si and test_se signals not driving any nets. These are ports on the design but they have nothing connected to them. They will be used later for scan-based test.

Initially you have five boxes corresponding to the five Verilog modules in your design: mult16chip, mult16bist, bist, glue, and mult16. Each of these modules has various views in Design Analyzer. The current view is displayed on the bottom right had corner of the Design Analyzer window: Designs View. 2.3.2 If you single click on the mult16chip module, the following is displayed at the bottom of the window: Design: mult16chip (mult16chip.db) You can double-click on the mult16chip box, or click on the down-arrow on the left side of the window to descend into that design. You should now have the following displayed: Current Design: mult16chip You can change between hierarchy (button containing a block diagram), symbol (button containing a block with input and output pins), and schematic (button containing an and gate symbol) views. In schematic view you can see all of the I/O pad symbols, the mult16bist block, and how they are interconnected. If you click on an object or net, the window displays what you have selected. For example a blue box in the centre (you may need to zoom-in) of your design should be Instance: mult16bist (mult16bist). 2.3.3 If you double-click on that instance, Current Instance: mult16bist (mult16bist) should be displayed on your screen. You can explore the different views of the various modules. Note that all components displayed except the I/O pads are generic at this point. The mult16bist module shows the connection to the other three modules. Return to the top level of the design by clicking on the up-arrow a few times. 2.3.4 The design is currently in a Synopsys database. Save the design in this form as follows: Select the top-level module (mult16chip) and then: File -> Save As... OK the Save File form to save the design under the default name mult16chip.db The .db file is a Synopsys proprietary format which has the advantages of being quickly read/written by the tool, and it stores constraints placed on the design as well as the design information itself. This is not related to the .db directory created by Verilog in Module 1.

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MODULE 2: IMPORTING THE RTL CODE INTO SYNOPSYS

You can now proceed directly to Module 3, or exit from Synopsys: File -> Quit

THIS IS A NATURAL BREAK POINT

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MODULE 3: CONSTRAINING THE DESIGN

MODULE 3: CONSTRAINING THE DESIGN


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 3: To specify constraints on the design which are a way of ensuring the design meets the designers performance objectives

Synthesis

Scan Insertion

3.1
3.1.1

Specify the I/O pads


Gate-Level Simulation

For Module 3 you will need to start Design Analyzer from the Synopsys directory. cd Synopsys design_analyzer

Floorplanning

Placement

Clock Tree Generation

3.1.2 3.1.3

Bring up the Command Window: Setup -> Command Window... Read in the previously created design database: File -> Read... Double-click on mult16chip.db (or single-click on it, then click on OK). Note that Read is used to import .db files. The .db files preserve Synopsys environment settings as well as circuit structure.
Routing & Timing Verification

Physical Verification

I/O pads can be specified for your design in a number of places. Some of the common ways of adding I/O along with pro's and con's are discussed: They can be instantiated in the RTL code. This provides the advantage of being able to add all I/O pads (including for the scan circuitry which does not yet exist) up front. It also allows the instance names to be specified by the user so that top-level nets, including the clock and reset nets, can be easily identified later on. Also, adding the I/O up front allows Synopsys to synthesize the design knowing what drive/load is being applied to all the I/O nets. Finally, it allows the designer to specify which I/O is intended for use with this design, since this is a decision which should have been made up-front at the same time as the top-level pin-out. One disadvantage is that I/O pads are technology-specific, so including these in your RTL code makes it less generic. Adding I/O within Synopsys: The I/O pads can be added within Synopsys, but pads can only be added for existing nets, so scan chain-related pads need to be added after the scan chain has been inserted. Adding I/O after synthesis: I/O can be added to the gate-level Verilog netlist after Synthesis, either by a script or by manual editing. Or the I/O pads can be added in Design Planner or in Silicon Ensemble as an Engineering Change
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MODULE 3: CONSTRAINING THE DESIGN

Order (ECO), the same time power pads or corner cells are added. One main disadvantage to this method is that the design has not been synthesized with those pads in place, so pad constraints may not be taken into account. In this flow, I/O pads have been added to the RTL code. Since the desired pads were added, a dont_touch flag should now be set on all I/O pads to prevent Synopsys from modifying those pads. One way to set dont_touch on the I/O cells is to select each I/O pad in the Design Analyzer window, and set the attribute. Since this design has been created with all I/O pads, and NO OTHER modules starting with the letter "p", the attribute can also easily be set from the design_analyzer command line. 3.1.4 In the Command Window: design_analyzer> set_dont_touch find(cell "p*") Check the log and ensure all (and only) I/O pads have dont_touch set. If this is your own design you may need to use. remove_attribute find (cell "name") dont_touch and set_dont_touch find (cell "name") to ensure the desired effect is achieved.

3.2

Define the scan style

NOTE: Since the top-level module of this design (mult16chip) is only an I/O wrapper module, and it contains no other logic, the DFT methodology and synthesis of this design is focused on the mult16bist module. One reason for this is to overcome an observed problem with Synopsys that adding a scan chain from the top-level of the design modifies the wrapper, and adds un-needed logic and pins to the mult16bist module. 3.2.1 3.2.2 3.2.3 Select the module (mult16bist) Select: Attributes -> Optimization Directives -> Design... In the Design Attributes form, change Test Scan Style to Multiplexed Flip Flop Click Apply then Cancel In the main window: Click the down arrow to descend into mult16bist Select the Symbol View if not already displayed.

3.2.4

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MODULE 3: CONSTRAINING THE DESIGN

3.2.5

The bist_out pin will also function as the scan chain output pin. Select the bist_out port and then: Attributes -> Optimization Directives -> Output Port... In the Output Port Attributes form change Signal Type to Scan Out Click Apply and Cancel

3.2.6

In the main window, if you double-click on the test_se port the Input Port Attributes form should come up. Select: Signal Type: Test -> Scan Enable Click Apply

3.2.7

Repeat for the test_si pin, changing its Signal Type to Test -> Scan In Always click Apply after changing a form. Design Compiler now knows which pins to use for scan-based test.

3.2.8

You can Cancel the open forms.

3.3
3.3.1

Define the output load


Return to the top-level module of this design for the remainder of the constraints. To do this, click the Up-Arrow, and then double click on mult16chip. Click on the Symbol view button (from the left-side of the Synopsys Design Analyzer window) if you are not already viewing the symbol view of mult16chip.

3.3.2

To set the expected output load, select the bist_out and prod_out output ports (draw a box around them, or click on one, then hold shift while you click on the other) and select: Attributes -> Operating Environment -> Load... Enter a Capacitive load: of 20 The units for capacitance in this library are picofarads.

3.3.3

Click Apply then Cancel

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MODULE 3: CONSTRAINING THE DESIGN

3.4

Set maximum net transition (net slew)

CMOSP18 3.4 In the CMOSP18 design kit, maximum net transition is defined in the library, so it does not need to be defined here. Omit all of step 3.4. Synopsys calls net slew "transition time". The TLF file for the CMOSP35 black-box libraries have a maximum slew rate of 2.0 ns, although the cells have been characterized with slew rates up to 3.0 ns. In order to try and meet the TLF file's limit of 2.0, a maximum transition time is set within Synopsys. 3.4.1 To set this design constraint select: Attributes -> Optimization Constraints -> Design Constraints In the Design Constraints form select: Design Rules: Max Transition: 2.0 Test Constraints: Min Fault Coverage: 98% Click Apply

3.4.2

3.5
3.5.1 3.5.2 3.5.3

Define the clock


In the main window, click on the clk pin. Select: Attributes -> Clocks -> Specify... In the Specify Clock form change Period to 20 in nanoseconds Select Dont Touch Network Click Apply Click on Skew ...

3.5.4 3.5.5

In the Skew form, select Propagated Enter under Uncertainty: Min: 0.5 (note Max: is set the same) Click Apply Cancel any open forms. Note that the clk pin now has a red square wave shown on the symbol. This indicates it is a defined clock. Weve told Synopsys that there is an uncertainty of 0.5 ns on the clock signals, and not to touch the clock tree. The clock tree will be created later using CT-Gen.

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MODULE 3: CONSTRAINING THE DESIGN

3.6
3.6.1 3.6.2

Set general compile directives


Click on mult16chip Enter the following in the Command Window: design_analyzer> set_fix_multiple_port_nets -all This will prevent a number of port/net related problems during synthesis. All of the other default constraints should be adequate, and this design should be ready for synthesis.

3.7

Propagate top-level constraints down to mult16bist module for synthesis

Since the mult16bist module will synthesized later when the scan chain is added to the design, constraints and the clock definition which were added to the top-level of this design should now be propagated to the mult16bist level as well. 3.7.1 3.7.2 Select the mult16chip symbol In the Command Window enter: design_analyzer> characterize mult16bist If you view the symbol view of mult16bist you should now see that its clk pin also has the red square wave displayed, indicating that this pin has been defined as the clock pin for the module.

3.8
3.8.1 3.8.2 3.8.3

Save the constrained design


Ensure the top-level mult16chip module is selected, then: Select: File -> Save As... In the Save File form, change File Name to mult16chip_constrained.db Click OK You may now exit Synopsys Design Analyzer by selecting: File -> Quit

3.8.4

You have now completed Module 3. Module 4 includes compute-intensive steps which take your constrained design to a compiled design which meets all of the applied design constraints.

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MODULE 3: CONSTRAINING THE DESIGN

THIS IS A NATURAL BREAK POINT

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MODULE 4: COMPILING THE DESIGN

MODULE 4: COMPILING THE DESIGN


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 4: To synthesize the design into gates, meeting all pre-set constraints If you are not still in Design Analyzer, or have modified your design since Module 3, re-start Design Analyzer and Read mult16bist_constrained.db. Start up the Design Analyzer tool by entering at the Unix prompt:

Synthesis

Scan Insertion

Gate-Level Simulation

Floorplanning

design_analyzer Open the Command Window: Setup -> Command Window... Read in mult16bist_constrained.db: File -> Read...
Placement

Clock Tree Generation

4.1

Perform the initial compile

Routing & Timing Verification

CMOSP18 4.1 In this and subsequent compiles, you may get a message of the form: Error: Could not find user specified selection group:WireAreaCon. (WL-40) This is not a critical problem and these messages can be ignored. Since the top-level wrapper (mult16chip) already only contains I/O cells and the sub-module mult16bist, it does not need to be synthesized. As a way of maintaining two levels of hierarchy (one containing the I/O cells, and the other containing only standard cells), the design will be synthesized with the ungroup_all flag from the mult16bist level. 4.1.1 4.1.2 In the Synopsys Design Analyzer window select mult16bist To compile your design enter the following in the Command Window: design_analyzer> compile -scan -ungroup_all

Physical Verification

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MODULE 4: COMPILING THE DESIGN

This first compile takes approximately 10 minutes on an UltraSparc 10.

The command needs to be entered in the Command Window, instead of using the steps Tools -> Design Optimization... so that the -scan option can be specified which tells Design Compiler to use timing values from the scan-equivalent cells. This should eliminate problems being caused by the insertion of the scan chain after the design has been optimized. It is normal for the compile to generate a number of warnings, but no errors should exist. During code development stages the design was not ungrouped during compile, i.e. some hierarchy was maintained. For the place and route steps, hierarchy within the design core is not desired. Save the results of the first compile from the main window: Select the top-level box (mult16chip): File -> Save As... 4.1.3 In the Save File form, change File Name to mult16chip_compile1.db Click OK Generate a report using the following from the main window: Analysis -> Report... In the Report form select: Area, Constraints and Timing Click Apply Check the design: Analysis -> Check design Click OK the Check design form. No new warnings/errors should be present. You can ignore warning messages related to "Connection class violations".

4.1.4

4.1.5

You can experiment by generating different reports. You will notice that some reports (such as power) take much longer to generate than others. Your design may or may not have violations (such as a minor timing problem) resulting from the first compile step.

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MODULE 4: COMPILING THE DESIGN

4.2

Perform an incremental compile

CMOSP18 4.2 Since the constraints used for CMOSP18 are the same as were used for CMOSP35, it is very easy for Synopsys to meet the constraints on the first compile, and this second compile is not necessary. Even though it is not needed, users are encouraged to complete the incremental compile so design names will be consistent with the remainder of the tutorial. Since the design has no violations at this point the second compile is very quick. The mult16bist module now has been synthesized into CMOSP35-specific gates. Although the mult16, glue and bist modules still show up in the Designs View window, they are no longer bound to this design as they have been flattened into the mult16bist module. The mult16chip module should not have been changed by the compile. Figure 4.1 shows the schematic view of mult16chip. None of the synthesis steps in the design flow should modify this mult16chip module. As a designer you should have a much better idea now about your final design size, and if you will be able to meet your timing goal or not. Keep in mind that the timing values used are based on wireload files and may still be quite different from post-layout values. An incremental compile will be performed on this design. Now that the mult16bist module is flat, the incremental compile can be done from the top level.

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MODULE 4: COMPILING THE DESIGN

Figure 4.1: Schematic view of mult16chip

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MODULE 4: COMPILING THE DESIGN

4.2.1 4.2.2

Remove all designs: Setup -> Scripts -> Remove All Designs Re-load mult16chip_compile1.db Note that only two blocks (mult16bist and mult16chip) should be present, but both of the blocks contain logic. Click on the mult16chip Module Attempt an incremental compile with high effort as follows:
design_analyzer> compile -scan -map_effort high -incremental_map

4.2.3

4.2.4 4.2.5

Save the design as: mult16chip_compile2.db. Repeat the Check Design and Report steps.

For the purpose of this tutorial, you can continue if you have no violations, or if your timing violation is less than 2 ns. For your own designs, experience will tell you how much of a violation can be overcome by the placement and routing tools. If timing is not close, the design structure or performance goals may need to be rethought. It is good practice to visually inspect the mult16 chip I/O wrapper module to ensure it still contains all the I/O pads and no other logic cells.

THIS IS A NATURAL BREAK POINT

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MODULE 5: INSERTING SCAN

MODULE 5: INSERTING SCAN


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 5: To make the design testable via standard scan-based Design For Testability (DFT) techniques

Synthesis

Scan Insertion

The Synopsys tool Test Compiler is part of the Design Analyzer tool. Test Compiler will substitute all sequential devices (FFs) with scan equivalents, and then connect them together to form a scan chain. Test Compiler will then be used to create a set of test vectors which can detect stuck at 1 and stuck at 0 faults in the chip. Other features such as vector compaction, and fault coverage estimation will also be performed. 1. If you previously exited from Synopsys Design Analyzer, you will need to re-start the tool: cd cmc_digflow/Synopsys design_analyzer In the main window select: Setup -> Command Window... OR 1. If you have not exited from Design Analyzer, you should clear any current designs from the tool as follows: Setup -> Scripts -> Remove All Designs 2. From within the Synopsys Design Analyzer window, select: File -> Read... 3. Double-click on mult16chip_compile2.db (the compiled result from your previous step).

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

Your mult16chip module should still be an I/O wrapper. All standard cells should be in the mult16bist module. For this reason, and to avoid some scan chain insertion problems, the scan chain will be inserted directly into the mult16bist module.

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MODULE 5: INSERTING SCAN

5.1
5.1.1 5.1.2 5.1.3

Perform pre-insertion checks and check testability design rules


Select mult16bist Click: Tools -> Test Synthesis... In the Test Synthesis form click on: Check Design Rules All cells should be valid scan cells, and no violations should be reported.

5.2
5.2.1

Estimate fault coverage


To estimate the fault coverage, from within the Test Synthesis form, select: Test Manager... In the Test Manager form click on: Create Test Patterns... OK the Create Patterns form.

5.2.2

The purpose of the last two steps is to get an idea of how successful scan-based test will be with this specific design. If the fault coverage is lower than required/expected, you may need to re-think the RTL code or you may have a coding error in your design. If basic design methods are followed, fault coverage well above 90% should be obtained. When creating test patterns, you should get a warning about not having a scan path (that will be inserted in the next step). Test vectors are being generated on the assumption that all valid scan FFs will be included in the scan path. First random scan vectors are generated, and the faultcoverage provided by those vectors is determined. Next, specific vectors are generated in an attempt to isolate faults which were not detected by random patterns. Finally, all the vectors are "collapsed" to produce the minimum set of vectors required to test the maximum number of faults. In this design example over 99% fault coverage was achieved. In industry, the higher your fault coverage, the fewer defective chips will be packaged and placed in product. Reducing the number of defective chips used at the time of initial testing (with the scan-based test) reduces the time and money spent on defective product. The purpose of scan-based test is to detect problems created at the time of manufacture and packaging. It is not intended to find design faults. For more information on scan-based DFT, check the online documentation, or books on the subject. If everything is in order, the scan circuitry can be inserted.

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MODULE 5: INSERTING SCAN

5.3
5.3.1 5.3.2

Insert scan circuitry


Click on mult16bist In the Test Synthesis form click on: Insert Internal Scan Circuitry... OK the Insert Internal Scan Circuitry form. Test compiler will run the optimization engine to fix any constraints that were violated as a result of inserting the scan equivalent gates. There should be very few problems since the compile -scan option was used on the original compiles. If your design does not yet meet your timing goal, Design Compiler will try and optimize timing again at this point. On your own designs, as a result of the previous step, new _test versions of the sub-modules may be generated. The original groups as well as the new _test groups would now be displayed in the Design Analyzer window. Only the _test groups are associated with the top-level of the design at this time. When you tell Synopsys to save all levels of the design, the non _test groups will not be saved. In our case, all added scan circuitry has been added within mult16bist, so new modules should not have been created.

5.3.3

From the Test Synthesis form click on Check Design Rules There should still be no violations, and all sequential cells should be valid scan cells. If I/O were being added within Synopsys, instead of having been included in the RTL code, I/O pads would be added to the test_se and test_si signals at this time. Since all I/O pads are already contained in this design, no further modifications are required.

5.3.4

Cancel the Test Synthesis form.

5.4
5.4.1

Perform final check and save the design as a gate-level Verilog netlist
In the main window, select: mult16chip For a script that modifies the names used within the design to make them compatible with Cadence tools, select: Setup -> Scripts -> Change Names for Preview Select: File -> Save As... Change the File Name to mult16chip_scan.db Click OK

5.4.2

5.4.3

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MODULE 5: INSERTING SCAN

5.4.4

Select: File -> Save As... Change File Name to mult16chip_scan.v Change File Format to Verilog Click OK

5.4.5

Check the design Select: Analysis -> Check Design... Click OK Inserting the scan chain should have eliminated the unconnected inputs warnings. The only warnings left should be related to the clock net or connection class warnings. These are not a problem since CT-Gen will create a clock tree later.

5.4.6

Select: Analysis -> Report... In the Report form, select Area, Constraints and Timing. Click Apply It is a good idea to re-check the top-level of the design (mult16chip) to ensure this is still only a wrapper layer containing no added logic other than I/O cells. If this wrapper has been modified, the test vectors generated using mult16bist in the next section will not work with your final chip, and it will be very difficult to check for manufacturing faults. The design should still meet timing and all other constraints. If not, an incremental compile is required. Although minor modifications may be needed, this should now be a routable gate-level design.

5.5

Write timing constraints

The constraint files written by the following step contain estimated load and/or timing constraints. These values are used by the back-end tools to priorize net routing, and determine if the design meets timing goals. 5.5.1 From the Command Window, write out timing information for use by the Cadence tools.
design_analyzer> write_constraints -cover_design -format sdf-v2.1 -output mult16chip.sdf

If your design does not meet timing in Synopsys, warnings will be generated for every violation. The assumption is that these timing violations can be fixed during place and route. You can view the Standard Delay Format (sdf) file to see the actual constraints applied to your design. Both the placement and the routing tools will use these constraints to try and ensure your design meets timing.

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MODULE 5: INSERTING SCAN

You should ensure that one of the lines near the top of the file contains your proper design name: (DESIGN "mult16chip")

5.6

Create the physical test vectors

Generate the test vectors Now that the scan chain has been inserted in the design, the functional test vectors are generated. This is similar to the step used earlier to predict fault coverage, except this time the vectors are formatted and saved. 5.6.1 5.6.2 From the main window click on the mult16bist module, and select: Tools -> Test Synthesis... In the Test Synthesis form select: Test Manager... In the Test Manager form select: Create Test Patterns... In the Create Patterns form click OK The fault coverage should be very close to the value predicted earlier. Format the test vectors 5.6.4 In the Test Synthesis form select: Format Vectors... In the Format Vectors form change Format: to verilog Click OK This will generate two Verilog test benches: mult16bist_schk.v and mult16bist_0.v The first test bench exercises the scan chain to ensure values can be shifted in and out of the design as expected. The second file contains the actual test vectors. It is this file which should detect the majority of faults within your circuit. 5.6.5 You can now exit from Synopsys Design Analyzer: File -> Quit

5.6.3

You should now be ready for a gate-level simulation, and then to import the design into Cadence.

THIS IS A NATURAL BREAK POINT

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MODULE 6: GATE-LEVEL SIMULATION

MODULE 6: GATE-LEVEL SIMULATION


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 6: To verify the functionality of the gate-level netlist In Module 1 the RTL code was simulated to ensure it was functionally correct. Within Synopsys static timing analysis (report timing) was performed to ensure timing goals were met. Now in Module 6 simulations will verify the functionality of the gate-level netlist.

Synthesis

Scan Insertion

Gate-Level Simulation

Floorplanning

6.1

Modify or get your gate-level testbench

Placement

Some changes will be required to the test bench in order to simulate the new Verilog file. The file samples/mult16tb_gates.v has the required modifications already made. Either modify mult16tb_rtl.v (as discussed below) to be compatible with the gate-level netlist mult16chip_scan.v or use the already edited file samples/mult16tb_gates.v This section assumes you will use the provided sample file, but some discussion is provided on what edits have already been made to create that gate-compatible test bench. Copy the sample test bench cd cmc_digflow/HDLs cp ../samples/mult16tb_gates.v . If you compare the mult16tb_gates.v file with mult16tb_rtl.v (which was used in Module 1) you will see that the only changes to the test benches involve signalnaming conventions. In the RTL netlist, busses are written in the form A[15:0], but in the gate-level netlist, busses are expanded into all of their individual bits. Since the busses are expanded in the netlist generated by Synopsys, you need to use a similar style in your test bench. Also, since busses/signals have changed names, the $shm_probe statement used for probing RTL signals is no longer valid. You can modify the probe statement based on the new signal names, or (as in the samples/mult16tb_gates.v file) you can remove signal probing at this time, and just rely on the simulation output to verify proper simulation. 6.1.1

Clock Tree Generation

Routing & Timing Verification

Physical Verification

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MODULE 6: GATE-LEVEL SIMULATION

Modify the DFT test benches During the Format Vectors section of module 5, Synopsys generated two test benches for you. mult16bist_schk.v which verifies the integrity of your scan chain, and mult16bist_0.v which performs the actual scan-based simulation to determine if you have any faults in your design. Although these two files were generated for the mult16bist module, that module is pin-compatible with the mult16chip (top-level) module. So in order to have the scan checks call the top-level of your design, those two files need to be modified slightly. 6.1.2 From within the HDLs directory issue the following commands: cp ../Synopsys/mult16bist_schk.v mult16chip_schk.v cp ../Synopsys/mult16bist_0.v mult16chip_0.v Now using a text editor you are comfortable with, edit each of mult16chip_schk.v and mult16chip_0.v and search for the string "mult16bist"that string should appear three times in the file, twice in comment lines, and once as a module call (calling mult16bist). Change the module call to call mult16chip with all other parameters the same. In each case you will change a line which originally looks something like: mult16bist TOP_inst (.\prod_out_31_ (pin_1_), ... to mult16chip TOP_inst (.\prod_out_31_ (pin_1_), ... That is the only change required in each of the two files.

6.2

Prepare the Verilog files

Add a timescale to the Verilog netlist and prepare the gate-level netlist for simulation 6.2.1 Make a copy of the gate-level netlist in the HDLs directory cp ../Synopsys/mult16chip_scan.v mult16chip_gates.v 6.2.2 Edit the file mult16chip_gates.v, adding the following to the top of the file: `timescale 1ns/10ps (Note: the quote mark is a single backwards quote.) This time scale tells the Verilog simulator that time units are in nano seconds and the finest required simulation resolution is 10 ps. While looking at mult16chip_gates.v you can notice the structure of your design. By default Synopsys writes the top-level module (mult16chip in this case) last in the Verilog file.

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MODULE 6: GATE-LEVEL SIMULATION

6.3
6.3.1

Run the simulations


To simulate the new netlist using the bbox_ver.setup file, from the HDLs directory enter the following command:
verilog -f bbox_ver.setup mult16chip_gates.v mult16tb_gates.v

CMOSP18 6.3.1 Change:


verilog -f bbox_ver.setup mult16chip_gates.v mult16tb_gates.v

to
verilog -f cmosp18_ver.setup mult16chip_gates.v mult16tb_gates.v

You will get a number of warnings of the form: Warning! Too few module port connections [Verilog-TFNPC] "mult16chip_gates.v", 4058: U995(.I(mul_351_n479), .ZN(net8240)) These are a result of Synopsys not making connections to all of the pins on the device (Synopsys does not include vdd and vss ports in its Verilog models and does not always use both the q, and qb outputs from sequential devices). Here is the end-portion of a successful simulation output: Highest level modules: tb Bist_out went low at time: 0 Bist_out went high at time: 170 Bist_out went low at time: 230 Bist_out went high at time: 2450 Bist_out went low at time: 2510 Functional test error: Vector 995, Actual product was: 177356088 L67 mult16tb_gates.v: $finish at simulation time 2600000 1656 warnings Recall that the error in vector 995 was manually inserted. Also you should verify that all of the warnings are non-fatal.

6.3.2

Now the Synopsys-generated scan chain and vectors can be tested. It is assumed you are still in the HDLs directory. Enter at the Unix prompt:
verilog -f verilog -f bbox_ver.setup mult16chip_gates.v bbox_ver.setup mult16chip_gates.v mult16chip_schk.v mult16chip_0.v

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MODULE 6: GATE-LEVEL SIMULATION

CMOSP18 6.3.2 As in 6.3.1, in the verilog -f commands: Change bbox_ver.setup to cmosp18_ver.setup

The second simulation will take a few minutes to run.

6.3.3

The test vector simulations should both report: TEST COMPLETED WITH NO ERRORS.

6.4

Insert and detect a fault

OPTIONAL: To see the effect of a fault in your gate-level netlist, you can copy the design file to a new name, edit the gate-level code and insert a fault. Then re-run the Verilog simulations to see if the testing detects the intentional fault. 6.4.1 6.4.2 cp mult16chip_gates.v mult16chip_broke.v Edit the mult16bit_broke.v file, and randomly change one of the nets to 1b0 (a stuck-at-0 fault) or 1b1 (stuck-at-1), or possibly change a gate for another gate with the same pin-out, e.g., change ND2D2 to NR2D2 Re-run the simulations by entering at the Unix prompt: verilog -f bbox_ver.setup mult16chip_broke.v mult16tb_gates.v verilog -f bbox_ver.setup mult16chip_broke.v mult16chip_schk.v verilog -f bbox_ver.setup mult16chip_broke.v mult16chip_0.v

6.4.3

CMOSP18 6.4.3 As in 6.3.1, in the verilog -f commands: Change bbox_ver.setup to cmosp18_ver.setup Note that unless you modified part of the scan chain itself, the mult16bist_schk.v simulation should still work fine (as it just tests the scan chain).

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MODULE 6: GATE-LEVEL SIMULATION

The final simulation should detect over 99% of stuck-at type faults that you insert. In one test, a line half-way through the file was altered to include a stuck-at-0 fault. The random patterns in mult16tb.stim detected the fault, as did the mult16chip_0.v vectors, but the Built-In Self-Test (BIST) circuit did not trigger. It is obvious that the BIST algorithm used in this chip is very poor, and the algorithm should be rethought before being used in a design which is to be fabricated. You have now finished the front-end portion of designing your chip. This is a logical point to take a break, after which we recommend you proceed to Module 7 to floorplan your design within Physical Design Planner (DP).

THIS IS A NATURAL BREAK POINT

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MODULE 7: FLOORPLANNNING

MODULE 7: FLOORPLANNNING
RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 7: To create a floorplan for the design including a default group of cells, I/O ring connected by abutment, and defined placement sites for all cells You are now starting the physical portion of IC design. For the later modules you will require an individual design name for use with CMCs automated DRC service. If you have not yet obtained a user-specific design name, you should get one following the instructions at http://www.cmc.ca/Support/cmc_digflow.html

Synthesis

Scan Insertion

Gate-Level Simulation

Floorplanning

Placement

This section uses the Cadence tool Physical Design Planner (PDP or DP) for physical placement of a design. Before attempting this section for your own design you will require a detailed I/O ring floorplan which allows all of the I/O cells to be connected by abutment. The creation and placement of groups is not fully explored in this design example since it does not contain any macro-cells such as RAM or hard-cores.

Clock Tree Generation

Routing & Timing Verification

Physical Verification

7.1
7.1.1

Import the gate-level list


From the Unix command line, type: cd dp/run To start Design Planner you should be in the run/ directory and should type the following command at the Unix prompt: areaPdp & This will start areaPdp, the timing-driven floorplanning tool. After the tool starts (this may take a minute or two) the Pillar Command window and the log window should both appear. One user has noted that starting the areaPdp tool as listed in this step causes problems. The solution was to start the tool with the command: areaPdp -tech ../tech However, these problems may be related to other set-up issues. Please send a note to support@cmc.ca if you have problems using this step.

7.1.2

7.1.3

To import your design from a Verilog netlist into a Design Planner library, from the Pillar window, select the following menu pick: File->Import->Verilog... This brings up the ver2hld and View File windows.
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7.1.4

Select or enter the following values in the ver2hld form: Click on Run translation Input Verilog file names: ../../HDLs/mult16chip_gates.v Name of top cell: mult16chip Name of the global nets Power: VDD Ground: VSS Tie nets (up down): VDD VSS Output library name: design Create primitives with view name: abstract Create blocks with view name: autolayout Print informational messages OK the ver2hld form

7.1.5

In the Pillar window select: File -> Open... In the Open File window select: Libraries -> design Select mult16chip, and click OK Select autoLayout and click OK This should launch the areaPdp--Editing window.

7.1.6

7.2

Add power pads to the design

In the editing window you should see your I/O pads and standard cells. The first step is to add power cells to your design. This is done as an ECO (engineering change order) since the cells do not exist in your current netlist (adding these cells will modify the netlist). CMOSP18 7.2 The pad library used with the CMOSP18 technology is named tpz973g. In this library, core power pads are named PVDD1DGZ and PVSS1DGZ, while I/O (or ring) power pads are called PVDD2DGZ and PVSS2DGZ. Note there is no PVDD3DGZ since the I/O and core must operate at different voltages. (I/O's are characterized for 3.3V, but can tolerate 5V. The core cells are rated for 1.8V only.) There is a PVSS3DGZ cell which can be used if a common I/O and core ground is to be used.

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7.2.1

Select ECO -> Cells -> Add with Connectivity... Note that we are adding four core pairs, and six ring pairs. From the HTML datasheets for the CMOSP35 tpd773pn library, you can tell that PVDD1 has a core power connection, PVDD2 has I/O (or ring) power connections, and PVDD3 has both core and ring connections. In the Design Planner Glue Cell Addition form enter/modify: Library Name: tpd773pn Cell Name: PVDD1 View Name: abstract Prefix Name: vdd_core Number to Add: 4 Click Apply You should see four new I/O cells added to your workspace.

7.2.2

CMOSP18 7.2.2 Change tpd773pn to tpz973g Change PVDD1 to PVDD1DGZ 7.2.3 The PVSS1 cells follow the same convention. Change: Cell Name: PVSS1 Prefix Name: vss_core Click Apply CMOSP18 7.2.3 Change PVSS1 to PVSS1DGZ 7.2.4 Repeat again for six pairs of ring (I/O) cells using the following form for VDD: Cell Name: PVDD2 Prefix Name: vdd_ring Number to Add: 6 Click Apply CMOSP18 7.2.4 Change PVDD2 to PVDD2DGZ

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7.2.5

The PVSS2 cells follow the same convention. Change: Cell Name: PVSS2 Prefix Name: vss_ring Click Apply

CMOSP18 7.2.5 Change PVSS2 to PVSS2DGZ 7.2.6 Once all power pads have been added, Close the Design Planner Glue Cell Addition window.

7.3
7.3.1

Initialize the floorplan


The design floorplan is ready to be initialized. In the areaPdp--Editing window select: Floorplan -> Initialize... In the Design Estimation Parameters form, change: Estimate Aspect Ratio [X/Y]: 1.5 Standard Cell Routing Ratio: 0 Select Area? Click Apply & Close the form You should now see a die area with the specified aspect ratio, and your core and I/O cells spread out.

7.3.2

7.3.3

Corner cells are needed to connect the I/O rings. They are added next. In the areaPdp--Editing window, select: Place -> I/O -> Corner Cells -> Add... Fill out the Design Planner Add I/O Corners form by selecting: I/O Corner[BL] and add the following information: Library Name: tpd773pn Cell Name: PCORNER View Name: abstract

7.3.4

CMOSP18 7.3.4 Change tpd773pn to tpz973g Change PCORNER to PCORNERDG

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7.3.5 7.3.6 7.3.7

Now select the remaining I/O Corner[BR], I/O Corner[TR] and I/O Corner[TL] and copy and paste the entries across to the other boxes so all four corners are filled out the same. Apply & Close the Design Planner Add I/O Corners form. Placing the I/O tends to be problematic, so this is a good place to save an intermediate version of your design. From the AreaPdp--Editing window select: File -> Save As... In the Save File As form enter: Save as: initialized Click OK If something goes wrong with I/O placement, you can load this intermediate version and try again.

7.3.8

7.4
7.4.1

Create the ring of I/O cells


Your floorplan should now have placed corners. To place the remainder of your I/O cells requires an I/O placement file. In the areaPdp--Editing window select: Place -> I/O -> Pads/Pins... A placed file for this design is provided in the samples directory, but the steps to create it are listed here. If you have your own placement file, or wish to use the provided file proceed to step 7.4.3Add I/O Feeder Cells. The user is encouraged to use the provided file for this example.

Generate an initial I/O placement file for your design 7.4.2 Modify the Design Planner Place I/O Initialize form as listed: I/O Init Mode: print random io file I/O Init File Name: random.ioc I/O Init I/O boundry Mode: generate new I/O Init I/O to I/O Min Distance: 0.0 Click Apply A random.ioc file should be created. On your own design you should manually edit the I/O floorplan based on the bonding requirements for your chip. Creating a proper I/O floorplan is one of the most critical steps in the digital design process. The user must ensure opposite sides of the die are the exact same size. Other areas of concern to the

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user are: Is the I/O pad to I/O pad pitch compatible with the selected bonding process? Will the die fit within a selected package? Have an adequate number of core and ring power pairs been added to the design? New users are encouraged to consult experienced designers when deciding on an I/O floorplan.

Add I/O feeder cells 7.4.3 At the time of writing, there is a bonding pitch restriction on ICs fabricated through CMC, so the I/O pads must be spaced out. To accomplish this, a Unix Perl script has been written to add PFEED20 (20 micron wide feeder cells) to the I/O ring. You can run this script to modify the properly placed I/O file to create your final I/O. The placed I/O file for this design is samples/mult16chip.ioc. From the Unix prompt enter:
/CMC/kits/cmosp35/samples/feeder.pl ../../samples/mult16chip.ioc > placed.ioc

placed.ioc is the final I/O Init file that will be used, and it contains four PFEED20 cells for each I/O and corner cell. A placed.ioc file also exists in the samples directory if you wish to compare results or are unable to run Perl. If your design is core-bound, additional feeder cells will need to be added to your I/O ring in order to ensure the ring is properly and fully connected. There are no automated checks to ensure the I/O ring is properly or fully connected, so the ring should be visually inspected by the designer often during the placement and routing process.

CMOSP18 7.4.3 The CMOSP18 kit has a more robust Perl routine for adding feed cells to the I/O floorplan. The new routine, feedx.pl, is not technology-specific, and allows the user to specify different configurations of feeder cells as needed for their particular design. For the purpose of this tutorial we will target an I/O pitch of 100 microns. Since the I/O cells are 40 microns wide, we need to add three PFEED20 cells between each I/O pad. The new command to do this is:
/CMC/kits/cmosp18/samples/feedx.pl ../../samples/mult16chip.ioc \ 3 tpz973g/PFEED20/abstract > placed.ioc

Note the "\" character is a Unix line continuation character, and the command can be typed on two Unix command lines as shown (hitting <Return> after the "\", or can be typed as one long line without using the "\" character.

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7.4.4

To load this new I/O Init File, make changes to the Design Planner Place I/O Initialize form as follows: I/O Init Mode: load file&auto place I/O Init File Name: placed.ioc I/O Init I/O boundry Mode: generate new I/O Init I/O to I/O Min Distance: 0.0 Click Apply & Close

Justify your I/O placement 7.4.5 From the areaPdp--Editing window select: Place -> I/O -> Justify... In the Design Planner Place I/O Justify form set: I/O Corner to I/O Distance: 0.0 Click Apply & Close You may get an error related to the Boundary and other "Infos". Close inspection is the best way to tell whether the I/O ring is OK. This last step should ensure your I/O ring is properly connected by abutment. You should visually check that there are no gaps in the I/O ring. To do this, zoom in on the I/O ring, and pan around the design. If there are any problems, or required changes to your I/O ring, you can repeat the initialize I/O step, and subsequent steps. You do not need to add corner cells again (once they have been added to your design). Figure 7.1 illustrates many of the steps youve taken so far. Subsequent steps in 7.5 and 7.6 will complete this diagram

7.4.6

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.
Sets of four 20-micron wide feeder cells I/O and power cells

Default

Corner Cells

Default group of unplaced cells created by Floorplan -> Groups -> Generated by Logic... User-drawn region of rows Estimated core area generated by Initialized floorplan placed inside the core with Place -> Blocks/Groups (Leggo) ...

Figure 7.1: Floorplanned design

7.5

Define and place groups


Once you are happy with the I/O ring, you can prepare to place your standard cells. Most designs which do not contain macro cells and are smaller than 500,000 cells should be placed flat. This allows the timing-driven features of the placement and routing tools to ensure critical nets meet timing. If your design contains pre-placed blocks (hard cores) they are also floorplanned at this step.

7.5.1

To create groups based on logic, from the areaPdp--Editing window select: Floorplan -> Groups -> Generate by Logic...

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If your design imported from Synopsys contains more than one level of hierarchy within the core, you can flatten it here by selecting Cells/Group Min: 100,000. This will ensure all groups are at least 100,000 cells large. Our sample design is much smaller than this. 7.5.2 Since we have only one level of hierarchy in the core, select: Utilization Pin Grid (um): 1.4 Click Apply & Close

CMOSP18 7.5.2 Change: Utilization Pin Grid (um): 0.66 This should create one group of cells called default located outside of your die area. Your group has the default area utilization of 75%. This means only 75% of the total area available for placing cells in that group is actually cell area, and the remaining 25% unused area can be used for adding power striping, space between rows of cells, space for adding clock tree buffers, and to reduce routing congestion. Experience will make you a better judge of what utilization factor is best, but since this sample design has so much wasted core area anyway, there is no point in trying to achieve greater utilization. 7.5.3 To place the group(s): Select Place -> Blocks/Groups In the Design Block/Group Placement form: Click Apply to have your block reshaped and placed in the core (sometimes this reshaping will not happen - this is not a problem). Be sure that your default group ( yellow box) is within the marked core area, otherwise you may have problems in Qplace. Exceeding the core area by only 10% will definitely cause errors in Qplace. If the default group cannot be placed inside the core area: Select Adjustable Core Area(%): 10.0 And Apply again 7.5.5 Close the Design Block/Group Placement form

7.5.4

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7.6

Create placement sites

Creating rows of placement sites: The placement tools require rows of possible placement sites where the I/O and core cells will be placed. Since the I/Os are already placed, the I/O rows are generated from the preplaced I/Os. The core placement rows are generated in a manually drawn region which is just larger than your placed block. If you had more than one placed block, your region of rows would have to cover all of the placed blocks in your core area. 7.6.1 From the areaPdp--Editing window, select: Floorplan -> Rows -> Create I/O Rows... In the Design Planner Draw I/O Site form select: Site Name: pad From Preplaced IOs Click Apply & Close 7.6.2 To create a region of cell placement site rows, select: Floorplan -> Rows -> Create Region of Rows... Since our design is I/O bound, and there is lots of cell area, rows will be placed with VDD rails at the top, VSS at the bottom, and a gap between the rows. If space is more of an issue, every second row can be inverted so the rails are abutted, and no gap is required between rows. 7.6.3 In this step you will be drawing a box around the core of your design (see dotted box in Figure 7.1). Before proceeding you may wish to zoom-in on the core area of your design by drawing a box around the core using the right-hand mouse button. You should be able to see all of the default group (yellow box containing green standard cells) before proceeding. In the Design Planner Draw Site Region form select: Channel Offset Offset: 1.25 Click Apply & Close

CMOSP18 7.6.3 Change: Channel Offset Offset: 1.12

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7.6.4

The bottom of your areaPdp--Editing window should now say: Please Specify Point 1 for RegionThe tool wants you to define the region which is filled by rows. If your default group (yellow box) is totally within the marked core area, you can draw the region larger than the group, but smaller than the core. If the group is partially outside your core area, draw the region just slightly larger than the default group. Once youve decided where to draw your region, click once to mark the upper left corner of the region, and once to mark the lower right (see Figure 7.1). If you are not happy with your region of rows, you can delete it with: Floorplan -> Rows -> Delete... and try again.

7.6.5

7.7
7.7.1

Define special nets


The last step in floorplanning is to tell the tool which are the special nets in your design. From the areaPdp--Editing window select: Floorplan -> Nets -> Setup Special Nets... In the Special Net Connectivity form, enter the following settings: Match Name? ON Net Name? clk or use Browse to select the root clk net Net Type: clock Click on Set By Net Type Click on Set Name Net Type In the same form, set up for VDD: Net Name? VDD Net Type: supply Click on Set Name Net Type In the DEF Print Properties section, Net name? VDD Ensure Special is set to (* VDD) Click on Set Net Properties Repeat the above steps for VSS. Net Name? VSS Net Type: ground Click on Set Name Net Type In the DEF Print Properties section, Net name? VSS Change Special to (* VSS)

7.7.2

7.7.3

7.7.4

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Click on Set Net Properties Click on Print Special Connectivity Summary to View File We have provided an example of a Summary for your reference.

# Special Net Connectivity Summary, May 11 16:57:30 1999 # Cell (design mult16chip autoLayout) # Net clk, Type clock # Net VSS, Type ground # Net VDD, Type supply (DEFSPECIAL_CONN (NET VDD (SPECIAL_SUM (SPECIAL (INST_TERMS 2136) (ROUTE_SHAPES 0 ) ) ENDSPECIAL_SUM) (DEF_SPECIALNETS "( * VDD )" ) ENDNET) (NET VSS (SPECIAL_SUM (SPECIAL (INST_TERMS 2136) (ROUTE_SHAPES 0 ) ) ENDSPECIAL_SUM) (DEF_SPECIALNETS "( * VSS )" ) ENDNET) ENDDEFSPECIAL_CONN) Note the INST_TERMS numbers will likely differ in your design from those shown above 7.7.5 Close the Special Net Connectivity form and Quit the ViewFile form.

7.8

Add power stripes (power planning)

Before the standard cells are placed, you need to add power stripes. These stripes, along with the power rails built into each standard cell, form a power and ground grid. The stripes are placed but not connected before the cells are placed so Qplace (the timing-driven placement engine) knows to avoid placing cells under the power stripes. 7.8.1 To add power stripes through your design, select: Floorplan -> Preroutes -> Supply Stripes...

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7.8.2

Modify the Design Planner Route Stripes form as follows: Net Name(s): VDD VSS Layer: metal2 Width(s): 3.2 3.2 Spacing 1.0 Start Position: 200 Number of Stripes: 3 Apply & Close

CMOSP18 7.8.2 Make the following changes: Width(s): 1.48 1.48 Spacing 0.5 Start Position: 70 Metal2 is selected for the stripes since it is the default metal for vertical routing (metal1 & metal3 are default for horizontal routing). The Widths of 3.2 and Spacing of 1.0 are selected to keep the center of the stripes on the 1.4-micron routing grid. It is just estimated that the design can use three pairs of stripes, and given the core is approximately 800 microns across, starting the first stripe at 200 microns will divide the core into approximately four equal sections. The number and spacing of stripes is dependent on the shape/size of your core and your power distribution requirements. If you don't like the routing, you can click Undo Last and preroute the power stripes again. 7.8.3 Save the design at this point. You have now completed floorplanning. File -> Save As... Save as: floorplan

THIS IS A NATURAL BREAK POINT

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MODULE 8: TIMING-DRIVEN PLACEMENT OF STANDARD CELLS

MODULE 8: TIMING-DRIVEN PLACEMENT OF STANDARD CELLS


Objective 8: To use forward-annotated timing information from Synopsys to place the core cells

RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Synthesis

Scan Insertion

8.1

Use the QPlace sequencer

Gate-Level Simulation

NOTE: When perfoming step 8.1, it is important that: 1. 2. Your Unix search path is set to include the present working directory Your account is set up to use all the Cadence tools from the .cshrc file. If the search path does not include ./ , perfoming step 8.1.4 will result in this error report: cannot find .run_sdf2def You can easily add ./ at the end of your Unix search path by adding the following to your .cshrc file: set present_directory = ( ./ ) set path = ( $path $present_directory)

Floorplanning

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

8.1.1

To bring up the placement sequencer, from the areaPdp--Editing window select: Place -> Blocks/Cells (QPlace)... In the Qplace Sequencer, select Sequencer Setup... In the Sequencer Setup form select: Under General Timing Driven Convert SDF Constraints SDF Constraints File: ../../Synopsys/mult16chip.sdf GCF Constraint File: ../../samples/mult16chip.gcf Under Placement (Qplace) Select Placement Options...

8.1.2

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MODULE 8: TIMING-DRIVEN PLACEMENT OF STANDARD CELLS

8.1.3

In the Qplace Placement Parameters form select: Prewire Keep Out? (this prevents cells from being placed under the power stripes.) Close the Qplace Placement Parameters and Sequencer Setup forms. In the Qplace Sequencer select: Congestion Map Display

8.1.4

NOTE: There is currently a bug in the Design Planner Sequencer which causes the sequencer to fail if steps are run one by one, instead of using the sequencer to run all the placement steps at once. Also, since the Qplace sequencer spawns a new Unix shell to run the Qplace tools, your account MUST be set up to use all of the Cadence tools in your .cshrc (or equivalent) file. If you manually enter a command line script or use some other means of setting up your account to work with Cadence tools, it is likely the next step will fail since you will not be given the chance to set up the temporary shell used to run Qplace. Also, this step will fail if your .cshrc file has an "exit" statement located before the statement(s) that sets your Cadence environment. 8.1.5 Click Apply in the Qplace Sequencer This step insructs Design Planner to: - create a library description file (LEF) listing the cells included in the design - create a design file (DEF) containing the cell interconnect information but no placement information at this time - create a timing constraints file based on the .sdf file from Synopsys - use all these files to call Qplace, the timing-driven placement engine. Qplace will create a new .def file which is then imported back into Design Planner. With luck there will be no problems! Qplace works by placing cells in various sites while trying to minimize the length of nets required to connect the cells. When timing-based placement is selected, the nets are given weights based on how much timing slack (or negative slack) exists in each net. Placement on this design takes about 10 minutes on an Ultra Sparc 10. Your own design will likely take longer depending on design size, number of critical nets, and CPU resources available.

8.1.6

Once Qplace has completed, Save your design as placed. You should now ensure the placement step worked (if not, your future steps will also fail). One way to tell is to zoom-in on the core of your design, and see if the cells are now spaced out over the core area (instead of all packed together as they were in Figure 7.1).

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MODULE 8: TIMING-DRIVEN PLACEMENT OF STANDARD CELLS

You can also view the log files in the new mult16chip_QP directory and ensure there were no errors. A congestion map will have been imported. This map can be used to determine the estimated routing congestion for your design.

8.2
8.2.1

View placement congestion


You may turn off the site row display if you have the site drawing layer visible. In the Pillar window, select: Environment->Layers... Under Layer-Purposes select Site Drawing Deselect visible Click Redraw The congestion map display is much easier to read now.

8.2.2

8.2.3

To view the values that are displayed, zoom in closely on the congested area within the core. The congestion is displayed using the following format: h (6, 10, 20) v (6, 10, 20) where 6 is the number of tracks used 10 is the number of tracks available 20 is the number of tracks for all layers

8.2.4

To remove the congestion grid, from the QPlace Sequencer click on Options next to Congestion Map Display. In the Congestion Map Display form, click on Clear.

8.3
8.3.1

Perform timing analysis based on initial placement


Before you insert the clock tree, you should ensure that your placement will come close to meeting your timing constraints. The timing check can also be run a second time following the clock tree generation. Note the estimated delays on the clock net at this point. Do they change after clock tree insertion? To begin, select: Timing -> Analysis -> Setup Run Environment... In the DP Setup Run Environment window: Change the GCF File to ../../samples/mult16chip.gcf Click on Apply & Close.

8.3.2

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MODULE 8: TIMING-DRIVEN PLACEMENT OF STANDARD CELLS

8.3.3

To begin the timing check, select Timing -> Analysis ->Check Timing vs. Constraints... (NOTE: If you have your constraints and timing information captured in a gcf file you can use the Analyze Timing option from the Pearl menu instead. For more information on this see the Cadence documentation). In the DP Check Timing vs. Constraints window select: Display Graphical Interface Set the Create_New_SPF flag Change the Path Constraint Reference Type to SDF, and file name to ../../Synopsys/mult16chip.sdf Now click on the Pearl Delay/Parasitic Input: Options... button In the DP-Pearl Create RC Parasitics window, select: Create Using: CDS Steiner Tree Ouput As: rSPF Next click on the Create Using: Options... button In the Design Planner CDS Steiner Tree RC Option window, make sure the Extract Boundary Info flag is set on. Also turn on the Read Congestion Map flag and add the path to the congestion map created when running Qplace, mult16chip_QP/placed.congMap

8.3.4

8.3.5

8.3.6

8.3.7

Click Apply & Close in the Design Planner CDS Steiner Tree RC Option window. Click Close in the DP-Pearl Create RC Parasitics window. Click Apply & Close in the DP Check Timing vs. Constraints window. After a short while the Pearl GUI should pop up. The left hand side window is the Pearl Console window, and the right-hand side window shows the worst case possibilities of constraint violations in the Pearl Summary window. CMC has observed an error with some versions of Pearl where the Pearl Console is the only Pearl window that opens, and it contains an error message: Error: invalid command name "FindSDFPathConstraints" If you have this in your window, manually enter the command: cmd> findpathconstraints in the Pearl Console. This should cause the Pearl Summary window to be produced. The constraints used (set back when using Synopsys) set a maximum time for the data to become stable. The worst estimated result (least amount of slack time) is #1. If you click on #1 a new set of windows opens up showing a schematic of the path as well as a list of delays through each component. If you view your PDP design window you will see the path highlighted in your floorplan. If you click on any of the components or paths in the schematic or list, the appropriate gate or net will also be hightlighted in the floorplan.

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MODULE 8: TIMING-DRIVEN PLACEMENT OF STANDARD CELLS

You can also experiment with the timingverify, findpathsfrom clk ^, and checklimits commands as described later in section 11.4. Although minor violations may be corrected by timing-driven routing, the sample design had no problems at this point. All timing should easily be met at this point. When you are done close all the Pearl windows. To remove the highlighted path(s), select View -> Clear or just click on the Clear button in the areaPdp-Editing window.

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MODULE 9: CREATING A CLOCK TREE

MODULE 9: CREATING A CLOCK TREE


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 9: To add clock buffer cells and nets to create a balanced clock tree which exceeds the parameters specified in synthesis. Also, to generate a golden Verilog netlist of the design to be used for final verification

Synthesis

Scan Insertion

Gate-Level Simulation

Now that the cells have been placed, the clock tree can be created

Floorplanning

9.1

Define the clock tree

Placement

A clock tree will be synthesized to replace the existing clock tree. Since Synopsys was instructed to not touch the clock tree, it currently consists of one net called clk_top. CT Gen will be told to replace clk_top with a balanced tree meeting the desired performance criteria. 9.1.1 To define the clock net select: Place -> Clock -> Setup -> By Name... In the Design Planner Create Clock form enter: Clock Net Name: clk_top Options... In the Design Planner Clock Tree Options form, enter values to match the clock specified in Synopsys, but over-constrain the Max Skew by a bit. Note the I/O instance name of the clock input pad is pclk from the original rtl.v file, and the output pin of that cell is C from the I/O cell html data files. Enter: Clock Root Driver: pclk (the instance name of mult16chips clock input pad) Root Output Pin: C Wave Rise Time: 0.2 Wave Fall Time: 0.2 Wave High Time: 9.8 Wave Low Time: 9.8 Min Insertion Delay: 0.0 (default) Max Insertion Delay: 10 Max Skew: 0.01

Clock Tree Generation

Routing & Timing Verification

Physical Verification

9.1.2

9.1.3

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MODULE 9: CREATING A CLOCK TREE

Max Transition: 2.0 Click Apply & Close Close the Design Planner Create Clock form. 9.1.4 From the areaPdp--Editing window select: Place -> Clock -> Generate (CT-Gen)... In the Design Planner CTGen Sequencer select: Sequencer Setup... 9.1.5 In the Design Planner CTGen Global Options form, enter: Destination View: CTGenPlaced GCF Constraints File: ../../samples/mult16chip.gcf Close Click Apply Close in the Design Planner CTGen Sequencer window.

This step takes a few minutes

9.1.6

If CTGen is successful, you should be able to open the new design. From the Pillar window select: File -> Open... You may need to select Libraries -> design Double-click on CTGenPlaced This design only exists in memory at this time. To save the CTGenPlaced design to disk, select: File -> Save

9.1.7

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MODULE 9: CREATING A CLOCK TREE

9.2
9.2.1

View the clock tree


To have the clock tree highlighted, select Edit -> Select or just click on net under Select in the areaPdp--Editing window. Then click on By Name... In the Select/Deselect by Name form, enter: Name: clk Name Match: wildcard Type: inst Then to have the tool highlight all the instances with clk in their name, click on: Select/Deselect: Type+ To remove those, click on Type- or All TypeExcept for the clock pad in the I/O ring, all of the highlighted instances should be new cells used to buffer the clock tree. To see flight-lines representing the clock tree nets, change: Type: net Click: Select/Deselect: Type+ The clock nets form a structured tree pattern with the trunk of the tree connecting these new buffer (or inverter) cells, and the leaf nodes of the tree being clock pins on your designs Flip-Flops (FFs). You can open the placed design and repeat. You should find the only "clk" instance is the I/O pad, and that the clk nets are a crude string of nets going from one FF clk pin to another.

9.2.2

9.2.3

9.2.4

Details on what CTGen actually did to your design can be viewed in the mult16chip_CTGEN/rpt directory. A sample final.timing file is shown (note that your results may not be the same): Report: ./rpt/final.timing Design: mult16chip Clock tree root: pclk C Timing start pin: pclk C Max. transition time at leaf pins: Min. insertion delay to leaf pins: Max. insertion delay to leaf pins: Max. skew between leaf pins: 0.092 ns 1.303 ns 1.315 ns 0.012 ns 0.106 ns 0.384 ns 0.393 ns 0.008 For CMOSP18

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MODULE 9: CREATING A CLOCK TREE

Note that CTGen tried to meet the constraints placed earlier. The 0.012 ns max. skew between leaf pins is greater than the 0.01 ns specified, and this shows up as a violation in final.violations. The 0.012 max skew is still considerably smaller than the 0.5 ns value which was used for design synthesis when the clock was specified in Synopsys. The skew was over-constrained for demonstration purposes in order to get CTGen to create a nice looking clock tree. This design would probably be OK with a specified max skew of 0.3 or more.

9.3

Write out the "golden netlist"


Now that this design has a clock tree, the netlist (cells and connections to them) should not need to be changed. At this point we generate a "golden" gate-level netlist which should be re-simulated to ensure none of the steps so far have broken the design. Assuming all simulations are OK this "golden" netlist will be used as the schematic when the final layout is verified with automatic Layout Vs. Schematic (LVS) at the end of the design cycle.

9.3.1 9.3.2

In the Pillar window select: File -> Export -> Verilog... In the plr2ver form, enter: Source Library Name: design Source Cell Name: mult16chip Source View Name: CTGenPlaced Verilog File Name: mult16chip_gold.v Click on Physical Nets Removal Options... In the Physical Nets Removal Options window, select: Do not remove Power/Ground Nets Click OK Do not click Remove Specific Nets, since no nets or cells need to be removed.

9.3.3

9.3.4

In the plr2ver form select: Tie Net Options... In the Tie Net Options window enter: Tie Up Net(s): VDD Tie Down Net(s): VSS Tie Net Handling Method: Supply Signal Click OK

9.3.5

Again in the plr2ver window, select: Print Informational Messages Click OK

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MODULE 9: CREATING A CLOCK TREE

The command should complete without errors. CMOSP18 9.3.6 To prepare the Verilog netlist for LVS, follow the instructions in the Digital Design Tips file in the kit documentation and add VDD/VSS ring pads.

9.4

Add a power ring around the core

Before proceeding to Silicon Ensemble to route the design, you will add a core power ring. The purpose of the core ring is to form a power distribution network connecting the existing stripes, and power rails. 9.4.1 9.4.2 In the areaPdp--Editing window ensure you are still editing the ctgen version of your design, and select: Floorplan -> Preroutes -> Supply Rings... In the Design Planner Route Rings form change: Net Name(s): VDD VSS Ring Mode: core LayerH Width(s) 30 30 Spacing(s): 30 5 LayerV Width(s) 30 30 Spacing(s): 30 5

CMOSP18 9.4.2 Change: LayerH Width(s) 15 15 Spacing(s): 15 3 LayerV Width(s) 15 15 Spacing(s): 15 3 Click Apply The supply ring width was selected to avoid problems related to the maximum metal width size of 35. If your design power requirements need a ring wider than 30 microns, you will need to slot the metal lines before Design Rule Check (DRC). The power rings were added after Verilog out to avoid a problem with via instances being added to the golden netlist. 9.4.3 9.4.4 If you are not happy with it, you can click Undo Last to delete the power ring, and place it again. In the areaPdp - Editing window, resave the CTGen Placed view by selecting: File -> Save

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MODULE 9: CREATING A CLOCK TREE

9.5
9.5.1

Export the placed design


This design can now be exported to Silicon Ensemble. From the areaPdp--Editing window, select: Interfaces -> Silicon Ensemble -> Export -> LEF... In the hld2lef window: LEFOUT File Name: mult16chip_dp.lef Ensure Output All Instances is selected. Select LEF DB UNITS: 1000 Click OK

9.5.2

9.5.3

Select: Interfaces -> Silicon Ensemble -> Export -> DEF... Make the following changes to the hld2def form: Output Def File Name: mult16chip_dp.def DEFOUT Sections: Technology, Floorplan & Pins DEFOUT Components: Cells&Placement DEFOUT Nets/Special Net: Nets&Routing DEFOUT Net Selection: All (default) DF DB Units: 1000 Click OK

9.5.4

9.5.5

From the Pillar window select: File -> Exit... You are now ready to route your design from Silicon Ensemble

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MODULE 9: CREATING A CLOCK TREE

CMOSP18 9.5.6 Modify the LEF file for Wroute with antenna fixing in Silicon Ensemble (SE) The antenna fixing features in the Wroute tool of SE5.3 can only be applied to the LEF file found in V3.0 of the CMOSP18 kit. If you are using the CMOSP18 kit, you should comment out all the antenna LEF syntax used in the file you just exported from areaPdp. From the Unix prompt enter: vi mult16chip_dp.lef In the vi window enter: :%s /ANTENNASIZE/#ANTENNASIZE/g Save the file and quit: :wq cd ../.. .

THIS IS A NATURAL BREAK POINT

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MODULE 10: IMPORTING THE PLACED DESIGN

MODULE 10: IMPORTING THE PLACED DESIGN


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 10: To verify the functionality of the golden netlist, then import into the Silicon Ensemble environment all of the design libraries and constraints needed to route the design

Synthesis

Scan Insertion

Gate-Level Simulation

This Module and Module 11 make use of the Silicon Ensemble interface to route the power, clock, and regular nets of the design, and then again using Pearl analyze the timing of the design based on extracted parasitics of the routed nets.

Floorplanning

Placement

10.1

Simulate the golden Verilog netlist

Clock Tree Generation

Before importing the placed design into Silicon Emsemble for routing, it is good practice to verify that the current design is functionally equivalent to the original gate level design. To do this, the golden Verilog netlist is simulated. 10.1.1 To repeat the Verilog simulations, first: cd cmc_digflow/HDLs/ cp ../dp/run/mult16chip_gold.v . To simulate these different test benches, follow the same steps as in 6.2.2 and 6.3 EXCEPT use mult16chip_gold.v in place of mult16chip_gates.v wherever it occurs. You will notice fewer "Too few module port connections" warnings now since PDP included VDD and VSS connections in the Verilog netlist. Some designers may want to include extracted timing delays in the form of an SDF file generated in Silicon Ensemble, however since Pearl static timing analysis will confirm that there are no timing violations in the design, the purpose of the Verilog simulation is strictly to confirm that the functionality of the netlist remains the same as it was before the clock-tree was inserted. Once satisfied that the "golden netlist" has all the desired functionality, you can continue with the design flow, and route your design. Later the golden netlist will be compared with the final layout to ensure the layout submitted for fabrication contains the same components and connections as the Verilog netlist which has just been shown via simulation to be correct.

Routing & Timing Verification

Physical Verification

10.1.2

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MODULE 10: IMPORTING THE PLACED DESIGN

Before attempting this module for your own design a Global Constraint File is needed. For this design example, a GCF file has already been created and exists in the samples directory.

10.2

Start Silicon Ensemble

TIP: If you enable your NumLock key, Silicon Ensemble may behave strangely when zooming in, moving cells, or using the ruler... so leave your NumLock key off!!! 10.2.1 To change into the SE directory, at the Unix prompt enter: cd cmc_digflow/se Ensure you have an appropriate se.ini file by entering: more se.ini The se.ini file is technology-specific, and sets the environment for Silicon Ensemble, including the path to the library (dbs) where all designs will be saved. It also sets some other default values (Verilog bus delimiter, placement and routing variable, etc.). 10.2.3 Since HLD Unix shell variables should not be set when you use SEUltra or SE-Signal Integrity, you should unsetenv all these variables before you run Silicon Ensemble. At your Unix prompt, type setenv to list all the enviroment settings. unsetenv all those settings with HLD: unsetenv HLD_INSTALL_PATH unsetenv HLD_TECH_DIR To start up Silicon Ensemble, at the Unix prompt enter: sesi -m=200 &

10.2.2

10.3
10.3.1

Import the results from Design Planner (PDP) into Silicon Ensemble
A library database must be created or loaded before you import the netlist. This was saved in PDP. File->Import->LEF... In the Import LEF form: Select: ../dp/run/mult16chip_dp.lef Select OK This creates a library database in memory. This database contains a complete technology section and physical descriptions of each macro cell (by size, symmetry characteristics, pins and blockages) for each cell used in your design.

10.3.2

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MODULE 10: IMPORTING THE PLACED DESIGN

There should be no errors with the library. The .lef file just imported contains all cells used in your design. If for some reason you wish to add/change cells in Silicon Ensemble, you may also need to import a LEF for the standard cell library. This would be needed if you used CT-Gen, or Placement Based Optimization (PBO) within Silicon Ensemble. Modifying the cells used in your design would also make it necessary to re-generate a "golden" Verilog netlist. 10.3.3 To create the design database, select: File-> Import DEF... ../dp/run/mult16chip_dp.def Click OK You should have three warnings, two about importing cells that dont have VDD or VSS connections (these are PFEED20, PVDD2, and PVSS2 cells) and a warning about changing the design name. All of these are OK. CMOSP18 10.3.3 To pass the additional antenna LEF file into Wroute, in the command line at the bottom of the SE window type:
SET V WROUTE.ADDITION.LEFNAME "/CMC/kits/cmosp18/VSdir/lef/vst_n18_antenna.lef" ; SET V WROUTE.ANTENNA.REPORT.NAME "mult16chip_antenna.rpt" ;

10.4
10.4.1

Import design-specific constraints


You now need to import a timing library for use by Wroute (the Timing-Based Router). The timing libraries to be used are specified in a design specific global constraints file which has been created for this design. File -> Import -> Timing Library...

10.4.2

In the Import Timing Library form, select: ../samples/mult16chip.gcf Click OK You should not have any errors but you may have warnings about the PVDD2 and PVSS2 pads. This design-specific constraint file will be used later as a means of defining the system clock prior to timing analysis. The user can specify which set of timing libraries to use for their design in the gcf file. In the case of this design, worst-case timing values are used.

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MODULE 10: IMPORTING THE PLACED DESIGN

10.4.3

From the main Silicon Ensemble window, select: File -> Import -> System Constraints... Select the file: cmc_digflow/samples/mult16chip.gcf Click OK The system constraints set in this file are an ideal 50 MHz clock, and 20 pF pin loads.

10.4.4

Finally you need to import your original constraints file from Synopsys. File -> Import -> SDF... In the Import SDF form enter: ../Synopsys/mult16chip.sdf Click OK If your design is not already visible, you can click on the "Fit" button located on the lefthand side of the Silicon Ensemble main window. Your design has been imported in with the default name "LIBRARY".

10.4.5

10.4.6

To save this as a Silicon Ensemble database. Select: File -> Save As... In the Save As form, enter: a Design Name of from_dp

This is a good time to look around the Silicon Ensemble tool, and look further at your design. If you zoom in on your design core, and continue to zoom in, you will eventually see the "routing grid". All of the pins in the core of your design should be centered on the routing grid. Most steps already completed in PDP can also be run from within Silicon Ensemble. Unfortunately the setup files for each tool are different, so the commands do not look/feel the same. In industry almost all CAD tools are run as batch scripts from the command line. This is to minimize the amount of time and money required when a tools license needs to be "checked out"

THIS IS A NATURAL BREAK POINT

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MODULE 11: ROUTING

MODULE 11: ROUTING


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Synthesis

CMOSP18 ROUTING WITH ANTENNA AND CROSSTALK FIXING


Scan Insertion

Objective 11: Using existing timing constraints, route the design and verify the routed design meets timing goals

Gate-Level Simulation

Floorplanning

11.1 Route power


The first step is to route the chips power nets. If you have previously exited from the Silicon Ensemble tool, you should reload the from_dp version of your design. 11.1.1 In the main window select: Route -> Connect Ring... Ensure the Nets are set to "VSS" and "VDD" (The quotes are optional). 11.1.2 This design has no Blocks, or I/O Ring (the I/O are already connected by abutment). So only the other three options need to be run. Deselect: Block Deselect: IO Ring Click OK the Connect Ring form. You may get messages about "A normal via may be lost..." however these are not a problem. 11.1.3 Once the power routing is complete, click the Fit button, and see if there are any violations. These will show up as Xs in the design. If you have no violations you can skip to step 11.1.5 to save your design and continue to route the clock nets. CMC has found that there are violations quite often when routing power. One step which has been taken to reduce problems is moving the Power pads to the center of the I/O ring sides. 11.1.4 If your design did not route on the first attempt, one thing to try is: Reload the from_dp design (File -> Open...) Bring up the Connect Ring form Deselect: Block, IO Pad & IO Ring With Stripe and Follow Pins selected, click Apply.

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

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MODULE 11: ROUTING

Click Fit to see if any errors exist. If not, deselect: Stripe & Follow Pins Select: IO Pad Click Apply If there are no error markers after clicking the Fit button you can proceed to Wroute. If you still have violations, you will have to experiment to resolve your power routing problems.

CMOSP18 11.1.4 It is recommended that you run Verify -> Geometry now to check if there are any violations in power routing. 11.1.5 Before attempting to route the design... File -> Save As... Design Name: preroute

11.2 Route the clock nets


Since the most critical nets in your design are typically your clock tree, they will be routed first. 11.2.1 From the main window select: Route -> Clock Route... Enter: Maximum Clock Skew (ns): 0.1 This is more than the PDP predicted limit of 0.010 but still less than the Synthesized value of 0.5. It is the 0.5ns maximum clock skew that all the other timing constraints are based on, so in order for your constraints to be valid the clock skew must be constrained to under 0.5ns. 11.2.2 Click OK the ClockRoute form. You should get a report that ends something like:
... clockRoute clockRoute clockRoute clockRoute clockRoute clockRoute clockRoute clockRoute clockRoute clockRoute clockRoute : : : : : : : : : : : =========================================== ============ ClockRoute Result ============ =========================================== Tree 1: Clock tree root: pclk C M1 wirelength: 2348 [19%] -> 2347.8 [19%] (100%). M2 wirelength: 6278 [51%] -> 6277.9 [51%] (100%). M3 wirelength: 3573 [29%] -> 3572.5 [29%] (100%). Wirelength: 12198 -> 12198 (100%). Min delay :792 ps -> 792 ps (100%). Max delay :801 ps -> 801 ps (100%). Max skew :9 ps -> 9 ps (100%).

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MODULE 11: ROUTING

clockRoute : =========================================== clockRoute : More details in clockRouteRun/clock1.path,clockRoute.rpt. clockRoute : ===========================================

This shows the Insertion delay (time from I/O pad to leaf-cell) ranging between 0.792 and 0.801 ns for a maximum clock skew of 0.009 ns. This is even lower than the PDP predicted value. 11.2.3 If you zoom in on the core of your design, you should see a few added traces. To see what the routed clock tree looks like. Select: Edit -> Find... In the Find form, enter: Type Net: Name: clk* Select Hilight The clock net should be shown on your design. Note that the traces all follow the routing grid now, but the general shape is the same as was shown in PDP. 11.2.4 Once done using Find, click on: Dehilight All then Cancel

11.3 Perform timing-driven routing


CMOSP18 11.3 Perform timing-driven routing with antenna fixing The remainder of your nets can now be routed with Wroute. 11.3.1 To run Wroute select: Route -> Wroute... In the Wroute form note that Global and Final Route, as well as Auto Search And Repair are already selected. Click on: Timing Driven Routing Click on: Options In the Options form, set Nets to Route to All Click OK Close the Options form Click OK

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MODULE 11: ROUTING

This step will take a few minutes.

If everything has gone right so far, Wroute should be able to route your design. In the sample case, 482 Violations existed after initial routing, but after 6 automated search and repair passes all of the violations were corrected.

11.3.2 Save the design as: wroute Zooming in on the core of your design will show a considerable number of traces. 11.3.3 You can now have Silicon Ensemble run a couple of basic checks on your design. Neither should produce any errors: CMOSP18 11.3.3 Before Verify -> Connectivity: Add Verify -> Antenna... Click OK Verify -> Connectivity... Click OK Verify -> Geometry... Click OK Any problems (marked with Xs) will need to be identified and corrected

This step will take a few minutes.

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MODULE 11: ROUTING

11.4 Verify timing


The final step in Silicon Ensemble is to do a timing check to ensure the routed design still meets the specified timing constraints. CMOSP18 11.4 Analyze crosstalk For the remainder of this module, the steps required to use CMOSP18 are significantly different from the steps for CMOSP35. All the steps for CMOSP18 are therefore included at the end of this module. 11.4.1 Select: Report -> Timing Analysis... In the Report Timing Analysis form select: Violation types: All Generate RSPF Interactive mode Click OK After a few minutes of processing, the Pearl Console window will appear. Because of the way the automated scripts work, only violations will be displayed automatically. If your design meets your timing constraints, nothing will be displayed in the Pearl Summary window. 11.4.2 To repeat the timing verification check, enter the Pearl command: cmd> timingverify The 10 worst Setup, Hold and pulse Width paths should be displayed. You can click on any path of interest and view the schematic of that path in the Path Schematic window (you may need to open this by clicking on Path Details Window under "Windows").

11.4.3 Also of interest may be: cmd> findpathsfrom clk ^ This command will show the longest delay timing paths generated by a rising clock edge. 11.4.4 Another report that shows potential problems is: cmd> checklimits which shows any nets that violate the libraries 1.5 ns maximum slew limit. Violations here imply that those nets change value too slowly, and this could be a design problem. If your design meets all other timing goals, and you have minor slew violations, you may be able to ignore these. Violations here likely indicate that net will draw more power than average because of the slower transitions. In the sample design there were minor slew limit violations on nets driving I/O pads.

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MODULE 11: ROUTING

11.4.5 Quit Perl with File -> Exit

11.5 Export the routed design


If you are confident that your routed design meets the timing goals, you can now export the design DEF for importing into the Cadence DFII environment for LVS and DRC verification, metal slotting, adding a logo, and stream out into a GDSII database. 11.5.1 To write your DEF, select: File -> Export -> DEF... Click OK the Export DEF form.

THIS IS A NATURAL BREAK POINT

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MODULE 11: ROUTING

CMOSP18 11.4 Analyze crosstalk


For crosstalk analysis, you must first run the Affirma HyperExtract parasitic extractor to get the grounded and coupling capacitance and generate a crosstalk report. CMOSP18 11.4.1 To extract capacitances for crosstalk analysis using the HyperExtract parasitics extractor: Select Report -> RC CMOSP18 11.4.2 In the Report RC form Report Filename: wroute.rspf (default) In Extraction Model, select: Hyperextract HyperRules Name: /CMC/kits/cmosp18/samples/cmosp18.rules CMOSP18 11.4.3 Click More HyperExtract Options In the Hyperextract Options form: Click Signal Integrity in the upper right of the HyperExtract Options form. Select Coupling File Select Capacitance Threshold Select Length Threshold (microns) Click OK the HyperExtract Options form CMOSP18 11.4.4 Again in the Report RC form: Select view Report Click OK the Report RC form It is not recommended that you exit Silicon Ensemble inside Module 11, but if you do you will need to re-import your gcf file.

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MODULE 11: ROUTING

CMOSP18 11.5 Generate crosstalk report


After parasitics extraction, the wroute.xcoup file has the extracted grounded and coupling capacitances. Now you can run the crosstalk magnitude calculator to: 1) examine the effects of the crosstalk on overall stage delays, 2) compute the delays, and 3)send the delays to the timing analyzer. After the usual timing analysis has run, the timing analyzer in Pearl analyzes the design for crosstalk glitches and crosstalk effects on timing. This analysis is based on all of the following: 1) the cross-coupling capacitances derived by the parasitics extractor, 2) internally calculated timing windows that define signal switching relative to the clocks, 3) GCF clock definitions and 4) TLF crosstalk limits. It writes the results to the report file. CMOSP18 11.5.1 Select Report -> Timing Analysis In the Report Timing Analysis form, select: Timing Check: All Click on all the electrical rules checks CMOSP18 11.5.2 Click on Report Cross Talk HyperExtract RSPF File: wroute.rspf (default) Coupling Capacitance File: wroute.xcoup Report File Name Prefix: wroute_xtalk Click on Interactive Mode Click OK The crosstalk calculator will generate three files: a .err file, a .repair file, and a .rpt file. After a short while the Pearl GUI should pop up. You may get a report that has something like:

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MODULE 11: ROUTING

CMOSP18 11.5.2 contd


... Reading (C)TLF file '/CMC_DEV/kits/VSlibrary/cmosp18Lib.2/tsm_library/ctlf/timingvst_n18_sc_tsm_c4_wc.ctlf' (C)TLF library open is OK. Timing window file 'wroute_xtalk.twf' read OK. 2 signals too fast, 0 signals too slow. 1000 nets 2 nets had no input C - consult log file for details 2 inconsistencies in HyperExtract output 0 nets claimed N coupling caps, but had different no. 2 nets had more coupling than total capacitance 0 pin lists with fewer pins than they said they had. 0 nets with bizarre cap/unit length 2 nets had implausible coupling ratios. 2 wires had implausibly small Rs. 2 rising drive and 2 falling drive implausibly small. 1811 nets processed, total wire 181922.4 0 unknown nets encountered (maybe with repetitions) 58 constant nets, length 64969.4, ( 35.7%) 5 nets had errors, length 8204.9, ( 4.5%) Max crosstalk induced timing delta is 2.9n, (0 > 1us) Sum of all error voltages is 0.527 volts The log file contains a more detailed description of any problems encountered. Crosstalk Magnitude Calculation complete Check log file wroute_xtalk.log for messages Annotating SDF files ...

You can check the .rpt file and .err file for details about crosstalk violations.

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MODULE 11: ROUTING

IMPORTANT Please note that there is a compatibility problem between Silicon Ensemble and DFII and if you use the fix shown below in 11.6 to 11.9, your file will not stream in correctly into DFII and you will not be able to DRC. You should do the step 11.3.3 in the original text, but it is NOT recommended that you do the other steps in 11.6 to 11.9--they are provided here for your interest only at this time.

CMOSP18 11.6 Fix crosstalk problems


There are two solutions for crosstalk problems. The placer implements buffer insertion and driver upsizing, and the router implements shielded routing. Shielded routing is recommended in this tutorial to fix the crosstalk problem. Shielded routing creates power and ground nets on both sides of selected signal nets to shield the signals from crosstalk. The nets with violations are listed in the .repair file. Detailed information about these violations can be checked in the .err file. 11.6.1 Select Edit -> Find Type: Net Click on Show List 11.6.2 Name: (Type one of the names of the victim nets listed in the .repair file -- for example, prod_top_21_) Click Find Now prod_top_21_ will display in the list window Select prod_top_21_ Click Select 11.6.3 The net named prod_top_21_ will be hightlighted in the design window. Zoom in with your right mouse button. Select Edit -> Properties... The Name: prod_top_21_ should be displayed in the Edit Properties window SHIELDNET (value): VSS ( you can also choose VDD or both ) Click OK

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MODULE 11: ROUTING

11.6.4 Click Deselect all 11.6.5 Repeat steps 11.6.2 to 11.6.4 (from above) until all the SHIELDNET properties of the victim nets have been set. Click Cancel in the Find window

CMOSP18 11.7 Re-wroute the design


11.7.1 Now re-wroute the design with crosstalk fixing: Select Route -> Wroute... Click Options 11.7.2 In the WRoute Options window: Nets To Route: All with Named Nets First Type the names of the victim nets listed in the .repair file into the blank, for example: prod_top_21_ prod_top_7_ prod_top_8_ prod_top_6_ prod_top_12_ OK the WRoute Options window 11.7.3 Click Timing Driven Routing Click OK 11.7.4 After Wroute is finished, add filler cells to the design by following the instructions in the Digital Design Tips file in the kit documentation.

CMOSP18 11.8 Re-extract the RC parameters and re-check crosstalk violations after fixing
11.8.1 Repeat all the steps in 11.4 for CMOSP18 (see above) except in step 11.4.3, change the Coupling file name to after_fix.coup 11.8.2 Repeat all the steps in 11.5 except Report File Name Prefix: after_fix Check if there are still any crosstalk violations in the Pearl console window. If not, you can omit the following step and go to step 11.10

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MODULE 11: ROUTING

11.9 Fix crosstalk problems identified in crosstalk error file


If you still have several crosstalk violations, you should now do crosstalking fixing based on the .err file. The crosstalk error file contains detailed infomation about the nets with crosstalk violations, including the aggressor and victim nets. The default extension for this file is .err . The file contains syntax like the following:
Victim Net: prod_top_8_ (Driver: NOR2D1.Z) Edge: FALL Peak Glitch: 1.096 Glitch Limit: 1.000 Total Cc: 0.272p ( 75.8%) Cgnd: 0.0868p Rsource : 3829.9 Rwire: 494.3 Clock Group 1 GROUP_OF_50 MHz 50/50 Group cycle: 20n Peak glitch: 1.09625 @ 2.3n Cumul. Coupling Trans. Aggressor Glitch Glitch Cap Time Net --------------------------------------0.413 0.413 0.0987p 0.392n prod_top_12_ 0.377 0.790 0.0992p 0.569n prod_top_7_ 0.214 1.004 0.0508p 0.38n prod_top_4_ 0.088 1.092 0.0221p 0.481n prod_top_9_ 0.001 1.094 0.000391p 0.629n prod_top_6_ 0.001 1.095 0.000194p 0.35n prod_top_11_ 0.001 1.095 0.00019p 0.329n mult16bist/n164 0.001 1.096 0.000148p 0.346n mult16bist/n165 + 1 signals of 0.001 V or less Statistical: Biggest glitch expected during chip life is volts. 2.838

The name of the aggressor nets and how much they contribute to the glitch is listed in this file. For example, the Peak glitch of victim net prod_top_8_ is 1.096v, only 0.096v more than the limit. Note that prod_top_4_ and prod_top_9_ contributed 0.214v and 0.088v to the glitch respectively and it has not been shielded by VDD or VSS nets in the last fixing.

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MODULE 11: ROUTING

11.9.1 Fix crosstalk problems identified in error file Follow step 11.6 to shield prod_top_4_ and prod_top_9_ with either VSS or VDD or both. Then redo step 11.7 and step 11.8. Check the error message. If you still have violations, repeat step 11.9 again. 11.9.2 You can now have Silicon Ensemble run a couple of basic checks on your design. Neither should produce any errors: Verify -> Connectivity... Click OK Verify -> Geometry... Click OK Any problems (marked with Xs) will need to be identified and corrected

11.9.3 Before verifying timing: File -> Save As... Design Name: after_fixing

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MODULE 11: ROUTING

CMOSP18 11.10 Verify timing


The final step in Silicon Ensemble is to do a timing check to ensure the routed design with antenna and crosstalk fixing meets the specified timing constraints. 11.10.1Select: Report -> Timing Analysis... In the Report Timing Analysis form select: Violation type: All Generate RSPF Interactive mode Click OK After a few minutes of processing, the Pearl Console window will appear. Because of the way the automated scripts work, only violations will be displayed automatically. If your design meets your timing constraints, nothing will be displayed in the Pearl Summary window. 11.10.2To repeat the timing verification check, enter the Pearl command: cmd> timingverify The 10 worst Setup, Hold and pulse Width paths should be displayed. You can click on any path of interest and view the schematic of that path in the Path Schematic window (you may need to open this by clicking on Path Details Window under "Windows").

11.10.3Also of interest may be: cmd> findpathsfrom clk ^ This command will show the longest delay timing paths generated by a rising clock edge. 11.10.4Another report that shows potential problems is: cmd> checklimits which shows any nets that violate the libraries 1.5 ns maximum slew limit. Violations here imply that those nets change value too slowly, and this could be a design problem. If your design meets all other timing goals, and you have minor slew violations, you may be able to ignore these. Violations here likely indicate that net will draw more power than average because of the slower transitions. In the sample design there were minor slew limit violations on nets driving I/O pads. 11.10.5Quit Pearl with File -> Exit

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MODULE 11: ROUTING

CMOSP18 11.11 Export the routed design


If you are confident that your routed design meets the timing goals, you can now export the design DEF for importing into the Cadence DFII environment for LVS and DRC verification, metal slotting, adding a logo, and stream out into a GDSII database. 11.11.1To write your DEF, select: File -> Export -> DEF... Click OK the Export DEF form. NOTE: DEF OUT has problems with shielded net properties. Therefore DEF IN may not work in DFII.

THIS IS A NATURAL BREAK POINT

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MODULE 12: PERFORMING LVS VERIFICATION

MODULE 12: PERFORMING LVS VERIFICATION


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 12: To verify the physical (Placed & Routed) version of your design contains the same instances, nets, and connectivity as the verified "golden" netlist

Synthesis

Scan Insertion

CMOSP18 Remember your design name should be of the form: TCFuuxxx Where T represents a tutorial design, CF represents the CMOSP18 technology code, uu is the university code for your site, and xxx is your individual tutorial ID code assigned by CMC.

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

12.1 Start DFII with the appropriate technology


Layout-versus-schematic verification essentially compares one netlist (the one to be verified) to another (the golden reference). The netlist can come in the form of a schematic view, a netlist view, an extracted view or an autolayout view. In the digital flow supported by CMC, Diva LVS in Cadence Design Framework II is used to compare: 1. the final layout in the form of a DEF (Design Exchange Format) file created from Silicon Ensemble to the "golden" Verilog netlist which is created after clock tree synthesis and subsequently functionally verified.
Routing & Timing Verification

Physical Verification

2.

Since Diva cannot work directly with a Verilog netlist, the netlist must first be converted to a schematic view. Also the DEF file needs to be translated into layout view for the purpose of layout extraction. To perform LVS: 12.1.1 At the Unix prompt, enter the following to change your working directory: cd cmc_digflow/dfII To ensure your account is set up for the macro-extraction you will perform within Cadence, copy a .simrc file from the kits sample directory to your home directory, for example:

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MODULE 12: PERFORMING LVS VERIFICATION

cp /CMC/kits/cmosp35/samples/simrc.lvsMacro ~youraccount/.simrc

Type: startCds -t cmosp35 The main Cadence Command Interpretor Window (CIW) should open. CMOSP18 12.1.1 Change lines to:
cd cmc_diglow18/dfII cp /CMC/kits/cmosp18/samples/simrc.lvsMacro ~youraccount/.simrc startCds -t cmosp18

12.1.2 Create a working library attached to the CMOSP35 technology file by selecting: File->New->Library... 12.1.3 In the New Library form under the Library section enter: Name: design Under the Technology File section select: Attach to an existing techfile Click OK 12.1.4 An Attach Design Library to Technology File window should appear. Change Technology Library: cmosp35 Click OK

CMOSP18 12.1.4 Change: Technology Library: cmosp18_defin_techlib Click OK 12.1.5 Import the Verilog netlist into the library by selecting: File->Import->Verilog... 12.1.6 Make the following changes to the Verilog In form: Target Library Name: design Reference Libraries: tcb773p tpd773pn Verilog Files To Import: ../HDLs/mult16chip_gold.v -v options: /CMC/kits/cmosp35/models/verilog/nwb/bcells.v Power Net Name: POWER Ground Net Name: GROUND

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MODULE 12: PERFORMING LVS VERIFICATION

Click OK It will take a while to import the netlist, and you may get some "Waiting for ipc:1 to terminate" messages within the Cadence CIW window. You may also get a "Connectivity extraction failed..." warning message, but this does not seem to be a problem. CMOSP18 12.1.6 Change appropriate fields to: Target Library Name: design Reference Libraries: vst_n18_sc_tsm_c4 tpz973g Verilog Files To Import: ../HDLs/mult16chip_gold.v -v Options:
/CMC/kits/cmosp18/VSdir/verilog/tpz973g.v /CMC/kits/cmosp18/VSdir/verilog/vs18sc.v

Power Net Name: POWER Ground Net Name: GROUND Note both the tpz973.v (pad) and vs18sc.v (standard cell) libraries are entered in the -v Options: line of the form, separated by a space. Note all VDD and VSS signals should already be properly assigned in your mult16chip_gold.v netlist, and no nets should actually be assigned the names POWER or GROUND at this step. We cannot use VDD and VSS as power and ground at this step since Cadence has a problem assigning Global Net names for nets which already exist as explicit nets in your Verilog netlist. Note all VDD and VSS signals should already be properly assigned in your mult16chip_gold.v netlist, and no nets should actually be assigned the names POWER or GROUND at this step. We cannot use VDD and VSS as power and ground at this step since Cadence has a problem assigning Global Net names for nets which already exist as explicit nets in your Verilog netlist. 12.1.7 Click OK in the VerilogIn window. The Log File should contain a number of messages of the form: module AN2D1 already in target/reference library tcb773p and other than the above mentioned warning, no other errors or warnings should be present.

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MODULE 12: PERFORMING LVS VERIFICATION

12.1.8 You can File -> Close Window the Log File window. If you are interested in the source of the warning message, look at the vanerr.log file. You will see the Verilog Analyzer tool does not support the syntax used in some of the UDPs in the bcells.v file. This does not affect the importing of the netlist into Cadence.

12.2 Open your schematic


12.2.1 To view your design schematic, open the schematic view by bringing up the Library Manager. You can use Tools -> Library Manager or press F6 on your keyboard. In the Library Manager, click on: Library: design Cell: mult16chip Then right-click on View: Schematic. 12.2.2 Holding the right mouse button down select Open... This should bring up the Virtuoso-Schematic Editing window. You can now import the physical representation of your design.

CMOSP18 12.2.3 - 12.2.8 Note the following steps (12.2.3 - 12.2.8) are new steps which ensure the power rings on your design exist in your schematic. 12.2.3 In the Virtuoso - Schematic Editing window select: Check -> Rules Setup... 12.2.4 In the Setup Schematic Rules Checks form under Physical Checks select: Solder On CrossOver: Ignored Click on OK 12.2.5 In the Virtuoso - Schematic Editing window select: Edit -> Select -> All... OK the Schematic Select All form. This will take a minute or so. 12.2.6 In the Virtuoso - Schematic Editing window select: CMC SKILL -> Schematic -> Hook up pins

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MODULE 12: PERFORMING LVS VERIFICATION

CMOSP18 12.2.7 - 12.2.8 12.2.7 In the Hookup pins form remove all entries except: VDDCORE, VDDRING, VSSCORE & VSSRING OK the form. Again, it will take a few minutes. This will produce warnings of the form:
Warning: Pin "VDDCORE" on instance "pprod00": floating input/output. Warning: Pin "PAD" on instance "vdd_core": floating input/output. Warning: Terminal "VSSRING" in view schematic not found in "mult16chip symbol". Warning: Port number mismatch between views "schematic" and "symbol" of "design mult16chip".

Warnings of this form can be ignored. You will also have a warning box marked on your design which can also likely be ignored. You should not have any Errors (just warnings) at this point. 12.2.8 You can now check and save your design using the Check and Save icon (a box with a check mark in it) in the upper left corner of the Virtuoso - Schematic Editing window. Again it will take a while, but this time there should only be a few warnings and no errors. Warnings of the following form are normal:
Warning: Pin "PAD" on instance "vdd_core": floating input/output. Warning: Terminal "VSSRING" in view schematic not found in "mult16chip symbol". west.lakeWarning: Port number mismatch between views "schematic" and "symbol" of "design mult16chip".

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MODULE 12: PERFORMING LVS VERIFICATION

12.3 Import the DEF view from Silicon Ensemble


12.3.1 From the CIW window select: File -> Import -> DEF... 12.3.2 Make the following changes to the Read DEF File into CellView form: Library Name: design Cell Name: mult16chip View Name: autoLayout Use Ref. Library Names: tcb773p tpd773pn DEF File Name: ../se/wroute.def CMOSP18 12.3.2 Make the following changes to the Read DEF File into CellView form: Library Name: design Cell Name: mult16chip View Name: autoLayout Use Ref. Library Names: tpz973g vst_n18_sc_tsm_c4 cmosp18_defin_techlib DEF File Name: ../se/wroute.def Click OK Again it will take a few minutes to import the design into a dfII database. You may get the following warnings which you can ignore:
*WARNING* Failed to open cellView "design mult16chip autoLayout" in mode "r". *WARNING* InstTerm pclk C missing for cell PDI. Skipping. *WARNING* Rectangle being created has no area

12.3.3 Open the autoLayout view using the library browser. A CMC-provided Skill routine is used to slot all the wide metal busses in your design. If you have busses wider than 35 microns which have vias on them, additional manual edits will be required to slot the metal within the via instance, and remove extra vias. Once the autoLayout view is open, to ensure the design is saved to disk, select: Design -> Save 12.3.4 In the Virtuoso Editing... autoLayout window select: Tools -> Layout 12.3.5 CMC SKILL -> P&R -> Slot wide metal busses You can now save the modified design with Design -> Save

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MODULE 12: PERFORMING LVS VERIFICATION

12.4 Run LVS


12.4.1 Although this design will require edits, there is no point in proceeding if it does not still match your golden netlist. In order to find out, this physical layout is extracted, and then LVS (Layout Vs. Schematic) is run to determine if the extracted view matches your Schematic view. Select: Verify -> Extract... In the Extractor form: Extract Method: macro cell CMOSP18 12.4.1 Select: Verify -> Extract... In the Extractor form: Extract Method: macro cell Rules Library: cmosp18

Click OK You will get Warning messages about terminals in the autoLayout not present in the extracted view, but should have no errors. 12.4.2 Close the autoLayout window with: Window -> Close 12.4.3 Open the extracted view and run LVS by selecting: Verify->LVS... The LVS form should have design mult16chip schematic and design mult16chip extracted already filled in since those windows are open. If not, you can fill them in now. 12.4.4 Click Run in the LVS window. While LVS is running, you can select "Info" on the LVS form, and click on Run Info: Log File in the Display Run Information form. You may get some warning messages of the form: Warning: Unknown device "resistor" on a compareDeviceProperty command. These warnings are not a problem. When complete you should not have an LVS problem. The bottom of the si.log form should have something like:

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MODULE 12: PERFORMING LVS VERIFICATION

The net-lists match. layout un-matched rewired size errors pruned active total un-matched merged pruned active total schematic instances 0 0 0 0 0 0 0 0 1802 1802 1802 1802 nets 0 0 0 0 0 0 2051 2051 2051 2051 terminals 0

un-matched matched but different type total End comparison:

0 0 0 72 Jan 25 15:24:25 2000

Comparison program completed successfully.

12.4.5 You can now close all windows except the CIW and Library Manager

THIS IS A NATURAL BREAK POINT

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MODULE 13: FIXING MINOR DRC PROBLEMS

MODULE 13: FIXING MINOR DRC PROBLEMS


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 13: To use manual edits of the layout to fix minor DRC violations

Synthesis

Scan Insertion

This module saves the design under the view of "layout". For your own design, you may want to save changes to the layout at regular intervals. Note that the design is farily large at this point, and you may run into disk space problems. Also, once metal fill is added to your design, it is very difficult to view or edit the nets within your design.

Gate-Level Simulation

Floorplanning

Placement

13.1 Perform initial DRC


To view any problems that need correcting before placing the logo and metal fill in your design, you should run an initial Design Rule Check (DRC). 13.1.1 Open the autoLayout view, then Verify -> DRC You may need to select Tools -> Layout if the DRC Menu option is not selectable. In the DRC form click on Set Switches. Since this is a black-box design, and you have not added any of your own cells, select: interconnect_only OK the Set Switches and DRC forms

Clock Tree Generation

Routing & Timing Verification

Physical Verification

13.1.2

CMOSP18 13.1.2 Select: Rules Library: cmosp18 Click OK

This step takes a few minutes. It runs faster if you deselect Echo Commands in the DRC form.

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MODULE 13: FIXING MINOR DRC PROBLEMS

Once DRC has completed, any problems will be reported in the log, and highlighted with a flashing marker in the autoLayout view. In the case of the sample design there were: 2 metal1 maxSize is 35.0um x 35.0um 2 metal2 maxSize is 35.0um x 35.0um 13.1.3 Before editing the design to fix these problems, save your design, changing the View Name to layout. You may wish to also save a backup copy of your layout at this point in case you run into problems editing the layout. 13.1.4 Close the autoLayout window, and open the new layout view.

13.2 Clean up the layout


Before your design can be fabricated, the DRC problems must be fixed. You can zoom in on a flashing marker, or have Cadence zoom in automatically. 13.2.1 To have the tool auto-zoom: Select: Verify -> Markers -> Find Select: Zoom To Markers in the Find Marker form Click Apply

Errors in different designs will vary. The sample design had only one type of errorthe size of metal in via arrays joining the 70-micron wide power traces violates the 35 by 35-micron maximum metal size allowed in this technology. If you have other errors in your design, you should understand what they are, and why they exist. One or two errors may be hints to other problems. Numerous errors usually indicate a problem earlier in the flow. 13.2.2 The specific details of editing via arrays to correct the metal size errors will vary from design to design. It is best to have an experienced person show you the procedure. A summary of the steps is listed below. It is very important to ensure that no mistakes are made in this step!! 1. 2. Flatten the instance so the vias are selectable Using the Layer Selection Window (LSW) make only vias selectable. Select and delete vias where slots will (or currently do) exist, or delete one set of vias if you have via overlap problems.

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MODULE 13: FIXING MINOR DRC PROBLEMS

3.

Make only drawing metal selectable and visible, and using chop open up slots where they currently exist, and lengthen slots where needed. Remove the left-over instance markera small diamond shape that should only be selected by drawing a box around it. Do not try and click on it, as it is difficult to tell what has been selected.

4.

CAUTION!! Errors made editing power net connections can cause a chip to fail, but may not be detected by subsequent LVS or DRC steps!!

13.3 Fix "metal maxSize is 35.0um x 35.0um" errors


Silicon Ensemble presently requires all power connections to the core ring to have a width of 70 microns. The CMC Skill script was used to slot wide traces, so the 70-micron power traces are not a problem. However, the Silicon Ensemble Power Route tool created via array instances to connect 70-micron wide traces, and these traces include 70-micron x 70-micron metal plates over and under the via instances which do not get slotted by the Skill routine. These metal plates are the cause of the error message and are likely included in most designs. In fact these are the only type of DRC violation that are present in the sample design.

Figure 13.1: Via Array Instance Before Edits (error marker not shown)

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MODULE 13: FIXING MINOR DRC PROBLEMS

The following instructions document how to correct these violations when the via connects metal1 to metal2, and there is no bend in the trace at the point of the via. These instructions may not work for all cases, but can be used as general guidence for fixing similar types of violations. Extreme caution is required when editing the layout, especially power traces, since fatal mistakes made here can potentially go undetected. 13.3.1 After using Find Markers to identify the offending via instance, press <Control> F, then use the left mouse button to select the via array instance. Tip: When you have zoomed in within a chipand are selecting items, it is a good idea to refer to the Select: count at the top of the editing window to ensure the number of selected items corresponds with what you think. After selecting the via instance, only one item should be selected. To verify you have selected the via, select: Edit -> Properties and the form should report: Library: cmosp35 Cell: RuleVia View: Symbolic Close the Edit Properties form Flatten the instance using: Edit -> Hierarchy -> Flatten... In the Flatten form, select: Flatten Mode: displayed levels Flatten Pcells Click OK After flattening the instance, individual vias should now be visible (see Figure 3.2).

13.3.2 13.3.3

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MODULE 13: FIXING MINOR DRC PROBLEMS

Figure 13.2: Flattened Via Array (result of step 13.3.3) Remove vias over the area to be slotted 13.3.4 You should be able to see existing slots in the metal traces under the via array. These slots likely end 20 microns from the centre of the via array, leaving a 40-micron un-slotted area in the center of the array (actually there is also unslotted metal under the entire via array). Determine how far the existing slots need to be extended to leave an unslotted area < 35 microns long. In the case of the sample design, it is seen that extending the current slots by the width of four rows of vias will make the distance from the center of the via array to the start of the slot less than 17 microns, so the total unslotted region will be less than 34 microns long.

13.3.5

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MODULE 13: FIXING MINOR DRC PROBLEMS

13.3.6

To select and delete the vias under the current slot plus four more rows of vias, in the Layer Select Window (LSW): Click on NS (none selectable) Right-click on via12 dg to make only the metal1 to metal2 via layer selectable. In the Editing window draw a box around all vias partially or fully under the existing slot, and four more rows of vias (as in Figure 13.3). Once youve selected the vias (select: 76) delete them with: Edit -> Delete The result of the delete is shown in Figure 13.4.

13.3.7

13.3.8

Repeat for the other half of the via array.

Select the layers of metal to be chopped 13.3.9 In the LSW: Right-click on metal1 dg and metal2 dg to make those layers selectable.

13.3.10 Pointing the mouse in one of the areas you have just cleared of vias, but not inside the existing slot (since only two of the three metal layers you want to chop are present in the existing slot), left-click once (see the marker in Figure 13.4 showing where you should point). The Select count should indicate 1. Holding <Shift> left-click a couple more times. The Select count should go to 3. Further left-clicks while holding shift should not increase the count since youve already selected all three metal layers present. The metal layers you have selected are the original (already slotted) trace, and the two metal plates associated with the via array.

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MODULE 13: FIXING MINOR DRC PROBLEMS

Figure 13.3: Vias Selected for Deletion (step 13.3.7)

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MODULE 13: FIXING MINOR DRC PROBLEMS

POINT MOUSE HERE WHEN SELECTING METAL LAYERS IN STEP 13.3.9

Figure 13.4: Vias Deleted

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MODULE 13: FIXING MINOR DRC PROBLEMS

Chop a lengthened slot through the selected metal layers 13.3.11 Select: Edit -> Other -> Chop 13.3.12 Left-click once on the edge of the existing slot, outside of the via instance (see Figure 13.5 for an indicator) 13.3.13 Move the mouse to be in-line with the other edge of the existing slot, but drag it past the end of the existing slot bringing the new slot about as close to the remaining vias as shown in Figure 13.5 (note that if the new slot end is too close to the vias you will get a "metal to via spacing" DRC error). 13.3.14 Repeat the last three steps (chopping a new slot) for the other half of the via. The resulting edits should look similar to Figure 13.6. Remove the Pcell instance marker from the center of the via array. 13.3.15 Zoom in to the center of the via array. You will see a small diamond shape. Click on AS in the LSW window. Using the left mouse button, draw a box around the diamond marker being careful not to select any of the vias at the same time. One or more items should be listed as selected: in the header of the Virtuoso window. Select: Edit -> Delete 13.3.16 Once the DRC errors have been corrected, remove the markers from the layout with: Verify -> Markers -> Delete All OK the Delete All Markers form Design -> Save Optional: Repeat the DRC check.

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MODULE 13: FIXING MINOR DRC PROBLEMS

LEFT-CLICK HERE FIRST

EXISTING SLOT END 2ND POINT FOR CHOP FUNCTION

Figure 13.5: Area Selected to be Chopped (steps 13.3.11-13.3.13)

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MODULE 13: FIXING MINOR DRC PROBLEMS

Figure 13.6: Slots After Chopping (result of step 13.3.14)

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MODULE 14: ADDING A LOGO

MODULE 14: ADDING A LOGO


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 13: To add a logo that is a unique identifier of the design

Synthesis

14.1
14.1.1 14.1.2 14.1.3

Add a logo
Open the layout view In the CIW select: CMC Gateway->Place Logo In the Create Logo Instance Form: Change Logo String to the proper code for your design. For this tutorial, use the design name assigned when you registered before step 1.1.1. When you create your own design, follow the instructions on CMCs fabrication pages on the Web which give the details of naming conventions. Although you will use your assigned design name where appropriate in this tutorial, for demonstration purposes the design name TCDICABC will be used (the text in italicsICABCwill be different in the design name you have been assigned). The initial T means this design is used for the Tutorial Example, the following CD identifies the design as a CMOSP35 design. IC is the university code used by designers within CMC, and ABC would be the individual design code assigned at the start of the tutorial exercise. Although the full code is TCDICABC, only the last five letters will be used to form the logo on the die: ICABC

Scan Insertion

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

14.1.4 14.1.5 14.1.6

Make sure Logo Layer has been selected as top metal. For example, metal3 for CMOSP35 and metal6 for CMOSP18. Click OK on the Create Logo Instance Form. You will now be prompted to "Enter the Logo cell Lower Left origin..." In the layout view, point the mouse locator ABOVE the die (well out of your design area. and left-click. We are placing the logo out of the chip, and then moving it inside of the die. This is done to avoid shorting existing wires with the logo. Once your logo is placed outside of your design, you can see the size

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MODULE 14: ADDING A LOGO

and decide where to place it inside of your die area. 14.1.7 14.1.8 14.1.9 In the layout window click on the Move icon (about halfway down the left-hand side of the screen) In the Move window, change Snap Mode to anyAngle When the Move window comes up, you should be prompted to "Select the figure to be moved:" Holding down the left-hand mouse button, draw a box around the logo (but nothing else). All the letters in the logo (and nothing else) should now be highlighted in your layout. Now single click with the left mouse button near the center of your logo.

14.1.10 The logo should now "follow" your mouse movements. Move the logo within your die to an area where the logo does not interfere with any existing traces. Left-click again, and the logo will be moved. Cancel the Move window. You should now zoom-in on the logo to double check to ensure you have not shorted any traces.

14.2

Remove the PR Boundary

One final edit to your layout is needed. There is a prBoundry layer which will cause problems for the automated fill routine if it is not removed. 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 Pointing within your design, press "f" to fit the design to the screen. In the LSW, click on prBound by and select: NV and NS Right-click on prBound by in the LSW to make that layer selectable. Point the mouse in the Virtuoso Editing window and use <Control> R to redraw the screen. Point the mouse somewhere inside the core, but not at any one item. You should see a dotted line around the edge of your design. Left-click, and the edge of your design should turn white, and then the Select: count should indicate 1 (top row of the Virtuoso Editing window). You have just selected the design Place & route boundary. This needs to be deleted: Edit -> Delete.

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MODULE 14: ADDING A LOGO

Your design will look exactly the same after deleting this PR boundary, but the skill routine in the next section will now work! 14.2.6 Save your design: Design -> Save

14.3
14.3.1

Ensure edits have not introduced new errors


Re-run the Extract, LVS and DRC steps (steps 12.4 -> 13.2) using the "layout" view instead of "autoLayout". When you try and run the LVS you may get a note saying the run directory differs from the form contents. Change the Run Directory to LVS2 (or some other unused directory name) and continue as before. Any LVS errors that appear now are the result of your edits, and any DRC problems remaining were either missed, or created with your edits. You will need to repeat the edit, LVS & DRC process on this layout until you have no errors. Both LVS and DRS should be 100% "clean" at this point.

THIS IS A NATURAL BREAK POINT

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MODULE 15: INITIAL SUBMISSION TO CMCS DRC SERVICE

MODULE 15: INITIAL SUBMISSION TO CMCS DRC SERVICE


Objective 15 To submit your design layout to CMCs DRC service in order to check problems not flagged by previous Diva checks, and to identify nets with antenna rule violations

RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Synthesis

Scan Insertion

Gate-Level Simulation

Floorplanning

CMOSP18 Reminder: All design names should start with TCF (represents CMOSP18) not TCD (CMOSP35). The CMC Design Rule Check service should be your "final sign-off" DRC. The CMC DRC service differs from the Diva DRC check in three main ways: 1. The CMC service replaces abstract views of black-box cells with physical layouts. The CMC service flags antenna rule violations differently, and The CMC service can handle larger designs (such as designs which have had metal fill added).

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

2. 3.

Since you are going to eventually use the CMC DRC service for final DRC on your metal filled design, you should also run it on your pre-metal filled design, so you can determine whether any errors in the final design are a result of the fill routine. This preliminary CMC DRC check will also flag nets which need to be fixed because of antenna rule violations.

15.1 Create a copy of your design with the new name


15.1.1 Open the mult16chip layout view 15.1.2 Create a new design by selecting Design -> Save As... 15.1.3 Change the Save As form to read: Library Name: design Cell Name: TCDICABC (use the design name CMC assigned to you) View Name: layout

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MODULE 15: INITIAL SUBMISSION TO CMCS DRC SERVICE

Click OK 15.1.4 Close all Cadence windows except the CIW and Library Manager.

15.2 Convert your design into a GDSII (stream) format


15.2.1 From the CIW select: File -> Export -> Stream... 15.2.2 In the Stream Out form specify: Template File: strm_out.template Library Name: design Top Cell Name: TCDICABC (use your own design ID) Output File: TCDICABC_prefill User-Defined Data And Options: User-Defined Data In the Stream Out User-Defined Data window enter: Layer Map Table: /CMC/kits/cmosp35/cmosp35.strmMapTable Click OK the User-Defined Data form Click Template File: Save Click OK the Stream Out form

CMOSP18 15.2.2 Change Layer Map Table: /CMC/kits/cmosp18/cmosp18.strmMapTable 15.2.3 View the PIPO.LOG file, you should have no errors (your PIPO.LOG values may not be exactly as shown). You may have multiple warning messages but these can be ignored. Here is the Summary from the sample run: Summary Of Objects -----------------------23944 32 18707 0 453 14161 0 89 Rectangles Polygons Paths Ellipses Labels Instances Arrays Cells

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MODULE 15: INITIAL SUBMISSION TO CMCS DRC SERVICE

00:00:10 Elapsed time 00:00:08 CPU time 49405 Kbytes of memory *** There were 0 error and 466 warning messages *** 15.2.4 You can now exit from Cadence, as it will take a few hours to get the DRC results back from CMC.

15.2.5 In the dfII directory, compress the _prefill version of your design with the Unix command: compress < TCDICABC_prefill > TCDICABC_prefill.Z rm TCDICABC_prefill Note that the final "Z" in the first command above is an upper-case "Z". This is a requirement of the DRC service. As an alternative, the following may work, depending on your Unix version, and is easier to type: compress < TCDICABC_prefill If you get an error about "name too long to add .Z extension" you will need to use the compress and rm commands as documented. Again be sure to use your assigned name instead of ICABC. All users of the CMC DRC service are encouraged to read the FAQ for that service.

15.3 Submit the design to CMC for DRC checking


NOTE: The automated DRC procedure may have changedcheck the Fabrication Web pages for full details! (http://www.cmc.ca/Fabrication/) 15.3.1 To send your design to CMC, at the Unix prompt: ftp keeper.cmc.ca Log in with your CMC username and password. ftp> bin ftp> cd fab ftp> put TCDICABC_prefill.Z ftp> quit 15.3.2 Now send an e-mail message to fab@cmc.ca with a subject of: TCDICABC_prefill.Z and

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MODULE 15: INITIAL SUBMISSION TO CMCS DRC SERVICE

include your name and e-mail address in the body. The automated fabrication service will automatically detect and process this DRC request.

It may take a full business day to complete your DRC run.

If you are working on a real design, you should submit a layout to the automated DRC service as early in the design cycle as possible, even if all aspects of your design are not yet complete. The sooner you know about any potential problems, the better chance you will have of fixing them.

This is a good time to document any problems, ideas, or suggestions you have about this training material so far. What steps have you had the most problems with? What changes would make it easier for you or others to attempt this exercise for the first time? Any other ideas or comments? Any comments you have now (or at any time) can be sent to support@cmc.ca

15.3.3 After some time (30 minutes), you should be able to check the progress of the DRC job at the Web page: http://www.cmc.ca/Fabrication/DRC/cd/TCDICABC CMOSP18 DRC reports for CMOSP18 designs are accessible from the page: http://www.cmc.ca/Fabrication/DRC/cf/ Check the "received on" time to ensure the results being viewed are for the design you just submitted. It will take a while (one hour if no other users have DRC jobs queued) for all checks to complete.

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MODULE 15: INITIAL SUBMISSION TO CMCS DRC SERVICE

You should check and understand all of the results. If you have any questions, send an email to fab@cmc.ca. It is important to ensure your black-box cells were "swapped" so make sure you check the "Blackbox cell log" to find out .

THIS IS A NATURAL BREAK POINT

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MODULE 16: FIXING ANTENNA RULE VIOLATIONS

MODULE 16: FIXING ANTENNA RULE VIOLATIONS


RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Objective 16: To import and view the results of CMCs DRC service, and fix antenna problems on identified nets

Synthesis

Scan Insertion

16.1
16.1.1

Save antenna rule error messages


For the sample design used in this tutorial, clicking on the CMC Web page link for Standard DRC rule results shows nothing listed under the CELL-NAME heading. This implies there were no basic DRC problems. Clicking on metal1/via12 Antenna DRC results and metal2/via23 Antenna DRC results shows there were 9 error messages in each category. NOTE: The name listed under CELL-NAME, as this will be the Top Cell Name used in dfII. These antenna rule violations must be fixed before proceeding.

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

16.1.2

Follow the instructions on the DRC page, or as listed below to save and view the antenna rule problems. If you have other DRC problems flagged by the service, they must be understood and corrected before continuing!! Within Netscape (or another Web browser), point at: download Antenna DRC error layer #1 (gds2) and hold down the right mouse button. Select: Save Link As... Note the default file name, and click OK Repeat for the download Antenna DRC error layer #2 (gds2) link.

16.2
16.2.1

Fix the nets associated with the flagged Antenna rule violations
Start Cadence from within the digflow/dfII directory: cd digflow/dfII startCds -t cmosp35 Import the prefill DRC results(from the CIW): File -> Import -> Stream...

16.2.2

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MODULE 16: FIXING ANTENNA RULE VIOLATIONS

16.2.3

In the Stream In form select: User-Defined Data And Options: User-Defined Data In the Stream In User-Defined Data form enter: Layer Map Table: /CMC/kits/cmosp35/cmosp35.strmMapTable Click OK Back in the Stream In form, continue with: Template File: strm_in.template Input File: <name of first file saved from Netscape> Top Cell Name: <name noted in Netscape, for example AR263> Library Name: ICABC_prefill_DRC ASCII Technology File Name: /CMC/kits/cmosp35/cmosp35.tf Click Template File: Save Click Apply

16.2.4

16.2.5

16.2.6

Check the PIPO.LOG file, but the design should have streamed in to the new ICABC_prefill_DRC library. Repeat steps 16.2.4 to 16.2.6, using the second saved Input File and the corresponding Top Cell Name:. The Library Name, and all other entries can be kept the same. Check the log file again, and if OK, cancel the Stream In form. If you had "regular" DRC errors (other than antenna problems), you should import that file last using a Top Cell Name with the form TOPTCDICABC.

16.2.7

16.3
16.3.1

View the DRC results on your design


Open the layout of the design submitted to the DRC service (design TCDICABC layout) in Cadence as follows. Within the Virtuoso Editing window for the TCDICABC layout select: Create -> Instance... After opening the TCDICABC layout it may be necessary to select Tools -> Layout.

16.3.2

In the Create Instance form, click on Browse In the browser, select the Library ICABC_prefill_DRC and one of the cells you imported in steps 16.2.4 to 16.2.7. The View should default to layout. If you move the mouse over your open layout a yellow box should also be displayed over your design. In order to have the DRC markers properly positioned, you need to position

16.3.3

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MODULE 16: FIXING ANTENNA RULE VIOLATIONS

your mouse marker at exactly X: 0.0 Y:0.0 (as seen at the top of the layout window). To do this, use the right mouse button to zoom in on the origin of the layout. You may have to zoom in a couple of times. 16.3.4 Once youve zoomed in on the origin (and the coordinates are exactly 0.0, 0.0), left-click once to place the new DRC marker object. You may not see anything initially, but dont click a second time! Press Esc to cancel the Create Instance operation. Press f to show the whole layout. You may now see a new instance outline placed on your design. Place the other DRC result instance(s) following the same procedure. Your second (and later) DRC instances may overlap the first, or may be difficult to locate in the layout once placed.

16.4
16.4.1 16.4.2

Locate the DRC problem nets


In the Virtuoso window, press <Shift> F to reveal the DRC markers. Select: Verify -> Markers -> Find... In the Find Marker form select: Zoom To Markers Search Scope: Cellview Click Apply If no markers are found, change: Access Mode to read Search Scope to hierarchy Apply Cancel any save design forms.

16.4.3

16.4.4

What are antenna effect violations and how are they fixed? Antenna problems result from large (or long) nets being connected to a transistor gate. During the fabrication process, the long net acts as a receiver antenna and can cause the gate to be damaged. Antenna problems are controlled by placing a diode between the offending net and the substrate. This allows discharge to the substrate during the fabrication steps related to adding metal layers.

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MODULE 16: FIXING ANTENNA RULE VIOLATIONS

The marker identified by the Find Markers function is likely within an I/O cell, or standard cell. The offending net may not be marked, but can be identified as the large net feeding into the cell containing the marker flag. You will likely need to zoom-out a few times to see which net feeds into the cell containing the marker. Once you have identified the offending net, a diode is placed on that net from the CMOSP35 library using the following procedure (Figure 16.1 shows the results of the next set of steps):

NEW DIODE PLACED NEW DIODE PLACED ON OFFENDING NET, AWAY ON OFFENDING NET, FROM OTHER NETS OR OBSTRUCTIONS AWAY FROM OTHER

ANTENNA RULE VIOLATION MARKER

Figure 16.1: Diode Placement

16.4.5

Create -> Instance... Use Browse, or fill out the form to show: Library: cmosp35 Cell: m1ant_diode Cell View: layout
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MODULE 16: FIXING ANTENNA RULE VIOLATIONS

Note that this example assumes the net is metal1, but if the net is another metal one of the other two diodes would be used (for example, use m3m2m1ant_diode to fix metal3 nets). 16.4.6 You may want to zoom in on the net, and turn "gravity" off so the cursor moves more freely within the design. To turn off gravity press: <Shift> E Click off "gravity" in the Editor form, and click OK The diode instance should be following the mouse in the Virtuoso window, and you can place the diode under the offending net. The new diode should not be placed too close to existing cells, nets, or bends in the net or DRC violations may occur. 16.4.7 You can select Next in the Find Markers form to identify and fix the next offending net. Note that as long as you are adding diodes to the same metal layer you should not need to reopen the Create Instance form (it should already be active). If you place a diode in a bad location, you can select it by drawing a box around it using the left mouse button, and remove it by selecting: Edit -> Delete Also note that although you have added two sets of antenna rule violation markers from the DRC service, some or all of the errors flagged in the two forms may be the same. In the case of the sample design, all markers flagged by the second antenna rule were the same as those flagged by the first. Also, all antenna rule violations were with nets connecting I/O output cells. 16.4.8 16.4.9 Once you have placed a diode on all of the offending nets, cancel the Find Markers form. You should select the marker instances added to your design, and delete them. Pressing <Control> F will make instance outlines visible.

The next step will add metal fill which will make local DRC checks impractical. If you have made a lot of edits to your design or are unsure of your edits, you can repeat the DRC check on this layout before proceeding. If you proceed without a DRC check, you should be very confident that no errors

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MODULE 16: FIXING ANTENNA RULE VIOLATIONS

exist. If you proceed without detecting an existing error, you will have to re-do the edit and metal fill steps, and repeat final DRC before proceeding.

THIS IS A NATURAL BREAK POINT

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MODULE 17: PREPARING YOUR DESIGN FOR FABRICATION

MODULE 17: PREPARING YOUR DESIGN FOR FABRICATION


Objective 17: To add metal and poly fill to meet fabrication requirements, and complete final LVS and DRC verification Technology suppliers have minimum metal and poly density limits for designs. You will need to add fill to your design to meet those requirements. The required fill minimums and your current fill percentages are available from your CMC DRC results page. Adding metal fill to your layout makes it very difficult to view or make any additional edits to your design. Because of this, for your own design you may want to save your layout again (under another name) before adding fill. Since this tutorial example design is not being fabricated and to avoid unneccessary disk usage, you do not need to make the extra save. You should be aware that, even without the extra save, the steps in this module will require approximately 500 megabytes of disk space. If your final DRC still has problems not related to the fill, you will find it much easier to fix those problems on the pre-filled version of the layout, and then run the fill routine again than to try and fix the filled version of your design.

RTL Simulation

Verilog Design Analyzer Design Analyzer Verilog Design Planner DP/Qplace DP/CTGen Silicon Ensemble DFII

Synthesis

Scan Insertion

Gate-Level Simulation

Floorplanning

Placement

Clock Tree Generation

Routing & Timing Verification

Physical Verification

17.1 Add fill


This step adds a fill pattern to unused areas of your design. Once the fill pattern has been added to your design, the database will be very large, and further edits/ DRCs will not be practical. The fill is added to the final version of your design. 17.1.1 Your TCDICABC layout should still be open. Select: Create -> Instance... 17.1.2 In the Create Instance form enter: Library: cmosp35 Cell: dummyFill View: layout Mosaic: Rows: 400 Columns: 1150 17.1.3 Move the mouse over your design, and you should see a large box. If you have used the default I/O placement for your chip, this box should fit just
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MODULE 17: PREPARING YOUR DESIGN FOR FABRICATION

inside the I/O ring of your design.

Visually center the box in your design, and left-click once. Cancel the Create Instance form. If you are creating the dummyFill array on your own design, you will have to experiment with Rows and Columns values until you find one that is close. Or you can calculate the required size based on the area you wish to cover and the 4 by 7 micron size of the basic fill cell. You can see the dummyFill grid by pressing <Shift> F and zooming in on a section of your design. 17.1.4 To have Cadence generate a metal fill pattern over your design using the dummyFill instance as a mask, click on: Verify -> DRC... 17.1.5 In the DRC form select: Rules File: divaFill.rul Press Tab Set Switches: Select all switches (do_fill_metal1 do_fill_metal2 do_fill_metal3 do_fill_poly1) NOTE: If the listed switches are not available, you may need to cancel the DRC form and try again. You MUST have the listed switches selected. OK the Set Switches and DRC forms. Diva will now fill the region you selected by placing the dummyFill instance with a valid fill pattern, then cut-back the fill pattern whereever it interferes with existing metal (poly) of that same layer. 17.1.6 Once the metal fill routine is done, save your design: Design -> Save

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MODULE 17: PREPARING YOUR DESIGN FOR FABRICATION

17.2 Perform final LVS


17.2.1 Next LVS will be used to compare this final layout with the golden netlist to ensure no nets were shorted, or other problems introduced. In the Virtuoso filled design layout window select: Verify -> Extract... Change Extract Method to: macro cell OK the Extractor

This will take 5-10 minutes to complete

17.2.2 When complete, close the TCDICABC layout window, and open the extracted version of the TCDICABC design and the schematic version of mult16chip. 17.2.3 Run LVS against the two extracted versions by selecting: Verify -> LVS... You may get a message saying the "LVS Run directory does not match the Run Form". This is because you have already done one LVS. 17.2.4 Click: Use: Form Contents OK the LVS Form Contents Different window. 17.2.5 In the LVS window change: Run Directory: LVS2 17.2.6 Ensure Schematic is filled out as: Library: design Cell: mult16chip View: schematic And extracted is: Library: design Cell: TCDICABC (or your design name) View: extracted

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MODULE 17: PREPARING YOUR DESIGN FOR FABRICATION

17.2.7 As with the previous LVS, click on RUN, and then Info -> Run Info: Log File. If this LVS does not have the exact same result as your original LVS, either your edits or the fill routine has corrupted the design. You must identify and correct any problems!!

17.3 Perform final DRC


17.3.1 Repeat the stream out and CMC DRC service checks (steps 15.2 and 15.3), this time using a stream file name of TCDICABC_filled. You should be able to load the strm_out.template file you saved earlier to simplify filling in the form. When viewing the Web-based DRC results, be extra careful to ensure you are looking at results for your current submission and not for the original submission. It is a good practice to click Reload in your Web browser and check the time-stamp on every page. 17.3.2 Once you have run the DRC service, you should have absolutely no DRC or antenna problems!! If you do have problems, you must import the new DRC markers as ICABC_filled_DRC, identify the cause and fix them. If the problems are not a result of the fill routine, it is likely easier to fix the problems in a copy of the design you saved before the fill routine was run. Your final DRC and LVS clean layout would be saved as ICDICABC which is the implementation version. This version should never be edited, and is your copy of the design submitted. It is a good idea to .tar up your working directory at this point, and archive it for reference once your chip has been fabricated. Consult the CMC Web pages for more information on actually having a design fabricated through CMC.

CONGRATULATIONS! YOU HAVE NOW COMPLETED THE TUTORIAL

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