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VHDL Implementation and Test Homework Problem Set

Homework Problem Set: VHDL Implementation and Test
Solve the problems listed in this document and submit the VHDL files to the ITEE Submission System (http://submit.itee.uq.edu.au/). The submission closes at 4pm on Thursday of Week 11.

Question 1 (2 Marks, submit ‘comb_lock.vhd’)
This question requires you to implement a 4 Bit Combination Lock using Combination Logic only (aka no Flip-Flops or Latches). The design has 4 inputs, each being a single Binary Coded Decimal. The design also includes 2 outputs the locked output which is high when the system is locked, and the unlocked output which is high when the system is unlocked. The system is unlocked when the 4 digits match the predefined combination, otherwise the system is locked. The predefined combinational value is the last 4 digits of your student number. For example if your student number is s4123456 your code would be 3456; where 6 is the least significant digit or digit_0. VHDL Entity:
entity comb_lock is port ( digit_0 digit_1 digit_2 digit_3

: : : :

in in in in

std_logic_vector(3 std_logic_vector(3 std_logic_vector(3 std_logic_vector(3

downto downto downto downto

0); 0); 0); 0);

locked : out std_logic; unlocked : out std_logic ); end comb_lock;

Block Diagram

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VHDL Implementation and Test Homework Problem Set

Question 2 (3 Marks, submit ‘comb_lock_test.vhd’)
Using the module you created in Question 1 create a simulation test bench, this test bench should thoroughly test the module. Your test bench will be used to test a number of different implementations of the module described in Question 1; these modules will implement both correct and incorrect versions of the design in Question 1. Name the test bench “comb_lock_test”.

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VHDL Implementation and Test Homework Problem Set

Question 3 (5 Marks, submit ‘sync_lock.vhd’)
This question requires you to implement a 4 Bit Combination Lock using The design has a synchronous reset and a single 4 bit Binary Coded Decimal digit input. The design includes 2 outputs for the locked and unlocked state of the system, and 4 outputs for the current value of the digits in Binary Coded Decimal form. The system is unlocked when the 4 digits which have been synchronously input over 4 clock cycles match the predefined combination, otherwise the system is locked. The output for locked and unlocked should be synchronous and change once the fourth input is entered (every 4 clock cycles). See the timing diagram for more details. The predefined combinational value is the last 4 digits of your student number. For example if your student number is s4123456 your code would be 3456; where 6 is the least significant digit or the first digit input. VHDL Entity:
entity sync_lock is port ( clk : in std_logic; rst : in std_logic; en : in std_logic; input : in std_logic_vector(3 downto 0); digit_0 : out std_logic_vector(3 digit_1 : out std_logic_vector(3 digit_2 : out std_logic_vector(3 digit_3 : out std_logic_vector(3 locked : out std_logic; unlocked : out std_logic ); end sync_lock; downto downto downto downto 0); 0); 0); 0);

Block Diagram

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VHDL Implementation and Test Homework Problem Set

Timing Diagram

Question 4 (5 Marks, submit ‘sync_lock_test.vhd’)
Using the module you created in Question 3 create a simulation test bench, this test bench should thoroughly test the module. Your test bench will be used to test a number of different implementations of the module described in Question 3; these modules will implement both correct and incorrect versions of the design in Question 3. Name the test bench “sync_lock_test”.

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